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authorPeter Sewell <Peter.Sewell@cl.cam.ac.uk>2019-09-12 07:13:53 +0100
committerPeter Sewell <Peter.Sewell@cl.cam.ac.uk>2019-09-12 07:13:53 +0100
commit4817059f90df4ea862879b8639f5e5fa58472ed4 (patch)
treee5372987f8faf242b77d5ab44e52b22903c38a32
parentfb76c0c38a4fcae438141160a16933ba2f05beb6 (diff)
parente1f0f43514d281f2690e9c3c632d627c76558b6e (diff)
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update funding ack
-rw-r--r--Makefile74
-rw-r--r--README.md28
-rw-r--r--c_emulator/riscv_platform.c3
-rw-r--r--c_emulator/riscv_platform.h1
-rw-r--r--c_emulator/riscv_platform_impl.c1
-rw-r--r--c_emulator/riscv_platform_impl.h1
-rw-r--r--c_emulator/riscv_prelude.c20
-rw-r--r--c_emulator/riscv_prelude.h5
-rw-r--r--c_emulator/riscv_sail.h1
-rw-r--r--c_emulator/riscv_sim.c97
-rw-r--r--descr2
-rw-r--r--doc/ExtendingGuide.md29
-rw-r--r--doc/README.md2
-rw-r--r--doc/ReadingGuide.md53
-rw-r--r--doc/Status.md58
-rw-r--r--doc/figs/Makefile11
-rw-r--r--doc/figs/riscvcsimdeps.svg93
-rw-r--r--doc/figs/riscvcsimdeps.tex62
-rw-r--r--doc/figs/riscvspecdeps.svg250
-rw-r--r--doc/figs/riscvspecdeps.tex96
-rw-r--r--handwritten_support/0.11/riscv_extras.lem (renamed from handwritten_support/0.7.1/riscv_extras.lem)85
-rw-r--r--handwritten_support/0.11/riscv_extras_sequential.lem (renamed from handwritten_support/0.7.1/riscv_extras_sequential.lem)39
-rw-r--r--handwritten_support/riscv_extras.lem4
-rw-r--r--handwritten_support/riscv_extras.v22
-rw-r--r--handwritten_support/riscv_extras_sequential.lem4
-rw-r--r--model/main.sail4
-rw-r--r--model/prelude.sail68
-rw-r--r--model/prelude_mapping.sail6
-rw-r--r--model/prelude_mem.sail58
-rw-r--r--model/riscv_addr_checks.sail2
-rw-r--r--model/riscv_analysis.sail253
-rw-r--r--model/riscv_csr_ext.sail27
-rw-r--r--model/riscv_csr_map.sail277
-rw-r--r--model/riscv_duopod.sail32
-rw-r--r--model/riscv_ext_regs.sail8
-rw-r--r--model/riscv_fetch.sail24
-rw-r--r--model/riscv_fetch_rvfi.sail50
-rw-r--r--model/riscv_insts_aext.sail41
-rw-r--r--model/riscv_insts_base.sail124
-rw-r--r--model/riscv_insts_begin.sail2
-rw-r--r--model/riscv_insts_cext.sail4
-rw-r--r--model/riscv_insts_end.sail4
-rw-r--r--model/riscv_insts_zicsr.sail59
-rw-r--r--model/riscv_jalr_seq.sail7
-rw-r--r--model/riscv_mem.sail161
-rw-r--r--model/riscv_next_control.sail78
-rw-r--r--model/riscv_next_regs.sail8
-rw-r--r--model/riscv_pc_access.sail10
-rw-r--r--model/riscv_platform.sail111
-rw-r--r--model/riscv_pmp_control.sail185
-rw-r--r--model/riscv_pmp_regs.sail143
-rw-r--r--model/riscv_pte.sail67
-rw-r--r--model/riscv_ptw.sail42
-rw-r--r--model/riscv_regs.sail17
-rw-r--r--model/riscv_step.sail19
-rw-r--r--model/riscv_step_rvfi.sail3
-rw-r--r--model/riscv_sys_control.sail161
-rw-r--r--model/riscv_sys_exceptions.sail12
-rw-r--r--model/riscv_sys_regs.sail86
-rw-r--r--model/riscv_termination_duo.sail1
-rw-r--r--model/riscv_termination_rv64.sail4
-rw-r--r--model/riscv_types.sail178
-rw-r--r--model/riscv_types_ext.sail22
-rw-r--r--model/riscv_vmem_common.sail104
-rw-r--r--model/riscv_vmem_rv32.sail29
-rw-r--r--model/riscv_vmem_rv64.sail35
-rw-r--r--model/riscv_vmem_sv32.sail141
-rw-r--r--model/riscv_vmem_sv39.sail141
-rw-r--r--model/riscv_vmem_sv48.sail94
-rw-r--r--model/riscv_vmem_types.sail18
-rw-r--r--ocaml_emulator/platform.ml7
-rw-r--r--ocaml_emulator/riscv_ocaml_sim.ml3
-rw-r--r--opam9
-rw-r--r--os-boot/README.md49
-rw-r--r--os-boot/image-notes.txt39
-rw-r--r--os-boot/os-boot-patch.diff71
-rw-r--r--os-boot/rv64-2gb-hafnium.dts53
-rwxr-xr-xos-boot/rv64-hafnium-054a7a-linux-4.20.0-gcc-8.3.0-2gb.bblbin0 -> 28282728 bytes
-rwxr-xr-xos-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bblbin0 -> 10048160 bytes
-rw-r--r--prover_snapshots/README.md6
-rw-r--r--prover_snapshots/coq/.gitignore5
-rw-r--r--prover_snapshots/coq/README.md7
-rw-r--r--prover_snapshots/coq/RV32/riscv.v42479
-rw-r--r--prover_snapshots/coq/RV32/riscv_extras.v155
-rw-r--r--prover_snapshots/coq/RV32/riscv_types.v14073
-rw-r--r--prover_snapshots/coq/RV64/riscv.v43007
-rw-r--r--prover_snapshots/coq/RV64/riscv_extras.v155
-rw-r--r--prover_snapshots/coq/RV64/riscv_types.v14318
-rwxr-xr-xprover_snapshots/coq/build27
-rwxr-xr-xprover_snapshots/coq/clean13
-rw-r--r--prover_snapshots/coq/duopod/riscv_duopod.v1792
-rw-r--r--prover_snapshots/coq/duopod/riscv_duopod_types.v186
-rw-r--r--prover_snapshots/coq/duopod/riscv_extras.v155
-rw-r--r--prover_snapshots/coq/lib/sail/Hoare.v810
-rw-r--r--prover_snapshots/coq/lib/sail/Makefile26
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_impl_base.v1103
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_instr_kinds.v332
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_operators.v232
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_operators_bitlists.v182
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_operators_mwords.v544
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_prompt.v229
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_prompt_monad.v367
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_real.v36
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_state.v167
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_state_lemmas.v819
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_state_lifting.v61
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_state_monad.v323
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_state_monad_lemmas.v542
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_string.v194
-rw-r--r--prover_snapshots/coq/lib/sail/Sail2_values.v2490
-rw-r--r--prover_snapshots/coq/lib/sail/_CoqProject2
-rw-r--r--prover_snapshots/hol4/.gitignore9
-rw-r--r--prover_snapshots/hol4/README.md11
-rw-r--r--prover_snapshots/hol4/RV32/Holmakefile13
-rw-r--r--prover_snapshots/hol4/RV32/riscvAuxiliaryScript.sml50
-rw-r--r--prover_snapshots/hol4/RV32/riscvScript.sml34910
-rw-r--r--prover_snapshots/hol4/RV32/riscv_extrasScript.sml276
-rw-r--r--prover_snapshots/hol4/RV32/riscv_typesScript.sml2208
-rw-r--r--prover_snapshots/hol4/RV64/Holmakefile13
-rw-r--r--prover_snapshots/hol4/RV64/riscvAuxiliaryScript.sml59
-rw-r--r--prover_snapshots/hol4/RV64/riscvScript.sml35352
-rw-r--r--prover_snapshots/hol4/RV64/riscv_extrasScript.sml276
-rw-r--r--prover_snapshots/hol4/RV64/riscv_typesScript.sml2236
-rwxr-xr-xprover_snapshots/hol4/build5
-rwxr-xr-xprover_snapshots/hol4/clean5
-rw-r--r--prover_snapshots/hol4/lib/lem/Holmakefile14
-rw-r--r--prover_snapshots/hol4/lib/lem/lemLib.sml105
-rw-r--r--prover_snapshots/hol4/lib/lem/lemScript.sml284
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_assert_extraScript.sml46
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_basic_classesScript.sml503
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_boolScript.sml75
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_eitherScript.sml83
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_functionScript.sml72
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_function_extraScript.sml25
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_listScript.sml776
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_list_extraScript.sml110
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_machine_wordScript.sml433
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_mapScript.sml153
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_map_extraScript.sml72
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_maybeScript.sml112
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_maybe_extraScript.sml23
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_numScript.sml1329
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_num_extraScript.sml73
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_pervasivesScript.sml18
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_pervasives_extraScript.sml16
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_relationScript.sml448
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_setScript.sml317
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_set_extraScript.sml118
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_set_helpersScript.sml47
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_showScript.sml85
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_show_extraScript.sml67
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_sortingScript.sml107
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_stringScript.sml74
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_string_extraScript.sml124
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_tupleScript.sml51
-rw-r--r--prover_snapshots/hol4/lib/lem/lem_wordScript.sml1021
-rw-r--r--prover_snapshots/hol4/lib/sail/Holmakefile29
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_instr_kindsScript.sml543
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_operatorsScript.sml327
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_operators_bitlistsScript.sml746
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_operators_mwordsScript.sml627
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_promptScript.sml15
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_prompt_monadScript.sml34
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_stateAuxiliaryScript.sml61
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_stateScript.sml156
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_state_monadScript.sml370
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_stringScript.sml555
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_valuesAuxiliaryScript.sml139
-rw-r--r--prover_snapshots/hol4/lib/sail/sail2_valuesScript.sml1318
-rw-r--r--prover_snapshots/isabelle/README.md25
-rw-r--r--prover_snapshots/isabelle/ROOTS3
-rw-r--r--prover_snapshots/isabelle/RV32/ROOT4
-rw-r--r--prover_snapshots/isabelle/RV32/Riscv.thy36556
-rw-r--r--prover_snapshots/isabelle/RV32/RiscvAuxiliary.thy35
-rw-r--r--prover_snapshots/isabelle/RV32/Riscv_extras.thy362
-rw-r--r--prover_snapshots/isabelle/RV32/Riscv_lemmas.thy983
-rw-r--r--prover_snapshots/isabelle/RV32/Riscv_types.thy2304
-rw-r--r--prover_snapshots/isabelle/RV64/ROOT4
-rw-r--r--prover_snapshots/isabelle/RV64/Riscv.thy37028
-rw-r--r--prover_snapshots/isabelle/RV64/RiscvAuxiliary.thy37
-rw-r--r--prover_snapshots/isabelle/RV64/Riscv_extras.thy362
-rw-r--r--prover_snapshots/isabelle/RV64/Riscv_lemmas.thy995
-rw-r--r--prover_snapshots/isabelle/RV64/Riscv_types.thy2335
-rw-r--r--prover_snapshots/isabelle/lib/ROOTS2
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem.thy108
-rw-r--r--prover_snapshots/isabelle/lib/lem/LemExtraDefs.thy1255
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_assert_extra.thy45
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_basic_classes.thy501
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_bool.thy75
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_either.thy85
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_function.thy72
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_function_extra.thy29
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_list.thy776
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_list_extra.thy117
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_machine_word.thy453
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_map.thy159
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_map_extra.thy82
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_maybe.thy113
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_maybe_extra.thy24
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_num.thy1313
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_num_extra.thy34
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_pervasives.thy31
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy26
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_relation.thy449
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_set.thy325
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_set_extra.thy121
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_set_helpers.thy50
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_show.thy87
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_show_extra.thy74
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_sorting.thy110
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_string.thy75
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_string_extra.thy137
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_tuple.thy51
-rw-r--r--prover_snapshots/isabelle/lib/lem/Lem_word.thy1024
-rw-r--r--prover_snapshots/isabelle/lib/lem/ROOT5
-rw-r--r--prover_snapshots/isabelle/lib/sail/Hoare.thy525
-rw-r--r--prover_snapshots/isabelle/lib/sail/ROOT11
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy576
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_operators.thy326
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy750
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy623
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy169
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_prompt.thy181
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy405
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy384
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_state.thy152
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy536
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_state_lifting.thy75
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_state_monad.thy377
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy243
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_string.thy555
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_values.thy1275
-rw-r--r--prover_snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy368
-rw-r--r--sail-riscv.install2
-rwxr-xr-xtest/get_perf.py4
235 files changed, 311246 insertions, 1285 deletions
diff --git a/Makefile b/Makefile
index f1acbf2..2c8981a 100644
--- a/Makefile
+++ b/Makefile
@@ -36,7 +36,7 @@ SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling
SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
SAIL_RV64_VM_SRCS = riscv_vmem_sv39.sail riscv_vmem_sv48.sail riscv_vmem_rv64.sail
-SAIL_VM_SRCS = riscv_vmem_common.sail riscv_vmem_tlb.sail
+SAIL_VM_SRCS = riscv_pte.sail riscv_ptw.sail riscv_vmem_common.sail riscv_vmem_tlb.sail
ifeq ($(ARCH),RV32)
SAIL_VM_SRCS += $(SAIL_RV32_VM_SRCS)
else
@@ -45,8 +45,14 @@ endif
# Non-instruction sources
PRELUDE = prelude.sail prelude_mapping.sail $(SAIL_XLEN) prelude_mem_metadata.sail prelude_mem.sail
-SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
-SAIL_ARCH_SRCS = $(PRELUDE) riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
+
+SAIL_REGS_SRCS = riscv_reg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail
+SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail
+SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
+
+SAIL_ARCH_SRCS = $(PRELUDE)
+SAIL_ARCH_SRCS += riscv_types_ext.sail riscv_types.sail
+SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail
@@ -73,11 +79,11 @@ PLATFORM_OCAML_SRCS = $(addprefix ocaml_emulator/,platform.ml platform_impl.ml r
# Attempt to work with either sail from opam or built from repo in SAIL_DIR
ifneq ($(SAIL_DIR),)
# Use sail repo in SAIL_DIR
-SAIL:=$(SAIL_DIR)/sail
+SAIL:=$(SAIL_DIR)/sail -dno_cast
export SAIL_DIR
else
# Use sail from opam package
-SAIL_DIR=$(shell opam config var sail:share)
+SAIL_DIR:=$(shell opam config var sail:share)
SAIL:=sail
endif
SAIL_LIB_DIR:=$(SAIL_DIR)/lib
@@ -92,10 +98,14 @@ BBV_DIR?=../bbv
C_WARNINGS ?=
#-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function
C_INCS = $(addprefix c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h)
-C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c)
+C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_sim.c)
+
+# portability for MacPorts/MacOS
+C_SYS_INCLUDES = -I /opt/local/include
+C_SYS_LIBDIRS = -L /opt/local/lib
-C_FLAGS = -I $(SAIL_LIB_DIR) -I c_emulator
-C_LIBS = -lgmp -lz
+C_FLAGS = $(C_SYS_INCLUDES) -I $(SAIL_LIB_DIR) -I c_emulator
+C_LIBS = $(C_SYS_LIBDIRS) -lgmp -lz
# The C simulator can be built to be linked against Spike for tandem-verification.
# This needs the C bindings to Spike from https://github.com/SRI-CSL/l3riscv
@@ -114,17 +124,17 @@ ifneq (,$(COVERAGE))
C_FLAGS += --coverage -O1
SAIL_FLAGS += -Oconstant_fold
else
-C_FLAGS += -O2
+C_FLAGS += -O3 -flto
endif
# Feature detect if we are on the latest development version of Sail
# and use an updated lem file if so. This is just until the opam
-# version catches up with changes to the monad embedding.
-SAIL_LATEST := $(shell $(SAIL) -emacs 1>&2 2> /dev/null; echo $$?)
+# version catches up with changes to the barrier type.
+SAIL_LATEST := $(shell $(SAIL) -have_feature FEATURE_UNION_BARRIER 1>&2 2> /dev/null; echo $$?)
ifeq ($(SAIL_LATEST),0)
-RISCV_EXTRAS_LEM = riscv_extras.lem
+RISCV_EXTRAS_LEM = 0.11/riscv_extras.lem
else
-RISCV_EXTRAS_LEM = 0.7.1/riscv_extras.lem
+RISCV_EXTRAS_LEM = riscv_extras.lem
endif
all: ocaml_emulator/riscv_ocaml_sim_$(ARCH) c_emulator/riscv_sim_$(ARCH) riscv_isa riscv_coq riscv_hol riscv_rmem
@@ -140,6 +150,9 @@ check: $(SAIL_SRCS) model/main.sail Makefile
interpret: $(SAIL_SRCS) model/main.sail
$(SAIL) -i $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail
+riscv.smt_model: $(SAIL_SRCS)
+ $(SAIL) -smt_serialize $(SAIL_FLAGS) $(SAIL_SRCS) -o riscv
+
cgen: $(SAIL_SRCS) model/main.sail
$(SAIL) -cgen $(SAIL_FLAGS) $(SAIL_SRCS) model/main.sail
@@ -168,6 +181,9 @@ ocaml_emulator/coverage_$(ARCH): ocaml_emulator/_sbuild/coverage.native
mkdir ocaml_emulator/bisect && mv bisect*.out bisect/
mkdir ocaml_emulator/coverage_$(ARCH) && bisect-ppx-report -html ocaml_emulator/coverage_$(ARCH)/ -I ocaml_emulator/_sbuild/ bisect/bisect*.out
+cloc:
+ cloc --by-file --force-lang C,sail $(SAIL_SRCS)
+
gcovr:
gcovr -r . --html --html-detail -o index.html
@@ -178,27 +194,20 @@ generated_definitions/ocaml/riscv_duopod_ocaml: $(PRELUDE_SRCS) model/riscv_duop
ocaml_emulator/tracecmp: ocaml_emulator/tracecmp.ml
ocamlfind ocamlopt -annot -linkpkg -package unix $^ -o $@
-generated_definitions/c/riscv.c: $(SAIL_SRCS) model/main.sail Makefile
- mkdir -p generated_definitions/c
- $(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h $(SAIL_SRCS) model/main.sail -o $(basename $@)
-
-c_emulator/riscv_c: generated_definitions/c/riscv.c $(C_INCS) $(C_SRCS) Makefile
- gcc $(C_WARNINGS) $(C_FLAGS) $< $(C_SRCS) $(SAIL_LIB_DIR)/*.c -lgmp -lz -I $(SAIL_LIB_DIR) -o $@
-
generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile
mkdir -p generated_definitions/c
- $(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@)
+ $(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@)
-c_emulator/riscv_sim_$(ARCH): generated_definitions/c/riscv_model_$(ARCH).c c_emulator/riscv_sim.c $(C_INCS) $(C_SRCS) Makefile
- gcc -g $(C_WARNINGS) $(C_FLAGS) $< c_emulator/riscv_sim.c $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
+c_emulator/riscv_sim_$(ARCH): generated_definitions/c/riscv_model_$(ARCH).c $(C_INCS) $(C_SRCS) Makefile
+ gcc -g $(C_WARNINGS) $(C_FLAGS) $< $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
generated_definitions/c/riscv_rvfi_model.c: $(SAIL_RVFI_SRCS) model/main.sail Makefile
mkdir -p generated_definitions/c
$(SAIL) $(SAIL_FLAGS) -O -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@)
sed -i -e '/^[[:space:]]*$$/d' $@
-c_emulator/riscv_rvfi: generated_definitions/c/riscv_rvfi_model.c c_emulator/riscv_sim.c $(C_INCS) $(C_SRCS) Makefile
- gcc -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII c_emulator/riscv_sim.c $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
+c_emulator/riscv_rvfi: generated_definitions/c/riscv_rvfi_model.c $(C_INCS) $(C_SRCS) Makefile
+ gcc -g $(C_WARNINGS) $(C_FLAGS) $< -DRVFI_DII $(C_SRCS) $(SAIL_LIB_DIR)/*.c $(C_LIBS) -o $@
latex: $(SAIL_SRCS) Makefile
mkdir -p generated_definitions/latex
@@ -273,7 +282,7 @@ riscv_hol: generated_definitions/hol4/$(ARCH)/riscvScript.sml
riscv_hol_build: generated_definitions/hol4/$(ARCH)/riscvTheory.uo
.PHONY: riscv_hol riscv_hol_build
-COQ_LIBS = -R $(BBV_DIR)/theories bbv -R $(SAIL_LIB_DIR)/coq Sail -R coq '' -R generated_definitions/coq/$(ARCH) '' -R handwritten_support ''
+COQ_LIBS = -R $(BBV_DIR)/theories bbv -R $(SAIL_LIB_DIR)/coq Sail -R generated_definitions/coq/$(ARCH) '' -R handwritten_support ''
riscv_coq: $(addprefix generated_definitions/coq/$(ARCH)/,riscv.v riscv_types.v)
riscv_coq_build: generated_definitions/coq/$(ARCH)/riscv.vo
@@ -282,7 +291,7 @@ riscv_coq_build: generated_definitions/coq/$(ARCH)/riscv.vo
$(addprefix generated_definitions/coq/$(ARCH)/,riscv.v riscv_types.v): $(SAIL_COQ_SRCS) Makefile
mkdir -p generated_definitions/coq/$(ARCH)
$(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -coq_output_dir generated_definitions/coq/$(ARCH) -o riscv -coq_lib riscv_extras $(SAIL_COQ_SRCS)
-$(addprefix generated_definitions/coq/$(ARCH)/,riscv_duopod.v riscv_duopod_types.v): $(PRELUDE_SRCS) model/riscv_duopod.sail
+$(addprefix generated_definitions/coq/$(ARCH)/,riscv_duopod.v riscv_duopod_types.v): $(PRELUDE_SRCS) model/riscv_duopod.sail model/riscv_termination_duo.sail
mkdir -p generated_definitions/coq/$(ARCH)
$(SAIL) $(SAIL_FLAGS) -dcoq_undef_axioms -coq -coq_output_dir generated_definitions/coq/$(ARCH) -o riscv_duopod -coq_lib riscv_extras $^
@@ -324,9 +333,16 @@ generated_definitions/for-rmem/riscv.defs: $(SAIL_RMEM_SRCS)
#LOC_FILES:=$(SAIL_SRCS) main.sail
#include $(SAIL_DIR)/etc/loc.mk
+FORCE:
+
+SHARE_FILES:=$(wildcard model/*.sail) $(wildcard c_emulator/*.c) $(wildcard c_emulator/*.h)
+sail-riscv.install: FORCE
+ echo 'bin: ["c_emulator/riscv_sim_RV64" "c_emulator/riscv_sim_RV32"]' > sail-riscv.install
+ echo 'share: [ $(foreach f,$(SHARE_FILES),"$f" {"$f"}) ]' >> sail-riscv.install
+
opam-build:
- make ARCH=64 c_emulator/riscv_sim_RV64
- make ARCH=32 c_emulator/riscv_sim_RV32
+ $(MAKE) ARCH=64 c_emulator/riscv_sim_RV64
+ $(MAKE) ARCH=32 c_emulator/riscv_sim_RV32
opam-install:
if [ -z "$(INSTALL_DIR)" ]; then echo INSTALL_DIR is unset; false; fi
diff --git a/README.md b/README.md
index b31a7cb..5315026 100644
--- a/README.md
+++ b/README.md
@@ -10,6 +10,10 @@ conventional OS with a terminal output device. The model specifies
assembly language formats of the instructions, the corresponding
encoders and decoders, and the instruction semantics.
+This is one of [several formal models](https://github.com/riscv/ISA_Formal_Spec_Public_Review/blob/master/comparison_table.md) compared within the
+[RISC-V ISA Formal Spec Public Review](https://github.com/riscv/ISA_Formal_Spec_Public_Review).
+
+
Directory Structure
-------------------
@@ -28,6 +32,8 @@ sail-riscv
| +---- hol4
| +---- latex
|
++---- prover_snapshots // Snapshots of generated theorem prover definitions
+|
|---- handwritten_support // Prover support files
|
+---- c_emulator // supporting platform files for C emulator
@@ -47,7 +53,9 @@ Documentation
A [reading guide](doc/ReadingGuide.md) to the model is provided in the
[doc/](doc/) subdirectory, along with a guide on [how to
-extend](doc/ExtendingGuide.md) the model.
+extend](doc/ExtendingGuide.md) the model. The current status of the
+coverage of the prose RISC-V specification is summarized
+[here](doc/Status.md).
Simulators
----------
@@ -65,8 +73,10 @@ Coq, Isabelle and HOL4.
Building the model
------------------
-Install Sail via Opam, or build Sail from source and have `SAIL_DIR` in
-your environment pointing to its top-level directory.
+Install Sail [via
+Opam](https://github.com/rems-project/sail/wiki/OPAMInstall), or build Sail
+from source and have `SAIL_DIR` in your environment pointing to its
+top-level directory.
```
$ make
@@ -103,7 +113,16 @@ corresponding prover libraries in the Sail directory
Executing test binaries
-----------------------
-The C and OCaml simulators can be used to execute small test binaries.
+The C and OCaml simulators can be used to execute small test binaries. The
+OCaml simulator depends on the Device Tree Compiler package, which can be
+installed in Ubuntu with:
+
+```
+$ sudo apt-get install device-tree-compiler
+```
+
+Then, you can run test binaries:
+
```
$ ./ocaml_emulator/riscv_ocaml_sim_<arch> <elf-file>
@@ -142,7 +161,6 @@ Cambridge Computer Laboratory (Department of Computer Science and
Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and
under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA
SSITH research programme.
-
This software was developed within the Rigorous
Engineering of Mainstream Systems (REMS) project, partly funded by
EPSRC grant EP/K008528/1, at the Universities of Cambridge and
diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
index dcc5766..c88f688 100644
--- a/c_emulator/riscv_platform.c
+++ b/c_emulator/riscv_platform.c
@@ -23,6 +23,9 @@ bool plat_enable_misaligned_access(unit u)
bool plat_mtval_has_illegal_inst_bits(unit u)
{ return rv_mtval_has_illegal_inst_bits; }
+bool plat_enable_pmp(unit u)
+{ return rv_enable_pmp; }
+
mach_bits plat_ram_base(unit u)
{ return rv_ram_base; }
diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
index 31f2807..85cf3fd 100644
--- a/c_emulator/riscv_platform.h
+++ b/c_emulator/riscv_platform.h
@@ -7,6 +7,7 @@ bool sys_enable_writable_misa(unit);
bool plat_enable_dirty_update(unit);
bool plat_enable_misaligned_access(unit);
bool plat_mtval_has_illegal_inst_bits(unit);
+bool plat_enable_pmp(unit);
mach_bits plat_ram_base(unit);
mach_bits plat_ram_size(unit);
diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
index 5894fc9..695384c 100644
--- a/c_emulator/riscv_platform_impl.c
+++ b/c_emulator/riscv_platform_impl.c
@@ -3,6 +3,7 @@
#include <stdio.h>
/* Settings of the platform implementation, with common defaults. */
+bool rv_enable_pmp = false;
bool rv_enable_rvc = true;
bool rv_enable_writable_misa = true;
diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
index cf3bc30..60b9181 100644
--- a/c_emulator/riscv_platform_impl.h
+++ b/c_emulator/riscv_platform_impl.h
@@ -7,6 +7,7 @@
#define DEFAULT_RSTVEC 0x00001000
+extern bool rv_enable_pmp;
extern bool rv_enable_rvc;
extern bool rv_enable_writable_misa;
extern bool rv_enable_dirty_update;
diff --git a/c_emulator/riscv_prelude.c b/c_emulator/riscv_prelude.c
index 1621913..92f8415 100644
--- a/c_emulator/riscv_prelude.c
+++ b/c_emulator/riscv_prelude.c
@@ -30,3 +30,23 @@ unit print_platform(sail_string s)
if (config_print_platform) printf("%s\n", s);
return UNIT;
}
+
+bool get_config_print_instr(unit u)
+{
+ return (config_print_instr) ? true : false;
+}
+
+bool get_config_print_reg(unit u)
+{
+ return (config_print_reg) ? true : false;
+}
+
+bool get_config_print_mem(unit u)
+{
+ return (config_print_mem_access) ? true : false;
+}
+
+bool get_config_print_platform(unit u)
+{
+ return (config_print_platform) ? true : false;
+}
diff --git a/c_emulator/riscv_prelude.h b/c_emulator/riscv_prelude.h
index a296c7e..da292fe 100644
--- a/c_emulator/riscv_prelude.h
+++ b/c_emulator/riscv_prelude.h
@@ -8,3 +8,8 @@ unit print_instr(sail_string s);
unit print_reg(sail_string s);
unit print_mem_access(sail_string s);
unit print_platform(sail_string s);
+
+bool get_config_print_instr(unit u);
+bool get_config_print_reg(unit u);
+bool get_config_print_mem(unit u);
+bool get_config_print_platform(unit u);
diff --git a/c_emulator/riscv_sail.h b/c_emulator/riscv_sail.h
index a02482e..f177c57 100644
--- a/c_emulator/riscv_sail.h
+++ b/c_emulator/riscv_sail.h
@@ -19,6 +19,7 @@ unit ztick_platform(unit);
unit z_set_Misa_C(struct zMisa*, mach_bits);
#ifdef RVFI_DII
+unit zext_rvfi_init(unit);
unit zrvfi_set_instr_packet(mach_bits);
mach_bits zrvfi_get_cmd(unit);
bool zrvfi_step(sail_int);
diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index c70b31c..6188e96 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -69,17 +69,38 @@ bool config_print_reg = true;
bool config_print_mem_access = true;
bool config_print_platform = true;
+void set_config_print(char *var, bool val) {
+ if (var == NULL || strcmp("all", var) == 0) {
+ config_print_instr = val;
+ config_print_mem_access = val;
+ config_print_reg = val;
+ config_print_platform = val;
+ } else if (strcmp("instr", var) == 0) {
+ config_print_instr = val;
+ } else if (strcmp("reg", var) == 0) {
+ config_print_reg = val;
+ } else if (strcmp("mem", var) == 0) {
+ config_print_mem_access = val;
+ } else if (strcmp("platform", var) == 0) {
+ config_print_platform = val;
+ } else {
+ fprintf(stderr, "Unknown trace category: '%s' (should be instr|reg|mem|platform|all)\n", var);
+ exit(1);
+ }
+}
+
struct timeval init_start, init_end, run_end;
int total_insns = 0;
+int insn_limit = 0;
static struct option options[] = {
{"enable-dirty-update", no_argument, 0, 'd'},
{"enable-misaligned", no_argument, 0, 'm'},
+ {"enable-pmp", no_argument, 0, 'P'},
{"ram-size", required_argument, 0, 'z'},
{"disable-compressed", no_argument, 0, 'C'},
{"disable-writable-misa", no_argument, 0, 'I'},
{"mtval-has-illegal-inst-bits", no_argument, 0, 'i'},
- {"dump-dts", no_argument, 0, 's'},
{"device-tree-blob", required_argument, 0, 'b'},
{"terminal-log", required_argument, 0, 't'},
{"show-times", required_argument, 0, 'p'},
@@ -89,6 +110,9 @@ static struct option options[] = {
{"rvfi-dii", required_argument, 0, 'r'},
#endif
{"help", no_argument, 0, 'h'},
+ {"trace", optional_argument, 0, 'v'},
+ {"no-trace", optional_argument, 0, 'V'},
+ {"inst-limit", required_argument, 0, 'l'},
{0, 0, 0, 0}
};
@@ -101,7 +125,7 @@ static void print_usage(const char *argv0, int ec)
#endif
struct option *opt = options;
while (opt->name) {
- fprintf(stdout, "\t -%c\t %s\n", (char)opt->val, opt->name);
+ fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name);
opt++;
}
exit(ec);
@@ -172,7 +196,7 @@ char *process_args(int argc, char **argv)
int c, idx = 1;
uint64_t ram_size = 0;
while(true) {
- c = getopt_long(argc, argv, "admCspz:b:t:v:hr:T:", options, &idx);
+ c = getopt_long(argc, argv, "admCIispz:b:t:hr:T:V::v::l:", options, &idx);
if (c == -1) break;
switch (c) {
case 'a':
@@ -186,19 +210,27 @@ char *process_args(int argc, char **argv)
fprintf(stderr, "enabling misaligned access.\n");
rv_enable_misaligned = true;
break;
+ case 'P':
+ fprintf(stderr, "enabling PMP support.\n");
+ rv_enable_pmp = true;
+ break;
case 'C':
+ fprintf(stderr, "disabling RVC compressed instructions.\n");
rv_enable_rvc = false;
break;
case 'I':
+ fprintf(stderr, "disabling writable misa CSR.\n");
rv_enable_writable_misa = false;
break;
case 'i':
+ fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
rv_mtval_has_illegal_inst_bits = true;
break;
case 's':
do_dump_dts = true;
break;
case 'p':
+ fprintf(stderr, "will show execution times on completion.\n");
do_show_times = true;
break;
case 'z':
@@ -206,16 +238,22 @@ char *process_args(int argc, char **argv)
if (ram_size) {
fprintf(stderr, "setting ram-size to %" PRIu64 " MB\n", ram_size);
rv_ram_size = ram_size << 20;
+ } else {
+ fprintf(stderr, "invalid ram-size '%s' provided.\n", optarg);
+ exit(1);
}
break;
case 'b':
dtb_file = strdup(optarg);
+ fprintf(stderr, "using %s as DTB file.\n", dtb_file);
break;
case 't':
term_log = strdup(optarg);
+ fprintf(stderr, "using %s for terminal output.\n", term_log);
break;
case 'T':
sig_file = strdup(optarg);
+ fprintf(stderr, "using %s for test-signature output.\n", sig_file);
break;
case 'h':
print_usage(argv[0], 0);
@@ -224,20 +262,32 @@ char *process_args(int argc, char **argv)
case 'r':
rvfi_dii = true;
rvfi_dii_port = atoi(optarg);
+ fprintf(stderr, "using %d as RVFI port.\n", rvfi_dii_port);
break;
#endif
- default:
- fprintf(stderr, "Unrecognized optchar %c\n", c);
+ case 'V':
+ set_config_print(optarg, false);
+ break;
+ case 'v':
+ set_config_print(optarg, true);
+ break;
+ case 'l':
+ insn_limit = atoi(optarg);
+ break;
+ case '?':
print_usage(argv[0], 1);
+ break;
}
}
if (do_dump_dts) dump_dts();
#ifdef RVFI_DII
if (idx > argc || (idx == argc && !rvfi_dii)) print_usage(argv[0], 0);
#else
- if (optind >= argc) print_usage(argv[0], 0);
+ if (optind >= argc) {
+ fprintf(stderr, "No elf file provided.\n");
+ print_usage(argv[0], 0);
+ }
#endif
- if (term_log == NULL) term_log = strdup("term.log");
if (dtb_file) read_dtb(dtb_file);
#ifdef RVFI_DII
@@ -419,10 +469,14 @@ void init_sail(uint64_t elf_entry)
zinit_model(UNIT);
#ifdef RVFI_DII
if (rvfi_dii) {
+ zext_rvfi_init(UNIT);
rv_ram_base = UINT64_C(0x80000000);
rv_ram_size = UINT64_C(0x10000);
rv_rom_base = UINT64_C(0);
rv_rom_size = UINT64_C(0);
+ rv_clint_base = UINT64_C(0);
+ rv_clint_size = UINT64_C(0);
+ rv_htif_tohost = UINT64_C(0);
zPC = elf_entry;
} else
#endif
@@ -564,10 +618,12 @@ int compare_states(struct tv_spike_t *s)
void flush_logs(void)
{
- fprintf(stderr, "\n");
- fflush(stderr);
- fprintf(stdout, "\n");
- fflush(stdout);
+ if(config_print_instr) {
+ fprintf(stderr, "\n");
+ fflush(stderr);
+ fprintf(stdout, "\n");
+ fflush(stdout);
+ }
}
#ifdef RVFI_DII
@@ -604,7 +660,13 @@ void run_sail(void)
bool need_instr = true;
#endif
- while (!zhtif_done) {
+ struct timeval interval_start;
+ if (gettimeofday(&interval_start, NULL) < 0) {
+ fprintf(stderr, "Cannot gettimeofday: %s\n", strerror(errno));
+ exit(1);
+ }
+
+ while (!zhtif_done && (insn_limit == 0 || total_insns < insn_limit)) {
#ifdef RVFI_DII
if (rvfi_dii) {
if (need_instr) {
@@ -666,6 +728,15 @@ void run_sail(void)
total_insns++;
}
+ if (do_show_times && (total_insns & 0xfffff) == 0) {
+ uint64_t start_us = 1000000 * ((uint64_t) interval_start.tv_sec) + ((uint64_t)interval_start.tv_usec);
+ if (gettimeofday(&interval_start, NULL) < 0) {
+ fprintf(stderr, "Cannot gettimeofday: %s\n", strerror(errno));
+ exit(1);
+ }
+ uint64_t end_us = 1000000 * ((uint64_t) interval_start.tv_sec) + ((uint64_t)interval_start.tv_usec);
+ fprintf(stdout, "kips: %" PRIu64 "\n", ((uint64_t)1000) * 0x100000 / (end_us - start_us));
+ }
#ifdef ENABLE_SPIKE
{ /* run a Spike step */
tv_step(s);
@@ -728,7 +799,7 @@ void init_logs()
}
#endif
- if ((term_fd = open(term_log, O_WRONLY|O_CREAT|O_TRUNC, S_IRUSR|S_IRGRP|S_IROTH|S_IWUSR)) < 0) {
+ if (term_log != NULL && (term_fd = open(term_log, O_WRONLY|O_CREAT|O_TRUNC, S_IRUSR|S_IRGRP|S_IROTH|S_IWUSR)) < 0) {
fprintf(stderr, "Cannot create terminal log '%s': %s\n", term_log, strerror(errno));
exit(1);
}
diff --git a/descr b/descr
index 8f657db..e44ab06 100644
--- a/descr
+++ b/descr
@@ -1 +1 @@
-This package installs a RISC-V emulator (32 and 64 bits) built form the Sail model at https://github.com/rems-project/sail-riscv . \ No newline at end of file
+This package installs a RISC-V emulator (32 and 64 bits) built form the Sail model at https://github.com/rems-project/sail-riscv
diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md
index a13ec94..60e45db 100644
--- a/doc/ExtendingGuide.md
+++ b/doc/ExtendingGuide.md
@@ -44,7 +44,9 @@ exception. This is supported using the `ext` field in the
`sync_exception` type in `riscv_sync_exception.sail`, which is where
the extension can store this information. The addresses involved in
exception handling can be modified by following the interface provided
-in `riscv_sys_exceptions.sail`.
+in `riscv_sys_exceptions.sail`. New exception codes can be introduced
+using the `E_Extension` variant of the `ExceptionType` in
+`riscv_types`.
Adding low-level platform functionality
---------------------------------------
@@ -64,8 +66,8 @@ If this functionality requires the definition of new interrupt
sources, their encodings would need to be added to `riscv_types.sail`,
and their delegation and handling added to `riscv_sys_control.sail`.
-Modifying memory access
------------------------
+Modifying physical memory access
+--------------------------------
Physical memory addressing and access is defined in `riscv_mem.sail`.
Any new regions of memory that are accessible via physical addresses
@@ -84,12 +86,23 @@ to any newly defined architectural state. One can examine how normal
physical memory access is implemented in `riscv_mem.sail` with helpers
in `prelude_mem.sail` and `prelude_mem_metadata.sail`.
+Extending virtual memory and address translation
+------------------------------------------------
+
Virtual memory is implemented in `riscv_vmem.sail`, and defining new
-address translation schemes will require modifying the
-top-level `translateAddr` function. Any access control checks on
-virtual addresses and the specifics of the new address translation can be
-specified in a separate file. This functionality can access any newly
-defined architectural state.
+address translation schemes will require modifying the top-level
+`translateAddr` function. New types of memory access can be defined
+using the definitions in `riscv_vmem_types`. Any access control
+checks on virtual addresses and the specifics of the new address
+translation can be specified in a separate file. This functionality
+can access any newly defined architectural state.
+
+The RV64 architecture has reserved bits in the PTE that can be
+utilized for research experimentation. These bits can be accessed and
+modified using the `ext_pte` argument in functions implementing the
+page-table walk. The information computed by and used during the
+page-table can also be varied using the `ext_ptw` argument, which can
+be defined and used by extensions as needed.
Checking and transforming memory addresses
------------------------------------------
diff --git a/doc/README.md b/doc/README.md
deleted file mode 100644
index 9057e2d..0000000
--- a/doc/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-See the [reading guide](../doc/ReadingGuide.md) to navigate the files
-in this directory.
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md
index deda95e..1e77a33 100644
--- a/doc/ReadingGuide.md
+++ b/doc/ReadingGuide.md
@@ -5,7 +5,12 @@ The model is written in the Sail language. Although specifications in
Sail are quite readable as pseudocode, it would help to have the [Sail
manual](https://github.com/rems-project/sail/blob/sail2/manual.pdf) handy.
-The model contains the following Sail modules in the `model` directory:
+The Sail modules in the `model` directory have the structure shown
+below. Arrows indicate a dependency relationship, and _italics_
+indicate fragments that are not strictly part of the specification,
+such as the platform memory map.
+
+<img src="figs/riscvspecdeps.svg">
- `riscv_xlen32.sail` and `riscv_xlen64.sail` define `xlen` for RV32
and RV64. One of them is chosen during the build using the ARCH
@@ -48,6 +53,11 @@ The model contains the following Sail modules in the `model` directory:
current implementation of these functions usually implement the same
behavior as the Spike emulator.
+- `riscv_pmp_regs.sail` and `riscv_pmp_control.sail` implement support
+ for physical memory protection (PMP). `riscv_pmp_regs` handle read
+ and write access to the PMP registers, while `riscv_pmp_control`
+ implements the permission checking and matching priority.
+
- `riscv_platform.sail` contains platform-specific functionality for
the model. It contains the physical memory map, the local interrupt
controller, and the MMIO interfaces to the clock, timer and terminal
@@ -67,10 +77,11 @@ The model contains the following Sail modules in the `model` directory:
are used in the weak memory concurrency model.
- The `riscv_vmem_*.sail` files describe the S-mode address
- translation. `riscv_vmem_common.sail` contains the definitions and
- processing of the page-table entries and their various permission
- and status bits. `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`,
- and `riscv_vmem_sv48.sail` contain the specifications for the
+ translation. `riscv_vmem_types` and `riscv_vmem_common.sail`
+ contain the definitions and processing of the page-table entries and
+ their various permission and status bits. `riscv_types_ext`,
+ `riscv_vmem_sv32.sail`, `riscv_vmem_sv39.sail`, and
+ `riscv_vmem_sv48.sail` contain the specifications for the
corresponding page-table walks, and `riscv_vmem_rv32.sail` and
`riscv_vmem_rv64.sail` describe the top-level address translation
for the corresponding architectures.
@@ -110,3 +121,35 @@ The model contains the following Sail modules in the `model` directory:
Note that the files above are listed in dependency order, i.e. files
earlier in the order do not depend on later files.
+
+Structure of the C emulator
+----------------------------
+
+The diagram below illustrates how the C emulator is built from the
+Sail model. The OCaml emulator follows the same approach.
+
+<img src="figs/riscvcsimdeps.svg">
+
+The nodes that are not colored are the handwritten C files for the C
+emulator. The black arrows indicate dependency relationships, while
+the red arrow indicates a file generated by the Sail compiler from
+Sail source files.
+
+`riscv_sim` is the top level file for the C emulator: it processes
+command line options, initializes the platform model with any ISA
+implementation choices if specified, and loads the ELF program or OS
+image into raw memory, including any ROM firmware such as the Berkeley
+boot loader and DeviceTree binary blobs, and initializes the memory
+map.
+
+The generated C model `riscv_model_$ARCH` is built from the Sail
+sources by the Sail compiler for the specified architecture $ARCH,
+either RV32 or RV64. It contains calls to the platform interface
+`riscv_platform` for platform-specific information; the latter is
+typically defined as externally specified in the Sail file
+`riscv_platform.sail`.
+
+The Sail system provides a C library for use with its C backend, which
+provides the low-level details of the implementation of raw memory and
+bitvectors (typically optimized to use the native machine word
+representation).
diff --git a/doc/Status.md b/doc/Status.md
new file mode 100644
index 0000000..68e016b
--- /dev/null
+++ b/doc/Status.md
@@ -0,0 +1,58 @@
+The following is a list of ISA features that are currently captured in
+the Sail specification.
+
+- The RV32I and RV64I primary base ISAs.
+
+- The M (multiply/divide), A (atomic), and C (compressed) Standard
+ Extensions.
+
+- The Zicsr Control and Status Register Standard Extension.
+
+- The N Standard Extension for User-Level Interrupts.
+
+- The Base Counters and Timers.
+
+- The Machine-Level and Supervisor-Level ISAs for RV32 and RV64.
+
+- Physical Memory Protection (PMP)
+
+For the status of the RVWMO memory consistency model, please see [the
+RMEM project](https://github.com/rems-project/rmem).
+
+The Sail specification is parameterized over the following
+platform-specific options:
+
+- handling of misaligned data accesses with or without M-mode traps.
+
+- updating of the PTE dirty bit with or without architectural
+ exceptions.
+
+- the contents of the `mtval` register on an illegal instruction
+ exception.
+
+The following is a list of ISA features that are specified in the
+prose ISA specification but that are not yet implemented in the Sail
+specification.
+
+- The RV32E and RV64E subsets of the primary base RV32I and RV64I
+ integer ISAs.
+
+- The RV128 primary base ISA.
+
+- The F (single-precision) and D (double-precision) Floating-Point
+ Standard Extensions.
+
+- An explicit and complete definition of the HINT instructions. As
+ currently implemented, some of them are implicitly implemented as
+ NOPs.
+
+- Specification and implementation of Endianness Control.
+
+- A complete implementation of all hardware performance counters.
+ These are used to count platform-specific events, and hence
+ platform-dependent.
+
+- A specification of the Physical Memory Attributes (PMAs) for the
+ physical memory map.
+
+- The Hypervisor Extension.
diff --git a/doc/figs/Makefile b/doc/figs/Makefile
new file mode 100644
index 0000000..59fe6cb
--- /dev/null
+++ b/doc/figs/Makefile
@@ -0,0 +1,11 @@
+all: riscvspecdeps.svg riscvcsimdeps.svg
+
+%.pdf: %.tex
+ pdflatex $<
+
+%.svg: %.pdf %.tex
+ dvisvgm -Z 1.5 --pdf $<
+
+clean:
+ rm riscvspecdeps.pdf riscvspecdeps.aux riscvspecdeps.log
+ rm riscvcsimdeps.pdf riscvcsimdeps.aux riscvcsimdeps.log
diff --git a/doc/figs/riscvcsimdeps.svg b/doc/figs/riscvcsimdeps.svg
new file mode 100644
index 0000000..8e7c31a
--- /dev/null
+++ b/doc/figs/riscvcsimdeps.svg
@@ -0,0 +1,93 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- This file was generated by dvisvgm 2.7 -->
+<svg version='1.1' xmlns='http://www.w3.org/2000/svg' xmlns:xlink='http://www.w3.org/1999/xlink' width='515.5965pt' height='443.757pt' viewBox='0 -295.838 343.731 295.838'>
+<g id='page1'>
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diff --git a/doc/figs/riscvcsimdeps.tex b/doc/figs/riscvcsimdeps.tex
new file mode 100644
index 0000000..42afda3
--- /dev/null
+++ b/doc/figs/riscvcsimdeps.tex
@@ -0,0 +1,62 @@
+\documentclass[tikz]{standalone}
+
+\usepackage{tikz}
+\usetikzlibrary{calc,positioning}
+
+\begin{document}
+\begin{tikzpicture}[
+ node distance=5mm,
+ align=center,
+ base/.style={rectangle, rounded corners=3mm, minimum size=10mm, thick, draw=black},
+ cmodel/.style={base, fill=yellow!50},
+ sail/.style={base, fill=red!30},
+ c/.style={base},
+ csail/.style={base,fill=red!10},
+ dep/.style={black, very thick},
+ gen/.style={red, very thick}
+ ]
+
+ \node (cmodel) [cmodel] {\textbf{C translation}\\
+ \texttt{riscv\_model\_\$ARCH}};
+
+ \node (csim) [c, above left=of cmodel] {\textbf{C Simulator}\\
+ \texttt{riscv\_sim}\\
+ command line options\\
+ initialization\\
+ exit code};
+
+ \coordinate (smloc) at ($(csim)!2!(csim -| cmodel)$);
+ \node (sailmodel) [sail] at (smloc) {\textbf{Sail model}\\
+ \texttt{*.sail}};
+
+ \node (plat) [c, below right=of cmodel] {\textbf{C platform interface}\\
+ \texttt{riscv\_platform}\\
+ ISA options\\
+ memory map\\
+ \textsc{lr/sc} reservation};
+
+ \node (platimpl) [c, below=of plat] {\textbf{C platform implementation}\\
+ \texttt{riscv\_platform\_impl}};
+
+ \coordinate (clib) at ($(cmodel)!1.5!(cmodel |- platimpl)$);
+
+ \node (csail) [csail] at (clib) {\textbf{C Sail library}\\
+ \texttt{sail,rts,elf}\\
+ Sail values\\
+ raw memory\\
+ ELF loading};
+
+ \draw[->,gen] (sailmodel) edge (cmodel);
+
+ \draw[->,dep] (cmodel) edge (plat)
+ edge (csail);
+
+ \draw[->,dep] (plat) edge (platimpl);
+
+ \draw[->,dep] (csim) edge (cmodel)
+ edge [out=-90,in=180] (platimpl)
+ edge [out=-90,in=135] (csail);
+
+ \draw[->,dep] (platimpl) edge (csail);
+\end{tikzpicture}
+\end{document}
diff --git a/doc/figs/riscvspecdeps.svg b/doc/figs/riscvspecdeps.svg
new file mode 100644
index 0000000..a7c7466
--- /dev/null
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+<path d='M323.75 74.6172C416.68 74.6172 380.465 213.988 380.465 307.875' stroke='#000' fill='none' stroke-width='1.19553' stroke-miterlimit='10'/>
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diff --git a/doc/figs/riscvspecdeps.tex b/doc/figs/riscvspecdeps.tex
new file mode 100644
index 0000000..212f477
--- /dev/null
+++ b/doc/figs/riscvspecdeps.tex
@@ -0,0 +1,96 @@
+\documentclass[tikz]{standalone}
+
+\usepackage{tikz}
+\usetikzlibrary{calc,positioning}
+
+\begin{document}
+\begin{tikzpicture}[
+ node distance=5mm,
+ align=center,
+ spec/.style={rectangle, rounded corners=3mm, minimum size=10mm,
+ thick, draw=black},
+ dep/.style={black, very thick}
+ ]
+
+ % layout the axial nodes
+
+ \node (prelude) [spec] {\textbf{prelude}\\
+ helpers (\texttt{prelude\_*})\\
+ raw physical memory (\texttt{prelude\_mem})};
+ \node (types) [spec, above=of prelude] {\texttt{riscv\_reg\_type, riscv\_types}\\
+ registers, indices,\\
+ exceptions, privilege-levels, \ldots};
+
+ \node (regfile) [spec, above=of types] {\texttt{riscv\_regs, riscv\_sys\_regs}\\
+ PC (+\texttt{riscv\_pc\_access})\\
+ integer regs (user)\\
+ system regs\\
+ current privilege};
+
+ \node (pmp) [spec, above=of regfile] {\textbf{PMP}\\
+ \texttt{riscv\_pmp\_regs, riscv\_pmp\_control}\\
+ physical memory protection};
+
+ % compute location for virtmem
+ \coordinate (vmloc) at ($(types)!3!(pmp)$);
+ \node (virtmem) [spec] at (vmloc) {\textbf{virtual memory}\\
+ PTE formats, TLB (\texttt{riscv\_vmem\_\{types,common\}})\\
+ page table walks (\texttt{riscv\_types\_ext},\texttt{riscv\_vmem\_svNN})\\
+ address translation (\texttt{riscv\_vmem\_rvNN})};
+
+
+ % compute other relative locations for vertical alignment
+ \coordinate (midpt) at ($(pmp.north)!0.5!(virtmem.south)$);
+ \coordinate (exloc) at ($(midpt)!1.1!90:(virtmem.south)$);
+ \coordinate (pmloc) at ($(midpt)!1.2!-90:(virtmem.south)$);
+
+ \node (excepts) [spec] at (exloc) {\textbf{privilege transition}\\
+ exceptions, interrupts\\
+ returns\\
+ (\texttt{riscv\_sync\_exception},\\
+ \texttt{riscv\_sys\_control})};
+
+ \node (physmem) [spec] at (pmloc) {\textbf{physical memory}\\
+ \textit{platform memory map},\\
+ \textit{MMIO devices} (\texttt{riscv\_platform})\\
+ memory access (\texttt{riscv\_mem})};
+
+
+
+ \node (addrchk) [spec, right=of virtmem] {\textbf{address checks, transforms}\\
+ \texttt{riscv\_addr\_checks*}};
+ \node (insts) [spec, above=of virtmem] {\textbf{instructions}\\
+ decode, execute, assembler (\texttt{riscv\_insts\_*})};
+ \node (fetch) [spec, above=of insts] {\texttt{riscv\_step}\\
+ fetch-execute\\
+ interrupt dispatch\\
+ clock tick};
+
+ \draw[<-,dep] (prelude) edge (types);
+
+ \draw[<-,dep] (types) edge [out=0, in=270] (physmem)
+ edge (regfile);
+
+ \draw[<-,dep] (regfile) edge (pmp)
+ edge [out=180, in=270] (excepts)
+ edge [out=0, in=270] (virtmem)
+ edge [out=180, in=180] (insts)
+ edge [out=180, in=180] (fetch);
+
+ \draw[<-,dep] (pmp) edge (physmem);
+
+ \draw[<-,dep] (excepts) edge (virtmem)
+ edge [out=90, in=180] (insts);
+
+ \draw[<-,dep] (addrchk) edge (insts)
+ edge [->,out=-45,in=0] (regfile);
+
+
+ \draw[<-,dep] (physmem) edge (virtmem);
+
+ \draw[<-,dep] (virtmem) edge (insts);
+
+ \draw[<-,dep] (insts) edge (fetch);
+
+\end{tikzpicture}
+\end{document}
diff --git a/handwritten_support/0.7.1/riscv_extras.lem b/handwritten_support/0.11/riscv_extras.lem
index c1a52c9..f4ade26 100644
--- a/handwritten_support/0.7.1/riscv_extras.lem
+++ b/handwritten_support/0.11/riscv_extras.lem
@@ -8,17 +8,17 @@ open import Sail2_prompt
type bitvector 'a = mword 'a
-let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw
-let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw
-let MEM_fence_r_r () = barrier Barrier_RISCV_r_r
-let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w
-let MEM_fence_w_w () = barrier Barrier_RISCV_w_w
-let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw
-let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r
-let MEM_fence_r_w () = barrier Barrier_RISCV_r_w
-let MEM_fence_w_r () = barrier Barrier_RISCV_w_r
-let MEM_fence_tso () = barrier Barrier_RISCV_tso
-let MEM_fence_i () = barrier Barrier_RISCV_i
+let MEM_fence_rw_rw () = barrier (Barrier_RISCV_rw_rw ())
+let MEM_fence_r_rw () = barrier (Barrier_RISCV_r_rw ())
+let MEM_fence_r_r () = barrier (Barrier_RISCV_r_r ())
+let MEM_fence_rw_w () = barrier (Barrier_RISCV_rw_w ())
+let MEM_fence_w_w () = barrier (Barrier_RISCV_w_w ())
+let MEM_fence_w_rw () = barrier (Barrier_RISCV_w_rw ())
+let MEM_fence_rw_r () = barrier (Barrier_RISCV_rw_r ())
+let MEM_fence_r_w () = barrier (Barrier_RISCV_r_w ())
+let MEM_fence_w_r () = barrier (Barrier_RISCV_w_r ())
+let MEM_fence_tso () = barrier (Barrier_RISCV_tso ())
+let MEM_fence_i () = barrier (Barrier_RISCV_i ())
val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
@@ -27,13 +27,13 @@ val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a
val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
-let MEMea addr size = write_mem_ea Write_plain addr size
-let MEMea_release addr size = write_mem_ea Write_RISCV_release addr size
-let MEMea_strong_release addr size = write_mem_ea Write_RISCV_strong_release addr size
-let MEMea_conditional addr size = write_mem_ea Write_RISCV_conditional addr size
-let MEMea_conditional_release addr size = write_mem_ea Write_RISCV_conditional_release addr size
+let MEMea addr size = write_mem_ea Write_plain () addr size
+let MEMea_release addr size = write_mem_ea Write_RISCV_release () addr size
+let MEMea_strong_release addr size = write_mem_ea Write_RISCV_strong_release () addr size
+let MEMea_conditional addr size = write_mem_ea Write_RISCV_conditional () addr size
+let MEMea_conditional_release addr size = write_mem_ea Write_RISCV_conditional_release () addr size
let MEMea_conditional_strong_release addr size
- = write_mem_ea Write_RISCV_conditional_strong_release addr size
+ = write_mem_ea Write_RISCV_conditional_strong_release () addr size
val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
@@ -42,22 +42,26 @@ val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => inte
val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
-let MEMr addrsize size hexRAM addr = read_mem Read_plain addr size
-let MEMr_acquire addrsize size hexRAM addr = read_mem Read_RISCV_acquire addr size
-let MEMr_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_strong_acquire addr size
-let MEMr_reserved addrsize size hexRAM addr = read_mem Read_RISCV_reserved addr size
-let MEMr_reserved_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_acquire addr size
-let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addr size
-
-val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
- integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
-let write_ram addrsize size hexRAM address value =
- write_mem_val value
-
-val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
- integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
-let read_ram addrsize size hexRAM address =
- read_mem Read_plain address size
+let MEMr addrsize size hexRAM addr = read_mem Read_plain addrsize addr size
+let MEMr_acquire addrsize size hexRAM addr = read_mem Read_RISCV_acquire addrsize addr size
+let MEMr_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_strong_acquire addrsize addr size
+let MEMr_reserved addrsize size hexRAM addr = read_mem Read_RISCV_reserved addrsize addr size
+let MEMr_reserved_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_acquire addrsize addr size
+let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV_reserved_strong_acquire addrsize addr size
+
+val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+
+let MEMw addrsize size hexRAM addr = write_mem Write_plain addrsize addr size
+let MEMw_release addrsize size hexRAM addr = write_mem Write_RISCV_release addrsize addr size
+let MEMw_strong_release addrsize size hexRAM addr = write_mem Write_RISCV_strong_release addrsize addr size
+let MEMw_conditional addrsize size hexRAM addr = write_mem Write_RISCV_conditional addrsize addr size
+let MEMw_conditional_release addrsize size hexRAM addr = write_mem Write_RISCV_conditional_release addrsize addr size
+let MEMw_conditional_strong_release addrsize size hexRAM addr = write_mem Write_RISCV_conditional_strong_release addrsize addr size
val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit
let load_reservation addr = ()
@@ -67,6 +71,14 @@ let speculate_conditional_success () = excl_result ()
let match_reservation _ = true
let cancel_reservation () = ()
+val sys_enable_writable_misa : unit -> bool
+let sys_enable_writable_misa () = true
+declare ocaml target_rep function sys_enable_writable_misa = `Platform.enable_writable_misa`
+
+val sys_enable_rvc : unit -> bool
+let sys_enable_rvc () = true
+declare ocaml target_rep function sys_enable_rvc = `Platform.enable_rvc`
+
val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a
let plat_ram_base () = wordFromInteger 0
declare ocaml target_rep function plat_ram_base = `Platform.dram_base`
@@ -99,6 +111,10 @@ val plat_enable_misaligned_access : unit -> bool
let plat_enable_misaligned_access () = false
declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access`
+val plat_enable_pmp : unit -> bool
+let plat_enable_pmp () = false
+declare ocaml target_rep function plat_enable_pmp = `Platform.enable_pmp`
+
val plat_mtval_has_illegal_inst_bits : unit -> bool
let plat_mtval_has_illegal_inst_bits () = false
declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits`
@@ -135,3 +151,6 @@ let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
+
+val print_dbg : string -> unit
+let print_dbg msg = ()
diff --git a/handwritten_support/0.7.1/riscv_extras_sequential.lem b/handwritten_support/0.11/riscv_extras_sequential.lem
index c1a52c9..ac70ee5 100644
--- a/handwritten_support/0.7.1/riscv_extras_sequential.lem
+++ b/handwritten_support/0.11/riscv_extras_sequential.lem
@@ -8,17 +8,17 @@ open import Sail2_prompt
type bitvector 'a = mword 'a
-let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw
-let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw
-let MEM_fence_r_r () = barrier Barrier_RISCV_r_r
-let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w
-let MEM_fence_w_w () = barrier Barrier_RISCV_w_w
-let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw
-let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r
-let MEM_fence_r_w () = barrier Barrier_RISCV_r_w
-let MEM_fence_w_r () = barrier Barrier_RISCV_w_r
-let MEM_fence_tso () = barrier Barrier_RISCV_tso
-let MEM_fence_i () = barrier Barrier_RISCV_i
+let MEM_fence_rw_rw () = barrier (Barrier_RISCV_rw_rw ())
+let MEM_fence_r_rw () = barrier (Barrier_RISCV_r_rw ())
+let MEM_fence_r_r () = barrier (Barrier_RISCV_r_r ())
+let MEM_fence_rw_w () = barrier (Barrier_RISCV_rw_w ())
+let MEM_fence_w_w () = barrier (Barrier_RISCV_w_w ())
+let MEM_fence_w_rw () = barrier (Barrier_RISCV_w_rw ())
+let MEM_fence_rw_r () = barrier (Barrier_RISCV_rw_r ())
+let MEM_fence_r_w () = barrier (Barrier_RISCV_r_w ())
+let MEM_fence_w_r () = barrier (Barrier_RISCV_w_r ())
+let MEM_fence_tso () = barrier (Barrier_RISCV_tso ())
+let MEM_fence_i () = barrier (Barrier_RISCV_i ())
val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
@@ -52,7 +52,7 @@ let MEMr_reserved_strong_acquire addrsize size hexRAM addr = read_mem Read_RISCV
val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
let write_ram addrsize size hexRAM address value =
- write_mem_val value
+ write_mem Write_plain address size value
val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
@@ -67,6 +67,14 @@ let speculate_conditional_success () = excl_result ()
let match_reservation _ = true
let cancel_reservation () = ()
+val sys_enable_writable_misa : unit -> bool
+let sys_enable_writable_misa () = true
+declare ocaml target_rep function sys_enable_writable_misa = `Platform.enable_writable_misa`
+
+val sys_enable_rvc : unit -> bool
+let sys_enable_rvc () = true
+declare ocaml target_rep function sys_enable_rvc = `Platform.enable_rvc`
+
val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a
let plat_ram_base () = wordFromInteger 0
declare ocaml target_rep function plat_ram_base = `Platform.dram_base`
@@ -99,6 +107,10 @@ val plat_enable_misaligned_access : unit -> bool
let plat_enable_misaligned_access () = false
declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access`
+val plat_enable_pmp : unit -> bool
+let plat_enable_pmp () = false
+declare ocaml target_rep function plat_enable_pmp = `Platform.enable_pmp`
+
val plat_mtval_has_illegal_inst_bits : unit -> bool
let plat_mtval_has_illegal_inst_bits () = false
declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits`
@@ -135,3 +147,6 @@ let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
let print_bits msg bs = () (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
+
+val print_dbg : string -> unit
+let print_dbg msg = ()
diff --git a/handwritten_support/riscv_extras.lem b/handwritten_support/riscv_extras.lem
index 66b5d94..da6106d 100644
--- a/handwritten_support/riscv_extras.lem
+++ b/handwritten_support/riscv_extras.lem
@@ -111,6 +111,10 @@ val plat_enable_misaligned_access : unit -> bool
let plat_enable_misaligned_access () = false
declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access`
+val plat_enable_pmp : unit -> bool
+let plat_enable_pmp () = false
+declare ocaml target_rep function plat_enable_pmp = `Platform.enable_pmp`
+
val plat_mtval_has_illegal_inst_bits : unit -> bool
let plat_mtval_has_illegal_inst_bits () = false
declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits`
diff --git a/handwritten_support/riscv_extras.v b/handwritten_support/riscv_extras.v
index 5828f88..84f6761 100644
--- a/handwritten_support/riscv_extras.v
+++ b/handwritten_support/riscv_extras.v
@@ -9,17 +9,17 @@ Import List.ListNotations.
Axiom real : Type.
-Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_rw.
-Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_rw.
-Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_r.
-Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_w.
-Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_w.
-Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_rw.
-Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_r.
-Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_w.
-Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_r.
-Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_tso.
-Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_i.
+Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_rw tt).
+Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_rw tt).
+Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_r tt).
+Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_w tt).
+Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_w tt).
+Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_rw tt).
+Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_r tt).
+Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_w tt).
+Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_r tt).
+Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_tso tt).
+Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_i tt).
(*
val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
diff --git a/handwritten_support/riscv_extras_sequential.lem b/handwritten_support/riscv_extras_sequential.lem
index 604911a..7715614 100644
--- a/handwritten_support/riscv_extras_sequential.lem
+++ b/handwritten_support/riscv_extras_sequential.lem
@@ -107,6 +107,10 @@ val plat_enable_misaligned_access : unit -> bool
let plat_enable_misaligned_access () = false
declare ocaml target_rep function plat_enable_misaligned_access = `Platform.enable_misaligned_access`
+val plat_enable_pmp : unit -> bool
+let plat_enable_pmp () = false
+declare ocaml target_rep function plat_enable_pmp = `Platform.enable_pmp`
+
val plat_mtval_has_illegal_inst_bits : unit -> bool
let plat_mtval_has_illegal_inst_bits () = false
declare ocaml target_rep function plat_mtval_has_illegal_inst_bits = `Platform.mtval_has_illegal_inst_bits`
diff --git a/model/main.sail b/model/main.sail
index 8040bdb..9abe1a5 100644
--- a/model/main.sail
+++ b/model/main.sail
@@ -1,6 +1,4 @@
-val main : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg}
-
-function main () = {
+function main () : unit -> unit = {
// initialize extensions
ext_init ();
diff --git a/model/prelude.sail b/model/prelude.sail
index 31d5668..a8faf3d 100644
--- a/model/prelude.sail
+++ b/model/prelude.sail
@@ -13,7 +13,7 @@ val string_take = "string_take" : (string, nat) -> string
val string_length = "string_length" : string -> nat
val string_append = {c: "concat_str", _: "string_append"} : (string, string) -> string
-val eq_anything = {ocaml: "(fun (x, y) -> x = y)", interpreter: "eq_anything", lem: "eq", coq: "generic_eq"} : forall ('a : Type). ('a, 'a) -> bool
+val eq_anything = {ocaml: "(fun (x, y) -> x = y)", interpreter: "eq_anything", lem: "eq", coq: "generic_eq", c: "eq_anything"} : forall ('a : Type). ('a, 'a) -> bool
overload operator == = {eq_string, eq_anything}
@@ -29,7 +29,7 @@ overload vector_update = {any_vector_update}
val update_subrange = {ocaml: "update_subrange", interpreter: "update_subrange", lem: "update_subrange_vec_dec", coq: "update_subrange_vec_dec"} : forall 'n 'm 'o.
(bits('n), atom('m), atom('o), bits('m - ('o - 1))) -> bits('n)
-val vector_concat = {ocaml: "append", lem: "append_list"} : forall ('n : Int) ('m : Int) ('a : Type).
+val vector_concat = {ocaml: "append", lem: "append_list", coq: "vec_concat"} : forall ('n : Int) ('m : Int) ('a : Type).
(vector('n, dec, 'a), vector('m, dec, 'a)) -> vector('n + 'm, dec, 'a)
overload append = {vector_concat}
@@ -50,16 +50,17 @@ overload operator & = {and_vec}
overload operator | = {or_vec}
-val cast cast_unit_vec : bit -> bits(1)
+val string_of_int = {c: "string_of_int", ocaml: "string_of_int", interpreter: "string_of_int", lem: "stringFromInteger", coq: "string_of_int"} : int -> string
-function cast_unit_vec b = match b {
- bitzero => 0b0,
- bitone => 0b1
-}
+val "string_of_bits" : forall 'n. bits('n) -> string
-val string_of_int = {c: "string_of_int", ocaml: "string_of_int", lem: "stringFromInteger", coq: "string_of_int"} : int -> string
+function string_of_bit(b: bit) -> string =
+ match b {
+ bitzero => "0b0",
+ bitone => "0b1"
+ }
-val BitStr = "string_of_bits" : forall 'n. bits('n) -> string
+overload BitStr = {string_of_bits, string_of_bit}
val xor_vec = {c: "xor_bits", _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n)
@@ -73,13 +74,13 @@ val sub_vec_int = {c: "sub_bits_int", _: "sub_vec_int"} : forall 'n. (bits('n),
overload operator - = {sub_vec, sub_vec_int}
-val quot_round_zero = {ocaml: "quot_round_zero", interpreter: "quot_round_zero", lem: "hardware_quot", c: "tdiv_int"} : (int, int) -> int
-val rem_round_zero = {ocaml: "rem_round_zero", interpreter: "rem_round_zero", lem: "hardware_mod", c: "tmod_int"} : (int, int) -> int
+val quot_round_zero = {ocaml: "quot_round_zero", interpreter: "quot_round_zero", lem: "hardware_quot", c: "tdiv_int", coq: "Z.quot"} : (int, int) -> int
+val rem_round_zero = {ocaml: "rem_round_zero", interpreter: "rem_round_zero", lem: "hardware_mod", c: "tmod_int", coq: "Z.rem"} : (int, int) -> int
/* The following should get us euclidean modulus, and is compatible with pre and post 0.9 versions of sail */
overload operator % = {emod_int, mod}
-val min_nat = {ocaml: "min_int", lem: "min", coq: "min_nat", c: "min_int"} : (nat, nat) -> nat
+val min_nat = {ocaml: "min_int", interpreter: "min_int", lem: "min", coq: "min_nat", c: "min_int"} : (nat, nat) -> nat
val min_int = {ocaml: "min_int", interpreter: "min_int", lem: "min", coq: "Z.min", c: "min_int"} : (int, int) -> int
@@ -101,25 +102,17 @@ val print_reg = {ocaml: "Platform.print_reg", interpreter: "print_endline",
val print_mem = {ocaml: "Platform.print_mem_access", interpreter: "print_endline", c: "print_mem_access", lem: "print_dbg", _: "print_endline"} : string -> unit
val print_platform = {ocaml: "Platform.print_platform", interpreter: "print_endline", c: "print_platform", lem: "print_dbg", _: "print_endline"} : string -> unit
-$ifndef FEATURE_IMPLICITS
-val EXTS : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m)
-val EXTZ : forall 'n 'm , 'm >= 'n . bits('n) -> bits('m)
-function EXTS v = sail_sign_extend(v, sizeof('m))
-function EXTZ v = sail_zero_extend(v, sizeof('m))
-
-val zeros_implicit : forall 'n, 'n >= 0 . unit -> bits('n)
-function zeros_implicit () = sail_zeros('n)
-overload zeros = {zeros_implicit, sail_zeros}
-
-val ones_n : forall 'n, 'n >= 0 . int('n) -> bits('n)
-function ones_n n = replicate_bits (0b1, n)
+val get_config_print_instr = {ocaml: "Platform.get_config_print_instr", c:"get_config_print_instr"} : unit -> bool
+val get_config_print_reg = {ocaml: "Platform.get_config_print_reg", c:"get_config_print_reg"} : unit -> bool
+val get_config_print_mem = {ocaml: "Platform.get_config_print_mem", c:"get_config_print_mem"} : unit -> bool
-val ones_implicit : forall 'n, 'n >= 0 . unit -> bits('n)
-function ones_implicit () = ones_n ('n)
+val get_config_print_platform = {ocaml: "Platform.get_config_print_platform", c:"get_config_print_platform"} : unit -> bool
+// defaults for other backends
+function get_config_print_instr () = false
+function get_config_print_reg () = false
+function get_config_print_mem () = false
+function get_config_print_platform () = false
-overload ones = {ones_implicit, ones_n}
-
-$else
val EXTS : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)
val EXTZ : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)
@@ -128,22 +121,15 @@ function EXTZ(m, v) = sail_zero_extend(v, m)
val zeros_implicit : forall 'n, 'n >= 0 . implicit('n) -> bits('n)
function zeros_implicit (n) = sail_zeros(n)
-overload zeros = {zeros_implicit, sail_zeros}
-
-val ones_n : forall 'n, 'n >= 0 . int('n) -> bits('n)
-function ones_n n = replicate_bits (0b1, n)
-
-val ones_implicit : forall 'n, 'n >= 0 . implicit('n) -> bits('n)
-function ones_implicit (n) = ones_n (n)
-
-overload ones = {ones_implicit, ones_n}
+overload zeros = {zeros_implicit}
-$endif
+val ones : forall 'n, 'n >= 0 . implicit('n) -> bits('n)
+function ones (n) = sail_ones (n)
-val cast bool_to_bits : bool -> bits(1)
+val bool_to_bits : bool -> bits(1)
function bool_to_bits x = if x then 0b1 else 0b0
-val cast bit_to_bool : bit -> bool
+val bit_to_bool : bit -> bool
function bit_to_bool b = match b {
bitone => true,
bitzero => false
diff --git a/model/prelude_mapping.sail b/model/prelude_mapping.sail
index e40edbf..070c4cb 100644
--- a/model/prelude_mapping.sail
+++ b/model/prelude_mapping.sail
@@ -1,5 +1,11 @@
/* Some helper functions for the assembler mappings. */
+/* These mappings produce a lot of pattern match warnings that are not useful.
+ The following directive suppresses them (and will be ignored by older versions of Sail
+ with one additional warning). Would be better to fix the warnings properly but I don't
+ know how. */
+$suppress_warnings
+
/* Python:
f = """val hex_bits_{0} : bits({0}) <-> string
val hex_bits_{0}_forwards = "decimal_string_of_bits" : bits({0}) -> string
diff --git a/model/prelude_mem.sail b/model/prelude_mem.sail
index 1c6c4cb..b8d47d0 100644
--- a/model/prelude_mem.sail
+++ b/model/prelude_mem.sail
@@ -4,9 +4,22 @@
* They also depend on the type of metadata that is read and written
* to physical memory. For models that do not require this metadata,
* a unit type can be used.
+ *
+ * The underlying __read_mem and __write_mem functions are from the
+ * Sail library. The metadata primitives __{Read,Write}RAM_Meta are
+ * in prelude_mem_metadata.
*/
-val write_ram : forall 'n, 'n > 0. (write_kind, xlenbits, atom('n), bits(8 * 'n), mem_meta) -> bool effect {wmv, wmvt}
+
+/* This is a slightly arbitrary limit on the maximum number of bytes
+ in a memory access. It helps to generate slightly better C code
+ because it means width argument can be fast native integer. It
+ would be even better if it could be <= 8 bytes so that data can
+ also be a 64-bit int but CHERI needs 128-bit accesses for
+ capabilities and SIMD / vector instructions will also need more. */
+ type max_mem_access : Int = 16
+
+val write_ram : forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, atom('n), bits(8 * 'n), mem_meta) -> bool effect {wmv, wmvt}
function write_ram(wk, addr, width, data, meta) = {
/* Write out metadata only if the value write succeeds.
* It is assumed for now that this write always succeeds;
@@ -19,39 +32,14 @@ function write_ram(wk, addr, width, data, meta) = {
ret
}
-val __TraceMemoryWrite : forall 'n 'm.
- (atom('n), bits('m), bits(8 * 'n)) -> unit
-
-val __ReadRAM = { lem: "MEMr", coq: "MEMr", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-
-val __ReadRAM_acquire = { lem: "MEMr_acquire", coq: "MEMr_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-
-val __ReadRAM_strong_acquire = { lem: "MEMr_strong_acquire", coq: "MEMr_strong_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-
-val __ReadRAM_reserved = { lem: "MEMr_reserved", coq: "MEMr_reserved", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-
-val __ReadRAM_reserved_acquire = { lem: "MEMr_reserved_acquire", coq: "MEMr_reserved_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-
-val __ReadRAM_reserved_strong_acquire = { lem: "MEMr_reserved_strong_acquire", coq: "MEMr_reserved_strong_acquire", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
- (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+val write_ram_ea : forall 'n, 0 < 'n <= max_mem_access . (write_kind, xlenbits, atom('n)) -> unit effect {eamem}
+function write_ram_ea(wk, addr, width) =
+ __write_mem_ea(wk, sizeof(xlen), addr, width)
-/* FIXME: the metadata is currently not read atomically wrt the value. */
-val __RISCV_read : forall 'n, 'n >= 0. (xlenbits, atom('n), bool, bool, bool) -> option(bits(8 * 'n)) effect {rmem}
-function __RISCV_read (addr, width, aq, rl, res) =
- match (aq, rl, res) {
- (false, false, false) => Some(__ReadRAM(sizeof(xlen), width, EXTZ(0x0), addr)),
- (true, false, false) => Some(__ReadRAM_acquire(sizeof(xlen), width, EXTZ(0x0), addr)),
- (true, true, false) => Some(__ReadRAM_strong_acquire(sizeof(xlen), width, EXTZ(0x0), addr)),
- (false, false, true) => Some(__ReadRAM_reserved(sizeof(xlen), width, EXTZ(0x0), addr)),
- (true, false, true) => Some(__ReadRAM_reserved_acquire(sizeof(xlen), width, EXTZ(0x0), addr)),
- (true, true, true) => Some(__ReadRAM_reserved_strong_acquire(sizeof(xlen), width, EXTZ(0x0), addr)),
- (false, true, false) => None(),
- (false, true, true) => None()
- }
+/* FIXME: Make this also return the metadata, which will also require external API changes. */
+val read_ram : forall 'n, 0 < 'n <= max_mem_access . (read_kind, xlenbits, atom('n)) -> bits(8 * 'n) effect {rmem}
+function read_ram(rk, addr, width) =
+ __read_mem(rk, sizeof(xlen), addr, width)
-val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
+val __TraceMemoryWrite : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
+val __TraceMemoryRead : forall 'n 'm. (atom('n), bits('m), bits(8 * 'n)) -> unit
diff --git a/model/riscv_addr_checks.sail b/model/riscv_addr_checks.sail
index 28e688d..318d2a2 100644
--- a/model/riscv_addr_checks.sail
+++ b/model/riscv_addr_checks.sail
@@ -46,7 +46,7 @@ type ext_data_addr_error = unit
/* Default data addr is just base register + immediate offset (may be zero).
Extensions might override and add additional checks. */
-function ext_data_get_addr(base : regidx, offset : xlenbits, acc : AccessType, rt : ReadType, width : word_width)
+function ext_data_get_addr(base : regidx, offset : xlenbits, acc : AccessType(ext_access_type), width : word_width)
-> Ext_DataAddr_Check(ext_data_addr_error) =
let addr = X(base) + offset in
Ext_DataAddr_OK(addr)
diff --git a/model/riscv_analysis.sail b/model/riscv_analysis.sail
index 34572f8..5b55e6e 100644
--- a/model/riscv_analysis.sail
+++ b/model/riscv_analysis.sail
@@ -1,15 +1,18 @@
$include <regfp.sail>
/* in reverse order because inc vectors don't seem to work (bug) */
-let GPRstr : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21",
+let GPRstrs : vector(32, dec, string) = [ "x31", "x30", "x29", "x28", "x27", "x26", "x25", "x24", "x23", "x22", "x21",
"x20", "x19", "x18", "x17", "x16", "x15", "x14", "x13", "x12", "x11",
"x10", "x9", "x8", "x7", "x6", "x5", "x4", "x3", "x2", "x1", "x0"
]
+function GPRstr(i: bits(5)) -> string = GPRstrs[unsigned(i)]
let CIA_fp = RFull("CIA")
let NIA_fp = RFull("NIA")
+$ifndef FEATURE_UNION_BARRIER
+
function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {
iR = [| |] : regfps;
oR = [| |] : regfps;
@@ -21,40 +24,40 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
match instr {
EBREAK() => (),
UTYPE(imm, rd, op) => {
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
RISCV_JAL(imm, rd) => {
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
let offset : bits(64) = EXTS(imm) in
Nias = [| NIAFP_concrete_address (PC + offset) |];
ik = IK_branch();
},
RISCV_JALR(imm, rs, rd) => {
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
let offset : bits(64) = EXTS(imm) in
Nias = [| NIAFP_indirect_address() |];
ik = IK_branch();
},
BTYPE(imm, rs2, rs1, op) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
ik = IK_branch();
let offset : bits(64) = EXTS(imm) in
Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];
},
ITYPE(imm, rs, rd, op) => {
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
SHIFTIOP(imm, rs, rd, op) => {
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
RTYPE(rs2, rs1, rd, op) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
CSR(csr, rs1, rd, is_imm, op) => {
let isWrite : bool = match op {
@@ -63,16 +66,16 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
};
iR = RFull(csr_name(csr)) :: iR;
if ~(is_imm) then {
- iR = RFull(GPRstr[rs1]) :: iR;
+ iR = RFull(GPRstr(rs1)) :: iR;
};
if isWrite then {
oR = RFull(csr_name(csr)) :: oR;
};
- oR = RFull(GPRstr[rd]) :: oR;
+ oR = RFull(GPRstr(rd)) :: oR;
},
LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
aR = iR;
ik =
match (aq, rl) {
@@ -84,9 +87,9 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
}
},
STORE(imm, rs2, rs1, width, aq, rl) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
ik =
match (aq, rl) {
(false, false) => IK_mem_write (Write_plain),
@@ -97,17 +100,17 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
}
},
ADDIW(imm, rs, rd) => {
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
SHIFTW(imm, rs, rd, op) => {
- if (rs == 0) then () else iR = RFull(GPRstr[rs]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
RTYPEW(rs2, rs1, rd, op) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
},
FENCE(pred, succ) => {
ik =
@@ -139,8 +142,180 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i
},
LOADRES(aq, rl, rs1, width, rd) => {
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ aR = iR;
+ ik = match (aq, rl) {
+ (false, false) => IK_mem_read (Read_RISCV_reserved),
+ (true, false) => IK_mem_read (Read_RISCV_reserved_acquire),
+ (true, true) => IK_mem_read (Read_RISCV_reserved_strong_acquire),
+ (false, true) => internal_error("LOADRES type not implemented in initial_analysis")
+ };
+ },
+ STORECON(aq, rl, rs2, rs1, width, rd) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ ik = match (aq, rl) {
+ (false, false) => IK_mem_write (Write_RISCV_conditional),
+ (false, true) => IK_mem_write (Write_RISCV_conditional_release),
+ (true, true) => IK_mem_write (Write_RISCV_conditional_strong_release),
+
+ (true, false) => internal_error("STORECON type not implemented in initial_analysis")
+ };
+ },
+ AMO(op, aq, rl, rs2, rs1, width, rd) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ ik = match (aq, rl) {
+ (false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional),
+ (false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release),
+ (true, false) => IK_mem_rmw (Read_RISCV_reserved_acquire,
+ Write_RISCV_conditional),
+ (true, true) => IK_mem_rmw (Read_RISCV_reserved_acquire,
+ Write_RISCV_conditional_release)
+ };
+ },
+ _ => ()
+ };
+ (iR,oR,aR,Nias,Dia,ik)
+}
+
+$else
+
+function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = {
+ iR = [| |] : regfps;
+ oR = [| |] : regfps;
+ aR = [| |] : regfps;
+ ik = IK_simple() : instruction_kind;
+ Nias = [| NIAFP_successor() |] : niafps;
+ Dia = DIAFP_none() : diafp;
+
+ match instr {
+ EBREAK() => (),
+ UTYPE(imm, rd, op) => {
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ RISCV_JAL(imm, rd) => {
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ let offset : bits(64) = EXTS(imm) in
+ Nias = [| NIAFP_concrete_address (PC + offset) |];
+ ik = IK_branch();
+ },
+ RISCV_JALR(imm, rs, rd) => {
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ let offset : bits(64) = EXTS(imm) in
+ Nias = [| NIAFP_indirect_address() |];
+ ik = IK_branch();
+ },
+ BTYPE(imm, rs2, rs1, op) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ ik = IK_branch();
+ let offset : bits(64) = EXTS(imm) in
+ Nias = [| NIAFP_concrete_address(PC + offset), NIAFP_successor() |];
+ },
+ ITYPE(imm, rs, rd, op) => {
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ SHIFTIOP(imm, rs, rd, op) => {
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ RTYPE(rs2, rs1, rd, op) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ CSR(csr, rs1, rd, is_imm, op) => {
+ let isWrite : bool = match op {
+ CSRRW => true,
+ _ => if is_imm then unsigned(rs1) != 0 else unsigned(rs1) != 0
+ };
+ iR = RFull(csr_name(csr)) :: iR;
+ if ~(is_imm) then {
+ iR = RFull(GPRstr(rs1)) :: iR;
+ };
+ if isWrite then {
+ oR = RFull(csr_name(csr)) :: oR;
+ };
+ oR = RFull(GPRstr(rd)) :: oR;
+ },
+ LOAD(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ aR = iR;
+ ik =
+ match (aq, rl) {
+ (false, false) => IK_mem_read (Read_plain),
+ (true, false) => IK_mem_read (Read_RISCV_acquire),
+ (true, true) => IK_mem_read (Read_RISCV_strong_acquire),
+
+ _ => internal_error("LOAD type not implemented in initial_analysis")
+ }
+ },
+ STORE(imm, rs2, rs1, width, aq, rl) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
+ ik =
+ match (aq, rl) {
+ (false, false) => IK_mem_write (Write_plain),
+ (false, true) => IK_mem_write (Write_RISCV_release),
+ (true, true) => IK_mem_write (Write_RISCV_strong_release),
+
+ _ => internal_error("STORE type not implemented in initial_analysis")
+ }
+ },
+ ADDIW(imm, rs, rd) => {
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ SHIFTW(imm, rs, rd, op) => {
+ if (rs == 0b00000) then () else iR = RFull(GPRstr(rs)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ RTYPEW(rs2, rs1, rd, op) => {
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
+ },
+ FENCE(pred, succ) => {
+ ik =
+ match (pred, succ) {
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_rw_rw ()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_r_rw ()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_r_r ()),
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_rw_w ()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_w_w ()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_w_rw ()),
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_rw_r ()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => IK_barrier (Barrier_RISCV_r_w ()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => IK_barrier (Barrier_RISCV_w_r ()),
+
+ (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => IK_simple (),
+
+ _ => internal_error("barrier type not implemented in initial_analysis")
+ };
+ },
+ FENCE_TSO(pred, succ) => {
+ ik =
+ match (pred, succ) {
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => IK_barrier (Barrier_RISCV_tso ()),
+ _ => internal_error("barrier type not implemented in initial_analysis")
+ };
+ },
+ FENCEI() => {
+ ik = IK_simple (); // for RMEM, should morally be Barrier_RISCV_i
+ },
+ LOADRES(aq, rl, rs1, width, rd) => {
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
aR = iR;
ik = match (aq, rl) {
(false, false) => IK_mem_read (Read_RISCV_reserved),
@@ -150,10 +325,10 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
};
},
STORECON(aq, rl, rs2, rs1, width, rd) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
ik = match (aq, rl) {
(false, false) => IK_mem_write (Write_RISCV_conditional),
(false, true) => IK_mem_write (Write_RISCV_conditional_release),
@@ -163,10 +338,10 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
};
},
AMO(op, aq, rl, rs2, rs1, width, rd) => {
- if (rs2 == 0) then () else iR = RFull(GPRstr[rs2]) :: iR;
- if (rs1 == 0) then () else iR = RFull(GPRstr[rs1]) :: iR;
- if (rs1 == 0) then () else aR = RFull(GPRstr[rs1]) :: aR;
- if (rd == 0) then () else oR = RFull(GPRstr[rd]) :: oR;
+ if (rs2 == 0b00000) then () else iR = RFull(GPRstr(rs2)) :: iR;
+ if (rs1 == 0b00000) then () else iR = RFull(GPRstr(rs1)) :: iR;
+ if (rs1 == 0b00000) then () else aR = RFull(GPRstr(rs1)) :: aR;
+ if (rd == 0b00000) then () else oR = RFull(GPRstr(rd)) :: oR;
ik = match (aq, rl) {
(false, false) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional),
(false, true) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release),
@@ -180,3 +355,5 @@ function initial_analysis (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,inst
};
(iR,oR,aR,Nias,Dia,ik)
}
+
+$endif
diff --git a/model/riscv_csr_ext.sail b/model/riscv_csr_ext.sail
index ea4f065..8c0cc17 100644
--- a/model/riscv_csr_ext.sail
+++ b/model/riscv_csr_ext.sail
@@ -1,20 +1,13 @@
-/* Extensions may want to add additional CSR registers to the CSR address map.
- * These functions support access to such registers.
- *
- * The default implementation provides access to the CSRs added by the 'N'
- * extension.
- */
-/* returns whether a CSR is defined and accessible at a given address
- * and privilege
- */
-function ext_is_CSR_defined(csr : csreg, p : Privilege) -> bool =
- is_NExt_CSR_defined(csr, p) // 'N' extension
+/* numeric fallback XXX apparent sail bug prevents this from compiling for C */
+//mapping clause csr_name_map = reg <-> "UNKNOWN CSR: " ^ hex_bits_12(reg)
+end csr_name_map
-/* returns the value of the CSR if it is defined */
-function ext_read_CSR(csr : csreg) -> option(xlenbits) =
- read_NExt_CSR(csr)
+function clause ext_is_CSR_defined(_, _) = false
+end ext_is_CSR_defined
-/* returns false if the CSR is not defined or if the write is unsuccessful */
-function ext_write_CSR(csr : csreg, value : xlenbits) -> bool =
- write_NExt_CSR(csr, value)
+function clause ext_read_CSR _ = None()
+end ext_read_CSR
+
+function clause ext_write_CSR (_, _) = None()
+end ext_write_CSR
diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index f484d8d..7ec161b 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -1,172 +1,119 @@
/* Mapping of csr addresses to their names. */
-val cast csr_name : csreg -> string
-function csr_name(csr) = {
- match (csr) {
- /* user trap setup */
- 0x000 => "ustatus",
- 0x004 => "uie",
- 0x005 => "utvec",
- /* user trap handling */
- 0x040 => "uscratch",
- 0x041 => "uepc",
- 0x042 => "ucause",
- 0x043 => "utval",
- 0x044 => "uip",
+val csr_name_map : csreg <-> string
+scattered mapping csr_name_map
- /* user floating-point context */
- 0x001 => "fflags",
- 0x002 => "frm",
- 0x003 => "fcsr",
- /* counter/timers */
- 0xC00 => "cycle",
- 0xC01 => "time",
- 0xC02 => "instret",
- 0xC80 => "cycleh",
- 0xC81 => "timeh",
- 0xC82 => "instreth",
- /* TODO: other hpm counters */
- /* supervisor trap setup */
- 0x100 => "sstatus",
- 0x102 => "sedeleg",
- 0x103 => "sideleg",
- 0x104 => "sie",
- 0x105 => "stvec",
- 0x106 => "scounteren",
- /* supervisor trap handling */
- 0x140 => "sscratch",
- 0x141 => "sepc",
- 0x142 => "scause",
- 0x143 => "stval",
- 0x144 => "sip",
- /* supervisor protection and translation */
- 0x180 => "satp",
- /* machine information registers */
- 0xF11 => "mvendorid",
- 0xF12 => "marchid",
- 0xF13 => "mimpid",
- 0xF14 => "mhartid",
- /* machine trap setup */
- 0x300 => "mstatus",
- 0x301 => "misa",
- 0x302 => "medeleg",
- 0x303 => "mideleg",
- 0x304 => "mie",
- 0x305 => "mtvec",
- 0x306 => "mcounteren",
- /* machine trap handling */
- 0x340 => "mscratch",
- 0x341 => "mepc",
- 0x342 => "mcause",
- 0x343 => "mtval",
- 0x344 => "mip",
+/* user trap setup */
+mapping clause csr_name_map = 0x000 <-> "ustatus"
+mapping clause csr_name_map = 0x004 <-> "uie"
+mapping clause csr_name_map = 0x005 <-> "utvec"
+/* user trap handling */
+mapping clause csr_name_map = 0x040 <-> "uscratch"
+mapping clause csr_name_map = 0x041 <-> "uepc"
+mapping clause csr_name_map = 0x042 <-> "ucause"
+mapping clause csr_name_map = 0x043 <-> "utval"
+mapping clause csr_name_map = 0x044 <-> "uip"
+/* user floating-point context */
+mapping clause csr_name_map = 0x001 <-> "fflags"
+mapping clause csr_name_map = 0x002 <-> "frm"
+mapping clause csr_name_map = 0x003 <-> "fcsr"
+/* counter/timers */
+mapping clause csr_name_map = 0xC00 <-> "cycle"
+mapping clause csr_name_map = 0xC01 <-> "time"
+mapping clause csr_name_map = 0xC02 <-> "instret"
+mapping clause csr_name_map = 0xC80 <-> "cycleh"
+mapping clause csr_name_map = 0xC81 <-> "timeh"
+mapping clause csr_name_map = 0xC82 <-> "instreth"
+/* TODO: other hpm counters */
+/* supervisor trap setup */
+mapping clause csr_name_map = 0x100 <-> "sstatus"
+mapping clause csr_name_map = 0x102 <-> "sedeleg"
+mapping clause csr_name_map = 0x103 <-> "sideleg"
+mapping clause csr_name_map = 0x104 <-> "sie"
+mapping clause csr_name_map = 0x105 <-> "stvec"
+mapping clause csr_name_map = 0x106 <-> "scounteren"
+/* supervisor trap handling */
+mapping clause csr_name_map = 0x140 <-> "sscratch"
+mapping clause csr_name_map = 0x141 <-> "sepc"
+mapping clause csr_name_map = 0x142 <-> "scause"
+mapping clause csr_name_map = 0x143 <-> "stval"
+mapping clause csr_name_map = 0x144 <-> "sip"
+/* supervisor protection and translation */
+mapping clause csr_name_map = 0x180 <-> "satp"
+/* machine information registers */
+mapping clause csr_name_map = 0xF11 <-> "mvendorid"
+mapping clause csr_name_map = 0xF12 <-> "marchid"
+mapping clause csr_name_map = 0xF13 <-> "mimpid"
+mapping clause csr_name_map = 0xF14 <-> "mhartid"
+/* machine trap setup */
+mapping clause csr_name_map = 0x300 <-> "mstatus"
+mapping clause csr_name_map = 0x301 <-> "misa"
+mapping clause csr_name_map = 0x302 <-> "medeleg"
+mapping clause csr_name_map = 0x303 <-> "mideleg"
+mapping clause csr_name_map = 0x304 <-> "mie"
+mapping clause csr_name_map = 0x305 <-> "mtvec"
+mapping clause csr_name_map = 0x306 <-> "mcounteren"
+/* machine trap handling */
+mapping clause csr_name_map = 0x340 <-> "mscratch"
+mapping clause csr_name_map = 0x341 <-> "mepc"
+mapping clause csr_name_map = 0x342 <-> "mcause"
+mapping clause csr_name_map = 0x343 <-> "mtval"
+mapping clause csr_name_map = 0x344 <-> "mip"
+/* machine protection and translation */
+mapping clause csr_name_map = 0x3A0 <-> "pmpcfg0"
+mapping clause csr_name_map = 0x3A1 <-> "pmpcfg1"
+mapping clause csr_name_map = 0x3A2 <-> "pmpcfg2"
+mapping clause csr_name_map = 0x3A3 <-> "pmpcfg3"
+mapping clause csr_name_map = 0x3B0 <-> "pmpaddr0"
+mapping clause csr_name_map = 0x3B1 <-> "pmpaddr1"
+mapping clause csr_name_map = 0x3B2 <-> "pmpaddr2"
+mapping clause csr_name_map = 0x3B3 <-> "pmpaddr3"
+mapping clause csr_name_map = 0x3B4 <-> "pmpaddr4"
+mapping clause csr_name_map = 0x3B5 <-> "pmpaddr5"
+mapping clause csr_name_map = 0x3B6 <-> "pmpaddr6"
+mapping clause csr_name_map = 0x3B7 <-> "pmpaddr7"
+mapping clause csr_name_map = 0x3B8 <-> "pmpaddr8"
+mapping clause csr_name_map = 0x3B9 <-> "pmpaddr9"
+mapping clause csr_name_map = 0x3BA <-> "pmpaddr10"
+mapping clause csr_name_map = 0x3BB <-> "pmpaddr11"
+mapping clause csr_name_map = 0x3BC <-> "pmpaddr12"
+mapping clause csr_name_map = 0x3BD <-> "pmpaddr13"
+mapping clause csr_name_map = 0x3BE <-> "pmpaddr14"
+mapping clause csr_name_map = 0x3BF <-> "pmpaddr15"
+/* machine counters/timers */
+mapping clause csr_name_map = 0xB00 <-> "mcycle"
+mapping clause csr_name_map = 0xB02 <-> "minstret"
+mapping clause csr_name_map = 0xB80 <-> "mcycleh"
+mapping clause csr_name_map = 0xB82 <-> "minstreth"
+/* TODO: other hpm counters and events */
+/* trigger/debug */
+mapping clause csr_name_map = 0x7a0 <-> "tselect"
+mapping clause csr_name_map = 0x7a1 <-> "tdata1"
+mapping clause csr_name_map = 0x7a2 <-> "tdata2"
+mapping clause csr_name_map = 0x7a3 <-> "tdata3"
- 0x3A0 => "pmpcfg0",
- 0x3B0 => "pmpaddr0",
- /* TODO: machine protection and translation */
- /* machine counters/timers */
- 0xB00 => "mcycle",
- 0xB02 => "minstret",
- 0xB80 => "mcycleh",
- 0xB82 => "minstreth",
- /* TODO: other hpm counters and events */
- /* trigger/debug */
- 0x7a0 => "tselect",
- _ => "UNKNOWN"
- }
-}
+val csr_name : csreg -> string
+function csr_name(csr) = csr_name_map(csr)
+overload to_str = {csr_name}
-mapping csr_name_map : csreg <-> string = {
- /* user trap setup */
- 0x000 <-> "ustatus",
- 0x004 <-> "uie",
- 0x005 <-> "utvec",
- /* user trap handling */
- 0x040 <-> "uscratch",
- 0x041 <-> "uepc",
- 0x042 <-> "ucause",
- 0x043 <-> "utval",
- 0x044 <-> "uip",
- /* user floating-point context */
- 0x001 <-> "fflags",
- 0x002 <-> "frm",
- 0x003 <-> "fcsr",
- /* counter/timers */
- 0xC00 <-> "cycle",
- 0xC01 <-> "time",
- 0xC02 <-> "instret",
- 0xC80 <-> "cycleh",
- 0xC81 <-> "timeh",
- 0xC82 <-> "instreth",
- /* TODO: other hpm counters */
- /* supervisor trap setup */
- 0x100 <-> "sstatus",
- 0x102 <-> "sedeleg",
- 0x103 <-> "sideleg",
- 0x104 <-> "sie",
- 0x105 <-> "stvec",
- 0x106 <-> "scounteren",
- /* supervisor trap handling */
- 0x140 <-> "sscratch",
- 0x141 <-> "sepc",
- 0x142 <-> "scause",
- 0x143 <-> "stval",
- 0x144 <-> "sip",
- /* supervisor protection and translation */
- 0x180 <-> "satp",
- /* machine information registers */
- 0xF11 <-> "mvendorid",
- 0xF12 <-> "marchid",
- 0xF13 <-> "mimpid",
- 0xF14 <-> "mhartid",
- /* machine trap setup */
- 0x300 <-> "mstatus",
- 0x301 <-> "misa",
- 0x302 <-> "medeleg",
- 0x303 <-> "mideleg",
- 0x304 <-> "mie",
- 0x305 <-> "mtvec",
- 0x306 <-> "mcounteren",
- /* machine trap handling */
- 0x340 <-> "mscratch",
- 0x341 <-> "mepc",
- 0x342 <-> "mcause",
- 0x343 <-> "mtval",
- 0x344 <-> "mip",
- /* machine protection and translation */
- 0x3A0 <-> "pmpcfg0",
- 0x3A1 <-> "pmpcfg1",
- 0x3A2 <-> "pmpcfg2",
- 0x3A3 <-> "pmpcfg3",
- 0x3B0 <-> "pmpaddr0",
- 0x3B1 <-> "pmpaddr1",
- 0x3B2 <-> "pmpaddr2",
- 0x3B3 <-> "pmpaddr3",
- 0x3B4 <-> "pmpaddr4",
- 0x3B5 <-> "pmpaddr5",
- 0x3B6 <-> "pmpaddr6",
- 0x3B7 <-> "pmpaddr7",
- 0x3B8 <-> "pmpaddr8",
- 0x3B9 <-> "pmpaddr9",
- 0x3BA <-> "pmpaddr10",
- 0x3BB <-> "pmpaddr11",
- 0x3BC <-> "pmpaddr12",
- 0x3BD <-> "pmpaddr13",
- 0x3BE <-> "pmpaddr14",
- 0x3BF <-> "pmpaddr15",
- /* machine counters/timers */
- 0xB00 <-> "mcycle",
- 0xB02 <-> "minstret",
- 0xB80 <-> "mcycleh",
- 0xB82 <-> "minstreth",
- /* TODO: other hpm counters and events */
- /* trigger/debug */
- 0x7a0 <-> "tselect",
- 0x7a1 <-> "tdata1",
- 0x7a2 <-> "tdata2",
- 0x7a3 <-> "tdata3"
+/* Extensions may want to add additional CSR registers to the CSR address map.
+ * These scattered functions support access to such registers.
+ *
+ * The default implementation provides access to the CSRs added by the 'N'
+ * extension.
+ */
- /* numeric fallback */
- /* reg <-> hex_bits_12(reg) */
- }
+/* returns whether a CSR is defined and accessible at a given address
+ * and privilege
+ */
+val ext_is_CSR_defined : (csreg, Privilege) -> bool effect {rreg}
+scattered function ext_is_CSR_defined
+
+/* returns the value of the CSR if it is defined */
+val ext_read_CSR : csreg -> option(xlenbits) effect {rreg}
+scattered function ext_read_CSR
+
+/* returns new value (after legalisation) if the CSR is defined */
+val ext_write_CSR : (csreg, xlenbits) -> option(xlenbits) effect {rreg, wreg}
+scattered function ext_write_CSR \ No newline at end of file
diff --git a/model/riscv_duopod.sail b/model/riscv_duopod.sail
index 99dbbba..395a332 100644
--- a/model/riscv_duopod.sail
+++ b/model/riscv_duopod.sail
@@ -1,14 +1,10 @@
// This file depends on the xlen definitions in riscv_xlen.sail.
-type regno ('n : Int), 0 <= 'n < 32 = atom('n)
type regbits = bits(5)
val zeros : forall 'n, 'n >= 0. atom('n) -> bits('n)
function zeros n = replicate_bits(0b0, n)
-val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)}
-function regbits_to_regno b = let r as atom(_) = unsigned(b) in r
-
/* Architectural state */
register PC : xlenbits
@@ -17,28 +13,30 @@ register nextPC : xlenbits
register Xs : vector(32, dec, xlenbits)
/* Getters and setters for X registers (special case for zeros register, x0) */
-val rX : forall 'n, 0 <= 'n < 32. regno('n) -> xlenbits effect {rreg}
+val rX : regbits -> xlenbits effect {rreg}
-function rX 0 = EXTZ(0x0)
-and rX (r if r > 0) = Xs[r]
+function rX(r) =
+ match r {
+ 0b00000 => EXTZ(0x0),
+ _ => Xs[unsigned(r)]
+ }
-val wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg}
+val wX : (regbits, xlenbits) -> unit effect {wreg}
function wX (r, v) =
- if r != 0 then {
- Xs[r] = v;
+ if r != 0b00000 then {
+ Xs[unsigned(r)] = v;
}
overload X = {rX, wX}
/* Accessors for memory */
+val MEMr = { lem: "MEMr", coq: "MEMr", _ : "read_ram" } : forall 'n 'm, 'n >= 0.
+ (atom('m), int('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
-val MEMr : forall 'n, 'n >= 0. (xlenbits, atom('n)) -> bits(8 * 'n) effect {rmem}
-function MEMr (addr, width) =
- match __RISCV_read(addr, width, false, false, false) {
- Some(v) => v,
- None() => zeros(8 * width)
- }
+val read_mem : forall 'n, 'n >= 0. (xlenbits, int('n)) -> bits(8 * 'n) effect {rmem}
+function read_mem(addr, width) =
+ MEMr(sizeof(xlen), width, EXTZ(0x0), addr)
/* Instruction decode and execute */
enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI}
@@ -73,7 +71,7 @@ function clause decode imm : bits(12) @ rs1 : regbits @ 0b011 @ rd : regbits @ 0
function clause execute(LOAD(imm, rs1, rd)) =
let addr : xlenbits = X(rs1) + EXTS(imm) in
- let result : xlenbits = MEMr(addr, xlen_bytes) in
+ let result : xlenbits = read_mem(addr, sizeof(xlen_bytes)) in
X(rd) = result
/* ****************************************************************** */
diff --git a/model/riscv_ext_regs.sail b/model/riscv_ext_regs.sail
index 55600af..9ff83b3 100644
--- a/model/riscv_ext_regs.sail
+++ b/model/riscv_ext_regs.sail
@@ -4,3 +4,11 @@
val ext_init_regs : unit -> unit effect {wreg}
function ext_init_regs () = ()
+
+/*!
+This function is called after above when running rvfi and allows the model
+to be initialised differently (e.g. CHERI cap regs are initialised
+to omnipotent instead of null).
+ */
+val ext_rvfi_init : unit -> unit effect {wreg}
+function ext_rvfi_init () = ()
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
index 2cc9ea2..64aff4b 100644
--- a/model/riscv_fetch.sail
+++ b/model/riscv_fetch.sail
@@ -12,17 +12,17 @@ function fetch() -> FetchResult =
match ext_fetch_check_pc(PC, PC) {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc) => {
- if (use_pc[0] != 0b0 | (use_pc[1] != 0b0 & (~ (haveRVC()))))
- then F_Error(E_Fetch_Addr_Align, PC)
- else match translateAddr(use_pc, Execute, Instruction) {
- TR_Failure(e) => F_Error(e, PC),
- TR_Address(ppclo) => {
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & (~ (haveRVC()))))
+ then F_Error(E_Fetch_Addr_Align(), PC)
+ else match translateAddr(use_pc, Execute()) {
+ TR_Failure(e, _) => F_Error(e, PC),
+ TR_Address(ppclo, _) => {
/* split instruction fetch into 16-bit granules to handle RVC, as
* well as to generate precise fault addresses in any fetch
* exceptions.
*/
- match checked_mem_read(Instruction, ppclo, 2, false, false, false) {
- MemException(e) => F_Error(E_Fetch_Access_Fault, PC),
+ match mem_read(Execute(), ppclo, 2, false, false, false) {
+ MemException(e) => F_Error(E_Fetch_Access_Fault(), PC),
MemValue(ilo) => {
if isRVC(ilo)
then F_RVC(ilo)
@@ -32,11 +32,11 @@ function fetch() -> FetchResult =
match ext_fetch_check_pc(PC, PC_hi) {
Ext_FetchAddr_Error(e) => F_Ext_Error(e),
Ext_FetchAddr_OK(use_pc_hi) => {
- match translateAddr(use_pc_hi, Execute, Instruction) {
- TR_Failure(e) => F_Error(e, PC_hi),
- TR_Address(ppchi) => {
- match checked_mem_read(Instruction, ppchi, 2, false, false, false) {
- MemException(e) => F_Error(E_Fetch_Access_Fault, PC_hi),
+ match translateAddr(use_pc_hi, Execute()) {
+ TR_Failure(e, _) => F_Error(e, PC_hi),
+ TR_Address(ppchi, _) => {
+ match mem_read(Execute(), ppchi, 2, false, false, false) {
+ MemException(e) => F_Error(E_Fetch_Access_Fault(), PC_hi),
MemValue(ihi) => F_Base(append(ihi, ilo))
}
}
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
index 822305a..0f2ed4b 100644
--- a/model/riscv_fetch_rvfi.sail
+++ b/model/riscv_fetch_rvfi.sail
@@ -1,21 +1,33 @@
-function fetch() -> FetchResult =
- /* check for legal PC */
- if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC()))))
- then F_Error(E_Fetch_Addr_Align, PC)
- else {
- let i = rvfi_instruction.rvfi_insn();
- rvfi_exec->rvfi_order() = minstret;
- rvfi_exec->rvfi_pc_rdata() = EXTS(PC);
- rvfi_exec->rvfi_insn() = EXTS(i);
+function fetch() -> FetchResult = {
+ rvfi_exec->rvfi_order() = minstret;
+ rvfi_exec->rvfi_pc_rdata() = EXTZ(get_arch_pc());
- /* TODO: should we write these even if they're not really registers? */
- rvfi_exec->rvfi_rs1_data() = EXTS(X(i[19 .. 15]));
- rvfi_exec->rvfi_rs2_data() = EXTS(X(i[24 .. 20]));
- rvfi_exec->rvfi_rs1_addr() = sail_zero_extend(i[19 .. 15],8);
- rvfi_exec->rvfi_rs2_addr() = sail_zero_extend(i[24 .. 20],8);
-
- if (i[1 .. 0] == 0b11)
- then F_Base(i)
- else F_RVC(i[15 .. 0])
+ /* First allow extensions to check pc */
+ match ext_fetch_check_pc(PC, PC) {
+ Ext_FetchAddr_Error(e) => F_Ext_Error(e),
+ Ext_FetchAddr_OK(use_pc) => {
+ /* then check PC alignment */
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & (~ (haveRVC()))))
+ then F_Error(E_Fetch_Addr_Align(), PC)
+ else {
+ let i = rvfi_instruction.rvfi_insn();
+ rvfi_exec->rvfi_insn() = EXTZ(i);
+ /* TODO: should we write these even if they're not really registers? */
+ rvfi_exec->rvfi_rs1_data() = EXTZ(X(i[19 .. 15]));
+ rvfi_exec->rvfi_rs2_data() = EXTZ(X(i[24 .. 20]));
+ rvfi_exec->rvfi_rs1_addr() = sail_zero_extend(i[19 .. 15],8);
+ rvfi_exec->rvfi_rs2_addr() = sail_zero_extend(i[24 .. 20],8);
+ if (i[1 .. 0] != 0b11)
+ then F_RVC(i[15 .. 0])
+ else {
+ /* fetch PC check for the next instruction granule */
+ PC_hi : xlenbits = PC + 2;
+ match ext_fetch_check_pc(PC, PC_hi) {
+ Ext_FetchAddr_Error(e) => F_Ext_Error(e),
+ Ext_FetchAddr_OK(use_pc_hi) => F_Base(i)
+ }
+ }
+ }
+ }
}
-
+}
diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
index 1ba280d..7eb01c5 100644
--- a/model/riscv_insts_aext.sail
+++ b/model/riscv_insts_aext.sail
@@ -44,7 +44,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
/* Get the address, X(rs1) (no offset).
* Extensions might perform additional checks on address validity.
*/
- match ext_data_get_addr(rs1, zeros(), Read, Data, width) {
+ match ext_data_get_addr(rs1, zeros(), Read(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) => {
let aligned : bool =
@@ -53,7 +53,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
*/
match width {
BYTE => true,
- HALF => vaddr[0] == 0b0,
+ HALF => vaddr[0..0] == 0b0,
WORD => vaddr[1..0] == 0b00,
DOUBLE => vaddr[2..0] == 0b000
};
@@ -61,13 +61,13 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
* - Andrew Waterman, isa-dev, 10 Jul 2018.
*/
if (~ (aligned))
- then { handle_mem_exception(vaddr, E_Load_Addr_Align); RETIRE_FAIL }
- else match translateAddr(vaddr, Read, Data) {
- TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr) =>
+ then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
+ else match translateAddr(vaddr, Read(Data)) {
+ TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+ TR_Address(addr, _) =>
match (width, sizeof(xlen)) {
- (WORD, _) => process_loadres(rd, vaddr, mem_read(addr, 4, aq, rl, true), false),
- (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(addr, 8, aq, rl, true), false),
+ (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, true), false),
+ (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, true), false),
_ => internal_error("LOADRES expected WORD or DOUBLE")
}
}
@@ -103,7 +103,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
/* Get the address, X(rs1) (no offset).
* Extensions might perform additional checks on address validity.
*/
- match ext_data_get_addr(rs1, zeros(), Read, Data, width) {
+ match ext_data_get_addr(rs1, zeros(), Write(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) => {
let aligned : bool =
@@ -112,20 +112,21 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
*/
match width {
BYTE => true,
- HALF => vaddr[0] == 0b0,
+ HALF => vaddr[0..0] == 0b0,
WORD => vaddr[1..0] == 0b00,
DOUBLE => vaddr[2..0] == 0b000
};
if (~ (aligned))
- then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); RETIRE_FAIL }
+ then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
else {
if match_reservation(vaddr) == false then {
/* cannot happen in rmem */
X(rd) = EXTZ(0b1); cancel_reservation(); RETIRE_SUCCESS
} else {
- match translateAddr(vaddr, Write, Data) {
- TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr) => {
+ match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here:
+ * both result in a SAMO exception */
+ TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+ TR_Address(addr, _) => {
let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
(WORD, _) => mem_write_ea(addr, 4, aq, rl, true),
(DOUBLE, 64) => mem_write_ea(addr, 8, aq, rl, true),
@@ -188,12 +189,12 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
/* Get the address, X(rs1) (no offset).
* Some extensions perform additional checks on address validity.
*/
- match ext_data_get_addr(rs1, zeros(), Read, Data, width) {
+ match ext_data_get_addr(rs1, zeros(), ReadWrite(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) => {
- match translateAddr(vaddr, ReadWrite, Data) {
- TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr) => {
+ match translateAddr(vaddr, ReadWrite(Data)) {
+ TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+ TR_Address(addr, _) => {
let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
(WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),
(DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),
@@ -204,8 +205,8 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
MemException(e) => { handle_mem_exception(addr, e); RETIRE_FAIL },
MemValue(_) => {
let rval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {
- (WORD, _) => extend_value(false, mem_read(addr, 4, aq, aq & rl, true)),
- (DOUBLE, 64) => extend_value(false, mem_read(addr, 8, aq, aq & rl, true)),
+ (WORD, _) => extend_value(false, mem_read(ReadWrite(Data), addr, 4, aq, aq & rl, true)),
+ (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data), addr, 8, aq, aq & rl, true)),
_ => internal_error ("AMO expected WORD or DOUBLE")
};
match (rval) {
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
index ae4c885..d80d34d 100644
--- a/model/riscv_insts_base.sail
+++ b/model/riscv_insts_base.sail
@@ -17,7 +17,7 @@ function clause execute UTYPE(imm, rd, op) = {
let off : xlenbits = EXTS(imm @ 0x000);
let ret : xlenbits = match op {
RISCV_LUI => off,
- RISCV_AUIPC => PC + off
+ RISCV_AUIPC => get_arch_pc() + off
};
X(rd) = ret;
RETIRE_SUCCESS
@@ -59,9 +59,9 @@ function clause execute (RISCV_JAL(imm, rd)) = {
},
Ext_ControlAddr_OK(target) => {
/* Perform standard alignment check */
- if target[1] & (~ (haveRVC()))
+ if bit_to_bool(target[1]) & (~ (haveRVC()))
then {
- handle_mem_exception(target, E_Fetch_Addr_Align);
+ handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
} else {
X(rd) = get_next_pc();
@@ -123,8 +123,8 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = {
RETIRE_FAIL
},
Ext_ControlAddr_OK(target) => {
- if target[1] & (~ (haveRVC())) then {
- handle_mem_exception(target, E_Fetch_Addr_Align);
+ if bit_to_bool(target[1]) & (~ (haveRVC())) then {
+ handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL;
} else {
set_next_pc(target);
@@ -167,8 +167,8 @@ function clause execute (ITYPE (imm, rs1, rd, op)) = {
let immext : xlenbits = EXTS(imm);
let result : xlenbits = match op {
RISCV_ADDI => rs1_val + immext,
- RISCV_SLTI => EXTZ(rs1_val <_s immext),
- RISCV_SLTIU => EXTZ(rs1_val <_u immext),
+ RISCV_SLTI => EXTZ(bool_to_bits(rs1_val <_s immext)),
+ RISCV_SLTIU => EXTZ(bool_to_bits(rs1_val <_u immext)),
RISCV_ANDI => rs1_val & immext,
RISCV_ORI => rs1_val | immext,
RISCV_XORI => rs1_val ^ immext
@@ -198,9 +198,9 @@ mapping encdec_sop : sop <-> bits(3) = {
RISCV_SRAI <-> 0b101
}
-mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == false
-mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == false
-mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == false
+mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
+mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
+mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = {
let rs1_val = X(rs1);
@@ -248,8 +248,8 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) = {
let rs2_val = X(rs2);
let result : xlenbits = match op {
RISCV_ADD => rs1_val + rs2_val,
- RISCV_SLT => EXTZ(rs1_val <_s rs2_val),
- RISCV_SLTU => EXTZ(rs1_val <_u rs2_val),
+ RISCV_SLT => EXTZ(bool_to_bits(rs1_val <_s rs2_val)),
+ RISCV_SLTU => EXTZ(bool_to_bits(rs1_val <_u rs2_val)),
RISCV_AND => rs1_val & rs2_val,
RISCV_OR => rs1_val | rs2_val,
RISCV_XOR => rs1_val ^ rs2_val,
@@ -287,7 +287,7 @@ mapping clause assembly = RTYPE(rs2, rs1, rd, op)
/* ****************************************************************** */
union clause ast = LOAD : (bits(12), regidx, regidx, bool, word_width, bool, bool)
-/* unsigned loads are only present for widths strictly less than xlen,
+/* unsigned loads are only present for widths strictly less than xlen,
signed loads also present for widths equal to xlen */
mapping clause encdec = LOAD(imm, rs1, rd, is_unsigned, size, false, false) if (word_width_bytes(size) < sizeof(xlen_bytes)) | (not_bool(is_unsigned) & word_width_bytes(size) <= sizeof(xlen_bytes))
<-> imm @ rs1 @ bool_bits(is_unsigned) @ size_bits(size) @ rd @ 0b0000011 if (word_width_bytes(size) < sizeof(xlen_bytes)) | (not_bool(is_unsigned) & word_width_bytes(size) <= sizeof(xlen_bytes))
@@ -309,32 +309,32 @@ function check_misaligned(vaddr : xlenbits, width : word_width) -> bool =
if plat_enable_misaligned_access() then false
else match width {
BYTE => false,
- HALF => vaddr[0] == true,
- WORD => vaddr[0] == true | vaddr[1] == true,
- DOUBLE => vaddr[0] == true | vaddr[1] == true | vaddr[2] == true
+ HALF => vaddr[0] == bitone,
+ WORD => vaddr[0] == bitone | vaddr[1] == bitone,
+ DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone
}
function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {
let offset : xlenbits = EXTS(imm);
/* Get the address, X(rs1) + offset.
Some extensions perform additional checks on address validity. */
- match ext_data_get_addr(rs1, offset, Read, Data, width) {
+ match ext_data_get_addr(rs1, offset, Read(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) =>
if check_misaligned(vaddr, width)
- then { handle_mem_exception(vaddr, E_Load_Addr_Align); RETIRE_FAIL }
- else match translateAddr(vaddr, Read, Data) {
- TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr) =>
+ then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
+ else match translateAddr(vaddr, Read(Data)) {
+ TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+ TR_Address(addr, _) =>
match (width, sizeof(xlen)) {
(BYTE, _) =>
- process_load(rd, vaddr, mem_read(addr, 1, aq, rl, false), is_unsigned),
+ process_load(rd, vaddr, mem_read(Read(Data), addr, 1, aq, rl, false), is_unsigned),
(HALF, _) =>
- process_load(rd, vaddr, mem_read(addr, 2, aq, rl, false), is_unsigned),
+ process_load(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, false), is_unsigned),
(WORD, _) =>
- process_load(rd, vaddr, mem_read(addr, 4, aq, rl, false), is_unsigned),
+ process_load(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, false), is_unsigned),
(DOUBLE, 64) =>
- process_load(rd, vaddr, mem_read(addr, 8, aq, rl, false), is_unsigned)
+ process_load(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, false), is_unsigned)
}
}
}
@@ -373,14 +373,14 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = {
let offset : xlenbits = EXTS(imm);
/* Get the address, X(rs1) + offset.
Some extensions perform additional checks on address validity. */
- match ext_data_get_addr(rs1, offset, Write, Data, width) {
+ match ext_data_get_addr(rs1, offset, Write(Data), width) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_OK(vaddr) =>
if check_misaligned(vaddr, width)
- then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); RETIRE_FAIL }
- else match translateAddr(vaddr, Write, Data) {
- TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr) => {
+ then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
+ else match translateAddr(vaddr, Write(Data)) {
+ TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
+ TR_Address(addr, _) => {
let eares : MemoryOpResult(unit) = match width {
BYTE => mem_write_ea(addr, 1, aq, rl, false),
HALF => mem_write_ea(addr, 2, aq, rl, false),
@@ -564,6 +564,31 @@ union clause ast = FENCE : (bits(4), bits(4))
mapping clause encdec = FENCE(pred, succ)
<-> 0b0000 @ pred @ succ @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111
+/* For future versions of Sail where barriers can be parameterised */
+$ifdef FEATURE_UNION_BARRIER
+
+function clause execute (FENCE(pred, succ)) = {
+ match (pred, succ) {
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_r_r()),
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_rw_w()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_w_w()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_w_rw()),
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()),
+ (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()),
+ (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()),
+
+ (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (),
+
+ _ => { print("FIXME: unsupported fence");
+ () }
+ };
+ RETIRE_SUCCESS
+}
+
+$else
+
function clause execute (FENCE(pred, succ)) = {
match (pred, succ) {
(_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw),
@@ -584,6 +609,8 @@ function clause execute (FENCE(pred, succ)) = {
RETIRE_SUCCESS
}
+$endif
+
mapping bit_maybe_r : bits(1) <-> string = {
0b1 <-> "r",
0b0 <-> ""
@@ -617,6 +644,21 @@ union clause ast = FENCE_TSO : (bits(4), bits(4))
mapping clause encdec = FENCE_TSO(pred, succ)
<-> 0b1000 @ pred @ succ @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111
+$ifdef FEATURE_UNION_BARRIER
+
+function clause execute (FENCE_TSO(pred, succ)) = {
+ match (pred, succ) {
+ (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_tso()),
+ (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (),
+
+ _ => { print("FIXME: unsupported fence");
+ () }
+ };
+ RETIRE_SUCCESS
+}
+
+$else
+
function clause execute (FENCE_TSO(pred, succ)) = {
match (pred, succ) {
(_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_tso),
@@ -628,6 +670,8 @@ function clause execute (FENCE_TSO(pred, succ)) = {
RETIRE_SUCCESS
}
+$endif
+
mapping clause assembly = FENCE_TSO(pred, succ)
<-> "fence.tso" ^ spc() ^ fence_bits(pred) ^ sep() ^ fence_bits(succ)
@@ -651,9 +695,9 @@ mapping clause encdec = ECALL()
function clause execute ECALL() = {
let t : sync_exception =
struct { trap = match (cur_privilege) {
- User => E_U_EnvCall,
- Supervisor => E_S_EnvCall,
- Machine => E_M_EnvCall
+ User => E_U_EnvCall(),
+ Supervisor => E_S_EnvCall(),
+ Machine => E_M_EnvCall()
},
excinfo = (None() : option(xlenbits)),
ext = None() };
@@ -687,7 +731,7 @@ mapping clause encdec = SRET()
function clause execute SRET() = {
match cur_privilege {
User => handle_illegal(),
- Supervisor => if (~ (haveSupMode ())) | mstatus.TSR() == true
+ Supervisor => if (~ (haveSupMode ())) | mstatus.TSR() == 0b1
then handle_illegal()
else set_next_pc(exception_handler(cur_privilege, CTL_SRET(), PC)),
Machine => if (~ (haveSupMode ()))
@@ -706,7 +750,7 @@ mapping clause encdec = EBREAK()
<-> 0b000000000001 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011
function clause execute EBREAK() = {
- handle_mem_exception(PC, E_Breakpoint);
+ handle_mem_exception(PC, E_Breakpoint());
RETIRE_FAIL
}
@@ -721,7 +765,7 @@ mapping clause encdec = WFI()
function clause execute WFI() =
match cur_privilege {
Machine => { platform_wfi(); RETIRE_SUCCESS },
- Supervisor => if mstatus.TW() == true
+ Supervisor => if mstatus.TW() == 0b1
then { handle_illegal(); RETIRE_FAIL }
else { platform_wfi(); RETIRE_SUCCESS },
User => { handle_illegal(); RETIRE_FAIL }
@@ -736,13 +780,13 @@ mapping clause encdec = SFENCE_VMA(rs1, rs2)
<-> 0b0001001 @ rs2 @ rs1 @ 0b000 @ 0b00000 @ 0b1110011
function clause execute SFENCE_VMA(rs1, rs2) = {
- let addr : option(xlenbits) = if rs1 == 0 then None() else Some(X(rs1));
- let asid : option(xlenbits) = if rs2 == 0 then None() else Some(X(rs2));
+ let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1));
+ let asid : option(xlenbits) = if rs2 == 0b00000 then None() else Some(X(rs2));
match cur_privilege {
User => { handle_illegal(); RETIRE_FAIL },
Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus.TVM()) {
- (Some(_), true) => { handle_illegal(); RETIRE_FAIL },
- (Some(_), false) => { flush_TLB(asid, addr); RETIRE_SUCCESS },
+ (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL },
+ (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS },
(_, _) => internal_error("unimplemented sfence architecture")
},
Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS }
diff --git a/model/riscv_insts_begin.sail b/model/riscv_insts_begin.sail
index b007246..b27711b 100644
--- a/model/riscv_insts_begin.sail
+++ b/model/riscv_insts_begin.sail
@@ -6,7 +6,7 @@
scattered union ast
/* returns whether an instruction was retired, used for computing minstret */
-val execute : ast -> Retired effect {escape, wreg, rreg, wmv, wmvt, eamem, rmem, barr, exmem}
+val execute : ast -> Retired effect {escape, wreg, rreg, wmv, wmvt, eamem, rmem, rmemt, barr, exmem, undef}
scattered function execute
val assembly : ast <-> string
diff --git a/model/riscv_insts_cext.sail b/model/riscv_insts_cext.sail
index c58c636..4f3d0c6 100644
--- a/model/riscv_insts_cext.sail
+++ b/model/riscv_insts_cext.sail
@@ -400,9 +400,9 @@ mapping clause assembly = C_BNEZ(imm, rs)
union clause ast = C_SLLI : (bits(6), regidx)
mapping clause encdec_compressed = C_SLLI(nzui5 @ nzui40, rsd)
- if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == false)
+ if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0)
<-> 0b000 @ nzui5 : bits(1) @ rsd : regidx @ nzui40 : bits(5) @ 0b10
- if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == false)
+ if nzui5 @ nzui40 != 0b000000 & rsd != zreg & (sizeof(xlen) == 64 | nzui5 == 0b0)
function clause execute (C_SLLI(shamt, rsd)) =
execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SLLI))
diff --git a/model/riscv_insts_end.sail b/model/riscv_insts_end.sail
index e52f19d..f6223dd 100644
--- a/model/riscv_insts_end.sail
+++ b/model/riscv_insts_end.sail
@@ -29,9 +29,11 @@ end assembly
end encdec
end encdec_compressed
-val cast print_insn : ast -> string
+val print_insn : ast -> string
function print_insn insn = assembly(insn)
+overload to_str = {print_insn}
+
val decode : bits(32) -> ast effect pure
function decode bv = encdec(bv)
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 9a2cf9f..dd8a4a0 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -34,8 +34,27 @@ function readCSR csr : csreg -> xlenbits = {
(0x343, _) => mtval,
(0x344, _) => mip.bits(),
- (0x3A0, _) => pmpcfg0,
+ (0x3A0, _) => pmpReadCfgReg(0), // pmpcfg0
+ (0x3A1, 32) => pmpReadCfgReg(1), // pmpcfg1
+ (0x3A2, _) => pmpReadCfgReg(2), // pmpcfg2
+ (0x3A3, 32) => pmpReadCfgReg(3), // pmpcfg3
+
(0x3B0, _) => pmpaddr0,
+ (0x3B1, _) => pmpaddr1,
+ (0x3B2, _) => pmpaddr2,
+ (0x3B3, _) => pmpaddr3,
+ (0x3B4, _) => pmpaddr4,
+ (0x3B5, _) => pmpaddr5,
+ (0x3B6, _) => pmpaddr6,
+ (0x3B7, _) => pmpaddr7,
+ (0x3B8, _) => pmpaddr8,
+ (0x3B9, _) => pmpaddr9,
+ (0x3BA, _) => pmpaddr10,
+ (0x3BB, _) => pmpaddr11,
+ (0x3BC, _) => pmpaddr12,
+ (0x3BD, _) => pmpaddr13,
+ (0x3BE, _) => pmpaddr14,
+ (0x3BF, _) => pmpaddr15,
/* machine mode counters */
(0xB00, _) => mcycle[(sizeof(xlen) - 1) .. 0],
@@ -75,7 +94,8 @@ function readCSR csr : csreg -> xlenbits = {
EXTZ(0x0) }
}
};
- print_reg("CSR " ^ csr ^ " -> " ^ BitStr(res));
+ if get_config_print_reg()
+ then print_reg("CSR " ^ to_str(csr) ^ " -> " ^ BitStr(res));
res
}
@@ -96,8 +116,28 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
(0x343, _) => { mtval = value; Some(mtval) },
(0x344, _) => { mip = legalize_mip(mip, value); Some(mip.bits()) },
- (0x3A0, _) => { pmpcfg0 = value; Some(pmpcfg0) }, /* FIXME: legalize */
- (0x3B0, _) => { pmpaddr0 = value; Some(pmpaddr0) }, /* FIXME: legalize */
+ // Note: Some(value) returned below is not the legalized value due to locked entries
+ (0x3A0, _) => { pmpWriteCfgReg(0, value); Some(value) }, // pmpcfg0
+ (0x3A1, 32) => { pmpWriteCfgReg(1, value); Some(value) }, // pmpcfg1
+ (0x3A2, _) => { pmpWriteCfgReg(2, value); Some(value) }, // pmpcfg2
+ (0x3A3, 32) => { pmpWriteCfgReg(3, value); Some(value) }, // pmpcfg3
+
+ (0x3B0, _) => { pmpaddr0 = pmpWriteAddr(pmp0cfg, pmpaddr0, value); Some(pmpaddr0) },
+ (0x3B1, _) => { pmpaddr1 = pmpWriteAddr(pmp1cfg, pmpaddr1, value); Some(pmpaddr1) },
+ (0x3B2, _) => { pmpaddr2 = pmpWriteAddr(pmp2cfg, pmpaddr2, value); Some(pmpaddr2) },
+ (0x3B3, _) => { pmpaddr3 = pmpWriteAddr(pmp3cfg, pmpaddr3, value); Some(pmpaddr3) },
+ (0x3B4, _) => { pmpaddr4 = pmpWriteAddr(pmp4cfg, pmpaddr4, value); Some(pmpaddr4) },
+ (0x3B5, _) => { pmpaddr5 = pmpWriteAddr(pmp5cfg, pmpaddr5, value); Some(pmpaddr5) },
+ (0x3B6, _) => { pmpaddr6 = pmpWriteAddr(pmp6cfg, pmpaddr6, value); Some(pmpaddr6) },
+ (0x3B7, _) => { pmpaddr7 = pmpWriteAddr(pmp7cfg, pmpaddr7, value); Some(pmpaddr7) },
+ (0x3B8, _) => { pmpaddr8 = pmpWriteAddr(pmp8cfg, pmpaddr8, value); Some(pmpaddr8) },
+ (0x3B9, _) => { pmpaddr9 = pmpWriteAddr(pmp9cfg, pmpaddr9, value); Some(pmpaddr9) },
+ (0x3BA, _) => { pmpaddr10 = pmpWriteAddr(pmp10cfg, pmpaddr10, value); Some(pmpaddr10) },
+ (0x3BB, _) => { pmpaddr11 = pmpWriteAddr(pmp11cfg, pmpaddr11, value); Some(pmpaddr11) },
+ (0x3BC, _) => { pmpaddr12 = pmpWriteAddr(pmp12cfg, pmpaddr12, value); Some(pmpaddr12) },
+ (0x3BD, _) => { pmpaddr13 = pmpWriteAddr(pmp13cfg, pmpaddr13, value); Some(pmpaddr13) },
+ (0x3BE, _) => { pmpaddr14 = pmpWriteAddr(pmp14cfg, pmpaddr14, value); Some(pmpaddr14) },
+ (0x3BF, _) => { pmpaddr15 = pmpWriteAddr(pmp15cfg, pmpaddr15, value); Some(pmpaddr15) },
/* machine mode counters */
(0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; Some(value) },
@@ -122,15 +162,12 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
(0x144, _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) },
(0x180, _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },
- _ => None()
+ _ => ext_write_CSR(csr, value)
};
match res {
- Some(v) => print_reg("CSR " ^ csr ^ " <- " ^ BitStr(v) ^ " (input: " ^ BitStr(value) ^ ")"),
- None() => { /* check extensions */
- if ext_write_CSR(csr, value)
- then ()
- else print_bits("unhandled write to CSR ", csr)
- }
+ Some(v) => if get_config_print_reg()
+ then print_reg("CSR " ^ to_str(csr) ^ " <- " ^ BitStr(v) ^ " (input: " ^ BitStr(value) ^ ")"),
+ None() => print_bits("unhandled write to CSR ", csr)
}
}
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail
index 5b37c78..6f04b69 100644
--- a/model/riscv_jalr_seq.sail
+++ b/model/riscv_jalr_seq.sail
@@ -15,10 +15,9 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = {
RETIRE_FAIL
},
Ext_ControlAddr_OK(addr) => {
- let target = [addr with 0 = bitzero]; /* clear addr[0] */
- if target[1] & (~ (haveRVC()))
- then {
- handle_mem_exception(target, E_Fetch_Addr_Align);
+ let target = [addr with 0 = bitzero]; /* clear addr[0] */
+ if bit_to_bool(target[1]) & ~(haveRVC()) then {
+ handle_mem_exception(target, E_Fetch_Addr_Align());
RETIRE_FAIL
} else {
X(rd) = get_next_pc();
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail
index 6b9d46c..6d761c3 100644
--- a/model/riscv_mem.sail
+++ b/model/riscv_mem.sail
@@ -2,45 +2,70 @@
*
* This assumes that the platform memory map has been defined, so that accesses
* to MMIO regions can be dispatched.
+ *
+ * The implementation below supports the reading and writing of memory
+ * metadata in addition to raw memory data.
+ *
+ * The external API for this module is
+ * {mem_read, mem_write_ea, mem_write_value_meta, mem_write_value}
+ * where mem_write_value is a special case of mem_write_value_meta that uses
+ * a default value of the metadata.
+ *
+ * The internal implementation first performs a PMP check (if PMP is
+ * enabled), and then dispatches to MMIO regions or physical memory as
+ * per the platform memory map.
*/
function is_aligned_addr forall 'n. (addr : xlenbits, width : atom('n)) -> bool =
unsigned(addr) % width == 0
// only used for actual memory regions, to avoid MMIO effects
-function phys_mem_read forall 'n, 'n > 0. (t : ReadType, addr : xlenbits, width : atom('n), aq : bool, rl: bool, res : bool) -> MemoryOpResult(bits(8 * 'n)) = {
+function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), addr : xlenbits, width : atom('n), aq : bool, rl: bool, res : bool) -> MemoryOpResult(bits(8 * 'n)) = {
let result = (match (aq, rl, res) {
- (false, false, false) => Some(__read_mem(Read_plain, sizeof(xlen), addr, width)),
- (true, false, false) => Some(__read_mem(Read_RISCV_acquire, sizeof(xlen), addr, width)),
- (true, true, false) => Some(__read_mem(Read_RISCV_strong_acquire, sizeof(xlen), addr, width)),
- (false, false, true) => Some(__read_mem(Read_RISCV_reserved, sizeof(xlen), addr, width)),
- (true, false, true) => Some(__read_mem(Read_RISCV_reserved_acquire, sizeof(xlen), addr, width)),
- (true, true, true) => Some(__read_mem(Read_RISCV_reserved_strong_acquire, sizeof(xlen), addr, width)),
+ (false, false, false) => Some(read_ram(Read_plain, addr, width)),
+ (true, false, false) => Some(read_ram(Read_RISCV_acquire, addr, width)),
+ (true, true, false) => Some(read_ram(Read_RISCV_strong_acquire, addr, width)),
+ (false, false, true) => Some(read_ram(Read_RISCV_reserved, addr, width)),
+ (true, false, true) => Some(read_ram(Read_RISCV_reserved_acquire, addr, width)),
+ (true, true, true) => Some(read_ram(Read_RISCV_reserved_strong_acquire, addr, width)),
(false, true, false) => None(), /* should these be instead throwing error_not_implemented as below? */
(false, true, true) => None()
}) : option(bits(8 * 'n));
match (t, result) {
- (Instruction, None()) => MemException(E_Fetch_Access_Fault),
- (Data, None()) => MemException(E_Load_Access_Fault),
- (_, Some(v)) => { print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v));
- MemValue(v) }
+ (Execute(), None()) => MemException(E_Fetch_Access_Fault()),
+ (Read(Data), None()) => MemException(E_Load_Access_Fault()),
+ (_, None()) => MemException(E_SAMO_Access_Fault()),
+ (_, Some(v)) => { if get_config_print_mem()
+ then print_mem("mem[" ^ to_str(t) ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v));
+ MemValue(v) }
}
}
-function checked_mem_read forall 'n, 'n > 0. (t : ReadType, addr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool) -> MemoryOpResult(bits(8 * 'n)) =
- /* treat MMIO regions as not executable for now. TODO: this should actually come from PMP/PMA. */
- if t == Data & within_mmio_readable(addr, width)
+/* dispatches to MMIO regions or physical memory regions depending on physical memory map */
+function checked_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), addr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool) -> MemoryOpResult(bits(8 * 'n)) =
+ if within_mmio_readable(addr, width)
then mmio_read(addr, width)
else if within_phys_mem(addr, width)
then phys_mem_read(t, addr, width, aq, rl, res)
- else MemException(E_Load_Access_Fault)
+ else MemException(E_Load_Access_Fault())
+
+/* PMP checks if enabled */
+function pmp_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_access_type), addr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool) -> MemoryOpResult(bits(8 * 'n)) =
+ if (~ (plat_enable_pmp ()))
+ then checked_mem_read(t, addr, width, aq, rl, res)
+ else {
+ match pmpCheck(addr, width, t, effectivePrivilege(mstatus, cur_privilege)) {
+ None() => checked_mem_read(t, addr, width, aq, rl, res),
+ Some(e) => MemException(e)
+ }
+ }
/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
$ifdef RVFI_DII
val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit effect {wreg}
function rvfi_read (addr, width, result) = {
- rvfi_exec->rvfi_mem_addr() = EXTS(addr);
+ rvfi_exec->rvfi_mem_addr() = EXTZ(addr);
match result {
MemValue(v) => if width <= 8
then { rvfi_exec->rvfi_mem_rdata() = sail_zero_extend(v,64);
@@ -56,45 +81,45 @@ $endif
/* NOTE: The rreg effect is due to MMIO. */
$ifdef RVFI_DII
-val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {wreg, rmem, rreg, escape}
+val mem_read : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {wreg, rmem, rreg, escape}
$else
-val mem_read : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg, escape}
+val mem_read : forall 'n, 0 < 'n <= max_mem_access . (AccessType(ext_access_type), xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) effect {rmem, rreg, escape}
$endif
-function mem_read (addr, width, aq, rl, res) = {
+function mem_read (typ, addr, width, aq, rl, res) = {
let result : MemoryOpResult(bits(8 * 'n)) =
if (aq | res) & (~ (is_aligned_addr(addr, width)))
- then MemException(E_Load_Addr_Align)
+ then MemException(E_Load_Addr_Align())
else match (aq, rl, res) {
(false, true, false) => throw(Error_not_implemented("load.rl")),
(false, true, true) => throw(Error_not_implemented("lr.rl")),
- (_, _, _) => checked_mem_read(Data, addr, width, aq, rl, res)
+ (_, _, _) => pmp_mem_read(typ, addr, width, aq, rl, res)
};
rvfi_read(addr, width, result);
result
}
-val mem_write_ea : forall 'n, 'n > 0. (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(unit) effect {eamem, escape}
+val mem_write_ea : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bool, bool, bool) -> MemoryOpResult(unit) effect {eamem, escape}
function mem_write_ea (addr, width, aq, rl, con) = {
if (rl | con) & (~ (is_aligned_addr(addr, width)))
- then MemException(E_SAMO_Addr_Align)
+ then MemException(E_SAMO_Addr_Align())
else match (aq, rl, con) {
- (false, false, false) => MemValue(__write_mem_ea(Write_plain, sizeof(xlen), addr, width)),
- (false, true, false) => MemValue(__write_mem_ea(Write_RISCV_release, sizeof(xlen), addr, width)),
- (false, false, true) => MemValue(__write_mem_ea(Write_RISCV_conditional, sizeof(xlen), addr, width)),
- (false, true , true) => MemValue(__write_mem_ea(Write_RISCV_conditional_release, sizeof(xlen), addr, width)),
+ (false, false, false) => MemValue(write_ram_ea(Write_plain, addr, width)),
+ (false, true, false) => MemValue(write_ram_ea(Write_RISCV_release, addr, width)),
+ (false, false, true) => MemValue(write_ram_ea(Write_RISCV_conditional, addr, width)),
+ (false, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_release, addr, width)),
(true, false, false) => throw(Error_not_implemented("store.aq")),
- (true, true, false) => MemValue(__write_mem_ea(Write_RISCV_strong_release, sizeof(xlen), addr, width)),
+ (true, true, false) => MemValue(write_ram_ea(Write_RISCV_strong_release, addr, width)),
(true, false, true) => throw(Error_not_implemented("sc.aq")),
- (true, true , true) => MemValue(__write_mem_ea(Write_RISCV_conditional_strong_release, sizeof(xlen), addr, width))
+ (true, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_strong_release, addr, width))
}
}
$ifdef RVFI_DII
-val rvfi_write : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg}
+val rvfi_write : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg}
function rvfi_write (addr, width, value) = {
- rvfi_exec->rvfi_mem_addr() = EXTS(addr);
+ rvfi_exec->rvfi_mem_addr() = EXTZ(addr);
if width <= 8 then {
rvfi_exec->rvfi_mem_wdata() = sail_zero_extend(value,64);
rvfi_exec->rvfi_mem_wmask() = rvfi_encode_width_mask(width);
@@ -106,55 +131,57 @@ function rvfi_write (addr, width, value) = ()
$endif
// only used for actual memory regions, to avoid MMIO effects
-function phys_mem_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), data : bits(8 * 'n), meta : mem_meta, aq : bool, rl : bool, con : bool) -> MemoryOpResult(bool) = {
+function phys_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, addr : xlenbits, width : atom('n), data : bits(8 * 'n), meta : mem_meta) -> MemoryOpResult(bool) = {
rvfi_write(addr, width, data);
- let result = (match (aq, rl, con) {
- (false, false, false) => MemValue(write_ram(Write_plain, addr, width, data, meta)),
- (false, true, false) => MemValue(write_ram(Write_RISCV_release, addr, width, data, meta)),
- (false, false, true) => MemValue(write_ram(Write_RISCV_conditional, addr, width, data, meta)),
- (false, true , true) => MemValue(write_ram(Write_RISCV_conditional_release, addr, width, data, meta)),
- (true, false, false) => throw(Error_not_implemented("store.aq")),
- (true, true, false) => MemValue(write_ram(Write_RISCV_strong_release, addr, width, data, meta)),
- (true, false, true) => throw(Error_not_implemented("sc.aq")),
- (true, true , true) => MemValue(write_ram(Write_RISCV_conditional_strong_release, addr, width, data, meta))
- }) : MemoryOpResult(bool);
- print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
+ let result = MemValue(write_ram(wk, addr, width, data, meta));
+ if get_config_print_mem()
+ then print_mem("mem[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
result
}
-// dispatches to MMIO regions or physical memory regions depending on physical memory map
-function checked_mem_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), data: bits(8 * 'n), meta: mem_meta, aq : bool, rl : bool, con : bool) -> MemoryOpResult(bool) =
+/* dispatches to MMIO regions or physical memory regions depending on physical memory map */
+function checked_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, addr : xlenbits, width : atom('n), data: bits(8 * 'n), meta: mem_meta) -> MemoryOpResult(bool) =
if within_mmio_writable(addr, width)
then mmio_write(addr, width, data)
else if within_phys_mem(addr, width)
- then phys_mem_write(addr, width, data, meta, aq, rl, con)
- else MemException(E_SAMO_Access_Fault)
+ then phys_mem_write(wk, addr, width, data, meta)
+ else MemException(E_SAMO_Access_Fault())
-/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
-
-/* Memory write with a default metadata value */
-/* NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime. */
-val mem_write_value : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, wmvt, rreg, wreg, escape}
-function mem_write_value (addr, width, value, aq, rl, con) = {
- if (rl | con) & (~ (is_aligned_addr(addr, width)))
- then MemException(E_SAMO_Addr_Align)
- else match (aq, rl, con) {
- (true, false, false) => throw(Error_not_implemented("store.aq")),
- (true, false, true) => throw(Error_not_implemented("sc.aq")),
- (_, _, _) => checked_mem_write(addr, width, value, default_meta, aq, rl, con)
+/* PMP checks if enabled */
+function pmp_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk: write_kind, addr : xlenbits, width : atom('n), data: bits(8 * 'n), ext_acc: ext_access_type, meta: mem_meta) -> MemoryOpResult(bool) =
+ if (~ (plat_enable_pmp ()))
+ then checked_mem_write(wk, addr, width, data, meta)
+ else match pmpCheck(addr, width, Write(ext_acc), effectivePrivilege(mstatus, cur_privilege)) {
+ None() => checked_mem_write(wk, addr, width, data, meta),
+ Some(e) => MemException(e)
}
-}
-/* Memory write with an explicit metadata value */
-/* NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime. */
-val mem_write_value_meta : forall 'n, 'n > 0. (xlenbits, atom('n), bits(8 * 'n), mem_meta, bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, wmvt, rreg, wreg, escape}
-function mem_write_value_meta (addr, width, value, meta, aq, rl, con) = {
+/* Atomic accesses can be done to MMIO regions, e.g. in kernel access to device registers. */
+
+/* Memory write with an explicit metadata value. Metadata writes are
+ * currently assumed to have the same alignment constraints as their
+ * data.
+ * NOTE: The wreg effect is due to MMIO, the rreg is due to checking mtime.
+ */
+val mem_write_value_meta : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bits(8 * 'n), ext_access_type, mem_meta, bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, wmvt, rreg, wreg, escape}
+function mem_write_value_meta (addr, width, value, ext_acc, meta, aq, rl, con) = {
rvfi_write(addr, width, value);
if (rl | con) & (~ (is_aligned_addr(addr, width)))
- then MemException(E_SAMO_Addr_Align)
+ then MemException(E_SAMO_Addr_Align())
else match (aq, rl, con) {
+ (false, false, false) => pmp_mem_write(Write_plain, addr, width, value, ext_acc, meta),
+ (false, true, false) => pmp_mem_write(Write_RISCV_release, addr, width, value, ext_acc, meta),
+ (false, false, true) => pmp_mem_write(Write_RISCV_conditional, addr, width, value, ext_acc, meta),
+ (false, true , true) => pmp_mem_write(Write_RISCV_conditional_release, addr, width, value, ext_acc, meta),
+ (true, true, false) => pmp_mem_write(Write_RISCV_strong_release, addr, width, value, ext_acc, meta),
+ (true, true , true) => pmp_mem_write(Write_RISCV_conditional_strong_release, addr, width, value, ext_acc, meta),
+ // throw an illegal instruction here?
(true, false, false) => throw(Error_not_implemented("store.aq")),
- (true, false, true) => throw(Error_not_implemented("sc.aq")),
- (_, _, _) => checked_mem_write(addr, width, value, meta, aq, rl, con)
+ (true, false, true) => throw(Error_not_implemented("sc.aq"))
}
}
+
+/* Memory write with a default metadata value. */
+val mem_write_value : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool) effect {wmv, wmvt, rreg, wreg, escape}
+function mem_write_value (addr, width, value, aq, rl, con) =
+ mem_write_value_meta(addr, width, value, default_write_acc, default_meta, aq, rl, con)
diff --git a/model/riscv_next_control.sail b/model/riscv_next_control.sail
index 6034aae..b0ced4a 100644
--- a/model/riscv_next_control.sail
+++ b/model/riscv_next_control.sail
@@ -1,54 +1,32 @@
/* Functional specification for the 'N' user-level interrupts standard extension. */
-function is_NExt_CSR_defined(csr : bits(12), p : Privilege) -> bool =
- match (csr) {
- 0x000 => haveUsrMode(), // ustatus
- 0x004 => haveUsrMode(), // uie
- 0x005 => haveUsrMode(), // utvec
- 0x040 => haveUsrMode(), // uscratch
- 0x041 => haveUsrMode(), // uepc
- 0x042 => haveUsrMode(), // ucause
- 0x043 => haveUsrMode(), // utval
- 0x044 => haveUsrMode(), // uip
- _ => false
- }
+function clause ext_is_CSR_defined(0x000, _) = haveUsrMode() // ustatus
+function clause ext_is_CSR_defined(0x004, _) = haveUsrMode() // uie
+function clause ext_is_CSR_defined(0x005, _) = haveUsrMode() // utvec
+function clause ext_is_CSR_defined(0x040, _) = haveUsrMode() // uscratch
+function clause ext_is_CSR_defined(0x041, _) = haveUsrMode() // uepc
+function clause ext_is_CSR_defined(0x042, _) = haveUsrMode() // ucause
+function clause ext_is_CSR_defined(0x043, _) = haveUsrMode() // utval
+function clause ext_is_CSR_defined(0x044, _) = haveUsrMode() // uip
-function read_NExt_CSR csr : csreg -> option(xlenbits) = {
- let res : option(xlenbits) =
- match csr {
- 0x000 => Some(lower_sstatus(lower_mstatus(mstatus)).bits()),
- 0x004 => Some(lower_sie(lower_mie(mie, mideleg), sideleg).bits()),
- 0x005 => Some(get_utvec()),
- 0x040 => Some(uscratch),
- 0x041 => Some(get_xret_target(User) & pc_alignment_mask()),
- 0x042 => Some(ucause.bits()),
- 0x043 => Some(utval),
- 0x044 => Some(lower_sip(lower_mip(mip, mideleg), sideleg).bits()),
- _ => None()
- };
- res
-}
+function clause ext_read_CSR(0x000) = Some(lower_sstatus(lower_mstatus(mstatus)).bits())
+function clause ext_read_CSR(0x004) = Some(lower_sie(lower_mie(mie, mideleg), sideleg).bits())
+function clause ext_read_CSR(0x005) = Some(get_utvec())
+function clause ext_read_CSR(0x040) = Some(uscratch)
+function clause ext_read_CSR(0x041) = Some(get_xret_target(User) & pc_alignment_mask())
+function clause ext_read_CSR(0x042) = Some(ucause.bits())
+function clause ext_read_CSR(0x043) = Some(utval)
+function clause ext_read_CSR(0x044) = Some(lower_sip(lower_mip(mip, mideleg), sideleg).bits())
-function write_NExt_CSR(csr : csreg, value : xlenbits) -> bool = {
- let res : option(xlenbits) =
- match csr {
- 0x000 => { mstatus = legalize_ustatus(mstatus, value); Some(mstatus.bits()) },
- 0x004 => { let sie = legalize_uie(lower_mie(mie, mideleg), sideleg, value);
- mie = lift_sie(mie, mideleg, sie);
- Some(mie.bits()) },
- 0x005 => { Some(set_utvec(value)) },
- 0x040 => { uscratch = value; Some(uscratch) },
- 0x041 => { Some(set_xret_target(User, value)) },
- 0x042 => { ucause->bits() = value; Some(ucause.bits()) },
- 0x043 => { utval = value; Some(utval) },
- 0x044 => { let sip = legalize_uip(lower_mip(mip, mideleg), sideleg, value);
- mip = lift_sip(mip, mideleg, sip);
- Some(mip.bits()) },
- _ => None()
- };
- match res {
- Some(v) => { print_reg("CSR " ^ csr ^ " <- " ^ BitStr(v) ^ " (input: " ^ BitStr(value) ^ ")");
- true },
- None() => false
- }
-}
+function clause ext_write_CSR(0x000, value) = { mstatus = legalize_ustatus(mstatus, value); Some(mstatus.bits()) }
+function clause ext_write_CSR(0x004, value) = { let sie = legalize_uie(lower_mie(mie, mideleg), sideleg, value);
+ mie = lift_sie(mie, mideleg, sie);
+ Some(mie.bits()) }
+function clause ext_write_CSR(0x005, value) = { Some(set_utvec(value)) }
+function clause ext_write_CSR(0x040, value) = { uscratch = value; Some(uscratch) }
+function clause ext_write_CSR(0x041, value) = { Some(set_xret_target(User, value)) }
+function clause ext_write_CSR(0x042, value) = { ucause->bits() = value; Some(ucause.bits()) }
+function clause ext_write_CSR(0x043, value) = { utval = value; Some(utval) }
+function clause ext_write_CSR(0x044, value) = { let sip = legalize_uip(lower_mip(mip, mideleg), sideleg, value);
+ mip = lift_sip(mip, mideleg, sip);
+ Some(mip.bits()) }
diff --git a/model/riscv_next_regs.sail b/model/riscv_next_regs.sail
index 5a3fb58..b9c9c59 100644
--- a/model/riscv_next_regs.sail
+++ b/model/riscv_next_regs.sail
@@ -55,7 +55,7 @@ function lower_sie(s : Sinterrupts, d : Sinterrupts) -> Uinterrupts = {
/* Returns the new value of sip from the previous sip (o) and the written uip (u) as delegated by sideleg (d). */
function lift_uip(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = {
let s : Sinterrupts = o;
- let s = if d.USI() == true then update_USI(s, u.USI()) else s;
+ let s = if d.USI() == 0b1 then update_USI(s, u.USI()) else s;
s
}
@@ -66,9 +66,9 @@ function legalize_uip(s : Sinterrupts, d : Sinterrupts, v : xlenbits) -> Sinterr
/* Returns the new value of sie from the previous sie (o) and the written uie (u) as delegated by sideleg (d). */
function lift_uie(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = {
let s : Sinterrupts = o;
- let s = if d.UEI() == true then update_UEI(s, u.UEI()) else s;
- let s = if d.UTI() == true then update_UTI(s, u.UTI()) else s;
- let s = if d.USI() == true then update_USI(s, u.USI()) else s;
+ let s = if d.UEI() == 0b1 then update_UEI(s, u.UEI()) else s;
+ let s = if d.UTI() == 0b1 then update_UTI(s, u.UTI()) else s;
+ let s = if d.USI() == 0b1 then update_USI(s, u.USI()) else s;
s
}
diff --git a/model/riscv_pc_access.sail b/model/riscv_pc_access.sail
index a51e627..2de44ba 100644
--- a/model/riscv_pc_access.sail
+++ b/model/riscv_pc_access.sail
@@ -1,5 +1,13 @@
/* accessors for default architectural addresses, for use from within instructions */
-/* FIXME: see note in cheri_addr_checks.sail */
+
+/*!
+ Retrieves the architectural PC value. This is not necessarily the value
+ found in the PC register as extensions may choose to override this function.
+ The value in the PC register is the absolute virtual address of the instruction
+ to fetch.
+ */
+val get_arch_pc : unit -> xlenbits effect {rreg}
+function get_arch_pc() = PC
val get_next_pc : unit -> xlenbits effect {rreg}
function get_next_pc() = nextPC
diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail
index 87fa425..35d0960 100644
--- a/model/riscv_platform.sail
+++ b/model/riscv_platform.sail
@@ -22,6 +22,12 @@ val elf_entry = {
val plat_ram_base = {c: "plat_ram_base", ocaml: "Platform.dram_base", interpreter: "Platform.dram_base", lem: "plat_ram_base"} : unit -> xlenbits
val plat_ram_size = {c: "plat_ram_size", ocaml: "Platform.dram_size", interpreter: "Platform.dram_size", lem: "plat_ram_size"} : unit -> xlenbits
+/* whether the platform supports PMP configurations */
+val plat_enable_pmp = {ocaml: "Platform.enable_pmp",
+ interpreter: "Platform.enable_pmp",
+ c: "plat_enable_pmp",
+ lem: "plat_enable_pmp"} : unit -> bool
+
/* whether the MMU should update dirty bits in PTEs */
val plat_enable_dirty_update = {ocaml: "Platform.enable_dirty_update",
interpreter: "Platform.enable_dirty_update",
@@ -63,7 +69,7 @@ function phys_mem_segments() =
/* Physical memory map predicates */
-function within_phys_mem forall 'n. (addr : xlenbits, width : atom('n)) -> bool = {
+function within_phys_mem forall 'n, 'n <= max_mem_access. (addr : xlenbits, width : atom('n)) -> bool = {
/* To avoid overflow issues when physical memory extends to the end
* of the addressable range, we need to perform address bound checks
* on unsigned unbounded integers.
@@ -91,7 +97,7 @@ function within_phys_mem forall 'n. (addr : xlenbits, width : atom('n)) -> bool
}
}
-function within_clint forall 'n. (addr : xlenbits, width : atom('n)) -> bool = {
+function within_clint forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = {
/* To avoid overflow issues when physical memory extends to the end
* of the addressable range, we need to perform address bound checks
* on unsigned unbounded integers.
@@ -103,10 +109,10 @@ function within_clint forall 'n. (addr : xlenbits, width : atom('n)) -> bool = {
& (addr_int + sizeof('n)) <= (clint_base_int + clint_size_int)
}
-function within_htif_writable forall 'n. (addr : xlenbits, width : atom('n)) -> bool =
+function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)
-function within_htif_readable forall 'n. (addr : xlenbits, width : atom('n)) -> bool =
+function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)
/* CLINT (Core Local Interruptor), based on Spike. */
@@ -142,54 +148,64 @@ function clint_load(addr, width) = {
/* FIXME: For now, only allow exact aligned access. */
if addr == MSIP_BASE & ('n == 8 | 'n == 4)
then {
- print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mip.MSI()));
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mip.MSI()));
MemValue(sail_zero_extend(mip.MSI(), sizeof(8 * 'n)))
}
else if addr == MTIMECMP_BASE & ('n == 4)
then {
- print_platform("clint<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[31..0]));
+ if get_config_print_platform()
+ then print_platform("clint<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[31..0]));
/* FIXME: Redundant zero_extend currently required by Lem backend */
MemValue(sail_zero_extend(mtimecmp[31..0], 32))
}
else if addr == MTIMECMP_BASE & ('n == 8)
then {
- print_platform("clint<8>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp));
+ if get_config_print_platform()
+ then print_platform("clint<8>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp));
/* FIXME: Redundant zero_extend currently required by Lem backend */
MemValue(sail_zero_extend(mtimecmp, 64))
}
else if addr == MTIMECMP_BASE_HI & ('n == 4)
then {
- print_platform("clint-hi<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[63..32]));
+ if get_config_print_platform()
+ then print_platform("clint-hi<4>[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtimecmp[63..32]));
/* FIXME: Redundant zero_extend currently required by Lem backend */
MemValue(sail_zero_extend(mtimecmp[63..32], 32))
}
else if addr == MTIME_BASE & ('n == 4)
then {
- print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
MemValue(sail_zero_extend(mtime[31..0], 32))
}
else if addr == MTIME_BASE & ('n == 8)
then {
- print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
MemValue(sail_zero_extend(mtime, 64))
}
else if addr == MTIME_BASE_HI & ('n == 4)
then {
- print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] -> " ^ BitStr(mtime));
MemValue(sail_zero_extend(mtime[63..32], 32))
}
else {
- print_platform("clint[" ^ BitStr(addr) ^ "] -> <not-mapped>");
- MemException(E_Load_Access_Fault)
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] -> <not-mapped>");
+ MemException(E_Load_Access_Fault())
}
}
function clint_dispatch() -> unit = {
- print_platform("clint::tick mtime <- " ^ BitStr(mtime));
- mip->MTI() = false;
+ if get_config_print_platform()
+ then print_platform("clint::tick mtime <- " ^ BitStr(mtime));
+ mip->MTI() = 0b0;
if mtimecmp <=_u mtime then {
- print_platform(" clint timer pending at mtime " ^ BitStr(mtime));
- mip->MTI() = true
+ if get_config_print_platform()
+ then print_platform(" clint timer pending at mtime " ^ BitStr(mtime));
+ mip->MTI() = 0b1
}
}
@@ -198,28 +214,33 @@ val clint_store: forall 'n, 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryO
function clint_store(addr, width, data) = {
let addr = addr - plat_clint_base ();
if addr == MSIP_BASE & ('n == 8 | 'n == 4) then {
- print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mip.MSI <- " ^ BitStr(data[0]) ^ ")");
- mip->MSI() = data[0] == 0b1;
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mip.MSI <- " ^ BitStr(data[0]) ^ ")");
+ mip->MSI() = [data[0]];
clint_dispatch();
MemValue(true)
} else if addr == MTIMECMP_BASE & 'n == 8 then {
- print_platform("clint<8>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
+ if get_config_print_platform()
+ then print_platform("clint<8>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
mtimecmp = sail_zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */
clint_dispatch();
MemValue(true)
} else if addr == MTIMECMP_BASE & 'n == 4 then {
- print_platform("clint<4>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
+ if get_config_print_platform()
+ then print_platform("clint<4>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
mtimecmp = vector_update_subrange(mtimecmp, 31, 0, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */
clint_dispatch();
MemValue(true)
} else if addr == MTIMECMP_BASE_HI & 'n == 4 then {
- print_platform("clint<4>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
+ if get_config_print_platform()
+ then print_platform("clint<4>[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (mtimecmp)");
mtimecmp = vector_update_subrange(mtimecmp, 63, 32, sail_zero_extend(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */
clint_dispatch();
MemValue(true)
} else {
- print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (<unmapped>)");
- MemException(E_SAMO_Access_Fault)
+ if get_config_print_platform()
+ then print_platform("clint[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data) ^ " (<unmapped>)");
+ MemException(E_SAMO_Access_Fault())
}
}
@@ -255,7 +276,8 @@ register htif_exit_code : bits(64)
val htif_load : forall 'n, 'n > 0. (xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) effect {rreg}
function htif_load(addr, width) = {
- print_platform("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost));
+ if get_config_print_platform()
+ then print_platform("htif[" ^ BitStr(addr) ^ "] -> " ^ BitStr(htif_tohost));
/* FIXME: For now, only allow the expected access widths. */
if width == 8 & (addr == plat_htif_tohost())
then MemValue(sail_zero_extend(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */
@@ -263,13 +285,14 @@ function htif_load(addr, width) = {
then MemValue(sail_zero_extend(htif_tohost[31..0], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */
else if width == 4 & addr == plat_htif_tohost() + 4
then MemValue(sail_zero_extend(htif_tohost[63..32], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */
- else MemException(E_Load_Access_Fault)
+ else MemException(E_Load_Access_Fault())
}
/* The rreg,wreg effects are an artifact of using 'register' to implement device state. */
val htif_store: forall 'n, 0 < 'n <= 8. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) effect {rreg,wreg}
function htif_store(addr, width, data) = {
- print_platform("htif[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
+ if get_config_print_platform()
+ then print_platform("htif[" ^ BitStr(addr) ^ "] <- " ^ BitStr(data));
/* Store the written value so that we can ack it later. */
if width == 8
then { htif_tohost = EXTZ(data) }
@@ -283,8 +306,9 @@ function htif_store(addr, width, data) = {
let cmd = Mk_htif_cmd(htif_tohost);
match cmd.device() {
0x00 => { /* syscall-proxy */
- print_platform("htif-syscall-proxy cmd: " ^ BitStr(cmd.payload()));
- if cmd.payload()[0] == 0b1
+ if get_config_print_platform()
+ then print_platform("htif-syscall-proxy cmd: " ^ BitStr(cmd.payload()));
+ if cmd.payload()[0] == bitone
then {
htif_done = true;
htif_exit_code = (sail_zero_extend(cmd.payload(), 64) >> 1)
@@ -292,7 +316,8 @@ function htif_store(addr, width, data) = {
else ()
},
0x01 => { /* terminal */
- print_platform("htif-term cmd: " ^ BitStr(cmd.payload()));
+ if get_config_print_platform()
+ then print_platform("htif-term cmd: " ^ BitStr(cmd.payload()));
match cmd.cmd() {
0x00 => /* TODO: terminal input handling */ (),
0x01 => plat_term_write(cmd.payload()[7..0]),
@@ -306,31 +331,39 @@ function htif_store(addr, width, data) = {
val htif_tick : unit -> unit effect {rreg, wreg}
function htif_tick() = {
- print_platform("htif::tick " ^ BitStr(htif_tohost));
+ if get_config_print_platform()
+ then print_platform("htif::tick " ^ BitStr(htif_tohost));
htif_tohost = EXTZ(0b0) /* htif ack */
}
/* Top-level MMIO dispatch */
-
-function within_mmio_readable forall 'n. (addr : xlenbits, width : atom('n)) -> bool =
+$ifndef RVFI_DII
+function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
within_clint(addr, width) | (within_htif_readable(addr, width) & 1 <= 'n)
+$else
+function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = false
+$endif
-function within_mmio_writable forall 'n. (addr : xlenbits, width : atom('n)) -> bool =
+$ifndef RVFI_DII
+function within_mmio_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
within_clint(addr, width) | (within_htif_writable(addr, width) & 'n <= 8)
+$else
+function within_mmio_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = false
+$endif
-function mmio_read forall 'n, 'n > 0. (addr : xlenbits, width : atom('n)) -> MemoryOpResult(bits(8 * 'n)) =
+function mmio_read forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> MemoryOpResult(bits(8 * 'n)) =
if within_clint(addr, width)
then clint_load(addr, width)
else if within_htif_readable(addr, width) & (1 <= 'n)
then htif_load(addr, width)
- else MemException(E_Load_Access_Fault)
+ else MemException(E_Load_Access_Fault())
-function mmio_write forall 'n, 'n > 0. (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =
+function mmio_write forall 'n, 0 <'n <= max_mem_access . (addr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =
if within_clint(addr, width)
then clint_store(addr, width, data)
else if within_htif_writable(addr, width) & 'n <= 8
then htif_store(addr, width, data)
- else MemException(E_SAMO_Access_Fault)
+ else MemException(E_SAMO_Access_Fault())
/* Platform initialization and ticking. */
@@ -350,7 +383,7 @@ function handle_illegal() -> unit = {
let info = if plat_mtval_has_illegal_inst_bits ()
then Some(instbits)
else None();
- let t : sync_exception = struct { trap = E_Illegal_Instr,
+ let t : sync_exception = struct { trap = E_Illegal_Instr(),
excinfo = info,
ext = None() };
set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC))
diff --git a/model/riscv_pmp_control.sail b/model/riscv_pmp_control.sail
new file mode 100644
index 0000000..4f43a6c
--- /dev/null
+++ b/model/riscv_pmp_control.sail
@@ -0,0 +1,185 @@
+/* address ranges */
+
+// TODO: handle PMP grain > 4 (i.e. G > 0).
+// TODO: handle the 34-bit paddr32 on RV32
+
+/* [min, max) of the matching range. */
+type pmp_addr_range = option((xlenbits, xlenbits))
+
+function pmpAddrRange(cfg: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmp_addr_range = {
+ match pmpAddrMatchType_of_bits(cfg.A()) {
+ OFF => None(),
+ TOR => { Some ((prev_pmpaddr << 2, pmpaddr << 2)) },
+ NA4 => { // TODO: I find the spec unclear for entries marked NA4 and G = 1.
+ // (for G >= 2, it is the same as NAPOT). In particular, it affects
+ // whether pmpaddr[0] is always read as 0.
+ let lo = pmpaddr << 2;
+ Some((lo, lo + 4))
+ },
+ NAPOT => { let mask = pmpaddr ^ (pmpaddr + 1); // generate 1s in signifying bits
+ let lo = pmpaddr & (~ (mask));
+ let len = mask + 1;
+ Some((lo << 2, (lo + len) << 2))
+ }
+ }
+}
+
+/* permission checks */
+
+val pmpCheckRWX: (Pmpcfg_ent, AccessType(ext_access_type)) -> bool
+function pmpCheckRWX(ent, acc) = {
+ match acc {
+ Read(Data) => ent.R() == 0b1,
+ Write(Data) => ent.W() == 0b1,
+ ReadWrite(Data) => ent.R() == 0b1 & ent.W() == 0b1,
+ Execute() => ent.X() == 0b1
+ }
+}
+
+// this needs to be called with the effective current privilege.
+val pmpCheckPerms: (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool
+function pmpCheckPerms(ent, acc, priv) = {
+ match priv {
+ Machine => if ent.L() == 0b1
+ then pmpCheckRWX(ent, acc)
+ else true,
+ _ => pmpCheckRWX(ent, acc)
+ }
+}
+
+/* matching logic */
+
+enum pmpAddrMatch = {PMP_NoMatch, PMP_PartialMatch, PMP_Match}
+
+function pmpMatchAddr(addr: xlenbits, width: xlenbits, rng: pmp_addr_range) -> pmpAddrMatch = {
+ match rng {
+ None() => PMP_NoMatch,
+ Some((lo, hi)) => if hi <_u lo /* to handle mis-configuration */
+ then PMP_NoMatch
+ else {
+ if (addr + width <_u lo) | (hi <_u addr)
+ then PMP_NoMatch
+ else if (lo <=_u addr) & (addr + width <=_u hi)
+ then PMP_Match
+ else PMP_PartialMatch
+ }
+ }
+}
+
+enum pmpMatch = {PMP_Success, PMP_Continue, PMP_Fail}
+
+function pmpMatchEntry(addr: xlenbits, width: xlenbits, acc: AccessType(ext_access_type), priv: Privilege,
+ ent: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmpMatch = {
+ let rng = pmpAddrRange(ent, pmpaddr, prev_pmpaddr);
+ match pmpMatchAddr(addr, width, rng) {
+ PMP_NoMatch => PMP_Continue,
+ PMP_PartialMatch => PMP_Fail,
+ PMP_Match => if pmpCheckPerms(ent, acc, priv)
+ then PMP_Success
+ else PMP_Fail
+ }
+}
+
+/* priority checks */
+
+function pmpCheck forall 'n, 'n > 0. (addr: xlenbits, width: atom('n), acc: AccessType(ext_access_type), priv: Privilege)
+ -> option(ExceptionType) = {
+ let width : xlenbits = to_bits(sizeof(xlen), width);
+ let check : bool =
+ match pmpMatchEntry(addr, width, acc, priv, pmp0cfg, pmpaddr0, zeros()) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp1cfg, pmpaddr1, pmpaddr0) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp2cfg, pmpaddr2, pmpaddr1) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp3cfg, pmpaddr3, pmpaddr2) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp4cfg, pmpaddr4, pmpaddr3) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp5cfg, pmpaddr5, pmpaddr4) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp6cfg, pmpaddr6, pmpaddr5) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp7cfg, pmpaddr7, pmpaddr6) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp8cfg, pmpaddr8, pmpaddr7) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp9cfg, pmpaddr9, pmpaddr8) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp10cfg, pmpaddr10, pmpaddr9) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp11cfg, pmpaddr11, pmpaddr10) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp12cfg, pmpaddr12, pmpaddr11) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp13cfg, pmpaddr13, pmpaddr12) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp14cfg, pmpaddr14, pmpaddr13) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue =>
+ match pmpMatchEntry(addr, width, acc, priv, pmp15cfg, pmpaddr15, pmpaddr14) {
+ PMP_Success => true,
+ PMP_Fail => false,
+ PMP_Continue => match priv {
+ Machine => true,
+ _ => false
+ }
+ }}}}}}}}}}}}}}}};
+
+ if check
+ then None()
+ else match acc {
+ Read(Data) => Some(E_Load_Access_Fault()),
+ Write(Data) => Some(E_SAMO_Access_Fault()),
+ ReadWrite(Data) => Some(E_SAMO_Access_Fault()),
+ Execute() => Some(E_Fetch_Access_Fault())
+ }
+}
+
+function init_pmp() -> unit = {
+ pmp0cfg = update_A(pmp0cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp1cfg = update_A(pmp1cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp2cfg = update_A(pmp2cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp3cfg = update_A(pmp3cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp4cfg = update_A(pmp4cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp5cfg = update_A(pmp5cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp6cfg = update_A(pmp6cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp7cfg = update_A(pmp7cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp8cfg = update_A(pmp8cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp9cfg = update_A(pmp9cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp10cfg = update_A(pmp10cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp11cfg = update_A(pmp11cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp12cfg = update_A(pmp12cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp13cfg = update_A(pmp13cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp14cfg = update_A(pmp14cfg, pmpAddrMatchType_to_bits(OFF));
+ pmp15cfg = update_A(pmp15cfg, pmpAddrMatchType_to_bits(OFF))
+}
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail
new file mode 100644
index 0000000..978ef18
--- /dev/null
+++ b/model/riscv_pmp_regs.sail
@@ -0,0 +1,143 @@
+/* PMP configuration entries */
+
+enum PmpAddrMatchType = {OFF, TOR, NA4, NAPOT}
+
+val pmpAddrMatchType_of_bits : bits(2) -> PmpAddrMatchType
+function pmpAddrMatchType_of_bits(bs) = {
+ match bs {
+ 0b00 => OFF,
+ 0b01 => TOR,
+ 0b10 => NA4,
+ 0b11 => NAPOT
+ }
+}
+
+val pmpAddrMatchType_to_bits : PmpAddrMatchType -> bits(2)
+function pmpAddrMatchType_to_bits(bs) = {
+ match bs {
+ OFF => 0b00,
+ TOR => 0b01,
+ NA4 => 0b10,
+ NAPOT => 0b11
+ }
+}
+
+bitfield Pmpcfg_ent : bits(8) = {
+ L : 7, /* locking */
+ A : 4 .. 3, /* address match type, encoded as above */
+
+ /* permissions */
+ X : 2, /* execute */
+ W : 1, /* write */
+ R : 0 /* read */
+}
+
+register pmp0cfg : Pmpcfg_ent
+register pmp1cfg : Pmpcfg_ent
+register pmp2cfg : Pmpcfg_ent
+register pmp3cfg : Pmpcfg_ent
+register pmp4cfg : Pmpcfg_ent
+register pmp5cfg : Pmpcfg_ent
+register pmp6cfg : Pmpcfg_ent
+register pmp7cfg : Pmpcfg_ent
+register pmp8cfg : Pmpcfg_ent
+register pmp9cfg : Pmpcfg_ent
+register pmp10cfg : Pmpcfg_ent
+register pmp11cfg : Pmpcfg_ent
+register pmp12cfg : Pmpcfg_ent
+register pmp13cfg : Pmpcfg_ent
+register pmp14cfg : Pmpcfg_ent
+register pmp15cfg : Pmpcfg_ent
+
+/* PMP address configuration */
+
+register pmpaddr0 : xlenbits
+register pmpaddr1 : xlenbits
+register pmpaddr2 : xlenbits
+register pmpaddr3 : xlenbits
+register pmpaddr4 : xlenbits
+register pmpaddr5 : xlenbits
+register pmpaddr6 : xlenbits
+register pmpaddr7 : xlenbits
+register pmpaddr8 : xlenbits
+register pmpaddr9 : xlenbits
+register pmpaddr10 : xlenbits
+register pmpaddr11 : xlenbits
+register pmpaddr12 : xlenbits
+register pmpaddr13 : xlenbits
+register pmpaddr14 : xlenbits
+register pmpaddr15 : xlenbits
+
+/* Packing and unpacking pmpcfg regs for xlen-width accesses */
+
+val pmpReadCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n)) -> xlenbits effect {rreg}
+function pmpReadCfgReg(n) = {
+ if sizeof(xlen) == 32
+ then match n {
+ 0 => append(pmp3cfg.bits(), append(pmp2cfg.bits(), append(pmp1cfg.bits(), pmp0cfg.bits()))),
+ 1 => append(pmp7cfg.bits(), append(pmp6cfg.bits(), append(pmp5cfg.bits(), pmp4cfg.bits()))),
+ 2 => append(pmp11cfg.bits(), append(pmp10cfg.bits(), append(pmp9cfg.bits(), pmp8cfg.bits()))),
+ 3 => append(pmp15cfg.bits(), append(pmp14cfg.bits(), append(pmp13cfg.bits(), pmp12cfg.bits())))
+ }
+ else match n { // sizeof(xlen) == 64
+ 0 => append(pmp7cfg.bits(), append(pmp6cfg.bits(), append(pmp5cfg.bits(), append(pmp4cfg.bits(), append(pmp3cfg.bits(), append(pmp2cfg.bits(), append(pmp1cfg.bits(), pmp0cfg.bits()))))))),
+ 2 => append(pmp15cfg.bits(), append(pmp14cfg.bits(), append(pmp13cfg.bits(), append(pmp12cfg.bits(), append(pmp11cfg.bits(), append(pmp10cfg.bits(), append(pmp9cfg.bits(), pmp8cfg.bits())))))))
+ }
+}
+
+/* Helper to handle locked entries */
+function pmpWriteCfg(cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent =
+ if cfg.L() == 0b1 then cfg else Mk_Pmpcfg_ent(v)
+
+val pmpWriteCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n), xlenbits) -> unit effect {rreg, wreg}
+function pmpWriteCfgReg(n, v) = {
+ if sizeof(xlen) == 32
+ then match n {
+ 0 => { pmp0cfg = pmpWriteCfg(pmp0cfg, v[7 ..0]);
+ pmp1cfg = pmpWriteCfg(pmp1cfg, v[15..8]);
+ pmp2cfg = pmpWriteCfg(pmp2cfg, v[23..16]);
+ pmp3cfg = pmpWriteCfg(pmp3cfg, v[31..24]);
+ },
+ 1 => { pmp4cfg = pmpWriteCfg(pmp4cfg, v[7 ..0]);
+ pmp5cfg = pmpWriteCfg(pmp5cfg, v[15..8]);
+ pmp6cfg = pmpWriteCfg(pmp6cfg, v[23..16]);
+ pmp7cfg = pmpWriteCfg(pmp7cfg, v[31..24]);
+ },
+ 2 => { pmp8cfg8 = pmpWriteCfg(pmp8cfg, v[7 ..0]);
+ pmp9cfg9 = pmpWriteCfg(pmp9cfg, v[15..8]);
+ pmp10cfg = pmpWriteCfg(pmp10cfg, v[23..16]);
+ pmp11cfg = pmpWriteCfg(pmp11cfg, v[31..24]);
+ },
+ 3 => { pmp12cfg = pmpWriteCfg(pmp12cfg, v[7 ..0]);
+ pmp13cfg = pmpWriteCfg(pmp13cfg, v[15..8]);
+ pmp14cfg = pmpWriteCfg(pmp14cfg, v[23..16]);
+ pmp15cfg = pmpWriteCfg(pmp15cfg, v[31..24]);
+ }
+ }
+ else if sizeof(xlen) == 64
+ then match n {
+ 0 => { pmp0cfg = pmpWriteCfg(pmp0cfg, v[7 ..0]);
+ pmp1cfg = pmpWriteCfg(pmp1cfg, v[15..8]);
+ pmp2cfg = pmpWriteCfg(pmp2cfg, v[23..16]);
+ pmp3cfg = pmpWriteCfg(pmp3cfg, v[31..24]);
+ pmp4cfg = pmpWriteCfg(pmp4cfg, v[39..32]);
+ pmp5cfg = pmpWriteCfg(pmp5cfg, v[47..40]);
+ pmp6cfg = pmpWriteCfg(pmp6cfg, v[55..48]);
+ pmp7cfg = pmpWriteCfg(pmp7cfg, v[63..56])
+ },
+ 2 => { pmp8cfg8 = pmpWriteCfg(pmp8cfg, v[7 ..0]);
+ pmp9cfg9 = pmpWriteCfg(pmp9cfg, v[15..8]);
+ pmp10cfg = pmpWriteCfg(pmp10cfg, v[23..16]);
+ pmp11cfg = pmpWriteCfg(pmp11cfg, v[31..24]);
+ pmp12cfg = pmpWriteCfg(pmp12cfg, v[39..32]);
+ pmp13cfg = pmpWriteCfg(pmp13cfg, v[47..40]);
+ pmp14cfg = pmpWriteCfg(pmp14cfg, v[55..48]);
+ pmp15cfg = pmpWriteCfg(pmp15cfg, v[63..56])
+ }
+ }
+}
+
+function pmpWriteAddr(cfg: Pmpcfg_ent, reg: xlenbits, v: xlenbits) -> xlenbits =
+ if sizeof(xlen) == 32
+ then { if cfg.L() == 0b1 then reg else v }
+ else { if cfg.L() == 0b1 then reg else EXTZ(v[53..0]) }
diff --git a/model/riscv_pte.sail b/model/riscv_pte.sail
new file mode 100644
index 0000000..d07018f
--- /dev/null
+++ b/model/riscv_pte.sail
@@ -0,0 +1,67 @@
+/* PTE attributes, permission checks and updates */
+
+type pteAttribs = bits(8)
+
+/* Reserved PTE bits could be used by extensions on RV64. There are
+ * no such available bits on RV32, so these bits will be zeros on RV32.
+ */
+type extPte = bits(10)
+
+bitfield PTE_Bits : pteAttribs = {
+ D : 7,
+ A : 6,
+ G : 5,
+ U : 4,
+ X : 3,
+ W : 2,
+ R : 1,
+ V : 0
+}
+
+function isPTEPtr(p : pteAttribs, ext : extPte) -> bool = {
+ let a = Mk_PTE_Bits(p);
+ a.R() == 0b0 & a.W() == 0b0 & a.X() == 0b0
+}
+
+function isInvalidPTE(p : pteAttribs, ext : extPte) -> bool = {
+ let a = Mk_PTE_Bits(p);
+ a.V() == 0b0 | (a.W() == 0b1 & a.R() == 0b0)
+}
+
+union PTE_Check = {
+ PTE_Check_Success : ext_ptw,
+ PTE_Check_Failure : ext_ptw
+}
+
+function to_pte_check(b : bool) -> PTE_Check =
+ if b then PTE_Check_Success(()) else PTE_Check_Failure(())
+
+/* For extensions: this function gets the extension-available bits of the PTE in extPte,
+ * and the accumulated information of the page-table-walk in ext_ptw. It should return
+ * the updated ext_ptw in both the success and failure cases.
+ */
+function checkPTEPermission(ac : AccessType(ext_access_type), priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits, ext : extPte, ext_ptw : ext_ptw) -> PTE_Check = {
+ match (ac, priv) {
+ (Read(Data), User) => to_pte_check(p.U() == 0b1 & (p.R() == 0b1 | (p.X() == 0b1 & mxr))),
+ (Write(Data), User) => to_pte_check(p.U() == 0b1 & p.W() == 0b1),
+ (ReadWrite(Data), User) => to_pte_check(p.U() == 0b1 & p.W() == 0b1 & (p.R() == 0b1 | (p.X() == 0b1 & mxr))),
+ (Execute(), User) => to_pte_check(p.U() == 0b1 & p.X() == 0b1),
+
+ (Read(Data), Supervisor) => to_pte_check((p.U() == 0b0 | do_sum) & (p.R() == 0b1 | (p.X() == 0b1 & mxr))),
+ (Write(Data), Supervisor) => to_pte_check((p.U() == 0b0 | do_sum) & p.W() == 0b1),
+ (ReadWrite(Data), Supervisor) => to_pte_check((p.U() == 0b0 | do_sum) & p.W() == 0b1 & (p.R() == 0b1 | (p.X() == 0b1 & mxr))),
+ (Execute(), Supervisor) => to_pte_check(p.U() == 0b0 & p.X() == 0b1),
+
+ (_, Machine) => internal_error("m-mode mem perm check")
+ }
+}
+
+function update_PTE_Bits(p : PTE_Bits, a : AccessType(ext_access_type), ext : extPte) -> option((PTE_Bits, extPte)) = {
+ let update_d = (a == Write(Data) | a == ReadWrite(Data)) & p.D() == 0b0; // dirty-bit
+ let update_a = p.A() == 0b0; // accessed-bit
+ if update_d | update_a then {
+ let np = update_A(p, 0b1);
+ let np = if update_d then update_D(np, 0b1) else np;
+ Some(np, ext)
+ } else None()
+}
diff --git a/model/riscv_ptw.sail b/model/riscv_ptw.sail
new file mode 100644
index 0000000..1675593
--- /dev/null
+++ b/model/riscv_ptw.sail
@@ -0,0 +1,42 @@
+/* failure modes for address-translation/page-table-walks */
+
+union PTW_Error = {
+ PTW_Access : unit, /* physical memory access error for a PTE */
+ PTW_Invalid_PTE : unit,
+ PTW_No_Permission : unit,
+ PTW_Misaligned : unit, /* misaligned superpage */
+ PTW_PTE_Update : unit, /* PTE update needed but not enabled */
+ PTW_Ext_Error : ext_ptw_error /* parameterized for errors from extensions */
+}
+
+val ptw_error_to_str : PTW_Error -> string
+function ptw_error_to_str(e) =
+ match (e) {
+ PTW_Access() => "mem-access-error",
+ PTW_Invalid_PTE() => "invalid-pte",
+ PTW_No_Permission() => "no-permission",
+ PTW_Misaligned() => "misaligned-superpage",
+ PTW_PTE_Update() => "pte-update-needed",
+ PTW_Ext_Error(e) => "extension-error"
+ }
+
+overload to_str = {ptw_error_to_str}
+
+/* conversion of these translation/PTW failures into architectural exceptions */
+function translationException(a : AccessType(ext_access_type), f : PTW_Error) -> ExceptionType = {
+ let e : ExceptionType =
+ match (a, f) {
+ (_, PTW_Ext_Error(e)) => E_Extension(ext_translate_exception(e)),
+ (ReadWrite(Data), PTW_Access()) => E_SAMO_Access_Fault(),
+ (ReadWrite(Data), _) => E_SAMO_Page_Fault(),
+ (Read(Data), PTW_Access()) => E_Load_Access_Fault(),
+ (Read(Data), _) => E_Load_Page_Fault(),
+ (Write(Data), PTW_Access()) => E_SAMO_Access_Fault(),
+ (Write(Data), _) => E_SAMO_Page_Fault(),
+ (Execute(), PTW_Access()) => E_Fetch_Access_Fault(),
+ (Execute(), _) => E_Fetch_Page_Fault()
+ } in {
+/* print_mem("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e); */
+ e
+ }
+}
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail
index b92f234..4b4a1ea 100644
--- a/model/riscv_regs.sail
+++ b/model/riscv_regs.sail
@@ -86,7 +86,7 @@ function rX r = {
$ifdef RVFI_DII
val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg}
function rvfi_wX (r,v) = {
- rvfi_exec->rvfi_rd_wdata() = EXTS(v);
+ rvfi_exec->rvfi_rd_wdata() = EXTZ(v);
rvfi_exec->rvfi_rd_addr() = to_bits(8,r);
}
$else
@@ -134,15 +134,22 @@ function wX (r, in_v) = {
};
if (r != 0) then {
rvfi_wX(r, in_v);
- print_reg("x" ^ string_of_int(r) ^ " <- " ^ RegStr(v));
+ if get_config_print_reg()
+ then print_reg("x" ^ string_of_int(r) ^ " <- " ^ RegStr(v));
}
}
-overload X = {rX, wX}
+function rX_bits(i: bits(5)) -> xlenbits = rX(unsigned(i))
+
+function wX_bits(i: bits(5), data: xlenbits) -> unit = {
+ wX(unsigned(i)) = data
+}
+
+overload X = {rX_bits, wX_bits, rX, wX}
/* register names */
-val cast reg_name_abi : regidx -> string
+val reg_name_abi : regidx -> string
function reg_name_abi(r) = {
match (r) {
@@ -181,6 +188,8 @@ function reg_name_abi(r) = {
}
}
+overload to_str = {reg_name_abi}
+
/* mappings for assembly */
val reg_name : bits(5) <-> string
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index 4b5c1c5..550e58e 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -1,8 +1,7 @@
/* The emulator fetch-execute-interrupt dispatch loop. */
/* returns whether to increment the step count in the trace */
-val step : int -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wmvt, wreg}
-function step(step_no) = {
+function step(step_no : int) -> bool = {
/* for step extensions */
ext_pre_step_hook();
@@ -10,7 +9,8 @@ function step(step_no) = {
let (retired, stepped) : (Retired, bool) =
match dispatchInterrupt(cur_privilege) {
Some(intr, priv) => {
- print_bits("Handling interrupt: ", intr);
+ if get_config_print_instr()
+ then print_bits("Handling interrupt: ", interruptType_to_bits(intr));
handle_interrupt(intr, priv);
(RETIRE_FAIL, false)
},
@@ -31,7 +31,10 @@ function step(step_no) = {
/* non-error cases: */
F_RVC(h) => {
let ast = decodeCompressed(h);
- print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ ast);
+ if get_config_print_instr()
+ then {
+ print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ to_str(cur_privilege) ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ to_str(ast));
+ };
/* check for RVC once here instead of every RVC execute clause. */
if haveRVC() then {
nextPC = PC + 2;
@@ -43,7 +46,10 @@ function step(step_no) = {
},
F_Base(w) => {
let ast = decode(w);
- print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast);
+ if get_config_print_instr()
+ then {
+ print_instr("[" ^ string_of_int(step_no) ^ "] [" ^ to_str(cur_privilege) ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ to_str(ast));
+ };
nextPC = PC + 4;
(execute(ext_post_decode_hook(ast)), true)
}
@@ -65,8 +71,7 @@ function step(step_no) = {
stepped
}
-val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wmvt, wreg}
-function loop () = {
+function loop () : unit -> unit = {
let insns_per_tick = plat_insns_per_tick();
i : int = 0;
step_no : int = 0;
diff --git a/model/riscv_step_rvfi.sail b/model/riscv_step_rvfi.sail
index abe9394..0ab482a 100644
--- a/model/riscv_step_rvfi.sail
+++ b/model/riscv_step_rvfi.sail
@@ -6,7 +6,7 @@ function ext_pre_step_hook() -> unit = ()
function ext_post_step_hook() -> unit = {
/* record the next pc */
- rvfi_exec->rvfi_pc_wdata() = EXTS(PC)
+ rvfi_exec->rvfi_pc_wdata() = EXTZ(get_arch_pc())
}
val ext_init : unit -> unit effect {wreg}
@@ -19,5 +19,6 @@ function ext_init() = {
rvfi_zero_exec_packet();
rvfi_halt_exec_packet();
let _ = rvfi_get_exec_packet();
+ ext_rvfi_init();
()
}
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 6bee610..8162cb8 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -28,8 +28,27 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
0x343 => p == Machine, // mtval
0x344 => p == Machine, // mip
- 0x3A0 => p == Machine, // pmpcfg0
+ 0x3A0 => p == Machine, // pmpcfg0
+ 0x3A1 => p == Machine & (sizeof(xlen) == 32), // pmpcfg1
+ 0x3A2 => p == Machine, // pmpcfg2
+ 0x3A3 => p == Machine & (sizeof(xlen) == 32), // pmpcfg3
+
0x3B0 => p == Machine, // pmpaddr0
+ 0x3B1 => p == Machine, // pmpaddr1
+ 0x3B2 => p == Machine, // pmpaddr2
+ 0x3B3 => p == Machine, // pmpaddr3
+ 0x3B4 => p == Machine, // pmpaddr4
+ 0x3B5 => p == Machine, // pmpaddr5
+ 0x3B6 => p == Machine, // pmpaddr6
+ 0x3B7 => p == Machine, // pmpaddr7
+ 0x3B8 => p == Machine, // pmpaddr8
+ 0x3B9 => p == Machine, // pmpaddr9
+ 0x3BA => p == Machine, // pmpaddrA
+ 0x3BB => p == Machine, // pmpaddrB
+ 0x3BC => p == Machine, // pmpaddrC
+ 0x3BD => p == Machine, // pmpaddrD
+ 0x3BE => p == Machine, // pmpaddrE
+ 0x3BF => p == Machine, // pmpaddrF
/* counters */
0xB00 => p == Machine, // mcycle
@@ -78,17 +97,17 @@ function check_CSR_access(csrrw, csrpr, p, isWrite) =
& (privLevel_to_bits(p) >=_u csrpr) /* privilege */
function check_TVM_SATP(csr : csreg, p : Privilege) -> bool =
- ~ (csr == 0x180 & p == Supervisor & mstatus.TVM() == true)
+ ~ (csr == 0x180 & p == Supervisor & mstatus.TVM() == 0b1)
function check_Counteren(csr : csreg, p : Privilege) -> bool =
match(csr, p) {
- (0xC00, Supervisor) => mcounteren.CY() == true,
- (0xC01, Supervisor) => mcounteren.TM() == true,
- (0xC02, Supervisor) => mcounteren.IR() == true,
+ (0xC00, Supervisor) => mcounteren.CY() == 0b1,
+ (0xC01, Supervisor) => mcounteren.TM() == 0b1,
+ (0xC02, Supervisor) => mcounteren.IR() == 0b1,
- (0xC00, User) => mcounteren.CY() == true & ((~ (haveSupMode())) | scounteren.CY() == true),
- (0xC01, User) => mcounteren.TM() == true & ((~ (haveSupMode())) | scounteren.TM() == true),
- (0xC02, User) => mcounteren.IR() == true & ((~ (haveSupMode())) | scounteren.IR() == true),
+ (0xC00, User) => mcounteren.CY() == 0b1 & ((~ (haveSupMode())) | scounteren.CY() == 0b1),
+ (0xC01, User) => mcounteren.TM() == 0b1 & ((~ (haveSupMode())) | scounteren.TM() == 0b1),
+ (0xC02, User) => mcounteren.IR() == 0b1 & ((~ (haveSupMode())) | scounteren.IR() == 0b1),
(_, _) => /* no HPM counters for now */
if 0xC03 <=_u csr & csr <=_u 0xC1F
@@ -125,10 +144,10 @@ val cancel_reservation = {ocaml: "Platform.cancel_reservation", interpreter: "Pl
*/
function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {
let idx = num_of_ExceptionType(e);
- let super = medeleg.bits()[idx];
+ let super = bit_to_bool(medeleg.bits()[idx]);
/* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */
let user = if haveSupMode()
- then super & haveNExt() & sedeleg.bits()[idx]
+ then super & haveNExt() & bit_to_bool(sedeleg.bits()[idx])
else super & haveNExt();
let deleg = if haveUsrMode() & user then User
else if haveSupMode() & super then Supervisor
@@ -143,16 +162,16 @@ function exception_delegatee(e : ExceptionType, p : Privilege) -> Privilege = {
*/
function findPendingInterrupt(ip : xlenbits) -> option(InterruptType) = {
let ip = Mk_Minterrupts(ip);
- if ip.MEI() == true then Some(I_M_External)
- else if ip.MSI() == true then Some(I_M_Software)
- else if ip.MTI() == true then Some(I_M_Timer)
- else if ip.SEI() == true then Some(I_S_External)
- else if ip.SSI() == true then Some(I_S_Software)
- else if ip.STI() == true then Some(I_S_Timer)
- else if ip.UEI() == true then Some(I_U_External)
- else if ip.USI() == true then Some(I_U_Software)
- else if ip.UTI() == true then Some(I_U_Timer)
- else None()
+ if ip.MEI() == 0b1 then Some(I_M_External)
+ else if ip.MSI() == 0b1 then Some(I_M_Software)
+ else if ip.MTI() == 0b1 then Some(I_M_Timer)
+ else if ip.SEI() == 0b1 then Some(I_S_External)
+ else if ip.SSI() == 0b1 then Some(I_S_Software)
+ else if ip.STI() == 0b1 then Some(I_S_Timer)
+ else if ip.UEI() == 0b1 then Some(I_U_External)
+ else if ip.USI() == 0b1 then Some(I_U_Software)
+ else if ip.UTI() == 0b1 then Some(I_U_Timer)
+ else None()
}
/* Process the pending interrupts xip at a privilege according to
@@ -195,9 +214,9 @@ function getPendingSet(priv : Privilege) -> option((xlenbits, Privilege)) = {
* while lower privileges are blocked. An unsupported privilege is
* considered blocked.
*/
- let mIE = priv != Machine | (priv == Machine & mstatus.MIE() == true);
- let sIE = haveSupMode() & (priv == User | (priv == Supervisor & mstatus.SIE() == true));
- let uIE = haveNExt() & (priv == User & mstatus.UIE() == true);
+ let mIE = priv != Machine | (priv == Machine & mstatus.MIE() == 0b1);
+ let sIE = haveSupMode() & (priv == User | (priv == Supervisor & mstatus.SIE() == 0b1));
+ let uIE = haveNExt() & (priv == User & mstatus.UIE() == 0b1);
match processPending(mip, mie, mideleg.bits(), mIE) {
Ints_Empty() => None(),
Ints_Pending(p) => let r = (p, Machine) in Some(r),
@@ -276,18 +295,20 @@ $endif
function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits), ext : option(ext_exception))
-> xlenbits = {
rvfi_trap();
- print_platform("handling " ^ (if intr then "int#" else "exc#")
- ^ BitStr(c) ^ " at priv " ^ del_priv ^ " with tval " ^ BitStr(tval(info)));
+ if get_config_print_platform()
+ then print_platform("handling " ^ (if intr then "int#" else "exc#")
+ ^ BitStr(c) ^ " at priv " ^ to_str(del_priv)
+ ^ " with tval " ^ BitStr(tval(info)));
cancel_reservation();
match (del_priv) {
Machine => {
- mcause->IsInterrupt() = intr;
+ mcause->IsInterrupt() = bool_to_bits(intr);
mcause->Cause() = EXTZ(c);
mstatus->MPIE() = mstatus.MIE();
- mstatus->MIE() = false;
+ mstatus->MIE() = 0b0;
mstatus->MPP() = privLevel_to_bits(cur_privilege);
mtval = tval(info);
mepc = pc;
@@ -296,21 +317,22 @@ function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlen
handle_trap_extension(del_priv, pc, ext);
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
prepare_trap_vector(del_priv, mcause)
},
Supervisor => {
assert (haveSupMode(), "no supervisor mode present for delegation");
- scause->IsInterrupt() = intr;
+ scause->IsInterrupt() = bool_to_bits(intr);
scause->Cause() = EXTZ(c);
mstatus->SPIE() = mstatus.SIE();
- mstatus->SIE() = false;
- mstatus->SPP() = match (cur_privilege) {
- User => false,
- Supervisor => true,
+ mstatus->SIE() = 0b0;
+ mstatus->SPP() = match cur_privilege {
+ User => 0b0,
+ Supervisor => 0b1,
Machine => internal_error("invalid privilege for s-mode trap")
};
stval = tval(info);
@@ -320,18 +342,19 @@ function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlen
handle_trap_extension(del_priv, pc, ext);
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
prepare_trap_vector(del_priv, scause)
},
User => {
assert(haveUsrMode(), "no user mode present for delegation");
- ucause->IsInterrupt() = intr;
+ ucause->IsInterrupt() = bool_to_bits(intr);
ucause->Cause() = EXTZ(c);
mstatus->UPIE() = mstatus.UIE();
- mstatus->UIE() = false;
+ mstatus->UIE() = 0b0;
utval = tval(info);
uepc = pc;
@@ -339,7 +362,8 @@ function trap_handler(del_priv : Privilege, intr : bool, c : exc_code, pc : xlen
handle_trap_extension(del_priv, pc, ext);
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
prepare_trap_vector(del_priv, ucause)
}
@@ -351,48 +375,56 @@ function exception_handler(cur_priv : Privilege, ctl : ctl_result,
match (cur_priv, ctl) {
(_, CTL_TRAP(e)) => {
let del_priv = exception_delegatee(e.trap, cur_priv);
- print_platform("trapping from " ^ cur_priv ^ " to " ^ del_priv
- ^ " to handle " ^ e.trap);
- trap_handler(del_priv, false, e.trap, pc, e.excinfo, e.ext)
+ if get_config_print_platform()
+ then print_platform("trapping from " ^ to_str(cur_priv) ^ " to " ^ to_str(del_priv)
+ ^ " to handle " ^ to_str(e.trap));
+ trap_handler(del_priv, false, exceptionType_to_bits(e.trap), pc, e.excinfo, e.ext)
},
(_, CTL_MRET()) => {
let prev_priv = cur_privilege;
mstatus->MIE() = mstatus.MPIE();
- mstatus->MPIE() = true;
+ mstatus->MPIE() = 0b1;
cur_privilege = privLevel_of_bits(mstatus.MPP());
mstatus->MPP() = privLevel_to_bits(if haveUsrMode() then User else Machine);
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
- print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_platform()
+ then print_platform("ret-ing from " ^ to_str(prev_priv) ^ " to " ^ to_str(cur_privilege));
cancel_reservation();
- get_xret_target(Machine) & pc_alignment_mask()
+ prepare_xret_target(Machine) & pc_alignment_mask()
},
(_, CTL_SRET()) => {
let prev_priv = cur_privilege;
mstatus->SIE() = mstatus.SPIE();
- mstatus->SPIE() = true;
- cur_privilege = if mstatus.SPP() == true then Supervisor else User;
+ mstatus->SPIE() = 0b1;
+ cur_privilege = if mstatus.SPP() == 0b1 then Supervisor else User;
/* S-mode implies that U-mode is supported (issue 331 on riscv-isa-manual). */
- mstatus->SPP() = false;
+ mstatus->SPP() = 0b0;
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
- print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_platform()
+ then print_platform("ret-ing from " ^ to_str(prev_priv)
+ ^ " to " ^ to_str(cur_privilege));
cancel_reservation();
- get_xret_target(Supervisor) & pc_alignment_mask()
+ prepare_xret_target(Supervisor) & pc_alignment_mask()
},
(_, CTL_URET()) => {
let prev_priv = cur_privilege;
mstatus->UIE() = mstatus.UPIE();
- mstatus->UPIE() = true;
+ mstatus->UPIE() = 0b1;
cur_privilege = User;
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
- print_platform("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()));
+ if get_config_print_platform()
+ then print_platform("ret-ing from " ^ to_str(prev_priv) ^ " to " ^ to_str(cur_privilege));
cancel_reservation();
- get_xret_target(User) & pc_alignment_mask()
+ prepare_xret_target(User) & pc_alignment_mask()
}
}
}
@@ -405,7 +437,7 @@ function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = {
}
function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit =
- set_next_pc(trap_handler(del_priv, true, i, PC, None(), None()))
+ set_next_pc(trap_handler(del_priv, true, interruptType_to_bits(i), PC, None(), None()))
/* state state initialization */
@@ -415,16 +447,16 @@ function init_sys() -> unit = {
mhartid = EXTZ(0b0);
misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
- misa->A() = true; /* atomics */
- misa->C() = sys_enable_rvc (); /* RVC */
- misa->I() = true; /* base integer ISA */
- misa->M() = true; /* integer multiply/divide */
- misa->U() = true; /* user-mode */
- misa->S() = true; /* supervisor-mode */
+ misa->A() = 0b1; /* atomics */
+ misa->C() = bool_to_bits(sys_enable_rvc()); /* RVC */
+ misa->I() = 0b1; /* base integer ISA */
+ misa->M() = 0b1; /* integer multiply/divide */
+ misa->U() = 0b1; /* user-mode */
+ misa->S() = 0b1; /* supervisor-mode */
mstatus = set_mstatus_SXL(mstatus, misa.MXL());
mstatus = set_mstatus_UXL(mstatus, misa.MXL());
- mstatus->SD() = false;
+ mstatus->SD() = 0b0;
mip->bits() = EXTZ(0b0);
mie->bits() = EXTZ(0b0);
@@ -444,8 +476,11 @@ function init_sys() -> unit = {
minstret = EXTZ(0b0);
minstret_written = false;
+ init_pmp();
+
// log compatibility with spike
- print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")")
+ if get_config_print_reg()
+ then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")")
}
/* memory access exceptions, defined here for use by the platform model. */
diff --git a/model/riscv_sys_exceptions.sail b/model/riscv_sys_exceptions.sail
index d2be25f..94d869e 100644
--- a/model/riscv_sys_exceptions.sail
+++ b/model/riscv_sys_exceptions.sail
@@ -17,7 +17,13 @@ function prepare_trap_vector(p : Privilege, cause : Mcause) -> xlenbits = {
}
}
-/* used for xRET */
+/* xRET handling involves three functions:
+ *
+ * get_xret_target: used to read the value of the xret target (no control flow transfer)
+ * set_xret_target: used to write a value of the xret target (no control flow transfer)
+ * prepare_xret_target: used to get the value for control transfer to the xret target
+ */
+
val get_xret_target : Privilege -> xlenbits effect {rreg}
function get_xret_target(p) =
match p {
@@ -37,6 +43,10 @@ function set_xret_target(p, value) = {
target
}
+val prepare_xret_target : (Privilege) -> xlenbits effect {rreg, wreg}
+function prepare_xret_target(p) =
+ get_xret_target(p)
+
/* other trap-related CSRs */
function get_mtvec() -> xlenbits =
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 7b5b9e6..143fd35 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -80,8 +80,8 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
if sys_enable_writable_misa ()
then { /* Allow modifications to C only for now. */
let v = Mk_Misa(v);
- /* Suppress changing C if nextPC would become misaligned. */
- if v.C() == false & nextPC[1] == true
+ /* Suppress changing C if nextPC would become misaligned or C was disabled at boot. */
+ if (v.C() == 0b0 & nextPC[1] == bitone) | ~(sys_enable_rvc())
then m
else update_C(m, v.C())
}
@@ -90,12 +90,12 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
/* helpers to check support for various extensions. */
/* we currently don't model 'E', so always assume 'I'. */
-function haveAtomics() -> bool = misa.A() == true
-function haveRVC() -> bool = misa.C() == true
-function haveMulDiv() -> bool = misa.M() == true
-function haveSupMode() -> bool = misa.S() == true
-function haveUsrMode() -> bool = misa.U() == true
-function haveNExt() -> bool = misa.N() == true
+function haveAtomics() -> bool = misa.A() == 0b1
+function haveRVC() -> bool = misa.C() == 0b1
+function haveMulDiv() -> bool = misa.M() == 0b1
+function haveSupMode() -> bool = misa.S() == 0b1
+function haveUsrMode() -> bool = misa.U() == 0b1
+function haveNExt() -> bool = misa.N() == 0b1
bitfield Mstatus : xlenbits = {
SD : xlen - 1,
@@ -128,6 +128,11 @@ bitfield Mstatus : xlenbits = {
}
register mstatus : Mstatus
+function effectivePrivilege(m : Mstatus, priv : Privilege) -> Privilege =
+ if m.MPRV() == 0b1
+ then privLevel_of_bits(mstatus.MPP())
+ else cur_privilege
+
function get_mstatus_SXL(m : Mstatus) -> arch_xlen = {
if sizeof(xlen) == 32
then arch_to_bits(RV32)
@@ -169,17 +174,19 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = {
*/
// let m = update_FS(m, extStatus_to_bits(Off));
- let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty
- | extStatus_of_bits(m.XS()) == Dirty);
+ let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty;
+ let m = update_SD(m, bool_to_bits(dirty));
/* We don't support dynamic changes to SXL and UXL. */
let m = set_mstatus_SXL(m, get_mstatus_SXL(o));
let m = set_mstatus_UXL(m, get_mstatus_UXL(o));
/* Hardwired to zero in the absence of 'N'. */
- let m = update_UPIE(m, false);
- let m = update_UIE(m, false);
- m
+ if (~ (haveUsrMode())) then {
+ let m = update_UPIE(m, 0b0);
+ let m = update_UIE(m, 0b0);
+ m
+ } else m
}
/* architecture and extension checks */
@@ -256,9 +263,9 @@ function legalize_mideleg(o : Minterrupts, v : xlenbits) -> Minterrupts = {
/* M-mode interrupt delegation bits "should" be hardwired to 0. */
/* FIXME: needs verification against eventual spec language. */
let m = Mk_Minterrupts(v);
- let m = update_MEI(m, false);
- let m = update_MTI(m, false);
- let m = update_MSI(m, false);
+ let m = update_MEI(m, 0b0);
+ let m = update_MTI(m, 0b0);
+ let m = update_MSI(m, 0b0);
m
}
@@ -285,7 +292,7 @@ register medeleg : Medeleg /* Delegation to S-mode */
function legalize_medeleg(o : Medeleg, v : xlenbits) -> Medeleg = {
let m = Mk_Medeleg(v);
/* M-EnvCalls delegation is not supported */
- let m = update_MEnvCall(m, false);
+ let m = update_MEnvCall(m, 0b0);
m
}
@@ -317,7 +324,7 @@ function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = {
let base : xlenbits = m.Base() @ 0b00;
match (trapVectorMode_of_bits(m.Mode())) {
TV_Direct => Some(base),
- TV_Vector => if c.IsInterrupt() == true
+ TV_Vector => if c.IsInterrupt() == 0b1
then Some(base + (EXTZ(c.Cause()) << 2))
else Some(base),
TV_Reserved => None()
@@ -332,13 +339,15 @@ register mepc : xlenbits
* When misa.C is writable, it zeroes only xepc[0].
*/
function legalize_xepc(v : xlenbits) -> xlenbits =
- if sys_enable_writable_misa () | misa.C() == true
+ /* allow writing xepc[1] only if misa.C is enabled or could be enabled
+ XXX specification says this legalization should be done on read */
+ if (sys_enable_writable_misa() & sys_enable_rvc()) | misa.C() == 0b1
then [v with 0 = bitzero]
else v & EXTS(0b100)
/* masking for reads to xepc */
function pc_alignment_mask() -> xlenbits =
- ~(EXTZ(if misa.C() == true then 0b00 else 0b10))
+ ~(EXTZ(if misa.C() == 0b1 then 0b00 else 0b10))
/* auxiliary exception registers */
@@ -359,17 +368,17 @@ register scounteren : Counteren
function legalize_mcounteren(c : Counteren, v : xlenbits) -> Counteren = {
/* no HPM counters yet */
- let c = update_IR(c, v[2]);
- let c = update_TM(c, v[1]);
- let c = update_CY(c, v[0]);
+ let c = update_IR(c, [v[2]]);
+ let c = update_TM(c, [v[1]]);
+ let c = update_CY(c, [v[0]]);
c
}
function legalize_scounteren(c : Counteren, v : xlenbits) -> Counteren = {
/* no HPM counters yet */
- let c = update_IR(c, v[2]);
- let c = update_TM(c, v[1]);
- let c = update_CY(c, v[0]);
+ let c = update_IR(c, [v[2]]);
+ let c = update_TM(c, [v[1]]);
+ let c = update_CY(c, [v[0]]);
c
}
@@ -403,11 +412,6 @@ register marchid : xlenbits
/* TODO: this should be readonly, and always 0 for now */
register mhartid : xlenbits
-/* physical memory protection configuration */
-register pmpaddr0 : xlenbits
-register pmpcfg0 : xlenbits
-
-
/* S-mode registers */
/* sstatus reveals a subset of mstatus */
@@ -462,8 +466,8 @@ function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
let m = update_XS(m, s.XS());
// See comment for mstatus.FS.
let m = update_FS(m, s.FS());
- let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty
- | extStatus_of_bits(m.XS()) == Dirty);
+ let dirty = extStatus_of_bits(m.FS()) == Dirty | extStatus_of_bits(m.XS()) == Dirty;
+ let m = update_SD(m, bool_to_bits(dirty));
let m = update_SPP(m, s.SPP());
let m = update_SPIE(m, s.SPIE());
@@ -535,8 +539,8 @@ function lift_sip(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterru
let m : Minterrupts = o;
let m = update_SSI(m, s.SSI() & d.SSI());
if haveNExt() then {
- let m = if d.UEI() == true then update_UEI(m, s.UEI()) else m;
- let m = if d.USI() == true then update_USI(m, s.USI()) else m;
+ let m = if d.UEI() == 0b1 then update_UEI(m, s.UEI()) else m;
+ let m = if d.USI() == 0b1 then update_USI(m, s.USI()) else m;
m
} else m
}
@@ -548,13 +552,13 @@ function legalize_sip(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterr
/* Returns the new value of mie from the previous mie (o) and the written sie (s) as delegated by mideleg (d). */
function lift_sie(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = {
let m : Minterrupts = o;
- let m = if d.SEI() == true then update_SEI(m, s.SEI()) else m;
- let m = if d.STI() == true then update_STI(m, s.STI()) else m;
- let m = if d.SSI() == true then update_SSI(m, s.SSI()) else m;
+ let m = if d.SEI() == 0b1 then update_SEI(m, s.SEI()) else m;
+ let m = if d.STI() == 0b1 then update_STI(m, s.STI()) else m;
+ let m = if d.SSI() == 0b1 then update_SSI(m, s.SSI()) else m;
if haveNExt() then {
- let m = if d.UEI() == true then update_UEI(m, s.UEI()) else m;
- let m = if d.UTI() == true then update_UTI(m, s.UTI()) else m;
- let m = if d.USI() == true then update_USI(m, s.USI()) else m;
+ let m = if d.UEI() == 0b1 then update_UEI(m, s.UEI()) else m;
+ let m = if d.UTI() == 0b1 then update_UTI(m, s.UTI()) else m;
+ let m = if d.USI() == 0b1 then update_USI(m, s.USI()) else m;
m
} else m
}
diff --git a/model/riscv_termination_duo.sail b/model/riscv_termination_duo.sail
new file mode 100644
index 0000000..74ee253
--- /dev/null
+++ b/model/riscv_termination_duo.sail
@@ -0,0 +1 @@
+termination_measure n_leading_spaces s = string_length(s)
diff --git a/model/riscv_termination_rv64.sail b/model/riscv_termination_rv64.sail
index 18005b8..48b9ce7 100644
--- a/model/riscv_termination_rv64.sail
+++ b/model/riscv_termination_rv64.sail
@@ -1,2 +1,2 @@
-termination_measure walk39(_,_,_,_,_,_,level,_) = level
-termination_measure walk48(_,_,_,_,_,_,level,_) = level
+termination_measure walk39(_,_,_,_,_,_,level,_, _) = level
+termination_measure walk48(_,_,_,_,_,_,level,_, _) = level
diff --git a/model/riscv_types.sail b/model/riscv_types.sail
index 1cb595e..cacf0db 100644
--- a/model/riscv_types.sail
+++ b/model/riscv_types.sail
@@ -22,7 +22,7 @@ type csreg = bits(12) /* CSR addressing */
type regno ('n : Int), 0 <= 'n < 32 = atom('n)
-val cast regidx_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)}
+val regidx_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)}
function regidx_to_regno b = let 'r = unsigned(b) in r
/* mapping RVC register indices into normal indices */
@@ -65,7 +65,7 @@ function arch_to_bits(a : Architecture) -> arch_xlen =
type priv_level = bits(2)
enum Privilege = {User, Supervisor, Machine}
-val cast privLevel_to_bits : Privilege -> priv_level
+val privLevel_to_bits : Privilege -> priv_level
function privLevel_to_bits (p) =
match (p) {
User => 0b00,
@@ -73,7 +73,7 @@ function privLevel_to_bits (p) =
Machine => 0b11
}
-val cast privLevel_of_bits : priv_level -> Privilege
+val privLevel_of_bits : priv_level -> Privilege
function privLevel_of_bits (p) =
match (p) {
0b00 => User,
@@ -81,7 +81,7 @@ function privLevel_of_bits (p) =
0b11 => Machine
}
-val cast privLevel_to_str : Privilege -> string
+val privLevel_to_str : Privilege -> string
function privLevel_to_str (p) =
match (p) {
User => "U",
@@ -89,31 +89,20 @@ function privLevel_to_str (p) =
Machine => "M"
}
+overload to_str = {privLevel_to_str}
+
/* enum denoting whether an executed instruction retires */
enum Retired = {RETIRE_SUCCESS, RETIRE_FAIL}
/* memory access types */
-enum AccessType = {Read, Write, ReadWrite, Execute}
-
-val cast accessType_to_str : AccessType -> string
-function accessType_to_str (a) =
- match (a) {
- Read => "R",
- Write => "W",
- ReadWrite => "RW",
- Execute => "X"
- }
-
-enum ReadType = {Instruction, Data}
-
-val cast readType_to_str : ReadType -> string
-function readType_to_str (r) =
- match (r) {
- Instruction => "I",
- Data => "D"
- }
+union AccessType ('a : Type) = {
+ Read : 'a,
+ Write : 'a,
+ ReadWrite : 'a,
+ Execute : unit
+}
enum word_width = {BYTE, HALF, WORD, DOUBLE}
@@ -133,7 +122,7 @@ enum InterruptType = {
I_M_External
}
-val cast interruptType_to_bits : InterruptType -> exc_code
+val interruptType_to_bits : InterruptType -> exc_code
function interruptType_to_bits (i) =
match (i) {
I_U_Software => 0x00,
@@ -149,76 +138,103 @@ function interruptType_to_bits (i) =
/* architectural exception definitions */
-enum ExceptionType = {
- E_Fetch_Addr_Align,
- E_Fetch_Access_Fault,
- E_Illegal_Instr,
- E_Breakpoint,
- E_Load_Addr_Align,
- E_Load_Access_Fault,
- E_SAMO_Addr_Align,
- E_SAMO_Access_Fault,
- E_U_EnvCall,
- E_S_EnvCall,
- E_Reserved_10,
- E_M_EnvCall,
- E_Fetch_Page_Fault,
- E_Load_Page_Fault,
- E_Reserved_14,
- E_SAMO_Page_Fault,
+union ExceptionType = {
+ E_Fetch_Addr_Align : unit,
+ E_Fetch_Access_Fault : unit,
+ E_Illegal_Instr : unit,
+ E_Breakpoint : unit,
+ E_Load_Addr_Align : unit,
+ E_Load_Access_Fault : unit,
+ E_SAMO_Addr_Align : unit,
+ E_SAMO_Access_Fault : unit,
+ E_U_EnvCall : unit,
+ E_S_EnvCall : unit,
+ E_Reserved_10 : unit,
+ E_M_EnvCall : unit,
+ E_Fetch_Page_Fault : unit,
+ E_Load_Page_Fault : unit,
+ E_Reserved_14 : unit,
+ E_SAMO_Page_Fault : unit,
/* extensions */
- E_CHERI
+ E_Extension : ext_exc_type
}
-val cast exceptionType_to_bits : ExceptionType -> exc_code
+val exceptionType_to_bits : ExceptionType -> exc_code
function exceptionType_to_bits(e) =
match (e) {
- E_Fetch_Addr_Align => 0x00,
- E_Fetch_Access_Fault => 0x01,
- E_Illegal_Instr => 0x02,
- E_Breakpoint => 0x03,
- E_Load_Addr_Align => 0x04,
- E_Load_Access_Fault => 0x05,
- E_SAMO_Addr_Align => 0x06,
- E_SAMO_Access_Fault => 0x07,
- E_U_EnvCall => 0x08,
- E_S_EnvCall => 0x09,
- E_Reserved_10 => 0x0a,
- E_M_EnvCall => 0x0b,
- E_Fetch_Page_Fault => 0x0c,
- E_Load_Page_Fault => 0x0d,
- E_Reserved_14 => 0x0e,
- E_SAMO_Page_Fault => 0x0f,
+ E_Fetch_Addr_Align() => 0x00,
+ E_Fetch_Access_Fault() => 0x01,
+ E_Illegal_Instr() => 0x02,
+ E_Breakpoint() => 0x03,
+ E_Load_Addr_Align() => 0x04,
+ E_Load_Access_Fault() => 0x05,
+ E_SAMO_Addr_Align() => 0x06,
+ E_SAMO_Access_Fault() => 0x07,
+ E_U_EnvCall() => 0x08,
+ E_S_EnvCall() => 0x09,
+ E_Reserved_10() => 0x0a,
+ E_M_EnvCall() => 0x0b,
+ E_Fetch_Page_Fault() => 0x0c,
+ E_Load_Page_Fault() => 0x0d,
+ E_Reserved_14() => 0x0e,
+ E_SAMO_Page_Fault() => 0x0f,
/* extensions */
- E_CHERI => 0x20 /* FIXME: this is reserved for a future standard */
+ E_Extension(e) => 0x18 /* First code for a custom extension */
}
-val cast exceptionType_to_str : ExceptionType -> string
+val num_of_ExceptionType : ExceptionType -> {'n, (0 <= 'n < xlen). int('n)}
+function num_of_ExceptionType(e) =
+ match (e) {
+ E_Fetch_Addr_Align() => 0,
+ E_Fetch_Access_Fault() => 1,
+ E_Illegal_Instr() => 2,
+ E_Breakpoint() => 3,
+ E_Load_Addr_Align() => 4,
+ E_Load_Access_Fault() => 5,
+ E_SAMO_Addr_Align() => 6,
+ E_SAMO_Access_Fault() => 7,
+ E_U_EnvCall() => 8,
+ E_S_EnvCall() => 9,
+ E_Reserved_10() => 10,
+ E_M_EnvCall() => 11,
+ E_Fetch_Page_Fault() => 12,
+ E_Load_Page_Fault() => 13,
+ E_Reserved_14() => 14,
+ E_SAMO_Page_Fault() => 15,
+
+ /* extensions */
+ E_Extension(e) => 24 /* First code for a custom extension */
+
+ }
+
+val exceptionType_to_str : ExceptionType -> string
function exceptionType_to_str(e) =
match (e) {
- E_Fetch_Addr_Align => "misaligned-fetch",
- E_Fetch_Access_Fault => "fetch-access-fault",
- E_Illegal_Instr => "illegal-instruction",
- E_Breakpoint => "breakpoint",
- E_Load_Addr_Align => "misaligned-load",
- E_Load_Access_Fault => "load-access-fault",
- E_SAMO_Addr_Align => "misaliged-store/amo",
- E_SAMO_Access_Fault => "store/amo-access-fault",
- E_U_EnvCall => "u-call",
- E_S_EnvCall => "s-call",
- E_Reserved_10 => "reserved-0",
- E_M_EnvCall => "m-call",
- E_Fetch_Page_Fault => "fetch-page-fault",
- E_Load_Page_Fault => "load-page-fault",
- E_Reserved_14 => "reserved-1",
- E_SAMO_Page_Fault => "store/amo-page-fault",
+ E_Fetch_Addr_Align() => "misaligned-fetch",
+ E_Fetch_Access_Fault() => "fetch-access-fault",
+ E_Illegal_Instr() => "illegal-instruction",
+ E_Breakpoint() => "breakpoint",
+ E_Load_Addr_Align() => "misaligned-load",
+ E_Load_Access_Fault() => "load-access-fault",
+ E_SAMO_Addr_Align() => "misaliged-store/amo",
+ E_SAMO_Access_Fault() => "store/amo-access-fault",
+ E_U_EnvCall() => "u-call",
+ E_S_EnvCall() => "s-call",
+ E_Reserved_10() => "reserved-0",
+ E_M_EnvCall() => "m-call",
+ E_Fetch_Page_Fault() => "fetch-page-fault",
+ E_Load_Page_Fault() => "load-page-fault",
+ E_Reserved_14() => "reserved-1",
+ E_SAMO_Page_Fault() => "store/amo-page-fault",
/* extensions */
- E_CHERI => "CHERI"
+ E_Extension(e) => "extension-exception"
}
+overload to_str = {exceptionType_to_str}
+
/* model-internal exceptions */
union exception = {
@@ -240,7 +256,7 @@ function internal_error(s) = {
type tv_mode = bits(2)
enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved}
-val cast trapVectorMode_of_bits : tv_mode -> TrapVectorMode
+val trapVectorMode_of_bits : tv_mode -> TrapVectorMode
function trapVectorMode_of_bits (m) =
match (m) {
0b00 => TV_Direct,
@@ -253,7 +269,7 @@ function trapVectorMode_of_bits (m) =
type ext_status = bits(2)
enum ExtStatus = {Off, Initial, Clean, Dirty}
-val cast extStatus_to_bits : ExtStatus -> ext_status
+val extStatus_to_bits : ExtStatus -> ext_status
function extStatus_to_bits(e) =
match (e) {
Off => 0b00,
@@ -262,7 +278,7 @@ function extStatus_to_bits(e) =
Dirty => 0b11
}
-val cast extStatus_of_bits : ext_status -> ExtStatus
+val extStatus_of_bits : ext_status -> ExtStatus
function extStatus_of_bits(e) =
match (e) {
0b00 => Off,
diff --git a/model/riscv_types_ext.sail b/model/riscv_types_ext.sail
new file mode 100644
index 0000000..5a05c39
--- /dev/null
+++ b/model/riscv_types_ext.sail
@@ -0,0 +1,22 @@
+/* accumulator for information collected during PTW */
+
+/* This type is an accumulator; it is carried through the page-table
+ * walk, and folds in information along the walk, currently from the
+ * PTE checks from each PTE that is processed along the way.
+ */
+type ext_ptw = unit /* No extensions for page-table-walks */
+
+let init_ext_ptw : ext_ptw = () /* initial value of the accumulator */
+
+/* This type can be used for custom errors for page-table-walks,
+ * and values in this type are typically generated from the final
+ * result of the ext_ptw at the end of the walk.
+ */
+type ext_ptw_error = unit /* No extensions for page-table-walk errors */
+
+/* This type supports extensions to the exceptions defined in the ISA. */
+type ext_exc_type = unit /* No exception extensions */
+
+/* Default translation of PTW errors into exception annotations */
+function ext_translate_exception(e : ext_ptw_error) -> ext_exc_type =
+ e
diff --git a/model/riscv_vmem_common.sail b/model/riscv_vmem_common.sail
index c153579..7f1b8eb 100644
--- a/model/riscv_vmem_common.sail
+++ b/model/riscv_vmem_common.sail
@@ -8,93 +8,6 @@
let PAGESIZE_BITS = 12
-/* PTE attributes, permission checks and updates */
-
-type pteAttribs = bits(8)
-
-bitfield PTE_Bits : pteAttribs = {
- D : 7,
- A : 6,
- G : 5,
- U : 4,
- X : 3,
- W : 2,
- R : 1,
- V : 0
-}
-
-function isPTEPtr(p : pteAttribs) -> bool = {
- let a = Mk_PTE_Bits(p);
- a.R() == false & a.W() == false & a.X() == false
-}
-
-function isInvalidPTE(p : pteAttribs) -> bool = {
- let a = Mk_PTE_Bits(p);
- a.V() == false | (a.W() == true & a.R() == false)
-}
-
-function checkPTEPermission(ac : AccessType, priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits) -> bool = {
- match (ac, priv) {
- (Read, User) => p.U() == true & (p.R() == true | (p.X() == true & mxr)),
- (Write, User) => p.U() == true & p.W() == true,
- (ReadWrite, User) => p.U() == true & p.W() == true & (p.R() == true | (p.X() == true & mxr)),
- (Execute, User) => p.U() == true & p.X() == true,
-
- (Read, Supervisor) => (p.U() == false | do_sum) & (p.R() == true | (p.X() == true & mxr)),
- (Write, Supervisor) => (p.U() == false | do_sum) & p.W() == true,
- (ReadWrite, Supervisor) => (p.U() == false | do_sum) & p.W() == true & (p.R() == true | (p.X() == true & mxr)),
- (Execute, Supervisor) => p.U() == false & p.X() == true,
-
- (_, Machine) => internal_error("m-mode mem perm check")
- }
-}
-
-function update_PTE_Bits(p : PTE_Bits, a : AccessType) -> option(PTE_Bits) = {
- let update_d = (a == Write | a == ReadWrite) & p.D() == false; // dirty-bit
- let update_a = p.A() == false; // accessed-bit
- if update_d | update_a then {
- let np = update_A(p, true);
- let np = if update_d then update_D(np, true) else np;
- Some(np)
- } else None()
-}
-
-/* failure modes for address-translation/page-table-walks */
-enum PTW_Error = {
- PTW_Access, /* physical memory access error for a PTE */
- PTW_Invalid_PTE,
- PTW_No_Permission,
- PTW_Misaligned, /* misaligned superpage */
- PTW_PTE_Update /* PTE update needed but not enabled */
-}
-val cast ptw_error_to_str : PTW_Error -> string
-function ptw_error_to_str(e) =
- match (e) {
- PTW_Access => "mem-access-error",
- PTW_Invalid_PTE => "invalid-pte",
- PTW_No_Permission => "no-permission",
- PTW_Misaligned => "misaligned-superpage",
- PTW_PTE_Update => "pte-update-needed"
- }
-
-/* conversion of these translation/PTW failures into architectural exceptions */
-function translationException(a : AccessType, f : PTW_Error) -> ExceptionType = {
- let e : ExceptionType =
- match (a, f) {
- (ReadWrite, PTW_Access) => E_SAMO_Access_Fault,
- (ReadWrite, _) => E_SAMO_Page_Fault,
- (Read, PTW_Access) => E_Load_Access_Fault,
- (Read, _) => E_Load_Page_Fault,
- (Write, PTW_Access) => E_SAMO_Access_Fault,
- (Write, _) => E_SAMO_Page_Fault,
- (Fetch, PTW_Access) => E_Fetch_Access_Fault,
- (Fetch, _) => E_Fetch_Page_Fault
- } in {
-/* print("translationException(" ^ a ^ ", " ^ f ^ ") -> " ^ e); */
- e
- }
-}
-
/*
* Definitions for RV32, which has a single address translation mode: Sv32.
*/
@@ -193,6 +106,7 @@ bitfield SV39_Paddr : paddr64 = {
}
bitfield SV39_PTE : pte64 = {
+ Ext : 63 .. 54,
PPNi : 53 .. 10,
RSW : 9 .. 8,
BITS : 7 .. 0
@@ -219,21 +133,27 @@ bitfield SV48_Paddr : paddr64 = {
}
bitfield SV48_PTE : pte48 = {
+ Ext : 63 .. 54,
PPNi : 53 .. 10,
RSW : 9 .. 8,
BITS : 7 .. 0
}
-/* Result of a page-table walk. */
+/* The types below are parameterized by 'paddr and 'pte to support
+ * various architectural widths (e.g. RV32, RV64). ext_ptw supports
+ * extensions to the default address translation and page-table-walk.
+ */
+
+/* Result of a page-table walk. */
union PTW_Result('paddr : Type, 'pte : Type) = {
- PTW_Success: ('paddr, 'pte, 'paddr, nat, bool),
- PTW_Failure: PTW_Error
+ PTW_Success: ('paddr, 'pte, 'paddr, nat, bool, ext_ptw),
+ PTW_Failure: (PTW_Error, ext_ptw)
}
/* Result of address translation */
union TR_Result('paddr : Type, 'failure : Type) = {
- TR_Address : 'paddr,
- TR_Failure : 'failure
+ TR_Address : ('paddr, ext_ptw),
+ TR_Failure : ('failure, ext_ptw)
}
diff --git a/model/riscv_vmem_rv32.sail b/model/riscv_vmem_rv32.sail
index f26e29e..4ff7891 100644
--- a/model/riscv_vmem_rv32.sail
+++ b/model/riscv_vmem_rv32.sail
@@ -17,7 +17,7 @@ function translationMode(priv) = {
match arch {
Some(RV32) => {
let s = Mk_Satp32(satp[31..0]);
- if s.Mode() == false then Sbare else Sv32
+ if s.Mode() == 0b0 then Sbare else Sv32
},
_ => internal_error("unsupported address translation arch")
}
@@ -26,26 +26,27 @@ function translationMode(priv) = {
/* Top-level address translation dispatcher */
-val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg}
-function translateAddr(vAddr, ac, rt) = {
- let effPriv : Privilege = match rt {
- Instruction => cur_privilege,
- Data => if mstatus.MPRV() == true
- then privLevel_of_bits(mstatus.MPP())
- else cur_privilege
+val translateAddr : (xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg}
+function translateAddr(vAddr, ac) = {
+ let effPriv : Privilege = match ac {
+ Execute() => cur_privilege,
+ _ => effectivePrivilege(mstatus, cur_privilege)
};
- let mxr : bool = mstatus.MXR() == true;
- let do_sum : bool = mstatus.SUM() == true;
+ let mxr : bool = mstatus.MXR() == 0b1;
+ let do_sum : bool = mstatus.SUM() == 0b1;
let mode : SATPMode = translationMode(effPriv);
let asid = curAsid32(satp);
let ptb = curPTB32(satp);
+ /* PTW extensions: initialize the PTW extension state */
+ let ext_ptw : ext_ptw = init_ext_ptw;
+
match mode {
- Sbare => TR_Address(vAddr),
- Sv32 => match translate32(asid, ptb, vAddr, ac, effPriv, mxr, do_sum, SV32_LEVELS - 1) {
- TR_Address(pa) => TR_Address(to_phys_addr(pa)),
- TR_Failure(f) => TR_Failure(translationException(ac, f))
+ Sbare => TR_Address(vAddr, ext_ptw),
+ Sv32 => match translate32(asid, ptb, vAddr, ac, effPriv, mxr, do_sum, SV32_LEVELS - 1, ext_ptw) {
+ TR_Address(pa, ext_ptw) => TR_Address(to_phys_addr(pa), ext_ptw),
+ TR_Failure(f, ext_ptw) => TR_Failure(translationException(ac, f), ext_ptw)
},
_ => internal_error("unsupported address translation scheme")
}
diff --git a/model/riscv_vmem_rv64.sail b/model/riscv_vmem_rv64.sail
index 538dd36..c55e9dc 100644
--- a/model/riscv_vmem_rv64.sail
+++ b/model/riscv_vmem_rv64.sail
@@ -24,7 +24,7 @@ function translationMode(priv) = {
},
Some(RV32) => {
let s = Mk_Satp32(satp[31..0]);
- if s.Mode() == false then Sbare else Sv32
+ if s.Mode() == 0b0 then Sbare else Sv32
},
_ => internal_error("unsupported address translation arch")
}
@@ -33,30 +33,31 @@ function translationMode(priv) = {
/* Top-level address translation dispatcher */
-val translateAddr : (xlenbits, AccessType, ReadType) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg}
-function translateAddr(vAddr, ac, rt) = {
- let effPriv : Privilege = match rt {
- Instruction => cur_privilege,
- Data => if mstatus.MPRV() == true
- then privLevel_of_bits(mstatus.MPP())
- else cur_privilege
+val translateAddr : (xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rreg, wmv, wmvt, wreg}
+function translateAddr(vAddr, ac) = {
+ let effPriv : Privilege = match ac {
+ Execute() => cur_privilege,
+ _ => effectivePrivilege(mstatus, cur_privilege)
};
- let mxr : bool = mstatus.MXR() == true;
- let do_sum : bool = mstatus.SUM() == true;
+ let mxr : bool = mstatus.MXR() == 0b1;
+ let do_sum : bool = mstatus.SUM() == 0b1;
let mode : SATPMode = translationMode(effPriv);
let asid = curAsid64(satp);
let ptb = curPTB64(satp);
+ /* PTW extensions: initialize the PTW extension state. */
+ let ext_ptw : ext_ptw = init_ext_ptw;
+
match mode {
- Sbare => TR_Address(vAddr),
- Sv39 => match translate39(asid, ptb, vAddr[38 .. 0], ac, effPriv, mxr, do_sum, SV39_LEVELS - 1) {
- TR_Address(pa) => TR_Address(EXTZ(pa)),
- TR_Failure(f) => TR_Failure(translationException(ac, f))
+ Sbare => TR_Address(vAddr, ext_ptw),
+ Sv39 => match translate39(asid, ptb, vAddr[38 .. 0], ac, effPriv, mxr, do_sum, SV39_LEVELS - 1, ext_ptw) {
+ TR_Address(pa, ext_ptw) => TR_Address(EXTZ(pa), ext_ptw),
+ TR_Failure(f, ext_ptw) => TR_Failure(translationException(ac, f), ext_ptw)
},
- Sv48 => match translate48(asid, ptb, vAddr[47 .. 0], ac, effPriv, mxr, do_sum, SV48_LEVELS - 1) {
- TR_Address(pa) => TR_Address(EXTZ(pa)),
- TR_Failure(f) => TR_Failure(translationException(ac, f))
+ Sv48 => match translate48(asid, ptb, vAddr[47 .. 0], ac, effPriv, mxr, do_sum, SV48_LEVELS - 1, ext_ptw) {
+ TR_Address(pa, ext_ptw) => TR_Address(EXTZ(pa), ext_ptw),
+ TR_Failure(f, ext_ptw) => TR_Failure(translationException(ac, f), ext_ptw)
},
_ => internal_error("unsupported address translation scheme")
}
diff --git a/model/riscv_vmem_sv32.sail b/model/riscv_vmem_sv32.sail
index 5561f09..e535915 100644
--- a/model/riscv_vmem_sv32.sail
+++ b/model/riscv_vmem_sv32.sail
@@ -6,70 +6,73 @@
function to_phys_addr(a : paddr32) -> xlenbits = a[31..0]
-val walk32 : (vaddr32, AccessType, Privilege, bool, bool, paddr32, nat, bool) -> PTW_Result(paddr32, SV32_PTE) effect {rmem, escape}
-function walk32(vaddr, ac, priv, mxr, do_sum, ptb, level, global) = {
+val walk32 : (vaddr32, AccessType(ext_access_type), Privilege, bool, bool, paddr32, nat, bool, ext_ptw) -> PTW_Result(paddr32, SV32_PTE) effect {rmem, rreg, escape}
+function walk32(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = {
let va = Mk_SV32_Vaddr(vaddr);
let pt_ofs : paddr32 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV32_LEVEL_BITS))[(SV32_LEVEL_BITS - 1) .. 0]),
PTE32_LOG_SIZE);
let pte_addr = ptb + pt_ofs;
- /* FIXME: we assume here that walks only access physical-memory-backed addresses, and not MMIO regions. */
- match (phys_mem_read(Data, to_phys_addr(pte_addr), 4, false, false, false)) {
+ match (mem_read(ac, to_phys_addr(pte_addr), 4, false, false, false)) {
MemException(_) => {
/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(to_phys_addr(ptb))
^ " pt_ofs=" ^ BitStr(to_phys_addr(pt_ofs))
^ " pte_addr=" ^ BitStr(to_phys_addr(pte_addr))
^ ": invalid pte address"); */
- PTW_Failure(PTW_Access)
+ PTW_Failure(PTW_Access(), ext_ptw)
},
MemValue(v) => {
let pte = Mk_SV32_PTE(v);
let pbits = pte.BITS();
+ let ext_pte : extPte = zeros(); // no reserved bits for extensions
let pattr = Mk_PTE_Bits(pbits);
- let is_global = global | (pattr.G() == true);
+ let is_global = global | (pattr.G() == 0b1);
/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(to_phys_addr(ptb))
^ " pt_ofs=" ^ BitStr(to_phys_addr(pt_ofs))
^ " pte_addr=" ^ BitStr(to_phys_addr(pte_addr))
^ " pte=" ^ BitStr(v)); */
- if isInvalidPTE(pbits) then {
+ if isInvalidPTE(pbits, ext_pte) then {
/* print("walk32: invalid pte"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
- if isPTEPtr(pbits) then {
+ if isPTEPtr(pbits, ext_pte) then {
if level == 0 then {
/* last-level PTE contains a pointer instead of a leaf */
/* print("walk32: last-level pte contains a ptr"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
/* walk down the pointer to the next level */
- walk32(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global)
+ walk32(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global, ext_ptw)
}
} else { /* leaf PTE */
- if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then {
-/* print("walk32: pte permission check failure"); */
- PTW_Failure(PTW_No_Permission)
- } else {
- if level > 0 then { /* superpage */
- /* fixme hack: to get a mask of appropriate size */
- let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV32_LEVEL_BITS) - 1;
- if (pte.PPNi() & mask) != EXTZ(0b0) then {
- /* misaligned superpage mapping */
-/* print("walk32: misaligned superpage mapping"); */
- PTW_Failure(PTW_Misaligned)
+ match checkPTEPermission(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) {
+ PTE_Check_Failure(ext_ptw) => {
+/* print("walk32: pte permission check failure"); */
+ PTW_Failure(PTW_No_Permission(), ext_ptw)
+ },
+ PTE_Check_Success(ext_ptw) => {
+ if level > 0 then { /* superpage */
+ /* fixme hack: to get a mask of appropriate size */
+ let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV32_LEVEL_BITS) - 1;
+ if (pte.PPNi() & mask) != EXTZ(0b0) then {
+ /* misaligned superpage mapping */
+/* print("walk32: misaligned superpage mapping"); */
+ PTW_Failure(PTW_Misaligned(), ext_ptw)
+ } else {
+ /* add the appropriate bits of the VPN to the superpage PPN */
+ let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
+/* let res = append(ppn, va.PgOfs());
+ print("walk32: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
+ ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
+ }
} else {
- /* add the appropriate bits of the VPN to the superpage PPN */
- let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
-/* let res = append(ppn, va.PgOfs());
- print("walk32: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
- ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global)
+ /* normal leaf PTE */
+/* let res = append(pte.PPNi(), va.PgOfs());
+ print("walk32: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
}
- } else {
- /* normal leaf PTE */
-/* let res = append(pte.PPNi(), va.PgOfs());
- print("walk32: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global)
}
}
}
@@ -112,64 +115,68 @@ function flush_TLB32(asid, addr) =
/* address translation */
-val translate32 : (asid32, paddr32, vaddr32, AccessType, Privilege, bool, bool, nat) -> TR_Result(paddr32, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
-function translate32(asid, ptb, vAddr, ac, priv, mxr, do_sum, level) = {
+val translate32 : (asid32, paddr32, vaddr32, AccessType(ext_access_type), Privilege, bool, bool, nat, ext_ptw) -> TR_Result(paddr32, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
+function translate32(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = {
match lookup_TLB32(asid, vAddr) {
Some(idx, ent) => {
/* print("translate32: TLB32 hit for " ^ BitStr(vAddr)); */
let pte = Mk_SV32_PTE(ent.pte);
+ let ext_pte : extPte = zeros(); // no reserved bits for extensions
let pteBits = Mk_PTE_Bits(pte.BITS());
- if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pteBits))
- then TR_Failure(PTW_No_Permission)
- else {
- match update_PTE_Bits(pteBits, ac) {
- None() => TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask)),
- Some(pbits) => {
- if ~ (plat_enable_dirty_update ())
- then {
- /* pte needs dirty/accessed update but that is not enabled */
- TR_Failure(PTW_PTE_Update)
- } else {
- /* update PTE entry and TLB */
- n_pte = update_BITS(pte, pbits.bits());
- n_ent : TLB32_Entry = ent;
- n_ent.pte = n_pte.bits();
- write_TLB32(idx, n_ent);
- /* update page table */
- match checked_mem_write(to_phys_addr(EXTZ(ent.pteAddr)), 4, n_pte.bits(), default_meta, false, false, false) {
- MemValue(_) => (),
- MemException(e) => internal_error("invalid physical address in TLB")
- };
- TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask))
+ match checkPTEPermission(ac, priv, mxr, do_sum, pteBits, ext_pte, ext_ptw) {
+ PTE_Check_Failure(ext_ptw) => { TR_Failure(PTW_No_Permission(), ext_ptw) },
+ PTE_Check_Success(ext_ptw) => {
+ match update_PTE_Bits(pteBits, ac, ext_pte) {
+ None() => TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask), ext_ptw),
+ Some(pbits, ext) => {
+ if ~ (plat_enable_dirty_update ())
+ then {
+ /* pte needs dirty/accessed update but that is not enabled */
+ TR_Failure(PTW_PTE_Update(), ext_ptw)
+ } else {
+ /* update PTE entry and TLB */
+ n_pte = update_BITS(pte, pbits.bits());
+ /* ext is unused since there are no reserved bits for extensions */
+ n_ent : TLB32_Entry = ent;
+ n_ent.pte = n_pte.bits();
+ write_TLB32(idx, n_ent);
+ /* update page table */
+ match mem_write_value(to_phys_addr(EXTZ(ent.pteAddr)), 4, n_pte.bits(), false, false, false) {
+ MemValue(_) => (),
+ MemException(e) => internal_error("invalid physical address in TLB")
+ };
+ TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask), ext_ptw)
+ }
}
}
}
}
},
None() => {
- match walk32(vAddr, ac, priv, mxr, do_sum, ptb, level, false) {
- PTW_Failure(f) => TR_Failure(f),
- PTW_Success(pAddr, pte, pteAddr, level, global) => {
- match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac) {
+ match walk32(vAddr, ac, priv, mxr, do_sum, ptb, level, false, ext_ptw) {
+ PTW_Failure(f, ext_ptw) => TR_Failure(f, ext_ptw),
+ PTW_Success(pAddr, pte, pteAddr, level, global, ext_ptw) => {
+ match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac, zeros()) {
None() => {
add_to_TLB32(asid, vAddr, pAddr, pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
- Some(pbits) =>
+ Some(pbits, ext) =>
if ~ (plat_enable_dirty_update ())
then {
/* pte needs dirty/accessed update but that is not enabled */
- TR_Failure(PTW_PTE_Update)
+ TR_Failure(PTW_PTE_Update(), ext_ptw)
} else {
w_pte : SV32_PTE = update_BITS(pte, pbits.bits());
- match checked_mem_write(to_phys_addr(pteAddr), 4, w_pte.bits(), default_meta, false, false, false) {
+ /* ext is unused since there are no reserved bits for extensions */
+ match mem_write_value(to_phys_addr(pteAddr), 4, w_pte.bits(), false, false, false) {
MemValue(_) => {
add_to_TLB32(asid, vAddr, pAddr, w_pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
MemException(e) => {
/* pte is not in valid memory */
- TR_Failure(PTW_Access)
+ TR_Failure(PTW_Access(), ext_ptw)
}
}
}
diff --git a/model/riscv_vmem_sv39.sail b/model/riscv_vmem_sv39.sail
index 53cc549..a1edc4e 100644
--- a/model/riscv_vmem_sv39.sail
+++ b/model/riscv_vmem_sv39.sail
@@ -1,69 +1,72 @@
/* Sv39 address translation for RV64. */
-val walk39 : (vaddr39, AccessType, Privilege, bool, bool, paddr64, nat, bool) -> PTW_Result(paddr64, SV39_PTE) effect {rmem, escape}
-function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) = {
+val walk39 : (vaddr39, AccessType(ext_access_type), Privilege, bool, bool, paddr64, nat, bool, ext_ptw) -> PTW_Result(paddr64, SV39_PTE) effect {rmem, rreg, escape}
+function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = {
let va = Mk_SV39_Vaddr(vaddr);
let pt_ofs : paddr64 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]),
PTE39_LOG_SIZE);
let pte_addr = ptb + pt_ofs;
- /* FIXME: we assume here that walks only access physical-memory-backed addresses, and not MMIO regions. */
- match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) {
+ match (mem_read(ac, EXTZ(pte_addr), 8, false, false, false)) {
MemException(_) => {
/* print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(ptb)
^ " pt_ofs=" ^ BitStr(pt_ofs)
^ " pte_addr=" ^ BitStr(pte_addr)
^ ": invalid pte address"); */
- PTW_Failure(PTW_Access)
+ PTW_Failure(PTW_Access(), ext_ptw)
},
MemValue(v) => {
let pte = Mk_SV39_PTE(v);
let pbits = pte.BITS();
+ let ext_pte = pte.Ext();
let pattr = Mk_PTE_Bits(pbits);
- let is_global = global | (pattr.G() == true);
+ let is_global = global | (pattr.G() == 0b1);
/* print("walk39(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(ptb)
^ " pt_ofs=" ^ BitStr(pt_ofs)
^ " pte_addr=" ^ BitStr(pte_addr)
^ " pte=" ^ BitStr(v)); */
- if isInvalidPTE(pbits) then {
+ if isInvalidPTE(pbits, ext_pte) then {
/* print("walk39: invalid pte"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
- if isPTEPtr(pbits) then {
+ if isPTEPtr(pbits, ext_pte) then {
if level == 0 then {
/* last-level PTE contains a pointer instead of a leaf */
/* print("walk39: last-level pte contains a ptr"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
/* walk down the pointer to the next level */
- walk39(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global)
+ walk39(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global, ext_ptw)
}
} else { /* leaf PTE */
- if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then {
-/* print("walk39: pte permission check failure"); */
- PTW_Failure(PTW_No_Permission)
- } else {
- if level > 0 then { /* superpage */
- /* fixme hack: to get a mask of appropriate size */
- let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV39_LEVEL_BITS) - 1;
- if (pte.PPNi() & mask) != EXTZ(0b0) then {
- /* misaligned superpage mapping */
-/* print("walk39: misaligned superpage mapping"); */
- PTW_Failure(PTW_Misaligned)
+ match checkPTEPermission(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) {
+ PTE_Check_Failure(ext_ptw) => {
+/* print("walk39: pte permission check failure"); */
+ PTW_Failure(PTW_No_Permission(), ext_ptw)
+ },
+ PTE_Check_Success(ext_ptw) => {
+ if level > 0 then { /* superpage */
+ /* fixme hack: to get a mask of appropriate size */
+ let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV39_LEVEL_BITS) - 1;
+ if (pte.PPNi() & mask) != EXTZ(0b0) then {
+ /* misaligned superpage mapping */
+/* print("walk39: misaligned superpage mapping"); */
+ PTW_Failure(PTW_Misaligned(), ext_ptw)
+ } else {
+ /* add the appropriate bits of the VPN to the superpage PPN */
+ let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
+/* let res = append(ppn, va.PgOfs());
+ print("walk39: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
+ ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
+ }
} else {
- /* add the appropriate bits of the VPN to the superpage PPN */
- let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
-/* let res = append(ppn, va.PgOfs());
- print("walk39: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
- ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global)
+ /* normal leaf PTE */
+/* let res = append(pte.PPNi(), va.PgOfs());
+ print("walk39: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
}
- } else {
- /* normal leaf PTE */
-/* let res = append(pte.PPNi(), va.PgOfs());
- print("walk39: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global)
}
}
}
@@ -106,64 +109,68 @@ function flush_TLB39(asid, addr) =
/* address translation */
-val translate39 : (asid64, paddr64, vaddr39, AccessType, Privilege, bool, bool, nat) -> TR_Result(paddr64, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
-function translate39(asid, ptb, vAddr, ac, priv, mxr, do_sum, level) = {
+val translate39 : (asid64, paddr64, vaddr39, AccessType(ext_access_type), Privilege, bool, bool, nat, ext_ptw) -> TR_Result(paddr64, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
+function translate39(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = {
match lookup_TLB39(asid, vAddr) {
Some(idx, ent) => {
/* print("translate39: TLB39 hit for " ^ BitStr(vAddr)); */
let pte = Mk_SV39_PTE(ent.pte);
+ let ext_pte = pte.Ext();
let pteBits = Mk_PTE_Bits(pte.BITS());
- if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pteBits))
- then TR_Failure(PTW_No_Permission)
- else {
- match update_PTE_Bits(pteBits, ac) {
- None() => TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask)),
- Some(pbits) => {
- if ~ (plat_enable_dirty_update ())
- then {
- /* pte needs dirty/accessed update but that is not enabled */
- TR_Failure(PTW_PTE_Update)
- } else {
- /* update PTE entry and TLB */
- n_pte = update_BITS(pte, pbits.bits());
- n_ent : TLB39_Entry = ent;
- n_ent.pte = n_pte.bits();
- write_TLB39(idx, n_ent);
- /* update page table */
- match checked_mem_write(EXTZ(ent.pteAddr), 8, n_pte.bits(), default_meta, false, false, false) {
- MemValue(_) => (),
- MemException(e) => internal_error("invalid physical address in TLB")
- };
- TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask))
+ match checkPTEPermission(ac, priv, mxr, do_sum, pteBits, ext_pte, ext_ptw) {
+ PTE_Check_Failure(ext_ptw) => { TR_Failure(PTW_No_Permission(), ext_ptw) },
+ PTE_Check_Success(ext_ptw) => {
+ match update_PTE_Bits(pteBits, ac, ext_pte) {
+ None() => TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask), ext_ptw),
+ Some(pbits, ext) => {
+ if ~ (plat_enable_dirty_update ())
+ then {
+ /* pte needs dirty/accessed update but that is not enabled */
+ TR_Failure(PTW_PTE_Update(), ext_ptw)
+ } else {
+ /* update PTE entry and TLB */
+ n_pte = update_BITS(pte, pbits.bits());
+ n_pte = update_Ext(n_pte, ext);
+ n_ent : TLB39_Entry = ent;
+ n_ent.pte = n_pte.bits();
+ write_TLB39(idx, n_ent);
+ /* update page table */
+ match mem_write_value(EXTZ(ent.pteAddr), 8, n_pte.bits(), false, false, false) {
+ MemValue(_) => (),
+ MemException(e) => internal_error("invalid physical address in TLB")
+ };
+ TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask), ext_ptw)
+ }
}
}
}
}
},
None() => {
- match walk39(vAddr, ac, priv, mxr, do_sum, ptb, level, false) {
- PTW_Failure(f) => TR_Failure(f),
- PTW_Success(pAddr, pte, pteAddr, level, global) => {
- match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac) {
+ match walk39(vAddr, ac, priv, mxr, do_sum, ptb, level, false, ext_ptw) {
+ PTW_Failure(f, ext_ptw) => TR_Failure(f, ext_ptw),
+ PTW_Success(pAddr, pte, pteAddr, level, global, ext_ptw) => {
+ match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac, pte.Ext()) {
None() => {
add_to_TLB39(asid, vAddr, pAddr, pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
- Some(pbits) =>
+ Some(pbits, ext) =>
if ~ (plat_enable_dirty_update ())
then {
/* pte needs dirty/accessed update but that is not enabled */
- TR_Failure(PTW_PTE_Update)
+ TR_Failure(PTW_PTE_Update(), ext_ptw)
} else {
w_pte : SV39_PTE = update_BITS(pte, pbits.bits());
- match checked_mem_write(EXTZ(pteAddr), 8, w_pte.bits(), default_meta, false, false, false) {
+ w_pte : SV39_PTE = update_Ext(w_pte, ext);
+ match mem_write_value(EXTZ(pteAddr), 8, w_pte.bits(), false, false, false) {
MemValue(_) => {
add_to_TLB39(asid, vAddr, pAddr, w_pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
MemException(e) => {
/* pte is not in valid memory */
- TR_Failure(PTW_Access)
+ TR_Failure(PTW_Access(), ext_ptw)
}
}
}
diff --git a/model/riscv_vmem_sv48.sail b/model/riscv_vmem_sv48.sail
index c1b4246..6bfeea4 100644
--- a/model/riscv_vmem_sv48.sail
+++ b/model/riscv_vmem_sv48.sail
@@ -1,69 +1,72 @@
/* Sv48 address translation for RV64. */
-val walk48 : (vaddr48, AccessType, Privilege, bool, bool, paddr64, nat, bool) -> PTW_Result(paddr64, SV48_PTE) effect {rmem, escape}
-function walk48(vaddr, ac, priv, mxr, do_sum, ptb, level, global) = {
+val walk48 : (vaddr48, AccessType(ext_access_type), Privilege, bool, bool, paddr64, nat, bool, ext_ptw) -> PTW_Result(paddr64, SV48_PTE) effect {rmem, rreg, escape}
+function walk48(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = {
let va = Mk_SV48_Vaddr(vaddr);
let pt_ofs : paddr64 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV48_LEVEL_BITS))[(SV48_LEVEL_BITS - 1) .. 0]),
PTE48_LOG_SIZE);
let pte_addr = ptb + pt_ofs;
- /* FIXME: we assume here that walks only access physical-memory-backed addresses, and not MMIO regions. */
- match (phys_mem_read(Data, EXTZ(pte_addr), 8, false, false, false)) {
+ match (mem_read(ac, EXTZ(pte_addr), 8, false, false, false)) {
MemException(_) => {
/* print("walk48(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(ptb)
^ " pt_ofs=" ^ BitStr(pt_ofs)
^ " pte_addr=" ^ BitStr(pte_addr)
^ ": invalid pte address"); */
- PTW_Failure(PTW_Access)
+ PTW_Failure(PTW_Access(), ext_ptw)
},
MemValue(v) => {
let pte = Mk_SV48_PTE(v);
let pbits = pte.BITS();
+ let ext_pte = pte.Ext();
let pattr = Mk_PTE_Bits(pbits);
- let is_global = global | (pattr.G() == true);
+ let is_global = global | (pattr.G() == 0b1);
/* print("walk48(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level)
^ " pt_base=" ^ BitStr(ptb)
^ " pt_ofs=" ^ BitStr(pt_ofs)
^ " pte_addr=" ^ BitStr(pte_addr)
^ " pte=" ^ BitStr(v)); */
- if isInvalidPTE(pbits) then {
+ if isInvalidPTE(pbits, ext_pte) then {
/* print("walk48: invalid pte"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
- if isPTEPtr(pbits) then {
+ if isPTEPtr(pbits, ext_pte) then {
if level == 0 then {
/* last-level PTE contains a pointer instead of a leaf */
/* print("walk48: last-level pte contains a ptr"); */
- PTW_Failure(PTW_Invalid_PTE)
+ PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
} else {
/* walk down the pointer to the next level */
- walk48(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global)
+ walk48(vaddr, ac, priv, mxr, do_sum, shiftl(EXTZ(pte.PPNi()), PAGESIZE_BITS), level - 1, is_global, ext_ptw)
}
} else { /* leaf PTE */
- if ~ (checkPTEPermission(ac, priv, mxr, do_sum, pattr)) then {
-/* print("walk48: pte permission check failure"); */
- PTW_Failure(PTW_No_Permission)
- } else {
- if level > 0 then { /* superpage */
- /* fixme hack: to get a mask of appropriate size */
- let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV48_LEVEL_BITS) - 1;
- if (pte.PPNi() & mask) != EXTZ(0b0) then {
- /* misaligned superpage mapping */
-/* print("walk48: misaligned superpage mapping"); */
- PTW_Failure(PTW_Misaligned)
+ match checkPTEPermission(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) {
+ PTE_Check_Failure(ext_ptw) => {
+/* print("walk48: pte permission check failure"); */
+ PTW_Failure(PTW_No_Permission(), ext_ptw)
+ },
+ PTE_Check_Success(ext_ptw) => {
+ if level > 0 then { /* superpage */
+ /* fixme hack: to get a mask of appropriate size */
+ let mask = shiftl(pte.PPNi() ^ pte.PPNi() ^ EXTZ(0b1), level * SV48_LEVEL_BITS) - 1;
+ if (pte.PPNi() & mask) != EXTZ(0b0) then {
+ /* misaligned superpage mapping */
+/* print("walk48: misaligned superpage mapping"); */
+ PTW_Failure(PTW_Misaligned(), ext_ptw)
+ } else {
+ /* add the appropriate bits of the VPN to the superpage PPN */
+ let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
+/* let res = append(ppn, va.PgOfs());
+ print("walk48: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
+ ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
+ }
} else {
- /* add the appropriate bits of the VPN to the superpage PPN */
- let ppn = pte.PPNi() | (EXTZ(va.VPNi()) & mask);
-/* let res = append(ppn, va.PgOfs());
- print("walk48: using superpage: pte.ppn=" ^ BitStr(pte.PPNi())
- ^ " ppn=" ^ BitStr(ppn) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global)
+ /* normal leaf PTE */
+/* let res = append(pte.PPNi(), va.PgOfs());
+ print("walk48: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
+ PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global, ext_ptw)
}
- } else {
- /* normal leaf PTE */
-/* let res = append(pte.PPNi(), va.PgOfs());
- print("walk48: pte.ppn=" ^ BitStr(pte.PPNi()) ^ " ppn=" ^ BitStr(pte.PPNi()) ^ " res=" ^ BitStr(res)); */
- PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global)
}
}
}
@@ -106,31 +109,32 @@ function flush_TLB48(asid, addr) =
/* address translation */
-val translate48 : (asid64, paddr64, vaddr48, AccessType, Privilege, bool, bool, nat) -> TR_Result(paddr64, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
-function translate48(asid, ptb, vAddr, ac, priv, mxr, do_sum, level) = {
- match walk48(vAddr, ac, priv, mxr, do_sum, ptb, level, false) {
- PTW_Failure(f) => TR_Failure(f),
- PTW_Success(pAddr, pte, pteAddr, level, global) => {
- match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac) {
+val translate48 : (asid64, paddr64, vaddr48, AccessType(ext_access_type), Privilege, bool, bool, nat, ext_ptw) -> TR_Result(paddr64, PTW_Error) effect {rreg, wreg, wmv, wmvt, escape, rmem}
+function translate48(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = {
+ match walk48(vAddr, ac, priv, mxr, do_sum, ptb, level, false, ext_ptw) {
+ PTW_Failure(f, ext_ptw) => TR_Failure(f, ext_ptw),
+ PTW_Success(pAddr, pte, pteAddr, level, global, ext_ptw) => {
+ match update_PTE_Bits(Mk_PTE_Bits(pte.BITS()), ac, pte.Ext()) {
None() => {
add_to_TLB48(asid, vAddr, pAddr, pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
- Some(pbits) =>
+ Some(pbits, ext) =>
if ~ (plat_enable_dirty_update ())
then {
/* pte needs dirty/accessed update but that is not enabled */
- TR_Failure(PTW_PTE_Update)
+ TR_Failure(PTW_PTE_Update(), ext_ptw)
} else {
w_pte : SV48_PTE = update_BITS(pte, pbits.bits());
- match checked_mem_write(EXTZ(pteAddr), 8, w_pte.bits(), default_meta, false, false, false) {
+ w_pte : SV48_PTE = update_Ext(w_pte, ext);
+ match mem_write_value(EXTZ(pteAddr), 8, w_pte.bits(), false, false, false) {
MemValue(_) => {
add_to_TLB48(asid, vAddr, pAddr, w_pte, pteAddr, level, global);
- TR_Address(pAddr)
+ TR_Address(pAddr, ext_ptw)
},
MemException(e) => {
/* pte is not in valid memory */
- TR_Failure(PTW_Access)
+ TR_Failure(PTW_Access(), ext_ptw)
}
}
}
diff --git a/model/riscv_vmem_types.sail b/model/riscv_vmem_types.sail
new file mode 100644
index 0000000..bf5551d
--- /dev/null
+++ b/model/riscv_vmem_types.sail
@@ -0,0 +1,18 @@
+// Extensions for memory Accesstype.
+
+type ext_access_type = unit
+
+let Data : ext_access_type = ()
+
+let default_write_acc : ext_access_type = Data
+
+val accessType_to_str : AccessType(ext_access_type) -> string
+function accessType_to_str (a) =
+ match (a) {
+ Read(Data) => "R",
+ Write(Data) => "W",
+ ReadWrite(Data) => "RW",
+ Execute() => "X"
+ }
+
+overload to_str = {accessType_to_str}
diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml
index 11abaf1..b2a19fe 100644
--- a/ocaml_emulator/platform.ml
+++ b/ocaml_emulator/platform.ml
@@ -9,6 +9,7 @@ let config_enable_writable_misa = ref true
let config_enable_dirty_update = ref false
let config_enable_misaligned_access = ref false
let config_mtval_has_illegal_inst_bits = ref false
+let config_enable_pmp = ref false
let platform_arch = ref P.RV64
@@ -39,6 +40,11 @@ let print_platform s =
then print_endline s
else ()
+let get_config_print_instr () = !config_print_instr
+let get_config_print_reg () = !config_print_reg
+let get_config_print_mem () = !config_print_mem_access
+let get_config_print_platform () = !config_print_platform
+
(* Mapping to Sail externs *)
let cur_arch_bitwidth () =
match !platform_arch with
@@ -72,6 +78,7 @@ let enable_rvc () = !config_enable_rvc
let enable_dirty_update () = !config_enable_dirty_update
let enable_misaligned_access () = !config_enable_misaligned_access
let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits
+let enable_pmp () = !config_enable_pmp
let rom_base () = arch_bits_of_int64 P.rom_base
let rom_size () = arch_bits_of_int !rom_size_ref
diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml
index 5f5c716..f827ad5 100644
--- a/ocaml_emulator/riscv_ocaml_sim.ml
+++ b/ocaml_emulator/riscv_ocaml_sim.ml
@@ -37,6 +37,9 @@ let options = Arg.align ([("-dump-dts",
("-enable-misaligned-access",
Arg.Set P.config_enable_misaligned_access,
" enable misaligned accesses without M-mode traps");
+ ("-enable-pmp",
+ Arg.Set P.config_enable_pmp,
+ " enable PMP support");
("-mtval-has-illegal-inst-bits",
Arg.Set P.config_mtval_has_illegal_inst_bits,
" mtval stores instruction bits on an illegal instruction exception");
diff --git a/opam b/opam
index dc44622..fb65f9a 100644
--- a/opam
+++ b/opam
@@ -1,6 +1,6 @@
opam-version: "1.2"
name: "sail-riscv"
-version: "0.1"
+version: "0.3"
maintainer: "Sail Devs <cl-sail-dev@lists.cam.ac.uk>"
authors: [
"Alasdair Armstrong"
@@ -17,14 +17,11 @@ homepage: "https://github.com/rems-project/sail-riscv/"
bug-reports: "https://github.com/rems-project/sail-riscv/issues"
license: "BSD3"
dev-repo: "https://github.com/rems-project/sail-riscv.git"
-build: [make "INSTALL_DIR=%{prefix}%" "opam-build"]
-install: [make "INSTALL_DIR=%{prefix}%" "opam-install"]
-remove: [
- make "INSTALL_DIR=%{prefix}%" "opam-uninstall"
-]
+build: [make "LEM_DIR=%{lem:share}%" "SAIL_DIR=%{sail:share}%" "SAIL=sail" "opam-build"]
depends: [
"ocamlfind"
"ocamlbuild"
+ "lem"
"sail" {>= "0.9"}
"linksem" {>= "0.3"}
"conf-gmp"
diff --git a/os-boot/README.md b/os-boot/README.md
index 4d80d39..087abac 100644
--- a/os-boot/README.md
+++ b/os-boot/README.md
@@ -10,6 +10,13 @@ interrupt controller). Console input is not currently supported.
32-bit OS boots require a workaround for the 64-bit HTIF interface,
which is currently not supported.
+OS boots use device-tree binary blobs generated by the `dtc` compiler,
+installable on Ubuntu and Debian machines with
+
+```
+sudo apt install device-tree-compiler
+```
+
Booting Linux with the C backend
--------------------------------
@@ -49,45 +56,15 @@ Caveats for OS boot
platform. This will not be needed once the C model can generate its
own DTB.
-Sample OS images
-----------------
-
-This directory contains some sample OS images and support files built
-for the basic platform implemented by the model. They were built with
-toolchains that emitted illegal instructions, and require the model to
-be patched to boot them:
+Sample Linux image
+------------------
-```
-patch -p1 < os-boot/os-boot-patch.diff
-```
-
-The device-tree for the 64-bit Sail model is described in `rv64-64mb.dts`. This file
-can be generated using:
-```
-./ocaml_emulator/riscv_ocaml_sim_RV64 -dump-dts > os-boot/rv64-64mb.dts
-```
+`rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl` contains a sample Linux RV64
+image that can be booted as follows, after first generating the
+device-tree blob for a 64MB RV64 machine using `dtc`:
-The device-tree binary for OS boots can be compiled from that source file:
```
dtc < os-boot/rv64-64mb.dts > os-boot/rv64-64mb.dtb
-```
-
-The 64-bit Linux image can then be booted as:
-```
-./c_emulator/riscv_sim_RV64 -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/linux-rv64-64mb.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
+./c_emulator/riscv_sim_RV64 -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl > >(gzip -c > execution-trace.log.gz) 2>&1
tail -f /tmp/console.log
```
-
-The 64-bit FreeBSD image requires hardware PTE update support (`-d`):
-```
-./c_emulator/riscv_sim_RV64 -d -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/freebsd-rv64.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
-```
-
-The 64-bit seL4 image runs its test-suite and requires more memory (`-z`):
-```
-dtc < os-boot/rv64-2gb.dts > os-boot/rv64-2gb.dtb
-./c_emulator/riscv_sim_RV64 -z 2048 -b os-boot/rv64-2gb.dtb -t /tmp/console.log os-boot/sel4-rv64.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
-```
-
-Note that the consistency of the `-z` argument and the contents of the
-DTB have to be ensured manually for now.
diff --git a/os-boot/image-notes.txt b/os-boot/image-notes.txt
new file mode 100644
index 0000000..f517f87
--- /dev/null
+++ b/os-boot/image-notes.txt
@@ -0,0 +1,39 @@
+This directory contains some sample OS images and support files built
+for the basic platform implemented by the model. They were built with
+toolchains that emitted illegal instructions, and require the model to
+be patched to boot them:
+
+```
+patch -p1 < os-boot/os-boot-patch.diff
+```
+
+The device-tree for the 64-bit Sail model is described in `rv64-64mb.dts`. This file
+can be generated using:
+```
+./ocaml_emulator/riscv_ocaml_sim_RV64 -dump-dts > os-boot/rv64-64mb.dts
+```
+
+The device-tree binary for OS boots can be compiled from that source file:
+```
+dtc < os-boot/rv64-64mb.dts > os-boot/rv64-64mb.dtb
+```
+
+The 64-bit Linux image can then be booted as:
+```
+./c_emulator/riscv_sim_RV64 -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/linux-rv64-64mb.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
+tail -f /tmp/console.log
+```
+
+The 64-bit FreeBSD image requires hardware PTE update support (`-d`):
+```
+./c_emulator/riscv_sim_RV64 -d -b os-boot/rv64-64mb.dtb -t /tmp/console.log os-boot/freebsd-rv64.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
+```
+
+The 64-bit seL4 image runs its test-suite and requires more memory (`-z`):
+```
+dtc < os-boot/rv64-2gb.dts > os-boot/rv64-2gb.dtb
+./c_emulator/riscv_sim_RV64 -z 2048 -b os-boot/rv64-2gb.dtb -t /tmp/console.log os-boot/sel4-rv64.bbl > >(gzip -c - > /tmp/exec-trace.log.gz) 2>&1
+```
+
+Note that the consistency of the `-z` argument and the contents of the
+DTB have to be ensured manually for now.
diff --git a/os-boot/os-boot-patch.diff b/os-boot/os-boot-patch.diff
index 03d0c30..f4f1a52 100644
--- a/os-boot/os-boot-patch.diff
+++ b/os-boot/os-boot-patch.diff
@@ -1,42 +1,49 @@
-diff --git a/model/prelude_mem.sail b/model/prelude_mem.sail
-index 8e483f8..8c68192 100644
---- a/model/prelude_mem.sail
-+++ b/model/prelude_mem.sail
-@@ -29,8 +29,8 @@ function __RISCV_write (addr, width, data, aq, rl, con) =
- (false, true, true) => __WriteRAM_conditional_release(sizeof(xlen), width, EXTZ(0x0), addr, data),
- (true, true, false) => __WriteRAM_strong_release(sizeof(xlen), width, EXTZ(0x0), addr, data),
- (true, true, true) => __WriteRAM_conditional_strong_release(sizeof(xlen), width, EXTZ(0x0), addr, data),
-- (true, false, false) => false,
-- (true, false, true) => false
-+ (true, false, false) => __WriteRAM(sizeof(xlen), width, EXTZ(0x0), addr, data),//false
-+ (true, false, true) => __WriteRAM(sizeof(xlen), width, EXTZ(0x0), addr, data) //false
- }
-
- val __TraceMemoryWrite : forall 'n 'm.
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail
-index 3549e80..1d77e6b 100644
+index 256d6de4..45640229 100644
--- a/model/riscv_mem.sail
+++ b/model/riscv_mem.sail
-@@ -88,9 +88,9 @@ function mem_write_ea (addr, width, aq, rl, con) = {
- (false, true, false) => MemValue(MEMea_release(addr, width)),
- (false, false, true) => MemValue(MEMea_conditional(addr, width)),
- (false, true , true) => MemValue(MEMea_conditional_release(addr, width)),
+@@ -28,8 +28,8 @@ function phys_mem_read forall 'n, 'n > 0. (t : AccessType, addr : xlenbits, widt
+ (false, false, true) => Some(read_ram(Read_RISCV_reserved, addr, width)),
+ (true, false, true) => Some(read_ram(Read_RISCV_reserved_acquire, addr, width)),
+ (true, true, true) => Some(read_ram(Read_RISCV_reserved_strong_acquire, addr, width)),
+- (false, true, false) => None(), /* should these be instead throwing error_not_implemented as below? */
+- (false, true, true) => None()
++ (false, true, false) => Some(read_ram(Read_plain, addr, width)),
++ (false, true, true) => Some(read_ram(Read_plain, addr, width))
+ }) : option(bits(8 * 'n));
+ match (t, result) {
+ (Execute, None()) => MemException(E_Fetch_Access_Fault),
+@@ -91,8 +91,8 @@ function mem_read (typ, addr, width, aq, rl, res) = {
+ if (aq | res) & (~ (is_aligned_addr(addr, width)))
+ then MemException(E_Load_Addr_Align)
+ else match (aq, rl, res) {
+- (false, true, false) => throw(Error_not_implemented("load.rl")),
+- (false, true, true) => throw(Error_not_implemented("lr.rl")),
++ (false, true, false) => pmp_mem_read(typ, addr, width, aq, rl, res),
++ (false, true, true) => pmp_mem_read(typ, addr, width, aq, rl, res),
+ (_, _, _) => pmp_mem_read(typ, addr, width, aq, rl, res)
+ };
+ rvfi_read(addr, width, result);
+@@ -109,9 +109,9 @@ function mem_write_ea (addr, width, aq, rl, con) = {
+ (false, true, false) => MemValue(write_ram_ea(Write_RISCV_release, addr, width)),
+ (false, false, true) => MemValue(write_ram_ea(Write_RISCV_conditional, addr, width)),
+ (false, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_release, addr, width)),
- (true, false, false) => throw(Error_not_implemented("store.aq")),
-+ (true, false, false) => MemValue(MEMea(addr, width)),//throw(Error_not_implemented("store.aq")),
- (true, true, false) => MemValue(MEMea_strong_release(addr, width)),
++ (true, false, false) => MemValue(write_ram_ea(Write_plain, addr, width)),
+ (true, true, false) => MemValue(write_ram_ea(Write_RISCV_strong_release, addr, width)),
- (true, false, true) => throw(Error_not_implemented("sc.aq")),
-+ (true, false, true) => MemValue(MEMea(addr, width)),//throw(Error_not_implemented("sc.aq")),
- (true, true , true) => MemValue(MEMea_conditional_strong_release(addr, width))
++ (true, false, true) => MemValue(write_ram_ea(Write_plain, addr, width)),
+ (true, true , true) => MemValue(write_ram_ea(Write_RISCV_conditional_strong_release, addr, width))
}
}
-@@ -133,8 +133,8 @@ function mem_write_value (addr, width, value, aq, rl, con) = {
- if (rl | con) & (~ (is_aligned_addr(addr, width)))
- then MemException(E_SAMO_Addr_Align)
- else match (aq, rl, con) {
+@@ -176,8 +176,8 @@ function mem_write_value_meta (addr, width, value, meta, aq, rl, con) = {
+ (true, true, false) => pmp_mem_write(Write_RISCV_strong_release, addr, width, value, meta),
+ (true, true , true) => pmp_mem_write(Write_RISCV_conditional_strong_release, addr, width, value, meta),
+ // throw an illegal instruction here?
- (true, false, false) => throw(Error_not_implemented("store.aq")),
-- (true, false, true) => throw(Error_not_implemented("sc.aq")),
-+ (true, false, false) => checked_mem_write(addr, width, value, aq, rl, con),//throw(Error_not_implemented("store.aq")),
-+ (true, false, true) => checked_mem_write(addr, width, value, aq, rl, con),//throw(Error_not_implemented("sc.aq")),
- (_, _, _) => checked_mem_write(addr, width, value, aq, rl, con)
+- (true, false, true) => throw(Error_not_implemented("sc.aq"))
++ (true, false, false) => pmp_mem_write(Write_plain, addr, width, value, meta),
++ (true, false, true) => pmp_mem_write(Write_plain, addr, width, value, meta)
}
}
+
diff --git a/os-boot/rv64-2gb-hafnium.dts b/os-boot/rv64-2gb-hafnium.dts
new file mode 100644
index 0000000..d67bfb2
--- /dev/null
+++ b/os-boot/rv64-2gb-hafnium.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "ucbbar,spike-bare-dev";
+ model = "ucbbar,spike-bare";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <10000000>;
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imac";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <1000000000>;
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "ucbbar,spike-bare-soc", "simple-bus";
+ ranges;
+ clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ };
+ };
+ htif {
+ compatible = "ucb,htif0";
+ };
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ linux,initrd-end = <0 0>;
+ linux,initrd-start = <0 0>;
+ bootargs = "rdinit=/sbin/init";
+ stdout-path = "";
+ };
+};
diff --git a/os-boot/rv64-hafnium-054a7a-linux-4.20.0-gcc-8.3.0-2gb.bbl b/os-boot/rv64-hafnium-054a7a-linux-4.20.0-gcc-8.3.0-2gb.bbl
new file mode 100755
index 0000000..abc018f
--- /dev/null
+++ b/os-boot/rv64-hafnium-054a7a-linux-4.20.0-gcc-8.3.0-2gb.bbl
Binary files differ
diff --git a/os-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl b/os-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl
new file mode 100755
index 0000000..701f06e
--- /dev/null
+++ b/os-boot/rv64-linux-4.15.0-gcc-7.2.0-64mb.bbl
Binary files differ
diff --git a/prover_snapshots/README.md b/prover_snapshots/README.md
new file mode 100644
index 0000000..c8c23bf
--- /dev/null
+++ b/prover_snapshots/README.md
@@ -0,0 +1,6 @@
+# Snapshots of theorem prover definitions
+
+This directory contains snapshots of definitions generated from the Sail RISC-V
+specification for the interactive theorem provers Isabelle/HOL, HOL4, and Coq.
+These snapshots are provided for convenience, and are not guaranteed to be
+up-to-date.
diff --git a/prover_snapshots/coq/.gitignore b/prover_snapshots/coq/.gitignore
new file mode 100644
index 0000000..9b243d9
--- /dev/null
+++ b/prover_snapshots/coq/.gitignore
@@ -0,0 +1,5 @@
+*.vo
+*.glob
+.*.aux
+deps
+.*.cache
diff --git a/prover_snapshots/coq/README.md b/prover_snapshots/coq/README.md
new file mode 100644
index 0000000..a709cfc
--- /dev/null
+++ b/prover_snapshots/coq/README.md
@@ -0,0 +1,7 @@
+Check out a copy of <https://github.com/mit-plv/bbv> in the parent directory and
+build it. Then run `./build`.
+
+The models were built with
+* `sail` commit `ba6d82bd`
+* `sail-riscv` commit `503cb6e`
+and checked against bbv commit `143c47b` and coq 8.9.0.
diff --git a/prover_snapshots/coq/RV32/riscv.v b/prover_snapshots/coq/RV32/riscv.v
new file mode 100644
index 0000000..5aa28ac
--- /dev/null
+++ b/prover_snapshots/coq/RV32/riscv.v
@@ -0,0 +1,42479 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Require Import riscv_types.
+Require Import riscv_extras.
+Import ListNotations.
+Open Scope string.
+Open Scope bool.
+Section Content.
+
+Definition is_none {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => true | None => false end.
+
+Definition eq_unit (_ : unit) (_ : unit)
+: {_bool : bool & ArithFact (_bool = true)} :=
+
+ build_ex(true).
+
+Definition neq_int (x : Z) (y : Z)
+: {_bool : bool & ArithFact (iff (_bool = true) (x <> y))} :=
+
+ build_ex(negb (Z.eqb x y)).
+
+Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y).
+
+Definition __id (x : Z) : {_retval : Z & ArithFact (_retval = x)} := build_ex(x).
+
+Definition concat_str_bits {n : Z} (str : string) (x : mword n)
+: string :=
+
+ String.append str (string_of_bits x).
+
+Definition concat_str_dec (str : string) (x : Z) : string := String.append str (dec_str x).
+
+
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)}
+: mword len :=
+
+ if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len
+ else zero_extend v len.
+
+Definition sail_ones (n : Z) `{ArithFact (n >= 0)} : mword n := not_vec (zeros n).
+
+Definition slice_mask (n : Z) (i : Z) (l : Z) `{ArithFact (n >= 0)}
+: mword n :=
+
+ if sumbool_of_bool ((Z.geb l n)) then shiftl (sail_ones n) i
+ else
+ let one : bits n := sail_mask n ((vec_of_bits [B1] : mword 1) : bits 1) in
+ shiftl (sub_vec (shiftl one l) one) i.
+
+Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)}
+: read_kind :=
+
+ let l__203 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__203 0)) then Read_plain
+ else if sumbool_of_bool ((Z.eqb l__203 1)) then Read_reserve
+ else if sumbool_of_bool ((Z.eqb l__203 2)) then Read_acquire
+ else if sumbool_of_bool ((Z.eqb l__203 3)) then Read_exclusive
+ else if sumbool_of_bool ((Z.eqb l__203 4)) then Read_exclusive_acquire
+ else if sumbool_of_bool ((Z.eqb l__203 5)) then Read_stream
+ else if sumbool_of_bool ((Z.eqb l__203 6)) then Read_RISCV_acquire
+ else if sumbool_of_bool ((Z.eqb l__203 7)) then Read_RISCV_strong_acquire
+ else if sumbool_of_bool ((Z.eqb l__203 8)) then Read_RISCV_reserved
+ else if sumbool_of_bool ((Z.eqb l__203 9)) then Read_RISCV_reserved_acquire
+ else if sumbool_of_bool ((Z.eqb l__203 10)) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked.
+
+Definition num_of_read_kind (arg_ : read_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 11)} :=
+
+ build_ex(match arg_ with
+ | Read_plain => 0
+ | Read_reserve => 1
+ | Read_acquire => 2
+ | Read_exclusive => 3
+ | Read_exclusive_acquire => 4
+ | Read_stream => 5
+ | Read_RISCV_acquire => 6
+ | Read_RISCV_strong_acquire => 7
+ | Read_RISCV_reserved => 8
+ | Read_RISCV_reserved_acquire => 9
+ | Read_RISCV_reserved_strong_acquire => 10
+ | Read_X86_locked => 11
+ end).
+
+Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: write_kind :=
+
+ let l__193 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__193 0)) then Write_plain
+ else if sumbool_of_bool ((Z.eqb l__193 1)) then Write_conditional
+ else if sumbool_of_bool ((Z.eqb l__193 2)) then Write_release
+ else if sumbool_of_bool ((Z.eqb l__193 3)) then Write_exclusive
+ else if sumbool_of_bool ((Z.eqb l__193 4)) then Write_exclusive_release
+ else if sumbool_of_bool ((Z.eqb l__193 5)) then Write_RISCV_release
+ else if sumbool_of_bool ((Z.eqb l__193 6)) then Write_RISCV_strong_release
+ else if sumbool_of_bool ((Z.eqb l__193 7)) then Write_RISCV_conditional
+ else if sumbool_of_bool ((Z.eqb l__193 8)) then Write_RISCV_conditional_release
+ else if sumbool_of_bool ((Z.eqb l__193 9)) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked.
+
+Definition num_of_write_kind (arg_ : write_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Write_plain => 0
+ | Write_conditional => 1
+ | Write_release => 2
+ | Write_exclusive => 3
+ | Write_exclusive_release => 4
+ | Write_RISCV_release => 5
+ | Write_RISCV_strong_release => 6
+ | Write_RISCV_conditional => 7
+ | Write_RISCV_conditional_release => 8
+ | Write_RISCV_conditional_strong_release => 9
+ | Write_X86_locked => 10
+ end).
+
+Definition a64_barrier_domain_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: a64_barrier_domain :=
+
+ let l__190 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__190 0)) then A64_FullShare
+ else if sumbool_of_bool ((Z.eqb l__190 1)) then A64_InnerShare
+ else if sumbool_of_bool ((Z.eqb l__190 2)) then A64_OuterShare
+ else A64_NonShare.
+
+Definition num_of_a64_barrier_domain (arg_ : a64_barrier_domain)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with
+ | A64_FullShare => 0
+ | A64_InnerShare => 1
+ | A64_OuterShare => 2
+ | A64_NonShare => 3
+ end).
+
+Definition a64_barrier_type_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: a64_barrier_type :=
+
+ let l__188 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__188 0)) then A64_barrier_all
+ else if sumbool_of_bool ((Z.eqb l__188 1)) then A64_barrier_LD
+ else A64_barrier_ST.
+
+Definition num_of_a64_barrier_type (arg_ : a64_barrier_type)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | A64_barrier_all => 0 | A64_barrier_LD => 1 | A64_barrier_ST => 2 end).
+
+Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: trans_kind :=
+
+ let l__186 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__186 0)) then Transaction_start
+ else if sumbool_of_bool ((Z.eqb l__186 1)) then Transaction_commit
+ else Transaction_abort.
+
+Definition num_of_trans_kind (arg_ : trans_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with
+ | Transaction_start => 0
+ | Transaction_commit => 1
+ | Transaction_abort => 2
+ end).
+
+Definition cache_op_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: cache_op_kind :=
+
+ let l__176 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__176 0)) then Cache_op_D_IVAC
+ else if sumbool_of_bool ((Z.eqb l__176 1)) then Cache_op_D_ISW
+ else if sumbool_of_bool ((Z.eqb l__176 2)) then Cache_op_D_CSW
+ else if sumbool_of_bool ((Z.eqb l__176 3)) then Cache_op_D_CISW
+ else if sumbool_of_bool ((Z.eqb l__176 4)) then Cache_op_D_ZVA
+ else if sumbool_of_bool ((Z.eqb l__176 5)) then Cache_op_D_CVAC
+ else if sumbool_of_bool ((Z.eqb l__176 6)) then Cache_op_D_CVAU
+ else if sumbool_of_bool ((Z.eqb l__176 7)) then Cache_op_D_CIVAC
+ else if sumbool_of_bool ((Z.eqb l__176 8)) then Cache_op_I_IALLUIS
+ else if sumbool_of_bool ((Z.eqb l__176 9)) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU.
+
+Definition num_of_cache_op_kind (arg_ : cache_op_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Cache_op_D_IVAC => 0
+ | Cache_op_D_ISW => 1
+ | Cache_op_D_CSW => 2
+ | Cache_op_D_CISW => 3
+ | Cache_op_D_ZVA => 4
+ | Cache_op_D_CVAC => 5
+ | Cache_op_D_CVAU => 6
+ | Cache_op_D_CIVAC => 7
+ | Cache_op_I_IALLUIS => 8
+ | Cache_op_I_IALLU => 9
+ | Cache_op_I_IVAU => 10
+ end).
+
+Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+
+
+
+Definition cast_unit_vec (b : bitU)
+: M (mword 1) :=
+
+ (match b with
+ | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ | _ => exit tt : M (mword 1)
+ end)
+ : M (mword 1).
+
+Definition get_config_print_instr '(tt : unit) : bool := false.
+
+Definition get_config_print_reg '(tt : unit) : bool := false.
+
+Definition get_config_print_mem '(tt : unit) : bool := false.
+
+Definition get_config_print_platform '(tt : unit) : bool := false.
+
+Definition EXTS {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := sign_extend v m.
+
+Definition EXTZ {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := zero_extend v m.
+
+Definition zeros_implicit (n : Z) `{ArithFact (n >= 0)} : mword n := zeros n.
+
+Definition ones (n : Z) `{ArithFact (n >= 0)} : mword n := sail_ones n.
+
+Definition bool_to_bits (x : bool)
+: mword 1 :=
+
+ if sumbool_of_bool (x) then (vec_of_bits [B1] : mword 1)
+ else (vec_of_bits [B0] : mword 1).
+
+Definition bit_to_bool (b : bitU)
+: M (bool) :=
+
+ (match b with
+ | B1 => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | B0 => returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool).
+
+Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0.
+
+Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.ltb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.geb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.ltb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.geb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.leb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition shift_right_arith64 (v : mword 64) (shift : mword 6)
+: mword 64 :=
+
+ let v128 : bits 128 := EXTS 128 v in
+ subrange_vec_dec (shift_bits_right v128 shift) 63 0.
+
+Definition shift_right_arith32 (v : mword 32) (shift : mword 5)
+: mword 32 :=
+
+ let v64 : bits 64 := EXTS 64 v in
+ subrange_vec_dec (shift_bits_right v64 shift) 31 0.
+
+Fixpoint _rec_n_leading_spaces (s : string) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M ({n : Z & ArithFact (n >= 0)}) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let p0_ := s in
+ (if ((generic_eq p0_ "")) then returnm (build_ex (0 : Z))
+ else
+ let p0_ := string_take s 1 in
+ (if ((generic_eq p0_ " ")) then
+ (_rec_n_leading_spaces (string_drop s 1) (Z.sub _reclimit 1) (_limit_reduces _acc)) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >=
+ 0)}) =>
+ returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.add 1 w__0)
+ : {_atom : Z & ArithFact (exists ex97093_ , _atom = (1 + ex97093_) /\ 0 <= ex97093_)})))
+ else returnm (build_ex (0 : Z)))
+ : M ({n : Z & ArithFact (n >= 0)}))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition n_leading_spaces (s : string)
+: M ({n : Z & ArithFact (n >= 0)}) :=
+
+ (_rec_n_leading_spaces s ((projT1 (string_length s)) : Z) (Zwf_guarded _))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition spc_forwards '(tt : unit) : string := " ".
+
+Definition spc_backwards (s : string) : unit := tt.
+
+Definition spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ n _) =>
+ let l__175 := n in
+ returnm ((if sumbool_of_bool ((Z.eqb l__175 0)) then None
+ else Some ((tt, build_ex n)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition opt_spc_forwards '(tt : unit) : string := "".
+
+Definition opt_spc_backwards (s : string) : unit := tt.
+
+Definition opt_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= 0)}) =>
+ returnm ((Some
+ ((tt, build_ex
+ w__0)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition def_spc_forwards '(tt : unit) : string := " ".
+
+Definition def_spc_backwards (s : string) : unit := tt.
+
+Definition def_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (opt_spc_matches_prefix s)
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition hex_bits_1_forwards_matches (bv : mword 1) : bool := true.
+
+Definition hex_bits_1_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_1_matches_prefix s) with
+ | Some ((g__253, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_1_backwards (s : string)
+: M (mword 1) :=
+
+ (match (hex_bits_1_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 1)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt)
+ : M (mword 1)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 1).
+
+Definition hex_bits_2_forwards_matches (bv : mword 2) : bool := true.
+
+Definition hex_bits_2_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_2_matches_prefix s) with
+ | Some ((g__252, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_2_backwards (s : string)
+: M (mword 2) :=
+
+ (match (hex_bits_2_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 2)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt)
+ : M (mword 2)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 2).
+
+Definition hex_bits_3_forwards_matches (bv : mword 3) : bool := true.
+
+Definition hex_bits_3_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_3_matches_prefix s) with
+ | Some ((g__251, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_3_backwards (s : string)
+: M (mword 3) :=
+
+ (match (hex_bits_3_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 3)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt)
+ : M (mword 3)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 3).
+
+Definition hex_bits_4_forwards_matches (bv : mword 4) : bool := true.
+
+Definition hex_bits_4_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_4_matches_prefix s) with
+ | Some ((g__250, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_4_backwards (s : string)
+: M (mword 4) :=
+
+ (match (hex_bits_4_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 4)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt)
+ : M (mword 4)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 4).
+
+Definition hex_bits_5_forwards_matches (bv : mword 5) : bool := true.
+
+Definition hex_bits_5_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_5_matches_prefix s) with
+ | Some ((g__249, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_5_backwards (s : string)
+: M (mword 5) :=
+
+ (match (hex_bits_5_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 5)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt)
+ : M (mword 5)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 5).
+
+Definition hex_bits_6_forwards_matches (bv : mword 6) : bool := true.
+
+Definition hex_bits_6_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_6_matches_prefix s) with
+ | Some ((g__248, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_6_backwards (s : string)
+: M (mword 6) :=
+
+ (match (hex_bits_6_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 6)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt)
+ : M (mword 6)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 6).
+
+Definition hex_bits_7_forwards_matches (bv : mword 7) : bool := true.
+
+Definition hex_bits_7_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_7_matches_prefix s) with
+ | Some ((g__247, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_7_backwards (s : string)
+: M (mword 7) :=
+
+ (match (hex_bits_7_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 7)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt)
+ : M (mword 7)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 7).
+
+Definition hex_bits_8_forwards_matches (bv : mword 8) : bool := true.
+
+Definition hex_bits_8_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_8_matches_prefix s) with
+ | Some ((g__246, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_8_backwards (s : string)
+: M (mword 8) :=
+
+ (match (hex_bits_8_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 8)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt)
+ : M (mword 8)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 8).
+
+Definition hex_bits_9_forwards_matches (bv : mword 9) : bool := true.
+
+Definition hex_bits_9_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_9_matches_prefix s) with
+ | Some ((g__245, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_9_backwards (s : string)
+: M (mword 9) :=
+
+ (match (hex_bits_9_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 9)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt)
+ : M (mword 9)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 9).
+
+Definition hex_bits_10_forwards_matches (bv : mword 10) : bool := true.
+
+Definition hex_bits_10_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_10_matches_prefix s) with
+ | Some ((g__244, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_10_backwards (s : string)
+: M (mword 10) :=
+
+ (match (hex_bits_10_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 10)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt)
+ : M (mword 10)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 10).
+
+Definition hex_bits_11_forwards_matches (bv : mword 11) : bool := true.
+
+Definition hex_bits_11_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_11_matches_prefix s) with
+ | Some ((g__243, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_11_backwards (s : string)
+: M (mword 11) :=
+
+ (match (hex_bits_11_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 11)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt)
+ : M (mword 11)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 11).
+
+Definition hex_bits_12_forwards_matches (bv : mword 12) : bool := true.
+
+Definition hex_bits_12_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_12_matches_prefix s) with
+ | Some ((g__242, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_12_backwards (s : string)
+: M (mword 12) :=
+
+ (match (hex_bits_12_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 12)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt)
+ : M (mword 12)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 12).
+
+Definition hex_bits_13_forwards_matches (bv : mword 13) : bool := true.
+
+Definition hex_bits_13_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_13_matches_prefix s) with
+ | Some ((g__241, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_13_backwards (s : string)
+: M (mword 13) :=
+
+ (match (hex_bits_13_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 13)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt)
+ : M (mword 13)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 13).
+
+Definition hex_bits_14_forwards_matches (bv : mword 14) : bool := true.
+
+Definition hex_bits_14_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_14_matches_prefix s) with
+ | Some ((g__240, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_14_backwards (s : string)
+: M (mword 14) :=
+
+ (match (hex_bits_14_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 14)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt)
+ : M (mword 14)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 14).
+
+Definition hex_bits_15_forwards_matches (bv : mword 15) : bool := true.
+
+Definition hex_bits_15_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_15_matches_prefix s) with
+ | Some ((g__239, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_15_backwards (s : string)
+: M (mword 15) :=
+
+ (match (hex_bits_15_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 15)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt)
+ : M (mword 15)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 15).
+
+Definition hex_bits_16_forwards_matches (bv : mword 16) : bool := true.
+
+Definition hex_bits_16_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_16_matches_prefix s) with
+ | Some ((g__238, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_16_backwards (s : string)
+: M (mword 16) :=
+
+ (match (hex_bits_16_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 16)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt)
+ : M (mword 16)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 16).
+
+Definition hex_bits_17_forwards_matches (bv : mword 17) : bool := true.
+
+Definition hex_bits_17_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_17_matches_prefix s) with
+ | Some ((g__237, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_17_backwards (s : string)
+: M (mword 17) :=
+
+ (match (hex_bits_17_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 17)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt)
+ : M (mword 17)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 17).
+
+Definition hex_bits_18_forwards_matches (bv : mword 18) : bool := true.
+
+Definition hex_bits_18_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_18_matches_prefix s) with
+ | Some ((g__236, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_18_backwards (s : string)
+: M (mword 18) :=
+
+ (match (hex_bits_18_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 18)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt)
+ : M (mword 18)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 18).
+
+Definition hex_bits_19_forwards_matches (bv : mword 19) : bool := true.
+
+Definition hex_bits_19_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_19_matches_prefix s) with
+ | Some ((g__235, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_19_backwards (s : string)
+: M (mword 19) :=
+
+ (match (hex_bits_19_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 19)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt)
+ : M (mword 19)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 19).
+
+Definition hex_bits_20_forwards_matches (bv : mword 20) : bool := true.
+
+Definition hex_bits_20_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_20_matches_prefix s) with
+ | Some ((g__234, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_20_backwards (s : string)
+: M (mword 20) :=
+
+ (match (hex_bits_20_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 20)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt)
+ : M (mword 20)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 20).
+
+Definition hex_bits_21_forwards_matches (bv : mword 21) : bool := true.
+
+Definition hex_bits_21_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_21_matches_prefix s) with
+ | Some ((g__233, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_21_backwards (s : string)
+: M (mword 21) :=
+
+ (match (hex_bits_21_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 21)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt)
+ : M (mword 21)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 21).
+
+Definition hex_bits_22_forwards_matches (bv : mword 22) : bool := true.
+
+Definition hex_bits_22_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_22_matches_prefix s) with
+ | Some ((g__232, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_22_backwards (s : string)
+: M (mword 22) :=
+
+ (match (hex_bits_22_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 22)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt)
+ : M (mword 22)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 22).
+
+Definition hex_bits_23_forwards_matches (bv : mword 23) : bool := true.
+
+Definition hex_bits_23_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_23_matches_prefix s) with
+ | Some ((g__231, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_23_backwards (s : string)
+: M (mword 23) :=
+
+ (match (hex_bits_23_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 23)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt)
+ : M (mword 23)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 23).
+
+Definition hex_bits_24_forwards_matches (bv : mword 24) : bool := true.
+
+Definition hex_bits_24_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_24_matches_prefix s) with
+ | Some ((g__230, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_24_backwards (s : string)
+: M (mword 24) :=
+
+ (match (hex_bits_24_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 24)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt)
+ : M (mword 24)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 24).
+
+Definition hex_bits_25_forwards_matches (bv : mword 25) : bool := true.
+
+Definition hex_bits_25_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_25_matches_prefix s) with
+ | Some ((g__229, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_25_backwards (s : string)
+: M (mword 25) :=
+
+ (match (hex_bits_25_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 25)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt)
+ : M (mword 25)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 25).
+
+Definition hex_bits_26_forwards_matches (bv : mword 26) : bool := true.
+
+Definition hex_bits_26_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_26_matches_prefix s) with
+ | Some ((g__228, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_26_backwards (s : string)
+: M (mword 26) :=
+
+ (match (hex_bits_26_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 26)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt)
+ : M (mword 26)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 26).
+
+Definition hex_bits_27_forwards_matches (bv : mword 27) : bool := true.
+
+Definition hex_bits_27_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_27_matches_prefix s) with
+ | Some ((g__227, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_27_backwards (s : string)
+: M (mword 27) :=
+
+ (match (hex_bits_27_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 27)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt)
+ : M (mword 27)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 27).
+
+Definition hex_bits_28_forwards_matches (bv : mword 28) : bool := true.
+
+Definition hex_bits_28_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_28_matches_prefix s) with
+ | Some ((g__226, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_28_backwards (s : string)
+: M (mword 28) :=
+
+ (match (hex_bits_28_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 28)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt)
+ : M (mword 28)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 28).
+
+Definition hex_bits_29_forwards_matches (bv : mword 29) : bool := true.
+
+Definition hex_bits_29_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_29_matches_prefix s) with
+ | Some ((g__225, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_29_backwards (s : string)
+: M (mword 29) :=
+
+ (match (hex_bits_29_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 29)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt)
+ : M (mword 29)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 29).
+
+Definition hex_bits_30_forwards_matches (bv : mword 30) : bool := true.
+
+Definition hex_bits_30_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_30_matches_prefix s) with
+ | Some ((g__224, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_30_backwards (s : string)
+: M (mword 30) :=
+
+ (match (hex_bits_30_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 30)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt)
+ : M (mword 30)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 30).
+
+Definition hex_bits_31_forwards_matches (bv : mword 31) : bool := true.
+
+Definition hex_bits_31_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_31_matches_prefix s) with
+ | Some ((g__223, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_31_backwards (s : string)
+: M (mword 31) :=
+
+ (match (hex_bits_31_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 31)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt)
+ : M (mword 31)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 31).
+
+Definition hex_bits_32_forwards_matches (bv : mword 32) : bool := true.
+
+Definition hex_bits_32_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_32_matches_prefix s) with
+ | Some ((g__222, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_32_backwards (s : string)
+: M (mword 32) :=
+
+ (match (hex_bits_32_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 32)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt)
+ : M (mword 32)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 32).
+
+Definition hex_bits_33_forwards_matches (bv : mword 33) : bool := true.
+
+Definition hex_bits_33_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_33_matches_prefix s) with
+ | Some ((g__221, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_33_backwards (s : string)
+: M (mword 33) :=
+
+ (match (hex_bits_33_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 33)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt)
+ : M (mword 33)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 33).
+
+Definition hex_bits_48_forwards_matches (bv : mword 48) : bool := true.
+
+Definition hex_bits_48_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_48_matches_prefix s) with
+ | Some ((g__220, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_48_backwards (s : string)
+: M (mword 48) :=
+
+ (match (hex_bits_48_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 48)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt)
+ : M (mword 48)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 48).
+
+Definition hex_bits_64_forwards_matches (bv : mword 64) : bool := true.
+
+Definition hex_bits_64_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_64_matches_prefix s) with
+ | Some ((g__219, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_64_backwards (s : string)
+: M (mword 64) :=
+
+ (match (hex_bits_64_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 64)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt)
+ : M (mword 64)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 64).
+
+Definition default_meta : mem_meta := tt.
+Hint Unfold default_meta : sail.
+Definition __WriteRAM_Meta (addr : mword 32) (width : Z) (meta : unit)
+: M (unit) :=
+
+ returnm (tt
+ : unit).
+
+Definition __ReadRAM_Meta (addr : mword 32) (width : Z) : M (unit) := returnm (tt : unit).
+
+Definition write_ram
+(wk : write_kind) (addr : mword 32) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (bool) :=
+
+ (write_mem wk 32 addr width data) >>= fun ret : bool =>
+ (if sumbool_of_bool (ret) then (__WriteRAM_Meta addr width meta) : M (unit)
+ else returnm (tt : unit)) >>
+ returnm (ret
+ : bool).
+
+Definition write_ram_ea (wk : write_kind) (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (unit) :=
+
+ (write_mem_ea wk 32 addr width)
+ : M (unit).
+
+Definition read_ram (rk : read_kind) (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (mword (8 * width)) :=
+
+ (read_mem rk 32 addr width)
+ : M (mword (8 * width)).
+
+Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Definition xlen_val := 32.
+Hint Unfold xlen_val : sail.
+Definition xlen_max_unsigned := Z.sub (projT1 (pow2 32)) 1.
+Hint Unfold xlen_max_unsigned : sail.
+Definition xlen_max_signed := Z.sub (projT1 (pow2 (Z.sub 32 1))) 1.
+Hint Unfold xlen_max_signed : sail.
+Definition xlen_min_signed := Z.sub 0 (projT1 (pow2 (Z.sub 32 1))).
+Hint Unfold xlen_min_signed : sail.
+Definition regidx_to_regno (b : mword 5)
+: {n : Z & ArithFact (0 <= n /\ n < 32)} :=
+
+ build_ex(let 'r := projT1 (uint b) in
+ r).
+
+Definition creg2reg_idx (creg : mword 3)
+: mword 5 :=
+
+ concat_vec (vec_of_bits [B0;B1] : mword 2) creg.
+
+Definition zreg : regidx := (vec_of_bits [B0;B0;B0;B0;B0] : mword 5).
+Hint Unfold zreg : sail.
+Definition ra : regidx := (vec_of_bits [B0;B0;B0;B0;B1] : mword 5).
+Hint Unfold ra : sail.
+Definition sp : regidx := (vec_of_bits [B0;B0;B0;B1;B0] : mword 5).
+Hint Unfold sp : sail.
+Definition Architecture_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: Architecture :=
+
+ let l__173 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__173 0)) then RV32
+ else if sumbool_of_bool ((Z.eqb l__173 1)) then RV64
+ else RV128.
+
+Definition num_of_Architecture (arg_ : Architecture)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RV32 => 0 | RV64 => 1 | RV128 => 2 end).
+
+Definition architecture (a : mword 2)
+: option Architecture :=
+
+ let b__0 := a in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Some (RV32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Some (RV64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then Some (RV128)
+ else None.
+
+Definition arch_to_bits (a : Architecture)
+: mword 2 :=
+
+ match a with
+ | RV32 => (vec_of_bits [B0;B1] : mword 2)
+ | RV64 => (vec_of_bits [B1;B0] : mword 2)
+ | RV128 => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition Privilege_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: Privilege :=
+
+ let l__171 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__171 0)) then User
+ else if sumbool_of_bool ((Z.eqb l__171 1)) then Supervisor
+ else Machine.
+
+Definition num_of_Privilege (arg_ : Privilege)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | User => 0 | Supervisor => 1 | Machine => 2 end).
+
+Definition privLevel_to_bits (p : Privilege)
+: mword 2 :=
+
+ match p with
+ | User => (vec_of_bits [B0;B0] : mword 2)
+ | Supervisor => (vec_of_bits [B0;B1] : mword 2)
+ | Machine => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition privLevel_of_bits (p : mword 2)
+: M (Privilege) :=
+
+ let b__0 := p in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (User : Privilege)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (Supervisor : Privilege)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (Machine : Privilege)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_types.sail 78:2 - 82:3" >>= fun _ =>
+ exit tt)
+ : M (Privilege).
+
+Definition privLevel_to_str (p : Privilege)
+: string :=
+
+ match p with | User => "U" | Supervisor => "S" | Machine => "M" end.
+
+Definition Retired_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)}
+: Retired :=
+
+ let l__170 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__170 0)) then RETIRE_SUCCESS
+ else RETIRE_FAIL.
+
+Definition num_of_Retired (arg_ : Retired)
+: {e : Z & ArithFact (0 <= e /\ e <= 1)} :=
+
+ build_ex(match arg_ with | RETIRE_SUCCESS => 0 | RETIRE_FAIL => 1 end).
+
+Definition AccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: AccessType :=
+
+ let l__167 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__167 0)) then Read
+ else if sumbool_of_bool ((Z.eqb l__167 1)) then Write
+ else if sumbool_of_bool ((Z.eqb l__167 2)) then ReadWrite
+ else Execute.
+
+Definition num_of_AccessType (arg_ : AccessType)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Read => 0 | Write => 1 | ReadWrite => 2 | Execute => 3 end).
+
+Definition accessType_to_str (a : AccessType)
+: string :=
+
+ match a with | Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" end.
+
+Definition word_width_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: word_width :=
+
+ let l__164 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__164 0)) then BYTE
+ else if sumbool_of_bool ((Z.eqb l__164 1)) then HALF
+ else if sumbool_of_bool ((Z.eqb l__164 2)) then WORD
+ else DOUBLE.
+
+Definition num_of_word_width (arg_ : word_width)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | BYTE => 0 | HALF => 1 | WORD => 2 | DOUBLE => 3 end).
+
+Definition InterruptType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)}
+: InterruptType :=
+
+ let l__156 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__156 0)) then I_U_Software
+ else if sumbool_of_bool ((Z.eqb l__156 1)) then I_S_Software
+ else if sumbool_of_bool ((Z.eqb l__156 2)) then I_M_Software
+ else if sumbool_of_bool ((Z.eqb l__156 3)) then I_U_Timer
+ else if sumbool_of_bool ((Z.eqb l__156 4)) then I_S_Timer
+ else if sumbool_of_bool ((Z.eqb l__156 5)) then I_M_Timer
+ else if sumbool_of_bool ((Z.eqb l__156 6)) then I_U_External
+ else if sumbool_of_bool ((Z.eqb l__156 7)) then I_S_External
+ else I_M_External.
+
+Definition num_of_InterruptType (arg_ : InterruptType)
+: {e : Z & ArithFact (0 <= e /\ e <= 8)} :=
+
+ build_ex(match arg_ with
+ | I_U_Software => 0
+ | I_S_Software => 1
+ | I_M_Software => 2
+ | I_U_Timer => 3
+ | I_S_Timer => 4
+ | I_M_Timer => 5
+ | I_U_External => 6
+ | I_S_External => 7
+ | I_M_External => 8
+ end).
+
+Definition interruptType_to_bits (i : InterruptType)
+: mword 8 :=
+
+ match i with
+ | I_U_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)
+ | I_S_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8)
+ | I_M_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8)
+ | I_U_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8)
+ | I_S_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8)
+ | I_M_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8)
+ | I_U_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8)
+ | I_S_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8)
+ | I_M_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8)
+ end.
+
+Definition ExceptionType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 16)}
+: ExceptionType :=
+
+ let l__140 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__140 0)) then E_Fetch_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__140 1)) then E_Fetch_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__140 2)) then E_Illegal_Instr
+ else if sumbool_of_bool ((Z.eqb l__140 3)) then E_Breakpoint
+ else if sumbool_of_bool ((Z.eqb l__140 4)) then E_Load_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__140 5)) then E_Load_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__140 6)) then E_SAMO_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__140 7)) then E_SAMO_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__140 8)) then E_U_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__140 9)) then E_S_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__140 10)) then E_Reserved_10
+ else if sumbool_of_bool ((Z.eqb l__140 11)) then E_M_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__140 12)) then E_Fetch_Page_Fault
+ else if sumbool_of_bool ((Z.eqb l__140 13)) then E_Load_Page_Fault
+ else if sumbool_of_bool ((Z.eqb l__140 14)) then E_Reserved_14
+ else if sumbool_of_bool ((Z.eqb l__140 15)) then E_SAMO_Page_Fault
+ else E_CHERI.
+
+Definition num_of_ExceptionType (arg_ : ExceptionType)
+: {e : Z & ArithFact (0 <= e /\ e <= 16)} :=
+
+ build_ex(match arg_ with
+ | E_Fetch_Addr_Align => 0
+ | E_Fetch_Access_Fault => 1
+ | E_Illegal_Instr => 2
+ | E_Breakpoint => 3
+ | E_Load_Addr_Align => 4
+ | E_Load_Access_Fault => 5
+ | E_SAMO_Addr_Align => 6
+ | E_SAMO_Access_Fault => 7
+ | E_U_EnvCall => 8
+ | E_S_EnvCall => 9
+ | E_Reserved_10 => 10
+ | E_M_EnvCall => 11
+ | E_Fetch_Page_Fault => 12
+ | E_Load_Page_Fault => 13
+ | E_Reserved_14 => 14
+ | E_SAMO_Page_Fault => 15
+ | E_CHERI => 16
+ end).
+
+Definition exceptionType_to_bits (e : ExceptionType)
+: mword 8 :=
+
+ match e with
+ | E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)
+ | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8)
+ | E_Illegal_Instr => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8)
+ | E_Breakpoint => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8)
+ | E_Load_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8)
+ | E_Load_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8)
+ | E_SAMO_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : mword 8)
+ | E_SAMO_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8)
+ | E_U_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8)
+ | E_S_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8)
+ | E_Reserved_10 => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8)
+ | E_M_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8)
+ | E_Fetch_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8)
+ | E_Load_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8)
+ | E_Reserved_14 => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B0] : mword 8)
+ | E_SAMO_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1] : mword 8)
+ | E_CHERI => (vec_of_bits [B0;B0;B1;B0;B0;B0;B0;B0] : mword 8)
+ end.
+
+Definition exceptionType_to_str (e : ExceptionType)
+: string :=
+
+ match e with
+ | E_Fetch_Addr_Align => "misaligned-fetch"
+ | E_Fetch_Access_Fault => "fetch-access-fault"
+ | E_Illegal_Instr => "illegal-instruction"
+ | E_Breakpoint => "breakpoint"
+ | E_Load_Addr_Align => "misaligned-load"
+ | E_Load_Access_Fault => "load-access-fault"
+ | E_SAMO_Addr_Align => "misaliged-store/amo"
+ | E_SAMO_Access_Fault => "store/amo-access-fault"
+ | E_U_EnvCall => "u-call"
+ | E_S_EnvCall => "s-call"
+ | E_Reserved_10 => "reserved-0"
+ | E_M_EnvCall => "m-call"
+ | E_Fetch_Page_Fault => "fetch-page-fault"
+ | E_Load_Page_Fault => "load-page-fault"
+ | E_Reserved_14 => "reserved-1"
+ | E_SAMO_Page_Fault => "store/amo-page-fault"
+ | E_CHERI => "CHERI"
+ end.
+
+Definition not_implemented {a : Type} (message : string)
+: M (a) :=
+
+ throw (Error_not_implemented
+ (message)).
+
+Definition internal_error {a : Type} (s : string)
+: M (a) :=
+
+ assert_exp' false s >>= fun _ => exit tt.
+
+Definition TrapVectorMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: TrapVectorMode :=
+
+ let l__138 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__138 0)) then TV_Direct
+ else if sumbool_of_bool ((Z.eqb l__138 1)) then TV_Vector
+ else TV_Reserved.
+
+Definition num_of_TrapVectorMode (arg_ : TrapVectorMode)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | TV_Direct => 0 | TV_Vector => 1 | TV_Reserved => 2 end).
+
+Definition trapVectorMode_of_bits (m : mword 2)
+: TrapVectorMode :=
+
+ let b__0 := m in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then TV_Direct
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then TV_Vector
+ else TV_Reserved.
+
+Definition ExtStatus_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: ExtStatus :=
+
+ let l__135 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__135 0)) then Off
+ else if sumbool_of_bool ((Z.eqb l__135 1)) then Initial
+ else if sumbool_of_bool ((Z.eqb l__135 2)) then Clean
+ else Dirty.
+
+Definition num_of_ExtStatus (arg_ : ExtStatus)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 end).
+
+Definition extStatus_to_bits (e : ExtStatus)
+: mword 2 :=
+
+ match e with
+ | Off => (vec_of_bits [B0;B0] : mword 2)
+ | Initial => (vec_of_bits [B0;B1] : mword 2)
+ | Clean => (vec_of_bits [B1;B0] : mword 2)
+ | Dirty => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition extStatus_of_bits (e : mword 2)
+: M (ExtStatus) :=
+
+ let b__0 := e in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (Off : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (Initial : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (Clean : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (Dirty : ExtStatus)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_types.sail 264:2 - 269:3" >>= fun _ =>
+ exit tt)
+ : M (ExtStatus).
+
+Definition SATPMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: SATPMode :=
+
+ let l__132 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__132 0)) then Sbare
+ else if sumbool_of_bool ((Z.eqb l__132 1)) then Sv32
+ else if sumbool_of_bool ((Z.eqb l__132 2)) then Sv39
+ else Sv48.
+
+Definition num_of_SATPMode (arg_ : SATPMode)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Sbare => 0 | Sv32 => 1 | Sv39 => 2 | Sv48 => 3 end).
+
+Definition satp64Mode_of_bits (a : Architecture) (m : mword 4)
+: option SATPMode :=
+
+ match (a, m) with
+ | (g__218, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0] : mword 4))) then Some (Sbare)
+ else
+ match (g__218, b__0) with
+ | (RV32, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1] : mword 4))) then Some (Sv32)
+ else match (RV32, b__0) with | (_, _) => None end
+ | (RV64, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0] : mword 4))) then Some (Sv39)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1] : mword 4))) then Some (Sv48)
+ else match (RV64, b__0) with | (_, _) => None end
+ | (_, _) => None
+ end
+ end.
+
+Definition uop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)}
+: uop :=
+
+ let l__131 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__131 0)) then RISCV_LUI
+ else RISCV_AUIPC.
+
+Definition num_of_uop (arg_ : uop)
+: {e : Z & ArithFact (0 <= e /\ e <= 1)} :=
+
+ build_ex(match arg_ with | RISCV_LUI => 0 | RISCV_AUIPC => 1 end).
+
+Definition bop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)}
+: bop :=
+
+ let l__126 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__126 0)) then RISCV_BEQ
+ else if sumbool_of_bool ((Z.eqb l__126 1)) then RISCV_BNE
+ else if sumbool_of_bool ((Z.eqb l__126 2)) then RISCV_BLT
+ else if sumbool_of_bool ((Z.eqb l__126 3)) then RISCV_BGE
+ else if sumbool_of_bool ((Z.eqb l__126 4)) then RISCV_BLTU
+ else RISCV_BGEU.
+
+Definition num_of_bop (arg_ : bop)
+: {e : Z & ArithFact (0 <= e /\ e <= 5)} :=
+
+ build_ex(match arg_ with
+ | RISCV_BEQ => 0
+ | RISCV_BNE => 1
+ | RISCV_BLT => 2
+ | RISCV_BGE => 3
+ | RISCV_BLTU => 4
+ | RISCV_BGEU => 5
+ end).
+
+Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)}
+: iop :=
+
+ let l__121 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__121 0)) then RISCV_ADDI
+ else if sumbool_of_bool ((Z.eqb l__121 1)) then RISCV_SLTI
+ else if sumbool_of_bool ((Z.eqb l__121 2)) then RISCV_SLTIU
+ else if sumbool_of_bool ((Z.eqb l__121 3)) then RISCV_XORI
+ else if sumbool_of_bool ((Z.eqb l__121 4)) then RISCV_ORI
+ else RISCV_ANDI.
+
+Definition num_of_iop (arg_ : iop)
+: {e : Z & ArithFact (0 <= e /\ e <= 5)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADDI => 0
+ | RISCV_SLTI => 1
+ | RISCV_SLTIU => 2
+ | RISCV_XORI => 3
+ | RISCV_ORI => 4
+ | RISCV_ANDI => 5
+ end).
+
+Definition sop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: sop :=
+
+ let l__119 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__119 0)) then RISCV_SLLI
+ else if sumbool_of_bool ((Z.eqb l__119 1)) then RISCV_SRLI
+ else RISCV_SRAI.
+
+Definition num_of_sop (arg_ : sop)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RISCV_SLLI => 0 | RISCV_SRLI => 1 | RISCV_SRAI => 2 end).
+
+Definition rop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 9)}
+: rop :=
+
+ let l__110 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__110 0)) then RISCV_ADD
+ else if sumbool_of_bool ((Z.eqb l__110 1)) then RISCV_SUB
+ else if sumbool_of_bool ((Z.eqb l__110 2)) then RISCV_SLL
+ else if sumbool_of_bool ((Z.eqb l__110 3)) then RISCV_SLT
+ else if sumbool_of_bool ((Z.eqb l__110 4)) then RISCV_SLTU
+ else if sumbool_of_bool ((Z.eqb l__110 5)) then RISCV_XOR
+ else if sumbool_of_bool ((Z.eqb l__110 6)) then RISCV_SRL
+ else if sumbool_of_bool ((Z.eqb l__110 7)) then RISCV_SRA
+ else if sumbool_of_bool ((Z.eqb l__110 8)) then RISCV_OR
+ else RISCV_AND.
+
+Definition num_of_rop (arg_ : rop)
+: {e : Z & ArithFact (0 <= e /\ e <= 9)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADD => 0
+ | RISCV_SUB => 1
+ | RISCV_SLL => 2
+ | RISCV_SLT => 3
+ | RISCV_SLTU => 4
+ | RISCV_XOR => 5
+ | RISCV_SRL => 6
+ | RISCV_SRA => 7
+ | RISCV_OR => 8
+ | RISCV_AND => 9
+ end).
+
+Definition ropw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)}
+: ropw :=
+
+ let l__106 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__106 0)) then RISCV_ADDW
+ else if sumbool_of_bool ((Z.eqb l__106 1)) then RISCV_SUBW
+ else if sumbool_of_bool ((Z.eqb l__106 2)) then RISCV_SLLW
+ else if sumbool_of_bool ((Z.eqb l__106 3)) then RISCV_SRLW
+ else RISCV_SRAW.
+
+Definition num_of_ropw (arg_ : ropw)
+: {e : Z & ArithFact (0 <= e /\ e <= 4)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADDW => 0
+ | RISCV_SUBW => 1
+ | RISCV_SLLW => 2
+ | RISCV_SRLW => 3
+ | RISCV_SRAW => 4
+ end).
+
+Definition sopw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: sopw :=
+
+ let l__104 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__104 0)) then RISCV_SLLIW
+ else if sumbool_of_bool ((Z.eqb l__104 1)) then RISCV_SRLIW
+ else RISCV_SRAIW.
+
+Definition num_of_sopw (arg_ : sopw)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RISCV_SLLIW => 0 | RISCV_SRLIW => 1 | RISCV_SRAIW => 2 end).
+
+Definition amoop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)}
+: amoop :=
+
+ let l__96 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__96 0)) then AMOSWAP
+ else if sumbool_of_bool ((Z.eqb l__96 1)) then AMOADD
+ else if sumbool_of_bool ((Z.eqb l__96 2)) then AMOXOR
+ else if sumbool_of_bool ((Z.eqb l__96 3)) then AMOAND
+ else if sumbool_of_bool ((Z.eqb l__96 4)) then AMOOR
+ else if sumbool_of_bool ((Z.eqb l__96 5)) then AMOMIN
+ else if sumbool_of_bool ((Z.eqb l__96 6)) then AMOMAX
+ else if sumbool_of_bool ((Z.eqb l__96 7)) then AMOMINU
+ else AMOMAXU.
+
+Definition num_of_amoop (arg_ : amoop)
+: {e : Z & ArithFact (0 <= e /\ e <= 8)} :=
+
+ build_ex(match arg_ with
+ | AMOSWAP => 0
+ | AMOADD => 1
+ | AMOXOR => 2
+ | AMOAND => 3
+ | AMOOR => 4
+ | AMOMIN => 5
+ | AMOMAX => 6
+ | AMOMINU => 7
+ | AMOMAXU => 8
+ end).
+
+Definition csrop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: csrop :=
+
+ let l__94 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__94 0)) then CSRRW
+ else if sumbool_of_bool ((Z.eqb l__94 1)) then CSRRS
+ else CSRRC.
+
+Definition num_of_csrop (arg_ : csrop)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | CSRRW => 0 | CSRRS => 1 | CSRRC => 2 end).
+
+Definition sep_forwards (arg_ : unit)
+: string :=
+
+ match arg_ with
+ | tt =>
+ string_append (opt_spc_forwards tt)
+ (string_append "," (string_append (def_spc_forwards tt) ""))
+ end.
+
+Definition _s0_ (_s1_ : string)
+: M (option unit) :=
+
+ (match _s1_ with
+ | _s2_ =>
+ (opt_spc_matches_prefix _s2_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3_ _)) =>
+ let _s4_ := string_drop _s2_ _s3_ in
+ (if ((string_startswith _s4_ ",")) then
+ (match (string_drop _s4_ (projT1 (string_length ","))) with
+ | _s5_ =>
+ (def_spc_matches_prefix _s5_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s6_ _)) =>
+ let p0_ := string_drop _s5_ _s6_ in
+ if ((generic_eq p0_ "")) then Some (tt)
+ else None
+ | _ => None
+ end)
+ : option unit)
+ end)
+ : M (option unit)
+ else returnm (None : option unit))
+ : M (option unit)
+ | _ => returnm (None : option unit)
+ end)
+ : M (option unit)
+ end)
+ : M (option unit).
+
+Definition sep_backwards (arg_ : string)
+: M (unit) :=
+
+ let _s7_ := arg_ in
+ (_s0_ _s7_) >>= fun w__0 : option unit =>
+ (if ((match w__0 with | Some (tt) => true | _ => false end)) then
+ (_s0_ _s7_) >>= fun w__1 : option unit =>
+ (match w__1 with | Some (tt) => returnm (tt : unit) | _ => exit tt : M (unit) end)
+ : M (unit)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (unit).
+
+Definition sep_forwards_matches (arg_ : unit) : bool := match arg_ with | tt => true end.
+
+Definition _s8_ (_s9_ : string)
+: M (option unit) :=
+
+ (match _s9_ with
+ | _s10_ =>
+ (opt_spc_matches_prefix _s10_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s11_ _)) =>
+ let _s12_ := string_drop _s10_ _s11_ in
+ (if ((string_startswith _s12_ ",")) then
+ (match (string_drop _s12_ (projT1 (string_length ","))) with
+ | _s13_ =>
+ (def_spc_matches_prefix _s13_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s14_ _)) =>
+ let p0_ := string_drop _s13_ _s14_ in
+ if ((generic_eq p0_ "")) then Some (tt)
+ else None
+ | _ => None
+ end)
+ : option unit)
+ end)
+ : M (option unit)
+ else returnm (None : option unit))
+ : M (option unit)
+ | _ => returnm (None : option unit)
+ end)
+ : M (option unit)
+ end)
+ : M (option unit).
+
+Definition sep_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s15_ := arg_ in
+ (_s8_ _s15_) >>= fun w__0 : option unit =>
+ (if ((match w__0 with | Some (tt) => true | _ => false end)) then
+ (_s8_ _s15_) >>= fun w__1 : option unit =>
+ (match w__1 with
+ | Some (tt) => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition _s16_ (_s17_ : string)
+: M (option string) :=
+
+ (match _s17_ with
+ | _s18_ =>
+ (opt_spc_matches_prefix _s18_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s19_ _)) =>
+ let _s20_ := string_drop _s18_ _s19_ in
+ (if ((string_startswith _s20_ ",")) then
+ (match (string_drop _s20_ (projT1 (string_length ","))) with
+ | _s21_ =>
+ (def_spc_matches_prefix _s21_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s22_ _)) =>
+ match (string_drop _s21_ _s22_) with | s_ => Some (s_) end
+ | _ => None
+ end)
+ : option string)
+ end)
+ : M (option string)
+ else returnm (None : option string))
+ : M (option string)
+ | _ => returnm (None : option string)
+ end)
+ : M (option string)
+ end)
+ : M (option string).
+
+Definition sep_matches_prefix (arg_ : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s23_ := arg_ in
+ (_s16_ _s23_) >>= fun w__0 : option string =>
+ (if ((match w__0 with | Some (s_) => true | _ => false end)) then
+ (_s16_ _s23_) >>= fun w__1 : option string =>
+ (match w__1 with
+ | Some (s_) =>
+ returnm ((Some
+ ((tt, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((unit * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((unit * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((unit * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bool_bits_forwards (arg_ : bool)
+: mword 1 :=
+
+ match arg_ with
+ | true => (vec_of_bits [B1] : mword 1)
+ | false => (vec_of_bits [B0] : mword 1)
+ end.
+
+Definition bool_bits_backwards (arg_ : mword 1)
+: M (bool) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition bool_bits_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition bool_bits_backwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bool_not_bits_forwards (arg_ : bool)
+: mword 1 :=
+
+ match arg_ with
+ | true => (vec_of_bits [B0] : mword 1)
+ | false => (vec_of_bits [B1] : mword 1)
+ end.
+
+Definition bool_not_bits_backwards (arg_ : mword 1)
+: M (bool) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition bool_not_bits_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition bool_not_bits_backwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else false.
+
+Definition size_bits_forwards (arg_ : word_width)
+: mword 2 :=
+
+ match arg_ with
+ | BYTE => (vec_of_bits [B0;B0] : mword 2)
+ | HALF => (vec_of_bits [B0;B1] : mword 2)
+ | WORD => (vec_of_bits [B1;B0] : mword 2)
+ | DOUBLE => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition size_bits_backwards (arg_ : mword 2)
+: M (word_width) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (BYTE : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (HALF : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (WORD : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (DOUBLE : word_width)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (word_width).
+
+Definition size_bits_forwards_matches (arg_ : word_width)
+: bool :=
+
+ match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end.
+
+Definition size_bits_backwards_matches (arg_ : mword 2)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true
+ else false.
+
+Definition size_mnemonic_forwards (arg_ : word_width)
+: string :=
+
+ match arg_ with | BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" end.
+
+Definition size_mnemonic_backwards (arg_ : string)
+: M (word_width) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "b")) then returnm (BYTE : word_width)
+ else if ((generic_eq p0_ "h")) then returnm (HALF : word_width)
+ else if ((generic_eq p0_ "w")) then returnm (WORD : word_width)
+ else if ((generic_eq p0_ "d")) then returnm (DOUBLE : word_width)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (word_width).
+
+Definition size_mnemonic_forwards_matches (arg_ : word_width)
+: bool :=
+
+ match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end.
+
+Definition size_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "b")) then true
+ else if ((generic_eq p0_ "h")) then true
+ else if ((generic_eq p0_ "w")) then true
+ else if ((generic_eq p0_ "d")) then true
+ else false.
+
+Definition _s36_ (_s37_ : string)
+: option string :=
+
+ let _s38_ := _s37_ in
+ if ((string_startswith _s38_ "d")) then
+ match (string_drop _s38_ (projT1 (string_length "d"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s32_ (_s33_ : string)
+: option string :=
+
+ let _s34_ := _s33_ in
+ if ((string_startswith _s34_ "w")) then
+ match (string_drop _s34_ (projT1 (string_length "w"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s28_ (_s29_ : string)
+: option string :=
+
+ let _s30_ := _s29_ in
+ if ((string_startswith _s30_ "h")) then
+ match (string_drop _s30_ (projT1 (string_length "h"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s24_ (_s25_ : string)
+: option string :=
+
+ let _s26_ := _s25_ in
+ if ((string_startswith _s26_ "b")) then
+ match (string_drop _s26_ (projT1 (string_length "b"))) with | s_ => Some (s_) end
+ else None.
+
+Definition size_mnemonic_matches_prefix (arg_ : string)
+: M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s27_ := arg_ in
+ (if ((match (_s24_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s24_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((BYTE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s28_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s28_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((HALF, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s32_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s32_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((WORD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s36_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s36_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((DOUBLE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((word_width * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))).
+
+Definition word_width_bytes (width : word_width)
+: {s : Z & ArithFact (s = 1 \/ s = 2 \/ s = 4 \/ s = 8)} :=
+
+ build_ex(match width with | BYTE => 1 | HALF => 2 | WORD => 4 | DOUBLE => 8 end).
+
+Definition zero_reg : regtype := EXTZ 32 (vec_of_bits [B0;B0;B0;B0] : mword 4).
+Hint Unfold zero_reg : sail.
+Definition RegStr (r : mword 32) : string := string_of_bits r.
+
+Definition regval_from_reg (r : mword 32) : mword 32 := r.
+
+Definition regval_into_reg (v : mword 32) : mword 32 := v.
+
+Definition rX (r : Z) `{ArithFact (0 <= r /\ r < 32)}
+: M (mword 32) :=
+
+ let l__62 := r in
+ (if sumbool_of_bool ((Z.eqb l__62 0)) then returnm (zero_reg : mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 1)) then
+ ((read_reg x1_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 2)) then
+ ((read_reg x2_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 3)) then
+ ((read_reg x3_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 4)) then
+ ((read_reg x4_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 5)) then
+ ((read_reg x5_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 6)) then
+ ((read_reg x6_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 7)) then
+ ((read_reg x7_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 8)) then
+ ((read_reg x8_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 9)) then
+ ((read_reg x9_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 10)) then
+ ((read_reg x10_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 11)) then
+ ((read_reg x11_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 12)) then
+ ((read_reg x12_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 13)) then
+ ((read_reg x13_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 14)) then
+ ((read_reg x14_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 15)) then
+ ((read_reg x15_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 16)) then
+ ((read_reg x16_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 17)) then
+ ((read_reg x17_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 18)) then
+ ((read_reg x18_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 19)) then
+ ((read_reg x19_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 20)) then
+ ((read_reg x20_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 21)) then
+ ((read_reg x21_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 22)) then
+ ((read_reg x22_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 23)) then
+ ((read_reg x23_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 24)) then
+ ((read_reg x24_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 25)) then
+ ((read_reg x25_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 26)) then
+ ((read_reg x26_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 27)) then
+ ((read_reg x27_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 28)) then
+ ((read_reg x28_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 29)) then
+ ((read_reg x29_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 30)) then
+ ((read_reg x30_ref) : M (mword 32))
+ : M (mword 32)
+ else if sumbool_of_bool ((Z.eqb l__62 31)) then
+ ((read_reg x31_ref) : M (mword 32))
+ : M (mword 32)
+ else assert_exp' false "invalid register number" >>= fun _ => exit tt) >>= fun v : regtype =>
+ returnm ((regval_from_reg v)
+ : mword 32).
+
+Definition rvfi_wX (r : Z) (v : mword 32) `{ArithFact (0 <= r /\ r < 32)} : unit := tt.
+
+Definition wX (r : Z) (in_v : mword 32) `{ArithFact (0 <= r /\ r < 32)}
+: M (unit) :=
+
+ let v := regval_into_reg in_v in
+ let l__30 := r in
+ (if sumbool_of_bool ((Z.eqb l__30 0)) then returnm (tt : unit)
+ else if sumbool_of_bool ((Z.eqb l__30 1)) then write_reg x1_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 2)) then write_reg x2_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 3)) then write_reg x3_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 4)) then write_reg x4_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 5)) then write_reg x5_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 6)) then write_reg x6_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 7)) then write_reg x7_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 8)) then write_reg x8_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 9)) then write_reg x9_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 10)) then write_reg x10_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 11)) then write_reg x11_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 12)) then write_reg x12_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 13)) then write_reg x13_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 14)) then write_reg x14_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 15)) then write_reg x15_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 16)) then write_reg x16_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 17)) then write_reg x17_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 18)) then write_reg x18_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 19)) then write_reg x19_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 20)) then write_reg x20_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 21)) then write_reg x21_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 22)) then write_reg x22_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 23)) then write_reg x23_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 24)) then write_reg x24_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 25)) then write_reg x25_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 26)) then write_reg x26_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 27)) then write_reg x27_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 28)) then write_reg x28_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 29)) then write_reg x29_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 30)) then write_reg x30_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__30 31)) then write_reg x31_ref v : M (unit)
+ else assert_exp' false "invalid register number" >>= fun _ => exit tt) >>
+ returnm ((if sumbool_of_bool ((projT1 (neq_int r 0))) then
+ let '_ := (rvfi_wX r in_v) : unit in
+ if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "x"
+ (String.append (string_of_int r) (String.append " <- " (RegStr v))))
+ else tt
+ else tt)
+ : unit).
+
+Definition reg_name_abi (r : mword 5)
+: M (string) :=
+
+ let b__0 := r in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm ("zero" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm ("ra" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then returnm ("sp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then returnm ("gp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm ("tp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then returnm ("t0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then returnm ("t1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then returnm ("t2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm ("fp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then returnm ("a5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm ("a6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then returnm ("a7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then returnm ("s2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then returnm ("s3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm ("s4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then returnm ("s5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then returnm ("s6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then returnm ("s7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then returnm ("s8" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then returnm ("s9" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then returnm ("s10" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then returnm ("s11" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then returnm ("t3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then returnm ("t4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then returnm ("t5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then returnm ("t6" : string)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_regs.sail 149:2 - 182:3" >>= fun _ =>
+ exit tt)
+ : M (string).
+
+Definition reg_name_forwards (arg_ : mword 5)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm ("zero" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm ("ra" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then returnm ("sp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then returnm ("gp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm ("tp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then returnm ("t0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then returnm ("t1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then returnm ("t2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm ("fp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then returnm ("a5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm ("a6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then returnm ("a7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then returnm ("s2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then returnm ("s3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm ("s4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then returnm ("s5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then returnm ("s6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then returnm ("s7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then returnm ("s8" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then returnm ("s9" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then returnm ("s10" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then returnm ("s11" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then returnm ("t3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then returnm ("t4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then returnm ("t5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then returnm ("t6" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition reg_name_backwards (arg_ : string)
+: M (mword 5) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "zero")) then returnm ((vec_of_bits [B0;B0;B0;B0;B0] : mword 5) : mword 5)
+ else if ((generic_eq p0_ "ra")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "sp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "gp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "tp")) then
+ returnm ((vec_of_bits [B0;B0;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "fp")) then
+ returnm ((vec_of_bits [B0;B1;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s1")) then
+ returnm ((vec_of_bits [B0;B1;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a0")) then
+ returnm ((vec_of_bits [B0;B1;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a1")) then
+ returnm ((vec_of_bits [B0;B1;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a2")) then
+ returnm ((vec_of_bits [B0;B1;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a3")) then
+ returnm ((vec_of_bits [B0;B1;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a4")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a5")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a6")) then
+ returnm ((vec_of_bits [B1;B0;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a7")) then
+ returnm ((vec_of_bits [B1;B0;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s2")) then
+ returnm ((vec_of_bits [B1;B0;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s3")) then
+ returnm ((vec_of_bits [B1;B0;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s4")) then
+ returnm ((vec_of_bits [B1;B0;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s5")) then
+ returnm ((vec_of_bits [B1;B0;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s6")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s7")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s8")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s9")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s10")) then
+ returnm ((vec_of_bits [B1;B1;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s11")) then
+ returnm ((vec_of_bits [B1;B1;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t3")) then
+ returnm ((vec_of_bits [B1;B1;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t4")) then
+ returnm ((vec_of_bits [B1;B1;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t5")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t6")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B1] : mword 5)
+ : mword 5)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 5).
+
+Definition reg_name_forwards_matches (arg_ : mword 5)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then true
+ else false.
+
+Definition reg_name_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "zero")) then true
+ else if ((generic_eq p0_ "ra")) then true
+ else if ((generic_eq p0_ "sp")) then true
+ else if ((generic_eq p0_ "gp")) then true
+ else if ((generic_eq p0_ "tp")) then true
+ else if ((generic_eq p0_ "t0")) then true
+ else if ((generic_eq p0_ "t1")) then true
+ else if ((generic_eq p0_ "t2")) then true
+ else if ((generic_eq p0_ "fp")) then true
+ else if ((generic_eq p0_ "s1")) then true
+ else if ((generic_eq p0_ "a0")) then true
+ else if ((generic_eq p0_ "a1")) then true
+ else if ((generic_eq p0_ "a2")) then true
+ else if ((generic_eq p0_ "a3")) then true
+ else if ((generic_eq p0_ "a4")) then true
+ else if ((generic_eq p0_ "a5")) then true
+ else if ((generic_eq p0_ "a6")) then true
+ else if ((generic_eq p0_ "a7")) then true
+ else if ((generic_eq p0_ "s2")) then true
+ else if ((generic_eq p0_ "s3")) then true
+ else if ((generic_eq p0_ "s4")) then true
+ else if ((generic_eq p0_ "s5")) then true
+ else if ((generic_eq p0_ "s6")) then true
+ else if ((generic_eq p0_ "s7")) then true
+ else if ((generic_eq p0_ "s8")) then true
+ else if ((generic_eq p0_ "s9")) then true
+ else if ((generic_eq p0_ "s10")) then true
+ else if ((generic_eq p0_ "s11")) then true
+ else if ((generic_eq p0_ "t3")) then true
+ else if ((generic_eq p0_ "t4")) then true
+ else if ((generic_eq p0_ "t5")) then true
+ else if ((generic_eq p0_ "t6")) then true
+ else false.
+
+Definition _s164_ (_s165_ : string)
+: option string :=
+
+ let _s166_ := _s165_ in
+ if ((string_startswith _s166_ "t6")) then
+ match (string_drop _s166_ (projT1 (string_length "t6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s160_ (_s161_ : string)
+: option string :=
+
+ let _s162_ := _s161_ in
+ if ((string_startswith _s162_ "t5")) then
+ match (string_drop _s162_ (projT1 (string_length "t5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s156_ (_s157_ : string)
+: option string :=
+
+ let _s158_ := _s157_ in
+ if ((string_startswith _s158_ "t4")) then
+ match (string_drop _s158_ (projT1 (string_length "t4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s152_ (_s153_ : string)
+: option string :=
+
+ let _s154_ := _s153_ in
+ if ((string_startswith _s154_ "t3")) then
+ match (string_drop _s154_ (projT1 (string_length "t3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s148_ (_s149_ : string)
+: option string :=
+
+ let _s150_ := _s149_ in
+ if ((string_startswith _s150_ "s11")) then
+ match (string_drop _s150_ (projT1 (string_length "s11"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s144_ (_s145_ : string)
+: option string :=
+
+ let _s146_ := _s145_ in
+ if ((string_startswith _s146_ "s10")) then
+ match (string_drop _s146_ (projT1 (string_length "s10"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s140_ (_s141_ : string)
+: option string :=
+
+ let _s142_ := _s141_ in
+ if ((string_startswith _s142_ "s9")) then
+ match (string_drop _s142_ (projT1 (string_length "s9"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s136_ (_s137_ : string)
+: option string :=
+
+ let _s138_ := _s137_ in
+ if ((string_startswith _s138_ "s8")) then
+ match (string_drop _s138_ (projT1 (string_length "s8"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s132_ (_s133_ : string)
+: option string :=
+
+ let _s134_ := _s133_ in
+ if ((string_startswith _s134_ "s7")) then
+ match (string_drop _s134_ (projT1 (string_length "s7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s128_ (_s129_ : string)
+: option string :=
+
+ let _s130_ := _s129_ in
+ if ((string_startswith _s130_ "s6")) then
+ match (string_drop _s130_ (projT1 (string_length "s6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s124_ (_s125_ : string)
+: option string :=
+
+ let _s126_ := _s125_ in
+ if ((string_startswith _s126_ "s5")) then
+ match (string_drop _s126_ (projT1 (string_length "s5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s120_ (_s121_ : string)
+: option string :=
+
+ let _s122_ := _s121_ in
+ if ((string_startswith _s122_ "s4")) then
+ match (string_drop _s122_ (projT1 (string_length "s4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s116_ (_s117_ : string)
+: option string :=
+
+ let _s118_ := _s117_ in
+ if ((string_startswith _s118_ "s3")) then
+ match (string_drop _s118_ (projT1 (string_length "s3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s112_ (_s113_ : string)
+: option string :=
+
+ let _s114_ := _s113_ in
+ if ((string_startswith _s114_ "s2")) then
+ match (string_drop _s114_ (projT1 (string_length "s2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s108_ (_s109_ : string)
+: option string :=
+
+ let _s110_ := _s109_ in
+ if ((string_startswith _s110_ "a7")) then
+ match (string_drop _s110_ (projT1 (string_length "a7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s104_ (_s105_ : string)
+: option string :=
+
+ let _s106_ := _s105_ in
+ if ((string_startswith _s106_ "a6")) then
+ match (string_drop _s106_ (projT1 (string_length "a6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s100_ (_s101_ : string)
+: option string :=
+
+ let _s102_ := _s101_ in
+ if ((string_startswith _s102_ "a5")) then
+ match (string_drop _s102_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s96_ (_s97_ : string)
+: option string :=
+
+ let _s98_ := _s97_ in
+ if ((string_startswith _s98_ "a4")) then
+ match (string_drop _s98_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s92_ (_s93_ : string)
+: option string :=
+
+ let _s94_ := _s93_ in
+ if ((string_startswith _s94_ "a3")) then
+ match (string_drop _s94_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s88_ (_s89_ : string)
+: option string :=
+
+ let _s90_ := _s89_ in
+ if ((string_startswith _s90_ "a2")) then
+ match (string_drop _s90_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s84_ (_s85_ : string)
+: option string :=
+
+ let _s86_ := _s85_ in
+ if ((string_startswith _s86_ "a1")) then
+ match (string_drop _s86_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s80_ (_s81_ : string)
+: option string :=
+
+ let _s82_ := _s81_ in
+ if ((string_startswith _s82_ "a0")) then
+ match (string_drop _s82_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s76_ (_s77_ : string)
+: option string :=
+
+ let _s78_ := _s77_ in
+ if ((string_startswith _s78_ "s1")) then
+ match (string_drop _s78_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s72_ (_s73_ : string)
+: option string :=
+
+ let _s74_ := _s73_ in
+ if ((string_startswith _s74_ "fp")) then
+ match (string_drop _s74_ (projT1 (string_length "fp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s68_ (_s69_ : string)
+: option string :=
+
+ let _s70_ := _s69_ in
+ if ((string_startswith _s70_ "t2")) then
+ match (string_drop _s70_ (projT1 (string_length "t2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s64_ (_s65_ : string)
+: option string :=
+
+ let _s66_ := _s65_ in
+ if ((string_startswith _s66_ "t1")) then
+ match (string_drop _s66_ (projT1 (string_length "t1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s60_ (_s61_ : string)
+: option string :=
+
+ let _s62_ := _s61_ in
+ if ((string_startswith _s62_ "t0")) then
+ match (string_drop _s62_ (projT1 (string_length "t0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s56_ (_s57_ : string)
+: option string :=
+
+ let _s58_ := _s57_ in
+ if ((string_startswith _s58_ "tp")) then
+ match (string_drop _s58_ (projT1 (string_length "tp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s52_ (_s53_ : string)
+: option string :=
+
+ let _s54_ := _s53_ in
+ if ((string_startswith _s54_ "gp")) then
+ match (string_drop _s54_ (projT1 (string_length "gp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s48_ (_s49_ : string)
+: option string :=
+
+ let _s50_ := _s49_ in
+ if ((string_startswith _s50_ "sp")) then
+ match (string_drop _s50_ (projT1 (string_length "sp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s44_ (_s45_ : string)
+: option string :=
+
+ let _s46_ := _s45_ in
+ if ((string_startswith _s46_ "ra")) then
+ match (string_drop _s46_ (projT1 (string_length "ra"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s40_ (_s41_ : string)
+: option string :=
+
+ let _s42_ := _s41_ in
+ if ((string_startswith _s42_ "zero")) then
+ match (string_drop _s42_ (projT1 (string_length "zero"))) with | s_ => Some (s_) end
+ else None.
+
+Definition reg_name_matches_prefix (arg_ : string)
+: M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s43_ := arg_ in
+ (if ((match (_s40_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s40_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s44_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s44_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s48_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s48_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s52_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s52_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s56_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s56_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s60_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s60_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s64_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s64_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s68_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s68_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s72_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s72_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s76_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s76_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s80_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s80_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s84_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s84_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s88_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s88_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s92_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s92_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s96_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s96_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s100_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s100_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s104_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s104_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s108_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s108_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s112_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s112_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s116_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s116_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s120_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s120_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s124_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s124_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s128_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s128_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s132_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s132_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s136_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s136_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s140_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s140_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s144_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s144_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s148_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s148_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s152_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s152_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s156_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s156_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s160_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s160_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s164_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s164_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition creg_name_forwards (arg_ : mword 3)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm ("s0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm ("a5" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition creg_name_backwards (arg_ : string)
+: M (mword 3) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "s0")) then returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "s1")) then returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a0")) then returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a1")) then returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a2")) then returnm ((vec_of_bits [B1;B0;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a3")) then returnm ((vec_of_bits [B1;B0;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a4")) then returnm ((vec_of_bits [B1;B1;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a5")) then returnm ((vec_of_bits [B1;B1;B1] : mword 3) : mword 3)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 3).
+
+Definition creg_name_forwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else false.
+
+Definition creg_name_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "s0")) then true
+ else if ((generic_eq p0_ "s1")) then true
+ else if ((generic_eq p0_ "a0")) then true
+ else if ((generic_eq p0_ "a1")) then true
+ else if ((generic_eq p0_ "a2")) then true
+ else if ((generic_eq p0_ "a3")) then true
+ else if ((generic_eq p0_ "a4")) then true
+ else if ((generic_eq p0_ "a5")) then true
+ else false.
+
+Definition _s196_ (_s197_ : string)
+: option string :=
+
+ let _s198_ := _s197_ in
+ if ((string_startswith _s198_ "a5")) then
+ match (string_drop _s198_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s192_ (_s193_ : string)
+: option string :=
+
+ let _s194_ := _s193_ in
+ if ((string_startswith _s194_ "a4")) then
+ match (string_drop _s194_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s188_ (_s189_ : string)
+: option string :=
+
+ let _s190_ := _s189_ in
+ if ((string_startswith _s190_ "a3")) then
+ match (string_drop _s190_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s184_ (_s185_ : string)
+: option string :=
+
+ let _s186_ := _s185_ in
+ if ((string_startswith _s186_ "a2")) then
+ match (string_drop _s186_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s180_ (_s181_ : string)
+: option string :=
+
+ let _s182_ := _s181_ in
+ if ((string_startswith _s182_ "a1")) then
+ match (string_drop _s182_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s176_ (_s177_ : string)
+: option string :=
+
+ let _s178_ := _s177_ in
+ if ((string_startswith _s178_ "a0")) then
+ match (string_drop _s178_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s172_ (_s173_ : string)
+: option string :=
+
+ let _s174_ := _s173_ in
+ if ((string_startswith _s174_ "s1")) then
+ match (string_drop _s174_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s168_ (_s169_ : string)
+: option string :=
+
+ let _s170_ := _s169_ in
+ if ((string_startswith _s170_ "s0")) then
+ match (string_drop _s170_ (projT1 (string_length "s0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition creg_name_matches_prefix (arg_ : string)
+: M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s171_ := arg_ in
+ (if ((match (_s168_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s168_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s172_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s172_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s176_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s176_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s180_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s180_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s184_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s184_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s188_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s188_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s192_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s192_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s196_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s196_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition init_base_regs '(tt : unit)
+: M (unit) :=
+
+ write_reg x1_ref zero_reg >>
+ write_reg x2_ref zero_reg >>
+ write_reg x3_ref zero_reg >>
+ write_reg x4_ref zero_reg >>
+ write_reg x5_ref zero_reg >>
+ write_reg x6_ref zero_reg >>
+ write_reg x7_ref zero_reg >>
+ write_reg x8_ref zero_reg >>
+ write_reg x9_ref zero_reg >>
+ write_reg x10_ref zero_reg >>
+ write_reg x11_ref zero_reg >>
+ write_reg x12_ref zero_reg >>
+ write_reg x13_ref zero_reg >>
+ write_reg x14_ref zero_reg >>
+ write_reg x15_ref zero_reg >>
+ write_reg x16_ref zero_reg >>
+ write_reg x17_ref zero_reg >>
+ write_reg x18_ref zero_reg >>
+ write_reg x19_ref zero_reg >>
+ write_reg x20_ref zero_reg >>
+ write_reg x21_ref zero_reg >>
+ write_reg x22_ref zero_reg >>
+ write_reg x23_ref zero_reg >>
+ write_reg x24_ref zero_reg >>
+ write_reg x25_ref zero_reg >>
+ write_reg x26_ref zero_reg >>
+ write_reg x27_ref zero_reg >>
+ write_reg x28_ref zero_reg >>
+ write_reg x29_ref zero_reg >>
+ write_reg x30_ref zero_reg >> write_reg x31_ref zero_reg : M (unit).
+
+Definition get_arch_pc '(tt : unit)
+: M (mword 32) :=
+
+ ((read_reg PC_ref) : M (mword 32))
+ : M (mword 32).
+
+Definition get_next_pc '(tt : unit)
+: M (mword 32) :=
+
+ ((read_reg nextPC_ref) : M (mword 32))
+ : M (mword 32).
+
+Definition set_next_pc (pc : mword 32) : M (unit) := write_reg nextPC_ref pc : M (unit).
+
+Definition tick_pc '(tt : unit)
+: M (unit) :=
+
+ ((read_reg nextPC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ write_reg PC_ref w__0
+ : M (unit).
+
+Definition Mk_Misa (v : mword 32) : Misa := {| Misa_Misa_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Misa_bits (v : Misa) : mword 32 := subrange_vec_dec v.(Misa_Misa_chunk_0) 31 0.
+
+Definition _set_Misa_bits (r_ref : register_ref regstate register_value Misa) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_bits (v : Misa) (x : mword 32)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Misa_MXL (v : Misa) : mword 2 := subrange_vec_dec v.(Misa_Misa_chunk_0) 31 30.
+
+Definition _set_Misa_MXL (r_ref : register_ref regstate register_value Misa) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 31 30 (subrange_vec_dec v 1 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_MXL (v : Misa) (x : mword 2)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 31 30 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Misa_Z (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25.
+
+Definition _set_Misa_Z (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Z (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_Y (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24.
+
+Definition _set_Misa_Y (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Y (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_X (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23.
+
+Definition _set_Misa_X (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_X (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_W (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22.
+
+Definition _set_Misa_W (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_W (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_V (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21.
+
+Definition _set_Misa_V (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_V (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_U (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20.
+
+Definition _set_Misa_U (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_U (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_T (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19.
+
+Definition _set_Misa_T (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_T (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_S (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18.
+
+Definition _set_Misa_S (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_S (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_R (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17.
+
+Definition _set_Misa_R (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_R (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_Q (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16.
+
+Definition _set_Misa_Q (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Q (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_P (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15.
+
+Definition _set_Misa_P (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_P (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_O (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14.
+
+Definition _set_Misa_O (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_O (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_N (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13.
+
+Definition _set_Misa_N (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_N (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_M (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12.
+
+Definition _set_Misa_M (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_M (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_L (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11.
+
+Definition _set_Misa_L (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_L (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_K (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10.
+
+Definition _set_Misa_K (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_K (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_J (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9.
+
+Definition _set_Misa_J (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_J (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_I (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8.
+
+Definition _set_Misa_I (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_I (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_H (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7.
+
+Definition _set_Misa_H (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_H (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_G (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6.
+
+Definition _set_Misa_G (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_G (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_F (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5.
+
+Definition _set_Misa_F (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_F (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_E (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4.
+
+Definition _set_Misa_E (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_E (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_D (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3.
+
+Definition _set_Misa_D (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_D (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_C (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2.
+
+Definition _set_Misa_C (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_C (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_B (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1.
+
+Definition _set_Misa_B (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_B (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_A (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0.
+
+Definition _set_Misa_A (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_A (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_misa (m : Misa) (v : mword 32)
+: M (Misa) :=
+
+ (if ((sys_enable_writable_misa tt)) then
+ let v := Mk_Misa v in
+ (and_boolM (returnm ((eq_vec (_get_Misa_C v) ((bool_to_bits false) : mword 1)) : bool))
+ (((read_reg nextPC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ (bit_to_bool (access_vec_dec w__0 1)) >>= fun w__1 : bool =>
+ returnm ((Bool.eqb w__1 true)
+ : bool))) >>= fun w__2 : bool =>
+ returnm ((if sumbool_of_bool (w__2) then m
+ else _update_Misa_C m (_get_Misa_C v))
+ : Misa)
+ else returnm (m : Misa))
+ : M (Misa).
+
+Definition haveAtomics '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_A w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveRVC '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveMulDiv '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_M w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveSupMode '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_S w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveUsrMode '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_U w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveNExt '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_N w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition Mk_Mstatus (v : mword 32)
+: Mstatus :=
+
+ {| Mstatus_Mstatus_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Mstatus_bits (v : Mstatus)
+: mword 32 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 31 0.
+
+Definition _set_Mstatus_bits (r_ref : register_ref regstate register_value Mstatus) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_bits (v : Mstatus) (x : mword 32)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Mstatus_SD (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 31 31.
+
+Definition _set_Mstatus_SD (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SD (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TSR (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22.
+
+Definition _set_Mstatus_TSR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TSR (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TW (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21.
+
+Definition _set_Mstatus_TW (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TW (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TVM (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20.
+
+Definition _set_Mstatus_TVM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TVM (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MXR (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19.
+
+Definition _set_Mstatus_MXR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MXR (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SUM (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18.
+
+Definition _set_Mstatus_SUM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SUM (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MPRV (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17.
+
+Definition _set_Mstatus_MPRV (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPRV (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_XS (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15.
+
+Definition _set_Mstatus_XS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_XS (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_FS (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13.
+
+Definition _set_Mstatus_FS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_FS (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_MPP (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11.
+
+Definition _set_Mstatus_MPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPP (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_SPP (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8.
+
+Definition _set_Mstatus_SPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SPP (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7.
+
+Definition _set_Mstatus_MPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5.
+
+Definition _set_Mstatus_SPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_UPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4.
+
+Definition _set_Mstatus_UPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_UPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3.
+
+Definition _set_Mstatus_MIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1.
+
+Definition _set_Mstatus_SIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_UIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0.
+
+Definition _set_Mstatus_UIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_UIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition effectivePrivilege (m : Mstatus) (priv : Privilege)
+: M (Privilege) :=
+
+ (if ((eq_vec (_get_Mstatus_MPRV m) ((bool_to_bits true) : mword 1))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (privLevel_of_bits (_get_Mstatus_MPP w__0))
+ : M (Privilege)
+ else read_reg cur_privilege_ref : M (Privilege))
+ : M (Privilege).
+
+Definition get_mstatus_SXL (m : Mstatus) : mword 2 := arch_to_bits RV32.
+
+Definition set_mstatus_SXL (m : Mstatus) (a : mword 2) : Mstatus := m.
+
+Definition get_mstatus_UXL (m : Mstatus) : mword 2 := arch_to_bits RV32.
+
+Definition set_mstatus_UXL (m : Mstatus) (a : mword 2) : Mstatus := m.
+
+Definition legalize_mstatus (o : Mstatus) (v : mword 32)
+: M (Mstatus) :=
+
+ let m : Mstatus := Mk_Mstatus v in
+ let m := _update_Mstatus_XS m (extStatus_to_bits Off) in
+ (or_boolM
+ ((extStatus_of_bits (_get_Mstatus_FS m)) >>= fun w__0 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__0) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))
+ ((extStatus_of_bits (_get_Mstatus_XS m)) >>= fun w__1 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__1) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))) >>= fun w__2 : bool =>
+ let m := _update_Mstatus_SD m ((bool_to_bits w__2) : mword 1) in
+ let m := set_mstatus_SXL m (get_mstatus_SXL o) in
+ let m := set_mstatus_UXL m (get_mstatus_UXL o) in
+ let m := _update_Mstatus_UPIE m ((bool_to_bits false) : mword 1) in
+ let m := _update_Mstatus_UIE m ((bool_to_bits false) : mword 1) in
+ returnm (m
+ : Mstatus).
+
+Definition cur_Architecture '(tt : unit)
+: M (Architecture) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | Machine => read_reg misa_ref >>= fun w__1 : Misa => returnm ((_get_Misa_MXL w__1) : mword 2)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus => returnm ((get_mstatus_SXL w__2) : mword 2)
+ | User =>
+ read_reg mstatus_ref >>= fun w__3 : Mstatus => returnm ((get_mstatus_UXL w__3) : mword 2)
+ end) >>= fun a : arch_xlen =>
+ (match (architecture a) with
+ | Some (a) => returnm (a : Architecture)
+ | None => (internal_error "Invalid current architecture") : M (Architecture)
+ end)
+ : M (Architecture).
+
+Definition in32BitMode '(tt : unit)
+: M (bool) :=
+
+ (cur_Architecture tt) >>= fun w__0 : Architecture => returnm ((generic_eq w__0 RV32) : bool).
+
+Definition Mk_Minterrupts (v : mword 32)
+: Minterrupts :=
+
+ {| Minterrupts_Minterrupts_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Minterrupts_bits (v : Minterrupts)
+: mword 32 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 31 0.
+
+Definition _set_Minterrupts_bits
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_bits (v : Minterrupts) (x : mword 32)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Minterrupts_MEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11.
+
+Definition _set_Minterrupts_MEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_SEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9.
+
+Definition _set_Minterrupts_SEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_SEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_UEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8.
+
+Definition _set_Minterrupts_UEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_UEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_MTI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7.
+
+Definition _set_Minterrupts_MTI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MTI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_STI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5.
+
+Definition _set_Minterrupts_STI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_STI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_UTI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4.
+
+Definition _set_Minterrupts_UTI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_UTI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_MSI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3.
+
+Definition _set_Minterrupts_MSI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MSI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_SSI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1.
+
+Definition _set_Minterrupts_SSI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_SSI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_USI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0.
+
+Definition _set_Minterrupts_USI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_USI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_mip (o : Minterrupts) (v : mword 32)
+: M (Minterrupts) :=
+
+ let v := Mk_Minterrupts v in
+ let m := _update_Minterrupts_SEI o (_get_Minterrupts_SEI v) in
+ let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in
+ let m := _update_Minterrupts_SSI m (_get_Minterrupts_SSI v) in
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m := _update_Minterrupts_UEI m (_get_Minterrupts_UEI v) in
+ let m := _update_Minterrupts_UTI m (_get_Minterrupts_UTI v) in
+ _update_Minterrupts_USI m (_get_Minterrupts_USI v)
+ else m)
+ : Minterrupts).
+
+Definition legalize_mie (o : Minterrupts) (v : mword 32)
+: M (Minterrupts) :=
+
+ let v := Mk_Minterrupts v in
+ let m := _update_Minterrupts_MEI o (_get_Minterrupts_MEI v) in
+ let m := _update_Minterrupts_MTI m (_get_Minterrupts_MTI v) in
+ let m := _update_Minterrupts_MSI m (_get_Minterrupts_MSI v) in
+ let m := _update_Minterrupts_SEI m (_get_Minterrupts_SEI v) in
+ let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in
+ let m := _update_Minterrupts_SSI m (_get_Minterrupts_SSI v) in
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m := _update_Minterrupts_UEI m (_get_Minterrupts_UEI v) in
+ let m := _update_Minterrupts_UTI m (_get_Minterrupts_UTI v) in
+ _update_Minterrupts_USI m (_get_Minterrupts_USI v)
+ else m)
+ : Minterrupts).
+
+Definition legalize_mideleg (o : Minterrupts) (v : mword 32)
+: Minterrupts :=
+
+ let m := Mk_Minterrupts v in
+ let m := _update_Minterrupts_MEI m ((bool_to_bits false) : mword 1) in
+ let m := _update_Minterrupts_MTI m ((bool_to_bits false) : mword 1) in
+ _update_Minterrupts_MSI m ((bool_to_bits false) : mword 1).
+
+Definition Mk_Medeleg (v : mword 32)
+: Medeleg :=
+
+ {| Medeleg_Medeleg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Medeleg_bits (v : Medeleg)
+: mword 32 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 31 0.
+
+Definition _set_Medeleg_bits (r_ref : register_ref regstate register_value Medeleg) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_bits (v : Medeleg) (x : mword 32)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15.
+
+Definition _set_Medeleg_SAMO_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13.
+
+Definition _set_Medeleg_Load_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12.
+
+Definition _set_Medeleg_Fetch_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_MEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10.
+
+Definition _set_Medeleg_MEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_MEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9.
+
+Definition _set_Medeleg_SEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_UEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8.
+
+Definition _set_Medeleg_UEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_UEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7.
+
+Definition _set_Medeleg_SAMO_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6.
+
+Definition _set_Medeleg_SAMO_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5.
+
+Definition _set_Medeleg_Load_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4.
+
+Definition _set_Medeleg_Load_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Breakpoint (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3.
+
+Definition _set_Medeleg_Breakpoint
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Breakpoint (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Illegal_Instr (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2.
+
+Definition _set_Medeleg_Illegal_Instr
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Illegal_Instr (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1.
+
+Definition _set_Medeleg_Fetch_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0.
+
+Definition _set_Medeleg_Fetch_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_medeleg (o : Medeleg) (v : mword 32)
+: Medeleg :=
+
+ let m := Mk_Medeleg v in
+ _update_Medeleg_MEnvCall m ((bool_to_bits false) : mword 1).
+
+Definition Mk_Mtvec (v : mword 32)
+: Mtvec :=
+
+ {| Mtvec_Mtvec_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Mtvec_bits (v : Mtvec)
+: mword 32 :=
+
+ subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 31 0.
+
+Definition _set_Mtvec_bits (r_ref : register_ref regstate register_value Mtvec) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_bits (v : Mtvec) (x : mword 32)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Mtvec_Base (v : Mtvec)
+: mword 30 :=
+
+ subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 31 2.
+
+Definition _set_Mtvec_Base (r_ref : register_ref regstate register_value Mtvec) (v : mword 30)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 31 2 (subrange_vec_dec v 29 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_Base (v : Mtvec) (x : mword 30)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 31 2 (subrange_vec_dec x 29 0)) ]}.
+
+Definition _get_Mtvec_Mode (v : Mtvec) : mword 2 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0.
+
+Definition _set_Mtvec_Mode (r_ref : register_ref regstate register_value Mtvec) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec v 1 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_Mode (v : Mtvec) (x : mword 2)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec x 1 0)) ]}.
+
+Definition legalize_tvec (o : Mtvec) (v : mword 32)
+: Mtvec :=
+
+ let v := Mk_Mtvec v in
+ match (trapVectorMode_of_bits (_get_Mtvec_Mode v)) with
+ | TV_Direct => v
+ | TV_Vector => v
+ | _ => _update_Mtvec_Mode v (_get_Mtvec_Mode o)
+ end.
+
+Definition Mk_Mcause (v : mword 32)
+: Mcause :=
+
+ {| Mcause_Mcause_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Mcause_bits (v : Mcause)
+: mword 32 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 31 0.
+
+Definition _set_Mcause_bits (r_ref : register_ref regstate register_value Mcause) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_bits (v : Mcause) (x : mword 32)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Mcause_IsInterrupt (v : Mcause)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 31 31.
+
+Definition _set_Mcause_IsInterrupt
+(r_ref : register_ref regstate register_value Mcause) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_IsInterrupt (v : Mcause) (x : mword 1)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mcause_Cause (v : Mcause)
+: mword 31 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 30 0.
+
+Definition _set_Mcause_Cause (r_ref : register_ref regstate register_value Mcause) (v : mword 31)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 30 0 (subrange_vec_dec v 30 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_Cause (v : Mcause) (x : mword 31)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 30 0 (subrange_vec_dec x 30 0)) ]}.
+
+Definition tvec_addr (m : Mtvec) (c : Mcause)
+: option (mword 32) :=
+
+ let base : xlenbits := concat_vec (_get_Mtvec_Base m) (vec_of_bits [B0;B0] : mword 2) in
+ match (trapVectorMode_of_bits (_get_Mtvec_Mode m)) with
+ | TV_Direct => Some (base)
+ | TV_Vector =>
+ if ((eq_vec (_get_Mcause_IsInterrupt c) ((bool_to_bits true) : mword 1))) then
+ Some
+ (add_vec base (shiftl (EXTZ 32 (_get_Mcause_Cause c)) 2))
+ else Some (base)
+ | TV_Reserved => None
+ end.
+
+Definition legalize_xepc (v : mword 32)
+: M (mword 32) :=
+
+ (or_boolM (returnm ((sys_enable_writable_misa tt) : bool))
+ (read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))
+ : bool))) >>= fun w__1 : bool =>
+ returnm ((if sumbool_of_bool (w__1) then update_vec_dec v 0 B0
+ else and_vec v (EXTS 32 (vec_of_bits [B1;B0;B0] : mword 3)))
+ : mword 32).
+
+Definition pc_alignment_mask '(tt : unit)
+: M (mword 32) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((not_vec
+ (EXTZ 32
+ (if ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))) then
+ (vec_of_bits [B0;B0] : mword 2)
+ else (vec_of_bits [B1;B0] : mword 2))))
+ : mword 32).
+
+Definition Mk_Counteren (v : mword 32)
+: Counteren :=
+
+ {| Counteren_Counteren_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Counteren_bits (v : Counteren)
+: mword 32 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0.
+
+Definition _set_Counteren_bits
+(r_ref : register_ref regstate register_value Counteren) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_bits (v : Counteren) (x : mword 32)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Counteren_HPM (v : Counteren)
+: mword 29 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3.
+
+Definition _set_Counteren_HPM
+(r_ref : register_ref regstate register_value Counteren) (v : mword 29)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec v 28 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_HPM (v : Counteren) (x : mword 29)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec x 28 0)) ]}.
+
+Definition _get_Counteren_IR (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2.
+
+Definition _set_Counteren_IR (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_IR (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Counteren_TM (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1.
+
+Definition _set_Counteren_TM (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_TM (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Counteren_CY (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0.
+
+Definition _set_Counteren_CY (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_CY (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_mcounteren (c : Counteren) (v : mword 32)
+: M (Counteren) :=
+
+ (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 =>
+ let c := _update_Counteren_IR c (w__0 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 =>
+ let c := _update_Counteren_TM c (w__1 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 =>
+ let c := _update_Counteren_CY c (w__2 : mword 1) in
+ returnm (c
+ : Counteren).
+
+Definition legalize_scounteren (c : Counteren) (v : mword 32)
+: M (Counteren) :=
+
+ (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 =>
+ let c := _update_Counteren_IR c (w__0 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 =>
+ let c := _update_Counteren_TM c (w__1 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 =>
+ let c := _update_Counteren_CY c (w__2 : mword 1) in
+ returnm (c
+ : Counteren).
+
+Definition retire_instruction '(tt : unit)
+: M (unit) :=
+
+ read_reg minstret_written_ref >>= fun w__0 : bool =>
+ (if ((Bool.eqb w__0 true)) then write_reg minstret_written_ref false : M (unit)
+ else
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg minstret_ref (add_vec_int w__1 1)
+ : M (unit))
+ : M (unit).
+
+Definition Mk_Sstatus (v : mword 32)
+: Sstatus :=
+
+ {| Sstatus_Sstatus_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Sstatus_bits (v : Sstatus)
+: mword 32 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 31 0.
+
+Definition _set_Sstatus_bits (r_ref : register_ref regstate register_value Sstatus) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_bits (v : Sstatus) (x : mword 32)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Sstatus_SD (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 31 31.
+
+Definition _set_Sstatus_SD (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SD (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_MXR (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19.
+
+Definition _set_Sstatus_MXR (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_MXR (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SUM (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18.
+
+Definition _set_Sstatus_SUM (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SUM (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_XS (v : Sstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15.
+
+Definition _set_Sstatus_XS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_XS (v : Sstatus) (x : mword 2)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Sstatus_FS (v : Sstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13.
+
+Definition _set_Sstatus_FS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_FS (v : Sstatus) (x : mword 2)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Sstatus_SPP (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8.
+
+Definition _set_Sstatus_SPP (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SPP (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SPIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5.
+
+Definition _set_Sstatus_SPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SPIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_UPIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4.
+
+Definition _set_Sstatus_UPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_UPIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1.
+
+Definition _set_Sstatus_SIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_UIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0.
+
+Definition _set_Sstatus_UIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_UIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition get_sstatus_UXL (s : Sstatus)
+: mword 2 :=
+
+ let m := Mk_Mstatus (_get_Sstatus_bits s) in
+ get_mstatus_UXL m.
+
+Definition set_sstatus_UXL (s : Sstatus) (a : mword 2)
+: Sstatus :=
+
+ let m := Mk_Mstatus (_get_Sstatus_bits s) in
+ let m := set_mstatus_UXL m a in
+ Mk_Sstatus (_get_Mstatus_bits m).
+
+Definition lower_mstatus (m : Mstatus)
+: Sstatus :=
+
+ let s := Mk_Sstatus (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sstatus_SD s (_get_Mstatus_SD m) in
+ let s := set_sstatus_UXL s (get_mstatus_UXL m) in
+ let s := _update_Sstatus_MXR s (_get_Mstatus_MXR m) in
+ let s := _update_Sstatus_SUM s (_get_Mstatus_SUM m) in
+ let s := _update_Sstatus_XS s (_get_Mstatus_XS m) in
+ let s := _update_Sstatus_FS s (_get_Mstatus_FS m) in
+ let s := _update_Sstatus_SPP s (_get_Mstatus_SPP m) in
+ let s := _update_Sstatus_SPIE s (_get_Mstatus_SPIE m) in
+ let s := _update_Sstatus_UPIE s (_get_Mstatus_UPIE m) in
+ let s := _update_Sstatus_SIE s (_get_Mstatus_SIE m) in
+ _update_Sstatus_UIE s (_get_Mstatus_UIE m).
+
+Definition lift_sstatus (m : Mstatus) (s : Sstatus)
+: M (Mstatus) :=
+
+ let m := _update_Mstatus_MXR m (_get_Sstatus_MXR s) in
+ let m := _update_Mstatus_SUM m (_get_Sstatus_SUM s) in
+ let m := _update_Mstatus_XS m (_get_Sstatus_XS s) in
+ let m := _update_Mstatus_FS m (_get_Sstatus_FS s) in
+ (or_boolM
+ ((extStatus_of_bits (_get_Mstatus_FS m)) >>= fun w__0 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__0) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))
+ ((extStatus_of_bits (_get_Mstatus_XS m)) >>= fun w__1 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__1) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))) >>= fun w__2 : bool =>
+ let m := _update_Mstatus_SD m ((bool_to_bits w__2) : mword 1) in
+ let m := _update_Mstatus_SPP m (_get_Sstatus_SPP s) in
+ let m := _update_Mstatus_SPIE m (_get_Sstatus_SPIE s) in
+ let m := _update_Mstatus_UPIE m (_get_Sstatus_UPIE s) in
+ let m := _update_Mstatus_SIE m (_get_Sstatus_SIE s) in
+ let m := _update_Mstatus_UIE m (_get_Sstatus_UIE s) in
+ returnm (m
+ : Mstatus).
+
+Definition legalize_sstatus (m : Mstatus) (v : mword 32)
+: M (Mstatus) :=
+
+ (lift_sstatus m (Mk_Sstatus v))
+ : M (Mstatus).
+
+Definition Mk_Sedeleg (v : mword 32)
+: Sedeleg :=
+
+ {| Sedeleg_Sedeleg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Sedeleg_bits (v : Sedeleg)
+: mword 32 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 31 0.
+
+Definition _set_Sedeleg_bits (r_ref : register_ref regstate register_value Sedeleg) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_bits (v : Sedeleg) (x : mword 32)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Sedeleg_UEnvCall (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8.
+
+Definition _set_Sedeleg_UEnvCall
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_UEnvCall (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_SAMO_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7.
+
+Definition _set_Sedeleg_SAMO_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_SAMO_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_SAMO_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6.
+
+Definition _set_Sedeleg_SAMO_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_SAMO_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Load_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5.
+
+Definition _set_Sedeleg_Load_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Load_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Load_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4.
+
+Definition _set_Sedeleg_Load_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Load_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Breakpoint (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3.
+
+Definition _set_Sedeleg_Breakpoint
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Breakpoint (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Illegal_Instr (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2.
+
+Definition _set_Sedeleg_Illegal_Instr
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Illegal_Instr (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Fetch_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1.
+
+Definition _set_Sedeleg_Fetch_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Fetch_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Fetch_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0.
+
+Definition _set_Sedeleg_Fetch_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Fetch_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_sedeleg (s : Sedeleg) (v : mword 32)
+: Sedeleg :=
+
+ Mk_Sedeleg (EXTZ 32 (subrange_vec_dec v 8 0)).
+
+Definition Mk_Sinterrupts (v : mword 32)
+: Sinterrupts :=
+
+ {| Sinterrupts_Sinterrupts_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Sinterrupts_bits (v : Sinterrupts)
+: mword 32 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 31 0.
+
+Definition _set_Sinterrupts_bits
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_bits (v : Sinterrupts) (x : mword 32)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Sinterrupts_SEI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9.
+
+Definition _set_Sinterrupts_SEI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_SEI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_UEI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8.
+
+Definition _set_Sinterrupts_UEI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_UEI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_STI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5.
+
+Definition _set_Sinterrupts_STI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_STI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_UTI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4.
+
+Definition _set_Sinterrupts_UTI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_UTI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_SSI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1.
+
+Definition _set_Sinterrupts_SSI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_SSI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_USI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0.
+
+Definition _set_Sinterrupts_USI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_USI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_mip (m : Minterrupts) (d : Minterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := Mk_Sinterrupts (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in
+ let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in
+ let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in
+ let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in
+ let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in
+ _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)).
+
+Definition lower_mie (m : Minterrupts) (d : Minterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := Mk_Sinterrupts (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in
+ let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in
+ let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in
+ let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in
+ let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in
+ _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)).
+
+Definition lift_sip (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts)
+: M (Minterrupts) :=
+
+ let m : Minterrupts := o in
+ let m := _update_Minterrupts_SSI m (and_vec (_get_Sinterrupts_SSI s) (_get_Minterrupts_SSI d)) in
+ (haveNExt tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s)
+ else m in
+ if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_USI m (_get_Sinterrupts_USI s)
+ else m
+ else m)
+ : Minterrupts).
+
+Definition legalize_sip (m : Minterrupts) (d : Minterrupts) (v : mword 32)
+: M (Minterrupts) :=
+
+ (lift_sip m d (Mk_Sinterrupts v))
+ : M (Minterrupts).
+
+Definition lift_sie (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts)
+: M (Minterrupts) :=
+
+ let m : Minterrupts := o in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_SEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_SEI m (_get_Sinterrupts_SEI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_STI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_STI m (_get_Sinterrupts_STI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_SSI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_SSI m (_get_Sinterrupts_SSI s)
+ else m in
+ (haveNExt tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UTI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UTI m (_get_Sinterrupts_UTI s)
+ else m in
+ if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_USI m (_get_Sinterrupts_USI s)
+ else m
+ else m)
+ : Minterrupts).
+
+Definition legalize_sie (m : Minterrupts) (d : Minterrupts) (v : mword 32)
+: M (Minterrupts) :=
+
+ (lift_sie m d (Mk_Sinterrupts v))
+ : M (Minterrupts).
+
+Definition Mk_Satp64 (v : mword 64)
+: Satp64 :=
+
+ {| Satp64_Satp64_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Satp64_bits (v : Satp64)
+: mword 64 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0.
+
+Definition _set_Satp64_bits (r_ref : register_ref regstate register_value Satp64) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_bits (v : Satp64) (x : mword 64)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Satp64_Mode (v : Satp64)
+: mword 4 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60.
+
+Definition _set_Satp64_Mode (r_ref : register_ref regstate register_value Satp64) (v : mword 4)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec v 3 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_Mode (v : Satp64) (x : mword 4)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec x 3 0)) ]}.
+
+Definition _get_Satp64_Asid (v : Satp64)
+: mword 16 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44.
+
+Definition _set_Satp64_Asid (r_ref : register_ref regstate register_value Satp64) (v : mword 16)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec v 15 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_Asid (v : Satp64) (x : mword 16)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec x 15 0)) ]}.
+
+Definition _get_Satp64_PPN (v : Satp64)
+: mword 44 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0.
+
+Definition _set_Satp64_PPN (r_ref : register_ref regstate register_value Satp64) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec v 43 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_PPN (v : Satp64) (x : mword 44)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec x 43 0)) ]}.
+
+Definition legalize_satp64 (a : Architecture) (o : mword 64) (v : mword 64)
+: mword 64 :=
+
+ let s := Mk_Satp64 v in
+ match (satp64Mode_of_bits a (_get_Satp64_Mode s)) with
+ | None => o
+ | Some (Sv32) => o
+ | Some (_) => _get_Satp64_bits s
+ end.
+
+Definition Mk_Satp32 (v : mword 32)
+: Satp32 :=
+
+ {| Satp32_Satp32_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Satp32_bits (v : Satp32)
+: mword 32 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 0.
+
+Definition _set_Satp32_bits (r_ref : register_ref regstate register_value Satp32) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_bits (v : Satp32) (x : mword 32)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Satp32_Mode (v : Satp32)
+: mword 1 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 31.
+
+Definition _set_Satp32_Mode (r_ref : register_ref regstate register_value Satp32) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_Mode (v : Satp32) (x : mword 1)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Satp32_Asid (v : Satp32)
+: mword 9 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 30 22.
+
+Definition _set_Satp32_Asid (r_ref : register_ref regstate register_value Satp32) (v : mword 9)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 30 22 (subrange_vec_dec v 8 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_Asid (v : Satp32) (x : mword 9)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 30 22 (subrange_vec_dec x 8 0)) ]}.
+
+Definition _get_Satp32_PPN (v : Satp32)
+: mword 22 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 21 0.
+
+Definition _set_Satp32_PPN (r_ref : register_ref regstate register_value Satp32) (v : mword 22)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 21 0 (subrange_vec_dec v 21 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_PPN (v : Satp32) (x : mword 22)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 21 0 (subrange_vec_dec x 21 0)) ]}.
+
+Definition legalize_satp32 (a : Architecture) (o : mword 32) (v : mword 32) : mword 32 := v.
+
+Definition PmpAddrMatchType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: PmpAddrMatchType :=
+
+ let l__27 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__27 0)) then OFF
+ else if sumbool_of_bool ((Z.eqb l__27 1)) then TOR
+ else if sumbool_of_bool ((Z.eqb l__27 2)) then NA4
+ else NAPOT.
+
+Definition num_of_PmpAddrMatchType (arg_ : PmpAddrMatchType)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | OFF => 0 | TOR => 1 | NA4 => 2 | NAPOT => 3 end).
+
+Definition pmpAddrMatchType_of_bits (bs : mword 2)
+: M (PmpAddrMatchType) :=
+
+ let b__0 := bs in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (OFF : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (TOR : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (NA4 : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then
+ returnm (NAPOT
+ : PmpAddrMatchType)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3" >>= fun _ =>
+ exit tt)
+ : M (PmpAddrMatchType).
+
+Definition pmpAddrMatchType_to_bits (bs : PmpAddrMatchType)
+: mword 2 :=
+
+ match bs with
+ | OFF => (vec_of_bits [B0;B0] : mword 2)
+ | TOR => (vec_of_bits [B0;B1] : mword 2)
+ | NA4 => (vec_of_bits [B1;B0] : mword 2)
+ | NAPOT => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition Mk_Pmpcfg_ent (v : mword 8)
+: Pmpcfg_ent :=
+
+ {| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := (subrange_vec_dec v 7 0) |}.
+
+Definition _get_Pmpcfg_ent_bits (v : Pmpcfg_ent)
+: mword 8 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0.
+
+Definition _set_Pmpcfg_ent_bits
+(r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_bits (v : Pmpcfg_ent) (x : mword 8)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_Pmpcfg_ent_L (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7.
+
+Definition _set_Pmpcfg_ent_L (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_L (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_A (v : Pmpcfg_ent)
+: mword 2 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3.
+
+Definition _set_Pmpcfg_ent_A (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 2)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_A (v : Pmpcfg_ent) (x : mword 2)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Pmpcfg_ent_X (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2.
+
+Definition _set_Pmpcfg_ent_X (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_X (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_W (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1.
+
+Definition _set_Pmpcfg_ent_W (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_W (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_R (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0.
+
+Definition _set_Pmpcfg_ent_R (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_R (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition pmpReadCfgReg (n : Z) `{ArithFact (0 <= n /\ n < 4)}
+: M (mword 32) :=
+
+ let l__23 := n in
+ (if sumbool_of_bool ((Z.eqb l__23 0)) then
+ read_reg pmp3cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ read_reg pmp2cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ read_reg pmp1cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ read_reg pmp0cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__0)
+ (concat_vec (_get_Pmpcfg_ent_bits w__1)
+ (concat_vec (_get_Pmpcfg_ent_bits w__2) (_get_Pmpcfg_ent_bits w__3))))
+ : mword (8 + (8 + (8 + 8))))
+ else if sumbool_of_bool ((Z.eqb l__23 1)) then
+ read_reg pmp7cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ read_reg pmp6cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ read_reg pmp5cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ read_reg pmp4cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__4)
+ (concat_vec (_get_Pmpcfg_ent_bits w__5)
+ (concat_vec (_get_Pmpcfg_ent_bits w__6) (_get_Pmpcfg_ent_bits w__7))))
+ : mword (8 + (8 + (8 + 8))))
+ else if sumbool_of_bool ((Z.eqb l__23 2)) then
+ read_reg pmp11cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ read_reg pmp10cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ read_reg pmp9cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ read_reg pmp8cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__8)
+ (concat_vec (_get_Pmpcfg_ent_bits w__9)
+ (concat_vec (_get_Pmpcfg_ent_bits w__10) (_get_Pmpcfg_ent_bits w__11))))
+ : mword (8 + (8 + (8 + 8))))
+ else if sumbool_of_bool ((Z.eqb l__23 3)) then
+ read_reg pmp15cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ read_reg pmp14cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ read_reg pmp13cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ read_reg pmp12cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__12)
+ (concat_vec (_get_Pmpcfg_ent_bits w__13)
+ (concat_vec (_get_Pmpcfg_ent_bits w__14) (_get_Pmpcfg_ent_bits w__15))))
+ : mword (8 + (8 + (8 + 8))))
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8" >>= fun _ =>
+ exit tt)
+ : M (mword 32).
+
+Definition pmpWriteCfg (cfg : Pmpcfg_ent) (v : mword 8)
+: Pmpcfg_ent :=
+
+ if ((eq_vec (_get_Pmpcfg_ent_L cfg) ((bool_to_bits true) : mword 1))) then cfg
+ else Mk_Pmpcfg_ent v.
+
+Definition pmpWriteCfgReg (n : Z) (v : mword 32) `{ArithFact (0 <= n /\ n < 4)}
+: M (unit) :=
+
+ let l__19 := n in
+ (if sumbool_of_bool ((Z.eqb l__19 0)) then
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ write_reg pmp0cfg_ref (pmpWriteCfg w__0 (subrange_vec_dec v 7 0)) >>
+ read_reg pmp1cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ write_reg pmp1cfg_ref (pmpWriteCfg w__1 (subrange_vec_dec v 15 8)) >>
+ read_reg pmp2cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ write_reg pmp2cfg_ref (pmpWriteCfg w__2 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp3cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ write_reg pmp3cfg_ref (pmpWriteCfg w__3 (subrange_vec_dec v 31 24))
+ : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__19 1)) then
+ read_reg pmp4cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ write_reg pmp4cfg_ref (pmpWriteCfg w__4 (subrange_vec_dec v 7 0)) >>
+ read_reg pmp5cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ write_reg pmp5cfg_ref (pmpWriteCfg w__5 (subrange_vec_dec v 15 8)) >>
+ read_reg pmp6cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ write_reg pmp6cfg_ref (pmpWriteCfg w__6 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp7cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ write_reg pmp7cfg_ref (pmpWriteCfg w__7 (subrange_vec_dec v 31 24))
+ : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__19 2)) then
+ read_reg pmp8cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ let pmp8cfg8 := pmpWriteCfg w__8 (subrange_vec_dec v 7 0) in
+ read_reg pmp9cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ let pmp9cfg9 := pmpWriteCfg w__9 (subrange_vec_dec v 15 8) in
+ read_reg pmp10cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ write_reg pmp10cfg_ref (pmpWriteCfg w__10 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp11cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ write_reg pmp11cfg_ref (pmpWriteCfg w__11 (subrange_vec_dec v 31 24))
+ : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__19 3)) then
+ read_reg pmp12cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ write_reg pmp12cfg_ref (pmpWriteCfg w__12 (subrange_vec_dec v 7 0)) >>
+ read_reg pmp13cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ write_reg pmp13cfg_ref (pmpWriteCfg w__13 (subrange_vec_dec v 15 8)) >>
+ read_reg pmp14cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ write_reg pmp14cfg_ref (pmpWriteCfg w__14 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp15cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ write_reg pmp15cfg_ref (pmpWriteCfg w__15 (subrange_vec_dec v 31 24))
+ : M (unit)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8" >>= fun _ =>
+ exit tt)
+ : M (unit).
+
+Definition pmpWriteAddr (cfg : Pmpcfg_ent) (reg : mword 32) (v : mword 32)
+: mword 32 :=
+
+ if ((eq_vec (_get_Pmpcfg_ent_L cfg) ((bool_to_bits true) : mword 1))) then reg
+ else v.
+
+Definition pmpAddrRange (cfg : Pmpcfg_ent) (pmpaddr : mword 32) (prev_pmpaddr : mword 32)
+: M (option ((mword 32 * mword 32))) :=
+
+ (pmpAddrMatchType_of_bits (_get_Pmpcfg_ent_A cfg)) >>= fun w__0 : PmpAddrMatchType =>
+ returnm ((match w__0 with
+ | OFF => None
+ | TOR => Some ((shiftl prev_pmpaddr 2, shiftl pmpaddr 2))
+ | NA4 =>
+ let lo := shiftl pmpaddr 2 in
+ Some
+ ((lo, add_vec_int lo 4))
+ | NAPOT =>
+ let mask := xor_vec pmpaddr (add_vec_int pmpaddr 1) in
+ let lo := and_vec pmpaddr (not_vec mask) in
+ let len := add_vec_int mask 1 in
+ Some
+ ((shiftl lo 2, shiftl (add_vec lo len) 2))
+ end)
+ : option ((mword 32 * mword 32))).
+
+Definition pmpCheckRWX (ent : Pmpcfg_ent) (acc : AccessType)
+: bool :=
+
+ match acc with
+ | Read => eq_vec (_get_Pmpcfg_ent_R ent) ((bool_to_bits true) : mword 1)
+ | Write => eq_vec (_get_Pmpcfg_ent_W ent) ((bool_to_bits true) : mword 1)
+ | ReadWrite =>
+ andb (eq_vec (_get_Pmpcfg_ent_R ent) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_Pmpcfg_ent_W ent) ((bool_to_bits true) : mword 1))
+ | Execute => eq_vec (_get_Pmpcfg_ent_X ent) ((bool_to_bits true) : mword 1)
+ end.
+
+Definition pmpCheckPerms (ent : Pmpcfg_ent) (acc : AccessType) (priv : Privilege)
+: bool :=
+
+ match priv with
+ | Machine =>
+ if ((eq_vec (_get_Pmpcfg_ent_L ent) ((bool_to_bits true) : mword 1))) then
+ pmpCheckRWX ent acc
+ else true
+ | _ => pmpCheckRWX ent acc
+ end.
+
+Definition pmpAddrMatch_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: pmpAddrMatch :=
+
+ let l__17 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__17 0)) then PMP_NoMatch
+ else if sumbool_of_bool ((Z.eqb l__17 1)) then PMP_PartialMatch
+ else PMP_Match.
+
+Definition num_of_pmpAddrMatch (arg_ : pmpAddrMatch)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | PMP_NoMatch => 0 | PMP_PartialMatch => 1 | PMP_Match => 2 end).
+
+Definition pmpMatchAddr (addr : mword 32) (width : mword 32) (rng : option ((mword 32 * mword 32)))
+: pmpAddrMatch :=
+
+ match rng with
+ | None => PMP_NoMatch
+ | Some ((lo, hi)) =>
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if ((orb (zopz0zI_u (add_vec addr width) lo) (zopz0zI_u hi addr))) then PMP_NoMatch
+ else if ((andb (zopz0zIzJ_u lo addr) (zopz0zIzJ_u (add_vec addr width) hi))) then PMP_Match
+ else PMP_PartialMatch
+ end.
+
+Definition pmpMatch_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: pmpMatch :=
+
+ let l__15 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__15 0)) then PMP_Success
+ else if sumbool_of_bool ((Z.eqb l__15 1)) then PMP_Continue
+ else PMP_Fail.
+
+Definition num_of_pmpMatch (arg_ : pmpMatch)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | PMP_Success => 0 | PMP_Continue => 1 | PMP_Fail => 2 end).
+
+Definition pmpMatchEntry
+(addr : mword 32) (width : mword 32) (acc : AccessType) (priv : Privilege) (ent : Pmpcfg_ent)
+(pmpaddr : mword 32) (prev_pmpaddr : mword 32)
+: M (pmpMatch) :=
+
+ (pmpAddrRange ent pmpaddr prev_pmpaddr) >>= fun rng =>
+ returnm ((match (pmpMatchAddr addr width rng) with
+ | PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc priv)) then PMP_Success else PMP_Fail
+ end)
+ : pmpMatch).
+
+Definition pmpCheck (addr : mword 32) (width : Z) (acc : AccessType) (priv : Privilege)
+`{ArithFact (width > 0)}
+: M (option ExceptionType) :=
+
+ let width : xlenbits := to_bits 32 width in
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ ((read_reg pmpaddr0_ref) : M (mword 32)) >>= fun w__1 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__0 w__1 (zeros_implicit 32)) >>= fun w__2 : pmpMatch =>
+ (match w__2 with
+ | PMP_Success => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp1cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ ((read_reg pmpaddr1_ref) : M (mword 32)) >>= fun w__4 : mword 32 =>
+ ((read_reg pmpaddr0_ref) : M (mword 32)) >>= fun w__5 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__3 w__4 w__5) >>= fun w__6 : pmpMatch =>
+ (match w__6 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp2cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ ((read_reg pmpaddr2_ref) : M (mword 32)) >>= fun w__8 : mword 32 =>
+ ((read_reg pmpaddr1_ref) : M (mword 32)) >>= fun w__9 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__7 w__8 w__9) >>= fun w__10 : pmpMatch =>
+ (match w__10 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp3cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ ((read_reg pmpaddr3_ref) : M (mword 32)) >>= fun w__12 : mword 32 =>
+ ((read_reg pmpaddr2_ref) : M (mword 32)) >>= fun w__13 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__11 w__12 w__13) >>= fun w__14 : pmpMatch =>
+ (match w__14 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp4cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ ((read_reg pmpaddr4_ref) : M (mword 32)) >>= fun w__16 : mword 32 =>
+ ((read_reg pmpaddr3_ref) : M (mword 32)) >>= fun w__17 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__15 w__16 w__17) >>= fun w__18 : pmpMatch =>
+ (match w__18 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp5cfg_ref >>= fun w__19 : Pmpcfg_ent =>
+ ((read_reg pmpaddr5_ref) : M (mword 32)) >>= fun w__20 : mword 32 =>
+ ((read_reg pmpaddr4_ref) : M (mword 32)) >>= fun w__21 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__19 w__20 w__21) >>= fun w__22 : pmpMatch =>
+ (match w__22 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp6cfg_ref >>= fun w__23 : Pmpcfg_ent =>
+ ((read_reg pmpaddr6_ref) : M (mword 32)) >>= fun w__24 : mword 32 =>
+ ((read_reg pmpaddr5_ref) : M (mword 32)) >>= fun w__25 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__23 w__24 w__25) >>= fun w__26 : pmpMatch =>
+ (match w__26 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp7cfg_ref >>= fun w__27 : Pmpcfg_ent =>
+ ((read_reg pmpaddr7_ref) : M (mword 32)) >>= fun w__28 : mword 32 =>
+ ((read_reg pmpaddr6_ref) : M (mword 32)) >>= fun w__29 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__27 w__28 w__29) >>= fun w__30 : pmpMatch =>
+ (match w__30 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp8cfg_ref >>= fun w__31 : Pmpcfg_ent =>
+ ((read_reg pmpaddr8_ref) : M (mword 32)) >>= fun w__32 : mword 32 =>
+ ((read_reg pmpaddr7_ref) : M (mword 32)) >>= fun w__33 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__31 w__32 w__33) >>= fun w__34 : pmpMatch =>
+ (match w__34 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp9cfg_ref >>= fun w__35 : Pmpcfg_ent =>
+ ((read_reg pmpaddr9_ref) : M (mword 32)) >>= fun w__36 : mword 32 =>
+ ((read_reg pmpaddr8_ref) : M (mword 32)) >>= fun w__37 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__35 w__36 w__37) >>= fun w__38 : pmpMatch =>
+ (match w__38 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp10cfg_ref >>= fun w__39 : Pmpcfg_ent =>
+ ((read_reg pmpaddr10_ref) : M (mword 32)) >>= fun w__40 : mword 32 =>
+ ((read_reg pmpaddr9_ref) : M (mword 32)) >>= fun w__41 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__39 w__40 w__41) >>= fun w__42 : pmpMatch =>
+ (match w__42 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp11cfg_ref >>= fun w__43 : Pmpcfg_ent =>
+ ((read_reg pmpaddr11_ref) : M (mword 32)) >>= fun w__44 : mword 32 =>
+ ((read_reg pmpaddr10_ref) : M (mword 32)) >>= fun w__45 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__43 w__44 w__45) >>= fun w__46 : pmpMatch =>
+ (match w__46 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp12cfg_ref >>= fun w__47 : Pmpcfg_ent =>
+ ((read_reg pmpaddr12_ref) : M (mword 32)) >>= fun w__48 : mword 32 =>
+ ((read_reg pmpaddr11_ref) : M (mword 32)) >>= fun w__49 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__47 w__48
+ w__49) >>= fun w__50 : pmpMatch =>
+ (match w__50 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp13cfg_ref >>= fun w__51 : Pmpcfg_ent =>
+ ((read_reg pmpaddr13_ref) : M (mword 32)) >>= fun w__52 : mword 32 =>
+ ((read_reg pmpaddr12_ref) : M (mword 32)) >>= fun w__53 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__51
+ w__52 w__53) >>= fun w__54 : pmpMatch =>
+ (match w__54 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp14cfg_ref >>= fun w__55 : Pmpcfg_ent =>
+ ((read_reg pmpaddr14_ref) : M (mword 32)) >>= fun w__56 : mword 32 =>
+ ((read_reg pmpaddr13_ref) : M (mword 32)) >>= fun w__57 : mword 32 =>
+ (pmpMatchEntry addr width acc priv w__55
+ w__56 w__57) >>= fun w__58 : pmpMatch =>
+ (match w__58 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp15cfg_ref >>= fun w__59 : Pmpcfg_ent =>
+ ((read_reg pmpaddr15_ref)
+ : M (mword 32)) >>= fun w__60 : mword 32 =>
+ ((read_reg pmpaddr14_ref)
+ : M (mword 32)) >>= fun w__61 : mword 32 =>
+ (pmpMatchEntry addr width acc priv
+ w__59 w__60 w__61) >>= fun w__62 : pmpMatch =>
+ returnm ((match w__62 with
+ | PMP_Success => true
+ | PMP_Fail => false
+ | PMP_Continue =>
+ match priv with
+ | Machine => true
+ | _ => false
+ end
+ end)
+ : bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end) >>= fun check' : bool =>
+ returnm ((if sumbool_of_bool (check') then None
+ else
+ match acc with
+ | Read => Some (E_Load_Access_Fault)
+ | Write => Some (E_SAMO_Access_Fault)
+ | ReadWrite => Some (E_SAMO_Access_Fault)
+ | Execute => Some (E_Fetch_Access_Fault)
+ end)
+ : option ExceptionType).
+
+Definition init_pmp '(tt : unit)
+: M (unit) :=
+
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ write_reg pmp0cfg_ref (_update_Pmpcfg_ent_A w__0 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp1cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ write_reg pmp1cfg_ref (_update_Pmpcfg_ent_A w__1 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp2cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ write_reg pmp2cfg_ref (_update_Pmpcfg_ent_A w__2 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp3cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ write_reg pmp3cfg_ref (_update_Pmpcfg_ent_A w__3 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp4cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ write_reg pmp4cfg_ref (_update_Pmpcfg_ent_A w__4 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp5cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ write_reg pmp5cfg_ref (_update_Pmpcfg_ent_A w__5 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp6cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ write_reg pmp6cfg_ref (_update_Pmpcfg_ent_A w__6 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp7cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ write_reg pmp7cfg_ref (_update_Pmpcfg_ent_A w__7 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp8cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ write_reg pmp8cfg_ref (_update_Pmpcfg_ent_A w__8 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp9cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ write_reg pmp9cfg_ref (_update_Pmpcfg_ent_A w__9 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp10cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ write_reg pmp10cfg_ref (_update_Pmpcfg_ent_A w__10 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp11cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ write_reg pmp11cfg_ref (_update_Pmpcfg_ent_A w__11 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp12cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ write_reg pmp12cfg_ref (_update_Pmpcfg_ent_A w__12 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp13cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ write_reg pmp13cfg_ref (_update_Pmpcfg_ent_A w__13 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp14cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ write_reg pmp14cfg_ref (_update_Pmpcfg_ent_A w__14 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp15cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ write_reg pmp15cfg_ref (_update_Pmpcfg_ent_A w__15 (pmpAddrMatchType_to_bits OFF))
+ : M (unit).
+
+Definition ext_init_regs '(tt : unit) : M (unit) := returnm (tt : unit).
+
+Definition ext_rvfi_init '(tt : unit) : M (unit) := returnm (tt : unit).
+
+Definition ext_fetch_check_pc (start_pc : mword 32) (pc : mword 32)
+: Ext_FetchAddr_Check unit :=
+
+ Ext_FetchAddr_OK
+ (pc).
+
+Definition ext_handle_fetch_check_error (err : unit) : unit := tt.
+
+Definition ext_control_check_addr (pc : mword 32)
+: Ext_ControlAddr_Check unit :=
+
+ Ext_ControlAddr_OK
+ (pc).
+
+Definition ext_control_check_pc (pc : mword 32)
+: Ext_ControlAddr_Check unit :=
+
+ Ext_ControlAddr_OK
+ (pc).
+
+Definition ext_handle_control_check_error (err : unit) : unit := tt.
+
+Definition ext_data_get_addr
+(base : mword 5) (offset : mword 32) (acc : AccessType) (width : word_width)
+: M (Ext_DataAddr_Check unit) :=
+
+ (rX (projT1 (regidx_to_regno base))) >>= fun w__0 : mword 32 =>
+ let addr := add_vec w__0 offset in
+ returnm ((Ext_DataAddr_OK
+ (addr))
+ : Ext_DataAddr_Check unit).
+
+Definition ext_handle_data_check_error (err : unit) : unit := tt.
+
+Definition csr_name (csr : mword 12)
+: string :=
+
+ let b__0 := csr in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "uie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "utvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "uscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "uepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "ucause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "utval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "uip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "fflags"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "frm"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "fcsr"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "cycle"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "time"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "instret"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "cycleh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "timeh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "instreth"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "sstatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "sedeleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "sideleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "sie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "stvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ "scounteren"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "sscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "sepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "scause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "stval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "sip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "satp"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ "mvendorid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ "marchid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ "mimpid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ "mhartid"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mstatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "misa"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "medeleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "mideleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "mie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "mtvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ "mcounteren"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "mepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "mcause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "mtval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "mip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ "pmpcfg0"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ "pmpaddr0"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mcycle"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "minstret"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mcycleh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "minstreth"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ "tselect"
+ else "UNKNOWN".
+
+Definition csr_name_map_forwards (arg_ : mword 12)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("ustatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("uie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("utvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("uscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("uepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("ucause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("utval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("uip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("fflags"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("frm"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("fcsr"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("cycle"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("time"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("instret"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("cycleh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("timeh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("instreth"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("sstatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("sedeleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("sideleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("sie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("stvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ("scounteren"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("sscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("sepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("scause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("stval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("sip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("satp"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ("mvendorid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ("marchid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mimpid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mhartid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mstatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("misa"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("medeleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mideleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("mtvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ("mcounteren"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("mepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("mcause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mtval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("pmpcfg0"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("pmpcfg1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("pmpcfg2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("pmpcfg3"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ returnm ("pmpaddr0"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ("pmpaddr1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ("pmpaddr2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ("pmpaddr3"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ("pmpaddr4"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ returnm ("pmpaddr5"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ returnm ("pmpaddr6"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ returnm ("pmpaddr7"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ returnm ("pmpaddr8"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ returnm ("pmpaddr9"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ returnm ("pmpaddr10"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ returnm ("pmpaddr11"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ returnm ("pmpaddr12"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ returnm ("pmpaddr13"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ returnm ("pmpaddr14"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ returnm ("pmpaddr15"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mcycle"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("minstret"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mcycleh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("minstreth"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("tselect"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("tdata1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("tdata2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("tdata3"
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition csr_name_map_backwards (arg_ : string)
+: M (mword 12) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "ustatus")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uie")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "utvec")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uscratch")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uepc")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "ucause")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "utval")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uip")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "fflags")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "frm")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "fcsr")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "cycle")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "time")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "instret")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "cycleh")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "timeh")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "instreth")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sstatus")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sedeleg")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sideleg")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sie")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "stvec")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "scounteren")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sscratch")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sepc")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "scause")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "stval")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sip")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "satp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mvendorid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "marchid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mimpid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mhartid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mstatus")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "misa")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "medeleg")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mideleg")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mie")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mtvec")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcounteren")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mscratch")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mepc")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcause")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mtval")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mip")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg3")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr3")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr4")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr5")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr6")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr7")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr8")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr9")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr10")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr11")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr12")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr13")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr14")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr15")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcycle")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "minstret")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcycleh")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "minstreth")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tselect")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata1")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata2")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata3")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 12).
+
+Definition csr_name_map_forwards_matches (arg_ : mword 12)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true
+ else false.
+
+Definition csr_name_map_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "ustatus")) then true
+ else if ((generic_eq p0_ "uie")) then true
+ else if ((generic_eq p0_ "utvec")) then true
+ else if ((generic_eq p0_ "uscratch")) then true
+ else if ((generic_eq p0_ "uepc")) then true
+ else if ((generic_eq p0_ "ucause")) then true
+ else if ((generic_eq p0_ "utval")) then true
+ else if ((generic_eq p0_ "uip")) then true
+ else if ((generic_eq p0_ "fflags")) then true
+ else if ((generic_eq p0_ "frm")) then true
+ else if ((generic_eq p0_ "fcsr")) then true
+ else if ((generic_eq p0_ "cycle")) then true
+ else if ((generic_eq p0_ "time")) then true
+ else if ((generic_eq p0_ "instret")) then true
+ else if ((generic_eq p0_ "cycleh")) then true
+ else if ((generic_eq p0_ "timeh")) then true
+ else if ((generic_eq p0_ "instreth")) then true
+ else if ((generic_eq p0_ "sstatus")) then true
+ else if ((generic_eq p0_ "sedeleg")) then true
+ else if ((generic_eq p0_ "sideleg")) then true
+ else if ((generic_eq p0_ "sie")) then true
+ else if ((generic_eq p0_ "stvec")) then true
+ else if ((generic_eq p0_ "scounteren")) then true
+ else if ((generic_eq p0_ "sscratch")) then true
+ else if ((generic_eq p0_ "sepc")) then true
+ else if ((generic_eq p0_ "scause")) then true
+ else if ((generic_eq p0_ "stval")) then true
+ else if ((generic_eq p0_ "sip")) then true
+ else if ((generic_eq p0_ "satp")) then true
+ else if ((generic_eq p0_ "mvendorid")) then true
+ else if ((generic_eq p0_ "marchid")) then true
+ else if ((generic_eq p0_ "mimpid")) then true
+ else if ((generic_eq p0_ "mhartid")) then true
+ else if ((generic_eq p0_ "mstatus")) then true
+ else if ((generic_eq p0_ "misa")) then true
+ else if ((generic_eq p0_ "medeleg")) then true
+ else if ((generic_eq p0_ "mideleg")) then true
+ else if ((generic_eq p0_ "mie")) then true
+ else if ((generic_eq p0_ "mtvec")) then true
+ else if ((generic_eq p0_ "mcounteren")) then true
+ else if ((generic_eq p0_ "mscratch")) then true
+ else if ((generic_eq p0_ "mepc")) then true
+ else if ((generic_eq p0_ "mcause")) then true
+ else if ((generic_eq p0_ "mtval")) then true
+ else if ((generic_eq p0_ "mip")) then true
+ else if ((generic_eq p0_ "pmpcfg0")) then true
+ else if ((generic_eq p0_ "pmpcfg1")) then true
+ else if ((generic_eq p0_ "pmpcfg2")) then true
+ else if ((generic_eq p0_ "pmpcfg3")) then true
+ else if ((generic_eq p0_ "pmpaddr0")) then true
+ else if ((generic_eq p0_ "pmpaddr1")) then true
+ else if ((generic_eq p0_ "pmpaddr2")) then true
+ else if ((generic_eq p0_ "pmpaddr3")) then true
+ else if ((generic_eq p0_ "pmpaddr4")) then true
+ else if ((generic_eq p0_ "pmpaddr5")) then true
+ else if ((generic_eq p0_ "pmpaddr6")) then true
+ else if ((generic_eq p0_ "pmpaddr7")) then true
+ else if ((generic_eq p0_ "pmpaddr8")) then true
+ else if ((generic_eq p0_ "pmpaddr9")) then true
+ else if ((generic_eq p0_ "pmpaddr10")) then true
+ else if ((generic_eq p0_ "pmpaddr11")) then true
+ else if ((generic_eq p0_ "pmpaddr12")) then true
+ else if ((generic_eq p0_ "pmpaddr13")) then true
+ else if ((generic_eq p0_ "pmpaddr14")) then true
+ else if ((generic_eq p0_ "pmpaddr15")) then true
+ else if ((generic_eq p0_ "mcycle")) then true
+ else if ((generic_eq p0_ "minstret")) then true
+ else if ((generic_eq p0_ "mcycleh")) then true
+ else if ((generic_eq p0_ "minstreth")) then true
+ else if ((generic_eq p0_ "tselect")) then true
+ else if ((generic_eq p0_ "tdata1")) then true
+ else if ((generic_eq p0_ "tdata2")) then true
+ else if ((generic_eq p0_ "tdata3")) then true
+ else false.
+
+Definition _s488_ (_s489_ : string)
+: option string :=
+
+ let _s490_ := _s489_ in
+ if ((string_startswith _s490_ "tdata3")) then
+ match (string_drop _s490_ (projT1 (string_length "tdata3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s484_ (_s485_ : string)
+: option string :=
+
+ let _s486_ := _s485_ in
+ if ((string_startswith _s486_ "tdata2")) then
+ match (string_drop _s486_ (projT1 (string_length "tdata2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s480_ (_s481_ : string)
+: option string :=
+
+ let _s482_ := _s481_ in
+ if ((string_startswith _s482_ "tdata1")) then
+ match (string_drop _s482_ (projT1 (string_length "tdata1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s476_ (_s477_ : string)
+: option string :=
+
+ let _s478_ := _s477_ in
+ if ((string_startswith _s478_ "tselect")) then
+ match (string_drop _s478_ (projT1 (string_length "tselect"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s472_ (_s473_ : string)
+: option string :=
+
+ let _s474_ := _s473_ in
+ if ((string_startswith _s474_ "minstreth")) then
+ match (string_drop _s474_ (projT1 (string_length "minstreth"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s468_ (_s469_ : string)
+: option string :=
+
+ let _s470_ := _s469_ in
+ if ((string_startswith _s470_ "mcycleh")) then
+ match (string_drop _s470_ (projT1 (string_length "mcycleh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s464_ (_s465_ : string)
+: option string :=
+
+ let _s466_ := _s465_ in
+ if ((string_startswith _s466_ "minstret")) then
+ match (string_drop _s466_ (projT1 (string_length "minstret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s460_ (_s461_ : string)
+: option string :=
+
+ let _s462_ := _s461_ in
+ if ((string_startswith _s462_ "mcycle")) then
+ match (string_drop _s462_ (projT1 (string_length "mcycle"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s456_ (_s457_ : string)
+: option string :=
+
+ let _s458_ := _s457_ in
+ if ((string_startswith _s458_ "pmpaddr15")) then
+ match (string_drop _s458_ (projT1 (string_length "pmpaddr15"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s452_ (_s453_ : string)
+: option string :=
+
+ let _s454_ := _s453_ in
+ if ((string_startswith _s454_ "pmpaddr14")) then
+ match (string_drop _s454_ (projT1 (string_length "pmpaddr14"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s448_ (_s449_ : string)
+: option string :=
+
+ let _s450_ := _s449_ in
+ if ((string_startswith _s450_ "pmpaddr13")) then
+ match (string_drop _s450_ (projT1 (string_length "pmpaddr13"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s444_ (_s445_ : string)
+: option string :=
+
+ let _s446_ := _s445_ in
+ if ((string_startswith _s446_ "pmpaddr12")) then
+ match (string_drop _s446_ (projT1 (string_length "pmpaddr12"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s440_ (_s441_ : string)
+: option string :=
+
+ let _s442_ := _s441_ in
+ if ((string_startswith _s442_ "pmpaddr11")) then
+ match (string_drop _s442_ (projT1 (string_length "pmpaddr11"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s436_ (_s437_ : string)
+: option string :=
+
+ let _s438_ := _s437_ in
+ if ((string_startswith _s438_ "pmpaddr10")) then
+ match (string_drop _s438_ (projT1 (string_length "pmpaddr10"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s432_ (_s433_ : string)
+: option string :=
+
+ let _s434_ := _s433_ in
+ if ((string_startswith _s434_ "pmpaddr9")) then
+ match (string_drop _s434_ (projT1 (string_length "pmpaddr9"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s428_ (_s429_ : string)
+: option string :=
+
+ let _s430_ := _s429_ in
+ if ((string_startswith _s430_ "pmpaddr8")) then
+ match (string_drop _s430_ (projT1 (string_length "pmpaddr8"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s424_ (_s425_ : string)
+: option string :=
+
+ let _s426_ := _s425_ in
+ if ((string_startswith _s426_ "pmpaddr7")) then
+ match (string_drop _s426_ (projT1 (string_length "pmpaddr7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s420_ (_s421_ : string)
+: option string :=
+
+ let _s422_ := _s421_ in
+ if ((string_startswith _s422_ "pmpaddr6")) then
+ match (string_drop _s422_ (projT1 (string_length "pmpaddr6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s416_ (_s417_ : string)
+: option string :=
+
+ let _s418_ := _s417_ in
+ if ((string_startswith _s418_ "pmpaddr5")) then
+ match (string_drop _s418_ (projT1 (string_length "pmpaddr5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s412_ (_s413_ : string)
+: option string :=
+
+ let _s414_ := _s413_ in
+ if ((string_startswith _s414_ "pmpaddr4")) then
+ match (string_drop _s414_ (projT1 (string_length "pmpaddr4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s408_ (_s409_ : string)
+: option string :=
+
+ let _s410_ := _s409_ in
+ if ((string_startswith _s410_ "pmpaddr3")) then
+ match (string_drop _s410_ (projT1 (string_length "pmpaddr3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s404_ (_s405_ : string)
+: option string :=
+
+ let _s406_ := _s405_ in
+ if ((string_startswith _s406_ "pmpaddr2")) then
+ match (string_drop _s406_ (projT1 (string_length "pmpaddr2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s400_ (_s401_ : string)
+: option string :=
+
+ let _s402_ := _s401_ in
+ if ((string_startswith _s402_ "pmpaddr1")) then
+ match (string_drop _s402_ (projT1 (string_length "pmpaddr1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s396_ (_s397_ : string)
+: option string :=
+
+ let _s398_ := _s397_ in
+ if ((string_startswith _s398_ "pmpaddr0")) then
+ match (string_drop _s398_ (projT1 (string_length "pmpaddr0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s392_ (_s393_ : string)
+: option string :=
+
+ let _s394_ := _s393_ in
+ if ((string_startswith _s394_ "pmpcfg3")) then
+ match (string_drop _s394_ (projT1 (string_length "pmpcfg3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s388_ (_s389_ : string)
+: option string :=
+
+ let _s390_ := _s389_ in
+ if ((string_startswith _s390_ "pmpcfg2")) then
+ match (string_drop _s390_ (projT1 (string_length "pmpcfg2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s384_ (_s385_ : string)
+: option string :=
+
+ let _s386_ := _s385_ in
+ if ((string_startswith _s386_ "pmpcfg1")) then
+ match (string_drop _s386_ (projT1 (string_length "pmpcfg1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s380_ (_s381_ : string)
+: option string :=
+
+ let _s382_ := _s381_ in
+ if ((string_startswith _s382_ "pmpcfg0")) then
+ match (string_drop _s382_ (projT1 (string_length "pmpcfg0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s376_ (_s377_ : string)
+: option string :=
+
+ let _s378_ := _s377_ in
+ if ((string_startswith _s378_ "mip")) then
+ match (string_drop _s378_ (projT1 (string_length "mip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s372_ (_s373_ : string)
+: option string :=
+
+ let _s374_ := _s373_ in
+ if ((string_startswith _s374_ "mtval")) then
+ match (string_drop _s374_ (projT1 (string_length "mtval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s368_ (_s369_ : string)
+: option string :=
+
+ let _s370_ := _s369_ in
+ if ((string_startswith _s370_ "mcause")) then
+ match (string_drop _s370_ (projT1 (string_length "mcause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s364_ (_s365_ : string)
+: option string :=
+
+ let _s366_ := _s365_ in
+ if ((string_startswith _s366_ "mepc")) then
+ match (string_drop _s366_ (projT1 (string_length "mepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s360_ (_s361_ : string)
+: option string :=
+
+ let _s362_ := _s361_ in
+ if ((string_startswith _s362_ "mscratch")) then
+ match (string_drop _s362_ (projT1 (string_length "mscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s356_ (_s357_ : string)
+: option string :=
+
+ let _s358_ := _s357_ in
+ if ((string_startswith _s358_ "mcounteren")) then
+ match (string_drop _s358_ (projT1 (string_length "mcounteren"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s352_ (_s353_ : string)
+: option string :=
+
+ let _s354_ := _s353_ in
+ if ((string_startswith _s354_ "mtvec")) then
+ match (string_drop _s354_ (projT1 (string_length "mtvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s348_ (_s349_ : string)
+: option string :=
+
+ let _s350_ := _s349_ in
+ if ((string_startswith _s350_ "mie")) then
+ match (string_drop _s350_ (projT1 (string_length "mie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s344_ (_s345_ : string)
+: option string :=
+
+ let _s346_ := _s345_ in
+ if ((string_startswith _s346_ "mideleg")) then
+ match (string_drop _s346_ (projT1 (string_length "mideleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s340_ (_s341_ : string)
+: option string :=
+
+ let _s342_ := _s341_ in
+ if ((string_startswith _s342_ "medeleg")) then
+ match (string_drop _s342_ (projT1 (string_length "medeleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s336_ (_s337_ : string)
+: option string :=
+
+ let _s338_ := _s337_ in
+ if ((string_startswith _s338_ "misa")) then
+ match (string_drop _s338_ (projT1 (string_length "misa"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s332_ (_s333_ : string)
+: option string :=
+
+ let _s334_ := _s333_ in
+ if ((string_startswith _s334_ "mstatus")) then
+ match (string_drop _s334_ (projT1 (string_length "mstatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s328_ (_s329_ : string)
+: option string :=
+
+ let _s330_ := _s329_ in
+ if ((string_startswith _s330_ "mhartid")) then
+ match (string_drop _s330_ (projT1 (string_length "mhartid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s324_ (_s325_ : string)
+: option string :=
+
+ let _s326_ := _s325_ in
+ if ((string_startswith _s326_ "mimpid")) then
+ match (string_drop _s326_ (projT1 (string_length "mimpid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s320_ (_s321_ : string)
+: option string :=
+
+ let _s322_ := _s321_ in
+ if ((string_startswith _s322_ "marchid")) then
+ match (string_drop _s322_ (projT1 (string_length "marchid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s316_ (_s317_ : string)
+: option string :=
+
+ let _s318_ := _s317_ in
+ if ((string_startswith _s318_ "mvendorid")) then
+ match (string_drop _s318_ (projT1 (string_length "mvendorid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s312_ (_s313_ : string)
+: option string :=
+
+ let _s314_ := _s313_ in
+ if ((string_startswith _s314_ "satp")) then
+ match (string_drop _s314_ (projT1 (string_length "satp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s308_ (_s309_ : string)
+: option string :=
+
+ let _s310_ := _s309_ in
+ if ((string_startswith _s310_ "sip")) then
+ match (string_drop _s310_ (projT1 (string_length "sip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s304_ (_s305_ : string)
+: option string :=
+
+ let _s306_ := _s305_ in
+ if ((string_startswith _s306_ "stval")) then
+ match (string_drop _s306_ (projT1 (string_length "stval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s300_ (_s301_ : string)
+: option string :=
+
+ let _s302_ := _s301_ in
+ if ((string_startswith _s302_ "scause")) then
+ match (string_drop _s302_ (projT1 (string_length "scause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s296_ (_s297_ : string)
+: option string :=
+
+ let _s298_ := _s297_ in
+ if ((string_startswith _s298_ "sepc")) then
+ match (string_drop _s298_ (projT1 (string_length "sepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s292_ (_s293_ : string)
+: option string :=
+
+ let _s294_ := _s293_ in
+ if ((string_startswith _s294_ "sscratch")) then
+ match (string_drop _s294_ (projT1 (string_length "sscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s288_ (_s289_ : string)
+: option string :=
+
+ let _s290_ := _s289_ in
+ if ((string_startswith _s290_ "scounteren")) then
+ match (string_drop _s290_ (projT1 (string_length "scounteren"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s284_ (_s285_ : string)
+: option string :=
+
+ let _s286_ := _s285_ in
+ if ((string_startswith _s286_ "stvec")) then
+ match (string_drop _s286_ (projT1 (string_length "stvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s280_ (_s281_ : string)
+: option string :=
+
+ let _s282_ := _s281_ in
+ if ((string_startswith _s282_ "sie")) then
+ match (string_drop _s282_ (projT1 (string_length "sie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s276_ (_s277_ : string)
+: option string :=
+
+ let _s278_ := _s277_ in
+ if ((string_startswith _s278_ "sideleg")) then
+ match (string_drop _s278_ (projT1 (string_length "sideleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s272_ (_s273_ : string)
+: option string :=
+
+ let _s274_ := _s273_ in
+ if ((string_startswith _s274_ "sedeleg")) then
+ match (string_drop _s274_ (projT1 (string_length "sedeleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s268_ (_s269_ : string)
+: option string :=
+
+ let _s270_ := _s269_ in
+ if ((string_startswith _s270_ "sstatus")) then
+ match (string_drop _s270_ (projT1 (string_length "sstatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s264_ (_s265_ : string)
+: option string :=
+
+ let _s266_ := _s265_ in
+ if ((string_startswith _s266_ "instreth")) then
+ match (string_drop _s266_ (projT1 (string_length "instreth"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s260_ (_s261_ : string)
+: option string :=
+
+ let _s262_ := _s261_ in
+ if ((string_startswith _s262_ "timeh")) then
+ match (string_drop _s262_ (projT1 (string_length "timeh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s256_ (_s257_ : string)
+: option string :=
+
+ let _s258_ := _s257_ in
+ if ((string_startswith _s258_ "cycleh")) then
+ match (string_drop _s258_ (projT1 (string_length "cycleh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s252_ (_s253_ : string)
+: option string :=
+
+ let _s254_ := _s253_ in
+ if ((string_startswith _s254_ "instret")) then
+ match (string_drop _s254_ (projT1 (string_length "instret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s248_ (_s249_ : string)
+: option string :=
+
+ let _s250_ := _s249_ in
+ if ((string_startswith _s250_ "time")) then
+ match (string_drop _s250_ (projT1 (string_length "time"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s244_ (_s245_ : string)
+: option string :=
+
+ let _s246_ := _s245_ in
+ if ((string_startswith _s246_ "cycle")) then
+ match (string_drop _s246_ (projT1 (string_length "cycle"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s240_ (_s241_ : string)
+: option string :=
+
+ let _s242_ := _s241_ in
+ if ((string_startswith _s242_ "fcsr")) then
+ match (string_drop _s242_ (projT1 (string_length "fcsr"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s236_ (_s237_ : string)
+: option string :=
+
+ let _s238_ := _s237_ in
+ if ((string_startswith _s238_ "frm")) then
+ match (string_drop _s238_ (projT1 (string_length "frm"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s232_ (_s233_ : string)
+: option string :=
+
+ let _s234_ := _s233_ in
+ if ((string_startswith _s234_ "fflags")) then
+ match (string_drop _s234_ (projT1 (string_length "fflags"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s228_ (_s229_ : string)
+: option string :=
+
+ let _s230_ := _s229_ in
+ if ((string_startswith _s230_ "uip")) then
+ match (string_drop _s230_ (projT1 (string_length "uip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s224_ (_s225_ : string)
+: option string :=
+
+ let _s226_ := _s225_ in
+ if ((string_startswith _s226_ "utval")) then
+ match (string_drop _s226_ (projT1 (string_length "utval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s220_ (_s221_ : string)
+: option string :=
+
+ let _s222_ := _s221_ in
+ if ((string_startswith _s222_ "ucause")) then
+ match (string_drop _s222_ (projT1 (string_length "ucause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s216_ (_s217_ : string)
+: option string :=
+
+ let _s218_ := _s217_ in
+ if ((string_startswith _s218_ "uepc")) then
+ match (string_drop _s218_ (projT1 (string_length "uepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s212_ (_s213_ : string)
+: option string :=
+
+ let _s214_ := _s213_ in
+ if ((string_startswith _s214_ "uscratch")) then
+ match (string_drop _s214_ (projT1 (string_length "uscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s208_ (_s209_ : string)
+: option string :=
+
+ let _s210_ := _s209_ in
+ if ((string_startswith _s210_ "utvec")) then
+ match (string_drop _s210_ (projT1 (string_length "utvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s204_ (_s205_ : string)
+: option string :=
+
+ let _s206_ := _s205_ in
+ if ((string_startswith _s206_ "uie")) then
+ match (string_drop _s206_ (projT1 (string_length "uie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s200_ (_s201_ : string)
+: option string :=
+
+ let _s202_ := _s201_ in
+ if ((string_startswith _s202_ "ustatus")) then
+ match (string_drop _s202_ (projT1 (string_length "ustatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition csr_name_map_matches_prefix (arg_ : string)
+: M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s203_ := arg_ in
+ (if ((match (_s200_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s200_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s204_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s204_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s208_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s208_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s212_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s212_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s216_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s216_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s220_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s220_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s224_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s224_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s228_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s228_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s232_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s232_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s236_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s236_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s240_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s240_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s244_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s244_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s248_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s248_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s252_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s252_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s256_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s256_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s260_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s260_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s264_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s264_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s268_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s268_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s272_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s272_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s276_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s276_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s280_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s280_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s284_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s284_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s288_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s288_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s292_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s292_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s296_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s296_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s300_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s300_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s304_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s304_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s308_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s308_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s312_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s312_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s316_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s316_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s320_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s320_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s324_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s324_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s328_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s328_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s332_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s332_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s336_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s336_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s340_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s340_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s344_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s344_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s348_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s348_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s352_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s352_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s356_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s356_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s360_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s360_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s364_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s364_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s368_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s368_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s372_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s372_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s376_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s376_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s380_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s380_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s384_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s384_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s388_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s388_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s392_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s392_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s396_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s396_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s400_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s400_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s404_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s404_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s408_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s408_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s412_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s412_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s416_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s416_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s420_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s420_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s424_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s424_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s428_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s428_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s432_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s432_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s436_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s436_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s440_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s440_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s444_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s444_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s448_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s448_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s452_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s452_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s456_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s456_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s460_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s460_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s464_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s464_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s468_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s468_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s472_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s472_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s476_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s476_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s480_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s480_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s484_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s484_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s488_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s488_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition Mk_Ustatus (v : mword 32)
+: Ustatus :=
+
+ {| Ustatus_Ustatus_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Ustatus_bits (v : Ustatus)
+: mword 32 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 31 0.
+
+Definition _set_Ustatus_bits (r_ref : register_ref regstate register_value Ustatus) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_bits (v : Ustatus) (x : mword 32)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Ustatus_UPIE (v : Ustatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 4 4.
+
+Definition _set_Ustatus_UPIE (r_ref : register_ref regstate register_value Ustatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_UPIE (v : Ustatus) (x : mword 1)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Ustatus_UIE (v : Ustatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 0 0.
+
+Definition _set_Ustatus_UIE (r_ref : register_ref regstate register_value Ustatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_UIE (v : Ustatus) (x : mword 1)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_sstatus (s : Sstatus)
+: Ustatus :=
+
+ let u := Mk_Ustatus (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Ustatus_UPIE u (_get_Sstatus_UPIE s) in
+ _update_Ustatus_UIE u (_get_Sstatus_UIE s).
+
+Definition lift_ustatus (s : Sstatus) (u : Ustatus)
+: Sstatus :=
+
+ let s := _update_Sstatus_UPIE s (_get_Ustatus_UPIE u) in
+ _update_Sstatus_UIE s (_get_Ustatus_UIE u).
+
+Definition legalize_ustatus (m : Mstatus) (v : mword 32)
+: M (Mstatus) :=
+
+ let u := Mk_Ustatus v in
+ let s := lower_mstatus m in
+ let s := lift_ustatus s u in
+ (lift_sstatus m s)
+ : M (Mstatus).
+
+Definition Mk_Uinterrupts (v : mword 32)
+: Uinterrupts :=
+
+ {| Uinterrupts_Uinterrupts_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Uinterrupts_bits (v : Uinterrupts)
+: mword 32 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 31 0.
+
+Definition _set_Uinterrupts_bits
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_bits (v : Uinterrupts) (x : mword 32)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Uinterrupts_UEI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 8 8.
+
+Definition _set_Uinterrupts_UEI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_UEI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Uinterrupts_UTI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 4 4.
+
+Definition _set_Uinterrupts_UTI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_UTI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Uinterrupts_USI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 0 0.
+
+Definition _set_Uinterrupts_USI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_USI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_sip (s : Sinterrupts) (d : Sinterrupts)
+: Uinterrupts :=
+
+ let u : Uinterrupts := Mk_Uinterrupts (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Uinterrupts_UEI u (and_vec (_get_Sinterrupts_UEI s) (_get_Sinterrupts_UEI d)) in
+ let u := _update_Uinterrupts_UTI u (and_vec (_get_Sinterrupts_UTI s) (_get_Sinterrupts_UTI d)) in
+ _update_Uinterrupts_USI u (and_vec (_get_Sinterrupts_USI s) (_get_Sinterrupts_USI d)).
+
+Definition lower_sie (s : Sinterrupts) (d : Sinterrupts)
+: Uinterrupts :=
+
+ let u : Uinterrupts := Mk_Uinterrupts (EXTZ 32 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Uinterrupts_UEI u (and_vec (_get_Sinterrupts_UEI s) (_get_Sinterrupts_UEI d)) in
+ let u := _update_Uinterrupts_UTI u (and_vec (_get_Sinterrupts_UTI s) (_get_Sinterrupts_UTI d)) in
+ _update_Uinterrupts_USI u (and_vec (_get_Sinterrupts_USI s) (_get_Sinterrupts_USI d)).
+
+Definition lift_uip (o : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := o in
+ if ((eq_vec (_get_Sinterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_USI s (_get_Uinterrupts_USI u)
+ else s.
+
+Definition legalize_uip (s : Sinterrupts) (d : Sinterrupts) (v : mword 32)
+: Sinterrupts :=
+
+ lift_uip s d (Mk_Uinterrupts v).
+
+Definition lift_uie (o : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := o in
+ let s :=
+ if ((eq_vec (_get_Sinterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_UEI s (_get_Uinterrupts_UEI u)
+ else s in
+ let s :=
+ if ((eq_vec (_get_Sinterrupts_UTI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_UTI s (_get_Uinterrupts_UTI u)
+ else s in
+ if ((eq_vec (_get_Sinterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_USI s (_get_Uinterrupts_USI u)
+ else s.
+
+Definition legalize_uie (s : Sinterrupts) (d : Sinterrupts) (v : mword 32)
+: Sinterrupts :=
+
+ lift_uie s d (Mk_Uinterrupts v).
+
+Definition handle_trap_extension (p : Privilege) (pc : mword 32) (u : option unit) : unit := tt.
+
+Definition prepare_trap_vector (p : Privilege) (cause : Mcause)
+: M (mword 32) :=
+
+ (match p with
+ | Machine => read_reg mtvec_ref : M (Mtvec)
+ | Supervisor => read_reg stvec_ref : M (Mtvec)
+ | User => read_reg utvec_ref : M (Mtvec)
+ end) >>= fun tvec : Mtvec =>
+ (match (tvec_addr tvec cause) with
+ | Some (epc) => returnm (epc : mword 32)
+ | None => (internal_error "Invalid tvec mode") : M (mword 32)
+ end)
+ : M (mword 32).
+
+Definition get_xret_target (p : Privilege)
+: M (mword 32) :=
+
+ (match p with
+ | Machine => ((read_reg mepc_ref) : M (mword 32)) : M (mword 32)
+ | Supervisor => ((read_reg sepc_ref) : M (mword 32)) : M (mword 32)
+ | User => ((read_reg uepc_ref) : M (mword 32)) : M (mword 32)
+ end)
+ : M (mword 32).
+
+Definition set_xret_target (p : Privilege) (value : mword 32)
+: M (mword 32) :=
+
+ (legalize_xepc value) >>= fun target =>
+ (match p with
+ | Machine => write_reg mepc_ref target : M (unit)
+ | Supervisor => write_reg sepc_ref target : M (unit)
+ | User => write_reg uepc_ref target : M (unit)
+ end) >>
+ returnm (target
+ : mword 32).
+
+Definition prepare_xret_target (p : Privilege)
+: M (mword 32) :=
+
+ (get_xret_target p)
+ : M (mword 32).
+
+Definition get_mtvec '(tt : unit)
+: M (mword 32) :=
+
+ read_reg mtvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 32).
+
+Definition get_stvec '(tt : unit)
+: M (mword 32) :=
+
+ read_reg stvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 32).
+
+Definition get_utvec '(tt : unit)
+: M (mword 32) :=
+
+ read_reg utvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 32).
+
+Definition set_mtvec (value : mword 32)
+: M (mword 32) :=
+
+ read_reg mtvec_ref >>= fun w__0 : Mtvec =>
+ write_reg mtvec_ref (legalize_tvec w__0 value) >>
+ read_reg mtvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 32).
+
+Definition set_stvec (value : mword 32)
+: M (mword 32) :=
+
+ read_reg stvec_ref >>= fun w__0 : Mtvec =>
+ write_reg stvec_ref (legalize_tvec w__0 value) >>
+ read_reg stvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 32).
+
+Definition set_utvec (value : mword 32)
+: M (mword 32) :=
+
+ read_reg utvec_ref >>= fun w__0 : Mtvec =>
+ write_reg utvec_ref (legalize_tvec w__0 value) >>
+ read_reg utvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 32).
+
+Definition is_NExt_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition read_NExt_CSR (csr : mword 12)
+: M (option (mword 32)) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ returnm ((Some
+ (_get_Ustatus_bits (lower_sstatus (lower_mstatus w__0))))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__1 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__2 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__3 : Sinterrupts =>
+ returnm ((Some
+ (_get_Uinterrupts_bits (lower_sie (lower_mie w__1 w__2) w__3)))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_utvec tt) >>= fun w__4 : mword 32 => returnm ((Some (w__4)) : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg uscratch_ref) : M (mword 32)) >>= fun w__5 : mword 32 =>
+ returnm ((Some
+ (w__5))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target User) >>= fun w__6 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__7 : mword 32 =>
+ returnm ((Some
+ (and_vec w__6 w__7))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg ucause_ref >>= fun w__8 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__8))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg utval_ref) : M (mword 32)) >>= fun w__9 : mword 32 =>
+ returnm ((Some
+ (w__9))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__10 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__11 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__12 : Sinterrupts =>
+ returnm ((Some
+ (_get_Uinterrupts_bits (lower_sip (lower_mip w__10 w__11) w__12)))
+ : option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option xlenbits).
+
+Definition write_NExt_CSR (csr : mword 12) (value : mword 32)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (legalize_ustatus w__0 value) >>= fun w__1 : Mstatus =>
+ write_reg mstatus_ref w__1 >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__2))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__3 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__4 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__5 : Sinterrupts =>
+ let sie := legalize_uie (lower_mie w__3 w__4) w__5 value in
+ read_reg mie_ref >>= fun w__6 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__7 : Minterrupts =>
+ (lift_sie w__6 w__7 sie) >>= fun w__8 : Minterrupts =>
+ write_reg mie_ref w__8 >>
+ read_reg mie_ref >>= fun w__9 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__9))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_utvec value) >>= fun w__10 : mword 32 => returnm ((Some (w__10)) : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg uscratch_ref value >>
+ ((read_reg uscratch_ref) : M (mword 32)) >>= fun w__11 : mword 32 =>
+ returnm ((Some
+ (w__11))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target User value) >>= fun w__12 : mword 32 =>
+ returnm ((Some
+ (w__12))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits ucause_ref value) >>
+ read_reg ucause_ref >>= fun w__13 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__13))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg utval_ref value >>
+ ((read_reg utval_ref) : M (mword 32)) >>= fun w__14 : mword 32 =>
+ returnm ((Some
+ (w__14))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__15 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__16 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__17 : Sinterrupts =>
+ let sip := legalize_uip (lower_mip w__15 w__16) w__17 value in
+ read_reg mip_ref >>= fun w__18 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__19 : Minterrupts =>
+ (lift_sip w__18 w__19 sip) >>= fun w__20 : Minterrupts =>
+ write_reg mip_ref w__20 >>
+ read_reg mip_ref >>= fun w__21 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__21))
+ : option (mword 32))
+ else returnm (None : option (mword 32))) >>= fun res : option xlenbits =>
+ returnm ((match res with
+ | Some (v) =>
+ let '_ :=
+ (if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr)
+ (String.append " <- "
+ (String.append (string_of_bits v)
+ (String.append " (input: "
+ (String.append (string_of_bits value) ")"))))))
+ else tt)
+ : unit in
+ true
+ | None => false
+ end)
+ : bool).
+
+Definition ext_is_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (is_NExt_CSR_defined csr p)
+ : M (bool).
+
+Definition ext_read_CSR (csr : mword 12)
+: M (option (mword 32)) :=
+
+ (read_NExt_CSR csr)
+ : M (option (mword 32)).
+
+Definition ext_write_CSR (csr : mword 12) (value : mword 32)
+: M (bool) :=
+
+ (write_NExt_CSR csr value)
+ : M (bool).
+
+Definition csrAccess (csr : mword 12) : mword 2 := subrange_vec_dec csr 11 10.
+
+Definition csrPriv (csr : mword 12) : mword 2 := subrange_vec_dec csr 9 8.
+
+Definition is_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 32 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 32 = 32))}))
+ else (ext_is_CSR_defined csr p) : M (bool))
+ : M (bool).
+
+Definition check_CSR_access (csrrw : mword 2) (csrpr : mword 2) (p : Privilege) (isWrite : bool)
+: bool :=
+
+ andb (negb (andb (Bool.eqb isWrite true) (eq_vec csrrw (vec_of_bits [B1;B1] : mword 2))))
+ (zopz0zKzJ_u (privLevel_to_bits p) csrpr).
+
+Definition check_TVM_SATP (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (and_boolM
+ (returnm ((eq_vec csr (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_TVM w__0) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun w__2 : bool =>
+ returnm ((negb w__2)
+ : bool).
+
+Definition check_Counteren (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (match (csr, p) with
+ | (b__0, Supervisor) =>
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__0 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__0) ((bool_to_bits true) : mword 1))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__1 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__1) ((bool_to_bits true) : mword 1))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__2 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__2) ((bool_to_bits true) : mword 1))
+ : bool)
+ else
+ returnm ((match (b__0, Supervisor) with
+ | (_, _) =>
+ if ((andb
+ (zopz0zIzJ_u
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12))))
+ then
+ false
+ else true
+ end)
+ : bool))
+ : M (bool)
+ | (b__3, User) =>
+ (if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__6 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__6) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__7 : bool => returnm ((negb w__7) : bool))
+ (read_reg scounteren_ref >>= fun w__8 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__8) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__11 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__11) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__12 : bool => returnm ((negb w__12) : bool))
+ (read_reg scounteren_ref >>= fun w__13 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__13) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__16 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__16) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__17 : bool => returnm ((negb w__17) : bool))
+ (read_reg scounteren_ref >>= fun w__18 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__18) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else
+ returnm ((match (b__3, User) with
+ | (_, _) =>
+ if ((andb
+ (zopz0zIzJ_u
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12))))
+ then
+ false
+ else true
+ end)
+ : bool))
+ : M (bool)
+ | (_, _) =>
+ returnm ((if ((andb
+ (zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) then
+ false
+ else true)
+ : bool)
+ end)
+ : M (bool).
+
+Definition check_CSR (csr : mword 12) (p : Privilege) (isWrite : bool)
+: M (bool) :=
+
+ (and_boolM ((is_CSR_defined csr p) : M (bool))
+ ((and_boolM (returnm ((check_CSR_access (csrAccess csr) (csrPriv csr) p isWrite) : bool))
+ ((and_boolM ((check_TVM_SATP csr p) : M (bool)) ((check_Counteren csr p) : M (bool)))
+ : M (bool)))
+ : M (bool)))
+ : M (bool).
+
+Axiom speculate_conditional : forall (_ : unit) , M (bool).
+
+Axiom load_reservation : forall (_ : mword 32) , unit.
+
+Axiom match_reservation : forall (_ : mword 32) , bool.
+
+Axiom cancel_reservation : forall (_ : unit) , unit.
+
+Definition exception_delegatee (e : ExceptionType) (p : Privilege)
+: M (Privilege) :=
+
+ let idx := projT1 (num_of_ExceptionType e) in
+ read_reg medeleg_ref >>= fun w__0 : Medeleg =>
+ let super := access_vec_dec (_get_Medeleg_bits w__0) idx in
+ (haveSupMode tt) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (and_boolM ((bit_to_bool super) : M (bool))
+ ((and_boolM ((haveNExt tt) : M (bool))
+ (read_reg sedeleg_ref >>= fun w__4 : Sedeleg =>
+ (bit_to_bool (access_vec_dec (_get_Sedeleg_bits w__4) idx))
+ : M (bool)))
+ : M (bool)))
+ : M (bool)
+ else (and_boolM ((bit_to_bool super) : M (bool)) ((haveNExt tt) : M (bool))) : M (bool)) >>= fun user =>
+ (and_boolMP (build_trivial_ex ((haveUsrMode tt) : M (bool)))
+ ((returnm (build_ex
+ user)) : M ({_bool : bool & ArithFact (iff (_bool = true) (user = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (user = true /\ simp_0 = true))})) >>= fun '(existT _ w__12 _) =>
+ (if sumbool_of_bool (w__12) then returnm (User : Privilege)
+ else
+ (and_boolM ((haveSupMode tt) : M (bool)) ((bit_to_bool super) : M (bool))) >>= fun w__15 : bool =>
+ returnm ((if sumbool_of_bool (w__15) then Supervisor
+ else Machine)
+ : Privilege)) >>= fun deleg =>
+ returnm ((if ((zopz0zI_u (privLevel_to_bits deleg) (privLevel_to_bits p))) then p
+ else deleg)
+ : Privilege).
+
+Definition findPendingInterrupt (ip : mword 32)
+: option InterruptType :=
+
+ let ip := Mk_Minterrupts ip in
+ if ((eq_vec (_get_Minterrupts_MEI ip) ((bool_to_bits true) : mword 1))) then Some (I_M_External)
+ else if ((eq_vec (_get_Minterrupts_MSI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_M_Software)
+ else if ((eq_vec (_get_Minterrupts_MTI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_M_Timer)
+ else if ((eq_vec (_get_Minterrupts_SEI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_External)
+ else if ((eq_vec (_get_Minterrupts_SSI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_Software)
+ else if ((eq_vec (_get_Minterrupts_STI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_Timer)
+ else if ((eq_vec (_get_Minterrupts_UEI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_External)
+ else if ((eq_vec (_get_Minterrupts_USI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_Software)
+ else if ((eq_vec (_get_Minterrupts_UTI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_Timer)
+ else None.
+
+Definition processPending
+(xip : Minterrupts) (xie : Minterrupts) (xideleg : mword 32) (priv_enabled : bool)
+: interrupt_set :=
+
+ let effective_pend :=
+ and_vec (_get_Minterrupts_bits xip) (and_vec (_get_Minterrupts_bits xie) (not_vec xideleg)) in
+ let effective_delg := and_vec (_get_Minterrupts_bits xip) xideleg in
+ if sumbool_of_bool ((andb priv_enabled
+ (neq_vec effective_pend (EXTZ 32 (vec_of_bits [B0] : mword 1))))) then
+ Ints_Pending
+ (effective_pend)
+ else if ((neq_vec effective_delg (EXTZ 32 (vec_of_bits [B0] : mword 1)))) then
+ Ints_Delegated
+ (effective_delg)
+ else Ints_Empty (tt).
+
+Definition getPendingSet (priv : Privilege)
+: M (option ((mword 32 * Privilege))) :=
+
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ assert_exp' w__0 "no user mode: M/U or M/S/U system required" >>= fun _ =>
+ read_reg mip_ref >>= fun w__1 : Minterrupts =>
+ read_reg mie_ref >>= fun w__2 : Minterrupts =>
+ let effective_pending := and_vec (_get_Minterrupts_bits w__1) (_get_Minterrupts_bits w__2) in
+ (if ((eq_vec effective_pending (EXTZ 32 (vec_of_bits [B0] : mword 1)))) then
+ returnm (None
+ : option ((mword 32 * Privilege)))
+ else
+ (or_boolM
+ (returnm ((neq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__3 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_MIE w__3) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun mIE =>
+ (and_boolM ((haveSupMode tt) : M (bool))
+ ((or_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv)
+ ((privLevel_to_bits Supervisor)
+ : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__6 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_SIE w__6) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool))) >>= fun sIE =>
+ (and_boolM ((haveNExt tt) : M (bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_UIE w__10) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun uIE =>
+ read_reg mip_ref >>= fun w__12 : Minterrupts =>
+ read_reg mie_ref >>= fun w__13 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__14 : Minterrupts =>
+ (match (processPending w__12 w__13 (_get_Minterrupts_bits w__14) mIE) with
+ | Ints_Empty (tt) => returnm (None : option ((mword 32 * Privilege)))
+ | Ints_Pending (p) =>
+ let r := (p, Machine) in
+ returnm ((Some
+ (r))
+ : option ((mword 32 * Privilege)))
+ | Ints_Delegated (d) =>
+ (haveSupMode tt) >>= fun w__15 : bool =>
+ (if sumbool_of_bool ((negb w__15)) then
+ returnm ((if sumbool_of_bool (uIE) then
+ let r := (d, User) in
+ Some
+ (r)
+ else None)
+ : option ((mword 32 * Privilege)))
+ else
+ read_reg mie_ref >>= fun w__16 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__17 : Sinterrupts =>
+ returnm ((match (processPending (Mk_Minterrupts d) w__16 (_get_Sinterrupts_bits w__17)
+ sIE) with
+ | Ints_Empty (tt) => None
+ | Ints_Pending (p) =>
+ let r := (p, Supervisor) in
+ Some
+ (r)
+ | Ints_Delegated (d) =>
+ if sumbool_of_bool (uIE) then
+ let r := (d, User) in
+ Some
+ (r)
+ else None
+ end)
+ : option ((mword 32 * Privilege))))
+ : M (option ((mword 32 * Privilege)))
+ end)
+ : M (option ((mword 32 * Privilege))))
+ : M (option ((mword 32 * Privilege))).
+
+Definition dispatchInterrupt (priv : Privilege)
+: M (option ((InterruptType * Privilege))) :=
+
+ (or_boolM ((haveUsrMode tt) >>= fun w__0 : bool => returnm ((negb w__0) : bool))
+ ((and_boolM ((haveSupMode tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))
+ ((haveNExt tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool)))
+ : M (bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ assert_exp (eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) "invalid current privilege" >>
+ read_reg mip_ref >>= fun w__5 : Minterrupts =>
+ read_reg mie_ref >>= fun w__6 : Minterrupts =>
+ let enabled_pending := and_vec (_get_Minterrupts_bits w__5) (_get_Minterrupts_bits w__6) in
+ returnm ((match (findPendingInterrupt enabled_pending) with
+ | Some (i) =>
+ let r := (i, Machine) in
+ Some
+ (r)
+ | None => None
+ end)
+ : option ((InterruptType * Privilege)))
+ else
+ (getPendingSet priv) >>= fun w__7 : option ((mword 32 * Privilege)) =>
+ returnm ((match w__7 with
+ | None => None
+ | Some ((ip, p)) =>
+ match (findPendingInterrupt ip) with
+ | None => None
+ | Some (i) =>
+ let r := (i, p) in
+ Some
+ (r)
+ end
+ end)
+ : option ((InterruptType * Privilege))))
+ : M (option ((InterruptType * Privilege))).
+
+Definition tval (excinfo : option (mword 32))
+: mword 32 :=
+
+ match excinfo with | Some (e) => e | None => EXTZ 32 (vec_of_bits [B0] : mword 1) end.
+
+Definition rvfi_trap '(tt : unit) : unit := tt.
+
+Definition trap_handler
+(del_priv : Privilege) (intr : bool) (c : mword 8) (pc : mword 32) (info : option (mword 32))
+(ext : option unit)
+: M (mword 32) :=
+
+ let '_ := (rvfi_trap tt) : unit in
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "handling "
+ (String.append (if sumbool_of_bool (intr) then "int#" else "exc#")
+ (String.append (string_of_bits c)
+ (String.append " at priv "
+ (String.append (privLevel_to_str del_priv)
+ (String.append " with tval " (string_of_bits (tval info))))))))
+ else tt)
+ : unit in
+ let '_ := (cancel_reservation tt) : unit in
+ (match del_priv with
+ | Machine =>
+ (_set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause mcause_ref (EXTZ 31 c)) >>
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (_set_Mstatus_MPIE mstatus_ref (_get_Mstatus_MIE w__0)) >>
+ (_set_Mstatus_MIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits w__1)) >>
+ write_reg mtval_ref (tval info) >>
+ write_reg mepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__2))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg mcause_ref >>= fun w__3 : Mcause =>
+ (prepare_trap_vector del_priv w__3)
+ : M (mword 32)
+ | Supervisor =>
+ (haveSupMode tt) >>= fun w__5 : bool =>
+ assert_exp' w__5 "no supervisor mode present for delegation" >>= fun _ =>
+ (_set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause scause_ref (EXTZ 31 c)) >>
+ read_reg mstatus_ref >>= fun w__6 : Mstatus =>
+ (_set_Mstatus_SPIE mstatus_ref (_get_Mstatus_SIE w__6)) >>
+ (_set_Mstatus_SIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ read_reg cur_privilege_ref >>= fun w__7 : Privilege =>
+ (match w__7 with
+ | User => returnm ((bool_to_bits false) : mword 1)
+ | Supervisor => returnm ((bool_to_bits true) : mword 1)
+ | Machine => (internal_error "invalid privilege for s-mode trap") : M (mword 1)
+ end) >>= fun w__9 : mword 1 =>
+ (_set_Mstatus_SPP mstatus_ref w__9) >>
+ write_reg stval_ref (tval info) >>
+ write_reg sepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__10))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg scause_ref >>= fun w__11 : Mcause =>
+ (prepare_trap_vector del_priv w__11)
+ : M (mword 32)
+ | User =>
+ (haveUsrMode tt) >>= fun w__13 : bool =>
+ assert_exp' w__13 "no user mode present for delegation" >>= fun _ =>
+ (_set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause ucause_ref (EXTZ 31 c)) >>
+ read_reg mstatus_ref >>= fun w__14 : Mstatus =>
+ (_set_Mstatus_UPIE mstatus_ref (_get_Mstatus_UIE w__14)) >>
+ (_set_Mstatus_UIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ write_reg utval_ref (tval info) >>
+ write_reg uepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__15 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__15))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg ucause_ref >>= fun w__16 : Mcause =>
+ (prepare_trap_vector del_priv w__16)
+ : M (mword 32)
+ end)
+ : M (mword 32).
+
+Definition exception_handler (cur_priv : Privilege) (ctl : ctl_result) (pc : mword 32)
+: M (mword 32) :=
+
+ (match (cur_priv, ctl) with
+ | (_, CTL_TRAP (e)) =>
+ (exception_delegatee e.(sync_exception_trap) cur_priv) >>= fun del_priv =>
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "trapping from "
+ (String.append (privLevel_to_str cur_priv)
+ (String.append " to "
+ (String.append (privLevel_to_str del_priv)
+ (String.append " to handle "
+ (exceptionType_to_str e.(sync_exception_trap)))))))
+ else tt)
+ : unit in
+ (trap_handler del_priv false ((exceptionType_to_bits e.(sync_exception_trap)) : mword 8) pc
+ e.(sync_exception_excinfo) e.(sync_exception_ext))
+ : M (mword 32)
+ | (_, CTL_MRET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ (_set_Mstatus_MIE mstatus_ref (_get_Mstatus_MPIE w__1)) >>
+ (_set_Mstatus_MPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ (privLevel_of_bits (_get_Mstatus_MPP w__2)) >>= fun w__3 : Privilege =>
+ write_reg cur_privilege_ref w__3 >>
+ (haveUsrMode tt) >>= fun w__4 : bool =>
+ (_set_Mstatus_MPP mstatus_ref
+ (privLevel_to_bits (if sumbool_of_bool (w__4) then User else Machine))) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__5 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__5))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__6 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__6)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target Machine) >>= fun w__7 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__8 : mword 32 => returnm ((and_vec w__7 w__8) : mword 32)
+ | (_, CTL_SRET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__9 : Mstatus =>
+ (_set_Mstatus_SIE mstatus_ref (_get_Mstatus_SPIE w__9)) >>
+ (_set_Mstatus_SPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ write_reg
+ cur_privilege_ref
+ (if ((eq_vec (_get_Mstatus_SPP w__10) ((bool_to_bits true) : mword 1))) then Supervisor
+ else User) >>
+ (_set_Mstatus_SPP mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__11 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__11))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__12 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__12)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target Supervisor) >>= fun w__13 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__14 : mword 32 =>
+ returnm ((and_vec w__13 w__14)
+ : mword 32)
+ | (_, CTL_URET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__15 : Mstatus =>
+ (_set_Mstatus_UIE mstatus_ref (_get_Mstatus_UPIE w__15)) >>
+ (_set_Mstatus_UPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ write_reg cur_privilege_ref User >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__16 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__16))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__17 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__17)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target User) >>= fun w__18 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__19 : mword 32 =>
+ returnm ((and_vec w__18 w__19)
+ : mword 32)
+ end)
+ : M (mword 32).
+
+Definition handle_mem_exception (addr : mword 32) (e : ExceptionType)
+: M (unit) :=
+
+ let t : sync_exception :=
+ {| sync_exception_trap := e;
+ sync_exception_excinfo := (Some (addr));
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__1 : mword 32 =>
+ (exception_handler w__0 (CTL_TRAP (t)) w__1) >>= fun w__2 : mword 32 =>
+ (set_next_pc w__2)
+ : M (unit).
+
+Definition handle_interrupt (i : InterruptType) (del_priv : Privilege)
+: M (unit) :=
+
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ (trap_handler del_priv true ((interruptType_to_bits i) : mword 8) w__0 None None) >>= fun w__1 : mword 32 =>
+ (set_next_pc w__1)
+ : M (unit).
+
+Definition init_sys '(tt : unit)
+: M (unit) :=
+
+ write_reg cur_privilege_ref Machine >>
+ write_reg mhartid_ref (EXTZ 32 (vec_of_bits [B0] : mword 1)) >>
+ (_set_Misa_MXL misa_ref (arch_to_bits RV32)) >>
+ (_set_Misa_A misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_C misa_ref ((bool_to_bits (sys_enable_rvc tt)) : mword 1)) >>
+ (_set_Misa_I misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_M misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_U misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_S misa_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ read_reg misa_ref >>= fun w__1 : Misa =>
+ write_reg mstatus_ref (set_mstatus_SXL w__0 (_get_Misa_MXL w__1)) >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ read_reg misa_ref >>= fun w__3 : Misa =>
+ write_reg mstatus_ref (set_mstatus_UXL w__2 (_get_Misa_MXL w__3)) >>
+ (_set_Mstatus_SD mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ (_set_Minterrupts_bits mip_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Minterrupts_bits mie_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Minterrupts_bits mideleg_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Medeleg_bits medeleg_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Mtvec_bits mtvec_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Mcause_bits mcause_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ write_reg mepc_ref (EXTZ 32 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mtval_ref (EXTZ 32 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mscratch_ref (EXTZ 32 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mcycle_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mtime_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ (_set_Counteren_bits mcounteren_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ write_reg minstret_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg minstret_written_ref false >>
+ (init_pmp tt) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- "
+ (String.append (string_of_bits (_get_Mstatus_bits w__4))
+ (String.append " (input: "
+ (String.append
+ (string_of_bits ((EXTZ 32 (vec_of_bits [B0] : mword 1)) : xlenbits))
+ ")")))))
+ : unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Axiom elf_tohost : forall (_ : unit) , Z.
+
+Axiom elf_entry : forall (_ : unit) , Z.
+
+Axiom plat_ram_base : forall (_ : unit) , mword 32.
+
+Axiom plat_ram_size : forall (_ : unit) , mword 32.
+
+Axiom plat_enable_pmp : forall (_ : unit) , bool.
+
+Axiom plat_enable_dirty_update : forall (_ : unit) , bool.
+
+Axiom plat_enable_misaligned_access : forall (_ : unit) , bool.
+
+Axiom plat_mtval_has_illegal_inst_bits : forall (_ : unit) , bool.
+
+Axiom plat_rom_base : forall (_ : unit) , mword 32.
+
+Axiom plat_rom_size : forall (_ : unit) , mword 32.
+
+Axiom plat_clint_base : forall (_ : unit) , mword 32.
+
+Axiom plat_clint_size : forall (_ : unit) , mword 32.
+
+Definition plat_htif_tohost '(tt : unit) : mword 32 := to_bits 32 (elf_tohost tt).
+
+Definition phys_mem_segments '(tt : unit)
+: list ((mword 32 * mword 32)) :=
+
+ (plat_rom_base tt, plat_rom_size tt) :: (plat_ram_base tt, plat_ram_size tt) :: [].
+
+Definition within_phys_mem (addr : mword 32) (width : Z) `{ArithFact (width <= 16)}
+: bool :=
+
+ let addr_int := projT1 (uint addr) in
+ let ram_base_int := projT1 (uint (plat_ram_base tt)) in
+ let rom_base_int := projT1 (uint (plat_rom_base tt)) in
+ let ram_size_int := projT1 (uint (plat_ram_size tt)) in
+ let rom_size_int := projT1 (uint (plat_rom_size tt)) in
+ if sumbool_of_bool ((andb (Z.leb ram_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width)))
+ (Z.add ram_base_int ram_size_int)))) then
+ true
+ else if sumbool_of_bool ((andb (Z.leb rom_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width)))
+ (Z.add rom_base_int rom_size_int)))) then
+ true
+ else
+ let '_ :=
+ (print_endline
+ (String.append "within_phys_mem: "
+ (String.append (string_of_bits addr) " not within phys-mem:")))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_rom_base: " (string_of_bits (plat_rom_base tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_rom_size: " (string_of_bits (plat_rom_size tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_ram_base: " (string_of_bits (plat_ram_base tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_ram_size: " (string_of_bits (plat_ram_size tt))))
+ : unit in
+ false.
+
+Definition within_clint (addr : mword 32) (width : Z) `{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ let addr_int := projT1 (uint addr) in
+ let clint_base_int := projT1 (uint (plat_clint_base tt)) in
+ let clint_size_int := projT1 (uint (plat_clint_size tt)) in
+ andb (Z.leb clint_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width))) (Z.add clint_base_int clint_size_int)).
+
+Definition within_htif_writable (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (eq_vec (plat_htif_tohost tt) addr)
+ (andb (eq_vec (add_vec_int (plat_htif_tohost tt) 4) addr) (Z.eqb width 4)).
+
+Definition within_htif_readable (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (eq_vec (plat_htif_tohost tt) addr)
+ (andb (eq_vec (add_vec_int (plat_htif_tohost tt) 4) addr) (Z.eqb width 4)).
+
+Axiom plat_insns_per_tick : forall (_ : unit) , Z.
+
+Definition MSIP_BASE : xlenbits :=
+EXTZ 32 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 20).
+Hint Unfold MSIP_BASE : sail.
+Definition MTIMECMP_BASE : xlenbits :=
+EXTZ 32 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 20).
+Hint Unfold MTIMECMP_BASE : sail.
+Definition MTIMECMP_BASE_HI : xlenbits :=
+EXTZ 32 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 20).
+Hint Unfold MTIMECMP_BASE_HI : sail.
+Definition MTIME_BASE : xlenbits :=
+EXTZ 32 (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0] : mword 20).
+Hint Unfold MTIME_BASE : sail.
+Definition MTIME_BASE_HI : xlenbits :=
+EXTZ 32 (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0] : mword 20).
+Hint Unfold MTIME_BASE_HI : sail.
+Definition clint_load (addr : mword 32) (width : Z) `{ArithFact (width > 0)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ let addr := sub_vec addr (plat_clint_base tt) in
+ (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE)
+ (orb (Z.eqb (projT1 (__id width)) 8) (Z.eqb (projT1 (__id width)) 4))))
+ then
+ (if ((get_config_print_platform tt)) then
+ read_reg mip_ref >>= fun w__0 : Minterrupts =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (_get_Minterrupts_MSI w__0))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg mip_ref >>= fun w__1 : Minterrupts =>
+ returnm ((MemValue
+ (zero_extend (_get_Minterrupts_MSI w__1) (Z.mul 8 (projT1 (__id width)))))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (subrange_vec_dec w__2 31 0))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__3 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 8)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__4 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint<8>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__4)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__5 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__5 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__6 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint-hi<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (subrange_vec_dec w__6 63 32))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__7 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__7 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb (projT1 (__id width)) 4))) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__8 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__8)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__9 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__9 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb (projT1 (__id width)) 8))) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__10 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__10)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__11 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__11 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__12 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__12)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__13 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__13 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint[" (String.append (string_of_bits addr) "] -> <not-mapped>"))
+ else tt)
+ : unit in
+ returnm ((MemException
+ (E_Load_Access_Fault))
+ : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition clint_dispatch '(tt : unit)
+: M (unit) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline (String.append "clint::tick mtime <- " (string_of_bits w__0)))
+ : unit)
+ else returnm (tt : unit)) >>
+ (_set_Minterrupts_MTI mip_ref ((bool_to_bits false) : mword 1)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (if ((zopz0zIzJ_u w__1 w__2)) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((print_endline
+ (String.append " clint timer pending at mtime " (string_of_bits w__3)))
+ : unit)
+ else returnm (tt : unit)) >>
+ (_set_Minterrupts_MTI mip_ref ((bool_to_bits true) : mword 1))
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Definition clint_store (addr : mword 32) (width : Z) (data : mword (8 * width))
+`{ArithFact (width > 0)}
+: M (MemoryOpResult bool) :=
+
+ let addr := sub_vec addr (plat_clint_base tt) in
+ (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE)
+ (orb (Z.eqb (projT1 (__id width)) 8) (Z.eqb (projT1 (__id width)) 4))))
+ then
+ (if ((get_config_print_platform tt)) then
+ (cast_unit_vec (access_vec_dec data 0)) >>= fun w__0 : mword 1 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] <- "
+ (String.append (string_of_bits data)
+ (String.append " (mip.MSI <- "
+ (String.append (string_of_bits w__0) ")")))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (cast_unit_vec (access_vec_dec data 0)) >>= fun w__1 : mword 1 =>
+ (_set_Minterrupts_MSI mip_ref
+ ((bool_to_bits (eq_vec w__1 (vec_of_bits [B1] : mword 1)))
+ : mword 1)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 8)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<8>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ write_reg mtimecmp_ref (zero_extend data 64) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ write_reg mtimecmp_ref (update_subrange_vec_dec w__2 31 0 (zero_extend data 32)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ write_reg mtimecmp_ref (update_subrange_vec_dec w__3 63 32 (zero_extend data 32)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (<unmapped>)"))))
+ else tt)
+ : unit in
+ returnm ((MemException
+ (E_SAMO_Access_Fault))
+ : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition tick_clock '(tt : unit)
+: M (unit) :=
+
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ write_reg mcycle_ref (add_vec_int w__0 1) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg mtime_ref (add_vec_int w__1 1) >> (clint_dispatch tt) : M (unit).
+
+Axiom plat_term_write : forall (_ : mword 8) , unit.
+
+Axiom plat_term_read : forall (_ : unit) , mword 8.
+
+Definition Mk_htif_cmd (v : mword 64)
+: htif_cmd :=
+
+ {| htif_cmd_htif_cmd_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_htif_cmd_bits (v : htif_cmd)
+: mword 64 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0.
+
+Definition _set_htif_cmd_bits (r_ref : register_ref regstate register_value htif_cmd) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_bits (v : htif_cmd) (x : mword 64)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_htif_cmd_device (v : htif_cmd)
+: mword 8 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56.
+
+Definition _set_htif_cmd_device
+(r_ref : register_ref regstate register_value htif_cmd) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec v 7 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_device (v : htif_cmd) (x : mword 8)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_htif_cmd_cmd (v : htif_cmd)
+: mword 8 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48.
+
+Definition _set_htif_cmd_cmd (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec v 7 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_cmd (v : htif_cmd) (x : mword 8)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_htif_cmd_payload (v : htif_cmd)
+: mword 48 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0.
+
+Definition _set_htif_cmd_payload
+(r_ref : register_ref regstate register_value htif_cmd) (v : mword 48)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_payload (v : htif_cmd) (x : mword 48)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}.
+
+Definition htif_load (addr : mword 32) (width : Z) `{ArithFact (width > 0)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline
+ (String.append "htif["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__0)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if sumbool_of_bool ((andb (Z.eqb width 8) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__1 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (Z.eqb width 4) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__2 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (Z.eqb width 4)
+ (eq_vec addr (add_vec_int (plat_htif_tohost tt) 4)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__3 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition htif_store (addr : mword 32) (width : Z) (data : mword (8 * width))
+`{ArithFact (0 < width /\ width <= 8)}
+: M (MemoryOpResult bool) :=
+
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif["
+ (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))
+ else tt)
+ : unit in
+ (if sumbool_of_bool ((Z.eqb width 8)) then write_reg htif_tohost_ref (EXTZ 64 data) : M (unit)
+ else if sumbool_of_bool ((andb (Z.eqb width 4) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ write_reg htif_tohost_ref (update_subrange_vec_dec w__0 31 0 (autocast (autocast data)))
+ : M (unit)
+ else if sumbool_of_bool ((andb (Z.eqb width 4)
+ (eq_vec addr (add_vec_int (plat_htif_tohost tt) 4)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg htif_tohost_ref (update_subrange_vec_dec w__1 63 32 (autocast (autocast data)))
+ : M (unit)
+ else write_reg htif_tohost_ref (EXTZ 64 data) : M (unit)) >>
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ let cmd := Mk_htif_cmd w__2 in
+ let b__0 := _get_htif_cmd_device cmd in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif-syscall-proxy cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))
+ else tt)
+ : unit in
+ (cast_unit_vec (access_vec_dec (_get_htif_cmd_payload cmd) 0)) >>= fun w__3 : mword 1 =>
+ (if ((eq_vec w__3 (vec_of_bits [B1] : mword 1))) then
+ write_reg htif_done_ref true >>
+ write_reg htif_exit_code_ref (shiftr (zero_extend (_get_htif_cmd_payload cmd) 64) 1)
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit)
+ else
+ returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif-term cmd: "
+ (string_of_bits (_get_htif_cmd_payload cmd)))
+ else tt)
+ : unit in
+ let b__2 := _get_htif_cmd_cmd cmd in
+ if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then tt
+ else if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then
+ plat_term_write (subrange_vec_dec (_get_htif_cmd_payload cmd) 7 0)
+ else print_endline (String.append "Unknown term cmd: " (string_of_bits b__2))
+ else print_endline (String.append "htif-???? cmd: " (string_of_bits data)))
+ : unit)) >>
+ returnm ((MemValue
+ (true))
+ : MemoryOpResult bool).
+
+Definition htif_tick '(tt : unit)
+: M (unit) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline (String.append "htif::tick " (string_of_bits w__0)))
+ : unit)
+ else returnm (tt : unit)) >>
+ write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))
+ : M (unit).
+
+Definition within_mmio_readable (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (within_clint addr width)
+ (andb (within_htif_readable addr width) (Z.leb 1 (projT1 (__id width)))).
+
+Definition within_mmio_writable (addr : mword 32) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (within_clint addr width)
+ (andb (within_htif_writable addr width) (Z.leb (projT1 (__id width)) 8)).
+
+Definition mmio_read (addr : mword 32) (width : Z) `{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((within_clint addr width)) then
+ (clint_load addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (within_htif_readable addr width) (Z.leb 1 (projT1 (__id width)))))
+ then
+ (htif_load addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition mmio_write (addr : mword 32) (width : Z) (data : mword (8 * width))
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((within_clint addr width)) then (clint_store addr width data) : M (MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (within_htif_writable addr width) (Z.leb (projT1 (__id width)) 8)))
+ then
+ (htif_store addr width data)
+ : M (MemoryOpResult bool)
+ else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition init_platform '(tt : unit)
+: M (unit) :=
+
+ write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg htif_done_ref false >>
+ write_reg htif_exit_code_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))
+ : M (unit).
+
+Definition tick_platform '(tt : unit) : M (unit) := (htif_tick tt) : M (unit).
+
+Definition handle_illegal '(tt : unit)
+: M (unit) :=
+
+ (if ((plat_mtval_has_illegal_inst_bits tt)) then
+ ((read_reg instbits_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ returnm ((Some
+ (w__0))
+ : option (mword 32))
+ else returnm (None : option (mword 32))) >>= fun info =>
+ let t : sync_exception :=
+ {| sync_exception_trap := E_Illegal_Instr;
+ sync_exception_excinfo := info;
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__2 : mword 32 =>
+ (exception_handler w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 32 =>
+ (set_next_pc w__3)
+ : M (unit).
+
+Definition platform_wfi '(tt : unit)
+: M (unit) :=
+
+ let '_ := (cancel_reservation tt) : unit in
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ (if ((zopz0zI_u w__0 w__1)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ write_reg mtime_ref w__2 >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ write_reg mcycle_ref w__3
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Definition is_aligned_addr (addr : mword 32) (width : Z)
+: bool :=
+
+ Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) width)) 0.
+
+Definition phys_mem_read
+(t : AccessType) (addr : mword 32) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (match (aq, rl, res) with
+ | (false, false, false) =>
+ (read_ram Read_plain addr width) >>= fun w__0 : mword (8 * width) =>
+ returnm ((Some
+ (w__0))
+ : option (mword (8 * width)))
+ | (true, false, false) =>
+ (read_ram Read_RISCV_acquire addr width) >>= fun w__1 : mword (8 * width) =>
+ returnm ((Some
+ (w__1))
+ : option (mword (8 * width)))
+ | (true, true, false) =>
+ (read_ram Read_RISCV_strong_acquire addr width) >>= fun w__2 : mword (8 * width) =>
+ returnm ((Some
+ (w__2))
+ : option (mword (8 * width)))
+ | (false, false, true) =>
+ (read_ram Read_RISCV_reserved addr width) >>= fun w__3 : mword (8 * width) =>
+ returnm ((Some
+ (w__3))
+ : option (mword (8 * width)))
+ | (true, false, true) =>
+ (read_ram Read_RISCV_reserved_acquire addr width) >>= fun w__4 : mword (8 * width) =>
+ returnm ((Some
+ (w__4))
+ : option (mword (8 * width)))
+ | (true, true, true) =>
+ (read_ram Read_RISCV_reserved_strong_acquire addr width) >>= fun w__5 : mword (8 * width) =>
+ returnm ((Some
+ (w__5))
+ : option (mword (8 * width)))
+ | (false, true, false) => returnm (None : option (mword (8 * width)))
+ | (false, true, true) => returnm (None : option (mword (8 * width)))
+ end) >>= fun w__6 : option (mword (8 * width)) =>
+ let result := w__6 : option (bits (8 * width)) in
+ returnm ((match (t, result) with
+ | (Execute, None) => MemException (E_Fetch_Access_Fault)
+ | (Read, None) => MemException (E_Load_Access_Fault)
+ | (_, None) => MemException (E_SAMO_Access_Fault)
+ | (_, Some (v)) =>
+ let '_ :=
+ (if ((get_config_print_mem tt)) then
+ print_endline
+ (String.append "mem["
+ (String.append (accessType_to_str t)
+ (String.append ","
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits v))))))
+ else tt)
+ : unit in
+ MemValue
+ (v)
+ end)
+ : MemoryOpResult (mword (8 * width))).
+
+Definition checked_mem_read
+(t : AccessType) (addr : mword 32) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((within_mmio_readable addr width)) then
+ (mmio_read addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else if ((within_phys_mem addr width)) then
+ (phys_mem_read t addr width aq rl res)
+ : M (MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition pmp_mem_read
+(t : AccessType) (addr : mword 32) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((negb (plat_enable_pmp tt))) then
+ (checked_mem_read t addr width aq rl res)
+ : M (MemoryOpResult (mword (8 * width)))
+ else
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2) >>= fun w__3 : Privilege =>
+ (pmpCheck addr width t w__3) >>= fun w__4 : option ExceptionType =>
+ (match w__4 with
+ | None => (checked_mem_read t addr width aq rl res) : M (MemoryOpResult (mword (8 * width)))
+ | Some (e) => returnm ((MemException (e)) : MemoryOpResult (mword (8 * width)))
+ end)
+ : M (MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition rvfi_read (addr : mword 32) (width : Z) (value : MemoryOpResult (mword (8 * width)))
+`{ArithFact (width > 0)}
+: unit :=
+
+ tt.
+
+Definition mem_read
+(typ : AccessType) (addr : mword 32) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if sumbool_of_bool ((andb (orb aq res) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_Load_Addr_Align))
+ : MemoryOpResult (mword (8 * width)))
+ else
+ (match (aq, rl, res) with
+ | (false, true, false) => throw (Error_not_implemented ("load.rl"))
+ | (false, true, true) => throw (Error_not_implemented ("lr.rl"))
+ | (_, _, _) =>
+ (pmp_mem_read typ addr width aq rl res) : M (MemoryOpResult (mword (8 * width)))
+ end)
+ : M (MemoryOpResult (mword (8 * width)))) >>= fun result : MemoryOpResult (bits (8 * width)) =>
+ let '_ := (rvfi_read addr width result) : unit in
+ returnm (result
+ : MemoryOpResult (mword (8 * width))).
+
+Definition mem_write_ea (addr : mword 32) (width : Z) (aq : bool) (rl : bool) (con : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult unit) :=
+
+ (if sumbool_of_bool ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_SAMO_Addr_Align))
+ : MemoryOpResult unit)
+ else
+ (match (aq, rl, con) with
+ | (false, false, false) =>
+ (write_ram_ea Write_plain addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit)
+ | (false, true, false) =>
+ (write_ram_ea Write_RISCV_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (false, false, true) =>
+ (write_ram_ea Write_RISCV_conditional addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (false, true, true) =>
+ (write_ram_ea Write_RISCV_conditional_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (true, false, false) => throw (Error_not_implemented ("store.aq"))
+ | (true, true, false) =>
+ (write_ram_ea Write_RISCV_strong_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (true, false, true) => throw (Error_not_implemented ("sc.aq"))
+ | (true, true, true) =>
+ (write_ram_ea Write_RISCV_conditional_strong_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ end)
+ : M (MemoryOpResult unit))
+ : M (MemoryOpResult unit).
+
+Definition rvfi_write (addr : mword 32) (width : Z) (value : mword (8 * width))
+`{ArithFact (width > 0)}
+: unit :=
+
+ tt.
+
+Definition phys_mem_write
+(wk : write_kind) (addr : mword 32) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ let '_ := (rvfi_write addr width data) : unit in
+ (write_ram wk addr width data meta) >>= fun w__0 : bool =>
+ let result := MemValue (w__0) in
+ let '_ :=
+ (if ((get_config_print_mem tt)) then
+ print_endline
+ (String.append "mem["
+ (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))
+ else tt)
+ : unit in
+ returnm (result
+ : MemoryOpResult bool).
+
+Definition checked_mem_write
+(wk : write_kind) (addr : mword 32) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((within_mmio_writable addr width)) then
+ (mmio_write addr width data)
+ : M (MemoryOpResult bool)
+ else if ((within_phys_mem addr width)) then
+ (phys_mem_write wk addr width data meta)
+ : M (MemoryOpResult bool)
+ else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition pmp_mem_write
+(wk : write_kind) (addr : mword 32) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((negb (plat_enable_pmp tt))) then
+ (checked_mem_write wk addr width data meta)
+ : M (MemoryOpResult bool)
+ else
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2) >>= fun w__3 : Privilege =>
+ (pmpCheck addr width Write w__3) >>= fun w__4 : option ExceptionType =>
+ (match w__4 with
+ | None => (checked_mem_write wk addr width data meta) : M (MemoryOpResult bool)
+ | Some (e) => returnm ((MemException (e)) : MemoryOpResult bool)
+ end)
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition mem_write_value_meta
+(addr : mword 32) (width : Z) (value : mword (8 * width)) (meta : unit) (aq : bool) (rl : bool)
+(con : bool) `{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ let '_ := (rvfi_write addr width value) : unit in
+ (if sumbool_of_bool ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_SAMO_Addr_Align))
+ : MemoryOpResult bool)
+ else
+ (match (aq, rl, con) with
+ | (false, false, false) =>
+ (pmp_mem_write Write_plain addr width value meta) : M (MemoryOpResult bool)
+ | (false, true, false) =>
+ (pmp_mem_write Write_RISCV_release addr width value meta) : M (MemoryOpResult bool)
+ | (false, false, true) =>
+ (pmp_mem_write Write_RISCV_conditional addr width value meta) : M (MemoryOpResult bool)
+ | (false, true, true) =>
+ (pmp_mem_write Write_RISCV_conditional_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, true, false) =>
+ (pmp_mem_write Write_RISCV_strong_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, true, true) =>
+ (pmp_mem_write Write_RISCV_conditional_strong_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, false, false) => throw (Error_not_implemented ("store.aq"))
+ | (true, false, true) => throw (Error_not_implemented ("sc.aq"))
+ end)
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition mem_write_value
+(addr : mword 32) (width : Z) (value : mword (8 * width)) (aq : bool) (rl : bool) (con : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (mem_write_value_meta addr width value default_meta aq rl con)
+ : M (MemoryOpResult bool).
+
+Definition PAGESIZE_BITS := 12.
+Hint Unfold PAGESIZE_BITS : sail.
+Definition Mk_PTE_Bits (v : mword 8)
+: PTE_Bits :=
+
+ {| PTE_Bits_PTE_Bits_chunk_0 := (subrange_vec_dec v 7 0) |}.
+
+Definition _get_PTE_Bits_bits (v : PTE_Bits)
+: mword 8 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0.
+
+Definition _set_PTE_Bits_bits (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_bits (v : PTE_Bits) (x : mword 8)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_PTE_Bits_D (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7.
+
+Definition _set_PTE_Bits_D (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_D (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_A (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6.
+
+Definition _set_PTE_Bits_A (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_A (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_G (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5.
+
+Definition _set_PTE_Bits_G (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_G (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_U (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4.
+
+Definition _set_PTE_Bits_U (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_U (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_X (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3.
+
+Definition _set_PTE_Bits_X (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_X (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_W (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2.
+
+Definition _set_PTE_Bits_W (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_W (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_R (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1.
+
+Definition _set_PTE_Bits_R (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_R (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_V (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0.
+
+Definition _set_PTE_Bits_V (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_V (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition isPTEPtr (p : mword 8)
+: bool :=
+
+ let a := Mk_PTE_Bits p in
+ andb (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits false) : mword 1))
+ (eq_vec (_get_PTE_Bits_X a) ((bool_to_bits false) : mword 1))).
+
+Definition isInvalidPTE (p : mword 8)
+: bool :=
+
+ let a := Mk_PTE_Bits p in
+ orb (eq_vec (_get_PTE_Bits_V a) ((bool_to_bits false) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))).
+
+Definition checkPTEPermission
+(ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits)
+: M (bool) :=
+
+ (match (ac, priv) with
+ | (Read, User) =>
+ returnm (andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))
+ | (Write, User) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (ReadWrite, User) =>
+ returnm (andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))))
+ | (Execute, User) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (Read, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))
+ | (Write, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)))
+ | (ReadWrite, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))))
+ | (Execute, Supervisor) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1))
+ (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (_, Machine) => (internal_error "m-mode mem perm check") : M (bool)
+ end)
+ : M (bool).
+
+Definition update_PTE_Bits (p : PTE_Bits) (a : AccessType)
+: option PTE_Bits :=
+
+ let update_d :=
+ andb (orb (generic_eq a Write) (generic_eq a ReadWrite))
+ (eq_vec (_get_PTE_Bits_D p) ((bool_to_bits false) : mword 1)) in
+ let update_a := eq_vec (_get_PTE_Bits_A p) ((bool_to_bits false) : mword 1) in
+ if sumbool_of_bool ((orb update_d update_a)) then
+ let np := _update_PTE_Bits_A p ((bool_to_bits true) : mword 1) in
+ let np :=
+ if sumbool_of_bool (update_d) then _update_PTE_Bits_D np ((bool_to_bits true) : mword 1)
+ else np in
+ Some
+ (np)
+ else None.
+
+Definition PTW_Error_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)}
+: PTW_Error :=
+
+ let l__11 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__11 0)) then PTW_Access
+ else if sumbool_of_bool ((Z.eqb l__11 1)) then PTW_Invalid_PTE
+ else if sumbool_of_bool ((Z.eqb l__11 2)) then PTW_No_Permission
+ else if sumbool_of_bool ((Z.eqb l__11 3)) then PTW_Misaligned
+ else PTW_PTE_Update.
+
+Definition num_of_PTW_Error (arg_ : PTW_Error)
+: {e : Z & ArithFact (0 <= e /\ e <= 4)} :=
+
+ build_ex(match arg_ with
+ | PTW_Access => 0
+ | PTW_Invalid_PTE => 1
+ | PTW_No_Permission => 2
+ | PTW_Misaligned => 3
+ | PTW_PTE_Update => 4
+ end).
+
+Definition ptw_error_to_str (e : PTW_Error)
+: string :=
+
+ match e with
+ | PTW_Access => "mem-access-error"
+ | PTW_Invalid_PTE => "invalid-pte"
+ | PTW_No_Permission => "no-permission"
+ | PTW_Misaligned => "misaligned-superpage"
+ | PTW_PTE_Update => "pte-update-needed"
+ end.
+
+Definition translationException (a : AccessType) (f : PTW_Error)
+: ExceptionType :=
+
+ match (a, f) with
+ | (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+ | (ReadWrite, _) => E_SAMO_Page_Fault
+ | (Read, PTW_Access) => E_Load_Access_Fault
+ | (Read, _) => E_Load_Page_Fault
+ | (Write, PTW_Access) => E_SAMO_Access_Fault
+ | (Write, _) => E_SAMO_Page_Fault
+ | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+ | (Fetch, _) => E_Fetch_Page_Fault
+ end.
+
+Definition curAsid32 (satp : mword 32)
+: mword 9 :=
+
+ let s := Mk_Satp32 satp in
+ _get_Satp32_Asid s.
+
+Definition curPTB32 (satp : mword 32)
+: mword 34 :=
+
+ let s : Satp32 := Mk_Satp32 satp in
+ shiftl (EXTZ 34 (_get_Satp32_PPN s)) PAGESIZE_BITS.
+
+Definition SV32_LEVEL_BITS := 10.
+Hint Unfold SV32_LEVEL_BITS : sail.
+Definition SV32_LEVELS := 2.
+Hint Unfold SV32_LEVELS : sail.
+Definition PTE32_LOG_SIZE := 2.
+Hint Unfold PTE32_LOG_SIZE : sail.
+Definition PTE32_SIZE := 4.
+Hint Unfold PTE32_SIZE : sail.
+Definition Mk_SV32_Vaddr (v : mword 32)
+: SV32_Vaddr :=
+
+ {| SV32_Vaddr_SV32_Vaddr_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_SV32_Vaddr_bits (v : SV32_Vaddr)
+: mword 32 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0.
+
+Definition _set_SV32_Vaddr_bits
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_bits (v : SV32_Vaddr) (x : mword 32)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_SV32_Vaddr_VPNi (v : SV32_Vaddr)
+: mword 20 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12.
+
+Definition _set_SV32_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 20)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12 (subrange_vec_dec v 19 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_VPNi (v : SV32_Vaddr) (x : mword 20)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12 (subrange_vec_dec x 19 0)) ]}.
+
+Definition _get_SV32_Vaddr_PgOfs (v : SV32_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV32_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_PgOfs (v : SV32_Vaddr) (x : mword 12)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV32_Paddr (v : mword 34)
+: SV32_Paddr :=
+
+ {| SV32_Paddr_SV32_Paddr_chunk_0 := (subrange_vec_dec v 33 0) |}.
+
+Definition _get_SV32_Paddr_bits (v : SV32_Paddr)
+: mword 34 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0.
+
+Definition _set_SV32_Paddr_bits
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 34)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0 (subrange_vec_dec v 33 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_bits (v : SV32_Paddr) (x : mword 34)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0 (subrange_vec_dec x 33 0)) ]}.
+
+Definition _get_SV32_Paddr_PPNi (v : SV32_Paddr)
+: mword 22 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12.
+
+Definition _set_SV32_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 22)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12 (subrange_vec_dec v 21 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_PPNi (v : SV32_Paddr) (x : mword 22)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12 (subrange_vec_dec x 21 0)) ]}.
+
+Definition _get_SV32_Paddr_PgOfs (v : SV32_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0.
+
+Definition _set_SV32_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_PgOfs (v : SV32_Paddr) (x : mword 12)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV32_PTE (v : mword 32)
+: SV32_PTE :=
+
+ {| SV32_PTE_SV32_PTE_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_SV32_PTE_bits (v : SV32_PTE)
+: mword 32 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 0.
+
+Definition _set_SV32_PTE_bits (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 32)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_bits (v : SV32_PTE) (x : mword 32)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_SV32_PTE_PPNi (v : SV32_PTE)
+: mword 22 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 10.
+
+Definition _set_SV32_PTE_PPNi (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 22)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 31 10 (subrange_vec_dec v 21 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_PPNi (v : SV32_PTE) (x : mword 22)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 10 (subrange_vec_dec x 21 0)) ]}.
+
+Definition _get_SV32_PTE_RSW (v : SV32_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 9 8.
+
+Definition _set_SV32_PTE_RSW (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_RSW (v : SV32_PTE) (x : mword 2)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV32_PTE_BITS (v : SV32_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 7 0.
+
+Definition _set_SV32_PTE_BITS (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_BITS (v : SV32_PTE) (x : mword 8)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition curAsid64 (satp : mword 64)
+: mword 16 :=
+
+ let s := Mk_Satp64 satp in
+ _get_Satp64_Asid s.
+
+Definition curPTB64 (satp : mword 64)
+: mword 56 :=
+
+ let s := Mk_Satp64 satp in
+ shiftl (EXTZ 56 (_get_Satp64_PPN s)) PAGESIZE_BITS.
+
+Definition SV39_LEVEL_BITS := 9.
+Hint Unfold SV39_LEVEL_BITS : sail.
+Definition SV39_LEVELS := 3.
+Hint Unfold SV39_LEVELS : sail.
+Definition PTE39_LOG_SIZE := 3.
+Hint Unfold PTE39_LOG_SIZE : sail.
+Definition PTE39_SIZE := 8.
+Hint Unfold PTE39_SIZE : sail.
+Definition Mk_SV39_Vaddr (v : mword 39)
+: SV39_Vaddr :=
+
+ {| SV39_Vaddr_SV39_Vaddr_chunk_0 := (subrange_vec_dec v 38 0) |}.
+
+Definition _get_SV39_Vaddr_bits (v : SV39_Vaddr)
+: mword 39 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0.
+
+Definition _set_SV39_Vaddr_bits
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 39)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec v 38 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_bits (v : SV39_Vaddr) (x : mword 39)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec x 38 0)) ]}.
+
+Definition _get_SV39_Vaddr_VPNi (v : SV39_Vaddr)
+: mword 27 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12.
+
+Definition _set_SV39_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 27)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_VPNi (v : SV39_Vaddr) (x : mword 27)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_SV39_Vaddr_PgOfs (v : SV39_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV39_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_PgOfs (v : SV39_Vaddr) (x : mword 12)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV39_Paddr (v : mword 56)
+: SV39_Paddr :=
+
+ {| SV39_Paddr_SV39_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}.
+
+Definition _get_SV39_Paddr_bits (v : SV39_Paddr)
+: mword 56 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0.
+
+Definition _set_SV39_Paddr_bits
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 56)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_bits (v : SV39_Paddr) (x : mword 56)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}.
+
+Definition _get_SV39_Paddr_PPNi (v : SV39_Paddr)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12.
+
+Definition _set_SV39_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_PPNi (v : SV39_Paddr) (x : mword 44)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV39_Paddr_PgOfs (v : SV39_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0.
+
+Definition _set_SV39_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_PgOfs (v : SV39_Paddr) (x : mword 12)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV39_PTE (v : mword 64)
+: SV39_PTE :=
+
+ {| SV39_PTE_SV39_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_SV39_PTE_bits (v : SV39_PTE)
+: mword 64 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0.
+
+Definition _set_SV39_PTE_bits (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_bits (v : SV39_PTE) (x : mword 64)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_SV39_PTE_PPNi (v : SV39_PTE)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10.
+
+Definition _set_SV39_PTE_PPNi (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 44)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_PPNi (v : SV39_PTE) (x : mword 44)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV39_PTE_RSW (v : SV39_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8.
+
+Definition _set_SV39_PTE_RSW (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_RSW (v : SV39_PTE) (x : mword 2)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV39_PTE_BITS (v : SV39_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0.
+
+Definition _set_SV39_PTE_BITS (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_BITS (v : SV39_PTE) (x : mword 8)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition SV48_LEVEL_BITS := 9.
+Hint Unfold SV48_LEVEL_BITS : sail.
+Definition SV48_LEVELS := 4.
+Hint Unfold SV48_LEVELS : sail.
+Definition PTE48_LOG_SIZE := 3.
+Hint Unfold PTE48_LOG_SIZE : sail.
+Definition PTE48_SIZE := 8.
+Hint Unfold PTE48_SIZE : sail.
+Definition Mk_SV48_Vaddr (v : mword 48)
+: SV48_Vaddr :=
+
+ {| SV48_Vaddr_SV48_Vaddr_chunk_0 := (subrange_vec_dec v 47 0) |}.
+
+Definition _get_SV48_Vaddr_bits (v : SV48_Vaddr)
+: mword 48 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0.
+
+Definition _set_SV48_Vaddr_bits
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 48)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_bits (v : SV48_Vaddr) (x : mword 48)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}.
+
+Definition _get_SV48_Vaddr_VPNi (v : SV48_Vaddr)
+: mword 27 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12.
+
+Definition _set_SV48_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 27)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_VPNi (v : SV48_Vaddr) (x : mword 27)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_SV48_Vaddr_PgOfs (v : SV48_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV48_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_PgOfs (v : SV48_Vaddr) (x : mword 12)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV48_Paddr (v : mword 56)
+: SV48_Paddr :=
+
+ {| SV48_Paddr_SV48_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}.
+
+Definition _get_SV48_Paddr_bits (v : SV48_Paddr)
+: mword 56 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0.
+
+Definition _set_SV48_Paddr_bits
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 56)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_bits (v : SV48_Paddr) (x : mword 56)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}.
+
+Definition _get_SV48_Paddr_PPNi (v : SV48_Paddr)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12.
+
+Definition _set_SV48_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_PPNi (v : SV48_Paddr) (x : mword 44)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV48_Paddr_PgOfs (v : SV48_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0.
+
+Definition _set_SV48_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_PgOfs (v : SV48_Paddr) (x : mword 12)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV48_PTE (v : mword 64)
+: SV48_PTE :=
+
+ {| SV48_PTE_SV48_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_SV48_PTE_bits (v : SV48_PTE)
+: mword 64 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 63 0.
+
+Definition _set_SV48_PTE_bits (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_bits (v : SV48_PTE) (x : mword 64)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_SV48_PTE_PPNi (v : SV48_PTE)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 53 10.
+
+Definition _set_SV48_PTE_PPNi (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 44)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_PPNi (v : SV48_PTE) (x : mword 44)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV48_PTE_RSW (v : SV48_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 9 8.
+
+Definition _set_SV48_PTE_RSW (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_RSW (v : SV48_PTE) (x : mword 2)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV48_PTE_BITS (v : SV48_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 7 0.
+
+Definition _set_SV48_PTE_BITS (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_BITS (v : SV48_PTE) (x : mword 8)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition make_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(asid : mword asidlen) (global : bool) (vAddr : mword valen) (pAddr : mword palen)
+(pte : mword ptelen) (level : Z) (pteAddr : mword palen) (levelBitSize : Z) `{ArithFact (valen > 0)}
+`{ArithFact (0 <= level)} `{ArithFact (0 <= levelBitSize)}
+: M (TLB_Entry asidlen valen palen ptelen) :=
+
+ let shift := Z.add PAGESIZE_BITS (Z.mul level levelBitSize) in
+ let vAddrMask : bits valen :=
+ sub_vec_int
+ (shiftl
+ (xor_vec vAddr (xor_vec vAddr (EXTZ (length_mword vAddr) (vec_of_bits [B1] : mword 1))))
+ shift) 1 in
+ let vMatchMask : bits valen := not_vec vAddrMask in
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm (({| TLB_Entry_asid := asid;
+ TLB_Entry_global := global;
+ TLB_Entry_pte := pte;
+ TLB_Entry_pteAddr := pteAddr;
+ TLB_Entry_vAddrMask := vAddrMask;
+ TLB_Entry_vMatchMask := vMatchMask;
+ TLB_Entry_vAddr := (and_vec vAddr vMatchMask);
+ TLB_Entry_pAddr := (shiftl (shiftr pAddr shift) shift);
+ TLB_Entry_age := w__0 |})
+ : TLB_Entry asidlen valen palen ptelen).
+
+Definition match_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(ent : TLB_Entry asidlen valen palen ptelen) (asid : mword asidlen) (vaddr : mword valen)
+: bool :=
+
+ andb (orb ent.(TLB_Entry_global) (eq_vec ent.(TLB_Entry_asid) asid))
+ (eq_vec ent.(TLB_Entry_vAddr) (and_vec ent.(TLB_Entry_vMatchMask) vaddr)).
+
+Definition flush_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(e : TLB_Entry asidlen valen palen ptelen) (asid : option (mword asidlen))
+(addr : option (mword valen))
+: bool :=
+
+ match (asid, addr) with
+ | (None, None) => true
+ | (None, Some (a)) => eq_vec e.(TLB_Entry_vAddr) (and_vec e.(TLB_Entry_vMatchMask) a)
+ | (Some (i), None) => andb (eq_vec e.(TLB_Entry_asid) i) (negb e.(TLB_Entry_global))
+ | (Some (i), Some (a)) =>
+ andb (eq_vec e.(TLB_Entry_asid) i)
+ (andb (eq_vec e.(TLB_Entry_vAddr) (and_vec a e.(TLB_Entry_vMatchMask)))
+ (negb e.(TLB_Entry_global)))
+ end.
+
+Definition to_phys_addr (a : mword 34) : mword 32 := subrange_vec_dec a 31 0.
+
+Fixpoint _rec_walk32
+(vaddr : mword 32) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool)
+(ptb : mword 34) (level : Z) (global : bool) (_reclimit : Z) `{ArithFact (0 <= level)}
+(_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M (PTW_Result (mword 34) SV32_PTE) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let va := Mk_SV32_Vaddr vaddr in
+ let pt_ofs : paddr32 :=
+ shiftl
+ (EXTZ 34
+ (subrange_vec_dec (shiftr (_get_SV32_Vaddr_VPNi va) (Z.mul level SV32_LEVEL_BITS))
+ (Z.sub SV32_LEVEL_BITS 1) 0)) PTE32_LOG_SIZE in
+ let pte_addr := add_vec ptb pt_ofs in
+ (mem_read ac (to_phys_addr pte_addr) 4 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 4)) =>
+ (match w__0 with
+ | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result (mword 34) SV32_PTE)
+ | MemValue (v) =>
+ let pte := Mk_SV32_PTE v in
+ let pbits := _get_SV32_PTE_BITS pte in
+ let pattr := Mk_PTE_Bits pbits in
+ let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in
+ (if ((isInvalidPTE pbits)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 34) SV32_PTE)
+ else if ((isPTEPtr pbits)) then
+ (if sumbool_of_bool ((Z.eqb level 0)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 34) SV32_PTE)
+ else
+ (_rec_walk32 vaddr ac priv mxr do_sum
+ (shiftl (EXTZ 34 (_get_SV32_PTE_PPNi pte)) PAGESIZE_BITS) (Z.sub level 1) is_global
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (PTW_Result (mword 34) SV32_PTE))
+ : M (PTW_Result (mword 34) SV32_PTE)
+ else
+ (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool =>
+ returnm ((if sumbool_of_bool ((negb w__3)) then PTW_Failure (PTW_No_Permission)
+ else if sumbool_of_bool ((Z.gtb level 0)) then
+ let mask :=
+ sub_vec_int
+ (shiftl
+ (xor_vec (_get_SV32_PTE_PPNi pte)
+ (xor_vec (_get_SV32_PTE_PPNi pte)
+ (EXTZ 22 (vec_of_bits [B1] : mword 1))))
+ (Z.mul level SV32_LEVEL_BITS)) 1 in
+ if ((neq_vec (and_vec (_get_SV32_PTE_PPNi pte) mask)
+ (EXTZ 22 (vec_of_bits [B0] : mword 1)))) then
+ PTW_Failure
+ (PTW_Misaligned)
+ else
+ let ppn :=
+ or_vec (_get_SV32_PTE_PPNi pte)
+ (and_vec (EXTZ 22 (_get_SV32_Vaddr_VPNi va)) mask) in
+ PTW_Success
+ ((concat_vec ppn (_get_SV32_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global))
+ else
+ PTW_Success
+ ((concat_vec (_get_SV32_PTE_PPNi pte) (_get_SV32_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global)))
+ : PTW_Result (mword 34) SV32_PTE))
+ : M (PTW_Result (mword 34) SV32_PTE)
+ end)
+ : M (PTW_Result (mword 34) SV32_PTE).
+
+Definition walk32
+(_arg0 : mword 32) (_arg1 : AccessType) (_arg2 : Privilege) (_arg3 : bool) (_arg4 : bool)
+(_arg5 : mword 34) (level : Z) (_arg7 : bool) `{ArithFact (0 <= level)}
+: M (PTW_Result (mword 34) SV32_PTE) :=
+
+ (_rec_walk32 _arg0 _arg1 _arg2 _arg3 _arg4 _arg5 level _arg7 (level : Z) (Zwf_guarded _))
+ : M (PTW_Result (mword 34) SV32_PTE).
+
+Definition lookup_TLB32 (asid : mword 9) (vaddr : mword 32)
+: M (option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 9 32 34 32))) :=
+
+ read_reg tlb32_ref >>= fun w__0 : option (TLB_Entry 9 32 34 32) =>
+ returnm ((match w__0 with
+ | None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((build_ex 0, e)) else None
+ end)
+ : option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 9 32 34 32))).
+
+Definition add_to_TLB32
+(asid : mword 9) (vAddr : mword 32) (pAddr : mword 34) (pte : SV32_PTE) (pteAddr : mword 34)
+(level : Z) (global : bool) `{ArithFact (0 <= level)}
+: M (unit) :=
+
+ (make_TLB_Entry asid global vAddr pAddr (_get_SV32_PTE_bits pte) level pteAddr SV32_LEVEL_BITS) >>= fun ent : TLB32_Entry =>
+ write_reg tlb32_ref (Some (ent))
+ : M (unit).
+
+Definition write_TLB32 (idx : Z) (ent : TLB_Entry 9 32 34 32) `{ArithFact (0 <= idx)}
+: M (unit) :=
+
+ write_reg tlb32_ref (Some (ent))
+ : M (unit).
+
+Definition flush_TLB32 (asid : option (mword 9)) (addr : option (mword 32))
+: M (unit) :=
+
+ read_reg tlb32_ref >>= fun w__0 : option (TLB_Entry 9 32 34 32) =>
+ (match w__0 with
+ | None => returnm (tt : unit)
+ | Some (e) =>
+ (if ((flush_TLB_Entry e asid addr)) then write_reg tlb32_ref None : M (unit)
+ else returnm (tt : unit))
+ : M (unit)
+ end)
+ : M (unit).
+
+Definition translate32
+(asid : mword 9) (ptb : mword 34) (vAddr : mword 32) (ac : AccessType) (priv : Privilege)
+(mxr : bool) (do_sum : bool) (level : Z) `{ArithFact (0 <= level)}
+: M (TR_Result (mword 34) PTW_Error) :=
+
+ (lookup_TLB32 asid vAddr) >>= fun w__0 : option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 9 32 34 32)) =>
+ (match w__0 with
+ | Some ((existT _ idx _, ent)) =>
+ let pte := Mk_SV32_PTE ent.(TLB_Entry_pte) in
+ let pteBits := Mk_PTE_Bits (_get_SV32_PTE_BITS pte) in
+ (checkPTEPermission ac priv mxr do_sum pteBits) >>= fun w__1 : bool =>
+ (if sumbool_of_bool ((negb w__1)) then
+ returnm ((TR_Failure
+ (PTW_No_Permission))
+ : TR_Result (mword 34) PTW_Error)
+ else
+ (match (update_PTE_Bits pteBits ac) with
+ | None =>
+ returnm ((TR_Address
+ (or_vec ent.(TLB_Entry_pAddr)
+ (EXTZ 34 (and_vec vAddr ent.(TLB_Entry_vAddrMask)))))
+ : TR_Result (mword 34) PTW_Error)
+ | Some (pbits) =>
+ (if ((negb (plat_enable_dirty_update tt))) then
+ returnm ((TR_Failure
+ (PTW_PTE_Update))
+ : TR_Result (mword 34) PTW_Error)
+ else
+ let n_pte := _update_SV32_PTE_BITS pte (_get_PTE_Bits_bits pbits) in
+ let n_ent : TLB32_Entry := ent in
+ let n_ent :=
+ {[ n_ent with TLB_Entry_pte := (_get_SV32_PTE_bits n_pte) ]}
+ : TLB_Entry 9 32 34 32 in
+ (write_TLB32 idx n_ent) >>
+ (mem_write_value (to_phys_addr (EXTZ 34 ent.(TLB_Entry_pteAddr))) 4
+ (_get_SV32_PTE_bits n_pte) false false false) >>= fun w__2 : MemoryOpResult bool =>
+ (match w__2 with
+ | MemValue (_) => returnm (tt : unit)
+ | MemException (e) =>
+ (internal_error "invalid physical address in TLB") : M (unit)
+ end) >>
+ returnm ((TR_Address
+ (or_vec ent.(TLB_Entry_pAddr)
+ (EXTZ 34 (and_vec vAddr ent.(TLB_Entry_vAddrMask)))))
+ : TR_Result (mword 34) PTW_Error))
+ : M (TR_Result (mword 34) PTW_Error)
+ end)
+ : M (TR_Result (mword 34) PTW_Error))
+ : M (TR_Result (mword 34) PTW_Error)
+ | None =>
+ (walk32 vAddr ac priv mxr do_sum ptb level false) >>= fun w__6 : PTW_Result (mword 34) SV32_PTE =>
+ (match w__6 with
+ | PTW_Failure (f) => returnm ((TR_Failure (f)) : TR_Result (mword 34) PTW_Error)
+ | PTW_Success ((pAddr, pte, pteAddr, existT _ level _, global)) =>
+ (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV32_PTE_BITS pte)) ac) with
+ | None =>
+ (add_to_TLB32 asid vAddr pAddr pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 34) PTW_Error)
+ | Some (pbits) =>
+ (if ((negb (plat_enable_dirty_update tt))) then
+ returnm ((TR_Failure
+ (PTW_PTE_Update))
+ : TR_Result (mword 34) PTW_Error)
+ else
+ let w_pte : SV32_PTE := _update_SV32_PTE_BITS pte (_get_PTE_Bits_bits pbits) in
+ (mem_write_value (to_phys_addr pteAddr) 4 (_get_SV32_PTE_bits w_pte) false false
+ false) >>= fun w__7 : MemoryOpResult bool =>
+ (match w__7 with
+ | MemValue (_) =>
+ (add_to_TLB32 asid vAddr pAddr w_pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 34) PTW_Error)
+ | MemException (e) =>
+ returnm ((TR_Failure (PTW_Access)) : TR_Result (mword 34) PTW_Error)
+ end)
+ : M (TR_Result (mword 34) PTW_Error))
+ : M (TR_Result (mword 34) PTW_Error)
+ end)
+ : M (TR_Result (mword 34) PTW_Error)
+ end)
+ : M (TR_Result (mword 34) PTW_Error)
+ end)
+ : M (TR_Result (mword 34) PTW_Error).
+
+Definition init_vmem_sv32 '(tt : unit) : M (unit) := write_reg tlb32_ref None : M (unit).
+
+Definition legalize_satp (a : Architecture) (o : mword 32) (v : mword 32)
+: mword 32 :=
+
+ legalize_satp32 a o v.
+
+Definition translationMode (priv : Privilege)
+: M (SATPMode) :=
+
+ (if ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))) then
+ returnm (Sbare
+ : SATPMode)
+ else
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ let arch := architecture (get_mstatus_SXL w__0) in
+ (match arch with
+ | Some (RV32) =>
+ ((read_reg satp_ref) : M (mword 32)) >>= fun w__1 : mword 32 =>
+ let s := Mk_Satp32 (subrange_vec_dec w__1 31 0) in
+ returnm ((if ((eq_vec (_get_Satp32_Mode s) ((bool_to_bits false) : mword 1))) then Sbare
+ else Sv32)
+ : SATPMode)
+ | _ => (internal_error "unsupported address translation arch") : M (SATPMode)
+ end)
+ : M (SATPMode))
+ : M (SATPMode).
+
+Definition translateAddr (vAddr : mword 32) (ac : AccessType)
+: M (TR_Result (mword 32) ExceptionType) :=
+
+ (match ac with
+ | Execute => read_reg cur_privilege_ref : M (Privilege)
+ | _ =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2)
+ : M (Privilege)
+ end) >>= fun effPriv : Privilege =>
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ let mxr : bool := eq_vec (_get_Mstatus_MXR w__4) ((bool_to_bits true) : mword 1) in
+ read_reg mstatus_ref >>= fun w__5 : Mstatus =>
+ let do_sum : bool := eq_vec (_get_Mstatus_SUM w__5) ((bool_to_bits true) : mword 1) in
+ (translationMode effPriv) >>= fun mode : SATPMode =>
+ ((read_reg satp_ref) : M (mword 32)) >>= fun w__6 : mword 32 =>
+ let asid := curAsid32 w__6 in
+ ((read_reg satp_ref) : M (mword 32)) >>= fun w__7 : mword 32 =>
+ let ptb := curPTB32 w__7 in
+ (match mode with
+ | Sbare => returnm ((TR_Address (vAddr)) : TR_Result (mword 32) ExceptionType)
+ | Sv32 =>
+ (translate32 asid ptb vAddr ac effPriv mxr do_sum (Z.sub SV32_LEVELS 1)) >>= fun w__8 : TR_Result (mword 34) PTW_Error =>
+ returnm ((match w__8 with
+ | TR_Address (pa) => TR_Address (to_phys_addr pa)
+ | TR_Failure (f) => TR_Failure (translationException ac f)
+ end)
+ : TR_Result (mword 32) ExceptionType)
+ | _ =>
+ (internal_error "unsupported address translation scheme")
+ : M (TR_Result (mword 32) ExceptionType)
+ end)
+ : M (TR_Result (mword 32) ExceptionType).
+
+Definition flush_TLB (asid_xlen : option (mword 32)) (addr_xlen : option (mword 32))
+: M (unit) :=
+
+ let asid : option asid32 :=
+ match asid_xlen with | None => None | Some (a) => Some (subrange_vec_dec a 8 0) end in
+ (flush_TLB32 asid addr_xlen)
+ : M (unit).
+
+Definition init_vmem '(tt : unit) : M (unit) := (init_vmem_sv32 tt) : M (unit).
+
+Definition encdec_uop_forwards (arg_ : uop)
+: mword 7 :=
+
+ match arg_ with
+ | RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7)
+ | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7)
+ end.
+
+Definition encdec_uop_backwards (arg_ : mword 7)
+: M (uop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then
+ returnm (RISCV_LUI
+ : uop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then
+ returnm (RISCV_AUIPC
+ : uop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (uop).
+
+Definition encdec_uop_forwards_matches (arg_ : uop)
+: bool :=
+
+ match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end.
+
+Definition encdec_uop_backwards_matches (arg_ : mword 7)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then true
+ else false.
+
+Definition utype_mnemonic_forwards (arg_ : uop)
+: string :=
+
+ match arg_ with | RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" end.
+
+Definition utype_mnemonic_backwards (arg_ : string)
+: M (uop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "lui")) then returnm (RISCV_LUI : uop)
+ else if ((generic_eq p0_ "auipc")) then returnm (RISCV_AUIPC : uop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (uop).
+
+Definition utype_mnemonic_forwards_matches (arg_ : uop)
+: bool :=
+
+ match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end.
+
+Definition utype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "lui")) then true
+ else if ((generic_eq p0_ "auipc")) then true
+ else false.
+
+Definition _s496_ (_s497_ : string)
+: option string :=
+
+ let _s498_ := _s497_ in
+ if ((string_startswith _s498_ "auipc")) then
+ match (string_drop _s498_ (projT1 (string_length "auipc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s492_ (_s493_ : string)
+: option string :=
+
+ let _s494_ := _s493_ in
+ if ((string_startswith _s494_ "lui")) then
+ match (string_drop _s494_ (projT1 (string_length "lui"))) with | s_ => Some (s_) end
+ else None.
+
+Definition utype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((uop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s495_ := arg_ in
+ (if ((match (_s492_ _s495_) with | Some (s_) => true | _ => false end)) then
+ (match (_s492_ _s495_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_LUI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((uop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s496_ _s495_) with | Some (s_) => true | _ => false end)) then
+ (match (_s496_ _s495_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_AUIPC, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((uop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((uop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_bop_forwards (arg_ : bop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_BEQ => (vec_of_bits [B0;B0;B0] : mword 3)
+ | RISCV_BNE => (vec_of_bits [B0;B0;B1] : mword 3)
+ | RISCV_BLT => (vec_of_bits [B1;B0;B0] : mword 3)
+ | RISCV_BGE => (vec_of_bits [B1;B0;B1] : mword 3)
+ | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : mword 3)
+ | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : mword 3)
+ end.
+
+Definition encdec_bop_backwards (arg_ : mword 3)
+: M (bop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (RISCV_BEQ : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (RISCV_BNE : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm (RISCV_BLT : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_BGE : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm (RISCV_BLTU : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm (RISCV_BGEU : bop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bop).
+
+Definition encdec_bop_forwards_matches (arg_ : bop)
+: bool :=
+
+ match arg_ with
+ | RISCV_BEQ => true
+ | RISCV_BNE => true
+ | RISCV_BLT => true
+ | RISCV_BGE => true
+ | RISCV_BLTU => true
+ | RISCV_BGEU => true
+ end.
+
+Definition encdec_bop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else false.
+
+Definition btype_mnemonic_forwards (arg_ : bop)
+: string :=
+
+ match arg_ with
+ | RISCV_BEQ => "beq"
+ | RISCV_BNE => "bne"
+ | RISCV_BLT => "blt"
+ | RISCV_BGE => "bge"
+ | RISCV_BLTU => "bltu"
+ | RISCV_BGEU => "bgeu"
+ end.
+
+Definition btype_mnemonic_backwards (arg_ : string)
+: M (bop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "beq")) then returnm (RISCV_BEQ : bop)
+ else if ((generic_eq p0_ "bne")) then returnm (RISCV_BNE : bop)
+ else if ((generic_eq p0_ "blt")) then returnm (RISCV_BLT : bop)
+ else if ((generic_eq p0_ "bge")) then returnm (RISCV_BGE : bop)
+ else if ((generic_eq p0_ "bltu")) then returnm (RISCV_BLTU : bop)
+ else if ((generic_eq p0_ "bgeu")) then returnm (RISCV_BGEU : bop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bop).
+
+Definition btype_mnemonic_forwards_matches (arg_ : bop)
+: bool :=
+
+ match arg_ with
+ | RISCV_BEQ => true
+ | RISCV_BNE => true
+ | RISCV_BLT => true
+ | RISCV_BGE => true
+ | RISCV_BLTU => true
+ | RISCV_BGEU => true
+ end.
+
+Definition btype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "beq")) then true
+ else if ((generic_eq p0_ "bne")) then true
+ else if ((generic_eq p0_ "blt")) then true
+ else if ((generic_eq p0_ "bge")) then true
+ else if ((generic_eq p0_ "bltu")) then true
+ else if ((generic_eq p0_ "bgeu")) then true
+ else false.
+
+Definition _s520_ (_s521_ : string)
+: option string :=
+
+ let _s522_ := _s521_ in
+ if ((string_startswith _s522_ "bgeu")) then
+ match (string_drop _s522_ (projT1 (string_length "bgeu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s516_ (_s517_ : string)
+: option string :=
+
+ let _s518_ := _s517_ in
+ if ((string_startswith _s518_ "bltu")) then
+ match (string_drop _s518_ (projT1 (string_length "bltu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s512_ (_s513_ : string)
+: option string :=
+
+ let _s514_ := _s513_ in
+ if ((string_startswith _s514_ "bge")) then
+ match (string_drop _s514_ (projT1 (string_length "bge"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s508_ (_s509_ : string)
+: option string :=
+
+ let _s510_ := _s509_ in
+ if ((string_startswith _s510_ "blt")) then
+ match (string_drop _s510_ (projT1 (string_length "blt"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s504_ (_s505_ : string)
+: option string :=
+
+ let _s506_ := _s505_ in
+ if ((string_startswith _s506_ "bne")) then
+ match (string_drop _s506_ (projT1 (string_length "bne"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s500_ (_s501_ : string)
+: option string :=
+
+ let _s502_ := _s501_ in
+ if ((string_startswith _s502_ "beq")) then
+ match (string_drop _s502_ (projT1 (string_length "beq"))) with | s_ => Some (s_) end
+ else None.
+
+Definition btype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((bop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s503_ := arg_ in
+ (if ((match (_s500_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s500_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BEQ, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s504_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s504_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BNE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s508_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s508_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BLT, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s512_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s512_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BGE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s516_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s516_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BLTU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s520_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s520_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BGEU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_iop_forwards (arg_ : iop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_ADDI => (vec_of_bits [B0;B0;B0] : mword 3)
+ | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : mword 3)
+ | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : mword 3)
+ | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : mword 3)
+ | RISCV_ORI => (vec_of_bits [B1;B1;B0] : mword 3)
+ | RISCV_XORI => (vec_of_bits [B1;B0;B0] : mword 3)
+ end.
+
+Definition encdec_iop_backwards (arg_ : mword 3)
+: M (iop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (RISCV_ADDI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm (RISCV_SLTI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm (RISCV_SLTIU : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm (RISCV_ANDI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm (RISCV_ORI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm (RISCV_XORI : iop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (iop).
+
+Definition encdec_iop_forwards_matches (arg_ : iop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDI => true
+ | RISCV_SLTI => true
+ | RISCV_SLTIU => true
+ | RISCV_ANDI => true
+ | RISCV_ORI => true
+ | RISCV_XORI => true
+ end.
+
+Definition encdec_iop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else false.
+
+Definition itype_mnemonic_forwards (arg_ : iop)
+: string :=
+
+ match arg_ with
+ | RISCV_ADDI => "addi"
+ | RISCV_SLTI => "slti"
+ | RISCV_SLTIU => "sltiu"
+ | RISCV_XORI => "xori"
+ | RISCV_ORI => "ori"
+ | RISCV_ANDI => "andi"
+ end.
+
+Definition itype_mnemonic_backwards (arg_ : string)
+: M (iop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "addi")) then returnm (RISCV_ADDI : iop)
+ else if ((generic_eq p0_ "slti")) then returnm (RISCV_SLTI : iop)
+ else if ((generic_eq p0_ "sltiu")) then returnm (RISCV_SLTIU : iop)
+ else if ((generic_eq p0_ "xori")) then returnm (RISCV_XORI : iop)
+ else if ((generic_eq p0_ "ori")) then returnm (RISCV_ORI : iop)
+ else if ((generic_eq p0_ "andi")) then returnm (RISCV_ANDI : iop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (iop).
+
+Definition itype_mnemonic_forwards_matches (arg_ : iop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDI => true
+ | RISCV_SLTI => true
+ | RISCV_SLTIU => true
+ | RISCV_XORI => true
+ | RISCV_ORI => true
+ | RISCV_ANDI => true
+ end.
+
+Definition itype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "addi")) then true
+ else if ((generic_eq p0_ "slti")) then true
+ else if ((generic_eq p0_ "sltiu")) then true
+ else if ((generic_eq p0_ "xori")) then true
+ else if ((generic_eq p0_ "ori")) then true
+ else if ((generic_eq p0_ "andi")) then true
+ else false.
+
+Definition _s544_ (_s545_ : string)
+: option string :=
+
+ let _s546_ := _s545_ in
+ if ((string_startswith _s546_ "andi")) then
+ match (string_drop _s546_ (projT1 (string_length "andi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s540_ (_s541_ : string)
+: option string :=
+
+ let _s542_ := _s541_ in
+ if ((string_startswith _s542_ "ori")) then
+ match (string_drop _s542_ (projT1 (string_length "ori"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s536_ (_s537_ : string)
+: option string :=
+
+ let _s538_ := _s537_ in
+ if ((string_startswith _s538_ "xori")) then
+ match (string_drop _s538_ (projT1 (string_length "xori"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s532_ (_s533_ : string)
+: option string :=
+
+ let _s534_ := _s533_ in
+ if ((string_startswith _s534_ "sltiu")) then
+ match (string_drop _s534_ (projT1 (string_length "sltiu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s528_ (_s529_ : string)
+: option string :=
+
+ let _s530_ := _s529_ in
+ if ((string_startswith _s530_ "slti")) then
+ match (string_drop _s530_ (projT1 (string_length "slti"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s524_ (_s525_ : string)
+: option string :=
+
+ let _s526_ := _s525_ in
+ if ((string_startswith _s526_ "addi")) then
+ match (string_drop _s526_ (projT1 (string_length "addi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition itype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((iop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s527_ := arg_ in
+ (if ((match (_s524_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s524_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADDI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s528_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s528_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s532_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s532_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTIU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s536_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s536_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_XORI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s540_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s540_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ORI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s544_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s544_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ANDI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((iop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_sop_forwards (arg_ : sop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_SLLI => (vec_of_bits [B0;B0;B1] : mword 3)
+ | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : mword 3)
+ | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : mword 3)
+ end.
+
+Definition encdec_sop_backwards (arg_ : mword 3)
+: M (sop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (RISCV_SLLI : sop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_SRLI : sop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition encdec_sop_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition encdec_sop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else false.
+
+Definition shiftiop_mnemonic_forwards (arg_ : sop)
+: string :=
+
+ match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end.
+
+Definition shiftiop_mnemonic_backwards (arg_ : string)
+: M (sop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slli")) then returnm (RISCV_SLLI : sop)
+ else if ((generic_eq p0_ "srli")) then returnm (RISCV_SRLI : sop)
+ else if ((generic_eq p0_ "srai")) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition shiftiop_mnemonic_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition shiftiop_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slli")) then true
+ else if ((generic_eq p0_ "srli")) then true
+ else if ((generic_eq p0_ "srai")) then true
+ else false.
+
+Definition _s556_ (_s557_ : string)
+: option string :=
+
+ let _s558_ := _s557_ in
+ if ((string_startswith _s558_ "srai")) then
+ match (string_drop _s558_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s552_ (_s553_ : string)
+: option string :=
+
+ let _s554_ := _s553_ in
+ if ((string_startswith _s554_ "srli")) then
+ match (string_drop _s554_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s548_ (_s549_ : string)
+: option string :=
+
+ let _s550_ := _s549_ in
+ if ((string_startswith _s550_ "slli")) then
+ match (string_drop _s550_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftiop_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s551_ := arg_ in
+ (if ((match (_s548_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s548_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s552_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s552_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s556_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s556_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition rtype_mnemonic_forwards (arg_ : rop)
+: string :=
+
+ match arg_ with
+ | RISCV_ADD => "add"
+ | RISCV_SLT => "slt"
+ | RISCV_SLTU => "sltu"
+ | RISCV_AND => "and"
+ | RISCV_OR => "or"
+ | RISCV_XOR => "xor"
+ | RISCV_SLL => "sll"
+ | RISCV_SRL => "srl"
+ | RISCV_SUB => "sub"
+ | RISCV_SRA => "sra"
+ end.
+
+Definition rtype_mnemonic_backwards (arg_ : string)
+: M (rop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "add")) then returnm (RISCV_ADD : rop)
+ else if ((generic_eq p0_ "slt")) then returnm (RISCV_SLT : rop)
+ else if ((generic_eq p0_ "sltu")) then returnm (RISCV_SLTU : rop)
+ else if ((generic_eq p0_ "and")) then returnm (RISCV_AND : rop)
+ else if ((generic_eq p0_ "or")) then returnm (RISCV_OR : rop)
+ else if ((generic_eq p0_ "xor")) then returnm (RISCV_XOR : rop)
+ else if ((generic_eq p0_ "sll")) then returnm (RISCV_SLL : rop)
+ else if ((generic_eq p0_ "srl")) then returnm (RISCV_SRL : rop)
+ else if ((generic_eq p0_ "sub")) then returnm (RISCV_SUB : rop)
+ else if ((generic_eq p0_ "sra")) then returnm (RISCV_SRA : rop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (rop).
+
+Definition rtype_mnemonic_forwards_matches (arg_ : rop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADD => true
+ | RISCV_SLT => true
+ | RISCV_SLTU => true
+ | RISCV_AND => true
+ | RISCV_OR => true
+ | RISCV_XOR => true
+ | RISCV_SLL => true
+ | RISCV_SRL => true
+ | RISCV_SUB => true
+ | RISCV_SRA => true
+ end.
+
+Definition rtype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "add")) then true
+ else if ((generic_eq p0_ "slt")) then true
+ else if ((generic_eq p0_ "sltu")) then true
+ else if ((generic_eq p0_ "and")) then true
+ else if ((generic_eq p0_ "or")) then true
+ else if ((generic_eq p0_ "xor")) then true
+ else if ((generic_eq p0_ "sll")) then true
+ else if ((generic_eq p0_ "srl")) then true
+ else if ((generic_eq p0_ "sub")) then true
+ else if ((generic_eq p0_ "sra")) then true
+ else false.
+
+Definition _s596_ (_s597_ : string)
+: option string :=
+
+ let _s598_ := _s597_ in
+ if ((string_startswith _s598_ "sra")) then
+ match (string_drop _s598_ (projT1 (string_length "sra"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s592_ (_s593_ : string)
+: option string :=
+
+ let _s594_ := _s593_ in
+ if ((string_startswith _s594_ "sub")) then
+ match (string_drop _s594_ (projT1 (string_length "sub"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s588_ (_s589_ : string)
+: option string :=
+
+ let _s590_ := _s589_ in
+ if ((string_startswith _s590_ "srl")) then
+ match (string_drop _s590_ (projT1 (string_length "srl"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s584_ (_s585_ : string)
+: option string :=
+
+ let _s586_ := _s585_ in
+ if ((string_startswith _s586_ "sll")) then
+ match (string_drop _s586_ (projT1 (string_length "sll"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s580_ (_s581_ : string)
+: option string :=
+
+ let _s582_ := _s581_ in
+ if ((string_startswith _s582_ "xor")) then
+ match (string_drop _s582_ (projT1 (string_length "xor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s576_ (_s577_ : string)
+: option string :=
+
+ let _s578_ := _s577_ in
+ if ((string_startswith _s578_ "or")) then
+ match (string_drop _s578_ (projT1 (string_length "or"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s572_ (_s573_ : string)
+: option string :=
+
+ let _s574_ := _s573_ in
+ if ((string_startswith _s574_ "and")) then
+ match (string_drop _s574_ (projT1 (string_length "and"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s568_ (_s569_ : string)
+: option string :=
+
+ let _s570_ := _s569_ in
+ if ((string_startswith _s570_ "sltu")) then
+ match (string_drop _s570_ (projT1 (string_length "sltu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s564_ (_s565_ : string)
+: option string :=
+
+ let _s566_ := _s565_ in
+ if ((string_startswith _s566_ "slt")) then
+ match (string_drop _s566_ (projT1 (string_length "slt"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s560_ (_s561_ : string)
+: option string :=
+
+ let _s562_ := _s561_ in
+ if ((string_startswith _s562_ "add")) then
+ match (string_drop _s562_ (projT1 (string_length "add"))) with | s_ => Some (s_) end
+ else None.
+
+Definition rtype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((rop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s563_ := arg_ in
+ (if ((match (_s560_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s560_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s564_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s564_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLT, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s568_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s568_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s572_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s572_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_AND, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s576_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s576_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_OR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s580_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s580_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_XOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s584_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s584_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLL, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s588_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s588_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRL, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s592_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s592_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SUB, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s596_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s596_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRA, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((rop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition extend_value {n : Z} (is_unsigned : bool) (value : MemoryOpResult (mword (8 * n)))
+`{ArithFact (0 < n /\ n <= 4)}
+: MemoryOpResult (mword 32) :=
+
+ match value with
+ | MemValue (v) =>
+ MemValue (if sumbool_of_bool (is_unsigned) then EXTZ 32 v else (EXTS 32 v) : xlenbits)
+ | MemException (e) => MemException (e)
+ end.
+
+Definition process_load {n : Z}
+(rd : mword 5) (addr : mword 32) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool)
+`{ArithFact (0 < n /\ n <= 4)}
+: M (Retired) :=
+
+ (match (extend_value is_unsigned value) with
+ | MemValue (result) =>
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ | MemException (e) => (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition check_misaligned (vaddr : mword 32) (width : word_width)
+: M (bool) :=
+
+ (if ((plat_enable_misaligned_access tt)) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else
+ (match width with
+ | BYTE =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | HALF =>
+ (bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__0 : bool =>
+ returnm ((Bool.eqb w__0 true)
+ : bool)
+ | WORD =>
+ (or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__1 : bool =>
+ returnm ((Bool.eqb w__1 true)
+ : bool))
+ ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__2 : bool =>
+ returnm ((Bool.eqb w__2 true)
+ : bool)))
+ : M (bool)
+ | DOUBLE =>
+ (or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__4 : bool =>
+ returnm ((Bool.eqb w__4 true)
+ : bool))
+ ((or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__5 : bool =>
+ returnm ((Bool.eqb w__5 true)
+ : bool))
+ ((bit_to_bool (access_vec_dec vaddr 2)) >>= fun w__6 : bool =>
+ returnm ((Bool.eqb w__6 true)
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ end)
+ : M (bool))
+ : M (bool).
+
+Definition maybe_aq_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => ".aq" | false => "" end.
+
+Definition maybe_aq_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ ".aq")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_aq_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_aq_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ ".aq")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s604_ (_s605_ : string)
+: option string :=
+
+ let _s606_ := _s605_ in
+ if ((string_startswith _s606_ "")) then
+ match (string_drop _s606_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s600_ (_s601_ : string)
+: option string :=
+
+ let _s602_ := _s601_ in
+ if ((string_startswith _s602_ ".aq")) then
+ match (string_drop _s602_ (projT1 (string_length ".aq"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_aq_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s603_ := arg_ in
+ (if ((match (_s600_ _s603_) with | Some (s_) => true | _ => false end)) then
+ (match (_s600_ _s603_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s604_ _s603_) with | Some (s_) => true | _ => false end)) then
+ (match (_s604_ _s603_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_rl_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => ".rl" | false => "" end.
+
+Definition maybe_rl_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ ".rl")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_rl_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_rl_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ ".rl")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s612_ (_s613_ : string)
+: option string :=
+
+ let _s614_ := _s613_ in
+ if ((string_startswith _s614_ "")) then
+ match (string_drop _s614_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s608_ (_s609_ : string)
+: option string :=
+
+ let _s610_ := _s609_ in
+ if ((string_startswith _s610_ ".rl")) then
+ match (string_drop _s610_ (projT1 (string_length ".rl"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_rl_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s611_ := arg_ in
+ (if ((match (_s608_ _s611_) with | Some (s_) => true | _ => false end)) then
+ (match (_s608_ _s611_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s612_ _s611_) with | Some (s_) => true | _ => false end)) then
+ (match (_s612_ _s611_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_u_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => "u" | false => "" end.
+
+Definition maybe_u_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "u")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_u_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_u_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "u")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s620_ (_s621_ : string)
+: option string :=
+
+ let _s622_ := _s621_ in
+ if ((string_startswith _s622_ "")) then
+ match (string_drop _s622_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s616_ (_s617_ : string)
+: option string :=
+
+ let _s618_ := _s617_ in
+ if ((string_startswith _s618_ "u")) then
+ match (string_drop _s618_ (projT1 (string_length "u"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_u_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s619_ := arg_ in
+ (if ((match (_s616_ _s619_) with | Some (s_) => true | _ => false end)) then
+ (match (_s616_ _s619_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s620_ _s619_) with | Some (s_) => true | _ => false end)) then
+ (match (_s620_ _s619_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition shiftw_mnemonic_forwards (arg_ : sop)
+: string :=
+
+ match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end.
+
+Definition shiftw_mnemonic_backwards (arg_ : string)
+: M (sop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slli")) then returnm (RISCV_SLLI : sop)
+ else if ((generic_eq p0_ "srli")) then returnm (RISCV_SRLI : sop)
+ else if ((generic_eq p0_ "srai")) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition shiftw_mnemonic_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition shiftw_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slli")) then true
+ else if ((generic_eq p0_ "srli")) then true
+ else if ((generic_eq p0_ "srai")) then true
+ else false.
+
+Definition _s632_ (_s633_ : string)
+: option string :=
+
+ let _s634_ := _s633_ in
+ if ((string_startswith _s634_ "srai")) then
+ match (string_drop _s634_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s628_ (_s629_ : string)
+: option string :=
+
+ let _s630_ := _s629_ in
+ if ((string_startswith _s630_ "srli")) then
+ match (string_drop _s630_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s624_ (_s625_ : string)
+: option string :=
+
+ let _s626_ := _s625_ in
+ if ((string_startswith _s626_ "slli")) then
+ match (string_drop _s626_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftw_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s627_ := arg_ in
+ (if ((match (_s624_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s624_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s628_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s628_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s632_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s632_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition rtypew_mnemonic_forwards (arg_ : ropw)
+: string :=
+
+ match arg_ with
+ | RISCV_ADDW => "addw"
+ | RISCV_SUBW => "subw"
+ | RISCV_SLLW => "sllw"
+ | RISCV_SRLW => "srlw"
+ | RISCV_SRAW => "sraw"
+ end.
+
+Definition rtypew_mnemonic_backwards (arg_ : string)
+: M (ropw) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "addw")) then returnm (RISCV_ADDW : ropw)
+ else if ((generic_eq p0_ "subw")) then returnm (RISCV_SUBW : ropw)
+ else if ((generic_eq p0_ "sllw")) then returnm (RISCV_SLLW : ropw)
+ else if ((generic_eq p0_ "srlw")) then returnm (RISCV_SRLW : ropw)
+ else if ((generic_eq p0_ "sraw")) then returnm (RISCV_SRAW : ropw)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (ropw).
+
+Definition rtypew_mnemonic_forwards_matches (arg_ : ropw)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDW => true
+ | RISCV_SUBW => true
+ | RISCV_SLLW => true
+ | RISCV_SRLW => true
+ | RISCV_SRAW => true
+ end.
+
+Definition rtypew_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "addw")) then true
+ else if ((generic_eq p0_ "subw")) then true
+ else if ((generic_eq p0_ "sllw")) then true
+ else if ((generic_eq p0_ "srlw")) then true
+ else if ((generic_eq p0_ "sraw")) then true
+ else false.
+
+Definition _s652_ (_s653_ : string)
+: option string :=
+
+ let _s654_ := _s653_ in
+ if ((string_startswith _s654_ "sraw")) then
+ match (string_drop _s654_ (projT1 (string_length "sraw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s648_ (_s649_ : string)
+: option string :=
+
+ let _s650_ := _s649_ in
+ if ((string_startswith _s650_ "srlw")) then
+ match (string_drop _s650_ (projT1 (string_length "srlw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s644_ (_s645_ : string)
+: option string :=
+
+ let _s646_ := _s645_ in
+ if ((string_startswith _s646_ "sllw")) then
+ match (string_drop _s646_ (projT1 (string_length "sllw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s640_ (_s641_ : string)
+: option string :=
+
+ let _s642_ := _s641_ in
+ if ((string_startswith _s642_ "subw")) then
+ match (string_drop _s642_ (projT1 (string_length "subw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s636_ (_s637_ : string)
+: option string :=
+
+ let _s638_ := _s637_ in
+ if ((string_startswith _s638_ "addw")) then
+ match (string_drop _s638_ (projT1 (string_length "addw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition rtypew_mnemonic_matches_prefix (arg_ : string)
+: M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s639_ := arg_ in
+ (if ((match (_s636_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s636_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADDW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s640_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s640_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SUBW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s644_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s644_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s648_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s648_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s652_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s652_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((ropw * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))).
+
+Definition shiftiwop_mnemonic_forwards (arg_ : sopw)
+: string :=
+
+ match arg_ with | RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" end.
+
+Definition shiftiwop_mnemonic_backwards (arg_ : string)
+: M (sopw) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slliw")) then returnm (RISCV_SLLIW : sopw)
+ else if ((generic_eq p0_ "srliw")) then returnm (RISCV_SRLIW : sopw)
+ else if ((generic_eq p0_ "sraiw")) then returnm (RISCV_SRAIW : sopw)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sopw).
+
+Definition shiftiwop_mnemonic_forwards_matches (arg_ : sopw)
+: bool :=
+
+ match arg_ with | RISCV_SLLIW => true | RISCV_SRLIW => true | RISCV_SRAIW => true end.
+
+Definition shiftiwop_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slliw")) then true
+ else if ((generic_eq p0_ "srliw")) then true
+ else if ((generic_eq p0_ "sraiw")) then true
+ else false.
+
+Definition _s664_ (_s665_ : string)
+: option string :=
+
+ let _s666_ := _s665_ in
+ if ((string_startswith _s666_ "sraiw")) then
+ match (string_drop _s666_ (projT1 (string_length "sraiw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s660_ (_s661_ : string)
+: option string :=
+
+ let _s662_ := _s661_ in
+ if ((string_startswith _s662_ "srliw")) then
+ match (string_drop _s662_ (projT1 (string_length "srliw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s656_ (_s657_ : string)
+: option string :=
+
+ let _s658_ := _s657_ in
+ if ((string_startswith _s658_ "slliw")) then
+ match (string_drop _s658_ (projT1 (string_length "slliw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftiwop_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s659_ := arg_ in
+ (if ((match (_s656_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s656_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s660_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s660_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s664_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s664_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sopw * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_r_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("r" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_r_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "r")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_r_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_r_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "r")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s672_ (_s673_ : string)
+: option string :=
+
+ let _s674_ := _s673_ in
+ if ((string_startswith _s674_ "")) then
+ match (string_drop _s674_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s668_ (_s669_ : string)
+: option string :=
+
+ let _s670_ := _s669_ in
+ if ((string_startswith _s670_ "r")) then
+ match (string_drop _s670_ (projT1 (string_length "r"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_r_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s671_ := arg_ in
+ (if ((match (_s668_ _s671_) with | Some (s_) => true | _ => false end)) then
+ (match (_s668_ _s671_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s672_ _s671_) with | Some (s_) => true | _ => false end)) then
+ (match (_s672_ _s671_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_w_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("w" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_w_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "w")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_w_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_w_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "w")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s680_ (_s681_ : string)
+: option string :=
+
+ let _s682_ := _s681_ in
+ if ((string_startswith _s682_ "")) then
+ match (string_drop _s682_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s676_ (_s677_ : string)
+: option string :=
+
+ let _s678_ := _s677_ in
+ if ((string_startswith _s678_ "w")) then
+ match (string_drop _s678_ (projT1 (string_length "w"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_w_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s679_ := arg_ in
+ (if ((match (_s676_ _s679_) with | Some (s_) => true | _ => false end)) then
+ (match (_s676_ _s679_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s680_ _s679_) with | Some (s_) => true | _ => false end)) then
+ (match (_s680_ _s679_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_i_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("i" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_i_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "i")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_i_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_i_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "i")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s688_ (_s689_ : string)
+: option string :=
+
+ let _s690_ := _s689_ in
+ if ((string_startswith _s690_ "")) then
+ match (string_drop _s690_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s684_ (_s685_ : string)
+: option string :=
+
+ let _s686_ := _s685_ in
+ if ((string_startswith _s686_ "i")) then
+ match (string_drop _s686_ (projT1 (string_length "i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_i_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s687_ := arg_ in
+ (if ((match (_s684_ _s687_) with | Some (s_) => true | _ => false end)) then
+ (match (_s684_ _s687_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s688_ _s687_) with | Some (s_) => true | _ => false end)) then
+ (match (_s688_ _s687_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_o_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("o" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_o_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "o")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_o_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_o_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "o")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s696_ (_s697_ : string)
+: option string :=
+
+ let _s698_ := _s697_ in
+ if ((string_startswith _s698_ "")) then
+ match (string_drop _s698_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s692_ (_s693_ : string)
+: option string :=
+
+ let _s694_ := _s693_ in
+ if ((string_startswith _s694_ "o")) then
+ match (string_drop _s694_ (projT1 (string_length "o"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_o_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s695_ := arg_ in
+ (if ((match (_s692_ _s695_) with | Some (s_) => true | _ => false end)) then
+ (match (_s692_ _s695_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s696_ _s695_) with | Some (s_) => true | _ => false end)) then
+ (match (_s696_ _s695_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition fence_bits_forwards (arg_ : mword 4)
+: M (string) :=
+
+ (match arg_ with
+ | v__0 =>
+ let i : bits 1 := subrange_vec_dec v__0 3 3 in
+ let w : bits 1 := subrange_vec_dec v__0 0 0 in
+ let r : bits 1 := subrange_vec_dec v__0 1 1 in
+ let o : bits 1 := subrange_vec_dec v__0 2 2 in
+ let i : bits 1 := subrange_vec_dec v__0 3 3 in
+ (bit_maybe_i_forwards i) >>= fun w__0 : string =>
+ (bit_maybe_o_forwards o) >>= fun w__1 : string =>
+ (bit_maybe_r_forwards r) >>= fun w__2 : string =>
+ (bit_maybe_w_forwards w) >>= fun w__3 : string =>
+ returnm ((string_append w__0
+ (string_append w__1 (string_append w__2 (string_append w__3 ""))))
+ : string)
+ end)
+ : M (string).
+
+Definition _s700_ (_s701_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) :=
+
+ (match _s701_ with
+ | _s702_ =>
+ (bit_maybe_i_matches_prefix _s702_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s703_ _)) =>
+ (match (string_drop _s702_ _s703_) with
+ | _s704_ =>
+ (bit_maybe_o_matches_prefix _s704_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s705_ _)) =>
+ (match (string_drop _s704_ _s705_) with
+ | _s706_ =>
+ (bit_maybe_r_matches_prefix _s706_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s707_ _)) =>
+ (match (string_drop _s706_ _s707_) with
+ | _s708_ =>
+ (bit_maybe_w_matches_prefix _s708_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s709_ _)) =>
+ let p0_ := string_drop _s708_ _s709_ in
+ if ((generic_eq p0_ "")) then Some ((i, o, r, w))
+ else None
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1))).
+
+Definition fence_bits_backwards (arg_ : string)
+: M (mword 4) :=
+
+ let _s710_ := arg_ in
+ (_s700_ _s710_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (if ((match w__0 with | Some ((i, o, r, w)) => true | _ => false end)) then
+ (_s700_ _s710_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (match w__1 with
+ | Some ((i, o, r, w)) =>
+ returnm ((concat_vec (i : bits 1)
+ (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))))
+ : mword (1 + (1 + (1 + 1))))
+ | _ => exit tt : M (mword 4)
+ end)
+ : M (mword 4)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 4).
+
+Definition fence_bits_forwards_matches (arg_ : mword 4)
+: bool :=
+
+ match arg_ with | v__1 => true end.
+
+Definition _s711_ (_s712_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) :=
+
+ (match _s712_ with
+ | _s713_ =>
+ (bit_maybe_i_matches_prefix _s713_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s714_ _)) =>
+ (match (string_drop _s713_ _s714_) with
+ | _s715_ =>
+ (bit_maybe_o_matches_prefix _s715_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s716_ _)) =>
+ (match (string_drop _s715_ _s716_) with
+ | _s717_ =>
+ (bit_maybe_r_matches_prefix _s717_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s718_ _)) =>
+ (match (string_drop _s717_ _s718_) with
+ | _s719_ =>
+ (bit_maybe_w_matches_prefix _s719_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s720_ _)) =>
+ let p0_ := string_drop _s719_ _s720_ in
+ if ((generic_eq p0_ "")) then Some ((i, o, r, w))
+ else None
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1))).
+
+Definition fence_bits_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s721_ := arg_ in
+ (_s711_ _s721_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (if ((match w__0 with | Some ((i, o, r, w)) => true | _ => false end)) then
+ (_s711_ _s721_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (match w__1 with
+ | Some ((i, o, r, w)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition _s722_ (_s723_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) :=
+
+ (match _s723_ with
+ | _s724_ =>
+ (bit_maybe_i_matches_prefix _s724_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s725_ _)) =>
+ (match (string_drop _s724_ _s725_) with
+ | _s726_ =>
+ (bit_maybe_o_matches_prefix _s726_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s727_ _)) =>
+ (match (string_drop _s726_ _s727_) with
+ | _s728_ =>
+ (bit_maybe_r_matches_prefix _s728_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s729_ _)) =>
+ (match (string_drop _s728_ _s729_) with
+ | _s730_ =>
+ (bit_maybe_w_matches_prefix _s730_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s731_ _)) =>
+ match (string_drop _s730_ _s731_) with
+ | s_ => Some ((i, o, r, w, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))).
+
+Definition fence_bits_matches_prefix (arg_ : string)
+: M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s732_ := arg_ in
+ (_s722_ _s732_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) =>
+ (if ((match w__0 with | Some ((i, o, r, w, s_)) => true | _ => false end)) then
+ (_s722_ _s732_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) =>
+ (match w__1 with
+ | Some ((i, o, r, w, s_)) =>
+ returnm ((Some
+ ((concat_vec (i : bits 1)
+ (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 4 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition aqrl_str (aq : bool) (rl : bool)
+: string :=
+
+ match (aq, rl) with
+ | (false, false) => ""
+ | (false, true) => ".rl"
+ | (true, false) => ".aq"
+ | (true, true) => ".aqrl"
+ end.
+
+Definition lrsc_width_str (width : word_width)
+: string :=
+
+ match width with | BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" end.
+
+Definition process_loadres {n : Z}
+(rd : mword 5) (addr : mword 32) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool)
+`{ArithFact (0 < n /\ n <= 4)}
+: M (Retired) :=
+
+ (match (extend_value is_unsigned value) with
+ | MemValue (result) =>
+ let '_ := (load_reservation addr) : unit in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ | MemException (e) => (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition encdec_amoop_forwards (arg_ : amoop)
+: mword 5 :=
+
+ match arg_ with
+ | AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)
+ | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)
+ | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)
+ | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)
+ | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)
+ | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)
+ | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : mword 5)
+ | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : mword 5)
+ end.
+
+Definition encdec_amoop_backwards (arg_ : mword 5)
+: M (amoop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm (AMOSWAP : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (AMOADD : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm (AMOXOR : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm (AMOAND : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm (AMOOR : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm (AMOMIN : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm (AMOMAX : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then
+ returnm (AMOMINU
+ : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then
+ returnm (AMOMAXU
+ : amoop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (amoop).
+
+Definition encdec_amoop_forwards_matches (arg_ : amoop)
+: bool :=
+
+ match arg_ with
+ | AMOSWAP => true
+ | AMOADD => true
+ | AMOXOR => true
+ | AMOAND => true
+ | AMOOR => true
+ | AMOMIN => true
+ | AMOMAX => true
+ | AMOMINU => true
+ | AMOMAXU => true
+ end.
+
+Definition encdec_amoop_backwards_matches (arg_ : mword 5)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then true
+ else false.
+
+Definition amo_mnemonic_forwards (arg_ : amoop)
+: string :=
+
+ match arg_ with
+ | AMOSWAP => "amoswap"
+ | AMOADD => "amoadd"
+ | AMOXOR => "amoxor"
+ | AMOAND => "amoand"
+ | AMOOR => "amoor"
+ | AMOMIN => "amomin"
+ | AMOMAX => "amomax"
+ | AMOMINU => "amominu"
+ | AMOMAXU => "amomaxu"
+ end.
+
+Definition amo_mnemonic_backwards (arg_ : string)
+: M (amoop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "amoswap")) then returnm (AMOSWAP : amoop)
+ else if ((generic_eq p0_ "amoadd")) then returnm (AMOADD : amoop)
+ else if ((generic_eq p0_ "amoxor")) then returnm (AMOXOR : amoop)
+ else if ((generic_eq p0_ "amoand")) then returnm (AMOAND : amoop)
+ else if ((generic_eq p0_ "amoor")) then returnm (AMOOR : amoop)
+ else if ((generic_eq p0_ "amomin")) then returnm (AMOMIN : amoop)
+ else if ((generic_eq p0_ "amomax")) then returnm (AMOMAX : amoop)
+ else if ((generic_eq p0_ "amominu")) then returnm (AMOMINU : amoop)
+ else if ((generic_eq p0_ "amomaxu")) then returnm (AMOMAXU : amoop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (amoop).
+
+Definition amo_mnemonic_forwards_matches (arg_ : amoop)
+: bool :=
+
+ match arg_ with
+ | AMOSWAP => true
+ | AMOADD => true
+ | AMOXOR => true
+ | AMOAND => true
+ | AMOOR => true
+ | AMOMIN => true
+ | AMOMAX => true
+ | AMOMINU => true
+ | AMOMAXU => true
+ end.
+
+Definition amo_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "amoswap")) then true
+ else if ((generic_eq p0_ "amoadd")) then true
+ else if ((generic_eq p0_ "amoxor")) then true
+ else if ((generic_eq p0_ "amoand")) then true
+ else if ((generic_eq p0_ "amoor")) then true
+ else if ((generic_eq p0_ "amomin")) then true
+ else if ((generic_eq p0_ "amomax")) then true
+ else if ((generic_eq p0_ "amominu")) then true
+ else if ((generic_eq p0_ "amomaxu")) then true
+ else false.
+
+Definition _s765_ (_s766_ : string)
+: option string :=
+
+ let _s767_ := _s766_ in
+ if ((string_startswith _s767_ "amomaxu")) then
+ match (string_drop _s767_ (projT1 (string_length "amomaxu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s761_ (_s762_ : string)
+: option string :=
+
+ let _s763_ := _s762_ in
+ if ((string_startswith _s763_ "amominu")) then
+ match (string_drop _s763_ (projT1 (string_length "amominu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s757_ (_s758_ : string)
+: option string :=
+
+ let _s759_ := _s758_ in
+ if ((string_startswith _s759_ "amomax")) then
+ match (string_drop _s759_ (projT1 (string_length "amomax"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s753_ (_s754_ : string)
+: option string :=
+
+ let _s755_ := _s754_ in
+ if ((string_startswith _s755_ "amomin")) then
+ match (string_drop _s755_ (projT1 (string_length "amomin"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s749_ (_s750_ : string)
+: option string :=
+
+ let _s751_ := _s750_ in
+ if ((string_startswith _s751_ "amoor")) then
+ match (string_drop _s751_ (projT1 (string_length "amoor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s745_ (_s746_ : string)
+: option string :=
+
+ let _s747_ := _s746_ in
+ if ((string_startswith _s747_ "amoand")) then
+ match (string_drop _s747_ (projT1 (string_length "amoand"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s741_ (_s742_ : string)
+: option string :=
+
+ let _s743_ := _s742_ in
+ if ((string_startswith _s743_ "amoxor")) then
+ match (string_drop _s743_ (projT1 (string_length "amoxor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s737_ (_s738_ : string)
+: option string :=
+
+ let _s739_ := _s738_ in
+ if ((string_startswith _s739_ "amoadd")) then
+ match (string_drop _s739_ (projT1 (string_length "amoadd"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s733_ (_s734_ : string)
+: option string :=
+
+ let _s735_ := _s734_ in
+ if ((string_startswith _s735_ "amoswap")) then
+ match (string_drop _s735_ (projT1 (string_length "amoswap"))) with | s_ => Some (s_) end
+ else None.
+
+Definition amo_mnemonic_matches_prefix (arg_ : string)
+: M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s736_ := arg_ in
+ (if ((match (_s733_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s733_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOSWAP, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s737_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s737_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOADD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s741_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s741_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOXOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s745_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s745_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOAND, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s749_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s749_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s753_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s753_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMIN, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s757_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s757_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMAX, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s761_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s761_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMINU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s765_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s765_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMAXU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((amoop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_mul_op_forwards (arg_ : (bool * bool * bool))
+: M (mword 3) :=
+
+ (match arg_ with
+ | (false, true, true) => returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3)
+ | (true, true, true) => returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3)
+ | (true, true, false) => returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3)
+ | (true, false, false) => returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3)
+ | _ => exit tt : M (mword 3)
+ end)
+ : M (mword 3).
+
+Definition encdec_mul_op_backwards (arg_ : mword 3)
+: M ((bool * bool * bool)) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (false, true, true)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (true, true, true)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm (true, true, false)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm (true, false, false)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M ((bool * bool * bool)).
+
+Definition encdec_mul_op_forwards_matches (arg_ : (bool * bool * bool))
+: bool :=
+
+ match arg_ with
+ | (false, true, true) => true
+ | (true, true, true) => true
+ | (true, true, false) => true
+ | (true, false, false) => true
+ | _ => false
+ end.
+
+Definition encdec_mul_op_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else false.
+
+Definition mul_mnemonic_forwards (arg_ : (bool * bool * bool))
+: M (string) :=
+
+ (match arg_ with
+ | (false, true, true) => returnm ("mul" : string)
+ | (true, true, true) => returnm ("mulh" : string)
+ | (true, true, false) => returnm ("mulhsu" : string)
+ | (true, false, false) => returnm ("mulhu" : string)
+ | _ => exit tt : M (string)
+ end)
+ : M (string).
+
+Definition mul_mnemonic_backwards (arg_ : string)
+: M ((bool * bool * bool)) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "mul")) then returnm (false, true, true)
+ else if ((generic_eq p0_ "mulh")) then returnm (true, true, true)
+ else if ((generic_eq p0_ "mulhsu")) then returnm (true, true, false)
+ else if ((generic_eq p0_ "mulhu")) then returnm (true, false, false)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M ((bool * bool * bool)).
+
+Definition mul_mnemonic_forwards_matches (arg_ : (bool * bool * bool))
+: bool :=
+
+ match arg_ with
+ | (false, true, true) => true
+ | (true, true, true) => true
+ | (true, true, false) => true
+ | (true, false, false) => true
+ | _ => false
+ end.
+
+Definition mul_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "mul")) then true
+ else if ((generic_eq p0_ "mulh")) then true
+ else if ((generic_eq p0_ "mulhsu")) then true
+ else if ((generic_eq p0_ "mulhu")) then true
+ else false.
+
+Definition _s781_ (_s782_ : string)
+: option string :=
+
+ let _s783_ := _s782_ in
+ if ((string_startswith _s783_ "mulhu")) then
+ match (string_drop _s783_ (projT1 (string_length "mulhu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s777_ (_s778_ : string)
+: option string :=
+
+ let _s779_ := _s778_ in
+ if ((string_startswith _s779_ "mulhsu")) then
+ match (string_drop _s779_ (projT1 (string_length "mulhsu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s773_ (_s774_ : string)
+: option string :=
+
+ let _s775_ := _s774_ in
+ if ((string_startswith _s775_ "mulh")) then
+ match (string_drop _s775_ (projT1 (string_length "mulh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s769_ (_s770_ : string)
+: option string :=
+
+ let _s771_ := _s770_ in
+ if ((string_startswith _s771_ "mul")) then
+ match (string_drop _s771_ (projT1 (string_length "mul"))) with | s_ => Some (s_) end
+ else None.
+
+Definition mul_mnemonic_matches_prefix (arg_ : string)
+: M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s772_ := arg_ in
+ (if ((match (_s769_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s769_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((false, true, true), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s773_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s773_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, true, true), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s777_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s777_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, true, false), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s781_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s781_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, false, false), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))))
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_not_u_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | false => "u" | true => "" end.
+
+Definition maybe_not_u_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "u")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_not_u_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | false => true | true => true end.
+
+Definition maybe_not_u_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "u")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s789_ (_s790_ : string)
+: option string :=
+
+ let _s791_ := _s790_ in
+ if ((string_startswith _s791_ "")) then
+ match (string_drop _s791_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s785_ (_s786_ : string)
+: option string :=
+
+ let _s787_ := _s786_ in
+ if ((string_startswith _s787_ "u")) then
+ match (string_drop _s787_ (projT1 (string_length "u"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_not_u_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s788_ := arg_ in
+ (if ((match (_s785_ _s788_) with | Some (s_) => true | _ => false end)) then
+ (match (_s785_ _s788_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s789_ _s788_) with | Some (s_) => true | _ => false end)) then
+ (match (_s789_ _s788_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_csrop_forwards (arg_ : csrop)
+: mword 2 :=
+
+ match arg_ with
+ | CSRRW => (vec_of_bits [B0;B1] : mword 2)
+ | CSRRS => (vec_of_bits [B1;B0] : mword 2)
+ | CSRRC => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition encdec_csrop_backwards (arg_ : mword 2)
+: M (csrop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (CSRRW : csrop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (CSRRS : csrop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (CSRRC : csrop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (csrop).
+
+Definition encdec_csrop_forwards_matches (arg_ : csrop)
+: bool :=
+
+ match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end.
+
+Definition encdec_csrop_backwards_matches (arg_ : mword 2)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true
+ else false.
+
+Definition readCSR (csr : mword 12)
+: M (mword 32) :=
+
+ (match (csr, 32) with
+ | (b__0, g__217) =>
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg mvendorid_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ returnm ((EXTZ 32 w__0)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg marchid_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg mimpid_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ ((read_reg mhartid_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ returnm ((_get_Mstatus_bits w__4)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg misa_ref >>= fun w__5 : Misa => returnm ((_get_Misa_bits w__5) : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg medeleg_ref >>= fun w__6 : Medeleg =>
+ returnm ((_get_Medeleg_bits w__6)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg mideleg_ref >>= fun w__7 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__7)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__8 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__8)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_mtvec tt)
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__10 : Counteren =>
+ returnm ((EXTZ 32 (_get_Counteren_bits w__10))
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mscratch_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target Machine) >>= fun w__12 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__13 : mword 32 =>
+ returnm ((and_vec w__12 w__13)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg mcause_ref >>= fun w__14 : Mcause =>
+ returnm ((_get_Mcause_bits w__14)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg mtval_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__16 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__16)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ (pmpReadCfgReg 0)
+ : M (mword 32)
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]
+ : mword 12)) (Z.eqb g__217 32))) then
+ (pmpReadCfgReg 1)
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ (pmpReadCfgReg 2)
+ : M (mword 32)
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]
+ : mword 12)) (Z.eqb g__217 32))) then
+ (pmpReadCfgReg 3)
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr0_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr1_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr2_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr3_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr4_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr5_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr6_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr7_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr8_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr9_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr10_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr11_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr12_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr13_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr14_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr15_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__37 : mword 64 =>
+ returnm ((subrange_vec_dec w__37 (Z.sub 32 1) 0)
+ : mword (31 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__38 : mword 64 =>
+ returnm ((subrange_vec_dec w__38 (Z.sub 32 1) 0)
+ : mword (31 - 0 + 1))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]
+ : mword 12)) (Z.eqb g__217 32))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__39 : mword 64 =>
+ returnm ((subrange_vec_dec w__39 63 32)
+ : mword (63 - 32 + 1))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]
+ : mword 12)) (Z.eqb g__217 32))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__40 : mword 64 =>
+ returnm ((subrange_vec_dec w__40 63 32)
+ : mword (63 - 32 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg tselect_ref) : M (mword 32)) >>= fun w__41 : mword 32 =>
+ returnm ((not_vec w__41)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__42 : Mstatus =>
+ returnm ((_get_Sstatus_bits (lower_mstatus w__42))
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg sedeleg_ref >>= fun w__43 : Sedeleg =>
+ returnm ((_get_Sedeleg_bits w__43)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg sideleg_ref >>= fun w__44 : Sinterrupts =>
+ returnm ((_get_Sinterrupts_bits w__44)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__45 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__46 : Minterrupts =>
+ returnm ((_get_Sinterrupts_bits (lower_mie w__45 w__46))
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_stvec tt)
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg scounteren_ref >>= fun w__48 : Counteren =>
+ returnm ((EXTZ 32 (_get_Counteren_bits w__48))
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg sscratch_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target Supervisor) >>= fun w__50 : mword 32 =>
+ (pc_alignment_mask tt) >>= fun w__51 : mword 32 =>
+ returnm ((and_vec w__50 w__51)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg scause_ref >>= fun w__52 : Mcause =>
+ returnm ((_get_Mcause_bits w__52)
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg stval_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__54 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__55 : Minterrupts =>
+ returnm ((_get_Sinterrupts_bits (lower_mip w__54 w__55))
+ : mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg satp_ref) : M (mword 32))
+ : M (mword 32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__57 : mword 64 =>
+ returnm ((subrange_vec_dec w__57 (Z.sub 32 1) 0)
+ : mword (31 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__58 : mword 64 =>
+ returnm ((subrange_vec_dec w__58 (Z.sub 32 1) 0)
+ : mword (31 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__59 : mword 64 =>
+ returnm ((subrange_vec_dec w__59 (Z.sub 32 1) 0)
+ : mword (31 - 0 + 1))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]
+ : mword 12)) (Z.eqb g__217 32))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__60 : mword 64 =>
+ returnm ((subrange_vec_dec w__60 63 32)
+ : mword (63 - 32 + 1))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]
+ : mword 12)) (Z.eqb g__217 32))) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__61 : mword 64 =>
+ returnm ((subrange_vec_dec w__61 63 32)
+ : mword (63 - 32 + 1))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]
+ : mword 12)) (Z.eqb g__217 32))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__62 : mword 64 =>
+ returnm ((subrange_vec_dec w__62 63 32)
+ : mword (63 - 32 + 1))
+ else
+ (ext_read_CSR csr) >>= fun w__63 : option (mword 32) =>
+ returnm ((match w__63 with
+ | Some (res) => res
+ | None =>
+ let '_ := (print_bits "unhandled read to CSR " csr) : unit in
+ EXTZ 32 (vec_of_bits [B0;B0;B0;B0] : mword 4)
+ end)
+ : mword 32))
+ : M (mword 32)
+ end) >>= fun res : xlenbits =>
+ let '_ :=
+ (if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr) (String.append " -> " (string_of_bits res))))
+ else tt)
+ : unit in
+ returnm (res
+ : mword 32).
+
+Definition writeCSR (csr : mword 12) (value : mword 32)
+: M (unit) :=
+
+ (match (csr, 32) with
+ | (b__0, g__216) =>
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (legalize_mstatus w__0 value) >>= fun w__1 : Mstatus =>
+ write_reg mstatus_ref w__1 >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__2))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg misa_ref >>= fun w__3 : Misa =>
+ (legalize_misa w__3 value) >>= fun w__4 : Misa =>
+ write_reg misa_ref w__4 >>
+ read_reg misa_ref >>= fun w__5 : Misa =>
+ returnm ((Some
+ (_get_Misa_bits w__5))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg medeleg_ref >>= fun w__6 : Medeleg =>
+ write_reg medeleg_ref (legalize_medeleg w__6 value) >>
+ read_reg medeleg_ref >>= fun w__7 : Medeleg =>
+ returnm ((Some
+ (_get_Medeleg_bits w__7))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg mideleg_ref >>= fun w__8 : Minterrupts =>
+ write_reg mideleg_ref (legalize_mideleg w__8 value) >>
+ read_reg mideleg_ref >>= fun w__9 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__9))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__10 : Minterrupts =>
+ (legalize_mie w__10 value) >>= fun w__11 : Minterrupts =>
+ write_reg mie_ref w__11 >>
+ read_reg mie_ref >>= fun w__12 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__12))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_mtvec value) >>= fun w__13 : mword 32 =>
+ returnm ((Some
+ (w__13))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__14 : Counteren =>
+ (legalize_mcounteren w__14 value) >>= fun w__15 : Counteren =>
+ write_reg mcounteren_ref w__15 >>
+ read_reg mcounteren_ref >>= fun w__16 : Counteren =>
+ returnm ((Some
+ (EXTZ 32 (_get_Counteren_bits w__16)))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg mscratch_ref value >>
+ ((read_reg mscratch_ref) : M (mword 32)) >>= fun w__17 : mword 32 =>
+ returnm ((Some
+ (w__17))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target Machine value) >>= fun w__18 : mword 32 =>
+ returnm ((Some
+ (w__18))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits mcause_ref value) >>
+ read_reg mcause_ref >>= fun w__19 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__19))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg mtval_ref value >>
+ ((read_reg mtval_ref) : M (mword 32)) >>= fun w__20 : mword 32 =>
+ returnm ((Some
+ (w__20))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__21 : Minterrupts =>
+ (legalize_mip w__21 value) >>= fun w__22 : Minterrupts =>
+ write_reg mip_ref w__22 >>
+ read_reg mip_ref >>= fun w__23 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__23))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ (pmpWriteCfgReg 0 value) >> returnm ((Some (value)) : option (mword 32))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1]
+ : mword 12)) (Z.eqb g__216 32))) then
+ (pmpWriteCfgReg 1 value) >> returnm ((Some (value)) : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ (pmpWriteCfgReg 2 value) >> returnm ((Some (value)) : option (mword 32))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1]
+ : mword 12)) (Z.eqb g__216 32))) then
+ (pmpWriteCfgReg 3 value) >> returnm ((Some (value)) : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ read_reg pmp0cfg_ref >>= fun w__24 : Pmpcfg_ent =>
+ ((read_reg pmpaddr0_ref) : M (mword 32)) >>= fun w__25 : mword 32 =>
+ write_reg pmpaddr0_ref (pmpWriteAddr w__24 w__25 value) >>
+ ((read_reg pmpaddr0_ref) : M (mword 32)) >>= fun w__26 : mword 32 =>
+ returnm ((Some
+ (w__26))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ read_reg pmp1cfg_ref >>= fun w__27 : Pmpcfg_ent =>
+ ((read_reg pmpaddr1_ref) : M (mword 32)) >>= fun w__28 : mword 32 =>
+ write_reg pmpaddr1_ref (pmpWriteAddr w__27 w__28 value) >>
+ ((read_reg pmpaddr1_ref) : M (mword 32)) >>= fun w__29 : mword 32 =>
+ returnm ((Some
+ (w__29))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ read_reg pmp2cfg_ref >>= fun w__30 : Pmpcfg_ent =>
+ ((read_reg pmpaddr2_ref) : M (mword 32)) >>= fun w__31 : mword 32 =>
+ write_reg pmpaddr2_ref (pmpWriteAddr w__30 w__31 value) >>
+ ((read_reg pmpaddr2_ref) : M (mword 32)) >>= fun w__32 : mword 32 =>
+ returnm ((Some
+ (w__32))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ read_reg pmp3cfg_ref >>= fun w__33 : Pmpcfg_ent =>
+ ((read_reg pmpaddr3_ref) : M (mword 32)) >>= fun w__34 : mword 32 =>
+ write_reg pmpaddr3_ref (pmpWriteAddr w__33 w__34 value) >>
+ ((read_reg pmpaddr3_ref) : M (mword 32)) >>= fun w__35 : mword 32 =>
+ returnm ((Some
+ (w__35))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ read_reg pmp4cfg_ref >>= fun w__36 : Pmpcfg_ent =>
+ ((read_reg pmpaddr4_ref) : M (mword 32)) >>= fun w__37 : mword 32 =>
+ write_reg pmpaddr4_ref (pmpWriteAddr w__36 w__37 value) >>
+ ((read_reg pmpaddr4_ref) : M (mword 32)) >>= fun w__38 : mword 32 =>
+ returnm ((Some
+ (w__38))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ read_reg pmp5cfg_ref >>= fun w__39 : Pmpcfg_ent =>
+ ((read_reg pmpaddr5_ref) : M (mword 32)) >>= fun w__40 : mword 32 =>
+ write_reg pmpaddr5_ref (pmpWriteAddr w__39 w__40 value) >>
+ ((read_reg pmpaddr5_ref) : M (mword 32)) >>= fun w__41 : mword 32 =>
+ returnm ((Some
+ (w__41))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ read_reg pmp6cfg_ref >>= fun w__42 : Pmpcfg_ent =>
+ ((read_reg pmpaddr6_ref) : M (mword 32)) >>= fun w__43 : mword 32 =>
+ write_reg pmpaddr6_ref (pmpWriteAddr w__42 w__43 value) >>
+ ((read_reg pmpaddr6_ref) : M (mword 32)) >>= fun w__44 : mword 32 =>
+ returnm ((Some
+ (w__44))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ read_reg pmp7cfg_ref >>= fun w__45 : Pmpcfg_ent =>
+ ((read_reg pmpaddr7_ref) : M (mword 32)) >>= fun w__46 : mword 32 =>
+ write_reg pmpaddr7_ref (pmpWriteAddr w__45 w__46 value) >>
+ ((read_reg pmpaddr7_ref) : M (mword 32)) >>= fun w__47 : mword 32 =>
+ returnm ((Some
+ (w__47))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ read_reg pmp8cfg_ref >>= fun w__48 : Pmpcfg_ent =>
+ ((read_reg pmpaddr8_ref) : M (mword 32)) >>= fun w__49 : mword 32 =>
+ write_reg pmpaddr8_ref (pmpWriteAddr w__48 w__49 value) >>
+ ((read_reg pmpaddr8_ref) : M (mword 32)) >>= fun w__50 : mword 32 =>
+ returnm ((Some
+ (w__50))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ read_reg pmp9cfg_ref >>= fun w__51 : Pmpcfg_ent =>
+ ((read_reg pmpaddr9_ref) : M (mword 32)) >>= fun w__52 : mword 32 =>
+ write_reg pmpaddr9_ref (pmpWriteAddr w__51 w__52 value) >>
+ ((read_reg pmpaddr9_ref) : M (mword 32)) >>= fun w__53 : mword 32 =>
+ returnm ((Some
+ (w__53))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ read_reg pmp10cfg_ref >>= fun w__54 : Pmpcfg_ent =>
+ ((read_reg pmpaddr10_ref) : M (mword 32)) >>= fun w__55 : mword 32 =>
+ write_reg pmpaddr10_ref (pmpWriteAddr w__54 w__55 value) >>
+ ((read_reg pmpaddr10_ref) : M (mword 32)) >>= fun w__56 : mword 32 =>
+ returnm ((Some
+ (w__56))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ read_reg pmp11cfg_ref >>= fun w__57 : Pmpcfg_ent =>
+ ((read_reg pmpaddr11_ref) : M (mword 32)) >>= fun w__58 : mword 32 =>
+ write_reg pmpaddr11_ref (pmpWriteAddr w__57 w__58 value) >>
+ ((read_reg pmpaddr11_ref) : M (mword 32)) >>= fun w__59 : mword 32 =>
+ returnm ((Some
+ (w__59))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ read_reg pmp12cfg_ref >>= fun w__60 : Pmpcfg_ent =>
+ ((read_reg pmpaddr12_ref) : M (mword 32)) >>= fun w__61 : mword 32 =>
+ write_reg pmpaddr12_ref (pmpWriteAddr w__60 w__61 value) >>
+ ((read_reg pmpaddr12_ref) : M (mword 32)) >>= fun w__62 : mword 32 =>
+ returnm ((Some
+ (w__62))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ read_reg pmp13cfg_ref >>= fun w__63 : Pmpcfg_ent =>
+ ((read_reg pmpaddr13_ref) : M (mword 32)) >>= fun w__64 : mword 32 =>
+ write_reg pmpaddr13_ref (pmpWriteAddr w__63 w__64 value) >>
+ ((read_reg pmpaddr13_ref) : M (mword 32)) >>= fun w__65 : mword 32 =>
+ returnm ((Some
+ (w__65))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ read_reg pmp14cfg_ref >>= fun w__66 : Pmpcfg_ent =>
+ ((read_reg pmpaddr14_ref) : M (mword 32)) >>= fun w__67 : mword 32 =>
+ write_reg pmpaddr14_ref (pmpWriteAddr w__66 w__67 value) >>
+ ((read_reg pmpaddr14_ref) : M (mword 32)) >>= fun w__68 : mword 32 =>
+ returnm ((Some
+ (w__68))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ read_reg pmp15cfg_ref >>= fun w__69 : Pmpcfg_ent =>
+ ((read_reg pmpaddr15_ref) : M (mword 32)) >>= fun w__70 : mword 32 =>
+ write_reg pmpaddr15_ref (pmpWriteAddr w__69 w__70 value) >>
+ ((read_reg pmpaddr15_ref) : M (mword 32)) >>= fun w__71 : mword 32 =>
+ returnm ((Some
+ (w__71))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__72 : mword 64 =>
+ write_reg mcycle_ref (update_subrange_vec_dec w__72 (Z.sub 32 1) 0 value) >>
+ returnm ((Some
+ (value))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__73 : mword 64 =>
+ write_reg minstret_ref (update_subrange_vec_dec w__73 (Z.sub 32 1) 0 value) >>
+ write_reg minstret_written_ref true >> returnm ((Some (value)) : option (mword 32))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]
+ : mword 12)) (Z.eqb g__216 32))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__74 : mword 64 =>
+ write_reg mcycle_ref (update_subrange_vec_dec w__74 63 32 value) >>
+ returnm ((Some
+ (value))
+ : option (mword 32))
+ else if sumbool_of_bool ((andb
+ (eq_vec b__0
+ (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]
+ : mword 12)) (Z.eqb g__216 32))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__75 : mword 64 =>
+ write_reg minstret_ref (update_subrange_vec_dec w__75 63 32 value) >>
+ write_reg minstret_written_ref true >> returnm ((Some (value)) : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg tselect_ref value >>
+ ((read_reg tselect_ref) : M (mword 32)) >>= fun w__76 : mword 32 =>
+ returnm ((Some
+ (w__76))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__77 : Mstatus =>
+ (legalize_sstatus w__77 value) >>= fun w__78 : Mstatus =>
+ write_reg mstatus_ref w__78 >>
+ read_reg mstatus_ref >>= fun w__79 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__79))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg sedeleg_ref >>= fun w__80 : Sedeleg =>
+ write_reg sedeleg_ref (legalize_sedeleg w__80 value) >>
+ read_reg sedeleg_ref >>= fun w__81 : Sedeleg =>
+ returnm ((Some
+ (_get_Sedeleg_bits w__81))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (_set_Sinterrupts_bits sideleg_ref value) >>
+ read_reg sideleg_ref >>= fun w__82 : Sinterrupts =>
+ returnm ((Some
+ (_get_Sinterrupts_bits w__82))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__83 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__84 : Minterrupts =>
+ (legalize_sie w__83 w__84 value) >>= fun w__85 : Minterrupts =>
+ write_reg mie_ref w__85 >>
+ read_reg mie_ref >>= fun w__86 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__86))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_stvec value) >>= fun w__87 : mword 32 =>
+ returnm ((Some
+ (w__87))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg scounteren_ref >>= fun w__88 : Counteren =>
+ (legalize_scounteren w__88 value) >>= fun w__89 : Counteren =>
+ write_reg scounteren_ref w__89 >>
+ read_reg scounteren_ref >>= fun w__90 : Counteren =>
+ returnm ((Some
+ (EXTZ 32 (_get_Counteren_bits w__90)))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg sscratch_ref value >>
+ ((read_reg sscratch_ref) : M (mword 32)) >>= fun w__91 : mword 32 =>
+ returnm ((Some
+ (w__91))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target Supervisor value) >>= fun w__92 : mword 32 =>
+ returnm ((Some
+ (w__92))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits scause_ref value) >>
+ read_reg scause_ref >>= fun w__93 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__93))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg stval_ref value >>
+ ((read_reg stval_ref) : M (mword 32)) >>= fun w__94 : mword 32 =>
+ returnm ((Some
+ (w__94))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__95 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__96 : Minterrupts =>
+ (legalize_sip w__95 w__96 value) >>= fun w__97 : Minterrupts =>
+ write_reg mip_ref w__97 >>
+ read_reg mip_ref >>= fun w__98 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__98))
+ : option (mword 32))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (cur_Architecture tt) >>= fun w__99 : Architecture =>
+ ((read_reg satp_ref) : M (mword 32)) >>= fun w__100 : mword 32 =>
+ write_reg satp_ref (legalize_satp w__99 w__100 value) >>
+ ((read_reg satp_ref) : M (mword 32)) >>= fun w__101 : mword 32 =>
+ returnm ((Some
+ (w__101))
+ : option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option (mword 32))
+ end) >>= fun res : option xlenbits =>
+ (match res with
+ | Some (v) =>
+ returnm ((if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr)
+ (String.append " <- "
+ (String.append (string_of_bits v)
+ (String.append " (input: "
+ (String.append (string_of_bits value) ")"))))))
+ else tt)
+ : unit)
+ | None =>
+ (ext_write_CSR csr value) >>= fun w__151 : bool =>
+ returnm ((if sumbool_of_bool (w__151) then tt
+ else print_bits "unhandled write to CSR " csr)
+ : unit)
+ end)
+ : M (unit).
+
+Definition maybe_i_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => "i" | false => "" end.
+
+Definition maybe_i_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "i")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_i_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_i_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "i")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s797_ (_s798_ : string)
+: option string :=
+
+ let _s799_ := _s798_ in
+ if ((string_startswith _s799_ "")) then
+ match (string_drop _s799_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s793_ (_s794_ : string)
+: option string :=
+
+ let _s795_ := _s794_ in
+ if ((string_startswith _s795_ "i")) then
+ match (string_drop _s795_ (projT1 (string_length "i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_i_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s796_ := arg_ in
+ (if ((match (_s793_ _s796_) with | Some (s_) => true | _ => false end)) then
+ (match (_s793_ _s796_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s797_ _s796_) with | Some (s_) => true | _ => false end)) then
+ (match (_s797_ _s796_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition csr_mnemonic_forwards (arg_ : csrop)
+: string :=
+
+ match arg_ with | CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" end.
+
+Definition csr_mnemonic_backwards (arg_ : string)
+: M (csrop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "csrrw")) then returnm (CSRRW : csrop)
+ else if ((generic_eq p0_ "csrrs")) then returnm (CSRRS : csrop)
+ else if ((generic_eq p0_ "csrrc")) then returnm (CSRRC : csrop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (csrop).
+
+Definition csr_mnemonic_forwards_matches (arg_ : csrop)
+: bool :=
+
+ match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end.
+
+Definition csr_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "csrrw")) then true
+ else if ((generic_eq p0_ "csrrs")) then true
+ else if ((generic_eq p0_ "csrrc")) then true
+ else false.
+
+Definition _s809_ (_s810_ : string)
+: option string :=
+
+ let _s811_ := _s810_ in
+ if ((string_startswith _s811_ "csrrc")) then
+ match (string_drop _s811_ (projT1 (string_length "csrrc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s805_ (_s806_ : string)
+: option string :=
+
+ let _s807_ := _s806_ in
+ if ((string_startswith _s807_ "csrrs")) then
+ match (string_drop _s807_ (projT1 (string_length "csrrs"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s801_ (_s802_ : string)
+: option string :=
+
+ let _s803_ := _s802_ in
+ if ((string_startswith _s803_ "csrrw")) then
+ match (string_drop _s803_ (projT1 (string_length "csrrw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition csr_mnemonic_matches_prefix (arg_ : string)
+: M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s804_ := arg_ in
+ (if ((match (_s801_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s801_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s805_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s805_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRS, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s809_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s809_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRC, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((csrop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_forwards (arg_ : ast)
+: M (mword 32) :=
+
+ (match arg_ with
+ | UTYPE ((imm, rd, op)) =>
+ returnm ((concat_vec (imm : mword 20) (concat_vec (rd : mword 5) (encdec_uop_forwards op)))
+ : mword (20 + (5 + 7)))
+ | RISCV_JAL ((v__2, rd)) =>
+ (if ((eq_vec (subrange_vec_dec v__2 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in
+ let imm_8 : bits 1 := subrange_vec_dec v__2 11 11 in
+ let imm_7_0 : bits 8 := subrange_vec_dec v__2 19 12 in
+ let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in
+ let imm_18_13 : bits 6 := subrange_vec_dec v__2 10 5 in
+ let imm_12_9 : bits 4 := subrange_vec_dec v__2 4 1 in
+ returnm ((concat_vec (imm_19 : bits 1)
+ (concat_vec (imm_18_13 : bits 6)
+ (concat_vec (imm_12_9 : bits 4)
+ (concat_vec (imm_8 : bits 1)
+ (concat_vec (imm_7_0 : bits 8)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | BTYPE ((v__4, rs2, rs1, op)) =>
+ (if ((eq_vec (subrange_vec_dec v__4 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in
+ let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in
+ let imm7_5_0 : bits 6 := subrange_vec_dec v__4 10 5 in
+ let imm5_4_1 : bits 4 := subrange_vec_dec v__4 4 1 in
+ let imm5_0 : bits 1 := subrange_vec_dec v__4 11 11 in
+ returnm ((concat_vec (imm7_6 : bits 1)
+ (concat_vec (imm7_5_0 : bits 6)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (encdec_bop_forwards op)
+ (concat_vec (imm5_4_1 : bits 4)
+ (concat_vec (imm5_0 : bits 1)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7))))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | ITYPE ((imm, rs1, rd, op)) =>
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (encdec_iop_forwards op)
+ (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) =>
+ (if sumbool_of_bool ((orb (Z.ltb (projT1 (word_width_bytes size)) 4)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)))) then
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (bool_bits_forwards is_unsigned)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7))))))
+ : mword (12 + (5 + (1 + (2 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | STORE ((v__6, rs2, rs1, size, false, false)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then
+ let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in
+ let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in
+ let imm5 : bits 5 := subrange_vec_dec v__6 4 0 in
+ returnm ((concat_vec (imm7 : bits 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (imm5 : bits 5)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7)))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | ADDIW ((imm, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | FENCE ((pred, succ)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4)
+ (concat_vec (pred : mword 4)
+ (concat_vec (succ : mword 4)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword (4 + (4 + (4 + (5 + (3 + (5 + 7)))))))
+ | FENCE_TSO ((pred, succ)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0;B0] : mword 4)
+ (concat_vec (pred : mword 4)
+ (concat_vec (succ : mword 4)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword (4 + (4 + (4 + (5 + (3 + (5 + 7)))))))
+ | FENCEI (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | ECALL (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | MRET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | SRET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | EBREAK (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | WFI (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | SFENCE_VMA ((rs1, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | AMO ((op, aq, rl, rs2, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then
+ returnm ((concat_vec (encdec_amoop_forwards op)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (encdec_mul_op_forwards (high, signed1, signed2)) >>= fun w__38 : mword 3 =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (w__38 : bits 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | DIV ((rs2, rs1, rd, s)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ | REM ((rs2, rs1, rd, s)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ | MULW ((rs2, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | DIVW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | REMW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ returnm ((concat_vec (csr : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (bool_bits_forwards is_imm)
+ (concat_vec (encdec_csrop_forwards op)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (12 + (5 + (1 + (2 + (5 + 7))))))
+ | URET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | ILLEGAL (s) => returnm (s : mword 32)
+ | _ => assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt
+ end)
+ : M (mword 32).
+
+Definition encdec_backwards (arg_ : mword 32)
+: M (ast) :=
+
+ let v__7 := arg_ in
+ let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in
+ (and_boolM (returnm ((encdec_uop_backwards_matches _mappingpatterns_23_) : bool))
+ ((if ((encdec_uop_backwards_matches _mappingpatterns_23_)) then
+ (encdec_uop_backwards _mappingpatterns_23_) >>= fun op => returnm ((true : bool) : bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ let imm : mword 20 := subrange_vec_dec v__7 31 12 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 20 := subrange_vec_dec v__7 31 12 in
+ let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in
+ (encdec_uop_backwards _mappingpatterns_23_) >>= fun op =>
+ returnm ((UTYPE
+ ((imm, rd, op)))
+ : ast)
+ else if ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then
+ let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm_8 : bits 1 := subrange_vec_dec v__7 20 20 in
+ let imm_7_0 : bits 8 := subrange_vec_dec v__7 19 12 in
+ let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let imm_18_13 : bits 6 := subrange_vec_dec v__7 30 25 in
+ let imm_12_9 : bits 4 := subrange_vec_dec v__7 24 21 in
+ returnm ((RISCV_JAL
+ ((concat_vec (imm_19 : bits 1)
+ (concat_vec (imm_7_0 : bits 8)
+ (concat_vec (imm_8 : bits 1)
+ (concat_vec (imm_18_13 : bits 6)
+ (concat_vec (imm_12_9 : bits 4) (vec_of_bits [B0] : mword 1))))), rd)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ returnm ((RISCV_JALR
+ ((imm, rs1, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (and_boolM (returnm ((encdec_bop_backwards_matches _mappingpatterns_24_) : bool))
+ ((if ((encdec_bop_backwards_matches _mappingpatterns_24_)) then
+ (encdec_bop_backwards _mappingpatterns_24_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let imm7_5_0 : bits 6 := subrange_vec_dec v__7 30 25 in
+ let imm5_4_1 : bits 4 := subrange_vec_dec v__7 11 8 in
+ let imm5_0 : bits 1 := subrange_vec_dec v__7 7 7 in
+ let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (encdec_bop_backwards _mappingpatterns_24_) >>= fun op =>
+ returnm ((BTYPE
+ ((concat_vec (imm7_6 : bits 1)
+ (concat_vec (imm5_0 : bits 1)
+ (concat_vec (imm7_5_0 : bits 6)
+ (concat_vec (imm5_4_1 : bits 4) (vec_of_bits [B0] : mword 1)))), rs2, rs1, op)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (and_boolM (returnm ((encdec_iop_backwards_matches _mappingpatterns_25_) : bool))
+ ((if ((encdec_iop_backwards_matches _mappingpatterns_25_)) then
+ (encdec_iop_backwards _mappingpatterns_25_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__7 : bool =>
+ (if sumbool_of_bool (w__7) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (encdec_iop_backwards _mappingpatterns_25_) >>= fun op =>
+ returnm ((ITYPE
+ ((imm, rs1, rd, op)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__8 : bool =>
+ returnm ((Bool.eqb w__8 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool = true) (simp_0 =
+ true /\
+ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__10 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__10) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SLLI)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__11 : bool =>
+ returnm ((Bool.eqb w__11 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__13 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__13) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SRLI)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__14 : bool =>
+ returnm ((Bool.eqb w__14 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__16 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__16) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SRAI)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_ADD)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLT)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLTU)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_AND)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_OR)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_XOR)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLL)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SRL)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SUB)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SRA)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_27_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_27_)) then
+ (size_bits_backwards _mappingpatterns_27_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_26_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_26_)) then
+ (bool_bits_backwards _mappingpatterns_26_) >>= fun is_unsigned =>
+ returnm (((orb (Z.ltb (projT1 (word_width_bytes size)) 4)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)))
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__18 : bool =>
+ returnm ((w__18
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__21 : bool =>
+ (if sumbool_of_bool (w__21) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in
+ (size_bits_backwards _mappingpatterns_27_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_26_) >>= fun is_unsigned =>
+ returnm ((LOAD
+ ((imm, rs1, rd, is_unsigned, size, false, false)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_28_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_28_)) then
+ (size_bits_backwards _mappingpatterns_28_) >>= fun size =>
+ returnm (((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__24 : bool =>
+ (if sumbool_of_bool (w__24) then
+ let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in
+ let imm5 : bits 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ (size_bits_backwards _mappingpatterns_28_) >>= fun size =>
+ returnm ((STORE
+ ((concat_vec (imm7 : bits 7) (imm5 : bits 5), rs2, rs1, size, false, false)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ returnm ((ADDIW
+ ((imm, rs1, rd)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SLLI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SRLI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SRAI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_ADDW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SUBW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SLLW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SRLW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SRAW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SLLIW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SRLIW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SRAIW)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 28)
+ (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__7 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ let succ : mword 4 := subrange_vec_dec v__7 23 20 in
+ let pred : mword 4 := subrange_vec_dec v__7 27 24 in
+ returnm ((FENCE
+ ((pred, succ)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 28)
+ (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__7 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ let succ : mword 4 := subrange_vec_dec v__7 23 20 in
+ let pred : mword 4 := subrange_vec_dec v__7 27 24 in
+ returnm ((FENCE_TSO
+ ((pred, succ)))
+ : ast)
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword 32))) then
+ returnm ((FENCEI
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((ECALL
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((MRET
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((SRET
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((EBREAK
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((WFI
+ (tt))
+ : ast )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__7 14 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword (14 - 0 + 1))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ returnm ((SFENCE_VMA
+ ((rs1, rs2)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_31_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_29_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_31_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_31_)) then
+ (size_bits_backwards _mappingpatterns_31_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_30_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_30_))
+ then
+ (bool_bits_backwards _mappingpatterns_30_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_29_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_29_)) then
+ (bool_bits_backwards _mappingpatterns_29_) >>= fun aq =>
+ returnm (((Z.leb (projT1 (word_width_bytes size))
+ 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__26 : bool =>
+ returnm ((w__26
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__28 : bool =>
+ returnm ((w__28
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 24 20)
+ (vec_of_bits [B0;B0;B0;B0;B0]
+ : mword (24 - 20 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))))
+ : bool))) >>= fun w__31 : bool =>
+ (if sumbool_of_bool (w__31) then
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_31_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_29_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (size_bits_backwards _mappingpatterns_31_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_30_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_29_) >>= fun aq =>
+ returnm ((LOADRES
+ ((aq, rl, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_34_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_34_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_34_)) then
+ (size_bits_backwards _mappingpatterns_34_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_33_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_33_))
+ then
+ (bool_bits_backwards _mappingpatterns_33_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_32_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_32_)) then
+ (bool_bits_backwards _mappingpatterns_32_) >>= fun aq =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size)) 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__33 : bool =>
+ returnm ((w__33
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__35 : bool =>
+ returnm ((w__35
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B1]
+ : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__38 : bool =>
+ (if sumbool_of_bool (w__38) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_34_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (size_bits_backwards _mappingpatterns_34_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_33_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_32_) >>= fun aq =>
+ returnm ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ let _mappingpatterns_38_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_37_ : mword 1 :=
+ subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_36_ : mword 1 :=
+ subrange_vec_dec v__7 26 26 in
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_38_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_38_))
+ then
+ (size_bits_backwards _mappingpatterns_38_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_37_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_37_)) then
+ (bool_bits_backwards _mappingpatterns_37_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_36_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_36_)) then
+ (bool_bits_backwards _mappingpatterns_36_) >>= fun aq =>
+ (and_boolM
+ (returnm ((encdec_amoop_backwards_matches
+ _mappingpatterns_35_)
+ : bool))
+ ((if ((encdec_amoop_backwards_matches
+ _mappingpatterns_35_)) then
+ (encdec_amoop_backwards
+ _mappingpatterns_35_) >>= fun op =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size))
+ 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__40 : bool =>
+ returnm ((w__40
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__42 : bool =>
+ returnm ((w__42
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__44 : bool =>
+ returnm ((w__44
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__47 : bool =>
+ (if sumbool_of_bool (w__47) then
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_38_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_37_ : mword 1 :=
+ subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_36_ : mword 1 :=
+ subrange_vec_dec v__7 26 26 in
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ (size_bits_backwards _mappingpatterns_38_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_37_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_36_) >>= fun aq =>
+ (encdec_amoop_backwards _mappingpatterns_35_) >>= fun op =>
+ returnm ((AMO
+ ((op, aq, rl, rs2, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_39_ : mword 3 :=
+ subrange_vec_dec v__7 14 12 in
+ (and_boolM
+ (returnm ((encdec_mul_op_backwards_matches
+ _mappingpatterns_39_)
+ : bool))
+ ((if ((encdec_mul_op_backwards_matches
+ _mappingpatterns_39_)) then
+ (encdec_mul_op_backwards _mappingpatterns_39_) >>= fun '(high, signed1, signed2) =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__50 : bool =>
+ (if sumbool_of_bool (w__50) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_39_ : mword 3 :=
+ subrange_vec_dec v__7 14 12 in
+ (encdec_mul_op_backwards _mappingpatterns_39_) >>= fun '(high, signed1, signed2) =>
+ returnm ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_40_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_40_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_40_)) then
+ (bool_not_bits_backwards _mappingpatterns_40_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__53 : bool =>
+ (if sumbool_of_bool (w__53) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_40_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_40_) >>= fun s =>
+ returnm ((DIV
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_41_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_41_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_41_)) then
+ (bool_not_bits_backwards _mappingpatterns_41_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__56 : bool =>
+ (if sumbool_of_bool (w__56) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_41_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_41_) >>= fun s =>
+ returnm ((REM
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7
+ 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec
+ (subrange_vec_dec
+ v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((MULW
+ ((rs2, rs1, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_42_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_42_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_42_)) then
+ (bool_not_bits_backwards _mappingpatterns_42_) >>= fun s =>
+ returnm (((Z.eqb 32 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__59 : bool =>
+ (if sumbool_of_bool (w__59) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_42_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_42_) >>= fun s =>
+ returnm ((DIVW
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_43_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_43_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_43_)) then
+ (bool_not_bits_backwards
+ _mappingpatterns_43_) >>= fun s =>
+ returnm (((Z.eqb 32 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec
+ (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__62 : bool =>
+ (if sumbool_of_bool (w__62) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_43_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_43_) >>= fun s =>
+ returnm ((REMW
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_45_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_44_ : mword 1 :=
+ subrange_vec_dec v__7 14 14 in
+ (and_boolM
+ (returnm ((encdec_csrop_backwards_matches
+ _mappingpatterns_45_)
+ : bool))
+ ((if ((encdec_csrop_backwards_matches
+ _mappingpatterns_45_)) then
+ (encdec_csrop_backwards
+ _mappingpatterns_45_) >>= fun op =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_44_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_44_)) then
+ (bool_bits_backwards
+ _mappingpatterns_44_) >>= fun is_imm =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__64 : bool =>
+ returnm ((w__64
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__67 : bool =>
+ (if sumbool_of_bool (w__67) then
+ let csr : mword 12 :=
+ subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 :=
+ subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let csr : mword 12 :=
+ subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_45_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_44_ : mword 1 :=
+ subrange_vec_dec v__7 14 14 in
+ (encdec_csrop_backwards _mappingpatterns_45_) >>= fun op =>
+ (bool_bits_backwards _mappingpatterns_44_) >>= fun is_imm =>
+ returnm ((CSR
+ ((csr, rs1, rd, is_imm, op)))
+ : ast)
+ else
+ returnm ((if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ URET
+ (tt)
+ else ILLEGAL (v__7))
+ : ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast).
+
+Definition encdec_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | UTYPE ((imm, rd, op)) => true
+ | RISCV_JAL ((v__220, rd)) =>
+ if ((eq_vec (subrange_vec_dec v__220 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true
+ else false
+ | RISCV_JALR ((imm, rs1, rd)) => true
+ | BTYPE ((v__222, rs2, rs1, op)) =>
+ if ((eq_vec (subrange_vec_dec v__222 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true
+ else false
+ | ITYPE ((imm, rs1, rd, op)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) => true
+ | LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) =>
+ if sumbool_of_bool ((orb (Z.ltb (projT1 (word_width_bytes size)) 4)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)))) then
+ true
+ else false
+ | STORE ((v__224, rs2, rs1, size, false, false)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then true else false
+ | ADDIW ((imm, rs1, rd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | FENCE ((pred, succ)) => true
+ | FENCE_TSO ((pred, succ)) => true
+ | FENCEI (tt) => true
+ | ECALL (tt) => true
+ | MRET (tt) => true
+ | SRET (tt) => true
+ | EBREAK (tt) => true
+ | WFI (tt) => true
+ | SFENCE_VMA ((rs1, rs2)) => true
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then true else false
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then true else false
+ | AMO ((op, aq, rl, rs2, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 4)) then true else false
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => true
+ | DIV ((rs2, rs1, rd, s)) => true
+ | REM ((rs2, rs1, rd, s)) => true
+ | MULW ((rs2, rs1, rd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | DIVW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | REMW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | CSR ((csr, rs1, rd, is_imm, op)) => true
+ | URET (tt) => true
+ | ILLEGAL (s) => true
+ | _ => false
+ end.
+
+Definition encdec_backwards_matches (arg_ : mword 32)
+: M (bool) :=
+
+ let v__225 := arg_ in
+ let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__225 6 0 in
+ (and_boolM (returnm ((encdec_uop_backwards_matches _mappingpatterns_0_) : bool))
+ ((if ((encdec_uop_backwards_matches _mappingpatterns_0_)) then
+ (encdec_uop_backwards _mappingpatterns_0_) >>= fun op => returnm ((true : bool) : bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__225 6 0 in
+ (encdec_uop_backwards _mappingpatterns_0_) >>= fun op => returnm (true : bool)
+ else if ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (and_boolM (returnm ((encdec_bop_backwards_matches _mappingpatterns_1_) : bool))
+ ((if ((encdec_bop_backwards_matches _mappingpatterns_1_)) then
+ (encdec_bop_backwards _mappingpatterns_1_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (encdec_bop_backwards _mappingpatterns_1_) >>= fun op => returnm (true : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (and_boolM (returnm ((encdec_iop_backwards_matches _mappingpatterns_2_) : bool))
+ ((if ((encdec_iop_backwards_matches _mappingpatterns_2_)) then
+ (encdec_iop_backwards _mappingpatterns_2_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__7 : bool =>
+ (if sumbool_of_bool (w__7) then
+ let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (encdec_iop_backwards _mappingpatterns_2_) >>= fun op => returnm (true : bool)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__8 : bool =>
+ returnm ((Bool.eqb w__8 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool = true) (simp_0 =
+ true /\
+ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__10 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__10) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__11 : bool =>
+ returnm ((Bool.eqb w__11 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__13 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__13) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 32 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (32 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (32 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__14 : bool =>
+ returnm ((Bool.eqb w__14 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (32 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (32 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__16 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (32 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__16) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__225 14 14 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_4_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_4_)) then
+ (size_bits_backwards _mappingpatterns_4_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_3_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_3_)) then
+ (bool_bits_backwards _mappingpatterns_3_) >>= fun is_unsigned =>
+ returnm (((orb (Z.ltb (projT1 (word_width_bytes size)) 4)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)))
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__18 : bool =>
+ returnm ((w__18
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__21 : bool =>
+ (if sumbool_of_bool (w__21) then
+ let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__225 14 14 in
+ (size_bits_backwards _mappingpatterns_4_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_3_) >>= fun is_unsigned =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_5_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_5_)) then
+ (size_bits_backwards _mappingpatterns_5_) >>= fun size =>
+ returnm (((Z.leb (projT1 (word_width_bytes size)) 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__24 : bool =>
+ (if sumbool_of_bool (w__24) then
+ let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ (size_bits_backwards _mappingpatterns_5_) >>= fun size =>
+ returnm (true
+ : bool)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 28)
+ (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__225 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 28)
+ (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__225 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__225 14 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword (14 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_8_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_6_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_8_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_8_)) then
+ (size_bits_backwards _mappingpatterns_8_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_7_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_7_))
+ then
+ (bool_bits_backwards _mappingpatterns_7_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_6_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_6_)) then
+ (bool_bits_backwards _mappingpatterns_6_) >>= fun aq =>
+ returnm (((Z.leb (projT1 (word_width_bytes size))
+ 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__26 : bool =>
+ returnm ((w__26
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__28 : bool =>
+ returnm ((w__28
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 24 20)
+ (vec_of_bits [B0;B0;B0;B0;B0]
+ : mword (24 - 20 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))))
+ : bool))) >>= fun w__31 : bool =>
+ (if sumbool_of_bool (w__31) then
+ let _mappingpatterns_8_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_6_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ (size_bits_backwards _mappingpatterns_8_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_7_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_6_) >>= fun aq =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_11_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_11_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_11_)) then
+ (size_bits_backwards _mappingpatterns_11_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_10_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_10_))
+ then
+ (bool_bits_backwards _mappingpatterns_10_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_9_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_9_)) then
+ (bool_bits_backwards _mappingpatterns_9_) >>= fun aq =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size)) 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__33 : bool =>
+ returnm ((w__33
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__35 : bool =>
+ returnm ((w__35
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B1]
+ : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__38 : bool =>
+ (if sumbool_of_bool (w__38) then
+ let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_11_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ (size_bits_backwards _mappingpatterns_11_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_10_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_9_) >>= fun aq =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ let _mappingpatterns_15_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_14_ : mword 1 :=
+ subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_13_ : mword 1 :=
+ subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_15_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_15_))
+ then
+ (size_bits_backwards _mappingpatterns_15_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_14_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_14_)) then
+ (bool_bits_backwards _mappingpatterns_14_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_13_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_13_)) then
+ (bool_bits_backwards _mappingpatterns_13_) >>= fun aq =>
+ (and_boolM
+ (returnm ((encdec_amoop_backwards_matches
+ _mappingpatterns_12_)
+ : bool))
+ ((if ((encdec_amoop_backwards_matches
+ _mappingpatterns_12_)) then
+ (encdec_amoop_backwards
+ _mappingpatterns_12_) >>= fun op =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size))
+ 4)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__40 : bool =>
+ returnm ((w__40
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__42 : bool =>
+ returnm ((w__42
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__44 : bool =>
+ returnm ((w__44
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__47 : bool =>
+ (if sumbool_of_bool (w__47) then
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ let _mappingpatterns_15_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_14_ : mword 1 :=
+ subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_13_ : mword 1 :=
+ subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ (size_bits_backwards _mappingpatterns_15_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_14_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_13_) >>= fun aq =>
+ (encdec_amoop_backwards _mappingpatterns_12_) >>= fun op =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_16_ : mword 3 :=
+ subrange_vec_dec v__225 14 12 in
+ (and_boolM
+ (returnm ((encdec_mul_op_backwards_matches
+ _mappingpatterns_16_)
+ : bool))
+ ((if ((encdec_mul_op_backwards_matches
+ _mappingpatterns_16_)) then
+ (encdec_mul_op_backwards _mappingpatterns_16_) >>= fun '(high, signed1, signed2) =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__50 : bool =>
+ (if sumbool_of_bool (w__50) then
+ let _mappingpatterns_16_ : mword 3 :=
+ subrange_vec_dec v__225 14 12 in
+ (encdec_mul_op_backwards _mappingpatterns_16_) >>= fun '(high, signed1, signed2) =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_17_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_17_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_17_)) then
+ (bool_not_bits_backwards _mappingpatterns_17_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__53 : bool =>
+ (if sumbool_of_bool (w__53) then
+ let _mappingpatterns_17_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_17_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_18_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_18_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_18_)) then
+ (bool_not_bits_backwards _mappingpatterns_18_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__56 : bool =>
+ (if sumbool_of_bool (w__56) then
+ let _mappingpatterns_18_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_18_) >>= fun s =>
+ returnm (true
+ : bool)
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec
+ (subrange_vec_dec
+ v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_19_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_19_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_19_)) then
+ (bool_not_bits_backwards _mappingpatterns_19_) >>= fun s =>
+ returnm (((Z.eqb 32 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__59 : bool =>
+ (if sumbool_of_bool (w__59) then
+ let _mappingpatterns_19_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_19_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_20_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_20_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_20_)) then
+ (bool_not_bits_backwards
+ _mappingpatterns_20_) >>= fun s =>
+ returnm (((Z.eqb 32 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec
+ (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__62 : bool =>
+ (if sumbool_of_bool (w__62) then
+ let _mappingpatterns_20_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_20_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_22_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_21_ : mword 1 :=
+ subrange_vec_dec v__225 14 14 in
+ (and_boolM
+ (returnm ((encdec_csrop_backwards_matches
+ _mappingpatterns_22_)
+ : bool))
+ ((if ((encdec_csrop_backwards_matches
+ _mappingpatterns_22_)) then
+ (encdec_csrop_backwards
+ _mappingpatterns_22_) >>= fun op =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_21_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_21_)) then
+ (bool_bits_backwards
+ _mappingpatterns_21_) >>= fun is_imm =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__64 : bool =>
+ returnm ((w__64
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__67 : bool =>
+ (if sumbool_of_bool (w__67) then
+ let _mappingpatterns_22_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_21_ : mword 1 :=
+ subrange_vec_dec v__225 14 14 in
+ (encdec_csrop_backwards _mappingpatterns_22_) >>= fun op =>
+ (bool_bits_backwards _mappingpatterns_21_) >>= fun is_imm =>
+ returnm (true
+ : bool)
+ else
+ returnm ((if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ true
+ else true)
+ : bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool).
+
+Definition encdec_compressed_forwards (arg_ : ast)
+: M (mword 16) :=
+
+ (match arg_ with
+ | C_NOP (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B1] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ | C_ADDI4SPN ((rd, v__438)) =>
+ (if ((let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__438 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__438 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__438 0 0 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__438 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__438 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__438 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nz54 : bits 2)
+ (concat_vec (nz96 : bits 4)
+ (concat_vec (nz2 : bits 1)
+ (concat_vec (nz3 : bits 1)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LW ((v__439, rs1, rd)) =>
+ let ui6 : bits 1 := subrange_vec_dec v__439 4 4 in
+ let ui6 : bits 1 := subrange_vec_dec v__439 4 4 in
+ let ui53 : bits 3 := subrange_vec_dec v__439 3 1 in
+ let ui2 : bits 1 := subrange_vec_dec v__439 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui2 : bits 1)
+ (concat_vec (ui6 : bits 1)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ | C_LD ((v__440, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ let ui76 : bits 2 := subrange_vec_dec v__440 4 3 in
+ let ui76 : bits 2 := subrange_vec_dec v__440 4 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__440 2 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SW ((v__441, rs1, rs2)) =>
+ let ui6 : bits 1 := subrange_vec_dec v__441 4 4 in
+ let ui6 : bits 1 := subrange_vec_dec v__441 4 4 in
+ let ui53 : bits 3 := subrange_vec_dec v__441 3 1 in
+ let ui2 : bits 1 := subrange_vec_dec v__441 0 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui2 : bits 1)
+ (concat_vec (ui6 : bits 1)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ | C_SD ((v__442, rs1, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ let ui76 : bits 2 := subrange_vec_dec v__442 4 3 in
+ let ui76 : bits 2 := subrange_vec_dec v__442 4 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__442 2 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : bits 3)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rs2 : bits 3) (vec_of_bits [B0;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDI ((v__443, rsd)) =>
+ (if ((let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__443 4 0 in
+ andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__443 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nzi5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (nzi40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JAL (v__444) =>
+ (if sumbool_of_bool ((Z.eqb 32 32)) then
+ let i11 : bits 1 := subrange_vec_dec v__444 10 10 in
+ let i98 : bits 2 := subrange_vec_dec v__444 8 7 in
+ let i7 : bits 1 := subrange_vec_dec v__444 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__444 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__444 4 4 in
+ let i4 : bits 1 := subrange_vec_dec v__444 3 3 in
+ let i31 : bits 3 := subrange_vec_dec v__444 2 0 in
+ let i11 : bits 1 := subrange_vec_dec v__444 10 10 in
+ let i10 : bits 1 := subrange_vec_dec v__444 9 9 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i4 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i31 : bits 3)
+ (concat_vec (i5 : bits 1)
+ (vec_of_bits [B0;B1] : mword 2))))))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDIW ((v__445, rsd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))) then
+ let imm5 : bits 1 := subrange_vec_dec v__445 5 5 in
+ let imm5 : bits 1 := subrange_vec_dec v__445 5 5 in
+ let imm40 : bits 5 := subrange_vec_dec v__445 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (imm5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LI ((v__446, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ let imm5 : bits 1 := subrange_vec_dec v__446 5 5 in
+ let imm5 : bits 1 := subrange_vec_dec v__446 5 5 in
+ let imm40 : bits 5 := subrange_vec_dec v__446 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (imm5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDI16SP (v__447) =>
+ (if ((let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__447 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__447 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__447 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__447 0 0 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__447 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__447 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__447 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__447 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (nzi9 : bits 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (nzi4 : bits 1)
+ (concat_vec (nzi6 : bits 1)
+ (concat_vec (nzi87 : bits 2)
+ (concat_vec (nzi5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LUI ((v__448, rd)) =>
+ (if sumbool_of_bool ((let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__448 4 0 in
+ andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))) then
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__448 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (imm17 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (imm1612 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SRLI ((v__449, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__449 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ then
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__449 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SRAI ((v__450, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__450 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ then
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__450 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ANDI ((v__451, rsd)) =>
+ let i5 : bits 1 := subrange_vec_dec v__451 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__451 5 5 in
+ let i40 : bits 5 := subrange_vec_dec v__451 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (i5 : bits 1)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (i40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ | C_SUB ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_XOR ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_OR ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_AND ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_SUBW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_J (v__452) =>
+ let i11 : bits 1 := subrange_vec_dec v__452 10 10 in
+ let i98 : bits 2 := subrange_vec_dec v__452 8 7 in
+ let i7 : bits 1 := subrange_vec_dec v__452 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__452 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__452 4 4 in
+ let i4 : bits 1 := subrange_vec_dec v__452 3 3 in
+ let i31 : bits 3 := subrange_vec_dec v__452 2 0 in
+ let i11 : bits 1 := subrange_vec_dec v__452 10 10 in
+ let i10 : bits 1 := subrange_vec_dec v__452 9 9 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i4 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i31 : bits 3)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))))
+ : mword 16)
+ | C_BEQZ ((v__453, rs)) =>
+ let i8 : bits 1 := subrange_vec_dec v__453 7 7 in
+ let i8 : bits 1 := subrange_vec_dec v__453 7 7 in
+ let i76 : bits 2 := subrange_vec_dec v__453 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__453 4 4 in
+ let i43 : bits 2 := subrange_vec_dec v__453 3 2 in
+ let i21 : bits 2 := subrange_vec_dec v__453 1 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (i8 : bits 1)
+ (concat_vec (i43 : bits 2)
+ (concat_vec (rs : cregidx)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i21 : bits 2)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ | C_BNEZ ((v__454, rs)) =>
+ let i8 : bits 1 := subrange_vec_dec v__454 7 7 in
+ let i8 : bits 1 := subrange_vec_dec v__454 7 7 in
+ let i76 : bits 2 := subrange_vec_dec v__454 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__454 4 4 in
+ let i43 : bits 2 := subrange_vec_dec v__454 3 2 in
+ let i21 : bits 2 := subrange_vec_dec v__454 1 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (i8 : bits 1)
+ (concat_vec (i43 : bits 2)
+ (concat_vec (rs : cregidx)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i21 : bits 2)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ | C_SLLI ((v__455, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__455 4 0 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 32 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))) then
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__455 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LWSP ((v__456, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ let ui76 : bits 2 := subrange_vec_dec v__456 5 4 in
+ let ui76 : bits 2 := subrange_vec_dec v__456 5 4 in
+ let ui5 : bits 1 := subrange_vec_dec v__456 3 3 in
+ let ui42 : bits 3 := subrange_vec_dec v__456 2 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (ui5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (ui42 : bits 3)
+ (concat_vec (ui76 : bits 2) (vec_of_bits [B1;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LDSP ((v__457, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))) then
+ let ui86 : bits 3 := subrange_vec_dec v__457 5 3 in
+ let ui86 : bits 3 := subrange_vec_dec v__457 5 3 in
+ let ui5 : bits 1 := subrange_vec_dec v__457 2 2 in
+ let ui43 : bits 2 := subrange_vec_dec v__457 1 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (ui5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (ui43 : bits 2)
+ (concat_vec (ui86 : bits 3) (vec_of_bits [B1;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SWSP ((v__458, rs2)) =>
+ let ui76 : bits 2 := subrange_vec_dec v__458 5 4 in
+ let ui76 : bits 2 := subrange_vec_dec v__458 5 4 in
+ let ui52 : bits 4 := subrange_vec_dec v__458 3 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (ui52 : bits 4)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ | C_SDSP ((v__459, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ let ui86 : bits 3 := subrange_vec_dec v__459 5 3 in
+ let ui86 : bits 3 := subrange_vec_dec v__459 5 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__459 2 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (ui86 : bits 3)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (rs1 : regidx)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JALR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (rs1 : regidx)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_MV ((rd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_EBREAK (tt) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ | C_ADD ((rsd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ILLEGAL (s) => returnm (s : mword 16)
+ | _ => assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt
+ end)
+ : M (mword 16).
+
+Definition encdec_compressed_backwards (arg_ : mword 16)
+: ast :=
+
+ let v__460 := arg_ in
+ if ((eq_vec v__460 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))
+ then
+ C_NOP
+ (tt)
+ else if ((andb
+ (let nz96 : bits 4 := subrange_vec_dec v__460 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__460 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))))
+ then
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ let nz96 : bits 4 := subrange_vec_dec v__460 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__460 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ C_ADDI4SPN
+ ((rd, concat_vec (nz96 : bits 4)
+ (concat_vec (nz54 : bits 2) (concat_vec (nz3 : bits 1) (nz2 : bits 1)))))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let ui2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ C_LW
+ ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rd))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ C_LD
+ ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let ui2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ C_SW
+ ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs2 : bits 3 := subrange_vec_dec v__460 4 2 in
+ let rs1 : bits 3 := subrange_vec_dec v__460 9 7 in
+ C_SD
+ ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rs2))
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ADDI
+ ((concat_vec (nzi5 : bits 1) (nzi40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb (Z.eqb 32 32)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let i98 : bits 2 := subrange_vec_dec v__460 10 9 in
+ let i7 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__460 7 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i4 : bits 1 := subrange_vec_dec v__460 11 11 in
+ let i31 : bits 3 := subrange_vec_dec v__460 5 3 in
+ let i11 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i10 : bits 1 := subrange_vec_dec v__460 8 8 in
+ C_JAL
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3))))))))
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ADDIW
+ ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_LI
+ ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rd))
+ else if ((andb
+ (let nzi9 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__460 6 6 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 7)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (11 - 7 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let nzi9 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__460 6 6 in
+ C_ADDI16SP
+ (concat_vec (nzi9 : bits 1)
+ (concat_vec (nzi87 : bits 2)
+ (concat_vec (nzi6 : bits 1) (concat_vec (nzi5 : bits 1) (nzi4 : bits 1)))))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_LUI
+ ((concat_vec (imm17 : bits 1) (imm1612 : bits 5), rd))
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B0;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SRLI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B0;B1] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SRAI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B1;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ANDI
+ ((concat_vec (i5 : bits 1) (i40 : bits 5), rsd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_SUB
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_XOR
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_OR
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_AND
+ ((rsd, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5)
+ (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_SUBW
+ ((rsd, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5)
+ (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_ADDW
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let i98 : bits 2 := subrange_vec_dec v__460 10 9 in
+ let i7 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__460 7 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i4 : bits 1 := subrange_vec_dec v__460 11 11 in
+ let i31 : bits 3 := subrange_vec_dec v__460 5 3 in
+ let i11 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i10 : bits 1 := subrange_vec_dec v__460 8 8 in
+ C_J
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3))))))))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let rs : cregidx := subrange_vec_dec v__460 9 7 in
+ let i8 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i43 : bits 2 := subrange_vec_dec v__460 11 10 in
+ let i21 : bits 2 := subrange_vec_dec v__460 4 3 in
+ C_BEQZ
+ ((concat_vec (i8 : bits 1)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let rs : cregidx := subrange_vec_dec v__460 9 7 in
+ let i8 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i43 : bits 2 := subrange_vec_dec v__460 11 10 in
+ let i21 : bits 2 := subrange_vec_dec v__460 4 3 in
+ C_BNEZ
+ ((concat_vec (i8 : bits 1)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs))
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 32 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))))
+ then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SLLI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 3 2 in
+ let ui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let ui42 : bits 3 := subrange_vec_dec v__460 6 4 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_LWSP
+ ((concat_vec (ui76 : bits 2) (concat_vec (ui5 : bits 1) (ui42 : bits 3)), rd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui86 : bits 3 := subrange_vec_dec v__460 4 2 in
+ let ui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let ui43 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_LDSP
+ ((concat_vec (ui86 : bits 3) (concat_vec (ui5 : bits 1) (ui43 : bits 2)), rd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui76 : bits 2 := subrange_vec_dec v__460 8 7 in
+ let ui52 : bits 4 := subrange_vec_dec v__460 12 9 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_SWSP
+ ((concat_vec (ui76 : bits 2) (ui52 : bits 4), rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui86 : bits 3 := subrange_vec_dec v__460 9 7 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_SDSP
+ ((concat_vec (ui86 : bits 3) (ui53 : bits 3), rs2))
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ C_JR
+ (rs1)
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ C_JALR
+ (rs1)
+ else if sumbool_of_bool ((andb
+ (let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_MV
+ ((rd, rs2))
+ else if ((eq_vec v__460
+ (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then
+ C_EBREAK
+ (tt)
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_ADD
+ ((rsd, rs2))
+ else C_ILLEGAL (v__460).
+
+Definition encdec_compressed_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | C_NOP (tt) => true
+ | C_ADDI4SPN ((rd, v__596)) =>
+ if ((let nz96 : bits 4 := subrange_vec_dec v__596 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__596 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__596 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__596 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__596 0 0 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then
+ true
+ else false
+ | C_LW ((v__597, rs1, rd)) => true
+ | C_LD ((v__598, rs1, rd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_SW ((v__599, rs1, rs2)) => true
+ | C_SD ((v__600, rs1, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_ADDI ((v__601, rsd)) =>
+ if ((let nzi5 : bits 1 := subrange_vec_dec v__601 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__601 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__601 4 0 in
+ andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_JAL (v__602) => if sumbool_of_bool ((Z.eqb 32 32)) then true else false
+ | C_ADDIW ((v__603, rsd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))) then
+ true
+ else false
+ | C_LI ((v__604, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_ADDI16SP (v__605) =>
+ if ((let nzi9 : bits 1 := subrange_vec_dec v__605 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__605 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__605 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__605 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__605 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__605 0 0 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then
+ true
+ else false
+ | C_LUI ((v__606, rd)) =>
+ if sumbool_of_bool ((let imm17 : bits 1 := subrange_vec_dec v__606 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__606 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__606 4 0 in
+ andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))) then
+ true
+ else false
+ | C_SRLI ((v__607, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__607 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__607 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__607 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then
+ true
+ else false
+ | C_SRAI ((v__608, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__608 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__608 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__608 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then
+ true
+ else false
+ | C_ANDI ((v__609, rsd)) => true
+ | C_SUB ((rsd, rs2)) => true
+ | C_XOR ((rsd, rs2)) => true
+ | C_OR ((rsd, rs2)) => true
+ | C_AND ((rsd, rs2)) => true
+ | C_SUBW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_ADDW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_J (v__610) => true
+ | C_BEQZ ((v__611, rs)) => true
+ | C_BNEZ ((v__612, rs)) => true
+ | C_SLLI ((v__613, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__613 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__613 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__613 4 0 in
+ andb (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 32 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))) then
+ true
+ else false
+ | C_LWSP ((v__614, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_LDSP ((v__615, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ (Z.eqb 32 64))) then
+ true
+ else false
+ | C_SWSP ((v__616, rs2)) => true
+ | C_SDSP ((v__617, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_JR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_JALR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_MV ((rd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_EBREAK (tt) => true
+ | C_ADD ((rsd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_ILLEGAL (s) => true
+ | _ => false
+ end.
+
+Definition encdec_compressed_backwards_matches (arg_ : mword 16)
+: bool :=
+
+ let v__618 := arg_ in
+ if ((eq_vec v__618 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))
+ then
+ true
+ else if ((andb
+ (let nz96 : bits 4 := subrange_vec_dec v__618 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__618 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__618 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__618 6 6 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 32)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let nzi9 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__618 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__618 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__618 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__618 6 6 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 7)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (11 - 7 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B0;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B0;B1] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B1;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5)
+ (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5)
+ (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 32 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 32 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs2 : regidx := subrange_vec_dec v__618 6 2 in
+ let rd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((eq_vec v__618
+ (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__618 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else true.
+
+Definition execute_WFI '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | Machine => (platform_wfi tt) >> returnm (RETIRE_SUCCESS : Retired)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ (if ((eq_vec (_get_Mstatus_TW w__1) ((bool_to_bits true) : mword 1))) then
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else (platform_wfi tt) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ | User => (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition execute_UTYPE (imm : mword 20) (rd : mword 5) (op : uop)
+: M (Retired) :=
+
+ let off : xlenbits :=
+ EXTS 32 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)) in
+ (match op with
+ | RISCV_LUI => returnm (off : mword 32)
+ | RISCV_AUIPC =>
+ (get_arch_pc tt) >>= fun w__0 : mword 32 => returnm ((add_vec w__0 off) : mword 32)
+ end) >>= fun ret : xlenbits =>
+ (wX (projT1 (regidx_to_regno rd)) ret) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_URET '(tt : unit)
+: M (Retired) :=
+
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool ((negb w__0)) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__2 : mword 32 =>
+ (exception_handler w__1 (CTL_URET (tt)) w__2) >>= fun w__3 : mword 32 =>
+ (set_next_pc w__3)
+ : M (unit)) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_STORECON
+(aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5)
+: M (Retired) :=
+
+ (speculate_conditional tt) >>= fun w__0 : bool =>
+ (if ((Bool.eqb w__0 false)) then
+ (wX (projT1 (regidx_to_regno rd)) (EXTZ 32 (vec_of_bits [B1] : mword 1))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else
+ (haveAtomics tt) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (ext_data_get_addr rs1 (zeros_implicit 32) Write width) >>= fun w__2 : Ext_DataAddr_Check unit =>
+ (match w__2 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (match width with
+ | BYTE =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | HALF =>
+ (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__3 : mword 1 =>
+ returnm ((eq_vec w__3 (vec_of_bits [B0] : mword 1))
+ : bool)
+ | WORD =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ : bool)
+ | DOUBLE =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 2 0)
+ (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))
+ : bool)
+ end) >>= fun aligned : bool =>
+ (if sumbool_of_bool ((negb aligned)) then
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else if ((Bool.eqb (match_reservation vaddr) false)) then
+ (wX (projT1 (regidx_to_regno rd)) (EXTZ 32 (vec_of_bits [B1] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else
+ (translateAddr vaddr Write) >>= fun w__4 : TR_Result (mword 32) ExceptionType =>
+ (match w__4 with
+ | TR_Failure (e) =>
+ (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 32) with
+ | (WORD, _) => (mem_write_ea addr 4 aq rl true) : M (MemoryOpResult unit)
+ | _ =>
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ (match (width, 32) with
+ | (WORD, _) =>
+ (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl true)
+ : M (MemoryOpResult bool)
+ | _ =>
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult bool)
+ end) >>= fun res : MemoryOpResult bool =>
+ (match res with
+ | MemValue (true) =>
+ (wX (projT1 (regidx_to_regno rd))
+ (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemValue (false) =>
+ (wX (projT1 (regidx_to_regno rd))
+ (EXTZ 32 (vec_of_bits [B1] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired))
+ : M (Retired).
+
+Definition execute_STORE
+(imm : mword 12) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (aq : bool) (rl : bool)
+: M (Retired) :=
+
+ let offset : xlenbits := EXTS 32 imm in
+ (ext_data_get_addr rs1 offset Write width) >>= fun w__0 : Ext_DataAddr_Check unit =>
+ (match w__0 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (check_misaligned vaddr width) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Write) >>= fun w__2 : TR_Result (mword 32) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match width with
+ | BYTE => (mem_write_ea addr 1 aq rl false) : M (MemoryOpResult unit)
+ | HALF => (mem_write_ea addr 2 aq rl false) : M (MemoryOpResult unit)
+ | WORD => (mem_write_ea addr 4 aq rl false) : M (MemoryOpResult unit)
+ | DOUBLE => (mem_write_ea addr 8 aq rl false) : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ (match (width, 32) with
+ | (BYTE, _) =>
+ (mem_write_value addr 1 (subrange_vec_dec rs2_val 7 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | (HALF, _) =>
+ (mem_write_value addr 2 (subrange_vec_dec rs2_val 15 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | (WORD, _) =>
+ (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | _ => exit tt : M (MemoryOpResult bool)
+ end) >>= fun res : MemoryOpResult bool =>
+ (match res with
+ | MemValue (true) => returnm (RETIRE_SUCCESS : Retired)
+ | MemValue (false) =>
+ (internal_error "store got false from mem_write_value") : M (Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_SRET '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | User => (handle_illegal tt) : M (unit)
+ | Supervisor =>
+ (or_boolM ((haveSupMode tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))
+ (read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_TSR w__2) ((bool_to_bits true) : mword 1))
+ : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__4 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__5 : mword 32 =>
+ (exception_handler w__4 (CTL_SRET (tt)) w__5) >>= fun w__6 : mword 32 =>
+ (set_next_pc w__6)
+ : M (unit))
+ : M (unit)
+ | Machine =>
+ (haveSupMode tt) >>= fun w__7 : bool =>
+ (if sumbool_of_bool ((negb w__7)) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__8 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__9 : mword 32 =>
+ (exception_handler w__8 (CTL_SRET (tt)) w__9) >>= fun w__10 : mword 32 =>
+ (set_next_pc w__10)
+ : M (unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_SHIFTW (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 32 =>
+ let rs1_val := subrange_vec_dec w__0 31 0 in
+ let result : bits 32 :=
+ match op with
+ | RISCV_SLLI => shift_bits_left rs1_val shamt
+ | RISCV_SRLI => shift_bits_right rs1_val shamt
+ | RISCV_SRAI => shift_right_arith32 rs1_val shamt
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SHIFTIWOP (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sopw)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let result : bits 32 :=
+ match op with
+ | RISCV_SLLIW => shift_bits_left (subrange_vec_dec rs1_val 31 0) shamt
+ | RISCV_SRLIW => shift_bits_right (subrange_vec_dec rs1_val 31 0) shamt
+ | RISCV_SRAIW => shift_right_arith32 (subrange_vec_dec rs1_val 31 0) shamt
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SHIFTIOP (shamt : mword 6) (rs1 : mword 5) (rd : mword 5) (op : sop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let result : xlenbits :=
+ match op with
+ | RISCV_SLLI => shift_bits_left rs1_val (subrange_vec_dec shamt 4 0)
+ | RISCV_SRLI => shift_bits_right rs1_val (subrange_vec_dec shamt 4 0)
+ | RISCV_SRAI => shift_right_arith32 rs1_val (subrange_vec_dec shamt 4 0)
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SFENCE_VMA (rs1 : mword 5) (rs2 : mword 5)
+: M (Retired) :=
+
+ (if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then
+ returnm (None
+ : option (mword 32))
+ else
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 32 =>
+ returnm ((Some
+ (w__0))
+ : option (mword 32))) >>= fun addr : option xlenbits =>
+ (if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then
+ returnm (None
+ : option (mword 32))
+ else
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__1 : mword 32 =>
+ returnm ((Some
+ (w__1))
+ : option (mword 32))) >>= fun asid : option xlenbits =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (match w__2 with
+ | User => (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__3 : Mstatus =>
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ let p__215 := (architecture (get_mstatus_SXL w__3), _get_Mstatus_TVM w__4) in
+ (match p__215 with
+ | (Some (g__214), v_0) =>
+ (if ((eq_vec v_0 ((bool_to_bits true) : mword 1))) then
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else if ((eq_vec v_0 ((bool_to_bits false) : mword 1))) then
+ (flush_TLB asid addr) >> returnm (RETIRE_SUCCESS : Retired)
+ else
+ (match (Some
+ (g__214), v_0) with
+ | (_, _) => (internal_error "unimplemented sfence architecture") : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ | (_, _) => (internal_error "unimplemented sfence architecture") : M (Retired)
+ end)
+ : M (Retired)
+ | Machine => (flush_TLB asid addr) >> returnm (RETIRE_SUCCESS : Retired)
+ end)
+ : M (Retired).
+
+Definition execute_RTYPEW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : ropw)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 32 =>
+ let rs1_val := subrange_vec_dec w__0 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__1 : mword 32 =>
+ let rs2_val := subrange_vec_dec w__1 31 0 in
+ let result : bits 32 :=
+ match op with
+ | RISCV_ADDW => add_vec rs1_val rs2_val
+ | RISCV_SUBW => sub_vec rs1_val rs2_val
+ | RISCV_SLLW => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SRLW => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SRAW => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0)
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_RTYPE (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : rop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let result : xlenbits :=
+ match op with
+ | RISCV_ADD => add_vec rs1_val rs2_val
+ | RISCV_SLT => EXTZ 32 (bool_to_bits (zopz0zI_s rs1_val rs2_val))
+ | RISCV_SLTU => EXTZ 32 (bool_to_bits (zopz0zI_u rs1_val rs2_val))
+ | RISCV_AND => and_vec rs1_val rs2_val
+ | RISCV_OR => or_vec rs1_val rs2_val
+ | RISCV_XOR => xor_vec rs1_val rs2_val
+ | RISCV_SLL => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SRL => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SUB => sub_vec rs1_val rs2_val
+ | RISCV_SRA => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0)
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_RISCV_JALR (imm : mword 12) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 32 =>
+ let t : xlenbits := add_vec w__0 (EXTS 32 imm) in
+ (match (ext_control_check_addr t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (addr) =>
+ let target := update_vec_dec addr 0 B0 in
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (get_next_pc tt) >>= fun w__4 : mword 32 =>
+ (wX (projT1 (regidx_to_regno rd)) w__4) >>
+ (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_RISCV_JAL (imm : mword 21) (rd : mword 5)
+: M (Retired) :=
+
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ let t : xlenbits := add_vec w__0 (EXTS 32 imm) in
+ (match (ext_control_check_pc t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (target) =>
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (get_next_pc tt) >>= fun w__4 : mword 32 =>
+ (wX (projT1 (regidx_to_regno rd)) w__4) >>
+ (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_REMW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 32 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 32 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let r : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int else Z.rem rs1_int rs2_int in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 (to_bits 32 r))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_REM (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let r : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int else Z.rem rs1_int rs2_int in
+ (wX (projT1 (regidx_to_regno rd)) (to_bits 32 r)) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MULW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 32 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 32 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z := projT1 (sint rs1_val) in
+ let rs2_int : Z := projT1 (sint rs2_val) in
+ let result32 := subrange_vec_dec (to_bits 64 (Z.mul rs1_int rs2_int)) 31 0 in
+ let result : xlenbits := EXTS 32 result32 in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MUL
+(rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (high : bool) (signed1 : bool) (signed2 : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (signed1) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (signed2) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let result_wide := to_bits (Z.mul 2 32) (Z.mul rs1_int rs2_int) in
+ let result :=
+ if sumbool_of_bool (high) then subrange_vec_dec result_wide (Z.sub (Z.mul 2 32) 1) 32
+ else subrange_vec_dec result_wide (Z.sub 32 1) 0 in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MRET '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits Machine) : mword 2))) then
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__2 : mword 32 =>
+ (exception_handler w__1 (CTL_MRET (tt)) w__2) >>= fun w__3 : mword 32 =>
+ (set_next_pc w__3)
+ : M (unit)
+ else (handle_illegal tt) : M (unit)) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_LOADRES
+(aq : bool) (rl : bool) (rs1 : mword 5) (width : word_width) (rd : mword 5)
+: M (Retired) :=
+
+ (haveAtomics tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (ext_data_get_addr rs1 (zeros_implicit 32) Read width) >>= fun w__1 : Ext_DataAddr_Check unit =>
+ (match w__1 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (match width with
+ | BYTE => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | HALF =>
+ (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__2 : mword 1 =>
+ returnm ((eq_vec w__2 (vec_of_bits [B0] : mword 1))
+ : bool)
+ | WORD =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ : bool)
+ | DOUBLE =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 2 0)
+ (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))
+ : bool)
+ end) >>= fun aligned : bool =>
+ (if sumbool_of_bool ((negb aligned)) then
+ (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Read) >>= fun w__3 : TR_Result (mword 32) ExceptionType =>
+ (match w__3 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 32) with
+ | (WORD, _) =>
+ (mem_read Read addr 4 aq rl true) >>= fun w__4 : MemoryOpResult (mword (8 * 4)) =>
+ (process_loadres rd vaddr w__4 false)
+ : M (Retired)
+ | _ => (internal_error "LOADRES expected WORD or DOUBLE") : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_LOAD
+(imm : mword 12) (rs1 : mword 5) (rd : mword 5) (is_unsigned : bool) (width : word_width)
+(aq : bool) (rl : bool)
+: M (Retired) :=
+
+ let offset : xlenbits := EXTS 32 imm in
+ (ext_data_get_addr rs1 offset Read width) >>= fun w__0 : Ext_DataAddr_Check unit =>
+ (match w__0 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (check_misaligned vaddr width) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Read) >>= fun w__2 : TR_Result (mword 32) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 32) with
+ | (BYTE, _) =>
+ (mem_read Read addr 1 aq rl false) >>= fun w__3 : MemoryOpResult (mword (8 * 1)) =>
+ (process_load rd vaddr w__3 is_unsigned)
+ : M (Retired)
+ | (HALF, _) =>
+ (mem_read Read addr 2 aq rl false) >>= fun w__5 : MemoryOpResult (mword (8 * 2)) =>
+ (process_load rd vaddr w__5 is_unsigned)
+ : M (Retired)
+ | (WORD, _) =>
+ (mem_read Read addr 4 aq rl false) >>= fun w__7 : MemoryOpResult (mword (8 * 4)) =>
+ (process_load rd vaddr w__7 is_unsigned)
+ : M (Retired)
+ | _ => exit tt : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_ITYPE (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (op : iop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let immext : xlenbits := EXTS 32 imm in
+ let result : xlenbits :=
+ match op with
+ | RISCV_ADDI => add_vec rs1_val immext
+ | RISCV_SLTI => EXTZ 32 (bool_to_bits (zopz0zI_s rs1_val immext))
+ | RISCV_SLTIU => EXTZ 32 (bool_to_bits (zopz0zI_u rs1_val immext))
+ | RISCV_ANDI => and_vec rs1_val immext
+ | RISCV_ORI => or_vec rs1_val immext
+ | RISCV_XORI => xor_vec rs1_val immext
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_ILLEGAL (s : mword 32)
+: M (Retired) :=
+
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_FENCE_TSO (pred : mword 4) (succ : mword 4)
+: M (Retired) :=
+
+ (match (pred, succ) with
+ | (v__794, v__795) =>
+ (if ((andb (eq_vec (subrange_vec_dec v__794 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__795 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_tso (tt)))
+ : M (unit)
+ else
+ returnm ((if ((andb
+ (eq_vec (subrange_vec_dec v__794 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__795 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then
+ tt
+ else
+ let '_ := (print_endline "FIXME: unsupported fence") : unit in
+ tt)
+ : unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition execute_FENCEI '(tt : unit) : Retired := RETIRE_SUCCESS.
+
+Definition execute_FENCE (pred : mword 4) (succ : mword 4)
+: M (Retired) :=
+
+ (match (pred, succ) with
+ | (v__754, v__755) =>
+ (if ((andb (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_r (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_r (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_r (tt)))
+ : M (unit)
+ else
+ returnm ((if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then
+ tt
+ else
+ let '_ := (print_endline "FIXME: unsupported fence") : unit in
+ tt)
+ : unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition execute_ECALL '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ let t : sync_exception :=
+ {| sync_exception_trap :=
+ (match w__0 with
+ | User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ end);
+ sync_exception_excinfo := (None : option xlenbits);
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__2 : mword 32 =>
+ (exception_handler w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 32 =>
+ (set_next_pc w__3) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_EBREAK '(tt : unit)
+: M (Retired) :=
+
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ (handle_mem_exception w__0 E_Breakpoint) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_DIVW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 32 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 32 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) else Z.quot rs1_int rs2_int in
+ let q' : Z :=
+ if sumbool_of_bool ((andb s (Z.gtb q (Z.sub (projT1 (pow2 31)) 1)))) then Z.sub 0 (pow 2 31)
+ else q in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 (to_bits 32 q'))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_DIV (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) else Z.quot rs1_int rs2_int in
+ let q' : Z :=
+ if sumbool_of_bool ((andb s (Z.gtb q xlen_max_signed))) then xlen_min_signed
+ else q in
+ (wX (projT1 (regidx_to_regno rd)) (to_bits 32 q')) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_C_NOP '(tt : unit) : Retired := RETIRE_SUCCESS.
+
+Definition execute_C_ILLEGAL (s : mword 16)
+: M (Retired) :=
+
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_CSR (csr : mword 12) (rs1 : mword 5) (rd : mword 5) (is_imm : bool) (op : csrop)
+: M (Retired) :=
+
+ (if sumbool_of_bool (is_imm) then returnm ((EXTZ 32 rs1) : mword 32)
+ else (rX (projT1 (regidx_to_regno rs1))) : M (mword 32)) >>= fun rs1_val : xlenbits =>
+ let isWrite : bool :=
+ match op with
+ | CSRRW => true
+ | _ =>
+ if sumbool_of_bool (is_imm) then projT1 (neq_int (projT1 (uint rs1_val)) 0)
+ else projT1 (neq_int (projT1 (uint rs1)) 0)
+ end in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ (check_CSR csr w__1 isWrite) >>= fun w__2 : bool =>
+ (if sumbool_of_bool ((negb w__2)) then (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (readCSR csr) >>= fun csr_val =>
+ (if sumbool_of_bool (isWrite) then
+ let new_val : xlenbits :=
+ match op with
+ | CSRRW => rs1_val
+ | CSRRS => or_vec csr_val rs1_val
+ | CSRRC => and_vec csr_val (not_vec rs1_val)
+ end in
+ (writeCSR csr new_val)
+ : M (unit)
+ else returnm (tt : unit)) >>
+ (wX (projT1 (regidx_to_regno rd)) csr_val) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired).
+
+Definition execute_BTYPE (imm : mword 13) (rs2 : mword 5) (rs1 : mword 5) (op : bop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let taken : bool :=
+ match op with
+ | RISCV_BEQ => eq_vec rs1_val rs2_val
+ | RISCV_BNE => neq_vec rs1_val rs2_val
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ end in
+ ((read_reg PC_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ let t : xlenbits := add_vec w__0 (EXTS 32 imm) in
+ (if sumbool_of_bool (taken) then
+ (match (ext_control_check_pc t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (target) =>
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired).
+
+Definition execute_AMO
+(op : amoop) (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width)
+(rd : mword 5)
+: M (Retired) :=
+
+ (haveAtomics tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (ext_data_get_addr rs1 (zeros_implicit 32) ReadWrite width) >>= fun w__1 : Ext_DataAddr_Check unit =>
+ (match w__1 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (translateAddr vaddr ReadWrite) >>= fun w__2 : TR_Result (mword 32) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 32) with
+ | (WORD, _) => (mem_write_ea addr 4 (andb aq rl) rl true) : M (MemoryOpResult unit)
+ | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val : xlenbits =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (match (width, 32) with
+ | (WORD, _) =>
+ (mem_read ReadWrite addr 4 aq (andb aq rl) true) >>= fun w__5 : MemoryOpResult (mword (8 * 4)) =>
+ returnm ((extend_value false w__5)
+ : MemoryOpResult (mword 32))
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE")
+ : M (MemoryOpResult (mword 32))
+ end) >>= fun rval : MemoryOpResult xlenbits =>
+ (match rval with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (loaded) =>
+ let result : xlenbits :=
+ match op with
+ | AMOSWAP => rs2_val
+ | AMOADD => add_vec rs2_val loaded
+ | AMOXOR => xor_vec rs2_val loaded
+ | AMOAND => and_vec rs2_val loaded
+ | AMOOR => or_vec rs2_val loaded
+ | AMOMIN =>
+ to_bits 32 (Z.min (projT1 (sint rs2_val)) (projT1 (sint loaded)))
+ | AMOMAX =>
+ to_bits 32 (Z.max (projT1 (sint rs2_val)) (projT1 (sint loaded)))
+ | AMOMINU =>
+ to_bits 32
+ (projT1
+ (min_nat (projT1 (uint rs2_val)) (projT1 (uint loaded))))
+ | AMOMAXU =>
+ to_bits 32
+ (projT1
+ (max_nat (projT1 (uint rs2_val)) (projT1 (uint loaded))))
+ end in
+ (match (width, 32) with
+ | (WORD, _) =>
+ (mem_write_value addr 4 (subrange_vec_dec result 31 0) (andb aq rl) rl
+ true)
+ : M (MemoryOpResult bool)
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult bool)
+ end) >>= fun wval : MemoryOpResult bool =>
+ (match wval with
+ | MemValue (true) =>
+ (wX (projT1 (regidx_to_regno rd)) loaded) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemValue (false) =>
+ (internal_error "AMO got false from mem_write_value") : M (Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_ADDIW (imm : mword 12) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 32 =>
+ let result : xlenbits := add_vec (EXTS 32 imm) w__0 in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 32 (subrange_vec_dec result 31 0))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition compressed_measure (instr : ast)
+: Z :=
+
+ match instr with
+ | C_ADDI4SPN ((rdc, nzimm)) => 1
+ | C_LW ((uimm, rsc, rdc)) => 1
+ | C_LD ((uimm, rsc, rdc)) => 1
+ | C_SW ((uimm, rsc1, rsc2)) => 1
+ | C_SD ((uimm, rsc1, rsc2)) => 1
+ | C_ADDI ((nzi, rsd)) => 1
+ | C_JAL (imm) => 1
+ | C_LI ((imm, rd)) => 1
+ | C_ADDI16SP (imm) => 1
+ | C_LUI ((imm, rd)) => 1
+ | C_SRLI ((shamt, rsd)) => 1
+ | C_SRAI ((shamt, rsd)) => 1
+ | C_ANDI ((imm, rsd)) => 1
+ | C_SUB ((rsd, rs2)) => 1
+ | C_XOR ((rsd, rs2)) => 1
+ | C_OR ((rsd, rs2)) => 1
+ | C_AND ((rsd, rs2)) => 1
+ | C_SUBW ((rsd, rs2)) => 1
+ | C_ADDW ((rsd, rs2)) => 1
+ | C_J (imm) => 1
+ | C_BEQZ ((imm, rs)) => 1
+ | C_BNEZ ((imm, rs)) => 1
+ | C_SLLI ((shamt, rsd)) => 1
+ | C_LWSP ((uimm, rd)) => 1
+ | C_LDSP ((uimm, rd)) => 1
+ | C_SWSP ((uimm, rs2)) => 1
+ | C_SDSP ((uimm, rs2)) => 1
+ | C_JR (rs1) => 1
+ | C_JALR (rs1) => 1
+ | C_MV ((rd, rs2)) => 1
+ | C_EBREAK (tt') => 1
+ | C_ADD ((rsd, rs2)) => 1
+ | _ => 0
+ end.
+
+Fixpoint _rec_execute (merge_var : ast) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M (Retired) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ (match merge_var with
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ let imm : bits 12 :=
+ concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rd := creg2reg_idx rdc in
+ (_rec_execute (ITYPE ((imm, sp, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LW ((uimm, rsc, rdc)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rd := creg2reg_idx rdc in
+ let rs := creg2reg_idx rsc in
+ (_rec_execute (LOAD ((imm, rs, rd, false, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LD ((uimm, rsc, rdc)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ let rd := creg2reg_idx rdc in
+ let rs := creg2reg_idx rsc in
+ (_rec_execute (LOAD ((imm, rs, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rs1 := creg2reg_idx rsc1 in
+ let rs2 := creg2reg_idx rsc2 in
+ (_rec_execute (STORE ((imm, rs2, rs1, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ let rs1 := creg2reg_idx rsc1 in
+ let rs2 := creg2reg_idx rsc2 in
+ (_rec_execute (STORE ((imm, rs2, rs1, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDI ((nzi, rsd)) =>
+ let imm : bits 12 := EXTS 12 nzi in
+ (_rec_execute (ITYPE ((imm, rsd, rsd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_JAL (imm) =>
+ (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDIW ((imm, rsd)) =>
+ (_rec_execute (ADDIW ((EXTS 12 imm, rsd, rsd))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LI ((imm, rd)) =>
+ let imm : bits 12 := EXTS 12 imm in
+ (_rec_execute (ITYPE ((imm, zreg, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDI16SP (imm) =>
+ let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in
+ (_rec_execute (ITYPE ((imm, sp, sp, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LUI ((imm, rd)) =>
+ let res : bits 20 := EXTS 20 imm in
+ (_rec_execute (UTYPE ((res, rd, RISCV_LUI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SRLI ((shamt, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SRAI ((shamt, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ANDI ((imm, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SUB ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_SUB))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_XOR ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_XOR))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_OR ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_OR))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_AND ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_AND))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SUBW ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_SUBW))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDW ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_ADDW))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_J (imm) =>
+ (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_BEQZ ((imm, rs)) =>
+ (_rec_execute
+ (BTYPE
+ ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_idx rs, RISCV_BEQ)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_BNEZ ((imm, rs)) =>
+ (_rec_execute
+ (BTYPE
+ ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_idx rs, RISCV_BNE)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SLLI ((shamt, rsd)) =>
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LWSP ((uimm, rd)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ (_rec_execute (LOAD ((imm, sp, rd, false, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LDSP ((uimm, rd)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ (_rec_execute (LOAD ((imm, sp, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SWSP ((uimm, rs2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ (_rec_execute (STORE ((imm, rs2, sp, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SDSP ((uimm, rs2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ (_rec_execute (STORE ((imm, rs2, sp, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_JR (rs1) =>
+ (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_JALR (rs1) =>
+ (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_MV ((rd, rs2)) =>
+ (_rec_execute (RTYPE ((rs2, zreg, rd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_EBREAK (tt) =>
+ (_rec_execute (EBREAK (tt)) (Z.sub _reclimit 1) (_limit_reduces _acc)) : M (Retired)
+ | C_ADD ((rsd, rs2)) =>
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | UTYPE ((imm, rd, op)) => (execute_UTYPE imm rd op) : M (Retired)
+ | RISCV_JAL ((imm, rd)) => (execute_RISCV_JAL imm rd) : M (Retired)
+ | BTYPE ((imm, rs2, rs1, op)) => (execute_BTYPE imm rs2 rs1 op) : M (Retired)
+ | ITYPE ((imm, rs1, rd, op)) => (execute_ITYPE imm rs1 rd op) : M (Retired)
+ | SHIFTIOP ((shamt, rs1, rd, op)) => (execute_SHIFTIOP shamt rs1 rd op) : M (Retired)
+ | RTYPE ((rs2, rs1, rd, op)) => (execute_RTYPE rs2 rs1 rd op) : M (Retired)
+ | LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl)) =>
+ (execute_LOAD imm rs1 rd is_unsigned width aq rl) : M (Retired)
+ | STORE ((imm, rs2, rs1, width, aq, rl)) =>
+ (execute_STORE imm rs2 rs1 width aq rl) : M (Retired)
+ | ADDIW ((imm, rs1, rd)) => (execute_ADDIW imm rs1 rd) : M (Retired)
+ | SHIFTW ((shamt, rs1, rd, op)) => (execute_SHIFTW shamt rs1 rd op) : M (Retired)
+ | RTYPEW ((rs2, rs1, rd, op)) => (execute_RTYPEW rs2 rs1 rd op) : M (Retired)
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => (execute_SHIFTIWOP shamt rs1 rd op) : M (Retired)
+ | FENCE ((pred, succ)) => (execute_FENCE pred succ) : M (Retired)
+ | FENCE_TSO ((pred, succ)) => (execute_FENCE_TSO pred succ) : M (Retired)
+ | FENCEI (arg0) => returnm ((execute_FENCEI arg0) : Retired)
+ | ECALL (arg0) => (execute_ECALL arg0) : M (Retired)
+ | MRET (arg0) => (execute_MRET arg0) : M (Retired)
+ | SRET (arg0) => (execute_SRET arg0) : M (Retired)
+ | EBREAK (arg0) => (execute_EBREAK arg0) : M (Retired)
+ | WFI (arg0) => (execute_WFI arg0) : M (Retired)
+ | SFENCE_VMA ((rs1, rs2)) => (execute_SFENCE_VMA rs1 rs2) : M (Retired)
+ | LOADRES ((aq, rl, rs1, width, rd)) => (execute_LOADRES aq rl rs1 width rd) : M (Retired)
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) =>
+ (execute_STORECON aq rl rs2 rs1 width rd) : M (Retired)
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ (execute_AMO op aq rl rs2 rs1 width rd) : M (Retired)
+ | C_NOP (arg0) => returnm ((execute_C_NOP arg0) : Retired)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (execute_MUL rs2 rs1 rd high signed1 signed2) : M (Retired)
+ | DIV ((rs2, rs1, rd, s)) => (execute_DIV rs2 rs1 rd s) : M (Retired)
+ | REM ((rs2, rs1, rd, s)) => (execute_REM rs2 rs1 rd s) : M (Retired)
+ | MULW ((rs2, rs1, rd)) => (execute_MULW rs2 rs1 rd) : M (Retired)
+ | DIVW ((rs2, rs1, rd, s)) => (execute_DIVW rs2 rs1 rd s) : M (Retired)
+ | REMW ((rs2, rs1, rd, s)) => (execute_REMW rs2 rs1 rd s) : M (Retired)
+ | CSR ((csr, rs1, rd, is_imm, op)) => (execute_CSR csr rs1 rd is_imm op) : M (Retired)
+ | URET (arg0) => (execute_URET arg0) : M (Retired)
+ | RISCV_JALR ((imm, rs1, rd)) => (execute_RISCV_JALR imm rs1 rd) : M (Retired)
+ | ILLEGAL (s) => (execute_ILLEGAL s) : M (Retired)
+ | C_ILLEGAL (s) => (execute_C_ILLEGAL s) : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute (i : ast)
+: M (Retired) :=
+
+ (_rec_execute i ((compressed_measure i) : Z) (Zwf_guarded _))
+ : M (Retired).
+
+Definition assembly_forwards (arg_ : ast)
+: M (string) :=
+
+ (match arg_ with
+ | UTYPE ((imm, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__0 : string =>
+ returnm ((string_append (utype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__0
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | RISCV_JAL ((imm, rd)) =>
+ (reg_name_forwards rd) >>= fun w__1 : string =>
+ returnm ((string_append "jal"
+ (string_append (spc_forwards tt)
+ (string_append w__1
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ (reg_name_forwards rd) >>= fun w__2 : string =>
+ (reg_name_forwards rs1) >>= fun w__3 : string =>
+ returnm ((string_append "jalr"
+ (string_append (spc_forwards tt)
+ (string_append w__2
+ (string_append (sep_forwards tt)
+ (string_append w__3
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | BTYPE ((imm, rs2, rs1, op)) =>
+ (reg_name_forwards rs1) >>= fun w__4 : string =>
+ (reg_name_forwards rs2) >>= fun w__5 : string =>
+ returnm ((string_append (btype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__4
+ (string_append (sep_forwards tt)
+ (string_append w__5
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | ITYPE ((imm, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__6 : string =>
+ (reg_name_forwards rs1) >>= fun w__7 : string =>
+ returnm ((string_append (itype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__6
+ (string_append (sep_forwards tt)
+ (string_append w__7
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | SHIFTIOP ((shamt, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__8 : string =>
+ (reg_name_forwards rs1) >>= fun w__9 : string =>
+ returnm ((string_append (shiftiop_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__8
+ (string_append (sep_forwards tt)
+ (string_append w__9
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ | RTYPE ((rs2, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__10 : string =>
+ (reg_name_forwards rs1) >>= fun w__11 : string =>
+ (reg_name_forwards rs2) >>= fun w__12 : string =>
+ returnm ((string_append (rtype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__10
+ (string_append (sep_forwards tt)
+ (string_append w__11
+ (string_append (sep_forwards tt) (string_append w__12 "")))))))
+ : string)
+ | LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl)) =>
+ (reg_name_forwards rd) >>= fun w__13 : string =>
+ (reg_name_forwards rs1) >>= fun w__14 : string =>
+ returnm ((string_append "l"
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_u_forwards is_unsigned)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__13
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm)
+ (string_append (opt_spc_forwards tt)
+ (string_append "("
+ (string_append (opt_spc_forwards tt)
+ (string_append w__14
+ (string_append (opt_spc_forwards tt)
+ (string_append ")" "")))))))))))))))
+ : string)
+ | STORE ((imm, rs2, rs1, size, aq, rl)) =>
+ (reg_name_forwards rs2) >>= fun w__15 : string =>
+ (reg_name_forwards rs1) >>= fun w__16 : string =>
+ returnm ((string_append "s"
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__15
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm)
+ (string_append (opt_spc_forwards tt)
+ (string_append "("
+ (string_append (opt_spc_forwards tt)
+ (string_append w__16
+ (string_append (opt_spc_forwards tt)
+ (string_append ")" ""))))))))))))))
+ : string)
+ | ADDIW ((imm, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__17 : string =>
+ (reg_name_forwards rs1) >>= fun w__18 : string =>
+ returnm ((string_append "addiw"
+ (string_append (spc_forwards tt)
+ (string_append w__17
+ (string_append (sep_forwards tt)
+ (string_append w__18
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__21 : string =>
+ (reg_name_forwards rs1) >>= fun w__22 : string =>
+ returnm ((string_append (shiftw_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__21
+ (string_append (sep_forwards tt)
+ (string_append w__22
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__25 : string =>
+ (reg_name_forwards rs1) >>= fun w__26 : string =>
+ (reg_name_forwards rs2) >>= fun w__27 : string =>
+ returnm ((string_append (rtypew_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__25
+ (string_append (sep_forwards tt)
+ (string_append w__26
+ (string_append (sep_forwards tt) (string_append w__27 "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__30 : string =>
+ (reg_name_forwards rs1) >>= fun w__31 : string =>
+ returnm ((string_append (shiftiwop_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__30
+ (string_append (sep_forwards tt)
+ (string_append w__31
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | FENCE ((pred, succ)) =>
+ (fence_bits_forwards pred) >>= fun w__34 : string =>
+ (fence_bits_forwards succ) >>= fun w__35 : string =>
+ returnm ((string_append "fence"
+ (string_append (spc_forwards tt)
+ (string_append w__34
+ (string_append (sep_forwards tt) (string_append w__35 "")))))
+ : string)
+ | FENCE_TSO ((pred, succ)) =>
+ (fence_bits_forwards pred) >>= fun w__36 : string =>
+ (fence_bits_forwards succ) >>= fun w__37 : string =>
+ returnm ((string_append "fence.tso"
+ (string_append (spc_forwards tt)
+ (string_append w__36
+ (string_append (sep_forwards tt) (string_append w__37 "")))))
+ : string)
+ | FENCEI (tt) => returnm ("fence.i" : string)
+ | ECALL (tt) => returnm ("ecall" : string)
+ | MRET (tt) => returnm ("mret" : string)
+ | SRET (tt) => returnm ("sret" : string)
+ | EBREAK (tt) => returnm ("ebreak" : string)
+ | WFI (tt) => returnm ("wfi" : string)
+ | SFENCE_VMA ((rs1, rs2)) =>
+ (reg_name_forwards rs1) >>= fun w__38 : string =>
+ (reg_name_forwards rs2) >>= fun w__39 : string =>
+ returnm ((string_append "sfence.vma"
+ (string_append (spc_forwards tt)
+ (string_append w__38
+ (string_append (sep_forwards tt) (string_append w__39 "")))))
+ : string)
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ (reg_name_forwards rd) >>= fun w__40 : string =>
+ (reg_name_forwards rs1) >>= fun w__41 : string =>
+ returnm ((string_append "lr."
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__40
+ (string_append (sep_forwards tt) (string_append w__41 ""))))))))
+ : string)
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ (reg_name_forwards rd) >>= fun w__42 : string =>
+ (reg_name_forwards rs1) >>= fun w__43 : string =>
+ (reg_name_forwards rs2) >>= fun w__44 : string =>
+ returnm ((string_append "sc."
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__42
+ (string_append (sep_forwards tt)
+ (string_append w__43
+ (string_append (sep_forwards tt) (string_append w__44 ""))))))))))
+ : string)
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ (reg_name_forwards rd) >>= fun w__45 : string =>
+ (reg_name_forwards rs1) >>= fun w__46 : string =>
+ (reg_name_forwards rs2) >>= fun w__47 : string =>
+ returnm ((string_append (amo_mnemonic_forwards op)
+ (string_append "."
+ (string_append (size_mnemonic_forwards width)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__45
+ (string_append (sep_forwards tt)
+ (string_append w__46
+ (string_append (sep_forwards tt) (string_append w__47 "")))))))))))
+ : string)
+ | C_NOP (tt) => returnm ("c.nop" : string)
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ (if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then
+ (creg_name_forwards rdc) >>= fun w__48 : string =>
+ returnm ((string_append "c.addi4spn"
+ (string_append (spc_forwards tt)
+ (string_append w__48
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (nzimm : mword 8) (vec_of_bits [B0;B0] : mword 2)))
+ "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LW ((uimm, rsc, rdc)) =>
+ (creg_name_forwards rdc) >>= fun w__51 : string =>
+ (creg_name_forwards rsc) >>= fun w__52 : string =>
+ returnm ((string_append "c.lw"
+ (string_append (spc_forwards tt)
+ (string_append w__51
+ (string_append (sep_forwards tt)
+ (string_append w__52
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0] : mword 2))) "")))))))
+ : string)
+ | C_LD ((uimm, rsc, rdc)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (creg_name_forwards rdc) >>= fun w__53 : string =>
+ (creg_name_forwards rsc) >>= fun w__54 : string =>
+ returnm ((string_append "c.ld"
+ (string_append (spc_forwards tt)
+ (string_append w__53
+ (string_append (sep_forwards tt)
+ (string_append w__54
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0;B0] : mword 3))) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ (creg_name_forwards rsc1) >>= fun w__57 : string =>
+ (creg_name_forwards rsc2) >>= fun w__58 : string =>
+ returnm ((string_append "c.sw"
+ (string_append (spc_forwards tt)
+ (string_append w__57
+ (string_append (sep_forwards tt)
+ (string_append w__58
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0] : mword 2))) "")))))))
+ : string)
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (creg_name_forwards rsc1) >>= fun w__59 : string =>
+ (creg_name_forwards rsc2) >>= fun w__60 : string =>
+ returnm ((string_append "c.sd"
+ (string_append (spc_forwards tt)
+ (string_append w__59
+ (string_append (sep_forwards tt)
+ (string_append w__60
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0;B0] : mword 3))) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDI ((nzi, rsd)) =>
+ (if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__63 : string =>
+ returnm ((string_append "c.addi"
+ (string_append (spc_forwards tt)
+ (string_append w__63
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits nzi) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JAL (imm) =>
+ (if sumbool_of_bool ((Z.eqb 32 32)) then
+ returnm ((string_append "c.jal"
+ (string_append (spc_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (imm : mword 11) (vec_of_bits [B0] : mword 1))) "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDIW ((imm, rsd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rsd) >>= fun w__68 : string =>
+ returnm ((string_append "c.addiw"
+ (string_append (spc_forwards tt)
+ (string_append w__68
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LI ((imm, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rd) >>= fun w__71 : string =>
+ returnm ((string_append "c.li"
+ (string_append (spc_forwards tt)
+ (string_append w__71
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDI16SP (imm) =>
+ (if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ returnm ((string_append "c.addi16sp"
+ (string_append (spc_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LUI ((imm, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))
+ : bool))) then
+ (reg_name_forwards rd) >>= fun w__76 : string =>
+ returnm ((string_append "c.lui"
+ (string_append (spc_forwards tt)
+ (string_append w__76
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SRLI ((shamt, rsd)) =>
+ (if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ (creg_name_forwards rsd) >>= fun w__79 : string =>
+ returnm ((string_append "c.srli"
+ (string_append (spc_forwards tt)
+ (string_append w__79
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SRAI ((shamt, rsd)) =>
+ (if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ (creg_name_forwards rsd) >>= fun w__82 : string =>
+ returnm ((string_append "c.srai"
+ (string_append (spc_forwards tt)
+ (string_append w__82
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ANDI ((imm, rsd)) =>
+ (creg_name_forwards rsd) >>= fun w__85 : string =>
+ returnm ((string_append "c.andi"
+ (string_append (spc_forwards tt)
+ (string_append w__85
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_SUB ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__86 : string =>
+ (creg_name_forwards rs2) >>= fun w__87 : string =>
+ returnm ((string_append "c.sub"
+ (string_append (spc_forwards tt)
+ (string_append w__86
+ (string_append (sep_forwards tt) (string_append w__87 "")))))
+ : string)
+ | C_XOR ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__88 : string =>
+ (creg_name_forwards rs2) >>= fun w__89 : string =>
+ returnm ((string_append "c.xor"
+ (string_append (spc_forwards tt)
+ (string_append w__88
+ (string_append (sep_forwards tt) (string_append w__89 "")))))
+ : string)
+ | C_OR ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__90 : string =>
+ (creg_name_forwards rs2) >>= fun w__91 : string =>
+ returnm ((string_append "c.or"
+ (string_append (spc_forwards tt)
+ (string_append w__90
+ (string_append (sep_forwards tt) (string_append w__91 "")))))
+ : string)
+ | C_AND ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__92 : string =>
+ (creg_name_forwards rs2) >>= fun w__93 : string =>
+ returnm ((string_append "c.and"
+ (string_append (spc_forwards tt)
+ (string_append w__92
+ (string_append (sep_forwards tt) (string_append w__93 "")))))
+ : string)
+ | C_SUBW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (creg_name_forwards rsd) >>= fun w__94 : string =>
+ (creg_name_forwards rs2) >>= fun w__95 : string =>
+ returnm ((string_append "c.subw"
+ (string_append (spc_forwards tt)
+ (string_append w__94
+ (string_append (sep_forwards tt) (string_append w__95 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (creg_name_forwards rsd) >>= fun w__98 : string =>
+ (creg_name_forwards rs2) >>= fun w__99 : string =>
+ returnm ((string_append "c.addw"
+ (string_append (spc_forwards tt)
+ (string_append w__98
+ (string_append (sep_forwards tt) (string_append w__99 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_J (imm) =>
+ returnm ((string_append "c.j"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) "")))
+ : string)
+ | C_BEQZ ((imm, rs)) =>
+ (creg_name_forwards rs) >>= fun w__102 : string =>
+ returnm ((string_append "c.beqz"
+ (string_append (spc_forwards tt)
+ (string_append w__102
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_BNEZ ((imm, rs)) =>
+ (creg_name_forwards rs) >>= fun w__103 : string =>
+ returnm ((string_append "c.bnez"
+ (string_append (spc_forwards tt)
+ (string_append w__103
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_SLLI ((shamt, rsd)) =>
+ (if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__104 : string =>
+ returnm ((string_append "c.slli"
+ (string_append (spc_forwards tt)
+ (string_append w__104
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LWSP ((uimm, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rd) >>= fun w__107 : string =>
+ returnm ((string_append "c.lwsp"
+ (string_append (spc_forwards tt)
+ (string_append w__107
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LDSP ((uimm, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 32 64))) then
+ (reg_name_forwards rd) >>= fun w__110 : string =>
+ returnm ((string_append "c.ldsp"
+ (string_append (spc_forwards tt)
+ (string_append w__110
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SWSP ((uimm, rd)) =>
+ (reg_name_forwards rd) >>= fun w__113 : string =>
+ returnm ((string_append "c.swsp"
+ (string_append (spc_forwards tt)
+ (string_append w__113
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ | C_SDSP ((uimm, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rs2) >>= fun w__114 : string =>
+ returnm ((string_append "c.sdsp"
+ (string_append (spc_forwards tt)
+ (string_append w__114
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rs1) >>= fun w__117 : string =>
+ returnm ((string_append "c.jr" (string_append (spc_forwards tt) (string_append w__117 "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JALR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rs1) >>= fun w__120 : string =>
+ returnm ((string_append "c.jalr"
+ (string_append (spc_forwards tt) (string_append w__120 "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_MV ((rd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rd) >>= fun w__123 : string =>
+ (reg_name_forwards rs2) >>= fun w__124 : string =>
+ returnm ((string_append "c.mv"
+ (string_append (spc_forwards tt)
+ (string_append w__123
+ (string_append (sep_forwards tt) (string_append w__124 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_EBREAK (tt) => returnm ("c.ebreak" : string)
+ | C_ADD ((rsd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__127 : string =>
+ (reg_name_forwards rs2) >>= fun w__128 : string =>
+ returnm ((string_append "c.add"
+ (string_append (spc_forwards tt)
+ (string_append w__127
+ (string_append (sep_forwards tt) (string_append w__128 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (mul_mnemonic_forwards (high, signed1, signed2)) >>= fun w__131 : string =>
+ (reg_name_forwards rd) >>= fun w__132 : string =>
+ (reg_name_forwards rs1) >>= fun w__133 : string =>
+ (reg_name_forwards rs2) >>= fun w__134 : string =>
+ returnm ((string_append w__131
+ (string_append (spc_forwards tt)
+ (string_append w__132
+ (string_append (sep_forwards tt)
+ (string_append w__133
+ (string_append (sep_forwards tt) (string_append w__134 "")))))))
+ : string)
+ | DIV ((rs2, rs1, rd, s)) =>
+ (reg_name_forwards rd) >>= fun w__135 : string =>
+ (reg_name_forwards rs1) >>= fun w__136 : string =>
+ (reg_name_forwards rs2) >>= fun w__137 : string =>
+ returnm ((string_append "div"
+ (string_append (maybe_not_u_forwards s)
+ (string_append (spc_forwards tt)
+ (string_append w__135
+ (string_append (sep_forwards tt)
+ (string_append w__136
+ (string_append (sep_forwards tt) (string_append w__137 ""))))))))
+ : string)
+ | REM ((rs2, rs1, rd, s)) =>
+ (reg_name_forwards rd) >>= fun w__138 : string =>
+ (reg_name_forwards rs1) >>= fun w__139 : string =>
+ (reg_name_forwards rs2) >>= fun w__140 : string =>
+ returnm ((string_append "rem"
+ (string_append (maybe_not_u_forwards s)
+ (string_append (spc_forwards tt)
+ (string_append w__138
+ (string_append (sep_forwards tt)
+ (string_append w__139
+ (string_append (sep_forwards tt) (string_append w__140 ""))))))))
+ : string)
+ | MULW ((rs2, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__141 : string =>
+ (reg_name_forwards rs1) >>= fun w__142 : string =>
+ (reg_name_forwards rs2) >>= fun w__143 : string =>
+ returnm ((string_append "mulw"
+ (string_append (spc_forwards tt)
+ (string_append w__141
+ (string_append (sep_forwards tt)
+ (string_append w__142
+ (string_append (sep_forwards tt) (string_append w__143 "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | DIVW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__146 : string =>
+ (reg_name_forwards rs1) >>= fun w__147 : string =>
+ (reg_name_forwards rs2) >>= fun w__148 : string =>
+ returnm ((string_append "div"
+ (string_append (maybe_not_u_forwards s)
+ (string_append "w"
+ (string_append (spc_forwards tt)
+ (string_append w__146
+ (string_append (sep_forwards tt)
+ (string_append w__147
+ (string_append (sep_forwards tt) (string_append w__148 "")))))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | REMW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 32 64)) then
+ (reg_name_forwards rd) >>= fun w__151 : string =>
+ (reg_name_forwards rs1) >>= fun w__152 : string =>
+ (reg_name_forwards rs2) >>= fun w__153 : string =>
+ returnm ((string_append "rem"
+ (string_append (maybe_not_u_forwards s)
+ (string_append "w"
+ (string_append (spc_forwards tt)
+ (string_append w__151
+ (string_append (sep_forwards tt)
+ (string_append w__152
+ (string_append (sep_forwards tt) (string_append w__153 "")))))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | CSR ((csr, rs1, rd, true, op)) =>
+ (reg_name_forwards rd) >>= fun w__156 : string =>
+ (csr_name_map_forwards csr) >>= fun w__157 : string =>
+ returnm ((string_append (csr_mnemonic_forwards op)
+ (string_append "i"
+ (string_append (spc_forwards tt)
+ (string_append w__156
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits rs1)
+ (string_append (sep_forwards tt) (string_append w__157 ""))))))))
+ : string)
+ | CSR ((csr, rs1, rd, false, op)) =>
+ (reg_name_forwards rd) >>= fun w__158 : string =>
+ (reg_name_forwards rs1) >>= fun w__159 : string =>
+ (csr_name_map_forwards csr) >>= fun w__160 : string =>
+ returnm ((string_append (csr_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__158
+ (string_append (sep_forwards tt)
+ (string_append w__159
+ (string_append (sep_forwards tt) (string_append w__160 "")))))))
+ : string)
+ | URET (tt) => returnm ("uret" : string)
+ | ILLEGAL (s) =>
+ returnm ((string_append "illegal"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) "")))
+ : string)
+ | C_ILLEGAL (s) =>
+ returnm ((string_append "c.illegal"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) "")))
+ : string)
+ end)
+ : M (string).
+
+Definition _s1677_ (_s1678_ : string)
+: M (option (mword 16)) :=
+
+ let _s1679_ := _s1678_ in
+ (if ((string_startswith _s1679_ "c.illegal")) then
+ (match (string_drop _s1679_ (projT1 (string_length "c.illegal"))) with
+ | _s1680_ =>
+ (spc_matches_prefix _s1680_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1681_ _)) =>
+ match (string_drop _s1680_ _s1681_) with
+ | _s1682_ =>
+ match (hex_bits_16_matches_prefix _s1682_) with
+ | Some ((s, existT _ _s1683_ _)) =>
+ let p0_ := string_drop _s1682_ _s1683_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 16))
+ end)
+ : M (option (mword 16))
+ else returnm (None : option (mword 16)))
+ : M (option (mword 16)).
+
+Definition _s1669_ (_s1670_ : string)
+: M (option (mword 32)) :=
+
+ let _s1671_ := _s1670_ in
+ (if ((string_startswith _s1671_ "illegal")) then
+ (match (string_drop _s1671_ (projT1 (string_length "illegal"))) with
+ | _s1672_ =>
+ (spc_matches_prefix _s1672_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1673_ _)) =>
+ match (string_drop _s1672_ _s1673_) with
+ | _s1674_ =>
+ match (hex_bits_32_matches_prefix _s1674_) with
+ | Some ((s, existT _ _s1675_ _)) =>
+ let p0_ := string_drop _s1674_ _s1675_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 32))
+ end)
+ : M (option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option (mword 32)).
+
+Definition _s1652_ (_s1653_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1653_ with
+ | _s1654_ =>
+ (csr_mnemonic_matches_prefix _s1654_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1655_ _)) =>
+ (match (string_drop _s1654_ _s1655_) with
+ | _s1656_ =>
+ (spc_matches_prefix _s1656_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1657_ _)) =>
+ (match (string_drop _s1656_ _s1657_) with
+ | _s1658_ =>
+ (reg_name_matches_prefix _s1658_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1659_ _)) =>
+ (match (string_drop _s1658_ _s1659_) with
+ | _s1660_ =>
+ (sep_matches_prefix _s1660_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1661_ _)) =>
+ (match (string_drop _s1660_ _s1661_) with
+ | _s1662_ =>
+ (reg_name_matches_prefix _s1662_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1663_ _)) =>
+ (match (string_drop _s1662_ _s1663_) with
+ | _s1664_ =>
+ (sep_matches_prefix _s1664_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1665_ _)) =>
+ (match (string_drop _s1664_ _s1665_) with
+ | _s1666_ =>
+ (csr_name_map_matches_prefix _s1666_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s1667_ _)) =>
+ let p0_ :=
+ string_drop _s1666_ _s1667_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1634_ (_s1635_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1635_ with
+ | _s1636_ =>
+ (csr_mnemonic_matches_prefix _s1636_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1637_ _)) =>
+ let _s1638_ := string_drop _s1636_ _s1637_ in
+ (if ((string_startswith _s1638_ "i")) then
+ (match (string_drop _s1638_ (projT1 (string_length "i"))) with
+ | _s1639_ =>
+ (spc_matches_prefix _s1639_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1640_ _)) =>
+ (match (string_drop _s1639_ _s1640_) with
+ | _s1641_ =>
+ (reg_name_matches_prefix _s1641_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1642_ _)) =>
+ (match (string_drop _s1641_ _s1642_) with
+ | _s1643_ =>
+ (sep_matches_prefix _s1643_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1644_ _)) =>
+ (match (string_drop _s1643_ _s1644_) with
+ | _s1645_ =>
+ (match (hex_bits_5_matches_prefix _s1645_) with
+ | Some ((rs1, existT _ _s1646_ _)) =>
+ (match (string_drop _s1645_ _s1646_) with
+ | _s1647_ =>
+ (sep_matches_prefix _s1647_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1648_ _)) =>
+ (match (string_drop _s1647_ _s1648_) with
+ | _s1649_ =>
+ (csr_name_map_matches_prefix _s1649_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s1650_ _)) =>
+ let p0_ :=
+ string_drop _s1649_ _s1650_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1615_ (_s1616_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1617_ := _s1616_ in
+ (if ((string_startswith _s1617_ "rem")) then
+ (match (string_drop _s1617_ (projT1 (string_length "rem"))) with
+ | _s1618_ =>
+ (maybe_not_u_matches_prefix _s1618_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1619_ _)) =>
+ let _s1620_ := string_drop _s1618_ _s1619_ in
+ (if ((string_startswith _s1620_ "w")) then
+ (match (string_drop _s1620_ (projT1 (string_length "w"))) with
+ | _s1621_ =>
+ (spc_matches_prefix _s1621_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1622_ _)) =>
+ (match (string_drop _s1621_ _s1622_) with
+ | _s1623_ =>
+ (reg_name_matches_prefix _s1623_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1624_ _)) =>
+ (match (string_drop _s1623_ _s1624_) with
+ | _s1625_ =>
+ (sep_matches_prefix _s1625_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1626_ _)) =>
+ (match (string_drop _s1625_ _s1626_) with
+ | _s1627_ =>
+ (reg_name_matches_prefix _s1627_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1628_ _)) =>
+ (match (string_drop _s1627_ _s1628_) with
+ | _s1629_ =>
+ (sep_matches_prefix _s1629_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1630_ _)) =>
+ (match (string_drop _s1629_ _s1630_) with
+ | _s1631_ =>
+ (reg_name_matches_prefix _s1631_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1632_ _)) =>
+ let p0_ :=
+ string_drop _s1631_
+ _s1632_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1596_ (_s1597_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1598_ := _s1597_ in
+ (if ((string_startswith _s1598_ "div")) then
+ (match (string_drop _s1598_ (projT1 (string_length "div"))) with
+ | _s1599_ =>
+ (maybe_not_u_matches_prefix _s1599_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1600_ _)) =>
+ let _s1601_ := string_drop _s1599_ _s1600_ in
+ (if ((string_startswith _s1601_ "w")) then
+ (match (string_drop _s1601_ (projT1 (string_length "w"))) with
+ | _s1602_ =>
+ (spc_matches_prefix _s1602_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1603_ _)) =>
+ (match (string_drop _s1602_ _s1603_) with
+ | _s1604_ =>
+ (reg_name_matches_prefix _s1604_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1605_ _)) =>
+ (match (string_drop _s1604_ _s1605_) with
+ | _s1606_ =>
+ (sep_matches_prefix _s1606_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1607_ _)) =>
+ (match (string_drop _s1606_ _s1607_) with
+ | _s1608_ =>
+ (reg_name_matches_prefix _s1608_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1609_ _)) =>
+ (match (string_drop _s1608_ _s1609_) with
+ | _s1610_ =>
+ (sep_matches_prefix _s1610_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1611_ _)) =>
+ (match (string_drop _s1610_ _s1611_) with
+ | _s1612_ =>
+ (reg_name_matches_prefix _s1612_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1613_ _)) =>
+ let p0_ :=
+ string_drop _s1612_
+ _s1613_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1580_ (_s1581_ : string)
+: M (option ((mword 5 * mword 5 * mword 5))) :=
+
+ let _s1582_ := _s1581_ in
+ (if ((string_startswith _s1582_ "mulw")) then
+ (match (string_drop _s1582_ (projT1 (string_length "mulw"))) with
+ | _s1583_ =>
+ (spc_matches_prefix _s1583_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1584_ _)) =>
+ (match (string_drop _s1583_ _s1584_) with
+ | _s1585_ =>
+ (reg_name_matches_prefix _s1585_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1586_ _)) =>
+ (match (string_drop _s1585_ _s1586_) with
+ | _s1587_ =>
+ (sep_matches_prefix _s1587_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1588_ _)) =>
+ (match (string_drop _s1587_ _s1588_) with
+ | _s1589_ =>
+ (reg_name_matches_prefix _s1589_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1590_ _)) =>
+ (match (string_drop _s1589_ _s1590_) with
+ | _s1591_ =>
+ (sep_matches_prefix _s1591_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1592_ _)) =>
+ (match (string_drop _s1591_ _s1592_) with
+ | _s1593_ =>
+ (reg_name_matches_prefix _s1593_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s1594_ _)) =>
+ let p0_ :=
+ string_drop _s1593_ _s1594_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5 * mword 5))).
+
+Definition _s1562_ (_s1563_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1564_ := _s1563_ in
+ (if ((string_startswith _s1564_ "rem")) then
+ (match (string_drop _s1564_ (projT1 (string_length "rem"))) with
+ | _s1565_ =>
+ (maybe_not_u_matches_prefix _s1565_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1566_ _)) =>
+ (match (string_drop _s1565_ _s1566_) with
+ | _s1567_ =>
+ (spc_matches_prefix _s1567_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1568_ _)) =>
+ (match (string_drop _s1567_ _s1568_) with
+ | _s1569_ =>
+ (reg_name_matches_prefix _s1569_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1570_ _)) =>
+ (match (string_drop _s1569_ _s1570_) with
+ | _s1571_ =>
+ (sep_matches_prefix _s1571_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1572_ _)) =>
+ (match (string_drop _s1571_ _s1572_) with
+ | _s1573_ =>
+ (reg_name_matches_prefix _s1573_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1574_ _)) =>
+ (match (string_drop _s1573_ _s1574_) with
+ | _s1575_ =>
+ (sep_matches_prefix _s1575_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1576_ _)) =>
+ (match (string_drop _s1575_ _s1576_) with
+ | _s1577_ =>
+ (reg_name_matches_prefix _s1577_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1578_ _)) =>
+ let p0_ :=
+ string_drop _s1577_ _s1578_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1544_ (_s1545_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1546_ := _s1545_ in
+ (if ((string_startswith _s1546_ "div")) then
+ (match (string_drop _s1546_ (projT1 (string_length "div"))) with
+ | _s1547_ =>
+ (maybe_not_u_matches_prefix _s1547_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1548_ _)) =>
+ (match (string_drop _s1547_ _s1548_) with
+ | _s1549_ =>
+ (spc_matches_prefix _s1549_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1550_ _)) =>
+ (match (string_drop _s1549_ _s1550_) with
+ | _s1551_ =>
+ (reg_name_matches_prefix _s1551_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1552_ _)) =>
+ (match (string_drop _s1551_ _s1552_) with
+ | _s1553_ =>
+ (sep_matches_prefix _s1553_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1554_ _)) =>
+ (match (string_drop _s1553_ _s1554_) with
+ | _s1555_ =>
+ (reg_name_matches_prefix _s1555_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1556_ _)) =>
+ (match (string_drop _s1555_ _s1556_) with
+ | _s1557_ =>
+ (sep_matches_prefix _s1557_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1558_ _)) =>
+ (match (string_drop _s1557_ _s1558_) with
+ | _s1559_ =>
+ (reg_name_matches_prefix _s1559_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1560_ _)) =>
+ let p0_ :=
+ string_drop _s1559_ _s1560_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1527_ (_s1528_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1528_ with
+ | _s1529_ =>
+ (mul_mnemonic_matches_prefix _s1529_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s1530_ _)) =>
+ (match (string_drop _s1529_ _s1530_) with
+ | _s1531_ =>
+ (spc_matches_prefix _s1531_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1532_ _)) =>
+ (match (string_drop _s1531_ _s1532_) with
+ | _s1533_ =>
+ (reg_name_matches_prefix _s1533_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1534_ _)) =>
+ (match (string_drop _s1533_ _s1534_) with
+ | _s1535_ =>
+ (sep_matches_prefix _s1535_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1536_ _)) =>
+ (match (string_drop _s1535_ _s1536_) with
+ | _s1537_ =>
+ (reg_name_matches_prefix _s1537_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1538_ _)) =>
+ (match (string_drop _s1537_ _s1538_) with
+ | _s1539_ =>
+ (sep_matches_prefix _s1539_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1540_ _)) =>
+ (match (string_drop _s1539_ _s1540_) with
+ | _s1541_ =>
+ (reg_name_matches_prefix _s1541_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1542_ _)) =>
+ let p0_ :=
+ string_drop _s1541_ _s1542_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1515_ (_s1516_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1517_ := _s1516_ in
+ (if ((string_startswith _s1517_ "c.add")) then
+ (match (string_drop _s1517_ (projT1 (string_length "c.add"))) with
+ | _s1518_ =>
+ (spc_matches_prefix _s1518_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1519_ _)) =>
+ (match (string_drop _s1518_ _s1519_) with
+ | _s1520_ =>
+ (reg_name_matches_prefix _s1520_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1521_ _)) =>
+ (match (string_drop _s1520_ _s1521_) with
+ | _s1522_ =>
+ (sep_matches_prefix _s1522_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1523_ _)) =>
+ (match (string_drop _s1522_ _s1523_) with
+ | _s1524_ =>
+ (reg_name_matches_prefix _s1524_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1525_ _)) =>
+ let p0_ := string_drop _s1524_ _s1525_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1503_ (_s1504_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1505_ := _s1504_ in
+ (if ((string_startswith _s1505_ "c.mv")) then
+ (match (string_drop _s1505_ (projT1 (string_length "c.mv"))) with
+ | _s1506_ =>
+ (spc_matches_prefix _s1506_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1507_ _)) =>
+ (match (string_drop _s1506_ _s1507_) with
+ | _s1508_ =>
+ (reg_name_matches_prefix _s1508_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1509_ _)) =>
+ (match (string_drop _s1508_ _s1509_) with
+ | _s1510_ =>
+ (sep_matches_prefix _s1510_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1511_ _)) =>
+ (match (string_drop _s1510_ _s1511_) with
+ | _s1512_ =>
+ (reg_name_matches_prefix _s1512_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1513_ _)) =>
+ let p0_ := string_drop _s1512_ _s1513_ in
+ if ((generic_eq p0_ "")) then Some ((rd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1495_ (_s1496_ : string)
+: M (option (mword 5)) :=
+
+ let _s1497_ := _s1496_ in
+ (if ((string_startswith _s1497_ "c.jalr")) then
+ (match (string_drop _s1497_ (projT1 (string_length "c.jalr"))) with
+ | _s1498_ =>
+ (spc_matches_prefix _s1498_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1499_ _)) =>
+ (match (string_drop _s1498_ _s1499_) with
+ | _s1500_ =>
+ (reg_name_matches_prefix _s1500_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s1501_ _)) =>
+ let p0_ := string_drop _s1500_ _s1501_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s1487_ (_s1488_ : string)
+: M (option (mword 5)) :=
+
+ let _s1489_ := _s1488_ in
+ (if ((string_startswith _s1489_ "c.jr")) then
+ (match (string_drop _s1489_ (projT1 (string_length "c.jr"))) with
+ | _s1490_ =>
+ (spc_matches_prefix _s1490_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1491_ _)) =>
+ (match (string_drop _s1490_ _s1491_) with
+ | _s1492_ =>
+ (reg_name_matches_prefix _s1492_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s1493_ _)) =>
+ let p0_ := string_drop _s1492_ _s1493_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s1475_ (_s1476_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1477_ := _s1476_ in
+ (if ((string_startswith _s1477_ "c.sdsp")) then
+ (match (string_drop _s1477_ (projT1 (string_length "c.sdsp"))) with
+ | _s1478_ =>
+ (spc_matches_prefix _s1478_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1479_ _)) =>
+ (match (string_drop _s1478_ _s1479_) with
+ | _s1480_ =>
+ (reg_name_matches_prefix _s1480_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s1481_ _)) =>
+ (match (string_drop _s1480_ _s1481_) with
+ | _s1482_ =>
+ (sep_matches_prefix _s1482_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1483_ _)) =>
+ match (string_drop _s1482_ _s1483_) with
+ | _s1484_ =>
+ match (hex_bits_6_matches_prefix _s1484_) with
+ | Some ((uimm, existT _ _s1485_ _)) =>
+ let p0_ := string_drop _s1484_ _s1485_ in
+ if ((generic_eq p0_ "")) then Some ((rs2, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1463_ (_s1464_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1465_ := _s1464_ in
+ (if ((string_startswith _s1465_ "c.swsp")) then
+ (match (string_drop _s1465_ (projT1 (string_length "c.swsp"))) with
+ | _s1466_ =>
+ (spc_matches_prefix _s1466_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1467_ _)) =>
+ (match (string_drop _s1466_ _s1467_) with
+ | _s1468_ =>
+ (reg_name_matches_prefix _s1468_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1469_ _)) =>
+ (match (string_drop _s1468_ _s1469_) with
+ | _s1470_ =>
+ (sep_matches_prefix _s1470_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1471_ _)) =>
+ match (string_drop _s1470_ _s1471_) with
+ | _s1472_ =>
+ match (hex_bits_6_matches_prefix _s1472_) with
+ | Some ((uimm, existT _ _s1473_ _)) =>
+ let p0_ := string_drop _s1472_ _s1473_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1451_ (_s1452_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1453_ := _s1452_ in
+ (if ((string_startswith _s1453_ "c.ldsp")) then
+ (match (string_drop _s1453_ (projT1 (string_length "c.ldsp"))) with
+ | _s1454_ =>
+ (spc_matches_prefix _s1454_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1455_ _)) =>
+ (match (string_drop _s1454_ _s1455_) with
+ | _s1456_ =>
+ (reg_name_matches_prefix _s1456_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1457_ _)) =>
+ (match (string_drop _s1456_ _s1457_) with
+ | _s1458_ =>
+ (sep_matches_prefix _s1458_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1459_ _)) =>
+ match (string_drop _s1458_ _s1459_) with
+ | _s1460_ =>
+ match (hex_bits_6_matches_prefix _s1460_) with
+ | Some ((uimm, existT _ _s1461_ _)) =>
+ let p0_ := string_drop _s1460_ _s1461_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1439_ (_s1440_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1441_ := _s1440_ in
+ (if ((string_startswith _s1441_ "c.lwsp")) then
+ (match (string_drop _s1441_ (projT1 (string_length "c.lwsp"))) with
+ | _s1442_ =>
+ (spc_matches_prefix _s1442_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1443_ _)) =>
+ (match (string_drop _s1442_ _s1443_) with
+ | _s1444_ =>
+ (reg_name_matches_prefix _s1444_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1445_ _)) =>
+ (match (string_drop _s1444_ _s1445_) with
+ | _s1446_ =>
+ (sep_matches_prefix _s1446_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1447_ _)) =>
+ match (string_drop _s1446_ _s1447_) with
+ | _s1448_ =>
+ match (hex_bits_6_matches_prefix _s1448_) with
+ | Some ((uimm, existT _ _s1449_ _)) =>
+ let p0_ := string_drop _s1448_ _s1449_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1427_ (_s1428_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1429_ := _s1428_ in
+ (if ((string_startswith _s1429_ "c.slli")) then
+ (match (string_drop _s1429_ (projT1 (string_length "c.slli"))) with
+ | _s1430_ =>
+ (spc_matches_prefix _s1430_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1431_ _)) =>
+ (match (string_drop _s1430_ _s1431_) with
+ | _s1432_ =>
+ (reg_name_matches_prefix _s1432_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1433_ _)) =>
+ (match (string_drop _s1432_ _s1433_) with
+ | _s1434_ =>
+ (sep_matches_prefix _s1434_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1435_ _)) =>
+ match (string_drop _s1434_ _s1435_) with
+ | _s1436_ =>
+ match (hex_bits_6_matches_prefix _s1436_) with
+ | Some ((shamt, existT _ _s1437_ _)) =>
+ let p0_ := string_drop _s1436_ _s1437_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1415_ (_s1416_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1417_ := _s1416_ in
+ (if ((string_startswith _s1417_ "c.bnez")) then
+ (match (string_drop _s1417_ (projT1 (string_length "c.bnez"))) with
+ | _s1418_ =>
+ (spc_matches_prefix _s1418_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1419_ _)) =>
+ (match (string_drop _s1418_ _s1419_) with
+ | _s1420_ =>
+ (creg_name_matches_prefix _s1420_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s1421_ _)) =>
+ (match (string_drop _s1420_ _s1421_) with
+ | _s1422_ =>
+ (sep_matches_prefix _s1422_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1423_ _)) =>
+ match (string_drop _s1422_ _s1423_) with
+ | _s1424_ =>
+ match (hex_bits_8_matches_prefix _s1424_) with
+ | Some ((imm, existT _ _s1425_ _)) =>
+ let p0_ := string_drop _s1424_ _s1425_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1403_ (_s1404_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1405_ := _s1404_ in
+ (if ((string_startswith _s1405_ "c.beqz")) then
+ (match (string_drop _s1405_ (projT1 (string_length "c.beqz"))) with
+ | _s1406_ =>
+ (spc_matches_prefix _s1406_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1407_ _)) =>
+ (match (string_drop _s1406_ _s1407_) with
+ | _s1408_ =>
+ (creg_name_matches_prefix _s1408_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s1409_ _)) =>
+ (match (string_drop _s1408_ _s1409_) with
+ | _s1410_ =>
+ (sep_matches_prefix _s1410_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1411_ _)) =>
+ match (string_drop _s1410_ _s1411_) with
+ | _s1412_ =>
+ match (hex_bits_8_matches_prefix _s1412_) with
+ | Some ((imm, existT _ _s1413_ _)) =>
+ let p0_ := string_drop _s1412_ _s1413_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1395_ (_s1396_ : string)
+: M (option (mword 11)) :=
+
+ let _s1397_ := _s1396_ in
+ (if ((string_startswith _s1397_ "c.j")) then
+ (match (string_drop _s1397_ (projT1 (string_length "c.j"))) with
+ | _s1398_ =>
+ (spc_matches_prefix _s1398_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1399_ _)) =>
+ match (string_drop _s1398_ _s1399_) with
+ | _s1400_ =>
+ match (hex_bits_11_matches_prefix _s1400_) with
+ | Some ((imm, existT _ _s1401_ _)) =>
+ let p0_ := string_drop _s1400_ _s1401_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s1383_ (_s1384_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1385_ := _s1384_ in
+ (if ((string_startswith _s1385_ "c.addw")) then
+ (match (string_drop _s1385_ (projT1 (string_length "c.addw"))) with
+ | _s1386_ =>
+ (spc_matches_prefix _s1386_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1387_ _)) =>
+ (match (string_drop _s1386_ _s1387_) with
+ | _s1388_ =>
+ (creg_name_matches_prefix _s1388_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1389_ _)) =>
+ (match (string_drop _s1388_ _s1389_) with
+ | _s1390_ =>
+ (sep_matches_prefix _s1390_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1391_ _)) =>
+ (match (string_drop _s1390_ _s1391_) with
+ | _s1392_ =>
+ (creg_name_matches_prefix _s1392_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1393_ _)) =>
+ let p0_ := string_drop _s1392_ _s1393_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1371_ (_s1372_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1373_ := _s1372_ in
+ (if ((string_startswith _s1373_ "c.subw")) then
+ (match (string_drop _s1373_ (projT1 (string_length "c.subw"))) with
+ | _s1374_ =>
+ (spc_matches_prefix _s1374_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1375_ _)) =>
+ (match (string_drop _s1374_ _s1375_) with
+ | _s1376_ =>
+ (creg_name_matches_prefix _s1376_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1377_ _)) =>
+ (match (string_drop _s1376_ _s1377_) with
+ | _s1378_ =>
+ (sep_matches_prefix _s1378_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1379_ _)) =>
+ (match (string_drop _s1378_ _s1379_) with
+ | _s1380_ =>
+ (creg_name_matches_prefix _s1380_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1381_ _)) =>
+ let p0_ := string_drop _s1380_ _s1381_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1359_ (_s1360_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1361_ := _s1360_ in
+ (if ((string_startswith _s1361_ "c.and")) then
+ (match (string_drop _s1361_ (projT1 (string_length "c.and"))) with
+ | _s1362_ =>
+ (spc_matches_prefix _s1362_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1363_ _)) =>
+ (match (string_drop _s1362_ _s1363_) with
+ | _s1364_ =>
+ (creg_name_matches_prefix _s1364_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1365_ _)) =>
+ (match (string_drop _s1364_ _s1365_) with
+ | _s1366_ =>
+ (sep_matches_prefix _s1366_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1367_ _)) =>
+ (match (string_drop _s1366_ _s1367_) with
+ | _s1368_ =>
+ (creg_name_matches_prefix _s1368_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1369_ _)) =>
+ let p0_ := string_drop _s1368_ _s1369_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1347_ (_s1348_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1349_ := _s1348_ in
+ (if ((string_startswith _s1349_ "c.or")) then
+ (match (string_drop _s1349_ (projT1 (string_length "c.or"))) with
+ | _s1350_ =>
+ (spc_matches_prefix _s1350_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1351_ _)) =>
+ (match (string_drop _s1350_ _s1351_) with
+ | _s1352_ =>
+ (creg_name_matches_prefix _s1352_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1353_ _)) =>
+ (match (string_drop _s1352_ _s1353_) with
+ | _s1354_ =>
+ (sep_matches_prefix _s1354_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1355_ _)) =>
+ (match (string_drop _s1354_ _s1355_) with
+ | _s1356_ =>
+ (creg_name_matches_prefix _s1356_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1357_ _)) =>
+ let p0_ := string_drop _s1356_ _s1357_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1335_ (_s1336_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1337_ := _s1336_ in
+ (if ((string_startswith _s1337_ "c.xor")) then
+ (match (string_drop _s1337_ (projT1 (string_length "c.xor"))) with
+ | _s1338_ =>
+ (spc_matches_prefix _s1338_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1339_ _)) =>
+ (match (string_drop _s1338_ _s1339_) with
+ | _s1340_ =>
+ (creg_name_matches_prefix _s1340_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1341_ _)) =>
+ (match (string_drop _s1340_ _s1341_) with
+ | _s1342_ =>
+ (sep_matches_prefix _s1342_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1343_ _)) =>
+ (match (string_drop _s1342_ _s1343_) with
+ | _s1344_ =>
+ (creg_name_matches_prefix _s1344_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1345_ _)) =>
+ let p0_ := string_drop _s1344_ _s1345_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1323_ (_s1324_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1325_ := _s1324_ in
+ (if ((string_startswith _s1325_ "c.sub")) then
+ (match (string_drop _s1325_ (projT1 (string_length "c.sub"))) with
+ | _s1326_ =>
+ (spc_matches_prefix _s1326_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1327_ _)) =>
+ (match (string_drop _s1326_ _s1327_) with
+ | _s1328_ =>
+ (creg_name_matches_prefix _s1328_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1329_ _)) =>
+ (match (string_drop _s1328_ _s1329_) with
+ | _s1330_ =>
+ (sep_matches_prefix _s1330_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1331_ _)) =>
+ (match (string_drop _s1330_ _s1331_) with
+ | _s1332_ =>
+ (creg_name_matches_prefix _s1332_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1333_ _)) =>
+ let p0_ := string_drop _s1332_ _s1333_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1311_ (_s1312_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1313_ := _s1312_ in
+ (if ((string_startswith _s1313_ "c.andi")) then
+ (match (string_drop _s1313_ (projT1 (string_length "c.andi"))) with
+ | _s1314_ =>
+ (spc_matches_prefix _s1314_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1315_ _)) =>
+ (match (string_drop _s1314_ _s1315_) with
+ | _s1316_ =>
+ (creg_name_matches_prefix _s1316_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1317_ _)) =>
+ (match (string_drop _s1316_ _s1317_) with
+ | _s1318_ =>
+ (sep_matches_prefix _s1318_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1319_ _)) =>
+ match (string_drop _s1318_ _s1319_) with
+ | _s1320_ =>
+ match (hex_bits_6_matches_prefix _s1320_) with
+ | Some ((imm, existT _ _s1321_ _)) =>
+ let p0_ := string_drop _s1320_ _s1321_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1299_ (_s1300_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1301_ := _s1300_ in
+ (if ((string_startswith _s1301_ "c.srai")) then
+ (match (string_drop _s1301_ (projT1 (string_length "c.srai"))) with
+ | _s1302_ =>
+ (spc_matches_prefix _s1302_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1303_ _)) =>
+ (match (string_drop _s1302_ _s1303_) with
+ | _s1304_ =>
+ (creg_name_matches_prefix _s1304_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1305_ _)) =>
+ (match (string_drop _s1304_ _s1305_) with
+ | _s1306_ =>
+ (sep_matches_prefix _s1306_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1307_ _)) =>
+ match (string_drop _s1306_ _s1307_) with
+ | _s1308_ =>
+ match (hex_bits_6_matches_prefix _s1308_) with
+ | Some ((shamt, existT _ _s1309_ _)) =>
+ let p0_ := string_drop _s1308_ _s1309_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1287_ (_s1288_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1289_ := _s1288_ in
+ (if ((string_startswith _s1289_ "c.srli")) then
+ (match (string_drop _s1289_ (projT1 (string_length "c.srli"))) with
+ | _s1290_ =>
+ (spc_matches_prefix _s1290_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1291_ _)) =>
+ (match (string_drop _s1290_ _s1291_) with
+ | _s1292_ =>
+ (creg_name_matches_prefix _s1292_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1293_ _)) =>
+ (match (string_drop _s1292_ _s1293_) with
+ | _s1294_ =>
+ (sep_matches_prefix _s1294_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1295_ _)) =>
+ match (string_drop _s1294_ _s1295_) with
+ | _s1296_ =>
+ match (hex_bits_6_matches_prefix _s1296_) with
+ | Some ((shamt, existT _ _s1297_ _)) =>
+ let p0_ := string_drop _s1296_ _s1297_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1275_ (_s1276_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1277_ := _s1276_ in
+ (if ((string_startswith _s1277_ "c.lui")) then
+ (match (string_drop _s1277_ (projT1 (string_length "c.lui"))) with
+ | _s1278_ =>
+ (spc_matches_prefix _s1278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1279_ _)) =>
+ (match (string_drop _s1278_ _s1279_) with
+ | _s1280_ =>
+ (reg_name_matches_prefix _s1280_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1281_ _)) =>
+ (match (string_drop _s1280_ _s1281_) with
+ | _s1282_ =>
+ (sep_matches_prefix _s1282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1283_ _)) =>
+ match (string_drop _s1282_ _s1283_) with
+ | _s1284_ =>
+ match (hex_bits_6_matches_prefix _s1284_) with
+ | Some ((imm, existT _ _s1285_ _)) =>
+ let p0_ := string_drop _s1284_ _s1285_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1267_ (_s1268_ : string)
+: M (option (mword 6)) :=
+
+ let _s1269_ := _s1268_ in
+ (if ((string_startswith _s1269_ "c.addi16sp")) then
+ (match (string_drop _s1269_ (projT1 (string_length "c.addi16sp"))) with
+ | _s1270_ =>
+ (spc_matches_prefix _s1270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1271_ _)) =>
+ match (string_drop _s1270_ _s1271_) with
+ | _s1272_ =>
+ match (hex_bits_6_matches_prefix _s1272_) with
+ | Some ((imm, existT _ _s1273_ _)) =>
+ let p0_ := string_drop _s1272_ _s1273_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 6))
+ end)
+ : M (option (mword 6))
+ else returnm (None : option (mword 6)))
+ : M (option (mword 6)).
+
+Definition _s1255_ (_s1256_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1257_ := _s1256_ in
+ (if ((string_startswith _s1257_ "c.li")) then
+ (match (string_drop _s1257_ (projT1 (string_length "c.li"))) with
+ | _s1258_ =>
+ (spc_matches_prefix _s1258_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1259_ _)) =>
+ (match (string_drop _s1258_ _s1259_) with
+ | _s1260_ =>
+ (reg_name_matches_prefix _s1260_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1261_ _)) =>
+ (match (string_drop _s1260_ _s1261_) with
+ | _s1262_ =>
+ (sep_matches_prefix _s1262_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1263_ _)) =>
+ match (string_drop _s1262_ _s1263_) with
+ | _s1264_ =>
+ match (hex_bits_6_matches_prefix _s1264_) with
+ | Some ((imm, existT _ _s1265_ _)) =>
+ let p0_ := string_drop _s1264_ _s1265_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1243_ (_s1244_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1245_ := _s1244_ in
+ (if ((string_startswith _s1245_ "c.addiw")) then
+ (match (string_drop _s1245_ (projT1 (string_length "c.addiw"))) with
+ | _s1246_ =>
+ (spc_matches_prefix _s1246_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1247_ _)) =>
+ (match (string_drop _s1246_ _s1247_) with
+ | _s1248_ =>
+ (reg_name_matches_prefix _s1248_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1249_ _)) =>
+ (match (string_drop _s1248_ _s1249_) with
+ | _s1250_ =>
+ (sep_matches_prefix _s1250_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1251_ _)) =>
+ match (string_drop _s1250_ _s1251_) with
+ | _s1252_ =>
+ match (hex_bits_6_matches_prefix _s1252_) with
+ | Some ((imm, existT _ _s1253_ _)) =>
+ let p0_ := string_drop _s1252_ _s1253_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1235_ (_s1236_ : string)
+: M (option (mword 11)) :=
+
+ let _s1237_ := _s1236_ in
+ (if ((string_startswith _s1237_ "c.jal")) then
+ (match (string_drop _s1237_ (projT1 (string_length "c.jal"))) with
+ | _s1238_ =>
+ (spc_matches_prefix _s1238_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1239_ _)) =>
+ match (string_drop _s1238_ _s1239_) with
+ | _s1240_ =>
+ match (hex_bits_12_matches_prefix _s1240_) with
+ | Some ((v__802, existT _ _s1241_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__802 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__802 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__802 11 1 in
+ let p0_ := string_drop _s1240_ _s1241_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s1223_ (_s1224_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1225_ := _s1224_ in
+ (if ((string_startswith _s1225_ "c.addi")) then
+ (match (string_drop _s1225_ (projT1 (string_length "c.addi"))) with
+ | _s1226_ =>
+ (spc_matches_prefix _s1226_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1227_ _)) =>
+ (match (string_drop _s1226_ _s1227_) with
+ | _s1228_ =>
+ (reg_name_matches_prefix _s1228_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1229_ _)) =>
+ (match (string_drop _s1228_ _s1229_) with
+ | _s1230_ =>
+ (sep_matches_prefix _s1230_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1231_ _)) =>
+ match (string_drop _s1230_ _s1231_) with
+ | _s1232_ =>
+ match (hex_bits_6_matches_prefix _s1232_) with
+ | Some ((nzi, existT _ _s1233_ _)) =>
+ let p0_ := string_drop _s1232_ _s1233_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, nzi))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1207_ (_s1208_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1209_ := _s1208_ in
+ (if ((string_startswith _s1209_ "c.sd")) then
+ (match (string_drop _s1209_ (projT1 (string_length "c.sd"))) with
+ | _s1210_ =>
+ (spc_matches_prefix _s1210_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1211_ _)) =>
+ (match (string_drop _s1210_ _s1211_) with
+ | _s1212_ =>
+ (creg_name_matches_prefix _s1212_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s1213_ _)) =>
+ (match (string_drop _s1212_ _s1213_) with
+ | _s1214_ =>
+ (sep_matches_prefix _s1214_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1215_ _)) =>
+ (match (string_drop _s1214_ _s1215_) with
+ | _s1216_ =>
+ (creg_name_matches_prefix _s1216_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s1217_ _)) =>
+ (match (string_drop _s1216_ _s1217_) with
+ | _s1218_ =>
+ (sep_matches_prefix _s1218_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1219_ _)) =>
+ match (string_drop _s1218_ _s1219_) with
+ | _s1220_ =>
+ match (hex_bits_8_matches_prefix _s1220_) with
+ | Some ((v__804, existT _ _s1221_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__804 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__804 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__804 7 3 in
+ let p0_ :=
+ string_drop _s1220_ _s1221_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1191_ (_s1192_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1193_ := _s1192_ in
+ (if ((string_startswith _s1193_ "c.sw")) then
+ (match (string_drop _s1193_ (projT1 (string_length "c.sw"))) with
+ | _s1194_ =>
+ (spc_matches_prefix _s1194_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1195_ _)) =>
+ (match (string_drop _s1194_ _s1195_) with
+ | _s1196_ =>
+ (creg_name_matches_prefix _s1196_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s1197_ _)) =>
+ (match (string_drop _s1196_ _s1197_) with
+ | _s1198_ =>
+ (sep_matches_prefix _s1198_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1199_ _)) =>
+ (match (string_drop _s1198_ _s1199_) with
+ | _s1200_ =>
+ (creg_name_matches_prefix _s1200_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s1201_ _)) =>
+ (match (string_drop _s1200_ _s1201_) with
+ | _s1202_ =>
+ (sep_matches_prefix _s1202_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1203_ _)) =>
+ match (string_drop _s1202_ _s1203_) with
+ | _s1204_ =>
+ match (hex_bits_7_matches_prefix _s1204_) with
+ | Some ((v__806, existT _ _s1205_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__806 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__806 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__806 6 2 in
+ let p0_ :=
+ string_drop _s1204_ _s1205_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1175_ (_s1176_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1177_ := _s1176_ in
+ (if ((string_startswith _s1177_ "c.ld")) then
+ (match (string_drop _s1177_ (projT1 (string_length "c.ld"))) with
+ | _s1178_ =>
+ (spc_matches_prefix _s1178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1179_ _)) =>
+ (match (string_drop _s1178_ _s1179_) with
+ | _s1180_ =>
+ (creg_name_matches_prefix _s1180_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1181_ _)) =>
+ (match (string_drop _s1180_ _s1181_) with
+ | _s1182_ =>
+ (sep_matches_prefix _s1182_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1183_ _)) =>
+ (match (string_drop _s1182_ _s1183_) with
+ | _s1184_ =>
+ (creg_name_matches_prefix _s1184_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s1185_ _)) =>
+ (match (string_drop _s1184_ _s1185_) with
+ | _s1186_ =>
+ (sep_matches_prefix _s1186_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1187_ _)) =>
+ match (string_drop _s1186_ _s1187_) with
+ | _s1188_ =>
+ match (hex_bits_8_matches_prefix _s1188_) with
+ | Some ((v__808, existT _ _s1189_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__808 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__808 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__808 7 3 in
+ let p0_ :=
+ string_drop _s1188_ _s1189_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1159_ (_s1160_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1161_ := _s1160_ in
+ (if ((string_startswith _s1161_ "c.lw")) then
+ (match (string_drop _s1161_ (projT1 (string_length "c.lw"))) with
+ | _s1162_ =>
+ (spc_matches_prefix _s1162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1163_ _)) =>
+ (match (string_drop _s1162_ _s1163_) with
+ | _s1164_ =>
+ (creg_name_matches_prefix _s1164_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1165_ _)) =>
+ (match (string_drop _s1164_ _s1165_) with
+ | _s1166_ =>
+ (sep_matches_prefix _s1166_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1167_ _)) =>
+ (match (string_drop _s1166_ _s1167_) with
+ | _s1168_ =>
+ (creg_name_matches_prefix _s1168_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s1169_ _)) =>
+ (match (string_drop _s1168_ _s1169_) with
+ | _s1170_ =>
+ (sep_matches_prefix _s1170_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1171_ _)) =>
+ match (string_drop _s1170_ _s1171_) with
+ | _s1172_ =>
+ match (hex_bits_7_matches_prefix _s1172_) with
+ | Some ((v__810, existT _ _s1173_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__810 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__810 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__810 6 2 in
+ let p0_ :=
+ string_drop _s1172_ _s1173_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1147_ (_s1148_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1149_ := _s1148_ in
+ (if ((string_startswith _s1149_ "c.addi4spn")) then
+ (match (string_drop _s1149_ (projT1 (string_length "c.addi4spn"))) with
+ | _s1150_ =>
+ (spc_matches_prefix _s1150_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1151_ _)) =>
+ (match (string_drop _s1150_ _s1151_) with
+ | _s1152_ =>
+ (creg_name_matches_prefix _s1152_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1153_ _)) =>
+ (match (string_drop _s1152_ _s1153_) with
+ | _s1154_ =>
+ (sep_matches_prefix _s1154_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1155_ _)) =>
+ match (string_drop _s1154_ _s1155_) with
+ | _s1156_ =>
+ match (hex_bits_10_matches_prefix _s1156_) with
+ | Some ((v__812, existT _ _s1157_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__812 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__812 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__812 9 2 in
+ let p0_ := string_drop _s1156_ _s1157_ in
+ if ((generic_eq p0_ "")) then Some ((rdc, nzimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1123_ (_s1124_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1124_ with
+ | _s1125_ =>
+ (amo_mnemonic_matches_prefix _s1125_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1126_ _)) =>
+ let _s1127_ := string_drop _s1125_ _s1126_ in
+ (if ((string_startswith _s1127_ ".")) then
+ (match (string_drop _s1127_ (projT1 (string_length "."))) with
+ | _s1128_ =>
+ (size_mnemonic_matches_prefix _s1128_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s1129_ _)) =>
+ (match (string_drop _s1128_ _s1129_) with
+ | _s1130_ =>
+ (maybe_aq_matches_prefix _s1130_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s1131_ _)) =>
+ (match (string_drop _s1130_ _s1131_) with
+ | _s1132_ =>
+ (maybe_rl_matches_prefix _s1132_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s1133_ _)) =>
+ (match (string_drop _s1132_ _s1133_) with
+ | _s1134_ =>
+ (spc_matches_prefix _s1134_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1135_ _)) =>
+ (match (string_drop _s1134_ _s1135_) with
+ | _s1136_ =>
+ (reg_name_matches_prefix _s1136_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s1137_ _)) =>
+ (match (string_drop _s1136_ _s1137_) with
+ | _s1138_ =>
+ (sep_matches_prefix _s1138_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1139_ _)) =>
+ (match (string_drop _s1138_ _s1139_) with
+ | _s1140_ =>
+ (reg_name_matches_prefix _s1140_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s1141_ _)) =>
+ (match (string_drop _s1140_
+ _s1141_) with
+ | _s1142_ =>
+ (sep_matches_prefix
+ _s1142_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s1143_ _)) =>
+ (match (string_drop
+ _s1142_
+ _s1143_) with
+ | _s1144_ =>
+ (reg_name_matches_prefix
+ _s1144_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s1145_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1144_
+ _s1145_ in
+ if ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2))
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1101_ (_s1102_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1103_ := _s1102_ in
+ (if ((string_startswith _s1103_ "sc.")) then
+ (match (string_drop _s1103_ (projT1 (string_length "sc."))) with
+ | _s1104_ =>
+ (size_mnemonic_matches_prefix _s1104_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1105_ _)) =>
+ (match (string_drop _s1104_ _s1105_) with
+ | _s1106_ =>
+ (maybe_aq_matches_prefix _s1106_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1107_ _)) =>
+ (match (string_drop _s1106_ _s1107_) with
+ | _s1108_ =>
+ (maybe_rl_matches_prefix _s1108_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1109_ _)) =>
+ (match (string_drop _s1108_ _s1109_) with
+ | _s1110_ =>
+ (spc_matches_prefix _s1110_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1111_ _)) =>
+ (match (string_drop _s1110_ _s1111_) with
+ | _s1112_ =>
+ (reg_name_matches_prefix _s1112_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1113_ _)) =>
+ (match (string_drop _s1112_ _s1113_) with
+ | _s1114_ =>
+ (sep_matches_prefix _s1114_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1115_ _)) =>
+ (match (string_drop _s1114_ _s1115_) with
+ | _s1116_ =>
+ (reg_name_matches_prefix _s1116_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s1117_ _)) =>
+ (match (string_drop _s1116_ _s1117_) with
+ | _s1118_ =>
+ (sep_matches_prefix _s1118_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s1119_ _)) =>
+ (match (string_drop _s1118_
+ _s1119_) with
+ | _s1120_ =>
+ (reg_name_matches_prefix
+ _s1120_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s1121_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1120_
+ _s1121_ in
+ if ((generic_eq
+ p0_ ""))
+ then
+ Some
+ ((size, aq, rl, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1083_ (_s1084_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5))) :=
+
+ let _s1085_ := _s1084_ in
+ (if ((string_startswith _s1085_ "lr.")) then
+ (match (string_drop _s1085_ (projT1 (string_length "lr."))) with
+ | _s1086_ =>
+ (size_mnemonic_matches_prefix _s1086_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1087_ _)) =>
+ (match (string_drop _s1086_ _s1087_) with
+ | _s1088_ =>
+ (maybe_aq_matches_prefix _s1088_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1089_ _)) =>
+ (match (string_drop _s1088_ _s1089_) with
+ | _s1090_ =>
+ (maybe_rl_matches_prefix _s1090_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1091_ _)) =>
+ (match (string_drop _s1090_ _s1091_) with
+ | _s1092_ =>
+ (spc_matches_prefix _s1092_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1093_ _)) =>
+ (match (string_drop _s1092_ _s1093_) with
+ | _s1094_ =>
+ (reg_name_matches_prefix _s1094_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1095_ _)) =>
+ (match (string_drop _s1094_ _s1095_) with
+ | _s1096_ =>
+ (sep_matches_prefix _s1096_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1097_ _)) =>
+ (match (string_drop _s1096_ _s1097_) with
+ | _s1098_ =>
+ (reg_name_matches_prefix _s1098_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s1099_ _)) =>
+ let p0_ :=
+ string_drop _s1098_ _s1099_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((size, aq, rl, rd, rs1))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5))).
+
+Definition _s1071_ (_s1072_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1073_ := _s1072_ in
+ (if ((string_startswith _s1073_ "sfence.vma")) then
+ (match (string_drop _s1073_ (projT1 (string_length "sfence.vma"))) with
+ | _s1074_ =>
+ (spc_matches_prefix _s1074_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1075_ _)) =>
+ (match (string_drop _s1074_ _s1075_) with
+ | _s1076_ =>
+ (reg_name_matches_prefix _s1076_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s1077_ _)) =>
+ (match (string_drop _s1076_ _s1077_) with
+ | _s1078_ =>
+ (sep_matches_prefix _s1078_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1079_ _)) =>
+ (match (string_drop _s1078_ _s1079_) with
+ | _s1080_ =>
+ (reg_name_matches_prefix _s1080_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1081_ _)) =>
+ let p0_ := string_drop _s1080_ _s1081_ in
+ if ((generic_eq p0_ "")) then Some ((rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1059_ (_s1060_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1061_ := _s1060_ in
+ (if ((string_startswith _s1061_ "fence.tso")) then
+ (match (string_drop _s1061_ (projT1 (string_length "fence.tso"))) with
+ | _s1062_ =>
+ (spc_matches_prefix _s1062_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1063_ _)) =>
+ (match (string_drop _s1062_ _s1063_) with
+ | _s1064_ =>
+ (fence_bits_matches_prefix _s1064_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1065_ _)) =>
+ (match (string_drop _s1064_ _s1065_) with
+ | _s1066_ =>
+ (sep_matches_prefix _s1066_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1067_ _)) =>
+ (match (string_drop _s1066_ _s1067_) with
+ | _s1068_ =>
+ (fence_bits_matches_prefix _s1068_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1069_ _)) =>
+ let p0_ := string_drop _s1068_ _s1069_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1047_ (_s1048_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1049_ := _s1048_ in
+ (if ((string_startswith _s1049_ "fence")) then
+ (match (string_drop _s1049_ (projT1 (string_length "fence"))) with
+ | _s1050_ =>
+ (spc_matches_prefix _s1050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1051_ _)) =>
+ (match (string_drop _s1050_ _s1051_) with
+ | _s1052_ =>
+ (fence_bits_matches_prefix _s1052_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1053_ _)) =>
+ (match (string_drop _s1052_ _s1053_) with
+ | _s1054_ =>
+ (sep_matches_prefix _s1054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1055_ _)) =>
+ (match (string_drop _s1054_ _s1055_) with
+ | _s1056_ =>
+ (fence_bits_matches_prefix _s1056_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1057_ _)) =>
+ let p0_ := string_drop _s1056_ _s1057_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1030_ (_s1031_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1031_ with
+ | _s1032_ =>
+ (shiftiwop_mnemonic_matches_prefix _s1032_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1033_ _)) =>
+ (match (string_drop _s1032_ _s1033_) with
+ | _s1034_ =>
+ (spc_matches_prefix _s1034_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1035_ _)) =>
+ (match (string_drop _s1034_ _s1035_) with
+ | _s1036_ =>
+ (reg_name_matches_prefix _s1036_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1037_ _)) =>
+ (match (string_drop _s1036_ _s1037_) with
+ | _s1038_ =>
+ (sep_matches_prefix _s1038_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1039_ _)) =>
+ (match (string_drop _s1038_ _s1039_) with
+ | _s1040_ =>
+ (reg_name_matches_prefix _s1040_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1041_ _)) =>
+ (match (string_drop _s1040_ _s1041_) with
+ | _s1042_ =>
+ (sep_matches_prefix _s1042_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1043_ _)) =>
+ match (string_drop _s1042_ _s1043_) with
+ | _s1044_ =>
+ match (hex_bits_5_matches_prefix
+ _s1044_) with
+ | Some ((shamt, existT _ _s1045_ _)) =>
+ let p0_ :=
+ string_drop _s1044_ _s1045_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1013_ (_s1014_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1014_ with
+ | _s1015_ =>
+ (rtypew_mnemonic_matches_prefix _s1015_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1016_ _)) =>
+ (match (string_drop _s1015_ _s1016_) with
+ | _s1017_ =>
+ (spc_matches_prefix _s1017_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1018_ _)) =>
+ (match (string_drop _s1017_ _s1018_) with
+ | _s1019_ =>
+ (reg_name_matches_prefix _s1019_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1020_ _)) =>
+ (match (string_drop _s1019_ _s1020_) with
+ | _s1021_ =>
+ (sep_matches_prefix _s1021_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1022_ _)) =>
+ (match (string_drop _s1021_ _s1022_) with
+ | _s1023_ =>
+ (reg_name_matches_prefix _s1023_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1024_ _)) =>
+ (match (string_drop _s1023_ _s1024_) with
+ | _s1025_ =>
+ (sep_matches_prefix _s1025_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1026_ _)) =>
+ (match (string_drop _s1025_ _s1026_) with
+ | _s1027_ =>
+ (reg_name_matches_prefix _s1027_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1028_ _)) =>
+ let p0_ :=
+ string_drop _s1027_ _s1028_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5))).
+
+Definition _s996_ (_s997_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s997_ with
+ | _s998_ =>
+ (shiftw_mnemonic_matches_prefix _s998_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s999_ _)) =>
+ (match (string_drop _s998_ _s999_) with
+ | _s1000_ =>
+ (spc_matches_prefix _s1000_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1001_ _)) =>
+ (match (string_drop _s1000_ _s1001_) with
+ | _s1002_ =>
+ (reg_name_matches_prefix _s1002_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1003_ _)) =>
+ (match (string_drop _s1002_ _s1003_) with
+ | _s1004_ =>
+ (sep_matches_prefix _s1004_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1005_ _)) =>
+ (match (string_drop _s1004_ _s1005_) with
+ | _s1006_ =>
+ (reg_name_matches_prefix _s1006_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1007_ _)) =>
+ (match (string_drop _s1006_ _s1007_) with
+ | _s1008_ =>
+ (sep_matches_prefix _s1008_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1009_ _)) =>
+ match (string_drop _s1008_ _s1009_) with
+ | _s1010_ =>
+ match (hex_bits_5_matches_prefix
+ _s1010_) with
+ | Some ((shamt, existT _ _s1011_ _)) =>
+ let p0_ :=
+ string_drop _s1010_ _s1011_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5))).
+
+Definition _s980_ (_s981_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s982_ := _s981_ in
+ (if ((string_startswith _s982_ "addiw")) then
+ (match (string_drop _s982_ (projT1 (string_length "addiw"))) with
+ | _s983_ =>
+ (spc_matches_prefix _s983_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s984_ _)) =>
+ (match (string_drop _s983_ _s984_) with
+ | _s985_ =>
+ (reg_name_matches_prefix _s985_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s986_ _)) =>
+ (match (string_drop _s985_ _s986_) with
+ | _s987_ =>
+ (sep_matches_prefix _s987_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s988_ _)) =>
+ (match (string_drop _s987_ _s988_) with
+ | _s989_ =>
+ (reg_name_matches_prefix _s989_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s990_ _)) =>
+ (match (string_drop _s989_ _s990_) with
+ | _s991_ =>
+ (sep_matches_prefix _s991_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s992_ _)) =>
+ match (string_drop _s991_ _s992_) with
+ | _s993_ =>
+ match (hex_bits_12_matches_prefix _s993_) with
+ | Some ((imm, existT _ _s994_ _)) =>
+ let p0_ := string_drop _s993_ _s994_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s952_ (_s953_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s954_ := _s953_ in
+ (if ((string_startswith _s954_ "s")) then
+ (match (string_drop _s954_ (projT1 (string_length "s"))) with
+ | _s955_ =>
+ (size_mnemonic_matches_prefix _s955_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s956_ _)) =>
+ (match (string_drop _s955_ _s956_) with
+ | _s957_ =>
+ (maybe_aq_matches_prefix _s957_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s958_ _)) =>
+ (match (string_drop _s957_ _s958_) with
+ | _s959_ =>
+ (maybe_rl_matches_prefix _s959_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s960_ _)) =>
+ (match (string_drop _s959_ _s960_) with
+ | _s961_ =>
+ (spc_matches_prefix _s961_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s962_ _)) =>
+ (match (string_drop _s961_ _s962_) with
+ | _s963_ =>
+ (reg_name_matches_prefix _s963_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s964_ _)) =>
+ (match (string_drop _s963_ _s964_) with
+ | _s965_ =>
+ (sep_matches_prefix _s965_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s966_ _)) =>
+ (match (string_drop _s965_ _s966_) with
+ | _s967_ =>
+ (match (hex_bits_12_matches_prefix _s967_) with
+ | Some ((imm, existT _ _s968_ _)) =>
+ (match (string_drop _s967_ _s968_) with
+ | _s969_ =>
+ (opt_spc_matches_prefix _s969_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s970_ _)) =>
+ let _s971_ :=
+ string_drop _s969_ _s970_ in
+ (if ((string_startswith _s971_
+ "(")) then
+ (match (string_drop _s971_
+ (projT1
+ (string_length
+ "("))) with
+ | _s972_ =>
+ (opt_spc_matches_prefix
+ _s972_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s973_ _)) =>
+ (match (string_drop
+ _s972_
+ _s973_) with
+ | _s974_ =>
+ (reg_name_matches_prefix
+ _s974_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s975_ _)) =>
+ (match (string_drop
+ _s974_
+ _s975_) with
+ | _s976_ =>
+ (opt_spc_matches_prefix
+ _s976_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s977_ _)) =>
+ let _s978_ :=
+ string_drop
+ _s976_
+ _s977_ in
+ if
+ ((string_startswith
+ _s978_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s978_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, aq, rl, rs2, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s922_ (_s923_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s924_ := _s923_ in
+ (if ((string_startswith _s924_ "l")) then
+ (match (string_drop _s924_ (projT1 (string_length "l"))) with
+ | _s925_ =>
+ (size_mnemonic_matches_prefix _s925_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s926_ _)) =>
+ (match (string_drop _s925_ _s926_) with
+ | _s927_ =>
+ (maybe_u_matches_prefix _s927_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s928_ _)) =>
+ (match (string_drop _s927_ _s928_) with
+ | _s929_ =>
+ (maybe_aq_matches_prefix _s929_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s930_ _)) =>
+ (match (string_drop _s929_ _s930_) with
+ | _s931_ =>
+ (maybe_rl_matches_prefix _s931_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s932_ _)) =>
+ (match (string_drop _s931_ _s932_) with
+ | _s933_ =>
+ (spc_matches_prefix _s933_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s934_ _)) =>
+ (match (string_drop _s933_ _s934_) with
+ | _s935_ =>
+ (reg_name_matches_prefix _s935_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s936_ _)) =>
+ (match (string_drop _s935_ _s936_) with
+ | _s937_ =>
+ (sep_matches_prefix _s937_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s938_ _)) =>
+ (match (string_drop _s937_ _s938_) with
+ | _s939_ =>
+ (match (hex_bits_12_matches_prefix
+ _s939_) with
+ | Some ((imm, existT _ _s940_ _)) =>
+ (match (string_drop _s939_
+ _s940_) with
+ | _s941_ =>
+ (opt_spc_matches_prefix
+ _s941_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s942_ _)) =>
+ let _s943_ :=
+ string_drop _s941_
+ _s942_ in
+ (if ((string_startswith
+ _s943_ "("))
+ then
+ (match (string_drop
+ _s943_
+ (projT1
+ (string_length
+ "("))) with
+ | _s944_ =>
+ (opt_spc_matches_prefix
+ _s944_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s945_ _)) =>
+ (match (string_drop
+ _s944_
+ _s945_) with
+ | _s946_ =>
+ (reg_name_matches_prefix
+ _s946_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s947_ _)) =>
+ (match (string_drop
+ _s946_
+ _s947_) with
+ | _s948_ =>
+ (opt_spc_matches_prefix
+ _s948_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s949_ _)) =>
+ let _s950_ :=
+ string_drop
+ _s948_
+ _s949_ in
+ if
+ ((string_startswith
+ _s950_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s950_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s905_ (_s906_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s906_ with
+ | _s907_ =>
+ (rtype_mnemonic_matches_prefix _s907_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s908_ _)) =>
+ (match (string_drop _s907_ _s908_) with
+ | _s909_ =>
+ (spc_matches_prefix _s909_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s910_ _)) =>
+ (match (string_drop _s909_ _s910_) with
+ | _s911_ =>
+ (reg_name_matches_prefix _s911_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s912_ _)) =>
+ (match (string_drop _s911_ _s912_) with
+ | _s913_ =>
+ (sep_matches_prefix _s913_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s914_ _)) =>
+ (match (string_drop _s913_ _s914_) with
+ | _s915_ =>
+ (reg_name_matches_prefix _s915_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s916_ _)) =>
+ (match (string_drop _s915_ _s916_) with
+ | _s917_ =>
+ (sep_matches_prefix _s917_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s918_ _)) =>
+ (match (string_drop _s917_ _s918_) with
+ | _s919_ =>
+ (reg_name_matches_prefix _s919_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s920_ _)) =>
+ let p0_ :=
+ string_drop _s919_ _s920_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5))).
+
+Definition _s888_ (_s889_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6))) :=
+
+ (match _s889_ with
+ | _s890_ =>
+ (shiftiop_mnemonic_matches_prefix _s890_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s891_ _)) =>
+ (match (string_drop _s890_ _s891_) with
+ | _s892_ =>
+ (spc_matches_prefix _s892_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s893_ _)) =>
+ (match (string_drop _s892_ _s893_) with
+ | _s894_ =>
+ (reg_name_matches_prefix _s894_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s895_ _)) =>
+ (match (string_drop _s894_ _s895_) with
+ | _s896_ =>
+ (sep_matches_prefix _s896_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s897_ _)) =>
+ (match (string_drop _s896_ _s897_) with
+ | _s898_ =>
+ (reg_name_matches_prefix _s898_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s899_ _)) =>
+ (match (string_drop _s898_ _s899_) with
+ | _s900_ =>
+ (sep_matches_prefix _s900_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s901_ _)) =>
+ match (string_drop _s900_ _s901_) with
+ | _s902_ =>
+ match (hex_bits_6_matches_prefix
+ _s902_) with
+ | Some ((shamt, existT _ _s903_ _)) =>
+ let p0_ :=
+ string_drop _s902_ _s903_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6))).
+
+Definition _s871_ (_s872_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s872_ with
+ | _s873_ =>
+ (itype_mnemonic_matches_prefix _s873_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s874_ _)) =>
+ (match (string_drop _s873_ _s874_) with
+ | _s875_ =>
+ (spc_matches_prefix _s875_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s876_ _)) =>
+ (match (string_drop _s875_ _s876_) with
+ | _s877_ =>
+ (reg_name_matches_prefix _s877_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s878_ _)) =>
+ (match (string_drop _s877_ _s878_) with
+ | _s879_ =>
+ (sep_matches_prefix _s879_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s880_ _)) =>
+ (match (string_drop _s879_ _s880_) with
+ | _s881_ =>
+ (reg_name_matches_prefix _s881_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s882_ _)) =>
+ (match (string_drop _s881_ _s882_) with
+ | _s883_ =>
+ (sep_matches_prefix _s883_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s884_ _)) =>
+ match (string_drop _s883_ _s884_) with
+ | _s885_ =>
+ match (hex_bits_12_matches_prefix
+ _s885_) with
+ | Some ((imm, existT _ _s886_ _)) =>
+ let p0_ :=
+ string_drop _s885_ _s886_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12))).
+
+Definition _s854_ (_s855_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13))) :=
+
+ (match _s855_ with
+ | _s856_ =>
+ (btype_mnemonic_matches_prefix _s856_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s857_ _)) =>
+ (match (string_drop _s856_ _s857_) with
+ | _s858_ =>
+ (spc_matches_prefix _s858_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s859_ _)) =>
+ (match (string_drop _s858_ _s859_) with
+ | _s860_ =>
+ (reg_name_matches_prefix _s860_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s861_ _)) =>
+ (match (string_drop _s860_ _s861_) with
+ | _s862_ =>
+ (sep_matches_prefix _s862_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s863_ _)) =>
+ (match (string_drop _s862_ _s863_) with
+ | _s864_ =>
+ (reg_name_matches_prefix _s864_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s865_ _)) =>
+ (match (string_drop _s864_ _s865_) with
+ | _s866_ =>
+ (sep_matches_prefix _s866_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s867_ _)) =>
+ match (string_drop _s866_ _s867_) with
+ | _s868_ =>
+ match (hex_bits_13_matches_prefix
+ _s868_) with
+ | Some ((imm, existT _ _s869_ _)) =>
+ let p0_ :=
+ string_drop _s868_ _s869_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rs1, rs2, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13))).
+
+Definition _s838_ (_s839_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s840_ := _s839_ in
+ (if ((string_startswith _s840_ "jalr")) then
+ (match (string_drop _s840_ (projT1 (string_length "jalr"))) with
+ | _s841_ =>
+ (spc_matches_prefix _s841_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s842_ _)) =>
+ (match (string_drop _s841_ _s842_) with
+ | _s843_ =>
+ (reg_name_matches_prefix _s843_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s844_ _)) =>
+ (match (string_drop _s843_ _s844_) with
+ | _s845_ =>
+ (sep_matches_prefix _s845_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s846_ _)) =>
+ (match (string_drop _s845_ _s846_) with
+ | _s847_ =>
+ (reg_name_matches_prefix _s847_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s848_ _)) =>
+ (match (string_drop _s847_ _s848_) with
+ | _s849_ =>
+ (sep_matches_prefix _s849_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s850_ _)) =>
+ match (string_drop _s849_ _s850_) with
+ | _s851_ =>
+ match (hex_bits_12_matches_prefix _s851_) with
+ | Some ((imm, existT _ _s852_ _)) =>
+ let p0_ := string_drop _s851_ _s852_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s826_ (_s827_ : string)
+: M (option ((mword 5 * mword 21))) :=
+
+ let _s828_ := _s827_ in
+ (if ((string_startswith _s828_ "jal")) then
+ (match (string_drop _s828_ (projT1 (string_length "jal"))) with
+ | _s829_ =>
+ (spc_matches_prefix _s829_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s830_ _)) =>
+ (match (string_drop _s829_ _s830_) with
+ | _s831_ =>
+ (reg_name_matches_prefix _s831_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s832_ _)) =>
+ (match (string_drop _s831_ _s832_) with
+ | _s833_ =>
+ (sep_matches_prefix _s833_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s834_ _)) =>
+ match (string_drop _s833_ _s834_) with
+ | _s835_ =>
+ match (hex_bits_21_matches_prefix _s835_) with
+ | Some ((imm, existT _ _s836_ _)) =>
+ let p0_ := string_drop _s835_ _s836_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ else returnm (None : option ((mword 5 * mword 21))))
+ : M (option ((mword 5 * mword 21))).
+
+Definition _s813_ (_s814_ : string)
+: M (option ((uop * mword 5 * mword 20))) :=
+
+ (match _s814_ with
+ | _s815_ =>
+ (utype_mnemonic_matches_prefix _s815_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s816_ _)) =>
+ (match (string_drop _s815_ _s816_) with
+ | _s817_ =>
+ (spc_matches_prefix _s817_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s818_ _)) =>
+ (match (string_drop _s817_ _s818_) with
+ | _s819_ =>
+ (reg_name_matches_prefix _s819_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s820_ _)) =>
+ (match (string_drop _s819_ _s820_) with
+ | _s821_ =>
+ (sep_matches_prefix _s821_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s822_ _)) =>
+ match (string_drop _s821_ _s822_) with
+ | _s823_ =>
+ match (hex_bits_20_matches_prefix _s823_) with
+ | Some ((imm, existT _ _s824_ _)) =>
+ let p0_ := string_drop _s823_ _s824_ in
+ if ((generic_eq p0_ "")) then Some ((op, rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20))).
+
+Definition assembly_backwards (arg_ : string)
+: M (ast) :=
+
+ let _s825_ := arg_ in
+ (_s813_ _s825_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) =>
+ (if ((match w__0 with | Some ((op, rd, imm)) => true | _ => false end)) then
+ (_s813_ _s825_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) =>
+ (match w__1 with
+ | Some ((op, rd, imm)) => returnm ((UTYPE ((imm, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s826_ _s825_) >>= fun w__4 : option ((mword 5 * mword 21)) =>
+ (if ((match w__4 with | Some ((rd, imm)) => true | _ => false end)) then
+ (_s826_ _s825_) >>= fun w__5 : option ((mword 5 * mword 21)) =>
+ (match w__5 with
+ | Some ((rd, imm)) => returnm ((RISCV_JAL ((imm, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s838_ _s825_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm)) => true | _ => false end)) then
+ (_s838_ _s825_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm)) => returnm ((RISCV_JALR ((imm, rs1, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s854_ _s825_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm)) => true | _ => false end)) then
+ (_s854_ _s825_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm)) => returnm ((BTYPE ((imm, rs2, rs1, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s871_ _s825_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm)) => true | _ => false end)) then
+ (_s871_ _s825_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm)) => returnm ((ITYPE ((imm, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s888_ _s825_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt)) => true | _ => false end))
+ then
+ (_s888_ _s825_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTIOP ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s905_ _s825_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2)) => true | _ => false end))
+ then
+ (_s905_ _s825_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm ((RTYPE ((rs2, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s922_ _s825_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s922_ _s825_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) =>
+ returnm ((LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s952_ _s825_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s952_ _s825_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) =>
+ returnm ((STORE ((imm, rs2, rs1, size, aq, rl))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s980_ _s825_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s980_ _s825_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm)) =>
+ returnm ((ADDIW ((imm, rs1, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s996_ _s825_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s996_ _s825_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTW ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1013_ _s825_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1013_ _s825_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm ((RTYPEW ((rs2, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1030_ _s825_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1030_ _s825_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTIWOP ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1047_ _s825_) >>= fun w__52 : option ((mword 4 * mword 4)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1047_ _s825_) >>= fun w__53 : option ((mword 4 * mword 4)) =>
+ (match w__53 with
+ | Some ((pred, succ)) =>
+ returnm ((FENCE ((pred, succ))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1059_ _s825_) >>= fun w__56 : option ((mword 4 * mword 4)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1059_ _s825_) >>= fun w__57 : option ((mword 4 * mword 4)) =>
+ (match w__57 with
+ | Some ((pred, succ)) =>
+ returnm ((FENCE_TSO ((pred, succ))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else if ((generic_eq _s825_ "fence.i")) then
+ returnm ((FENCEI
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "ecall")) then
+ returnm ((ECALL
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "mret")) then
+ returnm ((MRET
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "sret")) then
+ returnm ((SRET
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "ebreak")) then
+ returnm ((EBREAK
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "wfi")) then
+ returnm ((WFI
+ (tt))
+ : ast )
+ else
+ (_s1071_ _s825_) >>= fun w__60 : option ((mword 5 * mword 5)) =>
+ (if ((match w__60 with
+ | Some ((rs1, rs2)) => true
+ | _ => false
+ end)) then
+ (_s1071_ _s825_) >>= fun w__61 : option ((mword 5 * mword 5)) =>
+ (match w__61 with
+ | Some ((rs1, rs2)) =>
+ returnm ((SFENCE_VMA ((rs1, rs2))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1083_ _s825_) >>= fun w__64 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (if ((match w__64 with
+ | Some ((size, aq, rl, rd, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1083_ _s825_) >>= fun w__65 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (match w__65 with
+ | Some ((size, aq, rl, rd, rs1)) =>
+ returnm ((LOADRES
+ ((aq, rl, rs1, size, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1101_ _s825_) >>= fun w__68 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__68 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1101_ _s825_) >>= fun w__69 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__69 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ returnm ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1123_ _s825_) >>= fun w__72 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__72 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1123_ _s825_) >>= fun w__73 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__73 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ returnm ((AMO
+ ((op, aq, rl, rs2, rs1, width, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else if ((generic_eq _s825_ "c.nop")) then
+ returnm ((C_NOP
+ (tt))
+ : ast )
+ else
+ (_s1147_ _s825_) >>= fun w__76 : option ((mword 3 * mword 8)) =>
+ (if ((match w__76 with
+ | Some ((rdc, nzimm)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s1147_ _s825_) >>= fun w__77 : option ((mword 3 * mword 8)) =>
+ (match w__77 with
+ | Some ((rdc, nzimm)) =>
+ returnm ((C_ADDI4SPN
+ ((rdc, nzimm)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1159_ _s825_) >>= fun w__80 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__80 with
+ | Some ((rdc, rsc, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1159_ _s825_) >>= fun w__81 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__81 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm ((C_LW
+ ((uimm, rsc, rdc)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1175_ _s825_) >>= fun w__84 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__84 with
+ | Some ((rdc, rsc, uimm)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1175_ _s825_) >>= fun w__85 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__85 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm ((C_LD
+ ((uimm, rsc, rdc)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1191_ _s825_) >>= fun w__88 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__88 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1191_ _s825_) >>= fun w__89 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__89 with
+ | Some ((rsc1, rsc2, uimm)) =>
+ returnm ((C_SW
+ ((uimm, rsc1, rsc2)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1207_ _s825_) >>= fun w__92 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__92 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1207_ _s825_) >>= fun w__93 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__93 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ returnm ((C_SD
+ ((uimm, rsc1, rsc2)))
+ : ast )
+ | _ =>
+ exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1223_ _s825_) >>= fun w__96 : option ((mword 5 * mword 6)) =>
+ (if ((match w__96 with
+ | Some ((rsd, nzi)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s1223_ _s825_) >>= fun w__97 : option ((mword 5 * mword 6)) =>
+ (match w__97 with
+ | Some ((rsd, nzi)) =>
+ returnm ((C_ADDI
+ ((nzi, rsd)))
+ : ast )
+ | _ =>
+ exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1235_ _s825_) >>= fun w__100 : option (mword 11) =>
+ (if ((match w__100 with
+ | Some (imm) =>
+ Z.eqb 32 32
+ | _ => false
+ end)) then
+ (_s1235_ _s825_) >>= fun w__101 : option (mword 11) =>
+ (match w__101 with
+ | Some (imm) =>
+ returnm ((C_JAL
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1243_ _s825_) >>= fun w__104 : option ((mword 5 * mword 6)) =>
+ (if ((match w__104 with
+ | Some
+ ((rsd, imm)) =>
+ Z.eqb 32
+ 64
+ | _ => false
+ end)) then
+ (_s1243_ _s825_) >>= fun w__105 : option ((mword 5 * mword 6)) =>
+ (match w__105 with
+ | Some
+ ((rsd, imm)) =>
+ returnm ((C_ADDIW
+ ((imm, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1255_ _s825_) >>= fun w__108 : option ((mword 5 * mword 6)) =>
+ (if ((match w__108 with
+ | Some
+ ((rd, imm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s1255_
+ _s825_) >>= fun w__109 : option ((mword 5 * mword 6)) =>
+ (match w__109 with
+ | Some
+ ((rd, imm)) =>
+ returnm ((C_LI
+ ((imm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1267_
+ _s825_) >>= fun w__112 : option (mword 6) =>
+ (if ((match w__112 with
+ | Some
+ (imm) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1267_
+ _s825_) >>= fun w__113 : option (mword 6) =>
+ (match w__113 with
+ | Some
+ (imm) =>
+ returnm ((C_ADDI16SP
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1275_
+ _s825_) >>= fun w__116 : option ((mword 5 * mword 6)) =>
+ (if ((match w__116 with
+ | Some
+ ((rd, imm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1275_
+ _s825_) >>= fun w__117 : option ((mword 5 * mword 6)) =>
+ (match w__117 with
+ | Some
+ ((rd, imm)) =>
+ returnm ((C_LUI
+ ((imm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1287_
+ _s825_) >>= fun w__120 : option ((mword 3 * mword 6)) =>
+ (if ((match w__120 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1287_
+ _s825_) >>= fun w__121 : option ((mword 3 * mword 6)) =>
+ (match w__121 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SRLI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1299_
+ _s825_) >>= fun w__124 : option ((mword 3 * mword 6)) =>
+ (if ((match w__124 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1299_
+ _s825_) >>= fun w__125 : option ((mword 3 * mword 6)) =>
+ (match w__125 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SRAI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1311_
+ _s825_) >>= fun w__128 : option ((mword 3 * mword 6)) =>
+ (if
+ ((match w__128 with
+ | Some
+ ((rsd, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1311_
+ _s825_) >>= fun w__129 : option ((mword 3 * mword 6)) =>
+ (match w__129 with
+ | Some
+ ((rsd, imm)) =>
+ returnm ((C_ANDI
+ ((imm, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1323_
+ _s825_) >>= fun w__132 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__132 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1323_
+ _s825_) >>= fun w__133 : option ((mword 3 * mword 3)) =>
+ (match w__133 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_SUB
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1335_
+ _s825_) >>= fun w__136 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__136 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1335_
+ _s825_) >>= fun w__137 : option ((mword 3 * mword 3)) =>
+ (match w__137 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_XOR
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1347_
+ _s825_) >>= fun w__140 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__140 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1347_
+ _s825_) >>= fun w__141 : option ((mword 3 * mword 3)) =>
+ (match w__141 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_OR
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1359_
+ _s825_) >>= fun w__144 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__144 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1359_
+ _s825_) >>= fun w__145 : option ((mword 3 * mword 3)) =>
+ (match w__145 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_AND
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1371_
+ _s825_) >>= fun w__148 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__148 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1371_
+ _s825_) >>= fun w__149 : option ((mword 3 * mword 3)) =>
+ (match w__149 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_SUBW
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1383_
+ _s825_) >>= fun w__152 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__152 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1383_
+ _s825_) >>= fun w__153 : option ((mword 3 * mword 3)) =>
+ (match w__153 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_ADDW
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1395_
+ _s825_) >>= fun w__156 : option (mword 11) =>
+ (if
+ ((match w__156 with
+ | Some
+ (imm) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1395_
+ _s825_) >>= fun w__157 : option (mword 11) =>
+ (match w__157 with
+ | Some
+ (imm) =>
+ returnm ((C_J
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1403_
+ _s825_) >>= fun w__160 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__160 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1403_
+ _s825_) >>= fun w__161 : option ((mword 3 * mword 8)) =>
+ (match w__161 with
+ | Some
+ ((rs, imm)) =>
+ returnm ((C_BEQZ
+ ((imm, rs)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1415_
+ _s825_) >>= fun w__164 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__164 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1415_
+ _s825_) >>= fun w__165 : option ((mword 3 * mword 8)) =>
+ (match w__165 with
+ | Some
+ ((rs, imm)) =>
+ returnm ((C_BNEZ
+ ((imm, rs)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1427_
+ _s825_) >>= fun w__168 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__168 with
+ | Some
+ ((rsd, shamt)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1427_
+ _s825_) >>= fun w__169 : option ((mword 5 * mword 6)) =>
+ (match w__169 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SLLI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1439_
+ _s825_) >>= fun w__172 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__172 with
+ | Some
+ ((rd, uimm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1439_
+ _s825_) >>= fun w__173 : option ((mword 5 * mword 6)) =>
+ (match w__173 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_LWSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1451_
+ _s825_) >>= fun w__176 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__176 with
+ | Some
+ ((rd, uimm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 32
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s1451_
+ _s825_) >>= fun w__177 : option ((mword 5 * mword 6)) =>
+ (match w__177 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_LDSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1463_
+ _s825_) >>= fun w__180 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__180 with
+ | Some
+ ((rd, uimm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1463_
+ _s825_) >>= fun w__181 : option ((mword 5 * mword 6)) =>
+ (match w__181 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_SWSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1475_
+ _s825_) >>= fun w__184 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__184 with
+ | Some
+ ((rs2, uimm)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1475_
+ _s825_) >>= fun w__185 : option ((mword 5 * mword 6)) =>
+ (match w__185 with
+ | Some
+ ((rs2, uimm)) =>
+ returnm ((C_SDSP
+ ((uimm, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1487_
+ _s825_) >>= fun w__188 : option (mword 5) =>
+ (if
+ ((match w__188 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1487_
+ _s825_) >>= fun w__189 : option (mword 5) =>
+ (match w__189 with
+ | Some
+ (rs1) =>
+ returnm ((C_JR
+ (rs1))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1495_
+ _s825_) >>= fun w__192 : option (mword 5) =>
+ (if
+ ((match w__192 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1495_
+ _s825_) >>= fun w__193 : option (mword 5) =>
+ (match w__193 with
+ | Some
+ (rs1) =>
+ returnm ((C_JALR
+ (rs1))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1503_
+ _s825_) >>= fun w__196 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__196 with
+ | Some
+ ((rd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1503_
+ _s825_) >>= fun w__197 : option ((mword 5 * mword 5)) =>
+ (match w__197 with
+ | Some
+ ((rd, rs2)) =>
+ returnm ((C_MV
+ ((rd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else if
+ ((generic_eq
+ _s825_
+ "c.ebreak"))
+ then
+ returnm ((C_EBREAK
+ (tt))
+ : ast )
+ else
+ (_s1515_
+ _s825_) >>= fun w__200 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__200 with
+ | Some
+ ((rsd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1515_
+ _s825_) >>= fun w__201 : option ((mword 5 * mword 5)) =>
+ (match w__201 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_ADD
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1527_
+ _s825_) >>= fun w__204 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__204 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1527_
+ _s825_) >>= fun w__205 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__205 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ returnm ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1544_
+ _s825_) >>= fun w__208 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__208 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1544_
+ _s825_) >>= fun w__209 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__209 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((DIV
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1562_
+ _s825_) >>= fun w__212 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__212 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1562_
+ _s825_) >>= fun w__213 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__213 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((REM
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1580_
+ _s825_) >>= fun w__216 : option ((mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1580_
+ _s825_) >>= fun w__217 : option ((mword 5 * mword 5 * mword 5)) =>
+ (match w__217 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ returnm ((MULW
+ ((rs2, rs1, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1596_
+ _s825_) >>= fun w__220 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1596_
+ _s825_) >>= fun w__221 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__221 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((DIVW
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1615_
+ _s825_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1615_
+ _s825_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((REMW
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1634_
+ _s825_) >>= fun w__228 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1634_
+ _s825_) >>= fun w__229 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__229 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm ((CSR
+ ((csr, rs1, rd, true, op)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1652_
+ _s825_) >>= fun w__232 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1652_
+ _s825_) >>= fun w__233 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__233 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm ((CSR
+ ((csr, rs1, rd, false, op)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else if
+ ((generic_eq
+ _s825_
+ "uret"))
+ then
+ returnm ((URET
+ (tt))
+ : ast )
+ else
+ (_s1669_
+ _s825_) >>= fun w__236 : option (mword 32) =>
+ (if
+ ((match w__236 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1669_
+ _s825_) >>= fun w__237 : option (mword 32) =>
+ (match w__237 with
+ | Some
+ (s) =>
+ returnm ((ILLEGAL
+ (s))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1677_
+ _s825_) >>= fun w__240 : option (mword 16) =>
+ (if
+ ((match w__240 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1677_
+ _s825_) >>= fun w__241 : option (mword 16) =>
+ (match w__241 with
+ | Some
+ (s) =>
+ returnm ((C_ILLEGAL
+ (s))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ assert_exp' false "Pattern match failure at unknown location" >>= fun _ =>
+ exit tt)
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast).
+
+Definition assembly_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | UTYPE ((imm, rd, op)) => true
+ | RISCV_JAL ((imm, rd)) => true
+ | RISCV_JALR ((imm, rs1, rd)) => true
+ | BTYPE ((imm, rs2, rs1, op)) => true
+ | ITYPE ((imm, rs1, rd, op)) => true
+ | SHIFTIOP ((shamt, rs1, rd, op)) => true
+ | RTYPE ((rs2, rs1, rd, op)) => true
+ | LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl)) => true
+ | STORE ((imm, rs2, rs1, size, aq, rl)) => true
+ | ADDIW ((imm, rs1, rd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | FENCE ((pred, succ)) => true
+ | FENCE_TSO ((pred, succ)) => true
+ | FENCEI (tt) => true
+ | ECALL (tt) => true
+ | MRET (tt) => true
+ | SRET (tt) => true
+ | EBREAK (tt) => true
+ | WFI (tt) => true
+ | SFENCE_VMA ((rs1, rs2)) => true
+ | LOADRES ((aq, rl, rs1, size, rd)) => true
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) => true
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => true
+ | C_NOP (tt) => true
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then true else false
+ | C_LW ((uimm, rsc, rdc)) => true
+ | C_LD ((uimm, rsc, rdc)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_SW ((uimm, rsc1, rsc2)) => true
+ | C_SD ((uimm, rsc1, rsc2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_ADDI ((nzi, rsd)) =>
+ if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_JAL (imm) => if sumbool_of_bool ((Z.eqb 32 32)) then true else false
+ | C_ADDIW ((imm, rsd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_LI ((imm, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_ADDI16SP (imm) =>
+ if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_LUI ((imm, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))
+ : bool))) then
+ true
+ else false
+ | C_SRLI ((shamt, rsd)) =>
+ if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_SRAI ((shamt, rsd)) =>
+ if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_ANDI ((imm, rsd)) => true
+ | C_SUB ((rsd, rs2)) => true
+ | C_XOR ((rsd, rs2)) => true
+ | C_OR ((rsd, rs2)) => true
+ | C_AND ((rsd, rs2)) => true
+ | C_SUBW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_ADDW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_J (imm) => true
+ | C_BEQZ ((imm, rs)) => true
+ | C_BNEZ ((imm, rs)) => true
+ | C_SLLI ((shamt, rsd)) =>
+ if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_LWSP ((uimm, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_LDSP ((uimm, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ (Z.eqb 32 64))) then
+ true
+ else false
+ | C_SWSP ((uimm, rd)) => true
+ | C_SDSP ((uimm, rs2)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | C_JR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_JALR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_MV ((rd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_EBREAK (tt) => true
+ | C_ADD ((rsd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => true
+ | DIV ((rs2, rs1, rd, s)) => true
+ | REM ((rs2, rs1, rd, s)) => true
+ | MULW ((rs2, rs1, rd)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | DIVW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | REMW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 32 64)) then true else false
+ | CSR ((csr, rs1, rd, true, op)) => true
+ | CSR ((csr, rs1, rd, false, op)) => true
+ | URET (tt) => true
+ | ILLEGAL (s) => true
+ | C_ILLEGAL (s) => true
+ end.
+
+Definition _s2549_ (_s2550_ : string)
+: M (option (mword 16)) :=
+
+ let _s2551_ := _s2550_ in
+ (if ((string_startswith _s2551_ "c.illegal")) then
+ (match (string_drop _s2551_ (projT1 (string_length "c.illegal"))) with
+ | _s2552_ =>
+ (spc_matches_prefix _s2552_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2553_ _)) =>
+ match (string_drop _s2552_ _s2553_) with
+ | _s2554_ =>
+ match (hex_bits_16_matches_prefix _s2554_) with
+ | Some ((s, existT _ _s2555_ _)) =>
+ let p0_ := string_drop _s2554_ _s2555_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 16))
+ end)
+ : M (option (mword 16))
+ else returnm (None : option (mword 16)))
+ : M (option (mword 16)).
+
+Definition _s2541_ (_s2542_ : string)
+: M (option (mword 32)) :=
+
+ let _s2543_ := _s2542_ in
+ (if ((string_startswith _s2543_ "illegal")) then
+ (match (string_drop _s2543_ (projT1 (string_length "illegal"))) with
+ | _s2544_ =>
+ (spc_matches_prefix _s2544_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2545_ _)) =>
+ match (string_drop _s2544_ _s2545_) with
+ | _s2546_ =>
+ match (hex_bits_32_matches_prefix _s2546_) with
+ | Some ((s, existT _ _s2547_ _)) =>
+ let p0_ := string_drop _s2546_ _s2547_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 32))
+ end)
+ : M (option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option (mword 32)).
+
+Definition _s2524_ (_s2525_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s2525_ with
+ | _s2526_ =>
+ (csr_mnemonic_matches_prefix _s2526_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2527_ _)) =>
+ (match (string_drop _s2526_ _s2527_) with
+ | _s2528_ =>
+ (spc_matches_prefix _s2528_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2529_ _)) =>
+ (match (string_drop _s2528_ _s2529_) with
+ | _s2530_ =>
+ (reg_name_matches_prefix _s2530_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2531_ _)) =>
+ (match (string_drop _s2530_ _s2531_) with
+ | _s2532_ =>
+ (sep_matches_prefix _s2532_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2533_ _)) =>
+ (match (string_drop _s2532_ _s2533_) with
+ | _s2534_ =>
+ (reg_name_matches_prefix _s2534_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2535_ _)) =>
+ (match (string_drop _s2534_ _s2535_) with
+ | _s2536_ =>
+ (sep_matches_prefix _s2536_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2537_ _)) =>
+ (match (string_drop _s2536_ _s2537_) with
+ | _s2538_ =>
+ (csr_name_map_matches_prefix _s2538_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s2539_ _)) =>
+ let p0_ :=
+ string_drop _s2538_ _s2539_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s2506_ (_s2507_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s2507_ with
+ | _s2508_ =>
+ (csr_mnemonic_matches_prefix _s2508_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2509_ _)) =>
+ let _s2510_ := string_drop _s2508_ _s2509_ in
+ (if ((string_startswith _s2510_ "i")) then
+ (match (string_drop _s2510_ (projT1 (string_length "i"))) with
+ | _s2511_ =>
+ (spc_matches_prefix _s2511_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2512_ _)) =>
+ (match (string_drop _s2511_ _s2512_) with
+ | _s2513_ =>
+ (reg_name_matches_prefix _s2513_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2514_ _)) =>
+ (match (string_drop _s2513_ _s2514_) with
+ | _s2515_ =>
+ (sep_matches_prefix _s2515_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2516_ _)) =>
+ (match (string_drop _s2515_ _s2516_) with
+ | _s2517_ =>
+ (match (hex_bits_5_matches_prefix _s2517_) with
+ | Some ((rs1, existT _ _s2518_ _)) =>
+ (match (string_drop _s2517_ _s2518_) with
+ | _s2519_ =>
+ (sep_matches_prefix _s2519_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2520_ _)) =>
+ (match (string_drop _s2519_ _s2520_) with
+ | _s2521_ =>
+ (csr_name_map_matches_prefix _s2521_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s2522_ _)) =>
+ let p0_ :=
+ string_drop _s2521_ _s2522_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s2487_ (_s2488_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2489_ := _s2488_ in
+ (if ((string_startswith _s2489_ "rem")) then
+ (match (string_drop _s2489_ (projT1 (string_length "rem"))) with
+ | _s2490_ =>
+ (maybe_not_u_matches_prefix _s2490_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2491_ _)) =>
+ let _s2492_ := string_drop _s2490_ _s2491_ in
+ (if ((string_startswith _s2492_ "w")) then
+ (match (string_drop _s2492_ (projT1 (string_length "w"))) with
+ | _s2493_ =>
+ (spc_matches_prefix _s2493_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2494_ _)) =>
+ (match (string_drop _s2493_ _s2494_) with
+ | _s2495_ =>
+ (reg_name_matches_prefix _s2495_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2496_ _)) =>
+ (match (string_drop _s2495_ _s2496_) with
+ | _s2497_ =>
+ (sep_matches_prefix _s2497_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2498_ _)) =>
+ (match (string_drop _s2497_ _s2498_) with
+ | _s2499_ =>
+ (reg_name_matches_prefix _s2499_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2500_ _)) =>
+ (match (string_drop _s2499_ _s2500_) with
+ | _s2501_ =>
+ (sep_matches_prefix _s2501_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2502_ _)) =>
+ (match (string_drop _s2501_ _s2502_) with
+ | _s2503_ =>
+ (reg_name_matches_prefix _s2503_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2504_ _)) =>
+ let p0_ :=
+ string_drop _s2503_
+ _s2504_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2468_ (_s2469_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2470_ := _s2469_ in
+ (if ((string_startswith _s2470_ "div")) then
+ (match (string_drop _s2470_ (projT1 (string_length "div"))) with
+ | _s2471_ =>
+ (maybe_not_u_matches_prefix _s2471_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2472_ _)) =>
+ let _s2473_ := string_drop _s2471_ _s2472_ in
+ (if ((string_startswith _s2473_ "w")) then
+ (match (string_drop _s2473_ (projT1 (string_length "w"))) with
+ | _s2474_ =>
+ (spc_matches_prefix _s2474_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2475_ _)) =>
+ (match (string_drop _s2474_ _s2475_) with
+ | _s2476_ =>
+ (reg_name_matches_prefix _s2476_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2477_ _)) =>
+ (match (string_drop _s2476_ _s2477_) with
+ | _s2478_ =>
+ (sep_matches_prefix _s2478_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2479_ _)) =>
+ (match (string_drop _s2478_ _s2479_) with
+ | _s2480_ =>
+ (reg_name_matches_prefix _s2480_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2481_ _)) =>
+ (match (string_drop _s2480_ _s2481_) with
+ | _s2482_ =>
+ (sep_matches_prefix _s2482_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2483_ _)) =>
+ (match (string_drop _s2482_ _s2483_) with
+ | _s2484_ =>
+ (reg_name_matches_prefix _s2484_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2485_ _)) =>
+ let p0_ :=
+ string_drop _s2484_
+ _s2485_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2452_ (_s2453_ : string)
+: M (option ((mword 5 * mword 5 * mword 5))) :=
+
+ let _s2454_ := _s2453_ in
+ (if ((string_startswith _s2454_ "mulw")) then
+ (match (string_drop _s2454_ (projT1 (string_length "mulw"))) with
+ | _s2455_ =>
+ (spc_matches_prefix _s2455_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2456_ _)) =>
+ (match (string_drop _s2455_ _s2456_) with
+ | _s2457_ =>
+ (reg_name_matches_prefix _s2457_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2458_ _)) =>
+ (match (string_drop _s2457_ _s2458_) with
+ | _s2459_ =>
+ (sep_matches_prefix _s2459_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2460_ _)) =>
+ (match (string_drop _s2459_ _s2460_) with
+ | _s2461_ =>
+ (reg_name_matches_prefix _s2461_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2462_ _)) =>
+ (match (string_drop _s2461_ _s2462_) with
+ | _s2463_ =>
+ (sep_matches_prefix _s2463_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2464_ _)) =>
+ (match (string_drop _s2463_ _s2464_) with
+ | _s2465_ =>
+ (reg_name_matches_prefix _s2465_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s2466_ _)) =>
+ let p0_ :=
+ string_drop _s2465_ _s2466_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5 * mword 5))).
+
+Definition _s2434_ (_s2435_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2436_ := _s2435_ in
+ (if ((string_startswith _s2436_ "rem")) then
+ (match (string_drop _s2436_ (projT1 (string_length "rem"))) with
+ | _s2437_ =>
+ (maybe_not_u_matches_prefix _s2437_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2438_ _)) =>
+ (match (string_drop _s2437_ _s2438_) with
+ | _s2439_ =>
+ (spc_matches_prefix _s2439_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2440_ _)) =>
+ (match (string_drop _s2439_ _s2440_) with
+ | _s2441_ =>
+ (reg_name_matches_prefix _s2441_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2442_ _)) =>
+ (match (string_drop _s2441_ _s2442_) with
+ | _s2443_ =>
+ (sep_matches_prefix _s2443_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2444_ _)) =>
+ (match (string_drop _s2443_ _s2444_) with
+ | _s2445_ =>
+ (reg_name_matches_prefix _s2445_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2446_ _)) =>
+ (match (string_drop _s2445_ _s2446_) with
+ | _s2447_ =>
+ (sep_matches_prefix _s2447_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2448_ _)) =>
+ (match (string_drop _s2447_ _s2448_) with
+ | _s2449_ =>
+ (reg_name_matches_prefix _s2449_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2450_ _)) =>
+ let p0_ :=
+ string_drop _s2449_ _s2450_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2416_ (_s2417_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2418_ := _s2417_ in
+ (if ((string_startswith _s2418_ "div")) then
+ (match (string_drop _s2418_ (projT1 (string_length "div"))) with
+ | _s2419_ =>
+ (maybe_not_u_matches_prefix _s2419_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2420_ _)) =>
+ (match (string_drop _s2419_ _s2420_) with
+ | _s2421_ =>
+ (spc_matches_prefix _s2421_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2422_ _)) =>
+ (match (string_drop _s2421_ _s2422_) with
+ | _s2423_ =>
+ (reg_name_matches_prefix _s2423_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2424_ _)) =>
+ (match (string_drop _s2423_ _s2424_) with
+ | _s2425_ =>
+ (sep_matches_prefix _s2425_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2426_ _)) =>
+ (match (string_drop _s2425_ _s2426_) with
+ | _s2427_ =>
+ (reg_name_matches_prefix _s2427_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2428_ _)) =>
+ (match (string_drop _s2427_ _s2428_) with
+ | _s2429_ =>
+ (sep_matches_prefix _s2429_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2430_ _)) =>
+ (match (string_drop _s2429_ _s2430_) with
+ | _s2431_ =>
+ (reg_name_matches_prefix _s2431_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2432_ _)) =>
+ let p0_ :=
+ string_drop _s2431_ _s2432_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2399_ (_s2400_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s2400_ with
+ | _s2401_ =>
+ (mul_mnemonic_matches_prefix _s2401_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s2402_ _)) =>
+ (match (string_drop _s2401_ _s2402_) with
+ | _s2403_ =>
+ (spc_matches_prefix _s2403_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2404_ _)) =>
+ (match (string_drop _s2403_ _s2404_) with
+ | _s2405_ =>
+ (reg_name_matches_prefix _s2405_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2406_ _)) =>
+ (match (string_drop _s2405_ _s2406_) with
+ | _s2407_ =>
+ (sep_matches_prefix _s2407_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2408_ _)) =>
+ (match (string_drop _s2407_ _s2408_) with
+ | _s2409_ =>
+ (reg_name_matches_prefix _s2409_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2410_ _)) =>
+ (match (string_drop _s2409_ _s2410_) with
+ | _s2411_ =>
+ (sep_matches_prefix _s2411_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2412_ _)) =>
+ (match (string_drop _s2411_ _s2412_) with
+ | _s2413_ =>
+ (reg_name_matches_prefix _s2413_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2414_ _)) =>
+ let p0_ :=
+ string_drop _s2413_ _s2414_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2387_ (_s2388_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s2389_ := _s2388_ in
+ (if ((string_startswith _s2389_ "c.add")) then
+ (match (string_drop _s2389_ (projT1 (string_length "c.add"))) with
+ | _s2390_ =>
+ (spc_matches_prefix _s2390_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2391_ _)) =>
+ (match (string_drop _s2390_ _s2391_) with
+ | _s2392_ =>
+ (reg_name_matches_prefix _s2392_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2393_ _)) =>
+ (match (string_drop _s2392_ _s2393_) with
+ | _s2394_ =>
+ (sep_matches_prefix _s2394_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2395_ _)) =>
+ (match (string_drop _s2394_ _s2395_) with
+ | _s2396_ =>
+ (reg_name_matches_prefix _s2396_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2397_ _)) =>
+ let p0_ := string_drop _s2396_ _s2397_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s2375_ (_s2376_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s2377_ := _s2376_ in
+ (if ((string_startswith _s2377_ "c.mv")) then
+ (match (string_drop _s2377_ (projT1 (string_length "c.mv"))) with
+ | _s2378_ =>
+ (spc_matches_prefix _s2378_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2379_ _)) =>
+ (match (string_drop _s2378_ _s2379_) with
+ | _s2380_ =>
+ (reg_name_matches_prefix _s2380_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2381_ _)) =>
+ (match (string_drop _s2380_ _s2381_) with
+ | _s2382_ =>
+ (sep_matches_prefix _s2382_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2383_ _)) =>
+ (match (string_drop _s2382_ _s2383_) with
+ | _s2384_ =>
+ (reg_name_matches_prefix _s2384_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2385_ _)) =>
+ let p0_ := string_drop _s2384_ _s2385_ in
+ if ((generic_eq p0_ "")) then Some ((rd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s2367_ (_s2368_ : string)
+: M (option (mword 5)) :=
+
+ let _s2369_ := _s2368_ in
+ (if ((string_startswith _s2369_ "c.jalr")) then
+ (match (string_drop _s2369_ (projT1 (string_length "c.jalr"))) with
+ | _s2370_ =>
+ (spc_matches_prefix _s2370_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2371_ _)) =>
+ (match (string_drop _s2370_ _s2371_) with
+ | _s2372_ =>
+ (reg_name_matches_prefix _s2372_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s2373_ _)) =>
+ let p0_ := string_drop _s2372_ _s2373_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s2359_ (_s2360_ : string)
+: M (option (mword 5)) :=
+
+ let _s2361_ := _s2360_ in
+ (if ((string_startswith _s2361_ "c.jr")) then
+ (match (string_drop _s2361_ (projT1 (string_length "c.jr"))) with
+ | _s2362_ =>
+ (spc_matches_prefix _s2362_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2363_ _)) =>
+ (match (string_drop _s2362_ _s2363_) with
+ | _s2364_ =>
+ (reg_name_matches_prefix _s2364_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s2365_ _)) =>
+ let p0_ := string_drop _s2364_ _s2365_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s2347_ (_s2348_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2349_ := _s2348_ in
+ (if ((string_startswith _s2349_ "c.sdsp")) then
+ (match (string_drop _s2349_ (projT1 (string_length "c.sdsp"))) with
+ | _s2350_ =>
+ (spc_matches_prefix _s2350_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2351_ _)) =>
+ (match (string_drop _s2350_ _s2351_) with
+ | _s2352_ =>
+ (reg_name_matches_prefix _s2352_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s2353_ _)) =>
+ (match (string_drop _s2352_ _s2353_) with
+ | _s2354_ =>
+ (sep_matches_prefix _s2354_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2355_ _)) =>
+ match (string_drop _s2354_ _s2355_) with
+ | _s2356_ =>
+ match (hex_bits_6_matches_prefix _s2356_) with
+ | Some ((uimm, existT _ _s2357_ _)) =>
+ let p0_ := string_drop _s2356_ _s2357_ in
+ if ((generic_eq p0_ "")) then Some ((rs2, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2335_ (_s2336_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2337_ := _s2336_ in
+ (if ((string_startswith _s2337_ "c.swsp")) then
+ (match (string_drop _s2337_ (projT1 (string_length "c.swsp"))) with
+ | _s2338_ =>
+ (spc_matches_prefix _s2338_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2339_ _)) =>
+ (match (string_drop _s2338_ _s2339_) with
+ | _s2340_ =>
+ (reg_name_matches_prefix _s2340_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2341_ _)) =>
+ (match (string_drop _s2340_ _s2341_) with
+ | _s2342_ =>
+ (sep_matches_prefix _s2342_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2343_ _)) =>
+ match (string_drop _s2342_ _s2343_) with
+ | _s2344_ =>
+ match (hex_bits_6_matches_prefix _s2344_) with
+ | Some ((uimm, existT _ _s2345_ _)) =>
+ let p0_ := string_drop _s2344_ _s2345_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2323_ (_s2324_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2325_ := _s2324_ in
+ (if ((string_startswith _s2325_ "c.ldsp")) then
+ (match (string_drop _s2325_ (projT1 (string_length "c.ldsp"))) with
+ | _s2326_ =>
+ (spc_matches_prefix _s2326_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2327_ _)) =>
+ (match (string_drop _s2326_ _s2327_) with
+ | _s2328_ =>
+ (reg_name_matches_prefix _s2328_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2329_ _)) =>
+ (match (string_drop _s2328_ _s2329_) with
+ | _s2330_ =>
+ (sep_matches_prefix _s2330_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2331_ _)) =>
+ match (string_drop _s2330_ _s2331_) with
+ | _s2332_ =>
+ match (hex_bits_6_matches_prefix _s2332_) with
+ | Some ((uimm, existT _ _s2333_ _)) =>
+ let p0_ := string_drop _s2332_ _s2333_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2311_ (_s2312_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2313_ := _s2312_ in
+ (if ((string_startswith _s2313_ "c.lwsp")) then
+ (match (string_drop _s2313_ (projT1 (string_length "c.lwsp"))) with
+ | _s2314_ =>
+ (spc_matches_prefix _s2314_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2315_ _)) =>
+ (match (string_drop _s2314_ _s2315_) with
+ | _s2316_ =>
+ (reg_name_matches_prefix _s2316_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2317_ _)) =>
+ (match (string_drop _s2316_ _s2317_) with
+ | _s2318_ =>
+ (sep_matches_prefix _s2318_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2319_ _)) =>
+ match (string_drop _s2318_ _s2319_) with
+ | _s2320_ =>
+ match (hex_bits_6_matches_prefix _s2320_) with
+ | Some ((uimm, existT _ _s2321_ _)) =>
+ let p0_ := string_drop _s2320_ _s2321_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2299_ (_s2300_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2301_ := _s2300_ in
+ (if ((string_startswith _s2301_ "c.slli")) then
+ (match (string_drop _s2301_ (projT1 (string_length "c.slli"))) with
+ | _s2302_ =>
+ (spc_matches_prefix _s2302_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2303_ _)) =>
+ (match (string_drop _s2302_ _s2303_) with
+ | _s2304_ =>
+ (reg_name_matches_prefix _s2304_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2305_ _)) =>
+ (match (string_drop _s2304_ _s2305_) with
+ | _s2306_ =>
+ (sep_matches_prefix _s2306_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2307_ _)) =>
+ match (string_drop _s2306_ _s2307_) with
+ | _s2308_ =>
+ match (hex_bits_6_matches_prefix _s2308_) with
+ | Some ((shamt, existT _ _s2309_ _)) =>
+ let p0_ := string_drop _s2308_ _s2309_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2287_ (_s2288_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2289_ := _s2288_ in
+ (if ((string_startswith _s2289_ "c.bnez")) then
+ (match (string_drop _s2289_ (projT1 (string_length "c.bnez"))) with
+ | _s2290_ =>
+ (spc_matches_prefix _s2290_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2291_ _)) =>
+ (match (string_drop _s2290_ _s2291_) with
+ | _s2292_ =>
+ (creg_name_matches_prefix _s2292_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s2293_ _)) =>
+ (match (string_drop _s2292_ _s2293_) with
+ | _s2294_ =>
+ (sep_matches_prefix _s2294_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2295_ _)) =>
+ match (string_drop _s2294_ _s2295_) with
+ | _s2296_ =>
+ match (hex_bits_8_matches_prefix _s2296_) with
+ | Some ((imm, existT _ _s2297_ _)) =>
+ let p0_ := string_drop _s2296_ _s2297_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s2275_ (_s2276_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2277_ := _s2276_ in
+ (if ((string_startswith _s2277_ "c.beqz")) then
+ (match (string_drop _s2277_ (projT1 (string_length "c.beqz"))) with
+ | _s2278_ =>
+ (spc_matches_prefix _s2278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2279_ _)) =>
+ (match (string_drop _s2278_ _s2279_) with
+ | _s2280_ =>
+ (creg_name_matches_prefix _s2280_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s2281_ _)) =>
+ (match (string_drop _s2280_ _s2281_) with
+ | _s2282_ =>
+ (sep_matches_prefix _s2282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2283_ _)) =>
+ match (string_drop _s2282_ _s2283_) with
+ | _s2284_ =>
+ match (hex_bits_8_matches_prefix _s2284_) with
+ | Some ((imm, existT _ _s2285_ _)) =>
+ let p0_ := string_drop _s2284_ _s2285_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s2267_ (_s2268_ : string)
+: M (option (mword 11)) :=
+
+ let _s2269_ := _s2268_ in
+ (if ((string_startswith _s2269_ "c.j")) then
+ (match (string_drop _s2269_ (projT1 (string_length "c.j"))) with
+ | _s2270_ =>
+ (spc_matches_prefix _s2270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2271_ _)) =>
+ match (string_drop _s2270_ _s2271_) with
+ | _s2272_ =>
+ match (hex_bits_11_matches_prefix _s2272_) with
+ | Some ((imm, existT _ _s2273_ _)) =>
+ let p0_ := string_drop _s2272_ _s2273_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s2255_ (_s2256_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2257_ := _s2256_ in
+ (if ((string_startswith _s2257_ "c.addw")) then
+ (match (string_drop _s2257_ (projT1 (string_length "c.addw"))) with
+ | _s2258_ =>
+ (spc_matches_prefix _s2258_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2259_ _)) =>
+ (match (string_drop _s2258_ _s2259_) with
+ | _s2260_ =>
+ (creg_name_matches_prefix _s2260_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2261_ _)) =>
+ (match (string_drop _s2260_ _s2261_) with
+ | _s2262_ =>
+ (sep_matches_prefix _s2262_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2263_ _)) =>
+ (match (string_drop _s2262_ _s2263_) with
+ | _s2264_ =>
+ (creg_name_matches_prefix _s2264_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2265_ _)) =>
+ let p0_ := string_drop _s2264_ _s2265_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2243_ (_s2244_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2245_ := _s2244_ in
+ (if ((string_startswith _s2245_ "c.subw")) then
+ (match (string_drop _s2245_ (projT1 (string_length "c.subw"))) with
+ | _s2246_ =>
+ (spc_matches_prefix _s2246_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2247_ _)) =>
+ (match (string_drop _s2246_ _s2247_) with
+ | _s2248_ =>
+ (creg_name_matches_prefix _s2248_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2249_ _)) =>
+ (match (string_drop _s2248_ _s2249_) with
+ | _s2250_ =>
+ (sep_matches_prefix _s2250_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2251_ _)) =>
+ (match (string_drop _s2250_ _s2251_) with
+ | _s2252_ =>
+ (creg_name_matches_prefix _s2252_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2253_ _)) =>
+ let p0_ := string_drop _s2252_ _s2253_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2231_ (_s2232_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2233_ := _s2232_ in
+ (if ((string_startswith _s2233_ "c.and")) then
+ (match (string_drop _s2233_ (projT1 (string_length "c.and"))) with
+ | _s2234_ =>
+ (spc_matches_prefix _s2234_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2235_ _)) =>
+ (match (string_drop _s2234_ _s2235_) with
+ | _s2236_ =>
+ (creg_name_matches_prefix _s2236_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2237_ _)) =>
+ (match (string_drop _s2236_ _s2237_) with
+ | _s2238_ =>
+ (sep_matches_prefix _s2238_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2239_ _)) =>
+ (match (string_drop _s2238_ _s2239_) with
+ | _s2240_ =>
+ (creg_name_matches_prefix _s2240_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2241_ _)) =>
+ let p0_ := string_drop _s2240_ _s2241_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2219_ (_s2220_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2221_ := _s2220_ in
+ (if ((string_startswith _s2221_ "c.or")) then
+ (match (string_drop _s2221_ (projT1 (string_length "c.or"))) with
+ | _s2222_ =>
+ (spc_matches_prefix _s2222_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2223_ _)) =>
+ (match (string_drop _s2222_ _s2223_) with
+ | _s2224_ =>
+ (creg_name_matches_prefix _s2224_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2225_ _)) =>
+ (match (string_drop _s2224_ _s2225_) with
+ | _s2226_ =>
+ (sep_matches_prefix _s2226_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2227_ _)) =>
+ (match (string_drop _s2226_ _s2227_) with
+ | _s2228_ =>
+ (creg_name_matches_prefix _s2228_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2229_ _)) =>
+ let p0_ := string_drop _s2228_ _s2229_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2207_ (_s2208_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2209_ := _s2208_ in
+ (if ((string_startswith _s2209_ "c.xor")) then
+ (match (string_drop _s2209_ (projT1 (string_length "c.xor"))) with
+ | _s2210_ =>
+ (spc_matches_prefix _s2210_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2211_ _)) =>
+ (match (string_drop _s2210_ _s2211_) with
+ | _s2212_ =>
+ (creg_name_matches_prefix _s2212_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2213_ _)) =>
+ (match (string_drop _s2212_ _s2213_) with
+ | _s2214_ =>
+ (sep_matches_prefix _s2214_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2215_ _)) =>
+ (match (string_drop _s2214_ _s2215_) with
+ | _s2216_ =>
+ (creg_name_matches_prefix _s2216_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2217_ _)) =>
+ let p0_ := string_drop _s2216_ _s2217_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2195_ (_s2196_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2197_ := _s2196_ in
+ (if ((string_startswith _s2197_ "c.sub")) then
+ (match (string_drop _s2197_ (projT1 (string_length "c.sub"))) with
+ | _s2198_ =>
+ (spc_matches_prefix _s2198_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2199_ _)) =>
+ (match (string_drop _s2198_ _s2199_) with
+ | _s2200_ =>
+ (creg_name_matches_prefix _s2200_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2201_ _)) =>
+ (match (string_drop _s2200_ _s2201_) with
+ | _s2202_ =>
+ (sep_matches_prefix _s2202_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2203_ _)) =>
+ (match (string_drop _s2202_ _s2203_) with
+ | _s2204_ =>
+ (creg_name_matches_prefix _s2204_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2205_ _)) =>
+ let p0_ := string_drop _s2204_ _s2205_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2183_ (_s2184_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2185_ := _s2184_ in
+ (if ((string_startswith _s2185_ "c.andi")) then
+ (match (string_drop _s2185_ (projT1 (string_length "c.andi"))) with
+ | _s2186_ =>
+ (spc_matches_prefix _s2186_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2187_ _)) =>
+ (match (string_drop _s2186_ _s2187_) with
+ | _s2188_ =>
+ (creg_name_matches_prefix _s2188_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2189_ _)) =>
+ (match (string_drop _s2188_ _s2189_) with
+ | _s2190_ =>
+ (sep_matches_prefix _s2190_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2191_ _)) =>
+ match (string_drop _s2190_ _s2191_) with
+ | _s2192_ =>
+ match (hex_bits_6_matches_prefix _s2192_) with
+ | Some ((imm, existT _ _s2193_ _)) =>
+ let p0_ := string_drop _s2192_ _s2193_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2171_ (_s2172_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2173_ := _s2172_ in
+ (if ((string_startswith _s2173_ "c.srai")) then
+ (match (string_drop _s2173_ (projT1 (string_length "c.srai"))) with
+ | _s2174_ =>
+ (spc_matches_prefix _s2174_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2175_ _)) =>
+ (match (string_drop _s2174_ _s2175_) with
+ | _s2176_ =>
+ (creg_name_matches_prefix _s2176_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2177_ _)) =>
+ (match (string_drop _s2176_ _s2177_) with
+ | _s2178_ =>
+ (sep_matches_prefix _s2178_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2179_ _)) =>
+ match (string_drop _s2178_ _s2179_) with
+ | _s2180_ =>
+ match (hex_bits_6_matches_prefix _s2180_) with
+ | Some ((shamt, existT _ _s2181_ _)) =>
+ let p0_ := string_drop _s2180_ _s2181_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2159_ (_s2160_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2161_ := _s2160_ in
+ (if ((string_startswith _s2161_ "c.srli")) then
+ (match (string_drop _s2161_ (projT1 (string_length "c.srli"))) with
+ | _s2162_ =>
+ (spc_matches_prefix _s2162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2163_ _)) =>
+ (match (string_drop _s2162_ _s2163_) with
+ | _s2164_ =>
+ (creg_name_matches_prefix _s2164_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2165_ _)) =>
+ (match (string_drop _s2164_ _s2165_) with
+ | _s2166_ =>
+ (sep_matches_prefix _s2166_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2167_ _)) =>
+ match (string_drop _s2166_ _s2167_) with
+ | _s2168_ =>
+ match (hex_bits_6_matches_prefix _s2168_) with
+ | Some ((shamt, existT _ _s2169_ _)) =>
+ let p0_ := string_drop _s2168_ _s2169_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2147_ (_s2148_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2149_ := _s2148_ in
+ (if ((string_startswith _s2149_ "c.lui")) then
+ (match (string_drop _s2149_ (projT1 (string_length "c.lui"))) with
+ | _s2150_ =>
+ (spc_matches_prefix _s2150_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2151_ _)) =>
+ (match (string_drop _s2150_ _s2151_) with
+ | _s2152_ =>
+ (reg_name_matches_prefix _s2152_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2153_ _)) =>
+ (match (string_drop _s2152_ _s2153_) with
+ | _s2154_ =>
+ (sep_matches_prefix _s2154_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2155_ _)) =>
+ match (string_drop _s2154_ _s2155_) with
+ | _s2156_ =>
+ match (hex_bits_6_matches_prefix _s2156_) with
+ | Some ((imm, existT _ _s2157_ _)) =>
+ let p0_ := string_drop _s2156_ _s2157_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2139_ (_s2140_ : string)
+: M (option (mword 6)) :=
+
+ let _s2141_ := _s2140_ in
+ (if ((string_startswith _s2141_ "c.addi16sp")) then
+ (match (string_drop _s2141_ (projT1 (string_length "c.addi16sp"))) with
+ | _s2142_ =>
+ (spc_matches_prefix _s2142_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2143_ _)) =>
+ match (string_drop _s2142_ _s2143_) with
+ | _s2144_ =>
+ match (hex_bits_6_matches_prefix _s2144_) with
+ | Some ((imm, existT _ _s2145_ _)) =>
+ let p0_ := string_drop _s2144_ _s2145_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 6))
+ end)
+ : M (option (mword 6))
+ else returnm (None : option (mword 6)))
+ : M (option (mword 6)).
+
+Definition _s2127_ (_s2128_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2129_ := _s2128_ in
+ (if ((string_startswith _s2129_ "c.li")) then
+ (match (string_drop _s2129_ (projT1 (string_length "c.li"))) with
+ | _s2130_ =>
+ (spc_matches_prefix _s2130_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2131_ _)) =>
+ (match (string_drop _s2130_ _s2131_) with
+ | _s2132_ =>
+ (reg_name_matches_prefix _s2132_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2133_ _)) =>
+ (match (string_drop _s2132_ _s2133_) with
+ | _s2134_ =>
+ (sep_matches_prefix _s2134_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2135_ _)) =>
+ match (string_drop _s2134_ _s2135_) with
+ | _s2136_ =>
+ match (hex_bits_6_matches_prefix _s2136_) with
+ | Some ((imm, existT _ _s2137_ _)) =>
+ let p0_ := string_drop _s2136_ _s2137_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2115_ (_s2116_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2117_ := _s2116_ in
+ (if ((string_startswith _s2117_ "c.addiw")) then
+ (match (string_drop _s2117_ (projT1 (string_length "c.addiw"))) with
+ | _s2118_ =>
+ (spc_matches_prefix _s2118_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2119_ _)) =>
+ (match (string_drop _s2118_ _s2119_) with
+ | _s2120_ =>
+ (reg_name_matches_prefix _s2120_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2121_ _)) =>
+ (match (string_drop _s2120_ _s2121_) with
+ | _s2122_ =>
+ (sep_matches_prefix _s2122_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2123_ _)) =>
+ match (string_drop _s2122_ _s2123_) with
+ | _s2124_ =>
+ match (hex_bits_6_matches_prefix _s2124_) with
+ | Some ((imm, existT _ _s2125_ _)) =>
+ let p0_ := string_drop _s2124_ _s2125_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2107_ (_s2108_ : string)
+: M (option (mword 11)) :=
+
+ let _s2109_ := _s2108_ in
+ (if ((string_startswith _s2109_ "c.jal")) then
+ (match (string_drop _s2109_ (projT1 (string_length "c.jal"))) with
+ | _s2110_ =>
+ (spc_matches_prefix _s2110_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2111_ _)) =>
+ match (string_drop _s2110_ _s2111_) with
+ | _s2112_ =>
+ match (hex_bits_12_matches_prefix _s2112_) with
+ | Some ((v__814, existT _ _s2113_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__814 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__814 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__814 11 1 in
+ let p0_ := string_drop _s2112_ _s2113_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s2095_ (_s2096_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2097_ := _s2096_ in
+ (if ((string_startswith _s2097_ "c.addi")) then
+ (match (string_drop _s2097_ (projT1 (string_length "c.addi"))) with
+ | _s2098_ =>
+ (spc_matches_prefix _s2098_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2099_ _)) =>
+ (match (string_drop _s2098_ _s2099_) with
+ | _s2100_ =>
+ (reg_name_matches_prefix _s2100_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2101_ _)) =>
+ (match (string_drop _s2100_ _s2101_) with
+ | _s2102_ =>
+ (sep_matches_prefix _s2102_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2103_ _)) =>
+ match (string_drop _s2102_ _s2103_) with
+ | _s2104_ =>
+ match (hex_bits_6_matches_prefix _s2104_) with
+ | Some ((nzi, existT _ _s2105_ _)) =>
+ let p0_ := string_drop _s2104_ _s2105_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, nzi))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2079_ (_s2080_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2081_ := _s2080_ in
+ (if ((string_startswith _s2081_ "c.sd")) then
+ (match (string_drop _s2081_ (projT1 (string_length "c.sd"))) with
+ | _s2082_ =>
+ (spc_matches_prefix _s2082_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2083_ _)) =>
+ (match (string_drop _s2082_ _s2083_) with
+ | _s2084_ =>
+ (creg_name_matches_prefix _s2084_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2085_ _)) =>
+ (match (string_drop _s2084_ _s2085_) with
+ | _s2086_ =>
+ (sep_matches_prefix _s2086_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2087_ _)) =>
+ (match (string_drop _s2086_ _s2087_) with
+ | _s2088_ =>
+ (creg_name_matches_prefix _s2088_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2089_ _)) =>
+ (match (string_drop _s2088_ _s2089_) with
+ | _s2090_ =>
+ (sep_matches_prefix _s2090_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2091_ _)) =>
+ match (string_drop _s2090_ _s2091_) with
+ | _s2092_ =>
+ match (hex_bits_8_matches_prefix _s2092_) with
+ | Some ((v__816, existT _ _s2093_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__816 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__816 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__816 7 3 in
+ let p0_ :=
+ string_drop _s2092_ _s2093_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2063_ (_s2064_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2065_ := _s2064_ in
+ (if ((string_startswith _s2065_ "c.sw")) then
+ (match (string_drop _s2065_ (projT1 (string_length "c.sw"))) with
+ | _s2066_ =>
+ (spc_matches_prefix _s2066_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2067_ _)) =>
+ (match (string_drop _s2066_ _s2067_) with
+ | _s2068_ =>
+ (creg_name_matches_prefix _s2068_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2069_ _)) =>
+ (match (string_drop _s2068_ _s2069_) with
+ | _s2070_ =>
+ (sep_matches_prefix _s2070_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2071_ _)) =>
+ (match (string_drop _s2070_ _s2071_) with
+ | _s2072_ =>
+ (creg_name_matches_prefix _s2072_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2073_ _)) =>
+ (match (string_drop _s2072_ _s2073_) with
+ | _s2074_ =>
+ (sep_matches_prefix _s2074_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2075_ _)) =>
+ match (string_drop _s2074_ _s2075_) with
+ | _s2076_ =>
+ match (hex_bits_7_matches_prefix _s2076_) with
+ | Some ((v__818, existT _ _s2077_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__818 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__818 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__818 6 2 in
+ let p0_ :=
+ string_drop _s2076_ _s2077_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2047_ (_s2048_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2049_ := _s2048_ in
+ (if ((string_startswith _s2049_ "c.ld")) then
+ (match (string_drop _s2049_ (projT1 (string_length "c.ld"))) with
+ | _s2050_ =>
+ (spc_matches_prefix _s2050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2051_ _)) =>
+ (match (string_drop _s2050_ _s2051_) with
+ | _s2052_ =>
+ (creg_name_matches_prefix _s2052_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2053_ _)) =>
+ (match (string_drop _s2052_ _s2053_) with
+ | _s2054_ =>
+ (sep_matches_prefix _s2054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2055_ _)) =>
+ (match (string_drop _s2054_ _s2055_) with
+ | _s2056_ =>
+ (creg_name_matches_prefix _s2056_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2057_ _)) =>
+ (match (string_drop _s2056_ _s2057_) with
+ | _s2058_ =>
+ (sep_matches_prefix _s2058_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2059_ _)) =>
+ match (string_drop _s2058_ _s2059_) with
+ | _s2060_ =>
+ match (hex_bits_8_matches_prefix _s2060_) with
+ | Some ((v__820, existT _ _s2061_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__820 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__820 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__820 7 3 in
+ let p0_ :=
+ string_drop _s2060_ _s2061_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2031_ (_s2032_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2033_ := _s2032_ in
+ (if ((string_startswith _s2033_ "c.lw")) then
+ (match (string_drop _s2033_ (projT1 (string_length "c.lw"))) with
+ | _s2034_ =>
+ (spc_matches_prefix _s2034_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2035_ _)) =>
+ (match (string_drop _s2034_ _s2035_) with
+ | _s2036_ =>
+ (creg_name_matches_prefix _s2036_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2037_ _)) =>
+ (match (string_drop _s2036_ _s2037_) with
+ | _s2038_ =>
+ (sep_matches_prefix _s2038_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2039_ _)) =>
+ (match (string_drop _s2038_ _s2039_) with
+ | _s2040_ =>
+ (creg_name_matches_prefix _s2040_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2041_ _)) =>
+ (match (string_drop _s2040_ _s2041_) with
+ | _s2042_ =>
+ (sep_matches_prefix _s2042_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2043_ _)) =>
+ match (string_drop _s2042_ _s2043_) with
+ | _s2044_ =>
+ match (hex_bits_7_matches_prefix _s2044_) with
+ | Some ((v__822, existT _ _s2045_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__822 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__822 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__822 6 2 in
+ let p0_ :=
+ string_drop _s2044_ _s2045_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2019_ (_s2020_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2021_ := _s2020_ in
+ (if ((string_startswith _s2021_ "c.addi4spn")) then
+ (match (string_drop _s2021_ (projT1 (string_length "c.addi4spn"))) with
+ | _s2022_ =>
+ (spc_matches_prefix _s2022_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2023_ _)) =>
+ (match (string_drop _s2022_ _s2023_) with
+ | _s2024_ =>
+ (creg_name_matches_prefix _s2024_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2025_ _)) =>
+ (match (string_drop _s2024_ _s2025_) with
+ | _s2026_ =>
+ (sep_matches_prefix _s2026_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2027_ _)) =>
+ match (string_drop _s2026_ _s2027_) with
+ | _s2028_ =>
+ match (hex_bits_10_matches_prefix _s2028_) with
+ | Some ((v__824, existT _ _s2029_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__824 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__824 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__824 9 2 in
+ let p0_ := string_drop _s2028_ _s2029_ in
+ if ((generic_eq p0_ "")) then Some ((rdc, nzimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1995_ (_s1996_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1996_ with
+ | _s1997_ =>
+ (amo_mnemonic_matches_prefix _s1997_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1998_ _)) =>
+ let _s1999_ := string_drop _s1997_ _s1998_ in
+ (if ((string_startswith _s1999_ ".")) then
+ (match (string_drop _s1999_ (projT1 (string_length "."))) with
+ | _s2000_ =>
+ (size_mnemonic_matches_prefix _s2000_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s2001_ _)) =>
+ (match (string_drop _s2000_ _s2001_) with
+ | _s2002_ =>
+ (maybe_aq_matches_prefix _s2002_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2003_ _)) =>
+ (match (string_drop _s2002_ _s2003_) with
+ | _s2004_ =>
+ (maybe_rl_matches_prefix _s2004_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2005_ _)) =>
+ (match (string_drop _s2004_ _s2005_) with
+ | _s2006_ =>
+ (spc_matches_prefix _s2006_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2007_ _)) =>
+ (match (string_drop _s2006_ _s2007_) with
+ | _s2008_ =>
+ (reg_name_matches_prefix _s2008_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2009_ _)) =>
+ (match (string_drop _s2008_ _s2009_) with
+ | _s2010_ =>
+ (sep_matches_prefix _s2010_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2011_ _)) =>
+ (match (string_drop _s2010_ _s2011_) with
+ | _s2012_ =>
+ (reg_name_matches_prefix _s2012_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s2013_ _)) =>
+ (match (string_drop _s2012_
+ _s2013_) with
+ | _s2014_ =>
+ (sep_matches_prefix
+ _s2014_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2015_ _)) =>
+ (match (string_drop
+ _s2014_
+ _s2015_) with
+ | _s2016_ =>
+ (reg_name_matches_prefix
+ _s2016_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s2017_ _)) =>
+ let p0_ :=
+ string_drop
+ _s2016_
+ _s2017_ in
+ if ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2))
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1973_ (_s1974_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1975_ := _s1974_ in
+ (if ((string_startswith _s1975_ "sc.")) then
+ (match (string_drop _s1975_ (projT1 (string_length "sc."))) with
+ | _s1976_ =>
+ (size_mnemonic_matches_prefix _s1976_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1977_ _)) =>
+ (match (string_drop _s1976_ _s1977_) with
+ | _s1978_ =>
+ (maybe_aq_matches_prefix _s1978_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1979_ _)) =>
+ (match (string_drop _s1978_ _s1979_) with
+ | _s1980_ =>
+ (maybe_rl_matches_prefix _s1980_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1981_ _)) =>
+ (match (string_drop _s1980_ _s1981_) with
+ | _s1982_ =>
+ (spc_matches_prefix _s1982_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1983_ _)) =>
+ (match (string_drop _s1982_ _s1983_) with
+ | _s1984_ =>
+ (reg_name_matches_prefix _s1984_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1985_ _)) =>
+ (match (string_drop _s1984_ _s1985_) with
+ | _s1986_ =>
+ (sep_matches_prefix _s1986_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1987_ _)) =>
+ (match (string_drop _s1986_ _s1987_) with
+ | _s1988_ =>
+ (reg_name_matches_prefix _s1988_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s1989_ _)) =>
+ (match (string_drop _s1988_ _s1989_) with
+ | _s1990_ =>
+ (sep_matches_prefix _s1990_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s1991_ _)) =>
+ (match (string_drop _s1990_
+ _s1991_) with
+ | _s1992_ =>
+ (reg_name_matches_prefix
+ _s1992_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s1993_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1992_
+ _s1993_ in
+ if ((generic_eq
+ p0_ ""))
+ then
+ Some
+ ((size, aq, rl, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1955_ (_s1956_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5))) :=
+
+ let _s1957_ := _s1956_ in
+ (if ((string_startswith _s1957_ "lr.")) then
+ (match (string_drop _s1957_ (projT1 (string_length "lr."))) with
+ | _s1958_ =>
+ (size_mnemonic_matches_prefix _s1958_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1959_ _)) =>
+ (match (string_drop _s1958_ _s1959_) with
+ | _s1960_ =>
+ (maybe_aq_matches_prefix _s1960_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1961_ _)) =>
+ (match (string_drop _s1960_ _s1961_) with
+ | _s1962_ =>
+ (maybe_rl_matches_prefix _s1962_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1963_ _)) =>
+ (match (string_drop _s1962_ _s1963_) with
+ | _s1964_ =>
+ (spc_matches_prefix _s1964_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1965_ _)) =>
+ (match (string_drop _s1964_ _s1965_) with
+ | _s1966_ =>
+ (reg_name_matches_prefix _s1966_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1967_ _)) =>
+ (match (string_drop _s1966_ _s1967_) with
+ | _s1968_ =>
+ (sep_matches_prefix _s1968_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1969_ _)) =>
+ (match (string_drop _s1968_ _s1969_) with
+ | _s1970_ =>
+ (reg_name_matches_prefix _s1970_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s1971_ _)) =>
+ let p0_ :=
+ string_drop _s1970_ _s1971_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((size, aq, rl, rd, rs1))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5))).
+
+Definition _s1943_ (_s1944_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1945_ := _s1944_ in
+ (if ((string_startswith _s1945_ "sfence.vma")) then
+ (match (string_drop _s1945_ (projT1 (string_length "sfence.vma"))) with
+ | _s1946_ =>
+ (spc_matches_prefix _s1946_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1947_ _)) =>
+ (match (string_drop _s1946_ _s1947_) with
+ | _s1948_ =>
+ (reg_name_matches_prefix _s1948_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s1949_ _)) =>
+ (match (string_drop _s1948_ _s1949_) with
+ | _s1950_ =>
+ (sep_matches_prefix _s1950_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1951_ _)) =>
+ (match (string_drop _s1950_ _s1951_) with
+ | _s1952_ =>
+ (reg_name_matches_prefix _s1952_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1953_ _)) =>
+ let p0_ := string_drop _s1952_ _s1953_ in
+ if ((generic_eq p0_ "")) then Some ((rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1931_ (_s1932_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1933_ := _s1932_ in
+ (if ((string_startswith _s1933_ "fence.tso")) then
+ (match (string_drop _s1933_ (projT1 (string_length "fence.tso"))) with
+ | _s1934_ =>
+ (spc_matches_prefix _s1934_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1935_ _)) =>
+ (match (string_drop _s1934_ _s1935_) with
+ | _s1936_ =>
+ (fence_bits_matches_prefix _s1936_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1937_ _)) =>
+ (match (string_drop _s1936_ _s1937_) with
+ | _s1938_ =>
+ (sep_matches_prefix _s1938_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1939_ _)) =>
+ (match (string_drop _s1938_ _s1939_) with
+ | _s1940_ =>
+ (fence_bits_matches_prefix _s1940_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1941_ _)) =>
+ let p0_ := string_drop _s1940_ _s1941_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1919_ (_s1920_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1921_ := _s1920_ in
+ (if ((string_startswith _s1921_ "fence")) then
+ (match (string_drop _s1921_ (projT1 (string_length "fence"))) with
+ | _s1922_ =>
+ (spc_matches_prefix _s1922_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1923_ _)) =>
+ (match (string_drop _s1922_ _s1923_) with
+ | _s1924_ =>
+ (fence_bits_matches_prefix _s1924_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1925_ _)) =>
+ (match (string_drop _s1924_ _s1925_) with
+ | _s1926_ =>
+ (sep_matches_prefix _s1926_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1927_ _)) =>
+ (match (string_drop _s1926_ _s1927_) with
+ | _s1928_ =>
+ (fence_bits_matches_prefix _s1928_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1929_ _)) =>
+ let p0_ := string_drop _s1928_ _s1929_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1902_ (_s1903_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1903_ with
+ | _s1904_ =>
+ (shiftiwop_mnemonic_matches_prefix _s1904_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1905_ _)) =>
+ (match (string_drop _s1904_ _s1905_) with
+ | _s1906_ =>
+ (spc_matches_prefix _s1906_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1907_ _)) =>
+ (match (string_drop _s1906_ _s1907_) with
+ | _s1908_ =>
+ (reg_name_matches_prefix _s1908_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1909_ _)) =>
+ (match (string_drop _s1908_ _s1909_) with
+ | _s1910_ =>
+ (sep_matches_prefix _s1910_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1911_ _)) =>
+ (match (string_drop _s1910_ _s1911_) with
+ | _s1912_ =>
+ (reg_name_matches_prefix _s1912_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1913_ _)) =>
+ (match (string_drop _s1912_ _s1913_) with
+ | _s1914_ =>
+ (sep_matches_prefix _s1914_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1915_ _)) =>
+ match (string_drop _s1914_ _s1915_) with
+ | _s1916_ =>
+ match (hex_bits_5_matches_prefix
+ _s1916_) with
+ | Some ((shamt, existT _ _s1917_ _)) =>
+ let p0_ :=
+ string_drop _s1916_ _s1917_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1885_ (_s1886_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1886_ with
+ | _s1887_ =>
+ (rtypew_mnemonic_matches_prefix _s1887_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1888_ _)) =>
+ (match (string_drop _s1887_ _s1888_) with
+ | _s1889_ =>
+ (spc_matches_prefix _s1889_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1890_ _)) =>
+ (match (string_drop _s1889_ _s1890_) with
+ | _s1891_ =>
+ (reg_name_matches_prefix _s1891_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1892_ _)) =>
+ (match (string_drop _s1891_ _s1892_) with
+ | _s1893_ =>
+ (sep_matches_prefix _s1893_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1894_ _)) =>
+ (match (string_drop _s1893_ _s1894_) with
+ | _s1895_ =>
+ (reg_name_matches_prefix _s1895_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1896_ _)) =>
+ (match (string_drop _s1895_ _s1896_) with
+ | _s1897_ =>
+ (sep_matches_prefix _s1897_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1898_ _)) =>
+ (match (string_drop _s1897_ _s1898_) with
+ | _s1899_ =>
+ (reg_name_matches_prefix _s1899_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1900_ _)) =>
+ let p0_ :=
+ string_drop _s1899_ _s1900_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1868_ (_s1869_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1869_ with
+ | _s1870_ =>
+ (shiftw_mnemonic_matches_prefix _s1870_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1871_ _)) =>
+ (match (string_drop _s1870_ _s1871_) with
+ | _s1872_ =>
+ (spc_matches_prefix _s1872_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1873_ _)) =>
+ (match (string_drop _s1872_ _s1873_) with
+ | _s1874_ =>
+ (reg_name_matches_prefix _s1874_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1875_ _)) =>
+ (match (string_drop _s1874_ _s1875_) with
+ | _s1876_ =>
+ (sep_matches_prefix _s1876_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1877_ _)) =>
+ (match (string_drop _s1876_ _s1877_) with
+ | _s1878_ =>
+ (reg_name_matches_prefix _s1878_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1879_ _)) =>
+ (match (string_drop _s1878_ _s1879_) with
+ | _s1880_ =>
+ (sep_matches_prefix _s1880_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1881_ _)) =>
+ match (string_drop _s1880_ _s1881_) with
+ | _s1882_ =>
+ match (hex_bits_5_matches_prefix
+ _s1882_) with
+ | Some ((shamt, existT _ _s1883_ _)) =>
+ let p0_ :=
+ string_drop _s1882_ _s1883_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5))).
+
+Definition _s1852_ (_s1853_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s1854_ := _s1853_ in
+ (if ((string_startswith _s1854_ "addiw")) then
+ (match (string_drop _s1854_ (projT1 (string_length "addiw"))) with
+ | _s1855_ =>
+ (spc_matches_prefix _s1855_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1856_ _)) =>
+ (match (string_drop _s1855_ _s1856_) with
+ | _s1857_ =>
+ (reg_name_matches_prefix _s1857_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1858_ _)) =>
+ (match (string_drop _s1857_ _s1858_) with
+ | _s1859_ =>
+ (sep_matches_prefix _s1859_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1860_ _)) =>
+ (match (string_drop _s1859_ _s1860_) with
+ | _s1861_ =>
+ (reg_name_matches_prefix _s1861_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1862_ _)) =>
+ (match (string_drop _s1861_ _s1862_) with
+ | _s1863_ =>
+ (sep_matches_prefix _s1863_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1864_ _)) =>
+ match (string_drop _s1863_ _s1864_) with
+ | _s1865_ =>
+ match (hex_bits_12_matches_prefix _s1865_) with
+ | Some ((imm, existT _ _s1866_ _)) =>
+ let p0_ := string_drop _s1865_ _s1866_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s1824_ (_s1825_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s1826_ := _s1825_ in
+ (if ((string_startswith _s1826_ "s")) then
+ (match (string_drop _s1826_ (projT1 (string_length "s"))) with
+ | _s1827_ =>
+ (size_mnemonic_matches_prefix _s1827_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1828_ _)) =>
+ (match (string_drop _s1827_ _s1828_) with
+ | _s1829_ =>
+ (maybe_aq_matches_prefix _s1829_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1830_ _)) =>
+ (match (string_drop _s1829_ _s1830_) with
+ | _s1831_ =>
+ (maybe_rl_matches_prefix _s1831_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1832_ _)) =>
+ (match (string_drop _s1831_ _s1832_) with
+ | _s1833_ =>
+ (spc_matches_prefix _s1833_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1834_ _)) =>
+ (match (string_drop _s1833_ _s1834_) with
+ | _s1835_ =>
+ (reg_name_matches_prefix _s1835_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s1836_ _)) =>
+ (match (string_drop _s1835_ _s1836_) with
+ | _s1837_ =>
+ (sep_matches_prefix _s1837_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1838_ _)) =>
+ (match (string_drop _s1837_ _s1838_) with
+ | _s1839_ =>
+ (match (hex_bits_12_matches_prefix _s1839_) with
+ | Some ((imm, existT _ _s1840_ _)) =>
+ (match (string_drop _s1839_ _s1840_) with
+ | _s1841_ =>
+ (opt_spc_matches_prefix _s1841_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1842_ _)) =>
+ let _s1843_ :=
+ string_drop _s1841_ _s1842_ in
+ (if ((string_startswith
+ _s1843_ "(")) then
+ (match (string_drop _s1843_
+ (projT1
+ (string_length
+ "("))) with
+ | _s1844_ =>
+ (opt_spc_matches_prefix
+ _s1844_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s1845_ _)) =>
+ (match (string_drop
+ _s1844_
+ _s1845_) with
+ | _s1846_ =>
+ (reg_name_matches_prefix
+ _s1846_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s1847_ _)) =>
+ (match (string_drop
+ _s1846_
+ _s1847_) with
+ | _s1848_ =>
+ (opt_spc_matches_prefix
+ _s1848_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s1849_ _)) =>
+ let _s1850_ :=
+ string_drop
+ _s1848_
+ _s1849_ in
+ if
+ ((string_startswith
+ _s1850_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s1850_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, aq, rl, rs2, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s1794_ (_s1795_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s1796_ := _s1795_ in
+ (if ((string_startswith _s1796_ "l")) then
+ (match (string_drop _s1796_ (projT1 (string_length "l"))) with
+ | _s1797_ =>
+ (size_mnemonic_matches_prefix _s1797_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1798_ _)) =>
+ (match (string_drop _s1797_ _s1798_) with
+ | _s1799_ =>
+ (maybe_u_matches_prefix _s1799_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s1800_ _)) =>
+ (match (string_drop _s1799_ _s1800_) with
+ | _s1801_ =>
+ (maybe_aq_matches_prefix _s1801_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s1802_ _)) =>
+ (match (string_drop _s1801_ _s1802_) with
+ | _s1803_ =>
+ (maybe_rl_matches_prefix _s1803_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s1804_ _)) =>
+ (match (string_drop _s1803_ _s1804_) with
+ | _s1805_ =>
+ (spc_matches_prefix _s1805_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1806_ _)) =>
+ (match (string_drop _s1805_ _s1806_) with
+ | _s1807_ =>
+ (reg_name_matches_prefix _s1807_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s1808_ _)) =>
+ (match (string_drop _s1807_ _s1808_) with
+ | _s1809_ =>
+ (sep_matches_prefix _s1809_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1810_ _)) =>
+ (match (string_drop _s1809_ _s1810_) with
+ | _s1811_ =>
+ (match (hex_bits_12_matches_prefix
+ _s1811_) with
+ | Some
+ ((imm, existT _ _s1812_ _)) =>
+ (match (string_drop _s1811_
+ _s1812_) with
+ | _s1813_ =>
+ (opt_spc_matches_prefix
+ _s1813_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s1814_ _)) =>
+ let _s1815_ :=
+ string_drop _s1813_
+ _s1814_ in
+ (if ((string_startswith
+ _s1815_ "("))
+ then
+ (match (string_drop
+ _s1815_
+ (projT1
+ (string_length
+ "("))) with
+ | _s1816_ =>
+ (opt_spc_matches_prefix
+ _s1816_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s1817_ _)) =>
+ (match (string_drop
+ _s1816_
+ _s1817_) with
+ | _s1818_ =>
+ (reg_name_matches_prefix
+ _s1818_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s1819_ _)) =>
+ (match (string_drop
+ _s1818_
+ _s1819_) with
+ | _s1820_ =>
+ (opt_spc_matches_prefix
+ _s1820_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s1821_ _)) =>
+ let _s1822_ :=
+ string_drop
+ _s1820_
+ _s1821_ in
+ if
+ ((string_startswith
+ _s1822_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s1822_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s1777_ (_s1778_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1778_ with
+ | _s1779_ =>
+ (rtype_mnemonic_matches_prefix _s1779_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1780_ _)) =>
+ (match (string_drop _s1779_ _s1780_) with
+ | _s1781_ =>
+ (spc_matches_prefix _s1781_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1782_ _)) =>
+ (match (string_drop _s1781_ _s1782_) with
+ | _s1783_ =>
+ (reg_name_matches_prefix _s1783_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1784_ _)) =>
+ (match (string_drop _s1783_ _s1784_) with
+ | _s1785_ =>
+ (sep_matches_prefix _s1785_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1786_ _)) =>
+ (match (string_drop _s1785_ _s1786_) with
+ | _s1787_ =>
+ (reg_name_matches_prefix _s1787_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1788_ _)) =>
+ (match (string_drop _s1787_ _s1788_) with
+ | _s1789_ =>
+ (sep_matches_prefix _s1789_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1790_ _)) =>
+ (match (string_drop _s1789_ _s1790_) with
+ | _s1791_ =>
+ (reg_name_matches_prefix _s1791_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1792_ _)) =>
+ let p0_ :=
+ string_drop _s1791_ _s1792_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5))).
+
+Definition _s1760_ (_s1761_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6))) :=
+
+ (match _s1761_ with
+ | _s1762_ =>
+ (shiftiop_mnemonic_matches_prefix _s1762_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1763_ _)) =>
+ (match (string_drop _s1762_ _s1763_) with
+ | _s1764_ =>
+ (spc_matches_prefix _s1764_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1765_ _)) =>
+ (match (string_drop _s1764_ _s1765_) with
+ | _s1766_ =>
+ (reg_name_matches_prefix _s1766_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1767_ _)) =>
+ (match (string_drop _s1766_ _s1767_) with
+ | _s1768_ =>
+ (sep_matches_prefix _s1768_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1769_ _)) =>
+ (match (string_drop _s1768_ _s1769_) with
+ | _s1770_ =>
+ (reg_name_matches_prefix _s1770_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1771_ _)) =>
+ (match (string_drop _s1770_ _s1771_) with
+ | _s1772_ =>
+ (sep_matches_prefix _s1772_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1773_ _)) =>
+ match (string_drop _s1772_ _s1773_) with
+ | _s1774_ =>
+ match (hex_bits_6_matches_prefix
+ _s1774_) with
+ | Some ((shamt, existT _ _s1775_ _)) =>
+ let p0_ :=
+ string_drop _s1774_ _s1775_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6))).
+
+Definition _s1743_ (_s1744_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1744_ with
+ | _s1745_ =>
+ (itype_mnemonic_matches_prefix _s1745_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1746_ _)) =>
+ (match (string_drop _s1745_ _s1746_) with
+ | _s1747_ =>
+ (spc_matches_prefix _s1747_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1748_ _)) =>
+ (match (string_drop _s1747_ _s1748_) with
+ | _s1749_ =>
+ (reg_name_matches_prefix _s1749_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1750_ _)) =>
+ (match (string_drop _s1749_ _s1750_) with
+ | _s1751_ =>
+ (sep_matches_prefix _s1751_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1752_ _)) =>
+ (match (string_drop _s1751_ _s1752_) with
+ | _s1753_ =>
+ (reg_name_matches_prefix _s1753_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1754_ _)) =>
+ (match (string_drop _s1753_ _s1754_) with
+ | _s1755_ =>
+ (sep_matches_prefix _s1755_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1756_ _)) =>
+ match (string_drop _s1755_ _s1756_) with
+ | _s1757_ =>
+ match (hex_bits_12_matches_prefix
+ _s1757_) with
+ | Some ((imm, existT _ _s1758_ _)) =>
+ let p0_ :=
+ string_drop _s1757_ _s1758_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1726_ (_s1727_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13))) :=
+
+ (match _s1727_ with
+ | _s1728_ =>
+ (btype_mnemonic_matches_prefix _s1728_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1729_ _)) =>
+ (match (string_drop _s1728_ _s1729_) with
+ | _s1730_ =>
+ (spc_matches_prefix _s1730_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1731_ _)) =>
+ (match (string_drop _s1730_ _s1731_) with
+ | _s1732_ =>
+ (reg_name_matches_prefix _s1732_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s1733_ _)) =>
+ (match (string_drop _s1732_ _s1733_) with
+ | _s1734_ =>
+ (sep_matches_prefix _s1734_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1735_ _)) =>
+ (match (string_drop _s1734_ _s1735_) with
+ | _s1736_ =>
+ (reg_name_matches_prefix _s1736_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s1737_ _)) =>
+ (match (string_drop _s1736_ _s1737_) with
+ | _s1738_ =>
+ (sep_matches_prefix _s1738_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1739_ _)) =>
+ match (string_drop _s1738_ _s1739_) with
+ | _s1740_ =>
+ match (hex_bits_13_matches_prefix
+ _s1740_) with
+ | Some ((imm, existT _ _s1741_ _)) =>
+ let p0_ :=
+ string_drop _s1740_ _s1741_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rs1, rs2, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13))).
+
+Definition _s1710_ (_s1711_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s1712_ := _s1711_ in
+ (if ((string_startswith _s1712_ "jalr")) then
+ (match (string_drop _s1712_ (projT1 (string_length "jalr"))) with
+ | _s1713_ =>
+ (spc_matches_prefix _s1713_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1714_ _)) =>
+ (match (string_drop _s1713_ _s1714_) with
+ | _s1715_ =>
+ (reg_name_matches_prefix _s1715_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1716_ _)) =>
+ (match (string_drop _s1715_ _s1716_) with
+ | _s1717_ =>
+ (sep_matches_prefix _s1717_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1718_ _)) =>
+ (match (string_drop _s1717_ _s1718_) with
+ | _s1719_ =>
+ (reg_name_matches_prefix _s1719_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1720_ _)) =>
+ (match (string_drop _s1719_ _s1720_) with
+ | _s1721_ =>
+ (sep_matches_prefix _s1721_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1722_ _)) =>
+ match (string_drop _s1721_ _s1722_) with
+ | _s1723_ =>
+ match (hex_bits_12_matches_prefix _s1723_) with
+ | Some ((imm, existT _ _s1724_ _)) =>
+ let p0_ := string_drop _s1723_ _s1724_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s1698_ (_s1699_ : string)
+: M (option ((mword 5 * mword 21))) :=
+
+ let _s1700_ := _s1699_ in
+ (if ((string_startswith _s1700_ "jal")) then
+ (match (string_drop _s1700_ (projT1 (string_length "jal"))) with
+ | _s1701_ =>
+ (spc_matches_prefix _s1701_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1702_ _)) =>
+ (match (string_drop _s1701_ _s1702_) with
+ | _s1703_ =>
+ (reg_name_matches_prefix _s1703_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1704_ _)) =>
+ (match (string_drop _s1703_ _s1704_) with
+ | _s1705_ =>
+ (sep_matches_prefix _s1705_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1706_ _)) =>
+ match (string_drop _s1705_ _s1706_) with
+ | _s1707_ =>
+ match (hex_bits_21_matches_prefix _s1707_) with
+ | Some ((imm, existT _ _s1708_ _)) =>
+ let p0_ := string_drop _s1707_ _s1708_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ else returnm (None : option ((mword 5 * mword 21))))
+ : M (option ((mword 5 * mword 21))).
+
+Definition _s1685_ (_s1686_ : string)
+: M (option ((uop * mword 5 * mword 20))) :=
+
+ (match _s1686_ with
+ | _s1687_ =>
+ (utype_mnemonic_matches_prefix _s1687_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1688_ _)) =>
+ (match (string_drop _s1687_ _s1688_) with
+ | _s1689_ =>
+ (spc_matches_prefix _s1689_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1690_ _)) =>
+ (match (string_drop _s1689_ _s1690_) with
+ | _s1691_ =>
+ (reg_name_matches_prefix _s1691_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1692_ _)) =>
+ (match (string_drop _s1691_ _s1692_) with
+ | _s1693_ =>
+ (sep_matches_prefix _s1693_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s1694_ _)) =>
+ match (string_drop _s1693_ _s1694_) with
+ | _s1695_ =>
+ match (hex_bits_20_matches_prefix _s1695_) with
+ | Some ((imm, existT _ _s1696_ _)) =>
+ let p0_ := string_drop _s1695_ _s1696_ in
+ if ((generic_eq p0_ "")) then Some ((op, rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20))).
+
+Definition assembly_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s1697_ := arg_ in
+ (_s1685_ _s1697_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) =>
+ (if ((match w__0 with | Some ((op, rd, imm)) => true | _ => false end)) then
+ (_s1685_ _s1697_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) =>
+ (match w__1 with
+ | Some ((op, rd, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1698_ _s1697_) >>= fun w__4 : option ((mword 5 * mword 21)) =>
+ (if ((match w__4 with | Some ((rd, imm)) => true | _ => false end)) then
+ (_s1698_ _s1697_) >>= fun w__5 : option ((mword 5 * mword 21)) =>
+ (match w__5 with
+ | Some ((rd, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1710_ _s1697_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm)) => true | _ => false end)) then
+ (_s1710_ _s1697_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1726_ _s1697_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm)) => true | _ => false end)) then
+ (_s1726_ _s1697_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1743_ _s1697_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm)) => true | _ => false end)) then
+ (_s1743_ _s1697_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1760_ _s1697_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt)) => true | _ => false end))
+ then
+ (_s1760_ _s1697_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1777_ _s1697_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2)) => true | _ => false end))
+ then
+ (_s1777_ _s1697_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1794_ _s1697_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1794_ _s1697_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1824_ _s1697_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1824_ _s1697_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1852_ _s1697_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1852_ _s1697_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1868_ _s1697_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1868_ _s1697_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1885_ _s1697_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1885_ _s1697_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1902_ _s1697_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s1902_ _s1697_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1919_ _s1697_) >>= fun w__52 : option ((mword 4 * mword 4)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1919_ _s1697_) >>= fun w__53 : option ((mword 4 * mword 4)) =>
+ (match w__53 with
+ | Some ((pred, succ)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1931_ _s1697_) >>= fun w__56 : option ((mword 4 * mword 4)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1931_ _s1697_) >>= fun w__57 : option ((mword 4 * mword 4)) =>
+ (match w__57 with
+ | Some ((pred, succ)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else if ((generic_eq _s1697_ "fence.i")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "ecall")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "mret")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "sret")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "ebreak")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "wfi")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (_s1943_ _s1697_) >>= fun w__60 : option ((mword 5 * mword 5)) =>
+ (if ((match w__60 with
+ | Some ((rs1, rs2)) => true
+ | _ => false
+ end)) then
+ (_s1943_ _s1697_) >>= fun w__61 : option ((mword 5 * mword 5)) =>
+ (match w__61 with
+ | Some ((rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1955_ _s1697_) >>= fun w__64 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (if ((match w__64 with
+ | Some ((size, aq, rl, rd, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1955_ _s1697_) >>= fun w__65 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (match w__65 with
+ | Some ((size, aq, rl, rd, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1973_ _s1697_) >>= fun w__68 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__68 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1973_ _s1697_) >>= fun w__69 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__69 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1995_ _s1697_) >>= fun w__72 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__72 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1995_ _s1697_) >>= fun w__73 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__73 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else if ((generic_eq _s1697_ "c.nop"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2019_ _s1697_) >>= fun w__76 : option ((mword 3 * mword 8)) =>
+ (if ((match w__76 with
+ | Some ((rdc, nzimm)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s2019_ _s1697_) >>= fun w__77 : option ((mword 3 * mword 8)) =>
+ (match w__77 with
+ | Some ((rdc, nzimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2031_ _s1697_) >>= fun w__80 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__80 with
+ | Some ((rdc, rsc, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2031_ _s1697_) >>= fun w__81 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__81 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2047_ _s1697_) >>= fun w__84 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__84 with
+ | Some ((rdc, rsc, uimm)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2047_ _s1697_) >>= fun w__85 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__85 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2063_ _s1697_) >>= fun w__88 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__88 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2063_ _s1697_) >>= fun w__89 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__89 with
+ | Some ((rsc1, rsc2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2079_ _s1697_) >>= fun w__92 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__92 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2079_ _s1697_) >>= fun w__93 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__93 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2095_ _s1697_) >>= fun w__96 : option ((mword 5 * mword 6)) =>
+ (if ((match w__96 with
+ | Some ((rsd, nzi)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s2095_ _s1697_) >>= fun w__97 : option ((mword 5 * mword 6)) =>
+ (match w__97 with
+ | Some ((rsd, nzi)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2107_ _s1697_) >>= fun w__100 : option (mword 11) =>
+ (if ((match w__100 with
+ | Some (imm) =>
+ Z.eqb 32 32
+ | _ => false
+ end)) then
+ (_s2107_ _s1697_) >>= fun w__101 : option (mword 11) =>
+ (match w__101 with
+ | Some (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2115_ _s1697_) >>= fun w__104 : option ((mword 5 * mword 6)) =>
+ (if ((match w__104 with
+ | Some
+ ((rsd, imm)) =>
+ Z.eqb 32
+ 64
+ | _ => false
+ end)) then
+ (_s2115_ _s1697_) >>= fun w__105 : option ((mword 5 * mword 6)) =>
+ (match w__105 with
+ | Some
+ ((rsd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2127_ _s1697_) >>= fun w__108 : option ((mword 5 * mword 6)) =>
+ (if ((match w__108 with
+ | Some
+ ((rd, imm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s2127_
+ _s1697_) >>= fun w__109 : option ((mword 5 * mword 6)) =>
+ (match w__109 with
+ | Some
+ ((rd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2139_
+ _s1697_) >>= fun w__112 : option (mword 6) =>
+ (if ((match w__112 with
+ | Some
+ (imm) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2139_
+ _s1697_) >>= fun w__113 : option (mword 6) =>
+ (match w__113 with
+ | Some
+ (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2147_
+ _s1697_) >>= fun w__116 : option ((mword 5 * mword 6)) =>
+ (if ((match w__116 with
+ | Some
+ ((rd, imm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2147_
+ _s1697_) >>= fun w__117 : option ((mword 5 * mword 6)) =>
+ (match w__117 with
+ | Some
+ ((rd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2159_
+ _s1697_) >>= fun w__120 : option ((mword 3 * mword 6)) =>
+ (if ((match w__120 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2159_
+ _s1697_) >>= fun w__121 : option ((mword 3 * mword 6)) =>
+ (match w__121 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2171_
+ _s1697_) >>= fun w__124 : option ((mword 3 * mword 6)) =>
+ (if ((match w__124 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2171_
+ _s1697_) >>= fun w__125 : option ((mword 3 * mword 6)) =>
+ (match w__125 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2183_
+ _s1697_) >>= fun w__128 : option ((mword 3 * mword 6)) =>
+ (if
+ ((match w__128 with
+ | Some
+ ((rsd, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2183_
+ _s1697_) >>= fun w__129 : option ((mword 3 * mword 6)) =>
+ (match w__129 with
+ | Some
+ ((rsd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2195_
+ _s1697_) >>= fun w__132 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__132 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2195_
+ _s1697_) >>= fun w__133 : option ((mword 3 * mword 3)) =>
+ (match w__133 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2207_
+ _s1697_) >>= fun w__136 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__136 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2207_
+ _s1697_) >>= fun w__137 : option ((mword 3 * mword 3)) =>
+ (match w__137 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2219_
+ _s1697_) >>= fun w__140 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__140 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2219_
+ _s1697_) >>= fun w__141 : option ((mword 3 * mword 3)) =>
+ (match w__141 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2231_
+ _s1697_) >>= fun w__144 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__144 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2231_
+ _s1697_) >>= fun w__145 : option ((mword 3 * mword 3)) =>
+ (match w__145 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2243_
+ _s1697_) >>= fun w__148 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__148 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2243_
+ _s1697_) >>= fun w__149 : option ((mword 3 * mword 3)) =>
+ (match w__149 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2255_
+ _s1697_) >>= fun w__152 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__152 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2255_
+ _s1697_) >>= fun w__153 : option ((mword 3 * mword 3)) =>
+ (match w__153 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2267_
+ _s1697_) >>= fun w__156 : option (mword 11) =>
+ (if
+ ((match w__156 with
+ | Some
+ (imm) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2267_
+ _s1697_) >>= fun w__157 : option (mword 11) =>
+ (match w__157 with
+ | Some
+ (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2275_
+ _s1697_) >>= fun w__160 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__160 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2275_
+ _s1697_) >>= fun w__161 : option ((mword 3 * mword 8)) =>
+ (match w__161 with
+ | Some
+ ((rs, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2287_
+ _s1697_) >>= fun w__164 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__164 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2287_
+ _s1697_) >>= fun w__165 : option ((mword 3 * mword 8)) =>
+ (match w__165 with
+ | Some
+ ((rs, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2299_
+ _s1697_) >>= fun w__168 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__168 with
+ | Some
+ ((rsd, shamt)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2299_
+ _s1697_) >>= fun w__169 : option ((mword 5 * mword 6)) =>
+ (match w__169 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2311_
+ _s1697_) >>= fun w__172 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__172 with
+ | Some
+ ((rd, uimm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2311_
+ _s1697_) >>= fun w__173 : option ((mword 5 * mword 6)) =>
+ (match w__173 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2323_
+ _s1697_) >>= fun w__176 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__176 with
+ | Some
+ ((rd, uimm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 32
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s2323_
+ _s1697_) >>= fun w__177 : option ((mword 5 * mword 6)) =>
+ (match w__177 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2335_
+ _s1697_) >>= fun w__180 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__180 with
+ | Some
+ ((rd, uimm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2335_
+ _s1697_) >>= fun w__181 : option ((mword 5 * mword 6)) =>
+ (match w__181 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2347_
+ _s1697_) >>= fun w__184 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__184 with
+ | Some
+ ((rs2, uimm)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2347_
+ _s1697_) >>= fun w__185 : option ((mword 5 * mword 6)) =>
+ (match w__185 with
+ | Some
+ ((rs2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2359_
+ _s1697_) >>= fun w__188 : option (mword 5) =>
+ (if
+ ((match w__188 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2359_
+ _s1697_) >>= fun w__189 : option (mword 5) =>
+ (match w__189 with
+ | Some
+ (rs1) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2367_
+ _s1697_) >>= fun w__192 : option (mword 5) =>
+ (if
+ ((match w__192 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2367_
+ _s1697_) >>= fun w__193 : option (mword 5) =>
+ (match w__193 with
+ | Some
+ (rs1) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2375_
+ _s1697_) >>= fun w__196 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__196 with
+ | Some
+ ((rd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2375_
+ _s1697_) >>= fun w__197 : option ((mword 5 * mword 5)) =>
+ (match w__197 with
+ | Some
+ ((rd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else if
+ ((generic_eq
+ _s1697_
+ "c.ebreak"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2387_
+ _s1697_) >>= fun w__200 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__200 with
+ | Some
+ ((rsd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2387_
+ _s1697_) >>= fun w__201 : option ((mword 5 * mword 5)) =>
+ (match w__201 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2399_
+ _s1697_) >>= fun w__204 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__204 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2399_
+ _s1697_) >>= fun w__205 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__205 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2416_
+ _s1697_) >>= fun w__208 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__208 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2416_
+ _s1697_) >>= fun w__209 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__209 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2434_
+ _s1697_) >>= fun w__212 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__212 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2434_
+ _s1697_) >>= fun w__213 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__213 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2452_
+ _s1697_) >>= fun w__216 : option ((mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2452_
+ _s1697_) >>= fun w__217 : option ((mword 5 * mword 5 * mword 5)) =>
+ (match w__217 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2468_
+ _s1697_) >>= fun w__220 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2468_
+ _s1697_) >>= fun w__221 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__221 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2487_
+ _s1697_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2487_
+ _s1697_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2506_
+ _s1697_) >>= fun w__228 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2506_
+ _s1697_) >>= fun w__229 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__229 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2524_
+ _s1697_) >>= fun w__232 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2524_
+ _s1697_) >>= fun w__233 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__233 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else if
+ ((generic_eq
+ _s1697_
+ "uret"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2541_
+ _s1697_) >>= fun w__236 : option (mword 32) =>
+ (if
+ ((match w__236 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2541_
+ _s1697_) >>= fun w__237 : option (mword 32) =>
+ (match w__237 with
+ | Some
+ (s) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2549_
+ _s1697_) >>= fun w__240 : option (mword 16) =>
+ (if
+ ((match w__240 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2549_
+ _s1697_) >>= fun w__241 : option (mword 16) =>
+ (match w__241 with
+ | Some
+ (s) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool).
+
+Definition _s3457_ (_s3458_ : string)
+: M (option ((mword 16 * string))) :=
+
+ let _s3459_ := _s3458_ in
+ (if ((string_startswith _s3459_ "c.illegal")) then
+ (match (string_drop _s3459_ (projT1 (string_length "c.illegal"))) with
+ | _s3460_ =>
+ (spc_matches_prefix _s3460_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3461_ _)) =>
+ match (string_drop _s3460_ _s3461_) with
+ | _s3462_ =>
+ match (hex_bits_16_matches_prefix _s3462_) with
+ | Some ((s, existT _ _s3463_ _)) =>
+ match (string_drop _s3462_ _s3463_) with | s_ => Some ((s, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 16 * string)))
+ end)
+ : M (option ((mword 16 * string)))
+ else returnm (None : option ((mword 16 * string))))
+ : M (option ((mword 16 * string))).
+
+Definition _s3449_ (_s3450_ : string)
+: M (option ((mword 32 * string))) :=
+
+ let _s3451_ := _s3450_ in
+ (if ((string_startswith _s3451_ "illegal")) then
+ (match (string_drop _s3451_ (projT1 (string_length "illegal"))) with
+ | _s3452_ =>
+ (spc_matches_prefix _s3452_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3453_ _)) =>
+ match (string_drop _s3452_ _s3453_) with
+ | _s3454_ =>
+ match (hex_bits_32_matches_prefix _s3454_) with
+ | Some ((s, existT _ _s3455_ _)) =>
+ match (string_drop _s3454_ _s3455_) with | s_ => Some ((s, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 32 * string)))
+ end)
+ : M (option ((mword 32 * string)))
+ else returnm (None : option ((mword 32 * string))))
+ : M (option ((mword 32 * string))).
+
+Definition _s3445_ (_s3446_ : string)
+: option string :=
+
+ let _s3447_ := _s3446_ in
+ if ((string_startswith _s3447_ "uret")) then
+ match (string_drop _s3447_ (projT1 (string_length "uret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s3428_ (_s3429_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s3429_ with
+ | _s3430_ =>
+ (csr_mnemonic_matches_prefix _s3430_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s3431_ _)) =>
+ (match (string_drop _s3430_ _s3431_) with
+ | _s3432_ =>
+ (spc_matches_prefix _s3432_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3433_ _)) =>
+ (match (string_drop _s3432_ _s3433_) with
+ | _s3434_ =>
+ (reg_name_matches_prefix _s3434_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3435_ _)) =>
+ (match (string_drop _s3434_ _s3435_) with
+ | _s3436_ =>
+ (sep_matches_prefix _s3436_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3437_ _)) =>
+ (match (string_drop _s3436_ _s3437_) with
+ | _s3438_ =>
+ (reg_name_matches_prefix _s3438_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3439_ _)) =>
+ (match (string_drop _s3438_ _s3439_) with
+ | _s3440_ =>
+ (sep_matches_prefix _s3440_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3441_ _)) =>
+ (match (string_drop _s3440_ _s3441_) with
+ | _s3442_ =>
+ (csr_name_map_matches_prefix _s3442_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s3443_ _)) =>
+ match (string_drop _s3442_
+ _s3443_) with
+ | s_ =>
+ Some ((op, rd, rs1, csr, s_))
+ end
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s3410_ (_s3411_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s3411_ with
+ | _s3412_ =>
+ (csr_mnemonic_matches_prefix _s3412_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s3413_ _)) =>
+ let _s3414_ := string_drop _s3412_ _s3413_ in
+ (if ((string_startswith _s3414_ "i")) then
+ (match (string_drop _s3414_ (projT1 (string_length "i"))) with
+ | _s3415_ =>
+ (spc_matches_prefix _s3415_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3416_ _)) =>
+ (match (string_drop _s3415_ _s3416_) with
+ | _s3417_ =>
+ (reg_name_matches_prefix _s3417_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3418_ _)) =>
+ (match (string_drop _s3417_ _s3418_) with
+ | _s3419_ =>
+ (sep_matches_prefix _s3419_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3420_ _)) =>
+ (match (string_drop _s3419_ _s3420_) with
+ | _s3421_ =>
+ (match (hex_bits_5_matches_prefix _s3421_) with
+ | Some ((rs1, existT _ _s3422_ _)) =>
+ (match (string_drop _s3421_ _s3422_) with
+ | _s3423_ =>
+ (sep_matches_prefix _s3423_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s3424_ _)) =>
+ (match (string_drop _s3423_ _s3424_) with
+ | _s3425_ =>
+ (csr_name_map_matches_prefix _s3425_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s3426_ _)) =>
+ match (string_drop _s3425_
+ _s3426_) with
+ | s_ =>
+ Some
+ ((op, rd, rs1, csr, s_))
+ end
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s3391_ (_s3392_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3393_ := _s3392_ in
+ (if ((string_startswith _s3393_ "rem")) then
+ (match (string_drop _s3393_ (projT1 (string_length "rem"))) with
+ | _s3394_ =>
+ (maybe_not_u_matches_prefix _s3394_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3395_ _)) =>
+ let _s3396_ := string_drop _s3394_ _s3395_ in
+ (if ((string_startswith _s3396_ "w")) then
+ (match (string_drop _s3396_ (projT1 (string_length "w"))) with
+ | _s3397_ =>
+ (spc_matches_prefix _s3397_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3398_ _)) =>
+ (match (string_drop _s3397_ _s3398_) with
+ | _s3399_ =>
+ (reg_name_matches_prefix _s3399_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3400_ _)) =>
+ (match (string_drop _s3399_ _s3400_) with
+ | _s3401_ =>
+ (sep_matches_prefix _s3401_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3402_ _)) =>
+ (match (string_drop _s3401_ _s3402_) with
+ | _s3403_ =>
+ (reg_name_matches_prefix _s3403_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3404_ _)) =>
+ (match (string_drop _s3403_ _s3404_) with
+ | _s3405_ =>
+ (sep_matches_prefix _s3405_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3406_ _)) =>
+ (match (string_drop _s3405_ _s3406_) with
+ | _s3407_ =>
+ (reg_name_matches_prefix _s3407_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3408_ _)) =>
+ match (string_drop _s3407_
+ _s3408_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3372_ (_s3373_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3374_ := _s3373_ in
+ (if ((string_startswith _s3374_ "div")) then
+ (match (string_drop _s3374_ (projT1 (string_length "div"))) with
+ | _s3375_ =>
+ (maybe_not_u_matches_prefix _s3375_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3376_ _)) =>
+ let _s3377_ := string_drop _s3375_ _s3376_ in
+ (if ((string_startswith _s3377_ "w")) then
+ (match (string_drop _s3377_ (projT1 (string_length "w"))) with
+ | _s3378_ =>
+ (spc_matches_prefix _s3378_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3379_ _)) =>
+ (match (string_drop _s3378_ _s3379_) with
+ | _s3380_ =>
+ (reg_name_matches_prefix _s3380_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3381_ _)) =>
+ (match (string_drop _s3380_ _s3381_) with
+ | _s3382_ =>
+ (sep_matches_prefix _s3382_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3383_ _)) =>
+ (match (string_drop _s3382_ _s3383_) with
+ | _s3384_ =>
+ (reg_name_matches_prefix _s3384_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3385_ _)) =>
+ (match (string_drop _s3384_ _s3385_) with
+ | _s3386_ =>
+ (sep_matches_prefix _s3386_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3387_ _)) =>
+ (match (string_drop _s3386_ _s3387_) with
+ | _s3388_ =>
+ (reg_name_matches_prefix _s3388_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3389_ _)) =>
+ match (string_drop _s3388_
+ _s3389_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3356_ (_s3357_ : string)
+: M (option ((mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3358_ := _s3357_ in
+ (if ((string_startswith _s3358_ "mulw")) then
+ (match (string_drop _s3358_ (projT1 (string_length "mulw"))) with
+ | _s3359_ =>
+ (spc_matches_prefix _s3359_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3360_ _)) =>
+ (match (string_drop _s3359_ _s3360_) with
+ | _s3361_ =>
+ (reg_name_matches_prefix _s3361_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3362_ _)) =>
+ (match (string_drop _s3361_ _s3362_) with
+ | _s3363_ =>
+ (sep_matches_prefix _s3363_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3364_ _)) =>
+ (match (string_drop _s3363_ _s3364_) with
+ | _s3365_ =>
+ (reg_name_matches_prefix _s3365_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s3366_ _)) =>
+ (match (string_drop _s3365_ _s3366_) with
+ | _s3367_ =>
+ (sep_matches_prefix _s3367_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s3368_ _)) =>
+ (match (string_drop _s3367_ _s3368_) with
+ | _s3369_ =>
+ (reg_name_matches_prefix _s3369_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s3370_ _)) =>
+ match (string_drop _s3369_ _s3370_) with
+ | s_ => Some ((rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3338_ (_s3339_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3340_ := _s3339_ in
+ (if ((string_startswith _s3340_ "rem")) then
+ (match (string_drop _s3340_ (projT1 (string_length "rem"))) with
+ | _s3341_ =>
+ (maybe_not_u_matches_prefix _s3341_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3342_ _)) =>
+ (match (string_drop _s3341_ _s3342_) with
+ | _s3343_ =>
+ (spc_matches_prefix _s3343_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3344_ _)) =>
+ (match (string_drop _s3343_ _s3344_) with
+ | _s3345_ =>
+ (reg_name_matches_prefix _s3345_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3346_ _)) =>
+ (match (string_drop _s3345_ _s3346_) with
+ | _s3347_ =>
+ (sep_matches_prefix _s3347_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3348_ _)) =>
+ (match (string_drop _s3347_ _s3348_) with
+ | _s3349_ =>
+ (reg_name_matches_prefix _s3349_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3350_ _)) =>
+ (match (string_drop _s3349_ _s3350_) with
+ | _s3351_ =>
+ (sep_matches_prefix _s3351_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3352_ _)) =>
+ (match (string_drop _s3351_ _s3352_) with
+ | _s3353_ =>
+ (reg_name_matches_prefix _s3353_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3354_ _)) =>
+ match (string_drop _s3353_
+ _s3354_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3320_ (_s3321_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3322_ := _s3321_ in
+ (if ((string_startswith _s3322_ "div")) then
+ (match (string_drop _s3322_ (projT1 (string_length "div"))) with
+ | _s3323_ =>
+ (maybe_not_u_matches_prefix _s3323_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3324_ _)) =>
+ (match (string_drop _s3323_ _s3324_) with
+ | _s3325_ =>
+ (spc_matches_prefix _s3325_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3326_ _)) =>
+ (match (string_drop _s3325_ _s3326_) with
+ | _s3327_ =>
+ (reg_name_matches_prefix _s3327_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3328_ _)) =>
+ (match (string_drop _s3327_ _s3328_) with
+ | _s3329_ =>
+ (sep_matches_prefix _s3329_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3330_ _)) =>
+ (match (string_drop _s3329_ _s3330_) with
+ | _s3331_ =>
+ (reg_name_matches_prefix _s3331_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3332_ _)) =>
+ (match (string_drop _s3331_ _s3332_) with
+ | _s3333_ =>
+ (sep_matches_prefix _s3333_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3334_ _)) =>
+ (match (string_drop _s3333_ _s3334_) with
+ | _s3335_ =>
+ (reg_name_matches_prefix _s3335_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3336_ _)) =>
+ match (string_drop _s3335_
+ _s3336_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3303_ (_s3304_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s3304_ with
+ | _s3305_ =>
+ (mul_mnemonic_matches_prefix _s3305_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s3306_ _)) =>
+ (match (string_drop _s3305_ _s3306_) with
+ | _s3307_ =>
+ (spc_matches_prefix _s3307_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3308_ _)) =>
+ (match (string_drop _s3307_ _s3308_) with
+ | _s3309_ =>
+ (reg_name_matches_prefix _s3309_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3310_ _)) =>
+ (match (string_drop _s3309_ _s3310_) with
+ | _s3311_ =>
+ (sep_matches_prefix _s3311_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3312_ _)) =>
+ (match (string_drop _s3311_ _s3312_) with
+ | _s3313_ =>
+ (reg_name_matches_prefix _s3313_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3314_ _)) =>
+ (match (string_drop _s3313_ _s3314_) with
+ | _s3315_ =>
+ (sep_matches_prefix _s3315_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3316_ _)) =>
+ (match (string_drop _s3315_ _s3316_) with
+ | _s3317_ =>
+ (reg_name_matches_prefix _s3317_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s3318_ _)) =>
+ match (string_drop _s3317_
+ _s3318_) with
+ | s_ =>
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3291_ (_s3292_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s3293_ := _s3292_ in
+ (if ((string_startswith _s3293_ "c.add")) then
+ (match (string_drop _s3293_ (projT1 (string_length "c.add"))) with
+ | _s3294_ =>
+ (spc_matches_prefix _s3294_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3295_ _)) =>
+ (match (string_drop _s3294_ _s3295_) with
+ | _s3296_ =>
+ (reg_name_matches_prefix _s3296_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3297_ _)) =>
+ (match (string_drop _s3296_ _s3297_) with
+ | _s3298_ =>
+ (sep_matches_prefix _s3298_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3299_ _)) =>
+ (match (string_drop _s3298_ _s3299_) with
+ | _s3300_ =>
+ (reg_name_matches_prefix _s3300_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3301_ _)) =>
+ match (string_drop _s3300_ _s3301_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s3287_ (_s3288_ : string)
+: option string :=
+
+ let _s3289_ := _s3288_ in
+ if ((string_startswith _s3289_ "c.ebreak")) then
+ match (string_drop _s3289_ (projT1 (string_length "c.ebreak"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s3275_ (_s3276_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s3277_ := _s3276_ in
+ (if ((string_startswith _s3277_ "c.mv")) then
+ (match (string_drop _s3277_ (projT1 (string_length "c.mv"))) with
+ | _s3278_ =>
+ (spc_matches_prefix _s3278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3279_ _)) =>
+ (match (string_drop _s3278_ _s3279_) with
+ | _s3280_ =>
+ (reg_name_matches_prefix _s3280_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3281_ _)) =>
+ (match (string_drop _s3280_ _s3281_) with
+ | _s3282_ =>
+ (sep_matches_prefix _s3282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3283_ _)) =>
+ (match (string_drop _s3282_ _s3283_) with
+ | _s3284_ =>
+ (reg_name_matches_prefix _s3284_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3285_ _)) =>
+ match (string_drop _s3284_ _s3285_) with
+ | s_ => Some ((rd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s3267_ (_s3268_ : string)
+: M (option ((mword 5 * string))) :=
+
+ let _s3269_ := _s3268_ in
+ (if ((string_startswith _s3269_ "c.jalr")) then
+ (match (string_drop _s3269_ (projT1 (string_length "c.jalr"))) with
+ | _s3270_ =>
+ (spc_matches_prefix _s3270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3271_ _)) =>
+ (match (string_drop _s3270_ _s3271_) with
+ | _s3272_ =>
+ (reg_name_matches_prefix _s3272_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s3273_ _)) =>
+ match (string_drop _s3272_ _s3273_) with | s_ => Some ((rs1, s_)) end
+ | _ => None
+ end)
+ : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ else returnm (None : option ((mword 5 * string))))
+ : M (option ((mword 5 * string))).
+
+Definition _s3259_ (_s3260_ : string)
+: M (option ((mword 5 * string))) :=
+
+ let _s3261_ := _s3260_ in
+ (if ((string_startswith _s3261_ "c.jr")) then
+ (match (string_drop _s3261_ (projT1 (string_length "c.jr"))) with
+ | _s3262_ =>
+ (spc_matches_prefix _s3262_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3263_ _)) =>
+ (match (string_drop _s3262_ _s3263_) with
+ | _s3264_ =>
+ (reg_name_matches_prefix _s3264_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s3265_ _)) =>
+ match (string_drop _s3264_ _s3265_) with | s_ => Some ((rs1, s_)) end
+ | _ => None
+ end)
+ : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ else returnm (None : option ((mword 5 * string))))
+ : M (option ((mword 5 * string))).
+
+Definition _s3247_ (_s3248_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3249_ := _s3248_ in
+ (if ((string_startswith _s3249_ "c.sdsp")) then
+ (match (string_drop _s3249_ (projT1 (string_length "c.sdsp"))) with
+ | _s3250_ =>
+ (spc_matches_prefix _s3250_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3251_ _)) =>
+ (match (string_drop _s3250_ _s3251_) with
+ | _s3252_ =>
+ (reg_name_matches_prefix _s3252_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s3253_ _)) =>
+ (match (string_drop _s3252_ _s3253_) with
+ | _s3254_ =>
+ (sep_matches_prefix _s3254_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3255_ _)) =>
+ match (string_drop _s3254_ _s3255_) with
+ | _s3256_ =>
+ match (hex_bits_6_matches_prefix _s3256_) with
+ | Some ((uimm, existT _ _s3257_ _)) =>
+ match (string_drop _s3256_ _s3257_) with
+ | s_ => Some ((rs2, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3235_ (_s3236_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3237_ := _s3236_ in
+ (if ((string_startswith _s3237_ "c.swsp")) then
+ (match (string_drop _s3237_ (projT1 (string_length "c.swsp"))) with
+ | _s3238_ =>
+ (spc_matches_prefix _s3238_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3239_ _)) =>
+ (match (string_drop _s3238_ _s3239_) with
+ | _s3240_ =>
+ (reg_name_matches_prefix _s3240_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3241_ _)) =>
+ (match (string_drop _s3240_ _s3241_) with
+ | _s3242_ =>
+ (sep_matches_prefix _s3242_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3243_ _)) =>
+ match (string_drop _s3242_ _s3243_) with
+ | _s3244_ =>
+ match (hex_bits_6_matches_prefix _s3244_) with
+ | Some ((uimm, existT _ _s3245_ _)) =>
+ match (string_drop _s3244_ _s3245_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3223_ (_s3224_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3225_ := _s3224_ in
+ (if ((string_startswith _s3225_ "c.ldsp")) then
+ (match (string_drop _s3225_ (projT1 (string_length "c.ldsp"))) with
+ | _s3226_ =>
+ (spc_matches_prefix _s3226_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3227_ _)) =>
+ (match (string_drop _s3226_ _s3227_) with
+ | _s3228_ =>
+ (reg_name_matches_prefix _s3228_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3229_ _)) =>
+ (match (string_drop _s3228_ _s3229_) with
+ | _s3230_ =>
+ (sep_matches_prefix _s3230_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3231_ _)) =>
+ match (string_drop _s3230_ _s3231_) with
+ | _s3232_ =>
+ match (hex_bits_6_matches_prefix _s3232_) with
+ | Some ((uimm, existT _ _s3233_ _)) =>
+ match (string_drop _s3232_ _s3233_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3211_ (_s3212_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3213_ := _s3212_ in
+ (if ((string_startswith _s3213_ "c.lwsp")) then
+ (match (string_drop _s3213_ (projT1 (string_length "c.lwsp"))) with
+ | _s3214_ =>
+ (spc_matches_prefix _s3214_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3215_ _)) =>
+ (match (string_drop _s3214_ _s3215_) with
+ | _s3216_ =>
+ (reg_name_matches_prefix _s3216_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3217_ _)) =>
+ (match (string_drop _s3216_ _s3217_) with
+ | _s3218_ =>
+ (sep_matches_prefix _s3218_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3219_ _)) =>
+ match (string_drop _s3218_ _s3219_) with
+ | _s3220_ =>
+ match (hex_bits_6_matches_prefix _s3220_) with
+ | Some ((uimm, existT _ _s3221_ _)) =>
+ match (string_drop _s3220_ _s3221_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3199_ (_s3200_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3201_ := _s3200_ in
+ (if ((string_startswith _s3201_ "c.slli")) then
+ (match (string_drop _s3201_ (projT1 (string_length "c.slli"))) with
+ | _s3202_ =>
+ (spc_matches_prefix _s3202_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3203_ _)) =>
+ (match (string_drop _s3202_ _s3203_) with
+ | _s3204_ =>
+ (reg_name_matches_prefix _s3204_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3205_ _)) =>
+ (match (string_drop _s3204_ _s3205_) with
+ | _s3206_ =>
+ (sep_matches_prefix _s3206_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3207_ _)) =>
+ match (string_drop _s3206_ _s3207_) with
+ | _s3208_ =>
+ match (hex_bits_6_matches_prefix _s3208_) with
+ | Some ((shamt, existT _ _s3209_ _)) =>
+ match (string_drop _s3208_ _s3209_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3187_ (_s3188_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s3189_ := _s3188_ in
+ (if ((string_startswith _s3189_ "c.bnez")) then
+ (match (string_drop _s3189_ (projT1 (string_length "c.bnez"))) with
+ | _s3190_ =>
+ (spc_matches_prefix _s3190_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3191_ _)) =>
+ (match (string_drop _s3190_ _s3191_) with
+ | _s3192_ =>
+ (creg_name_matches_prefix _s3192_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s3193_ _)) =>
+ (match (string_drop _s3192_ _s3193_) with
+ | _s3194_ =>
+ (sep_matches_prefix _s3194_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3195_ _)) =>
+ match (string_drop _s3194_ _s3195_) with
+ | _s3196_ =>
+ match (hex_bits_8_matches_prefix _s3196_) with
+ | Some ((imm, existT _ _s3197_ _)) =>
+ match (string_drop _s3196_ _s3197_) with
+ | s_ => Some ((rs, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s3175_ (_s3176_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s3177_ := _s3176_ in
+ (if ((string_startswith _s3177_ "c.beqz")) then
+ (match (string_drop _s3177_ (projT1 (string_length "c.beqz"))) with
+ | _s3178_ =>
+ (spc_matches_prefix _s3178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3179_ _)) =>
+ (match (string_drop _s3178_ _s3179_) with
+ | _s3180_ =>
+ (creg_name_matches_prefix _s3180_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s3181_ _)) =>
+ (match (string_drop _s3180_ _s3181_) with
+ | _s3182_ =>
+ (sep_matches_prefix _s3182_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3183_ _)) =>
+ match (string_drop _s3182_ _s3183_) with
+ | _s3184_ =>
+ match (hex_bits_8_matches_prefix _s3184_) with
+ | Some ((imm, existT _ _s3185_ _)) =>
+ match (string_drop _s3184_ _s3185_) with
+ | s_ => Some ((rs, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s3167_ (_s3168_ : string)
+: M (option ((mword 11 * string))) :=
+
+ let _s3169_ := _s3168_ in
+ (if ((string_startswith _s3169_ "c.j")) then
+ (match (string_drop _s3169_ (projT1 (string_length "c.j"))) with
+ | _s3170_ =>
+ (spc_matches_prefix _s3170_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3171_ _)) =>
+ match (string_drop _s3170_ _s3171_) with
+ | _s3172_ =>
+ match (hex_bits_11_matches_prefix _s3172_) with
+ | Some ((imm, existT _ _s3173_ _)) =>
+ match (string_drop _s3172_ _s3173_) with | s_ => Some ((imm, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 11 * string)))
+ end)
+ : M (option ((mword 11 * string)))
+ else returnm (None : option ((mword 11 * string))))
+ : M (option ((mword 11 * string))).
+
+Definition _s3155_ (_s3156_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3157_ := _s3156_ in
+ (if ((string_startswith _s3157_ "c.addw")) then
+ (match (string_drop _s3157_ (projT1 (string_length "c.addw"))) with
+ | _s3158_ =>
+ (spc_matches_prefix _s3158_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3159_ _)) =>
+ (match (string_drop _s3158_ _s3159_) with
+ | _s3160_ =>
+ (creg_name_matches_prefix _s3160_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3161_ _)) =>
+ (match (string_drop _s3160_ _s3161_) with
+ | _s3162_ =>
+ (sep_matches_prefix _s3162_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3163_ _)) =>
+ (match (string_drop _s3162_ _s3163_) with
+ | _s3164_ =>
+ (creg_name_matches_prefix _s3164_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3165_ _)) =>
+ match (string_drop _s3164_ _s3165_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3143_ (_s3144_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3145_ := _s3144_ in
+ (if ((string_startswith _s3145_ "c.subw")) then
+ (match (string_drop _s3145_ (projT1 (string_length "c.subw"))) with
+ | _s3146_ =>
+ (spc_matches_prefix _s3146_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3147_ _)) =>
+ (match (string_drop _s3146_ _s3147_) with
+ | _s3148_ =>
+ (creg_name_matches_prefix _s3148_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3149_ _)) =>
+ (match (string_drop _s3148_ _s3149_) with
+ | _s3150_ =>
+ (sep_matches_prefix _s3150_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3151_ _)) =>
+ (match (string_drop _s3150_ _s3151_) with
+ | _s3152_ =>
+ (creg_name_matches_prefix _s3152_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3153_ _)) =>
+ match (string_drop _s3152_ _s3153_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3131_ (_s3132_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3133_ := _s3132_ in
+ (if ((string_startswith _s3133_ "c.and")) then
+ (match (string_drop _s3133_ (projT1 (string_length "c.and"))) with
+ | _s3134_ =>
+ (spc_matches_prefix _s3134_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3135_ _)) =>
+ (match (string_drop _s3134_ _s3135_) with
+ | _s3136_ =>
+ (creg_name_matches_prefix _s3136_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3137_ _)) =>
+ (match (string_drop _s3136_ _s3137_) with
+ | _s3138_ =>
+ (sep_matches_prefix _s3138_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3139_ _)) =>
+ (match (string_drop _s3138_ _s3139_) with
+ | _s3140_ =>
+ (creg_name_matches_prefix _s3140_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3141_ _)) =>
+ match (string_drop _s3140_ _s3141_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3119_ (_s3120_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3121_ := _s3120_ in
+ (if ((string_startswith _s3121_ "c.or")) then
+ (match (string_drop _s3121_ (projT1 (string_length "c.or"))) with
+ | _s3122_ =>
+ (spc_matches_prefix _s3122_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3123_ _)) =>
+ (match (string_drop _s3122_ _s3123_) with
+ | _s3124_ =>
+ (creg_name_matches_prefix _s3124_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3125_ _)) =>
+ (match (string_drop _s3124_ _s3125_) with
+ | _s3126_ =>
+ (sep_matches_prefix _s3126_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3127_ _)) =>
+ (match (string_drop _s3126_ _s3127_) with
+ | _s3128_ =>
+ (creg_name_matches_prefix _s3128_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3129_ _)) =>
+ match (string_drop _s3128_ _s3129_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3107_ (_s3108_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3109_ := _s3108_ in
+ (if ((string_startswith _s3109_ "c.xor")) then
+ (match (string_drop _s3109_ (projT1 (string_length "c.xor"))) with
+ | _s3110_ =>
+ (spc_matches_prefix _s3110_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3111_ _)) =>
+ (match (string_drop _s3110_ _s3111_) with
+ | _s3112_ =>
+ (creg_name_matches_prefix _s3112_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3113_ _)) =>
+ (match (string_drop _s3112_ _s3113_) with
+ | _s3114_ =>
+ (sep_matches_prefix _s3114_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3115_ _)) =>
+ (match (string_drop _s3114_ _s3115_) with
+ | _s3116_ =>
+ (creg_name_matches_prefix _s3116_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3117_ _)) =>
+ match (string_drop _s3116_ _s3117_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3095_ (_s3096_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3097_ := _s3096_ in
+ (if ((string_startswith _s3097_ "c.sub")) then
+ (match (string_drop _s3097_ (projT1 (string_length "c.sub"))) with
+ | _s3098_ =>
+ (spc_matches_prefix _s3098_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3099_ _)) =>
+ (match (string_drop _s3098_ _s3099_) with
+ | _s3100_ =>
+ (creg_name_matches_prefix _s3100_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3101_ _)) =>
+ (match (string_drop _s3100_ _s3101_) with
+ | _s3102_ =>
+ (sep_matches_prefix _s3102_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3103_ _)) =>
+ (match (string_drop _s3102_ _s3103_) with
+ | _s3104_ =>
+ (creg_name_matches_prefix _s3104_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3105_ _)) =>
+ match (string_drop _s3104_ _s3105_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3083_ (_s3084_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3085_ := _s3084_ in
+ (if ((string_startswith _s3085_ "c.andi")) then
+ (match (string_drop _s3085_ (projT1 (string_length "c.andi"))) with
+ | _s3086_ =>
+ (spc_matches_prefix _s3086_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3087_ _)) =>
+ (match (string_drop _s3086_ _s3087_) with
+ | _s3088_ =>
+ (creg_name_matches_prefix _s3088_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3089_ _)) =>
+ (match (string_drop _s3088_ _s3089_) with
+ | _s3090_ =>
+ (sep_matches_prefix _s3090_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3091_ _)) =>
+ match (string_drop _s3090_ _s3091_) with
+ | _s3092_ =>
+ match (hex_bits_6_matches_prefix _s3092_) with
+ | Some ((imm, existT _ _s3093_ _)) =>
+ match (string_drop _s3092_ _s3093_) with
+ | s_ => Some ((rsd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3071_ (_s3072_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3073_ := _s3072_ in
+ (if ((string_startswith _s3073_ "c.srai")) then
+ (match (string_drop _s3073_ (projT1 (string_length "c.srai"))) with
+ | _s3074_ =>
+ (spc_matches_prefix _s3074_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3075_ _)) =>
+ (match (string_drop _s3074_ _s3075_) with
+ | _s3076_ =>
+ (creg_name_matches_prefix _s3076_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3077_ _)) =>
+ (match (string_drop _s3076_ _s3077_) with
+ | _s3078_ =>
+ (sep_matches_prefix _s3078_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3079_ _)) =>
+ match (string_drop _s3078_ _s3079_) with
+ | _s3080_ =>
+ match (hex_bits_6_matches_prefix _s3080_) with
+ | Some ((shamt, existT _ _s3081_ _)) =>
+ match (string_drop _s3080_ _s3081_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3059_ (_s3060_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3061_ := _s3060_ in
+ (if ((string_startswith _s3061_ "c.srli")) then
+ (match (string_drop _s3061_ (projT1 (string_length "c.srli"))) with
+ | _s3062_ =>
+ (spc_matches_prefix _s3062_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3063_ _)) =>
+ (match (string_drop _s3062_ _s3063_) with
+ | _s3064_ =>
+ (creg_name_matches_prefix _s3064_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3065_ _)) =>
+ (match (string_drop _s3064_ _s3065_) with
+ | _s3066_ =>
+ (sep_matches_prefix _s3066_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3067_ _)) =>
+ match (string_drop _s3066_ _s3067_) with
+ | _s3068_ =>
+ match (hex_bits_6_matches_prefix _s3068_) with
+ | Some ((shamt, existT _ _s3069_ _)) =>
+ match (string_drop _s3068_ _s3069_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3047_ (_s3048_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3049_ := _s3048_ in
+ (if ((string_startswith _s3049_ "c.lui")) then
+ (match (string_drop _s3049_ (projT1 (string_length "c.lui"))) with
+ | _s3050_ =>
+ (spc_matches_prefix _s3050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3051_ _)) =>
+ (match (string_drop _s3050_ _s3051_) with
+ | _s3052_ =>
+ (reg_name_matches_prefix _s3052_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3053_ _)) =>
+ (match (string_drop _s3052_ _s3053_) with
+ | _s3054_ =>
+ (sep_matches_prefix _s3054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3055_ _)) =>
+ match (string_drop _s3054_ _s3055_) with
+ | _s3056_ =>
+ match (hex_bits_6_matches_prefix _s3056_) with
+ | Some ((imm, existT _ _s3057_ _)) =>
+ match (string_drop _s3056_ _s3057_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3039_ (_s3040_ : string)
+: M (option ((mword 6 * string))) :=
+
+ let _s3041_ := _s3040_ in
+ (if ((string_startswith _s3041_ "c.addi16sp")) then
+ (match (string_drop _s3041_ (projT1 (string_length "c.addi16sp"))) with
+ | _s3042_ =>
+ (spc_matches_prefix _s3042_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3043_ _)) =>
+ match (string_drop _s3042_ _s3043_) with
+ | _s3044_ =>
+ match (hex_bits_6_matches_prefix _s3044_) with
+ | Some ((imm, existT _ _s3045_ _)) =>
+ match (string_drop _s3044_ _s3045_) with | s_ => Some ((imm, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 6 * string)))
+ end)
+ : M (option ((mword 6 * string)))
+ else returnm (None : option ((mword 6 * string))))
+ : M (option ((mword 6 * string))).
+
+Definition _s3027_ (_s3028_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3029_ := _s3028_ in
+ (if ((string_startswith _s3029_ "c.li")) then
+ (match (string_drop _s3029_ (projT1 (string_length "c.li"))) with
+ | _s3030_ =>
+ (spc_matches_prefix _s3030_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3031_ _)) =>
+ (match (string_drop _s3030_ _s3031_) with
+ | _s3032_ =>
+ (reg_name_matches_prefix _s3032_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3033_ _)) =>
+ (match (string_drop _s3032_ _s3033_) with
+ | _s3034_ =>
+ (sep_matches_prefix _s3034_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3035_ _)) =>
+ match (string_drop _s3034_ _s3035_) with
+ | _s3036_ =>
+ match (hex_bits_6_matches_prefix _s3036_) with
+ | Some ((imm, existT _ _s3037_ _)) =>
+ match (string_drop _s3036_ _s3037_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3015_ (_s3016_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3017_ := _s3016_ in
+ (if ((string_startswith _s3017_ "c.addiw")) then
+ (match (string_drop _s3017_ (projT1 (string_length "c.addiw"))) with
+ | _s3018_ =>
+ (spc_matches_prefix _s3018_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3019_ _)) =>
+ (match (string_drop _s3018_ _s3019_) with
+ | _s3020_ =>
+ (reg_name_matches_prefix _s3020_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3021_ _)) =>
+ (match (string_drop _s3020_ _s3021_) with
+ | _s3022_ =>
+ (sep_matches_prefix _s3022_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3023_ _)) =>
+ match (string_drop _s3022_ _s3023_) with
+ | _s3024_ =>
+ match (hex_bits_6_matches_prefix _s3024_) with
+ | Some ((imm, existT _ _s3025_ _)) =>
+ match (string_drop _s3024_ _s3025_) with
+ | s_ => Some ((rsd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3007_ (_s3008_ : string)
+: M (option ((mword 11 * string))) :=
+
+ let _s3009_ := _s3008_ in
+ (if ((string_startswith _s3009_ "c.jal")) then
+ (match (string_drop _s3009_ (projT1 (string_length "c.jal"))) with
+ | _s3010_ =>
+ (spc_matches_prefix _s3010_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3011_ _)) =>
+ match (string_drop _s3010_ _s3011_) with
+ | _s3012_ =>
+ match (hex_bits_12_matches_prefix _s3012_) with
+ | Some ((v__826, existT _ _s3013_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__826 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__826 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__826 11 1 in
+ match (string_drop _s3012_ _s3013_) with | s_ => Some ((imm, s_)) end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 11 * string)))
+ end)
+ : M (option ((mword 11 * string)))
+ else returnm (None : option ((mword 11 * string))))
+ : M (option ((mword 11 * string))).
+
+Definition _s2995_ (_s2996_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s2997_ := _s2996_ in
+ (if ((string_startswith _s2997_ "c.addi")) then
+ (match (string_drop _s2997_ (projT1 (string_length "c.addi"))) with
+ | _s2998_ =>
+ (spc_matches_prefix _s2998_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2999_ _)) =>
+ (match (string_drop _s2998_ _s2999_) with
+ | _s3000_ =>
+ (reg_name_matches_prefix _s3000_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3001_ _)) =>
+ (match (string_drop _s3000_ _s3001_) with
+ | _s3002_ =>
+ (sep_matches_prefix _s3002_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3003_ _)) =>
+ match (string_drop _s3002_ _s3003_) with
+ | _s3004_ =>
+ match (hex_bits_6_matches_prefix _s3004_) with
+ | Some ((nzi, existT _ _s3005_ _)) =>
+ match (string_drop _s3004_ _s3005_) with
+ | s_ => Some ((rsd, nzi, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s2979_ (_s2980_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2981_ := _s2980_ in
+ (if ((string_startswith _s2981_ "c.sd")) then
+ (match (string_drop _s2981_ (projT1 (string_length "c.sd"))) with
+ | _s2982_ =>
+ (spc_matches_prefix _s2982_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2983_ _)) =>
+ (match (string_drop _s2982_ _s2983_) with
+ | _s2984_ =>
+ (creg_name_matches_prefix _s2984_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2985_ _)) =>
+ (match (string_drop _s2984_ _s2985_) with
+ | _s2986_ =>
+ (sep_matches_prefix _s2986_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2987_ _)) =>
+ (match (string_drop _s2986_ _s2987_) with
+ | _s2988_ =>
+ (creg_name_matches_prefix _s2988_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2989_ _)) =>
+ (match (string_drop _s2988_ _s2989_) with
+ | _s2990_ =>
+ (sep_matches_prefix _s2990_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2991_ _)) =>
+ match (string_drop _s2990_ _s2991_) with
+ | _s2992_ =>
+ match (hex_bits_8_matches_prefix _s2992_) with
+ | Some ((v__828, existT _ _s2993_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__828 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__828 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__828 7 3 in
+ match (string_drop _s2992_ _s2993_) with
+ | s_ => Some ((rsc1, rsc2, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2963_ (_s2964_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2965_ := _s2964_ in
+ (if ((string_startswith _s2965_ "c.sw")) then
+ (match (string_drop _s2965_ (projT1 (string_length "c.sw"))) with
+ | _s2966_ =>
+ (spc_matches_prefix _s2966_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2967_ _)) =>
+ (match (string_drop _s2966_ _s2967_) with
+ | _s2968_ =>
+ (creg_name_matches_prefix _s2968_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2969_ _)) =>
+ (match (string_drop _s2968_ _s2969_) with
+ | _s2970_ =>
+ (sep_matches_prefix _s2970_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2971_ _)) =>
+ (match (string_drop _s2970_ _s2971_) with
+ | _s2972_ =>
+ (creg_name_matches_prefix _s2972_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2973_ _)) =>
+ (match (string_drop _s2972_ _s2973_) with
+ | _s2974_ =>
+ (sep_matches_prefix _s2974_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2975_ _)) =>
+ match (string_drop _s2974_ _s2975_) with
+ | _s2976_ =>
+ match (hex_bits_7_matches_prefix _s2976_) with
+ | Some ((v__830, existT _ _s2977_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__830 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__830 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__830 6 2 in
+ match (string_drop _s2976_ _s2977_) with
+ | s_ => Some ((rsc1, rsc2, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2947_ (_s2948_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2949_ := _s2948_ in
+ (if ((string_startswith _s2949_ "c.ld")) then
+ (match (string_drop _s2949_ (projT1 (string_length "c.ld"))) with
+ | _s2950_ =>
+ (spc_matches_prefix _s2950_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2951_ _)) =>
+ (match (string_drop _s2950_ _s2951_) with
+ | _s2952_ =>
+ (creg_name_matches_prefix _s2952_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2953_ _)) =>
+ (match (string_drop _s2952_ _s2953_) with
+ | _s2954_ =>
+ (sep_matches_prefix _s2954_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2955_ _)) =>
+ (match (string_drop _s2954_ _s2955_) with
+ | _s2956_ =>
+ (creg_name_matches_prefix _s2956_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2957_ _)) =>
+ (match (string_drop _s2956_ _s2957_) with
+ | _s2958_ =>
+ (sep_matches_prefix _s2958_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2959_ _)) =>
+ match (string_drop _s2958_ _s2959_) with
+ | _s2960_ =>
+ match (hex_bits_8_matches_prefix _s2960_) with
+ | Some ((v__832, existT _ _s2961_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__832 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__832 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__832 7 3 in
+ match (string_drop _s2960_ _s2961_) with
+ | s_ => Some ((rdc, rsc, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2931_ (_s2932_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2933_ := _s2932_ in
+ (if ((string_startswith _s2933_ "c.lw")) then
+ (match (string_drop _s2933_ (projT1 (string_length "c.lw"))) with
+ | _s2934_ =>
+ (spc_matches_prefix _s2934_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2935_ _)) =>
+ (match (string_drop _s2934_ _s2935_) with
+ | _s2936_ =>
+ (creg_name_matches_prefix _s2936_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2937_ _)) =>
+ (match (string_drop _s2936_ _s2937_) with
+ | _s2938_ =>
+ (sep_matches_prefix _s2938_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2939_ _)) =>
+ (match (string_drop _s2938_ _s2939_) with
+ | _s2940_ =>
+ (creg_name_matches_prefix _s2940_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2941_ _)) =>
+ (match (string_drop _s2940_ _s2941_) with
+ | _s2942_ =>
+ (sep_matches_prefix _s2942_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2943_ _)) =>
+ match (string_drop _s2942_ _s2943_) with
+ | _s2944_ =>
+ match (hex_bits_7_matches_prefix _s2944_) with
+ | Some ((v__834, existT _ _s2945_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__834 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__834 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__834 6 2 in
+ match (string_drop _s2944_ _s2945_) with
+ | s_ => Some ((rdc, rsc, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2919_ (_s2920_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s2921_ := _s2920_ in
+ (if ((string_startswith _s2921_ "c.addi4spn")) then
+ (match (string_drop _s2921_ (projT1 (string_length "c.addi4spn"))) with
+ | _s2922_ =>
+ (spc_matches_prefix _s2922_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2923_ _)) =>
+ (match (string_drop _s2922_ _s2923_) with
+ | _s2924_ =>
+ (creg_name_matches_prefix _s2924_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2925_ _)) =>
+ (match (string_drop _s2924_ _s2925_) with
+ | _s2926_ =>
+ (sep_matches_prefix _s2926_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2927_ _)) =>
+ match (string_drop _s2926_ _s2927_) with
+ | _s2928_ =>
+ match (hex_bits_10_matches_prefix _s2928_) with
+ | Some ((v__836, existT _ _s2929_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__836 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__836 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__836 9 2 in
+ match (string_drop _s2928_ _s2929_) with
+ | s_ => Some ((rdc, nzimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s2915_ (_s2916_ : string)
+: option string :=
+
+ let _s2917_ := _s2916_ in
+ if ((string_startswith _s2917_ "c.nop")) then
+ match (string_drop _s2917_ (projT1 (string_length "c.nop"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2891_ (_s2892_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2892_ with
+ | _s2893_ =>
+ (amo_mnemonic_matches_prefix _s2893_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2894_ _)) =>
+ let _s2895_ := string_drop _s2893_ _s2894_ in
+ (if ((string_startswith _s2895_ ".")) then
+ (match (string_drop _s2895_ (projT1 (string_length "."))) with
+ | _s2896_ =>
+ (size_mnemonic_matches_prefix _s2896_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s2897_ _)) =>
+ (match (string_drop _s2896_ _s2897_) with
+ | _s2898_ =>
+ (maybe_aq_matches_prefix _s2898_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2899_ _)) =>
+ (match (string_drop _s2898_ _s2899_) with
+ | _s2900_ =>
+ (maybe_rl_matches_prefix _s2900_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2901_ _)) =>
+ (match (string_drop _s2900_ _s2901_) with
+ | _s2902_ =>
+ (spc_matches_prefix _s2902_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2903_ _)) =>
+ (match (string_drop _s2902_ _s2903_) with
+ | _s2904_ =>
+ (reg_name_matches_prefix _s2904_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2905_ _)) =>
+ (match (string_drop _s2904_ _s2905_) with
+ | _s2906_ =>
+ (sep_matches_prefix _s2906_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2907_ _)) =>
+ (match (string_drop _s2906_ _s2907_) with
+ | _s2908_ =>
+ (reg_name_matches_prefix _s2908_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s2909_ _)) =>
+ (match (string_drop _s2908_
+ _s2909_) with
+ | _s2910_ =>
+ (sep_matches_prefix
+ _s2910_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2911_ _)) =>
+ (match (string_drop
+ _s2910_
+ _s2911_) with
+ | _s2912_ =>
+ (reg_name_matches_prefix
+ _s2912_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s2913_ _)) =>
+ match (string_drop
+ _s2912_
+ _s2913_) with
+ | s_ =>
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_))
+ end
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2869_ (_s2870_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s2871_ := _s2870_ in
+ (if ((string_startswith _s2871_ "sc.")) then
+ (match (string_drop _s2871_ (projT1 (string_length "sc."))) with
+ | _s2872_ =>
+ (size_mnemonic_matches_prefix _s2872_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2873_ _)) =>
+ (match (string_drop _s2872_ _s2873_) with
+ | _s2874_ =>
+ (maybe_aq_matches_prefix _s2874_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2875_ _)) =>
+ (match (string_drop _s2874_ _s2875_) with
+ | _s2876_ =>
+ (maybe_rl_matches_prefix _s2876_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2877_ _)) =>
+ (match (string_drop _s2876_ _s2877_) with
+ | _s2878_ =>
+ (spc_matches_prefix _s2878_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2879_ _)) =>
+ (match (string_drop _s2878_ _s2879_) with
+ | _s2880_ =>
+ (reg_name_matches_prefix _s2880_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s2881_ _)) =>
+ (match (string_drop _s2880_ _s2881_) with
+ | _s2882_ =>
+ (sep_matches_prefix _s2882_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2883_ _)) =>
+ (match (string_drop _s2882_ _s2883_) with
+ | _s2884_ =>
+ (reg_name_matches_prefix _s2884_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s2885_ _)) =>
+ (match (string_drop _s2884_ _s2885_) with
+ | _s2886_ =>
+ (sep_matches_prefix _s2886_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s2887_ _)) =>
+ (match (string_drop _s2886_
+ _s2887_) with
+ | _s2888_ =>
+ (reg_name_matches_prefix
+ _s2888_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s2889_ _)) =>
+ match (string_drop
+ _s2888_
+ _s2889_) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2851_ (_s2852_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) :=
+
+ let _s2853_ := _s2852_ in
+ (if ((string_startswith _s2853_ "lr.")) then
+ (match (string_drop _s2853_ (projT1 (string_length "lr."))) with
+ | _s2854_ =>
+ (size_mnemonic_matches_prefix _s2854_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2855_ _)) =>
+ (match (string_drop _s2854_ _s2855_) with
+ | _s2856_ =>
+ (maybe_aq_matches_prefix _s2856_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2857_ _)) =>
+ (match (string_drop _s2856_ _s2857_) with
+ | _s2858_ =>
+ (maybe_rl_matches_prefix _s2858_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2859_ _)) =>
+ (match (string_drop _s2858_ _s2859_) with
+ | _s2860_ =>
+ (spc_matches_prefix _s2860_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2861_ _)) =>
+ (match (string_drop _s2860_ _s2861_) with
+ | _s2862_ =>
+ (reg_name_matches_prefix _s2862_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s2863_ _)) =>
+ (match (string_drop _s2862_ _s2863_) with
+ | _s2864_ =>
+ (sep_matches_prefix _s2864_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2865_ _)) =>
+ (match (string_drop _s2864_ _s2865_) with
+ | _s2866_ =>
+ (reg_name_matches_prefix _s2866_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s2867_ _)) =>
+ match (string_drop _s2866_
+ _s2867_) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rd, rs1, s_))
+ end
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))).
+
+Definition _s2839_ (_s2840_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s2841_ := _s2840_ in
+ (if ((string_startswith _s2841_ "sfence.vma")) then
+ (match (string_drop _s2841_ (projT1 (string_length "sfence.vma"))) with
+ | _s2842_ =>
+ (spc_matches_prefix _s2842_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2843_ _)) =>
+ (match (string_drop _s2842_ _s2843_) with
+ | _s2844_ =>
+ (reg_name_matches_prefix _s2844_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s2845_ _)) =>
+ (match (string_drop _s2844_ _s2845_) with
+ | _s2846_ =>
+ (sep_matches_prefix _s2846_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2847_ _)) =>
+ (match (string_drop _s2846_ _s2847_) with
+ | _s2848_ =>
+ (reg_name_matches_prefix _s2848_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2849_ _)) =>
+ match (string_drop _s2848_ _s2849_) with
+ | s_ => Some ((rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s2835_ (_s2836_ : string)
+: option string :=
+
+ let _s2837_ := _s2836_ in
+ if ((string_startswith _s2837_ "wfi")) then
+ match (string_drop _s2837_ (projT1 (string_length "wfi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2831_ (_s2832_ : string)
+: option string :=
+
+ let _s2833_ := _s2832_ in
+ if ((string_startswith _s2833_ "ebreak")) then
+ match (string_drop _s2833_ (projT1 (string_length "ebreak"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2827_ (_s2828_ : string)
+: option string :=
+
+ let _s2829_ := _s2828_ in
+ if ((string_startswith _s2829_ "sret")) then
+ match (string_drop _s2829_ (projT1 (string_length "sret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2823_ (_s2824_ : string)
+: option string :=
+
+ let _s2825_ := _s2824_ in
+ if ((string_startswith _s2825_ "mret")) then
+ match (string_drop _s2825_ (projT1 (string_length "mret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2819_ (_s2820_ : string)
+: option string :=
+
+ let _s2821_ := _s2820_ in
+ if ((string_startswith _s2821_ "ecall")) then
+ match (string_drop _s2821_ (projT1 (string_length "ecall"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2815_ (_s2816_ : string)
+: option string :=
+
+ let _s2817_ := _s2816_ in
+ if ((string_startswith _s2817_ "fence.i")) then
+ match (string_drop _s2817_ (projT1 (string_length "fence.i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2803_ (_s2804_ : string)
+: M (option ((mword 4 * mword 4 * string))) :=
+
+ let _s2805_ := _s2804_ in
+ (if ((string_startswith _s2805_ "fence.tso")) then
+ (match (string_drop _s2805_ (projT1 (string_length "fence.tso"))) with
+ | _s2806_ =>
+ (spc_matches_prefix _s2806_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2807_ _)) =>
+ (match (string_drop _s2806_ _s2807_) with
+ | _s2808_ =>
+ (fence_bits_matches_prefix _s2808_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s2809_ _)) =>
+ (match (string_drop _s2808_ _s2809_) with
+ | _s2810_ =>
+ (sep_matches_prefix _s2810_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2811_ _)) =>
+ (match (string_drop _s2810_ _s2811_) with
+ | _s2812_ =>
+ (fence_bits_matches_prefix _s2812_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s2813_ _)) =>
+ match (string_drop _s2812_ _s2813_) with
+ | s_ => Some ((pred, succ, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ else returnm (None : option ((mword 4 * mword 4 * string))))
+ : M (option ((mword 4 * mword 4 * string))).
+
+Definition _s2791_ (_s2792_ : string)
+: M (option ((mword 4 * mword 4 * string))) :=
+
+ let _s2793_ := _s2792_ in
+ (if ((string_startswith _s2793_ "fence")) then
+ (match (string_drop _s2793_ (projT1 (string_length "fence"))) with
+ | _s2794_ =>
+ (spc_matches_prefix _s2794_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2795_ _)) =>
+ (match (string_drop _s2794_ _s2795_) with
+ | _s2796_ =>
+ (fence_bits_matches_prefix _s2796_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s2797_ _)) =>
+ (match (string_drop _s2796_ _s2797_) with
+ | _s2798_ =>
+ (sep_matches_prefix _s2798_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2799_ _)) =>
+ (match (string_drop _s2798_ _s2799_) with
+ | _s2800_ =>
+ (fence_bits_matches_prefix _s2800_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s2801_ _)) =>
+ match (string_drop _s2800_ _s2801_) with
+ | s_ => Some ((pred, succ, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ else returnm (None : option ((mword 4 * mword 4 * string))))
+ : M (option ((mword 4 * mword 4 * string))).
+
+Definition _s2774_ (_s2775_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2775_ with
+ | _s2776_ =>
+ (shiftiwop_mnemonic_matches_prefix _s2776_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2777_ _)) =>
+ (match (string_drop _s2776_ _s2777_) with
+ | _s2778_ =>
+ (spc_matches_prefix _s2778_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2779_ _)) =>
+ (match (string_drop _s2778_ _s2779_) with
+ | _s2780_ =>
+ (reg_name_matches_prefix _s2780_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2781_ _)) =>
+ (match (string_drop _s2780_ _s2781_) with
+ | _s2782_ =>
+ (sep_matches_prefix _s2782_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2783_ _)) =>
+ (match (string_drop _s2782_ _s2783_) with
+ | _s2784_ =>
+ (reg_name_matches_prefix _s2784_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2785_ _)) =>
+ (match (string_drop _s2784_ _s2785_) with
+ | _s2786_ =>
+ (sep_matches_prefix _s2786_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2787_ _)) =>
+ match (string_drop _s2786_ _s2787_) with
+ | _s2788_ =>
+ match (hex_bits_5_matches_prefix
+ _s2788_) with
+ | Some ((shamt, existT _ _s2789_ _)) =>
+ match (string_drop _s2788_ _s2789_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2757_ (_s2758_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2758_ with
+ | _s2759_ =>
+ (rtypew_mnemonic_matches_prefix _s2759_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2760_ _)) =>
+ (match (string_drop _s2759_ _s2760_) with
+ | _s2761_ =>
+ (spc_matches_prefix _s2761_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2762_ _)) =>
+ (match (string_drop _s2761_ _s2762_) with
+ | _s2763_ =>
+ (reg_name_matches_prefix _s2763_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2764_ _)) =>
+ (match (string_drop _s2763_ _s2764_) with
+ | _s2765_ =>
+ (sep_matches_prefix _s2765_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2766_ _)) =>
+ (match (string_drop _s2765_ _s2766_) with
+ | _s2767_ =>
+ (reg_name_matches_prefix _s2767_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2768_ _)) =>
+ (match (string_drop _s2767_ _s2768_) with
+ | _s2769_ =>
+ (sep_matches_prefix _s2769_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2770_ _)) =>
+ (match (string_drop _s2769_ _s2770_) with
+ | _s2771_ =>
+ (reg_name_matches_prefix _s2771_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2772_ _)) =>
+ match (string_drop _s2771_
+ _s2772_) with
+ | s_ =>
+ Some ((op, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2740_ (_s2741_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2741_ with
+ | _s2742_ =>
+ (shiftw_mnemonic_matches_prefix _s2742_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2743_ _)) =>
+ (match (string_drop _s2742_ _s2743_) with
+ | _s2744_ =>
+ (spc_matches_prefix _s2744_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2745_ _)) =>
+ (match (string_drop _s2744_ _s2745_) with
+ | _s2746_ =>
+ (reg_name_matches_prefix _s2746_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2747_ _)) =>
+ (match (string_drop _s2746_ _s2747_) with
+ | _s2748_ =>
+ (sep_matches_prefix _s2748_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2749_ _)) =>
+ (match (string_drop _s2748_ _s2749_) with
+ | _s2750_ =>
+ (reg_name_matches_prefix _s2750_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2751_ _)) =>
+ (match (string_drop _s2750_ _s2751_) with
+ | _s2752_ =>
+ (sep_matches_prefix _s2752_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2753_ _)) =>
+ match (string_drop _s2752_ _s2753_) with
+ | _s2754_ =>
+ match (hex_bits_5_matches_prefix
+ _s2754_) with
+ | Some ((shamt, existT _ _s2755_ _)) =>
+ match (string_drop _s2754_ _s2755_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2724_ (_s2725_ : string)
+: M (option ((mword 5 * mword 5 * mword 12 * string))) :=
+
+ let _s2726_ := _s2725_ in
+ (if ((string_startswith _s2726_ "addiw")) then
+ (match (string_drop _s2726_ (projT1 (string_length "addiw"))) with
+ | _s2727_ =>
+ (spc_matches_prefix _s2727_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2728_ _)) =>
+ (match (string_drop _s2727_ _s2728_) with
+ | _s2729_ =>
+ (reg_name_matches_prefix _s2729_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2730_ _)) =>
+ (match (string_drop _s2729_ _s2730_) with
+ | _s2731_ =>
+ (sep_matches_prefix _s2731_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2732_ _)) =>
+ (match (string_drop _s2731_ _s2732_) with
+ | _s2733_ =>
+ (reg_name_matches_prefix _s2733_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2734_ _)) =>
+ (match (string_drop _s2733_ _s2734_) with
+ | _s2735_ =>
+ (sep_matches_prefix _s2735_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2736_ _)) =>
+ match (string_drop _s2735_ _s2736_) with
+ | _s2737_ =>
+ match (hex_bits_12_matches_prefix _s2737_) with
+ | Some ((imm, existT _ _s2738_ _)) =>
+ match (string_drop _s2737_ _s2738_) with
+ | s_ => Some ((rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2696_ (_s2697_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))) :=
+
+ let _s2698_ := _s2697_ in
+ (if ((string_startswith _s2698_ "s")) then
+ (match (string_drop _s2698_ (projT1 (string_length "s"))) with
+ | _s2699_ =>
+ (size_mnemonic_matches_prefix _s2699_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2700_ _)) =>
+ (match (string_drop _s2699_ _s2700_) with
+ | _s2701_ =>
+ (maybe_aq_matches_prefix _s2701_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2702_ _)) =>
+ (match (string_drop _s2701_ _s2702_) with
+ | _s2703_ =>
+ (maybe_rl_matches_prefix _s2703_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2704_ _)) =>
+ (match (string_drop _s2703_ _s2704_) with
+ | _s2705_ =>
+ (spc_matches_prefix _s2705_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2706_ _)) =>
+ (match (string_drop _s2705_ _s2706_) with
+ | _s2707_ =>
+ (reg_name_matches_prefix _s2707_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s2708_ _)) =>
+ (match (string_drop _s2707_ _s2708_) with
+ | _s2709_ =>
+ (sep_matches_prefix _s2709_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2710_ _)) =>
+ (match (string_drop _s2709_ _s2710_) with
+ | _s2711_ =>
+ (match (hex_bits_12_matches_prefix _s2711_) with
+ | Some ((imm, existT _ _s2712_ _)) =>
+ (match (string_drop _s2711_ _s2712_) with
+ | _s2713_ =>
+ (opt_spc_matches_prefix _s2713_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2714_ _)) =>
+ let _s2715_ :=
+ string_drop _s2713_ _s2714_ in
+ (if ((string_startswith
+ _s2715_ "(")) then
+ (match (string_drop _s2715_
+ (projT1
+ (string_length
+ "("))) with
+ | _s2716_ =>
+ (opt_spc_matches_prefix
+ _s2716_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s2717_ _)) =>
+ (match (string_drop
+ _s2716_
+ _s2717_) with
+ | _s2718_ =>
+ (reg_name_matches_prefix
+ _s2718_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s2719_ _)) =>
+ (match (string_drop
+ _s2718_
+ _s2719_) with
+ | _s2720_ =>
+ (opt_spc_matches_prefix
+ _s2720_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s2721_ _)) =>
+ let _s2722_ :=
+ string_drop
+ _s2720_
+ _s2721_ in
+ if
+ ((string_startswith
+ _s2722_
+ ")"))
+ then
+ match (string_drop
+ _s2722_
+ (projT1
+ (string_length
+ ")"))) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rs2, imm, rs1, s_))
+ end
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))).
+
+Definition _s2666_ (_s2667_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))) :=
+
+ let _s2668_ := _s2667_ in
+ (if ((string_startswith _s2668_ "l")) then
+ (match (string_drop _s2668_ (projT1 (string_length "l"))) with
+ | _s2669_ =>
+ (size_mnemonic_matches_prefix _s2669_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2670_ _)) =>
+ (match (string_drop _s2669_ _s2670_) with
+ | _s2671_ =>
+ (maybe_u_matches_prefix _s2671_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s2672_ _)) =>
+ (match (string_drop _s2671_ _s2672_) with
+ | _s2673_ =>
+ (maybe_aq_matches_prefix _s2673_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2674_ _)) =>
+ (match (string_drop _s2673_ _s2674_) with
+ | _s2675_ =>
+ (maybe_rl_matches_prefix _s2675_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2676_ _)) =>
+ (match (string_drop _s2675_ _s2676_) with
+ | _s2677_ =>
+ (spc_matches_prefix _s2677_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2678_ _)) =>
+ (match (string_drop _s2677_ _s2678_) with
+ | _s2679_ =>
+ (reg_name_matches_prefix _s2679_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2680_ _)) =>
+ (match (string_drop _s2679_ _s2680_) with
+ | _s2681_ =>
+ (sep_matches_prefix _s2681_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2682_ _)) =>
+ (match (string_drop _s2681_ _s2682_) with
+ | _s2683_ =>
+ (match (hex_bits_12_matches_prefix
+ _s2683_) with
+ | Some
+ ((imm, existT _ _s2684_ _)) =>
+ (match (string_drop _s2683_
+ _s2684_) with
+ | _s2685_ =>
+ (opt_spc_matches_prefix
+ _s2685_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s2686_ _)) =>
+ let _s2687_ :=
+ string_drop _s2685_
+ _s2686_ in
+ (if ((string_startswith
+ _s2687_ "("))
+ then
+ (match (string_drop
+ _s2687_
+ (projT1
+ (string_length
+ "("))) with
+ | _s2688_ =>
+ (opt_spc_matches_prefix
+ _s2688_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2689_ _)) =>
+ (match (string_drop
+ _s2688_
+ _s2689_) with
+ | _s2690_ =>
+ (reg_name_matches_prefix
+ _s2690_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s2691_ _)) =>
+ (match (string_drop
+ _s2690_
+ _s2691_) with
+ | _s2692_ =>
+ (opt_spc_matches_prefix
+ _s2692_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s2693_ _)) =>
+ let _s2694_ :=
+ string_drop
+ _s2692_
+ _s2693_ in
+ if
+ ((string_startswith
+ _s2694_
+ ")"))
+ then
+ match (string_drop
+ _s2694_
+ (projT1
+ (string_length
+ ")"))) with
+ | s_ =>
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1, s_))
+ end
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))).
+
+Definition _s2649_ (_s2650_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2650_ with
+ | _s2651_ =>
+ (rtype_mnemonic_matches_prefix _s2651_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2652_ _)) =>
+ (match (string_drop _s2651_ _s2652_) with
+ | _s2653_ =>
+ (spc_matches_prefix _s2653_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2654_ _)) =>
+ (match (string_drop _s2653_ _s2654_) with
+ | _s2655_ =>
+ (reg_name_matches_prefix _s2655_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2656_ _)) =>
+ (match (string_drop _s2655_ _s2656_) with
+ | _s2657_ =>
+ (sep_matches_prefix _s2657_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2658_ _)) =>
+ (match (string_drop _s2657_ _s2658_) with
+ | _s2659_ =>
+ (reg_name_matches_prefix _s2659_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2660_ _)) =>
+ (match (string_drop _s2659_ _s2660_) with
+ | _s2661_ =>
+ (sep_matches_prefix _s2661_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2662_ _)) =>
+ (match (string_drop _s2661_ _s2662_) with
+ | _s2663_ =>
+ (reg_name_matches_prefix _s2663_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2664_ _)) =>
+ match (string_drop _s2663_
+ _s2664_) with
+ | s_ =>
+ Some ((op, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2632_ (_s2633_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6 * string))) :=
+
+ (match _s2633_ with
+ | _s2634_ =>
+ (shiftiop_mnemonic_matches_prefix _s2634_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2635_ _)) =>
+ (match (string_drop _s2634_ _s2635_) with
+ | _s2636_ =>
+ (spc_matches_prefix _s2636_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2637_ _)) =>
+ (match (string_drop _s2636_ _s2637_) with
+ | _s2638_ =>
+ (reg_name_matches_prefix _s2638_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2639_ _)) =>
+ (match (string_drop _s2638_ _s2639_) with
+ | _s2640_ =>
+ (sep_matches_prefix _s2640_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2641_ _)) =>
+ (match (string_drop _s2640_ _s2641_) with
+ | _s2642_ =>
+ (reg_name_matches_prefix _s2642_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2643_ _)) =>
+ (match (string_drop _s2642_ _s2643_) with
+ | _s2644_ =>
+ (sep_matches_prefix _s2644_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2645_ _)) =>
+ match (string_drop _s2644_ _s2645_) with
+ | _s2646_ =>
+ match (hex_bits_6_matches_prefix
+ _s2646_) with
+ | Some ((shamt, existT _ _s2647_ _)) =>
+ match (string_drop _s2646_ _s2647_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string))).
+
+Definition _s2615_ (_s2616_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s2616_ with
+ | _s2617_ =>
+ (itype_mnemonic_matches_prefix _s2617_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2618_ _)) =>
+ (match (string_drop _s2617_ _s2618_) with
+ | _s2619_ =>
+ (spc_matches_prefix _s2619_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2620_ _)) =>
+ (match (string_drop _s2619_ _s2620_) with
+ | _s2621_ =>
+ (reg_name_matches_prefix _s2621_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2622_ _)) =>
+ (match (string_drop _s2621_ _s2622_) with
+ | _s2623_ =>
+ (sep_matches_prefix _s2623_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2624_ _)) =>
+ (match (string_drop _s2623_ _s2624_) with
+ | _s2625_ =>
+ (reg_name_matches_prefix _s2625_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2626_ _)) =>
+ (match (string_drop _s2625_ _s2626_) with
+ | _s2627_ =>
+ (sep_matches_prefix _s2627_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2628_ _)) =>
+ match (string_drop _s2627_ _s2628_) with
+ | _s2629_ =>
+ match (hex_bits_12_matches_prefix
+ _s2629_) with
+ | Some ((imm, existT _ _s2630_ _)) =>
+ match (string_drop _s2629_ _s2630_) with
+ | s_ =>
+ Some ((op, rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2598_ (_s2599_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13 * string))) :=
+
+ (match _s2599_ with
+ | _s2600_ =>
+ (btype_mnemonic_matches_prefix _s2600_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2601_ _)) =>
+ (match (string_drop _s2600_ _s2601_) with
+ | _s2602_ =>
+ (spc_matches_prefix _s2602_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2603_ _)) =>
+ (match (string_drop _s2602_ _s2603_) with
+ | _s2604_ =>
+ (reg_name_matches_prefix _s2604_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s2605_ _)) =>
+ (match (string_drop _s2604_ _s2605_) with
+ | _s2606_ =>
+ (sep_matches_prefix _s2606_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2607_ _)) =>
+ (match (string_drop _s2606_ _s2607_) with
+ | _s2608_ =>
+ (reg_name_matches_prefix _s2608_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s2609_ _)) =>
+ (match (string_drop _s2608_ _s2609_) with
+ | _s2610_ =>
+ (sep_matches_prefix _s2610_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2611_ _)) =>
+ match (string_drop _s2610_ _s2611_) with
+ | _s2612_ =>
+ match (hex_bits_13_matches_prefix
+ _s2612_) with
+ | Some ((imm, existT _ _s2613_ _)) =>
+ match (string_drop _s2612_ _s2613_) with
+ | s_ =>
+ Some ((op, rs1, rs2, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string))).
+
+Definition _s2582_ (_s2583_ : string)
+: M (option ((mword 5 * mword 5 * mword 12 * string))) :=
+
+ let _s2584_ := _s2583_ in
+ (if ((string_startswith _s2584_ "jalr")) then
+ (match (string_drop _s2584_ (projT1 (string_length "jalr"))) with
+ | _s2585_ =>
+ (spc_matches_prefix _s2585_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2586_ _)) =>
+ (match (string_drop _s2585_ _s2586_) with
+ | _s2587_ =>
+ (reg_name_matches_prefix _s2587_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2588_ _)) =>
+ (match (string_drop _s2587_ _s2588_) with
+ | _s2589_ =>
+ (sep_matches_prefix _s2589_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2590_ _)) =>
+ (match (string_drop _s2589_ _s2590_) with
+ | _s2591_ =>
+ (reg_name_matches_prefix _s2591_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2592_ _)) =>
+ (match (string_drop _s2591_ _s2592_) with
+ | _s2593_ =>
+ (sep_matches_prefix _s2593_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2594_ _)) =>
+ match (string_drop _s2593_ _s2594_) with
+ | _s2595_ =>
+ match (hex_bits_12_matches_prefix _s2595_) with
+ | Some ((imm, existT _ _s2596_ _)) =>
+ match (string_drop _s2595_ _s2596_) with
+ | s_ => Some ((rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2570_ (_s2571_ : string)
+: M (option ((mword 5 * mword 21 * string))) :=
+
+ let _s2572_ := _s2571_ in
+ (if ((string_startswith _s2572_ "jal")) then
+ (match (string_drop _s2572_ (projT1 (string_length "jal"))) with
+ | _s2573_ =>
+ (spc_matches_prefix _s2573_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2574_ _)) =>
+ (match (string_drop _s2573_ _s2574_) with
+ | _s2575_ =>
+ (reg_name_matches_prefix _s2575_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2576_ _)) =>
+ (match (string_drop _s2575_ _s2576_) with
+ | _s2577_ =>
+ (sep_matches_prefix _s2577_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2578_ _)) =>
+ match (string_drop _s2577_ _s2578_) with
+ | _s2579_ =>
+ match (hex_bits_21_matches_prefix _s2579_) with
+ | Some ((imm, existT _ _s2580_ _)) =>
+ match (string_drop _s2579_ _s2580_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ else returnm (None : option ((mword 5 * mword 21 * string))))
+ : M (option ((mword 5 * mword 21 * string))).
+
+Definition _s2557_ (_s2558_ : string)
+: M (option ((uop * mword 5 * mword 20 * string))) :=
+
+ (match _s2558_ with
+ | _s2559_ =>
+ (utype_mnemonic_matches_prefix _s2559_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2560_ _)) =>
+ (match (string_drop _s2559_ _s2560_) with
+ | _s2561_ =>
+ (spc_matches_prefix _s2561_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2562_ _)) =>
+ (match (string_drop _s2561_ _s2562_) with
+ | _s2563_ =>
+ (reg_name_matches_prefix _s2563_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2564_ _)) =>
+ (match (string_drop _s2563_ _s2564_) with
+ | _s2565_ =>
+ (sep_matches_prefix _s2565_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s2566_ _)) =>
+ match (string_drop _s2565_ _s2566_) with
+ | _s2567_ =>
+ match (hex_bits_20_matches_prefix _s2567_) with
+ | Some ((imm, existT _ _s2568_ _)) =>
+ match (string_drop _s2567_ _s2568_) with
+ | s_ => Some ((op, rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string))).
+
+Definition assembly_matches_prefix (arg_ : string)
+: M (option ((ast * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s2569_ := arg_ in
+ (_s2557_ _s2569_) >>= fun w__0 : option ((uop * mword 5 * mword 20 * string)) =>
+ (if ((match w__0 with | Some ((op, rd, imm, s_)) => true | _ => false end)) then
+ (_s2557_ _s2569_) >>= fun w__1 : option ((uop * mword 5 * mword 20 * string)) =>
+ (match w__1 with
+ | Some ((op, rd, imm, s_)) =>
+ returnm ((Some
+ ((UTYPE
+ ((imm, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2570_ _s2569_) >>= fun w__4 : option ((mword 5 * mword 21 * string)) =>
+ (if ((match w__4 with | Some ((rd, imm, s_)) => true | _ => false end)) then
+ (_s2570_ _s2569_) >>= fun w__5 : option ((mword 5 * mword 21 * string)) =>
+ (match w__5 with
+ | Some ((rd, imm, s_)) =>
+ returnm ((Some
+ ((RISCV_JAL
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2582_ _s2569_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm, s_)) => true | _ => false end)) then
+ (_s2582_ _s2569_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((RISCV_JALR
+ ((imm, rs1, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2598_ _s2569_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13 * string)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm, s_)) => true | _ => false end)) then
+ (_s2598_ _s2569_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13 * string)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm, s_)) =>
+ returnm ((Some
+ ((BTYPE
+ ((imm, rs2, rs1, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2615_ _s2569_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm, s_)) => true | _ => false end))
+ then
+ (_s2615_ _s2569_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((ITYPE
+ ((imm, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2632_ _s2569_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6 * string)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt, s_)) => true | _ => false end))
+ then
+ (_s2632_ _s2569_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6 * string)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTIOP
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2649_ _s2569_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2, s_)) => true | _ => false end))
+ then
+ (_s2649_ _s2569_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((RTYPE
+ ((rs2, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2666_ _s2569_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1, s_)) => true
+ | _ => false
+ end)) then
+ (_s2666_ _s2569_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1, s_)) =>
+ returnm ((Some
+ ((LOAD
+ ((imm, rs1, rd, is_unsigned, size, aq, rl)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2696_ _s2569_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1, s_)) => true
+ | _ => false
+ end)) then
+ (_s2696_ _s2569_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1, s_)) =>
+ returnm ((Some
+ ((STORE
+ ((imm, rs2, rs1, size, aq, rl)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2724_ _s2569_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm, s_)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2724_ _s2569_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((ADDIW
+ ((imm, rs1, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2740_ _s2569_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt, s_)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2740_ _s2569_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTW
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2757_ _s2569_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2, s_)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2757_ _s2569_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((RTYPEW
+ ((rs2, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2774_ _s2569_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt, s_)) => Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2774_ _s2569_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTIWOP
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2791_ _s2569_) >>= fun w__52 : option ((mword 4 * mword 4 * string)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ, s_)) => true
+ | _ => false
+ end)) then
+ (_s2791_ _s2569_) >>= fun w__53 : option ((mword 4 * mword 4 * string)) =>
+ (match w__53 with
+ | Some ((pred, succ, s_)) =>
+ returnm ((Some
+ ((FENCE
+ ((pred, succ)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2803_ _s2569_) >>= fun w__56 : option ((mword 4 * mword 4 * string)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ, s_)) => true
+ | _ => false
+ end)) then
+ (_s2803_ _s2569_) >>= fun w__57 : option ((mword 4 * mword 4 * string)) =>
+ (match w__57 with
+ | Some ((pred, succ, s_)) =>
+ returnm ((Some
+ ((FENCE_TSO
+ ((pred, succ)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2815_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2815_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((FENCEI
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2819_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2819_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((ECALL
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2823_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2823_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((MRET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2827_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2827_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((SRET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2831_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2831_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((EBREAK
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2835_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2835_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((WFI
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2839_ _s2569_) >>= fun w__72 : option ((mword 5 * mword 5 * string)) =>
+ (if ((match w__72 with
+ | Some ((rs1, rs2, s_)) => true
+ | _ => false
+ end)) then
+ (_s2839_ _s2569_) >>= fun w__73 : option ((mword 5 * mword 5 * string)) =>
+ (match w__73 with
+ | Some ((rs1, rs2, s_)) =>
+ returnm ((Some
+ ((SFENCE_VMA
+ ((rs1, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2851_ _s2569_) >>= fun w__76 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) =>
+ (if ((match w__76 with
+ | Some ((size, aq, rl, rd, rs1, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2851_ _s2569_) >>= fun w__77 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) =>
+ (match w__77 with
+ | Some ((size, aq, rl, rd, rs1, s_)) =>
+ returnm ((Some
+ ((LOADRES
+ ((aq, rl, rs1, size, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2869_ _s2569_) >>= fun w__80 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__80 with
+ | Some
+ ((size, aq, rl, rd, rs1, rs2, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2869_ _s2569_) >>= fun w__81 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__81 with
+ | Some ((size, aq, rl, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2891_ _s2569_) >>= fun w__84 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__84 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2891_ _s2569_) >>= fun w__85 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__85 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((AMO
+ ((op, aq, rl, rs2, rs1, width, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if ((match (_s2915_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2915_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((C_NOP
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2919_ _s2569_) >>= fun w__90 : option ((mword 3 * mword 8 * string)) =>
+ (if ((match w__90 with
+ | Some ((rdc, nzimm, s_)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s2919_ _s2569_) >>= fun w__91 : option ((mword 3 * mword 8 * string)) =>
+ (match w__91 with
+ | Some ((rdc, nzimm, s_)) =>
+ returnm ((Some
+ ((C_ADDI4SPN
+ ((rdc, nzimm)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2931_ _s2569_) >>= fun w__94 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__94 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2931_ _s2569_) >>= fun w__95 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__95 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ returnm ((Some
+ ((C_LW
+ ((uimm, rsc, rdc)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2947_ _s2569_) >>= fun w__98 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__98 with
+ | Some
+ ((rdc, rsc, uimm, s_)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2947_ _s2569_) >>= fun w__99 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__99 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ returnm ((Some
+ ((C_LD
+ ((uimm, rsc, rdc)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2963_ _s2569_) >>= fun w__102 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__102 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2963_ _s2569_) >>= fun w__103 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__103 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SW
+ ((uimm, rsc1, rsc2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2979_ _s2569_) >>= fun w__106 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__106 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ Z.eqb 32 64
+ | _ => false
+ end)) then
+ (_s2979_ _s2569_) >>= fun w__107 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__107 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SD
+ ((uimm, rsc1, rsc2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2995_ _s2569_) >>= fun w__110 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__110 with
+ | Some
+ ((rsd, nzi, s_)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s2995_ _s2569_) >>= fun w__111 : option ((mword 5 * mword 6 * string)) =>
+ (match w__111 with
+ | Some
+ ((rsd, nzi, s_)) =>
+ returnm ((Some
+ ((C_ADDI
+ ((nzi, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3007_ _s2569_) >>= fun w__114 : option ((mword 11 * string)) =>
+ (if ((match w__114 with
+ | Some
+ ((imm, s_)) =>
+ Z.eqb 32 32
+ | _ => false
+ end)) then
+ (_s3007_ _s2569_) >>= fun w__115 : option ((mword 11 * string)) =>
+ (match w__115 with
+ | Some ((imm, s_)) =>
+ returnm ((Some
+ ((C_JAL
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3015_ _s2569_) >>= fun w__118 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__118 with
+ | Some
+ ((rsd, imm, s_)) =>
+ Z.eqb 32
+ 64
+ | _ => false
+ end)) then
+ (_s3015_ _s2569_) >>= fun w__119 : option ((mword 5 * mword 6 * string)) =>
+ (match w__119 with
+ | Some
+ ((rsd, imm, s_)) =>
+ returnm ((Some
+ ((C_ADDIW
+ ((imm, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3027_ _s2569_) >>= fun w__122 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__122 with
+ | Some
+ ((rd, imm, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s3027_
+ _s2569_) >>= fun w__123 : option ((mword 5 * mword 6 * string)) =>
+ (match w__123 with
+ | Some
+ ((rd, imm, s_)) =>
+ returnm ((Some
+ ((C_LI
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3039_
+ _s2569_) >>= fun w__126 : option ((mword 6 * string)) =>
+ (if ((match w__126 with
+ | Some
+ ((imm, s_)) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3039_
+ _s2569_) >>= fun w__127 : option ((mword 6 * string)) =>
+ (match w__127 with
+ | Some
+ ((imm, s_)) =>
+ returnm ((Some
+ ((C_ADDI16SP
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3047_
+ _s2569_) >>= fun w__130 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__130 with
+ | Some
+ ((rd, imm, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3047_
+ _s2569_) >>= fun w__131 : option ((mword 5 * mword 6 * string)) =>
+ (match w__131 with
+ | Some
+ ((rd, imm, s_)) =>
+ returnm ((Some
+ ((C_LUI
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3059_
+ _s2569_) >>= fun w__134 : option ((mword 3 * mword 6 * string)) =>
+ (if ((match w__134 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3059_
+ _s2569_) >>= fun w__135 : option ((mword 3 * mword 6 * string)) =>
+ (match w__135 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SRLI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3071_
+ _s2569_) >>= fun w__138 : option ((mword 3 * mword 6 * string)) =>
+ (if ((match w__138 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3071_
+ _s2569_) >>= fun w__139 : option ((mword 3 * mword 6 * string)) =>
+ (match w__139 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SRAI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3083_
+ _s2569_) >>= fun w__142 : option ((mword 3 * mword 6 * string)) =>
+ (if
+ ((match w__142 with
+ | Some
+ ((rsd, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3083_
+ _s2569_) >>= fun w__143 : option ((mword 3 * mword 6 * string)) =>
+ (match w__143 with
+ | Some
+ ((rsd, imm, s_)) =>
+ returnm ((Some
+ ((C_ANDI
+ ((imm, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3095_
+ _s2569_) >>= fun w__146 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__146 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3095_
+ _s2569_) >>= fun w__147 : option ((mword 3 * mword 3 * string)) =>
+ (match w__147 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_SUB
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3107_
+ _s2569_) >>= fun w__150 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__150 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3107_
+ _s2569_) >>= fun w__151 : option ((mword 3 * mword 3 * string)) =>
+ (match w__151 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_XOR
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3119_
+ _s2569_) >>= fun w__154 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__154 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3119_
+ _s2569_) >>= fun w__155 : option ((mword 3 * mword 3 * string)) =>
+ (match w__155 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_OR
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3131_
+ _s2569_) >>= fun w__158 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__158 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3131_
+ _s2569_) >>= fun w__159 : option ((mword 3 * mword 3 * string)) =>
+ (match w__159 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_AND
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3143_
+ _s2569_) >>= fun w__162 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__162 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3143_
+ _s2569_) >>= fun w__163 : option ((mword 3 * mword 3 * string)) =>
+ (match w__163 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_SUBW
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3155_
+ _s2569_) >>= fun w__166 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__166 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3155_
+ _s2569_) >>= fun w__167 : option ((mword 3 * mword 3 * string)) =>
+ (match w__167 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_ADDW
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3167_
+ _s2569_) >>= fun w__170 : option ((mword 11 * string)) =>
+ (if
+ ((match w__170 with
+ | Some
+ ((imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3167_
+ _s2569_) >>= fun w__171 : option ((mword 11 * string)) =>
+ (match w__171 with
+ | Some
+ ((imm, s_)) =>
+ returnm ((Some
+ ((C_J
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3175_
+ _s2569_) >>= fun w__174 : option ((mword 3 * mword 8 * string)) =>
+ (if
+ ((match w__174 with
+ | Some
+ ((rs, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3175_
+ _s2569_) >>= fun w__175 : option ((mword 3 * mword 8 * string)) =>
+ (match w__175 with
+ | Some
+ ((rs, imm, s_)) =>
+ returnm ((Some
+ ((C_BEQZ
+ ((imm, rs)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3187_
+ _s2569_) >>= fun w__178 : option ((mword 3 * mword 8 * string)) =>
+ (if
+ ((match w__178 with
+ | Some
+ ((rs, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3187_
+ _s2569_) >>= fun w__179 : option ((mword 3 * mword 8 * string)) =>
+ (match w__179 with
+ | Some
+ ((rs, imm, s_)) =>
+ returnm ((Some
+ ((C_BNEZ
+ ((imm, rs)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3199_
+ _s2569_) >>= fun w__182 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__182 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3199_
+ _s2569_) >>= fun w__183 : option ((mword 5 * mword 6 * string)) =>
+ (match w__183 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SLLI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3211_
+ _s2569_) >>= fun w__186 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__186 with
+ | Some
+ ((rd, uimm, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3211_
+ _s2569_) >>= fun w__187 : option ((mword 5 * mword 6 * string)) =>
+ (match w__187 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_LWSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3223_
+ _s2569_) >>= fun w__190 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__190 with
+ | Some
+ ((rd, uimm, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 32
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s3223_
+ _s2569_) >>= fun w__191 : option ((mword 5 * mword 6 * string)) =>
+ (match w__191 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_LDSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3235_
+ _s2569_) >>= fun w__194 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__194 with
+ | Some
+ ((rd, uimm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3235_
+ _s2569_) >>= fun w__195 : option ((mword 5 * mword 6 * string)) =>
+ (match w__195 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_SWSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3247_
+ _s2569_) >>= fun w__198 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__198 with
+ | Some
+ ((rs2, uimm, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3247_
+ _s2569_) >>= fun w__199 : option ((mword 5 * mword 6 * string)) =>
+ (match w__199 with
+ | Some
+ ((rs2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SDSP
+ ((uimm, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3259_
+ _s2569_) >>= fun w__202 : option ((mword 5 * string)) =>
+ (if
+ ((match w__202 with
+ | Some
+ ((rs1, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3259_
+ _s2569_) >>= fun w__203 : option ((mword 5 * string)) =>
+ (match w__203 with
+ | Some
+ ((rs1, s_)) =>
+ returnm ((Some
+ ((C_JR
+ (rs1), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3267_
+ _s2569_) >>= fun w__206 : option ((mword 5 * string)) =>
+ (if
+ ((match w__206 with
+ | Some
+ ((rs1, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3267_
+ _s2569_) >>= fun w__207 : option ((mword 5 * string)) =>
+ (match w__207 with
+ | Some
+ ((rs1, s_)) =>
+ returnm ((Some
+ ((C_JALR
+ (rs1), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3275_
+ _s2569_) >>= fun w__210 : option ((mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__210 with
+ | Some
+ ((rd, rs2, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3275_
+ _s2569_) >>= fun w__211 : option ((mword 5 * mword 5 * string)) =>
+ (match w__211 with
+ | Some
+ ((rd, rs2, s_)) =>
+ returnm ((Some
+ ((C_MV
+ ((rd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if
+ ((match (_s3287_
+ _s2569_) with
+ | Some
+ (s_) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (match (_s3287_
+ _s2569_) with
+ | Some
+ (s_) =>
+ returnm ((Some
+ ((C_EBREAK
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3291_
+ _s2569_) >>= fun w__216 : option ((mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3291_
+ _s2569_) >>= fun w__217 : option ((mword 5 * mword 5 * string)) =>
+ (match w__217 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_ADD
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3303_
+ _s2569_) >>= fun w__220 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3303_
+ _s2569_) >>= fun w__221 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__221 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3320_
+ _s2569_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3320_
+ _s2569_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((DIV
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3338_
+ _s2569_) >>= fun w__228 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3338_
+ _s2569_) >>= fun w__229 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__229 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((REM
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3356_
+ _s2569_) >>= fun w__232 : option ((mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3356_
+ _s2569_) >>= fun w__233 : option ((mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__233 with
+ | Some
+ ((rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((MULW
+ ((rs2, rs1, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3372_
+ _s2569_) >>= fun w__236 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__236 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3372_
+ _s2569_) >>= fun w__237 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__237 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((DIVW
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3391_
+ _s2569_) >>= fun w__240 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__240 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 32
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3391_
+ _s2569_) >>= fun w__241 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__241 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((REMW
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3410_
+ _s2569_) >>= fun w__244 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if
+ ((match w__244 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3410_
+ _s2569_) >>= fun w__245 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__245 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ returnm ((Some
+ ((CSR
+ ((csr, rs1, rd, true, op)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3428_
+ _s2569_) >>= fun w__248 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if
+ ((match w__248 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3428_
+ _s2569_) >>= fun w__249 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__249 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ returnm ((Some
+ ((CSR
+ ((csr, rs1, rd, false, op)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if
+ ((match (_s3445_
+ _s2569_) with
+ | Some
+ (s_) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (match (_s3445_
+ _s2569_) with
+ | Some
+ (s_) =>
+ returnm ((Some
+ ((URET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3449_
+ _s2569_) >>= fun w__254 : option ((mword 32 * string)) =>
+ (if
+ ((match w__254 with
+ | Some
+ ((s, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3449_
+ _s2569_) >>= fun w__255 : option ((mword 32 * string)) =>
+ (match w__255 with
+ | Some
+ ((s, s_)) =>
+ returnm ((Some
+ ((ILLEGAL
+ (s), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3457_
+ _s2569_) >>= fun w__258 : option ((mword 16 * string)) =>
+ (if
+ ((match w__258 with
+ | Some
+ ((s, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3457_
+ _s2569_) >>= fun w__259 : option ((mword 16 * string)) =>
+ (match w__259 with
+ | Some
+ ((s, s_)) =>
+ returnm ((Some
+ ((C_ILLEGAL
+ (s), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ returnm (None
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))).
+
+Definition print_insn (insn : ast) : M (string) := (assembly_forwards insn) : M (string).
+
+Definition decode (bv : mword 32) : M (ast) := (encdec_backwards bv) : M (ast).
+
+Definition decodeCompressed (bv : mword 16) : ast := encdec_compressed_backwards bv.
+
+
+End Content.
diff --git a/prover_snapshots/coq/RV32/riscv_extras.v b/prover_snapshots/coq/RV32/riscv_extras.v
new file mode 100644
index 0000000..84f6761
--- /dev/null
+++ b/prover_snapshots/coq/RV32/riscv_extras.v
@@ -0,0 +1,155 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import String.
+Require Import List.
+Import List.ListNotations.
+
+Axiom real : Type.
+
+Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_rw tt).
+Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_rw tt).
+Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_r tt).
+Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_w tt).
+Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_w tt).
+Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_rw tt).
+Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_r tt).
+Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_w tt).
+Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_r tt).
+Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_tso tt).
+Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_i tt).
+(*
+val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+*)
+Definition MEMea {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addrsize addr size.
+Definition MEMea_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addrsize addr size.
+Definition MEMea_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addrsize addr size.
+Definition MEMea_conditional {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addrsize addr size.
+Definition MEMea_conditional_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addrsize addr size.
+Definition MEMea_conditional_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e
+ := write_mem_ea Write_RISCV_conditional_strong_release addrsize addr size.
+
+(*
+val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+*)
+
+Definition MEMr {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_plain addrsize addr size.
+Definition MEMr_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_acquire addrsize addr size.
+Definition MEMr_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_strong_acquire addrsize addr size.
+Definition MEMr_reserved {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved addrsize addr size.
+Definition MEMr_reserved_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_acquire addrsize addr size.
+Definition MEMr_reserved_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_strong_acquire addrsize addr size.
+
+(*
+val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+*)
+
+Definition MEMw {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_plain addrsize addr size v.
+Definition MEMw_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_release addrsize addr size v.
+Definition MEMw_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_strong_release addrsize addr size v.
+Definition MEMw_conditional {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional addrsize addr size v.
+Definition MEMw_conditional_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_release addrsize addr size v.
+Definition MEMw_conditional_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_strong_release addrsize addr size v.
+
+Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftl v (int_of_mword false n).
+
+Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftr v (int_of_mword false n).
+
+Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a :=
+ arith_shiftr v (int_of_mword false n).
+
+(* Use constants for undefined values for now *)
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) : Z := 0.
+(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*)
+
+Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)).
+
+(*val get_time_ns : unit -> integer*)
+Definition get_time_ns (_:unit) : Z := 0.
+(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*)
+
+Definition eq_bit (x : bitU) (y : bitU) : bool :=
+ match x, y with
+ | B0, B0 => true
+ | B1, B1 => true
+ | BU, BU => true
+ | _,_ => false
+ end.
+
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+apply existT with (x := ZEuclid.modulo m n).
+constructor.
+destruct H.
+assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
+(* Override the more general version *)
+
+Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
+Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
+
+Axiom sys_enable_writable_misa : unit -> bool.
+Axiom sys_enable_rvc : unit -> bool.
+
+(* The constraint solver can do this itself, but a Coq bug puts
+ anonymous_subproof into the term instead of an actual subproof. *)
+Lemma n_leading_spaces_fact {w__0} :
+ w__0 >= 0 -> exists ex17629_ : Z, 1 + w__0 = 1 + ex17629_ /\ 0 <= ex17629_.
+intro.
+exists w__0.
+omega.
+Qed.
+Hint Resolve n_leading_spaces_fact : sail.
diff --git a/prover_snapshots/coq/RV32/riscv_types.v b/prover_snapshots/coq/RV32/riscv_types.v
new file mode 100644
index 0000000..79dfb2a
--- /dev/null
+++ b/prover_snapshots/coq/RV32/riscv_types.v
@@ -0,0 +1,14073 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Import ListNotations.
+Definition bits (n : Z) : Type := mword n.
+
+Inductive regfp :=
+ | RFull : string -> regfp
+ | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RField : (string * string) -> regfp.
+Arguments regfp : clear implicits.
+
+Definition regfps : Type := list regfp.
+
+Inductive niafp :=
+ | NIAFP_successor : unit -> niafp
+ | NIAFP_concrete_address : bits 64 -> niafp
+ | NIAFP_indirect_address : unit -> niafp.
+Arguments niafp : clear implicits.
+
+Definition niafps : Type := list niafp.
+
+Inductive diafp :=
+ | DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp.
+Arguments diafp : clear implicits.
+
+Inductive a64_barrier_domain := A64_FullShare | A64_InnerShare | A64_OuterShare | A64_NonShare.
+Scheme Equality for a64_barrier_domain.
+Instance Decidable_eq_a64_barrier_domain :
+forall (x y : a64_barrier_domain), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_domain_eq_dec.
+
+Inductive a64_barrier_type := A64_barrier_all | A64_barrier_LD | A64_barrier_ST.
+Scheme Equality for a64_barrier_type.
+Instance Decidable_eq_a64_barrier_type :
+forall (x y : a64_barrier_type), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_type_eq_dec.
+
+Inductive cache_op_kind :=
+ Cache_op_D_IVAC
+ | Cache_op_D_ISW
+ | Cache_op_D_CSW
+ | Cache_op_D_CISW
+ | Cache_op_D_ZVA
+ | Cache_op_D_CVAC
+ | Cache_op_D_CVAU
+ | Cache_op_D_CIVAC
+ | Cache_op_I_IALLUIS
+ | Cache_op_I_IALLU
+ | Cache_op_I_IVAU.
+Scheme Equality for cache_op_kind.
+Instance Decidable_eq_cache_op_kind :
+forall (x y : cache_op_kind), Decidable (x = y) :=
+Decidable_eq_from_dec cache_op_kind_eq_dec.
+
+Definition xlen : Z := 32.
+Hint Unfold xlen : sail.
+
+Definition xlen_bytes : Z := 4.
+Hint Unfold xlen_bytes : sail.
+
+Definition xlenbits : Type := bits 32.
+
+Definition mem_meta : Type := unit.
+
+Definition max_mem_access : Z := 16.
+Hint Unfold max_mem_access : sail.
+
+Definition half : Type := bits 16.
+
+Definition word : Type := bits 32.
+
+Definition regidx : Type := bits 5.
+
+Definition cregidx : Type := bits 3.
+
+Definition csreg : Type := bits 12.
+
+Definition regno (n : Z)`{ArithFact (0 <= n /\ n < 32)} : Type := Z.
+
+Definition opcode : Type := bits 7.
+
+Definition imm12 : Type := bits 12.
+
+Definition imm20 : Type := bits 20.
+
+Definition amo : Type := bits 1.
+
+Inductive Architecture := RV32 | RV64 | RV128.
+Scheme Equality for Architecture.
+Instance Decidable_eq_Architecture :
+forall (x y : Architecture), Decidable (x = y) :=
+Decidable_eq_from_dec Architecture_eq_dec.
+
+Definition arch_xlen : Type := bits 2.
+
+Definition priv_level : Type := bits 2.
+
+Inductive Privilege := User | Supervisor | Machine.
+Scheme Equality for Privilege.
+Instance Decidable_eq_Privilege :
+forall (x y : Privilege), Decidable (x = y) :=
+Decidable_eq_from_dec Privilege_eq_dec.
+
+Inductive amoop := AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU.
+Scheme Equality for amoop.
+Instance Decidable_eq_amoop :
+forall (x y : amoop), Decidable (x = y) :=
+Decidable_eq_from_dec amoop_eq_dec.
+
+Inductive bop := RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU.
+Scheme Equality for bop.
+Instance Decidable_eq_bop :
+forall (x y : bop), Decidable (x = y) :=
+Decidable_eq_from_dec bop_eq_dec.
+
+Inductive csrop := CSRRW | CSRRS | CSRRC.
+Scheme Equality for csrop.
+Instance Decidable_eq_csrop :
+forall (x y : csrop), Decidable (x = y) :=
+Decidable_eq_from_dec csrop_eq_dec.
+
+Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI.
+Scheme Equality for iop.
+Instance Decidable_eq_iop :
+forall (x y : iop), Decidable (x = y) :=
+Decidable_eq_from_dec iop_eq_dec.
+
+Inductive rop :=
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND.
+Scheme Equality for rop.
+Instance Decidable_eq_rop :
+forall (x y : rop), Decidable (x = y) :=
+Decidable_eq_from_dec rop_eq_dec.
+
+Inductive ropw := RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW.
+Scheme Equality for ropw.
+Instance Decidable_eq_ropw :
+forall (x y : ropw), Decidable (x = y) :=
+Decidable_eq_from_dec ropw_eq_dec.
+
+Inductive sop := RISCV_SLLI | RISCV_SRLI | RISCV_SRAI.
+Scheme Equality for sop.
+Instance Decidable_eq_sop :
+forall (x y : sop), Decidable (x = y) :=
+Decidable_eq_from_dec sop_eq_dec.
+
+Inductive sopw := RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW.
+Scheme Equality for sopw.
+Instance Decidable_eq_sopw :
+forall (x y : sopw), Decidable (x = y) :=
+Decidable_eq_from_dec sopw_eq_dec.
+
+Inductive uop := RISCV_LUI | RISCV_AUIPC.
+Scheme Equality for uop.
+Instance Decidable_eq_uop :
+forall (x y : uop), Decidable (x = y) :=
+Decidable_eq_from_dec uop_eq_dec.
+
+Inductive word_width := BYTE | HALF | WORD | DOUBLE.
+Scheme Equality for word_width.
+Instance Decidable_eq_word_width :
+forall (x y : word_width), Decidable (x = y) :=
+Decidable_eq_from_dec word_width_eq_dec.
+
+Inductive ast :=
+ | UTYPE : (bits 20 * regidx * uop) -> ast
+ | RISCV_JAL : (bits 21 * regidx) -> ast
+ | RISCV_JALR : (bits 12 * regidx * regidx) -> ast
+ | BTYPE : (bits 13 * regidx * regidx * bop) -> ast
+ | ITYPE : (bits 12 * regidx * regidx * iop) -> ast
+ | SHIFTIOP : (bits 6 * regidx * regidx * sop) -> ast
+ | RTYPE : (regidx * regidx * regidx * rop) -> ast
+ | LOAD : (bits 12 * regidx * regidx * bool * word_width * bool * bool) -> ast
+ | STORE : (bits 12 * regidx * regidx * word_width * bool * bool) -> ast
+ | ADDIW : (bits 12 * regidx * regidx) -> ast
+ | SHIFTW : (bits 5 * regidx * regidx * sop) -> ast
+ | RTYPEW : (regidx * regidx * regidx * ropw) -> ast
+ | SHIFTIWOP : (bits 5 * regidx * regidx * sopw) -> ast
+ | FENCE : (bits 4 * bits 4) -> ast
+ | FENCE_TSO : (bits 4 * bits 4) -> ast
+ | FENCEI : unit -> ast
+ | ECALL : unit -> ast
+ | MRET : unit -> ast
+ | SRET : unit -> ast
+ | EBREAK : unit -> ast
+ | WFI : unit -> ast
+ | SFENCE_VMA : (regidx * regidx) -> ast
+ | LOADRES : (bool * bool * regidx * word_width * regidx) -> ast
+ | STORECON : (bool * bool * regidx * regidx * word_width * regidx) -> ast
+ | AMO : (amoop * bool * bool * regidx * regidx * word_width * regidx) -> ast
+ | C_NOP : unit -> ast
+ | C_ADDI4SPN : (cregidx * bits 8) -> ast
+ | C_LW : (bits 5 * cregidx * cregidx) -> ast
+ | C_LD : (bits 5 * cregidx * cregidx) -> ast
+ | C_SW : (bits 5 * cregidx * cregidx) -> ast
+ | C_SD : (bits 5 * cregidx * cregidx) -> ast
+ | C_ADDI : (bits 6 * regidx) -> ast
+ | C_JAL : bits 11 -> ast
+ | C_ADDIW : (bits 6 * regidx) -> ast
+ | C_LI : (bits 6 * regidx) -> ast
+ | C_ADDI16SP : bits 6 -> ast
+ | C_LUI : (bits 6 * regidx) -> ast
+ | C_SRLI : (bits 6 * cregidx) -> ast
+ | C_SRAI : (bits 6 * cregidx) -> ast
+ | C_ANDI : (bits 6 * cregidx) -> ast
+ | C_SUB : (cregidx * cregidx) -> ast
+ | C_XOR : (cregidx * cregidx) -> ast
+ | C_OR : (cregidx * cregidx) -> ast
+ | C_AND : (cregidx * cregidx) -> ast
+ | C_SUBW : (cregidx * cregidx) -> ast
+ | C_ADDW : (cregidx * cregidx) -> ast
+ | C_J : bits 11 -> ast
+ | C_BEQZ : (bits 8 * cregidx) -> ast
+ | C_BNEZ : (bits 8 * cregidx) -> ast
+ | C_SLLI : (bits 6 * regidx) -> ast
+ | C_LWSP : (bits 6 * regidx) -> ast
+ | C_LDSP : (bits 6 * regidx) -> ast
+ | C_SWSP : (bits 6 * regidx) -> ast
+ | C_SDSP : (bits 6 * regidx) -> ast
+ | C_JR : regidx -> ast
+ | C_JALR : regidx -> ast
+ | C_MV : (regidx * regidx) -> ast
+ | C_EBREAK : unit -> ast
+ | C_ADD : (regidx * regidx) -> ast
+ | MUL : (regidx * regidx * regidx * bool * bool * bool) -> ast
+ | DIV : (regidx * regidx * regidx * bool) -> ast
+ | REM : (regidx * regidx * regidx * bool) -> ast
+ | MULW : (regidx * regidx * regidx) -> ast
+ | DIVW : (regidx * regidx * regidx * bool) -> ast
+ | REMW : (regidx * regidx * regidx * bool) -> ast
+ | CSR : (bits 12 * regidx * regidx * bool * csrop) -> ast
+ | URET : unit -> ast
+ | ILLEGAL : word -> ast
+ | C_ILLEGAL : half -> ast.
+Arguments ast : clear implicits.
+
+Inductive Retired := RETIRE_SUCCESS | RETIRE_FAIL.
+Scheme Equality for Retired.
+Instance Decidable_eq_Retired :
+forall (x y : Retired), Decidable (x = y) :=
+Decidable_eq_from_dec Retired_eq_dec.
+
+Inductive AccessType := Read | Write | ReadWrite | Execute.
+Scheme Equality for AccessType.
+Instance Decidable_eq_AccessType :
+forall (x y : AccessType), Decidable (x = y) :=
+Decidable_eq_from_dec AccessType_eq_dec.
+
+Definition exc_code : Type := bits 8.
+
+Inductive InterruptType :=
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External.
+Scheme Equality for InterruptType.
+Instance Decidable_eq_InterruptType :
+forall (x y : InterruptType), Decidable (x = y) :=
+Decidable_eq_from_dec InterruptType_eq_dec.
+
+Inductive ExceptionType :=
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI.
+Scheme Equality for ExceptionType.
+Instance Decidable_eq_ExceptionType :
+forall (x y : ExceptionType), Decidable (x = y) :=
+Decidable_eq_from_dec ExceptionType_eq_dec.
+
+Inductive exception :=
+ | Error_not_implemented : string -> exception | Error_internal_error : unit -> exception.
+Arguments exception : clear implicits.
+
+Definition tv_mode : Type := bits 2.
+
+Inductive TrapVectorMode := TV_Direct | TV_Vector | TV_Reserved.
+Scheme Equality for TrapVectorMode.
+Instance Decidable_eq_TrapVectorMode :
+forall (x y : TrapVectorMode), Decidable (x = y) :=
+Decidable_eq_from_dec TrapVectorMode_eq_dec.
+
+Definition ext_status : Type := bits 2.
+
+Inductive ExtStatus := Off | Initial | Clean | Dirty.
+Scheme Equality for ExtStatus.
+Instance Decidable_eq_ExtStatus :
+forall (x y : ExtStatus), Decidable (x = y) :=
+Decidable_eq_from_dec ExtStatus_eq_dec.
+
+Definition satp_mode : Type := bits 4.
+
+Inductive SATPMode := Sbare | Sv32 | Sv39 | Sv48.
+Scheme Equality for SATPMode.
+Instance Decidable_eq_SATPMode :
+forall (x y : SATPMode), Decidable (x = y) :=
+Decidable_eq_from_dec SATPMode_eq_dec.
+
+Definition csrRW : Type := bits 2.
+
+Definition regtype : Type := xlenbits.
+
+Record Misa := { Misa_Misa_chunk_0 : mword 32; }.
+Arguments Misa : clear implicits.
+Notation "{[ r 'with' 'Misa_Misa_chunk_0' := e ]}" := {| Misa_Misa_chunk_0 := e |} (only parsing).
+
+Record SV48_PTE := { SV48_PTE_SV48_PTE_chunk_0 : mword 64; }.
+Arguments SV48_PTE : clear implicits.
+Notation "{[ r 'with' 'SV48_PTE_SV48_PTE_chunk_0' := e ]}" :=
+ {| SV48_PTE_SV48_PTE_chunk_0 := e |} (only parsing).
+
+Record PTE_Bits := { PTE_Bits_PTE_Bits_chunk_0 : mword 8; }.
+Arguments PTE_Bits : clear implicits.
+Notation "{[ r 'with' 'PTE_Bits_PTE_Bits_chunk_0' := e ]}" :=
+ {| PTE_Bits_PTE_Bits_chunk_0 := e |} (only parsing).
+
+Record Pmpcfg_ent := { Pmpcfg_ent_Pmpcfg_ent_chunk_0 : mword 8; }.
+Arguments Pmpcfg_ent : clear implicits.
+Notation "{[ r 'with' 'Pmpcfg_ent_Pmpcfg_ent_chunk_0' := e ]}" :=
+ {| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := e |} (only parsing).
+
+Record Mstatus := { Mstatus_Mstatus_chunk_0 : mword 32; }.
+Arguments Mstatus : clear implicits.
+Notation "{[ r 'with' 'Mstatus_Mstatus_chunk_0' := e ]}" :=
+ {| Mstatus_Mstatus_chunk_0 := e |} (only parsing).
+
+Record Sstatus := { Sstatus_Sstatus_chunk_0 : mword 32; }.
+Arguments Sstatus : clear implicits.
+Notation "{[ r 'with' 'Sstatus_Sstatus_chunk_0' := e ]}" :=
+ {| Sstatus_Sstatus_chunk_0 := e |} (only parsing).
+
+Record Ustatus := { Ustatus_Ustatus_chunk_0 : mword 32; }.
+Arguments Ustatus : clear implicits.
+Notation "{[ r 'with' 'Ustatus_Ustatus_chunk_0' := e ]}" :=
+ {| Ustatus_Ustatus_chunk_0 := e |} (only parsing).
+
+Record Minterrupts := { Minterrupts_Minterrupts_chunk_0 : mword 32; }.
+Arguments Minterrupts : clear implicits.
+Notation "{[ r 'with' 'Minterrupts_Minterrupts_chunk_0' := e ]}" :=
+ {| Minterrupts_Minterrupts_chunk_0 := e |} (only parsing).
+
+Record Sinterrupts := { Sinterrupts_Sinterrupts_chunk_0 : mword 32; }.
+Arguments Sinterrupts : clear implicits.
+Notation "{[ r 'with' 'Sinterrupts_Sinterrupts_chunk_0' := e ]}" :=
+ {| Sinterrupts_Sinterrupts_chunk_0 := e |} (only parsing).
+
+Record Uinterrupts := { Uinterrupts_Uinterrupts_chunk_0 : mword 32; }.
+Arguments Uinterrupts : clear implicits.
+Notation "{[ r 'with' 'Uinterrupts_Uinterrupts_chunk_0' := e ]}" :=
+ {| Uinterrupts_Uinterrupts_chunk_0 := e |} (only parsing).
+
+Record Medeleg := { Medeleg_Medeleg_chunk_0 : mword 32; }.
+Arguments Medeleg : clear implicits.
+Notation "{[ r 'with' 'Medeleg_Medeleg_chunk_0' := e ]}" :=
+ {| Medeleg_Medeleg_chunk_0 := e |} (only parsing).
+
+Record Sedeleg := { Sedeleg_Sedeleg_chunk_0 : mword 32; }.
+Arguments Sedeleg : clear implicits.
+Notation "{[ r 'with' 'Sedeleg_Sedeleg_chunk_0' := e ]}" :=
+ {| Sedeleg_Sedeleg_chunk_0 := e |} (only parsing).
+
+Record Mtvec := { Mtvec_Mtvec_chunk_0 : mword 32; }.
+Arguments Mtvec : clear implicits.
+Notation "{[ r 'with' 'Mtvec_Mtvec_chunk_0' := e ]}" :=
+ {| Mtvec_Mtvec_chunk_0 := e |} (only parsing).
+
+Record Satp32 := { Satp32_Satp32_chunk_0 : mword 32; }.
+Arguments Satp32 : clear implicits.
+Notation "{[ r 'with' 'Satp32_Satp32_chunk_0' := e ]}" :=
+ {| Satp32_Satp32_chunk_0 := e |} (only parsing).
+
+Record Mcause := { Mcause_Mcause_chunk_0 : mword 32; }.
+Arguments Mcause : clear implicits.
+Notation "{[ r 'with' 'Mcause_Mcause_chunk_0' := e ]}" :=
+ {| Mcause_Mcause_chunk_0 := e |} (only parsing).
+
+Record Counteren := { Counteren_Counteren_chunk_0 : mword 32; }.
+Arguments Counteren : clear implicits.
+Notation "{[ r 'with' 'Counteren_Counteren_chunk_0' := e ]}" :=
+ {| Counteren_Counteren_chunk_0 := e |} (only parsing).
+
+Record Satp64 := { Satp64_Satp64_chunk_0 : mword 64; }.
+Arguments Satp64 : clear implicits.
+Notation "{[ r 'with' 'Satp64_Satp64_chunk_0' := e ]}" :=
+ {| Satp64_Satp64_chunk_0 := e |} (only parsing).
+
+Inductive PmpAddrMatchType := OFF | TOR | NA4 | NAPOT.
+Scheme Equality for PmpAddrMatchType.
+Instance Decidable_eq_PmpAddrMatchType :
+forall (x y : PmpAddrMatchType), Decidable (x = y) :=
+Decidable_eq_from_dec PmpAddrMatchType_eq_dec.
+
+Definition pmp_addr_range : Type := option ((xlenbits * xlenbits)).
+
+Inductive pmpAddrMatch := PMP_NoMatch | PMP_PartialMatch | PMP_Match.
+Scheme Equality for pmpAddrMatch.
+Instance Decidable_eq_pmpAddrMatch :
+forall (x y : pmpAddrMatch), Decidable (x = y) :=
+Decidable_eq_from_dec pmpAddrMatch_eq_dec.
+
+Inductive pmpMatch := PMP_Success | PMP_Continue | PMP_Fail.
+Scheme Equality for pmpMatch.
+Instance Decidable_eq_pmpMatch :
+forall (x y : pmpMatch), Decidable (x = y) :=
+Decidable_eq_from_dec pmpMatch_eq_dec.
+
+Inductive Ext_FetchAddr_Check {a : Type} :=
+ | Ext_FetchAddr_OK : xlenbits -> Ext_FetchAddr_Check
+ | Ext_FetchAddr_Error : a -> Ext_FetchAddr_Check.
+Arguments Ext_FetchAddr_Check : clear implicits.
+
+Inductive Ext_ControlAddr_Check {a : Type} :=
+ | Ext_ControlAddr_OK : xlenbits -> Ext_ControlAddr_Check
+ | Ext_ControlAddr_Error : a -> Ext_ControlAddr_Check.
+Arguments Ext_ControlAddr_Check : clear implicits.
+
+Inductive Ext_DataAddr_Check {a : Type} :=
+ | Ext_DataAddr_OK : xlenbits -> Ext_DataAddr_Check | Ext_DataAddr_Error : a -> Ext_DataAddr_Check.
+Arguments Ext_DataAddr_Check : clear implicits.
+
+Definition ext_fetch_addr_error : Type := unit.
+
+Definition ext_control_addr_error : Type := unit.
+
+Definition ext_data_addr_error : Type := unit.
+
+Definition ext_exception : Type := unit.
+
+Record sync_exception :=
+ { sync_exception_trap : ExceptionType;
+ sync_exception_excinfo : option xlenbits;
+ sync_exception_ext : option ext_exception; }.
+Arguments sync_exception : clear implicits.
+Notation "{[ r 'with' 'sync_exception_trap' := e ]}" := {|
+ sync_exception_trap := e;
+ sync_exception_excinfo := sync_exception_excinfo r;
+ sync_exception_ext := sync_exception_ext r
+ |}.
+Notation "{[ r 'with' 'sync_exception_excinfo' := e ]}" := {|
+ sync_exception_excinfo := e;
+ sync_exception_trap := sync_exception_trap r;
+ sync_exception_ext := sync_exception_ext r
+ |}.
+Notation "{[ r 'with' 'sync_exception_ext' := e ]}" := {|
+ sync_exception_ext := e;
+ sync_exception_trap := sync_exception_trap r;
+ sync_exception_excinfo := sync_exception_excinfo r
+ |}.
+
+Inductive interrupt_set :=
+ | Ints_Pending : xlenbits -> interrupt_set
+ | Ints_Delegated : xlenbits -> interrupt_set
+ | Ints_Empty : unit -> interrupt_set.
+Arguments interrupt_set : clear implicits.
+
+Inductive ctl_result :=
+ | CTL_TRAP : sync_exception -> ctl_result
+ | CTL_SRET : unit -> ctl_result
+ | CTL_MRET : unit -> ctl_result
+ | CTL_URET : unit -> ctl_result.
+Arguments ctl_result : clear implicits.
+
+Inductive MemoryOpResult {a : Type} :=
+ | MemValue : a -> MemoryOpResult | MemException : ExceptionType -> MemoryOpResult.
+Arguments MemoryOpResult : clear implicits.
+
+Record htif_cmd := { htif_cmd_htif_cmd_chunk_0 : mword 64; }.
+Arguments htif_cmd : clear implicits.
+Notation "{[ r 'with' 'htif_cmd_htif_cmd_chunk_0' := e ]}" :=
+ {| htif_cmd_htif_cmd_chunk_0 := e |} (only parsing).
+
+Definition pteAttribs : Type := bits 8.
+
+Inductive PTW_Error :=
+ PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update.
+Scheme Equality for PTW_Error.
+Instance Decidable_eq_PTW_Error :
+forall (x y : PTW_Error), Decidable (x = y) :=
+Decidable_eq_from_dec PTW_Error_eq_dec.
+
+Definition vaddr32 : Type := bits 32.
+
+Definition paddr32 : Type := bits 34.
+
+Definition pte32 : Type := bits 32.
+
+Definition asid32 : Type := bits 9.
+
+Record SV32_Vaddr := { SV32_Vaddr_SV32_Vaddr_chunk_0 : mword 32; }.
+Arguments SV32_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV32_Vaddr_SV32_Vaddr_chunk_0' := e ]}" :=
+ {| SV32_Vaddr_SV32_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV48_Vaddr := { SV48_Vaddr_SV48_Vaddr_chunk_0 : mword 48; }.
+Arguments SV48_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV48_Vaddr_SV48_Vaddr_chunk_0' := e ]}" :=
+ {| SV48_Vaddr_SV48_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV48_Paddr := { SV48_Paddr_SV48_Paddr_chunk_0 : mword 56; }.
+Arguments SV48_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV48_Paddr_SV48_Paddr_chunk_0' := e ]}" :=
+ {| SV48_Paddr_SV48_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV32_Paddr := { SV32_Paddr_SV32_Paddr_chunk_0 : mword 34; }.
+Arguments SV32_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV32_Paddr_SV32_Paddr_chunk_0' := e ]}" :=
+ {| SV32_Paddr_SV32_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV32_PTE := { SV32_PTE_SV32_PTE_chunk_0 : mword 32; }.
+Arguments SV32_PTE : clear implicits.
+Notation "{[ r 'with' 'SV32_PTE_SV32_PTE_chunk_0' := e ]}" :=
+ {| SV32_PTE_SV32_PTE_chunk_0 := e |} (only parsing).
+
+Definition paddr64 : Type := bits 56.
+
+Definition pte64 : Type := bits 64.
+
+Definition asid64 : Type := bits 16.
+
+Definition vaddr39 : Type := bits 39.
+
+Record SV39_Vaddr := { SV39_Vaddr_SV39_Vaddr_chunk_0 : mword 39; }.
+Arguments SV39_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV39_Vaddr_SV39_Vaddr_chunk_0' := e ]}" :=
+ {| SV39_Vaddr_SV39_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV39_Paddr := { SV39_Paddr_SV39_Paddr_chunk_0 : mword 56; }.
+Arguments SV39_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV39_Paddr_SV39_Paddr_chunk_0' := e ]}" :=
+ {| SV39_Paddr_SV39_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV39_PTE := { SV39_PTE_SV39_PTE_chunk_0 : mword 64; }.
+Arguments SV39_PTE : clear implicits.
+Notation "{[ r 'with' 'SV39_PTE_SV39_PTE_chunk_0' := e ]}" :=
+ {| SV39_PTE_SV39_PTE_chunk_0 := e |} (only parsing).
+
+Definition vaddr48 : Type := bits 48.
+
+Definition pte48 : Type := bits 64.
+
+Inductive PTW_Result {paddr : Type} {pte : Type} :=
+ | PTW_Success : (paddr * pte * paddr * {n : Z & ArithFact (n >= 0)} * bool) -> PTW_Result
+ | PTW_Failure : PTW_Error -> PTW_Result.
+Arguments PTW_Result : clear implicits.
+
+Inductive TR_Result {paddr : Type} {failure : Type} :=
+ | TR_Address : paddr -> TR_Result | TR_Failure : failure -> TR_Result.
+Arguments TR_Result : clear implicits.
+
+Record TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z} :=
+ { TLB_Entry_asid : bits asidlen;
+ TLB_Entry_global : bool;
+ TLB_Entry_vAddr : bits valen;
+ TLB_Entry_pAddr : bits palen;
+ TLB_Entry_vMatchMask : bits valen;
+ TLB_Entry_vAddrMask : bits valen;
+ TLB_Entry_pte : bits ptelen;
+ TLB_Entry_pteAddr : bits palen;
+ TLB_Entry_age : bits 64; }.
+Arguments TLB_Entry : clear implicits.
+Notation "{[ r 'with' 'TLB_Entry_asid' := e ]}" := {|
+ TLB_Entry_asid := e;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_global' := e ]}" := {|
+ TLB_Entry_global := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vAddr' := e ]}" := {|
+ TLB_Entry_vAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pAddr' := e ]}" := {|
+ TLB_Entry_pAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vMatchMask' := e ]}" := {|
+ TLB_Entry_vMatchMask := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vAddrMask' := e ]}" := {|
+ TLB_Entry_vAddrMask := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pte' := e ]}" := {|
+ TLB_Entry_pte := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pteAddr' := e ]}" := {|
+ TLB_Entry_pteAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_age' := e ]}" := {|
+ TLB_Entry_age := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r
+ |}.
+
+Definition TLB32_Entry : Type := TLB_Entry 9 32 34 32.
+
+Inductive register_value :=
+ | Regval_vector : (Z * bool * list register_value) -> register_value
+ | Regval_list : list register_value -> register_value
+ | Regval_option : option register_value -> register_value
+ | Regval_Counteren : Counteren -> register_value
+ | Regval_Mcause : Mcause -> register_value
+ | Regval_Medeleg : Medeleg -> register_value
+ | Regval_Minterrupts : Minterrupts -> register_value
+ | Regval_Misa : Misa -> register_value
+ | Regval_Mstatus : Mstatus -> register_value
+ | Regval_Mtvec : Mtvec -> register_value
+ | Regval_Pmpcfg_ent : Pmpcfg_ent -> register_value
+ | Regval_Privilege : Privilege -> register_value
+ | Regval_Sedeleg : Sedeleg -> register_value
+ | Regval_Sinterrupts : Sinterrupts -> register_value
+ | Regval_TLB_Entry_9_32_34_32 : TLB_Entry 9 32 34 32 -> register_value
+ | Regval_bit : bitU -> register_value
+ | Regval_bitvector_32_dec : mword 32 -> register_value
+ | Regval_bitvector_64_dec : mword 64 -> register_value
+ | Regval_bool : bool -> register_value.
+Arguments register_value : clear implicits.
+
+Record regstate :=
+ { satp : mword 32;
+ tlb32 : option (TLB_Entry 9 32 34 32);
+ htif_exit_code : mword 64;
+ htif_done : bool;
+ htif_tohost : mword 64;
+ mtimecmp : mword 64;
+ utval : mword 32;
+ ucause : Mcause;
+ uepc : mword 32;
+ uscratch : mword 32;
+ utvec : Mtvec;
+ pmpaddr15 : mword 32;
+ pmpaddr14 : mword 32;
+ pmpaddr13 : mword 32;
+ pmpaddr12 : mword 32;
+ pmpaddr11 : mword 32;
+ pmpaddr10 : mword 32;
+ pmpaddr9 : mword 32;
+ pmpaddr8 : mword 32;
+ pmpaddr7 : mword 32;
+ pmpaddr6 : mword 32;
+ pmpaddr5 : mword 32;
+ pmpaddr4 : mword 32;
+ pmpaddr3 : mword 32;
+ pmpaddr2 : mword 32;
+ pmpaddr1 : mword 32;
+ pmpaddr0 : mword 32;
+ pmp15cfg : Pmpcfg_ent;
+ pmp14cfg : Pmpcfg_ent;
+ pmp13cfg : Pmpcfg_ent;
+ pmp12cfg : Pmpcfg_ent;
+ pmp11cfg : Pmpcfg_ent;
+ pmp10cfg : Pmpcfg_ent;
+ pmp9cfg : Pmpcfg_ent;
+ pmp8cfg : Pmpcfg_ent;
+ pmp7cfg : Pmpcfg_ent;
+ pmp6cfg : Pmpcfg_ent;
+ pmp5cfg : Pmpcfg_ent;
+ pmp4cfg : Pmpcfg_ent;
+ pmp3cfg : Pmpcfg_ent;
+ pmp2cfg : Pmpcfg_ent;
+ pmp1cfg : Pmpcfg_ent;
+ pmp0cfg : Pmpcfg_ent;
+ tselect : mword 32;
+ stval : mword 32;
+ scause : Mcause;
+ sepc : mword 32;
+ sscratch : mword 32;
+ stvec : Mtvec;
+ sideleg : Sinterrupts;
+ sedeleg : Sedeleg;
+ mhartid : mword 32;
+ marchid : mword 32;
+ mimpid : mword 32;
+ mvendorid : mword 32;
+ minstret_written : bool;
+ minstret : mword 64;
+ mtime : mword 64;
+ mcycle : mword 64;
+ scounteren : Counteren;
+ mcounteren : Counteren;
+ mscratch : mword 32;
+ mtval : mword 32;
+ mepc : mword 32;
+ mcause : Mcause;
+ mtvec : Mtvec;
+ medeleg : Medeleg;
+ mideleg : Minterrupts;
+ mie : Minterrupts;
+ mip : Minterrupts;
+ mstatus : Mstatus;
+ misa : Misa;
+ cur_inst : mword 32;
+ cur_privilege : Privilege;
+ x31 : mword 32;
+ x30 : mword 32;
+ x29 : mword 32;
+ x28 : mword 32;
+ x27 : mword 32;
+ x26 : mword 32;
+ x25 : mword 32;
+ x24 : mword 32;
+ x23 : mword 32;
+ x22 : mword 32;
+ x21 : mword 32;
+ x20 : mword 32;
+ x19 : mword 32;
+ x18 : mword 32;
+ x17 : mword 32;
+ x16 : mword 32;
+ x15 : mword 32;
+ x14 : mword 32;
+ x13 : mword 32;
+ x12 : mword 32;
+ x11 : mword 32;
+ x10 : mword 32;
+ x9 : mword 32;
+ x8 : mword 32;
+ x7 : mword 32;
+ x6 : mword 32;
+ x5 : mword 32;
+ x4 : mword 32;
+ x3 : mword 32;
+ x2 : mword 32;
+ x1 : mword 32;
+ Xs : vec (mword 32) 32;
+ instbits : mword 32;
+ nextPC : mword 32;
+ PC : mword 32; }.
+Arguments regstate : clear implicits.
+Notation "{[ r 'with' 'satp' := e ]}" := {|
+ satp := e;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'tlb32' := e ]}" := {|
+ tlb32 := e;
+ satp := satp r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_exit_code' := e ]}" := {|
+ htif_exit_code := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_done' := e ]}" := {|
+ htif_done := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_tohost' := e ]}" := {|
+ htif_tohost := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtimecmp' := e ]}" := {|
+ mtimecmp := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'utval' := e ]}" := {|
+ utval := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'ucause' := e ]}" := {|
+ ucause := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'uepc' := e ]}" := {|
+ uepc := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'uscratch' := e ]}" := {|
+ uscratch := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'utvec' := e ]}" := {|
+ utvec := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr15' := e ]}" := {|
+ pmpaddr15 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr14' := e ]}" := {|
+ pmpaddr14 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr13' := e ]}" := {|
+ pmpaddr13 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr12' := e ]}" := {|
+ pmpaddr12 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr11' := e ]}" := {|
+ pmpaddr11 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr10' := e ]}" := {|
+ pmpaddr10 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr9' := e ]}" := {|
+ pmpaddr9 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr8' := e ]}" := {|
+ pmpaddr8 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr7' := e ]}" := {|
+ pmpaddr7 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr6' := e ]}" := {|
+ pmpaddr6 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr5' := e ]}" := {|
+ pmpaddr5 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr4' := e ]}" := {|
+ pmpaddr4 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr3' := e ]}" := {|
+ pmpaddr3 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr2' := e ]}" := {|
+ pmpaddr2 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr1' := e ]}" := {|
+ pmpaddr1 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr0' := e ]}" := {|
+ pmpaddr0 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp15cfg' := e ]}" := {|
+ pmp15cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp14cfg' := e ]}" := {|
+ pmp14cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp13cfg' := e ]}" := {|
+ pmp13cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp12cfg' := e ]}" := {|
+ pmp12cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp11cfg' := e ]}" := {|
+ pmp11cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp10cfg' := e ]}" := {|
+ pmp10cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp9cfg' := e ]}" := {|
+ pmp9cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp8cfg' := e ]}" := {|
+ pmp8cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp7cfg' := e ]}" := {|
+ pmp7cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp6cfg' := e ]}" := {|
+ pmp6cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp5cfg' := e ]}" := {|
+ pmp5cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp4cfg' := e ]}" := {|
+ pmp4cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp3cfg' := e ]}" := {|
+ pmp3cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp2cfg' := e ]}" := {|
+ pmp2cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp1cfg' := e ]}" := {|
+ pmp1cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp0cfg' := e ]}" := {|
+ pmp0cfg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'tselect' := e ]}" := {|
+ tselect := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'stval' := e ]}" := {|
+ stval := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'scause' := e ]}" := {|
+ scause := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sepc' := e ]}" := {|
+ sepc := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sscratch' := e ]}" := {|
+ sscratch := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'stvec' := e ]}" := {|
+ stvec := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sideleg' := e ]}" := {|
+ sideleg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sedeleg' := e ]}" := {|
+ sedeleg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mhartid' := e ]}" := {|
+ mhartid := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'marchid' := e ]}" := {|
+ marchid := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mimpid' := e ]}" := {|
+ mimpid := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mvendorid' := e ]}" := {|
+ mvendorid := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'minstret_written' := e ]}" := {|
+ minstret_written := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'minstret' := e ]}" := {|
+ minstret := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtime' := e ]}" := {|
+ mtime := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcycle' := e ]}" := {|
+ mcycle := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'scounteren' := e ]}" := {|
+ scounteren := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcounteren' := e ]}" := {|
+ mcounteren := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mscratch' := e ]}" := {|
+ mscratch := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtval' := e ]}" := {|
+ mtval := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mepc' := e ]}" := {|
+ mepc := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcause' := e ]}" := {|
+ mcause := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtvec' := e ]}" := {|
+ mtvec := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'medeleg' := e ]}" := {|
+ medeleg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mideleg' := e ]}" := {|
+ mideleg := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mie' := e ]}" := {|
+ mie := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mip' := e ]}" := {|
+ mip := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mstatus' := e ]}" := {|
+ mstatus := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'misa' := e ]}" := {|
+ misa := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'cur_inst' := e ]}" := {|
+ cur_inst := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'cur_privilege' := e ]}" := {|
+ cur_privilege := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x31' := e ]}" := {|
+ x31 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x30' := e ]}" := {|
+ x30 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x29' := e ]}" := {|
+ x29 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x28' := e ]}" := {|
+ x28 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x27' := e ]}" := {|
+ x27 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x26' := e ]}" := {|
+ x26 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x25' := e ]}" := {|
+ x25 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x24' := e ]}" := {|
+ x24 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x23' := e ]}" := {|
+ x23 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x22' := e ]}" := {|
+ x22 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x21' := e ]}" := {|
+ x21 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x20' := e ]}" := {|
+ x20 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x19' := e ]}" := {|
+ x19 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x18' := e ]}" := {|
+ x18 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x17' := e ]}" := {|
+ x17 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x16' := e ]}" := {|
+ x16 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x15' := e ]}" := {|
+ x15 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x14' := e ]}" := {|
+ x14 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x13' := e ]}" := {|
+ x13 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x12' := e ]}" := {|
+ x12 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x11' := e ]}" := {|
+ x11 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x10' := e ]}" := {|
+ x10 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x9' := e ]}" := {|
+ x9 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x8' := e ]}" := {|
+ x8 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x7' := e ]}" := {|
+ x7 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x6' := e ]}" := {|
+ x6 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x5' := e ]}" := {|
+ x5 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x4' := e ]}" := {|
+ x4 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x3' := e ]}" := {|
+ x3 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x2' := e ]}" := {|
+ x2 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x1' := e ]}" := {|
+ x1 := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'Xs' := e ]}" := {|
+ Xs := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'instbits' := e ]}" := {|
+ instbits := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'nextPC' := e ]}" := {|
+ nextPC := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'PC' := e ]}" := {|
+ PC := e;
+ satp := satp r;
+ tlb32 := tlb32 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r
+ |}.
+
+
+
+Definition Counteren_of_regval (merge_var : register_value)
+: option Counteren :=
+
+ match merge_var with | Regval_Counteren (v) => Some (v) | _ => None end.
+
+Definition regval_of_Counteren (v : Counteren) : register_value := Regval_Counteren (v).
+
+Definition Mcause_of_regval (merge_var : register_value)
+: option Mcause :=
+
+ match merge_var with | Regval_Mcause (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mcause (v : Mcause) : register_value := Regval_Mcause (v).
+
+Definition Medeleg_of_regval (merge_var : register_value)
+: option Medeleg :=
+
+ match merge_var with | Regval_Medeleg (v) => Some (v) | _ => None end.
+
+Definition regval_of_Medeleg (v : Medeleg) : register_value := Regval_Medeleg (v).
+
+Definition Minterrupts_of_regval (merge_var : register_value)
+: option Minterrupts :=
+
+ match merge_var with | Regval_Minterrupts (v) => Some (v) | _ => None end.
+
+Definition regval_of_Minterrupts (v : Minterrupts) : register_value := Regval_Minterrupts (v).
+
+Definition Misa_of_regval (merge_var : register_value)
+: option Misa :=
+
+ match merge_var with | Regval_Misa (v) => Some (v) | _ => None end.
+
+Definition regval_of_Misa (v : Misa) : register_value := Regval_Misa (v).
+
+Definition Mstatus_of_regval (merge_var : register_value)
+: option Mstatus :=
+
+ match merge_var with | Regval_Mstatus (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mstatus (v : Mstatus) : register_value := Regval_Mstatus (v).
+
+Definition Mtvec_of_regval (merge_var : register_value)
+: option Mtvec :=
+
+ match merge_var with | Regval_Mtvec (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mtvec (v : Mtvec) : register_value := Regval_Mtvec (v).
+
+Definition Pmpcfg_ent_of_regval (merge_var : register_value)
+: option Pmpcfg_ent :=
+
+ match merge_var with | Regval_Pmpcfg_ent (v) => Some (v) | _ => None end.
+
+Definition regval_of_Pmpcfg_ent (v : Pmpcfg_ent) : register_value := Regval_Pmpcfg_ent (v).
+
+Definition Privilege_of_regval (merge_var : register_value)
+: option Privilege :=
+
+ match merge_var with | Regval_Privilege (v) => Some (v) | _ => None end.
+
+Definition regval_of_Privilege (v : Privilege) : register_value := Regval_Privilege (v).
+
+Definition Sedeleg_of_regval (merge_var : register_value)
+: option Sedeleg :=
+
+ match merge_var with | Regval_Sedeleg (v) => Some (v) | _ => None end.
+
+Definition regval_of_Sedeleg (v : Sedeleg) : register_value := Regval_Sedeleg (v).
+
+Definition Sinterrupts_of_regval (merge_var : register_value)
+: option Sinterrupts :=
+
+ match merge_var with | Regval_Sinterrupts (v) => Some (v) | _ => None end.
+
+Definition regval_of_Sinterrupts (v : Sinterrupts) : register_value := Regval_Sinterrupts (v).
+
+Definition TLB_Entry_9_32_34_32_of_regval (merge_var : register_value)
+: option (TLB_Entry 9 32 34 32) :=
+
+ match merge_var with | Regval_TLB_Entry_9_32_34_32 (v) => Some (v) | _ => None end.
+
+Definition regval_of_TLB_Entry_9_32_34_32 (v : TLB_Entry 9 32 34 32)
+: register_value :=
+
+ Regval_TLB_Entry_9_32_34_32
+ (v).
+
+Definition bit_of_regval (merge_var : register_value)
+: option bitU :=
+
+ match merge_var with | Regval_bit (v) => Some (v) | _ => None end.
+
+Definition regval_of_bit (v : bitU) : register_value := Regval_bit (v).
+
+Definition bitvector_32_dec_of_regval (merge_var : register_value)
+: option (mword 32) :=
+
+ match merge_var with | Regval_bitvector_32_dec (v) => Some (v) | _ => None end.
+
+Definition regval_of_bitvector_32_dec (v : mword 32)
+: register_value :=
+
+ Regval_bitvector_32_dec
+ (v).
+
+Definition bitvector_64_dec_of_regval (merge_var : register_value)
+: option (mword 64) :=
+
+ match merge_var with | Regval_bitvector_64_dec (v) => Some (v) | _ => None end.
+
+Definition regval_of_bitvector_64_dec (v : mword 64)
+: register_value :=
+
+ Regval_bitvector_64_dec
+ (v).
+
+Definition bool_of_regval (merge_var : register_value)
+: option bool :=
+
+ match merge_var with | Regval_bool (v) => Some (v) | _ => None end.
+
+Definition regval_of_bool (v : bool) : register_value := Regval_bool (v).
+
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with
+ | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None
+ | _ => None
+end.
+
+Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with
+ | Regval_list v => just_list (List.map of_regval v)
+ | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with
+ | Regval_option v => option_map of_regval v
+ | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition satp_ref := {|
+ name := "satp";
+ read_from := (fun s => s.(satp));
+ write_to := (fun v s => ({[ s with satp := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition tlb32_ref := {|
+ name := "tlb32";
+ read_from := (fun s => s.(tlb32));
+ write_to := (fun v s => ({[ s with tlb32 := v ]}));
+ of_regval := (fun v => option_of_regval (fun v => TLB_Entry_9_32_34_32_of_regval v) v);
+ regval_of := (fun v => regval_of_option (fun v => regval_of_TLB_Entry_9_32_34_32 v) v) |}.
+
+Definition htif_exit_code_ref := {|
+ name := "htif_exit_code";
+ read_from := (fun s => s.(htif_exit_code));
+ write_to := (fun v s => ({[ s with htif_exit_code := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition htif_done_ref := {|
+ name := "htif_done";
+ read_from := (fun s => s.(htif_done));
+ write_to := (fun v s => ({[ s with htif_done := v ]}));
+ of_regval := (fun v => bool_of_regval v);
+ regval_of := (fun v => regval_of_bool v) |}.
+
+Definition htif_tohost_ref := {|
+ name := "htif_tohost";
+ read_from := (fun s => s.(htif_tohost));
+ write_to := (fun v s => ({[ s with htif_tohost := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mtimecmp_ref := {|
+ name := "mtimecmp";
+ read_from := (fun s => s.(mtimecmp));
+ write_to := (fun v s => ({[ s with mtimecmp := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition utval_ref := {|
+ name := "utval";
+ read_from := (fun s => s.(utval));
+ write_to := (fun v s => ({[ s with utval := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition ucause_ref := {|
+ name := "ucause";
+ read_from := (fun s => s.(ucause));
+ write_to := (fun v s => ({[ s with ucause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition uepc_ref := {|
+ name := "uepc";
+ read_from := (fun s => s.(uepc));
+ write_to := (fun v s => ({[ s with uepc := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition uscratch_ref := {|
+ name := "uscratch";
+ read_from := (fun s => s.(uscratch));
+ write_to := (fun v s => ({[ s with uscratch := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition utvec_ref := {|
+ name := "utvec";
+ read_from := (fun s => s.(utvec));
+ write_to := (fun v s => ({[ s with utvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition pmpaddr15_ref := {|
+ name := "pmpaddr15";
+ read_from := (fun s => s.(pmpaddr15));
+ write_to := (fun v s => ({[ s with pmpaddr15 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr14_ref := {|
+ name := "pmpaddr14";
+ read_from := (fun s => s.(pmpaddr14));
+ write_to := (fun v s => ({[ s with pmpaddr14 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr13_ref := {|
+ name := "pmpaddr13";
+ read_from := (fun s => s.(pmpaddr13));
+ write_to := (fun v s => ({[ s with pmpaddr13 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr12_ref := {|
+ name := "pmpaddr12";
+ read_from := (fun s => s.(pmpaddr12));
+ write_to := (fun v s => ({[ s with pmpaddr12 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr11_ref := {|
+ name := "pmpaddr11";
+ read_from := (fun s => s.(pmpaddr11));
+ write_to := (fun v s => ({[ s with pmpaddr11 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr10_ref := {|
+ name := "pmpaddr10";
+ read_from := (fun s => s.(pmpaddr10));
+ write_to := (fun v s => ({[ s with pmpaddr10 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr9_ref := {|
+ name := "pmpaddr9";
+ read_from := (fun s => s.(pmpaddr9));
+ write_to := (fun v s => ({[ s with pmpaddr9 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr8_ref := {|
+ name := "pmpaddr8";
+ read_from := (fun s => s.(pmpaddr8));
+ write_to := (fun v s => ({[ s with pmpaddr8 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr7_ref := {|
+ name := "pmpaddr7";
+ read_from := (fun s => s.(pmpaddr7));
+ write_to := (fun v s => ({[ s with pmpaddr7 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr6_ref := {|
+ name := "pmpaddr6";
+ read_from := (fun s => s.(pmpaddr6));
+ write_to := (fun v s => ({[ s with pmpaddr6 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr5_ref := {|
+ name := "pmpaddr5";
+ read_from := (fun s => s.(pmpaddr5));
+ write_to := (fun v s => ({[ s with pmpaddr5 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr4_ref := {|
+ name := "pmpaddr4";
+ read_from := (fun s => s.(pmpaddr4));
+ write_to := (fun v s => ({[ s with pmpaddr4 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr3_ref := {|
+ name := "pmpaddr3";
+ read_from := (fun s => s.(pmpaddr3));
+ write_to := (fun v s => ({[ s with pmpaddr3 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr2_ref := {|
+ name := "pmpaddr2";
+ read_from := (fun s => s.(pmpaddr2));
+ write_to := (fun v s => ({[ s with pmpaddr2 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr1_ref := {|
+ name := "pmpaddr1";
+ read_from := (fun s => s.(pmpaddr1));
+ write_to := (fun v s => ({[ s with pmpaddr1 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmpaddr0_ref := {|
+ name := "pmpaddr0";
+ read_from := (fun s => s.(pmpaddr0));
+ write_to := (fun v s => ({[ s with pmpaddr0 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition pmp15cfg_ref := {|
+ name := "pmp15cfg";
+ read_from := (fun s => s.(pmp15cfg));
+ write_to := (fun v s => ({[ s with pmp15cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp14cfg_ref := {|
+ name := "pmp14cfg";
+ read_from := (fun s => s.(pmp14cfg));
+ write_to := (fun v s => ({[ s with pmp14cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp13cfg_ref := {|
+ name := "pmp13cfg";
+ read_from := (fun s => s.(pmp13cfg));
+ write_to := (fun v s => ({[ s with pmp13cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp12cfg_ref := {|
+ name := "pmp12cfg";
+ read_from := (fun s => s.(pmp12cfg));
+ write_to := (fun v s => ({[ s with pmp12cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp11cfg_ref := {|
+ name := "pmp11cfg";
+ read_from := (fun s => s.(pmp11cfg));
+ write_to := (fun v s => ({[ s with pmp11cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp10cfg_ref := {|
+ name := "pmp10cfg";
+ read_from := (fun s => s.(pmp10cfg));
+ write_to := (fun v s => ({[ s with pmp10cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp9cfg_ref := {|
+ name := "pmp9cfg";
+ read_from := (fun s => s.(pmp9cfg));
+ write_to := (fun v s => ({[ s with pmp9cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp8cfg_ref := {|
+ name := "pmp8cfg";
+ read_from := (fun s => s.(pmp8cfg));
+ write_to := (fun v s => ({[ s with pmp8cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp7cfg_ref := {|
+ name := "pmp7cfg";
+ read_from := (fun s => s.(pmp7cfg));
+ write_to := (fun v s => ({[ s with pmp7cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp6cfg_ref := {|
+ name := "pmp6cfg";
+ read_from := (fun s => s.(pmp6cfg));
+ write_to := (fun v s => ({[ s with pmp6cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp5cfg_ref := {|
+ name := "pmp5cfg";
+ read_from := (fun s => s.(pmp5cfg));
+ write_to := (fun v s => ({[ s with pmp5cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp4cfg_ref := {|
+ name := "pmp4cfg";
+ read_from := (fun s => s.(pmp4cfg));
+ write_to := (fun v s => ({[ s with pmp4cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp3cfg_ref := {|
+ name := "pmp3cfg";
+ read_from := (fun s => s.(pmp3cfg));
+ write_to := (fun v s => ({[ s with pmp3cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp2cfg_ref := {|
+ name := "pmp2cfg";
+ read_from := (fun s => s.(pmp2cfg));
+ write_to := (fun v s => ({[ s with pmp2cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp1cfg_ref := {|
+ name := "pmp1cfg";
+ read_from := (fun s => s.(pmp1cfg));
+ write_to := (fun v s => ({[ s with pmp1cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp0cfg_ref := {|
+ name := "pmp0cfg";
+ read_from := (fun s => s.(pmp0cfg));
+ write_to := (fun v s => ({[ s with pmp0cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition tselect_ref := {|
+ name := "tselect";
+ read_from := (fun s => s.(tselect));
+ write_to := (fun v s => ({[ s with tselect := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition stval_ref := {|
+ name := "stval";
+ read_from := (fun s => s.(stval));
+ write_to := (fun v s => ({[ s with stval := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition scause_ref := {|
+ name := "scause";
+ read_from := (fun s => s.(scause));
+ write_to := (fun v s => ({[ s with scause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition sepc_ref := {|
+ name := "sepc";
+ read_from := (fun s => s.(sepc));
+ write_to := (fun v s => ({[ s with sepc := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition sscratch_ref := {|
+ name := "sscratch";
+ read_from := (fun s => s.(sscratch));
+ write_to := (fun v s => ({[ s with sscratch := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition stvec_ref := {|
+ name := "stvec";
+ read_from := (fun s => s.(stvec));
+ write_to := (fun v s => ({[ s with stvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition sideleg_ref := {|
+ name := "sideleg";
+ read_from := (fun s => s.(sideleg));
+ write_to := (fun v s => ({[ s with sideleg := v ]}));
+ of_regval := (fun v => Sinterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Sinterrupts v) |}.
+
+Definition sedeleg_ref := {|
+ name := "sedeleg";
+ read_from := (fun s => s.(sedeleg));
+ write_to := (fun v s => ({[ s with sedeleg := v ]}));
+ of_regval := (fun v => Sedeleg_of_regval v);
+ regval_of := (fun v => regval_of_Sedeleg v) |}.
+
+Definition mhartid_ref := {|
+ name := "mhartid";
+ read_from := (fun s => s.(mhartid));
+ write_to := (fun v s => ({[ s with mhartid := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition marchid_ref := {|
+ name := "marchid";
+ read_from := (fun s => s.(marchid));
+ write_to := (fun v s => ({[ s with marchid := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition mimpid_ref := {|
+ name := "mimpid";
+ read_from := (fun s => s.(mimpid));
+ write_to := (fun v s => ({[ s with mimpid := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition mvendorid_ref := {|
+ name := "mvendorid";
+ read_from := (fun s => s.(mvendorid));
+ write_to := (fun v s => ({[ s with mvendorid := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition minstret_written_ref := {|
+ name := "minstret_written";
+ read_from := (fun s => s.(minstret_written));
+ write_to := (fun v s => ({[ s with minstret_written := v ]}));
+ of_regval := (fun v => bool_of_regval v);
+ regval_of := (fun v => regval_of_bool v) |}.
+
+Definition minstret_ref := {|
+ name := "minstret";
+ read_from := (fun s => s.(minstret));
+ write_to := (fun v s => ({[ s with minstret := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mtime_ref := {|
+ name := "mtime";
+ read_from := (fun s => s.(mtime));
+ write_to := (fun v s => ({[ s with mtime := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mcycle_ref := {|
+ name := "mcycle";
+ read_from := (fun s => s.(mcycle));
+ write_to := (fun v s => ({[ s with mcycle := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition scounteren_ref := {|
+ name := "scounteren";
+ read_from := (fun s => s.(scounteren));
+ write_to := (fun v s => ({[ s with scounteren := v ]}));
+ of_regval := (fun v => Counteren_of_regval v);
+ regval_of := (fun v => regval_of_Counteren v) |}.
+
+Definition mcounteren_ref := {|
+ name := "mcounteren";
+ read_from := (fun s => s.(mcounteren));
+ write_to := (fun v s => ({[ s with mcounteren := v ]}));
+ of_regval := (fun v => Counteren_of_regval v);
+ regval_of := (fun v => regval_of_Counteren v) |}.
+
+Definition mscratch_ref := {|
+ name := "mscratch";
+ read_from := (fun s => s.(mscratch));
+ write_to := (fun v s => ({[ s with mscratch := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition mtval_ref := {|
+ name := "mtval";
+ read_from := (fun s => s.(mtval));
+ write_to := (fun v s => ({[ s with mtval := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition mepc_ref := {|
+ name := "mepc";
+ read_from := (fun s => s.(mepc));
+ write_to := (fun v s => ({[ s with mepc := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition mcause_ref := {|
+ name := "mcause";
+ read_from := (fun s => s.(mcause));
+ write_to := (fun v s => ({[ s with mcause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition mtvec_ref := {|
+ name := "mtvec";
+ read_from := (fun s => s.(mtvec));
+ write_to := (fun v s => ({[ s with mtvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition medeleg_ref := {|
+ name := "medeleg";
+ read_from := (fun s => s.(medeleg));
+ write_to := (fun v s => ({[ s with medeleg := v ]}));
+ of_regval := (fun v => Medeleg_of_regval v);
+ regval_of := (fun v => regval_of_Medeleg v) |}.
+
+Definition mideleg_ref := {|
+ name := "mideleg";
+ read_from := (fun s => s.(mideleg));
+ write_to := (fun v s => ({[ s with mideleg := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mie_ref := {|
+ name := "mie";
+ read_from := (fun s => s.(mie));
+ write_to := (fun v s => ({[ s with mie := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mip_ref := {|
+ name := "mip";
+ read_from := (fun s => s.(mip));
+ write_to := (fun v s => ({[ s with mip := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mstatus_ref := {|
+ name := "mstatus";
+ read_from := (fun s => s.(mstatus));
+ write_to := (fun v s => ({[ s with mstatus := v ]}));
+ of_regval := (fun v => Mstatus_of_regval v);
+ regval_of := (fun v => regval_of_Mstatus v) |}.
+
+Definition misa_ref := {|
+ name := "misa";
+ read_from := (fun s => s.(misa));
+ write_to := (fun v s => ({[ s with misa := v ]}));
+ of_regval := (fun v => Misa_of_regval v);
+ regval_of := (fun v => regval_of_Misa v) |}.
+
+Definition cur_inst_ref := {|
+ name := "cur_inst";
+ read_from := (fun s => s.(cur_inst));
+ write_to := (fun v s => ({[ s with cur_inst := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition cur_privilege_ref := {|
+ name := "cur_privilege";
+ read_from := (fun s => s.(cur_privilege));
+ write_to := (fun v s => ({[ s with cur_privilege := v ]}));
+ of_regval := (fun v => Privilege_of_regval v);
+ regval_of := (fun v => regval_of_Privilege v) |}.
+
+Definition x31_ref := {|
+ name := "x31";
+ read_from := (fun s => s.(x31));
+ write_to := (fun v s => ({[ s with x31 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x30_ref := {|
+ name := "x30";
+ read_from := (fun s => s.(x30));
+ write_to := (fun v s => ({[ s with x30 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x29_ref := {|
+ name := "x29";
+ read_from := (fun s => s.(x29));
+ write_to := (fun v s => ({[ s with x29 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x28_ref := {|
+ name := "x28";
+ read_from := (fun s => s.(x28));
+ write_to := (fun v s => ({[ s with x28 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x27_ref := {|
+ name := "x27";
+ read_from := (fun s => s.(x27));
+ write_to := (fun v s => ({[ s with x27 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x26_ref := {|
+ name := "x26";
+ read_from := (fun s => s.(x26));
+ write_to := (fun v s => ({[ s with x26 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x25_ref := {|
+ name := "x25";
+ read_from := (fun s => s.(x25));
+ write_to := (fun v s => ({[ s with x25 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x24_ref := {|
+ name := "x24";
+ read_from := (fun s => s.(x24));
+ write_to := (fun v s => ({[ s with x24 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x23_ref := {|
+ name := "x23";
+ read_from := (fun s => s.(x23));
+ write_to := (fun v s => ({[ s with x23 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x22_ref := {|
+ name := "x22";
+ read_from := (fun s => s.(x22));
+ write_to := (fun v s => ({[ s with x22 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x21_ref := {|
+ name := "x21";
+ read_from := (fun s => s.(x21));
+ write_to := (fun v s => ({[ s with x21 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x20_ref := {|
+ name := "x20";
+ read_from := (fun s => s.(x20));
+ write_to := (fun v s => ({[ s with x20 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x19_ref := {|
+ name := "x19";
+ read_from := (fun s => s.(x19));
+ write_to := (fun v s => ({[ s with x19 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x18_ref := {|
+ name := "x18";
+ read_from := (fun s => s.(x18));
+ write_to := (fun v s => ({[ s with x18 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x17_ref := {|
+ name := "x17";
+ read_from := (fun s => s.(x17));
+ write_to := (fun v s => ({[ s with x17 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x16_ref := {|
+ name := "x16";
+ read_from := (fun s => s.(x16));
+ write_to := (fun v s => ({[ s with x16 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x15_ref := {|
+ name := "x15";
+ read_from := (fun s => s.(x15));
+ write_to := (fun v s => ({[ s with x15 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x14_ref := {|
+ name := "x14";
+ read_from := (fun s => s.(x14));
+ write_to := (fun v s => ({[ s with x14 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x13_ref := {|
+ name := "x13";
+ read_from := (fun s => s.(x13));
+ write_to := (fun v s => ({[ s with x13 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x12_ref := {|
+ name := "x12";
+ read_from := (fun s => s.(x12));
+ write_to := (fun v s => ({[ s with x12 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x11_ref := {|
+ name := "x11";
+ read_from := (fun s => s.(x11));
+ write_to := (fun v s => ({[ s with x11 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x10_ref := {|
+ name := "x10";
+ read_from := (fun s => s.(x10));
+ write_to := (fun v s => ({[ s with x10 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x9_ref := {|
+ name := "x9";
+ read_from := (fun s => s.(x9));
+ write_to := (fun v s => ({[ s with x9 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x8_ref := {|
+ name := "x8";
+ read_from := (fun s => s.(x8));
+ write_to := (fun v s => ({[ s with x8 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x7_ref := {|
+ name := "x7";
+ read_from := (fun s => s.(x7));
+ write_to := (fun v s => ({[ s with x7 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x6_ref := {|
+ name := "x6";
+ read_from := (fun s => s.(x6));
+ write_to := (fun v s => ({[ s with x6 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x5_ref := {|
+ name := "x5";
+ read_from := (fun s => s.(x5));
+ write_to := (fun v s => ({[ s with x5 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x4_ref := {|
+ name := "x4";
+ read_from := (fun s => s.(x4));
+ write_to := (fun v s => ({[ s with x4 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x3_ref := {|
+ name := "x3";
+ read_from := (fun s => s.(x3));
+ write_to := (fun v s => ({[ s with x3 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x2_ref := {|
+ name := "x2";
+ read_from := (fun s => s.(x2));
+ write_to := (fun v s => ({[ s with x2 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition x1_ref := {|
+ name := "x1";
+ read_from := (fun s => s.(x1));
+ write_to := (fun v s => ({[ s with x1 := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition Xs_ref := {|
+ name := "Xs";
+ read_from := (fun s => s.(Xs));
+ write_to := (fun v s => ({[ s with Xs := v ]}));
+ of_regval := (fun v => vector_of_regval 32 (fun v => bitvector_32_dec_of_regval v) v);
+ regval_of := (fun v => regval_of_vector (fun v => regval_of_bitvector_32_dec v) 32 false v) |}.
+
+Definition instbits_ref := {|
+ name := "instbits";
+ read_from := (fun s => s.(instbits));
+ write_to := (fun v s => ({[ s with instbits := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition nextPC_ref := {|
+ name := "nextPC";
+ read_from := (fun s => s.(nextPC));
+ write_to := (fun v s => ({[ s with nextPC := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition PC_ref := {|
+ name := "PC";
+ read_from := (fun s => s.(PC));
+ write_to := (fun v s => ({[ s with PC := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+ if string_dec reg_name "satp" then Some (satp_ref.(regval_of) (satp_ref.(read_from) s)) else
+ if string_dec reg_name "tlb32" then Some (tlb32_ref.(regval_of) (tlb32_ref.(read_from) s)) else
+ if string_dec reg_name "htif_exit_code" then Some (htif_exit_code_ref.(regval_of) (htif_exit_code_ref.(read_from) s)) else
+ if string_dec reg_name "htif_done" then Some (htif_done_ref.(regval_of) (htif_done_ref.(read_from) s)) else
+ if string_dec reg_name "htif_tohost" then Some (htif_tohost_ref.(regval_of) (htif_tohost_ref.(read_from) s)) else
+ if string_dec reg_name "mtimecmp" then Some (mtimecmp_ref.(regval_of) (mtimecmp_ref.(read_from) s)) else
+ if string_dec reg_name "utval" then Some (utval_ref.(regval_of) (utval_ref.(read_from) s)) else
+ if string_dec reg_name "ucause" then Some (ucause_ref.(regval_of) (ucause_ref.(read_from) s)) else
+ if string_dec reg_name "uepc" then Some (uepc_ref.(regval_of) (uepc_ref.(read_from) s)) else
+ if string_dec reg_name "uscratch" then Some (uscratch_ref.(regval_of) (uscratch_ref.(read_from) s)) else
+ if string_dec reg_name "utvec" then Some (utvec_ref.(regval_of) (utvec_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr15" then Some (pmpaddr15_ref.(regval_of) (pmpaddr15_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr14" then Some (pmpaddr14_ref.(regval_of) (pmpaddr14_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr13" then Some (pmpaddr13_ref.(regval_of) (pmpaddr13_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr12" then Some (pmpaddr12_ref.(regval_of) (pmpaddr12_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr11" then Some (pmpaddr11_ref.(regval_of) (pmpaddr11_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr10" then Some (pmpaddr10_ref.(regval_of) (pmpaddr10_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr9" then Some (pmpaddr9_ref.(regval_of) (pmpaddr9_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr8" then Some (pmpaddr8_ref.(regval_of) (pmpaddr8_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr7" then Some (pmpaddr7_ref.(regval_of) (pmpaddr7_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr6" then Some (pmpaddr6_ref.(regval_of) (pmpaddr6_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr5" then Some (pmpaddr5_ref.(regval_of) (pmpaddr5_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr4" then Some (pmpaddr4_ref.(regval_of) (pmpaddr4_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr3" then Some (pmpaddr3_ref.(regval_of) (pmpaddr3_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr2" then Some (pmpaddr2_ref.(regval_of) (pmpaddr2_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr1" then Some (pmpaddr1_ref.(regval_of) (pmpaddr1_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr0" then Some (pmpaddr0_ref.(regval_of) (pmpaddr0_ref.(read_from) s)) else
+ if string_dec reg_name "pmp15cfg" then Some (pmp15cfg_ref.(regval_of) (pmp15cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp14cfg" then Some (pmp14cfg_ref.(regval_of) (pmp14cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp13cfg" then Some (pmp13cfg_ref.(regval_of) (pmp13cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp12cfg" then Some (pmp12cfg_ref.(regval_of) (pmp12cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp11cfg" then Some (pmp11cfg_ref.(regval_of) (pmp11cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp10cfg" then Some (pmp10cfg_ref.(regval_of) (pmp10cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp9cfg" then Some (pmp9cfg_ref.(regval_of) (pmp9cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp8cfg" then Some (pmp8cfg_ref.(regval_of) (pmp8cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp7cfg" then Some (pmp7cfg_ref.(regval_of) (pmp7cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp6cfg" then Some (pmp6cfg_ref.(regval_of) (pmp6cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp5cfg" then Some (pmp5cfg_ref.(regval_of) (pmp5cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp4cfg" then Some (pmp4cfg_ref.(regval_of) (pmp4cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp3cfg" then Some (pmp3cfg_ref.(regval_of) (pmp3cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp2cfg" then Some (pmp2cfg_ref.(regval_of) (pmp2cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp1cfg" then Some (pmp1cfg_ref.(regval_of) (pmp1cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp0cfg" then Some (pmp0cfg_ref.(regval_of) (pmp0cfg_ref.(read_from) s)) else
+ if string_dec reg_name "tselect" then Some (tselect_ref.(regval_of) (tselect_ref.(read_from) s)) else
+ if string_dec reg_name "stval" then Some (stval_ref.(regval_of) (stval_ref.(read_from) s)) else
+ if string_dec reg_name "scause" then Some (scause_ref.(regval_of) (scause_ref.(read_from) s)) else
+ if string_dec reg_name "sepc" then Some (sepc_ref.(regval_of) (sepc_ref.(read_from) s)) else
+ if string_dec reg_name "sscratch" then Some (sscratch_ref.(regval_of) (sscratch_ref.(read_from) s)) else
+ if string_dec reg_name "stvec" then Some (stvec_ref.(regval_of) (stvec_ref.(read_from) s)) else
+ if string_dec reg_name "sideleg" then Some (sideleg_ref.(regval_of) (sideleg_ref.(read_from) s)) else
+ if string_dec reg_name "sedeleg" then Some (sedeleg_ref.(regval_of) (sedeleg_ref.(read_from) s)) else
+ if string_dec reg_name "mhartid" then Some (mhartid_ref.(regval_of) (mhartid_ref.(read_from) s)) else
+ if string_dec reg_name "marchid" then Some (marchid_ref.(regval_of) (marchid_ref.(read_from) s)) else
+ if string_dec reg_name "mimpid" then Some (mimpid_ref.(regval_of) (mimpid_ref.(read_from) s)) else
+ if string_dec reg_name "mvendorid" then Some (mvendorid_ref.(regval_of) (mvendorid_ref.(read_from) s)) else
+ if string_dec reg_name "minstret_written" then Some (minstret_written_ref.(regval_of) (minstret_written_ref.(read_from) s)) else
+ if string_dec reg_name "minstret" then Some (minstret_ref.(regval_of) (minstret_ref.(read_from) s)) else
+ if string_dec reg_name "mtime" then Some (mtime_ref.(regval_of) (mtime_ref.(read_from) s)) else
+ if string_dec reg_name "mcycle" then Some (mcycle_ref.(regval_of) (mcycle_ref.(read_from) s)) else
+ if string_dec reg_name "scounteren" then Some (scounteren_ref.(regval_of) (scounteren_ref.(read_from) s)) else
+ if string_dec reg_name "mcounteren" then Some (mcounteren_ref.(regval_of) (mcounteren_ref.(read_from) s)) else
+ if string_dec reg_name "mscratch" then Some (mscratch_ref.(regval_of) (mscratch_ref.(read_from) s)) else
+ if string_dec reg_name "mtval" then Some (mtval_ref.(regval_of) (mtval_ref.(read_from) s)) else
+ if string_dec reg_name "mepc" then Some (mepc_ref.(regval_of) (mepc_ref.(read_from) s)) else
+ if string_dec reg_name "mcause" then Some (mcause_ref.(regval_of) (mcause_ref.(read_from) s)) else
+ if string_dec reg_name "mtvec" then Some (mtvec_ref.(regval_of) (mtvec_ref.(read_from) s)) else
+ if string_dec reg_name "medeleg" then Some (medeleg_ref.(regval_of) (medeleg_ref.(read_from) s)) else
+ if string_dec reg_name "mideleg" then Some (mideleg_ref.(regval_of) (mideleg_ref.(read_from) s)) else
+ if string_dec reg_name "mie" then Some (mie_ref.(regval_of) (mie_ref.(read_from) s)) else
+ if string_dec reg_name "mip" then Some (mip_ref.(regval_of) (mip_ref.(read_from) s)) else
+ if string_dec reg_name "mstatus" then Some (mstatus_ref.(regval_of) (mstatus_ref.(read_from) s)) else
+ if string_dec reg_name "misa" then Some (misa_ref.(regval_of) (misa_ref.(read_from) s)) else
+ if string_dec reg_name "cur_inst" then Some (cur_inst_ref.(regval_of) (cur_inst_ref.(read_from) s)) else
+ if string_dec reg_name "cur_privilege" then Some (cur_privilege_ref.(regval_of) (cur_privilege_ref.(read_from) s)) else
+ if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else
+ if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else
+ if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else
+ if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else
+ if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else
+ if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else
+ if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else
+ if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else
+ if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else
+ if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else
+ if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else
+ if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else
+ if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else
+ if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else
+ if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else
+ if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else
+ if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else
+ if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else
+ if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else
+ if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else
+ if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else
+ if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else
+ if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else
+ if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else
+ if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else
+ if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else
+ if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else
+ if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else
+ if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else
+ if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else
+ if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else
+ if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else
+ if string_dec reg_name "instbits" then Some (instbits_ref.(regval_of) (instbits_ref.(read_from) s)) else
+ if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+ if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+ None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+ if string_dec reg_name "satp" then option_map (fun v => satp_ref.(write_to) v s) (satp_ref.(of_regval) v) else
+ if string_dec reg_name "tlb32" then option_map (fun v => tlb32_ref.(write_to) v s) (tlb32_ref.(of_regval) v) else
+ if string_dec reg_name "htif_exit_code" then option_map (fun v => htif_exit_code_ref.(write_to) v s) (htif_exit_code_ref.(of_regval) v) else
+ if string_dec reg_name "htif_done" then option_map (fun v => htif_done_ref.(write_to) v s) (htif_done_ref.(of_regval) v) else
+ if string_dec reg_name "htif_tohost" then option_map (fun v => htif_tohost_ref.(write_to) v s) (htif_tohost_ref.(of_regval) v) else
+ if string_dec reg_name "mtimecmp" then option_map (fun v => mtimecmp_ref.(write_to) v s) (mtimecmp_ref.(of_regval) v) else
+ if string_dec reg_name "utval" then option_map (fun v => utval_ref.(write_to) v s) (utval_ref.(of_regval) v) else
+ if string_dec reg_name "ucause" then option_map (fun v => ucause_ref.(write_to) v s) (ucause_ref.(of_regval) v) else
+ if string_dec reg_name "uepc" then option_map (fun v => uepc_ref.(write_to) v s) (uepc_ref.(of_regval) v) else
+ if string_dec reg_name "uscratch" then option_map (fun v => uscratch_ref.(write_to) v s) (uscratch_ref.(of_regval) v) else
+ if string_dec reg_name "utvec" then option_map (fun v => utvec_ref.(write_to) v s) (utvec_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr15" then option_map (fun v => pmpaddr15_ref.(write_to) v s) (pmpaddr15_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr14" then option_map (fun v => pmpaddr14_ref.(write_to) v s) (pmpaddr14_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr13" then option_map (fun v => pmpaddr13_ref.(write_to) v s) (pmpaddr13_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr12" then option_map (fun v => pmpaddr12_ref.(write_to) v s) (pmpaddr12_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr11" then option_map (fun v => pmpaddr11_ref.(write_to) v s) (pmpaddr11_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr10" then option_map (fun v => pmpaddr10_ref.(write_to) v s) (pmpaddr10_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr9" then option_map (fun v => pmpaddr9_ref.(write_to) v s) (pmpaddr9_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr8" then option_map (fun v => pmpaddr8_ref.(write_to) v s) (pmpaddr8_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr7" then option_map (fun v => pmpaddr7_ref.(write_to) v s) (pmpaddr7_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr6" then option_map (fun v => pmpaddr6_ref.(write_to) v s) (pmpaddr6_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr5" then option_map (fun v => pmpaddr5_ref.(write_to) v s) (pmpaddr5_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr4" then option_map (fun v => pmpaddr4_ref.(write_to) v s) (pmpaddr4_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr3" then option_map (fun v => pmpaddr3_ref.(write_to) v s) (pmpaddr3_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr2" then option_map (fun v => pmpaddr2_ref.(write_to) v s) (pmpaddr2_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr1" then option_map (fun v => pmpaddr1_ref.(write_to) v s) (pmpaddr1_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr0" then option_map (fun v => pmpaddr0_ref.(write_to) v s) (pmpaddr0_ref.(of_regval) v) else
+ if string_dec reg_name "pmp15cfg" then option_map (fun v => pmp15cfg_ref.(write_to) v s) (pmp15cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp14cfg" then option_map (fun v => pmp14cfg_ref.(write_to) v s) (pmp14cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp13cfg" then option_map (fun v => pmp13cfg_ref.(write_to) v s) (pmp13cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp12cfg" then option_map (fun v => pmp12cfg_ref.(write_to) v s) (pmp12cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp11cfg" then option_map (fun v => pmp11cfg_ref.(write_to) v s) (pmp11cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp10cfg" then option_map (fun v => pmp10cfg_ref.(write_to) v s) (pmp10cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp9cfg" then option_map (fun v => pmp9cfg_ref.(write_to) v s) (pmp9cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp8cfg" then option_map (fun v => pmp8cfg_ref.(write_to) v s) (pmp8cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp7cfg" then option_map (fun v => pmp7cfg_ref.(write_to) v s) (pmp7cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp6cfg" then option_map (fun v => pmp6cfg_ref.(write_to) v s) (pmp6cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp5cfg" then option_map (fun v => pmp5cfg_ref.(write_to) v s) (pmp5cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp4cfg" then option_map (fun v => pmp4cfg_ref.(write_to) v s) (pmp4cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp3cfg" then option_map (fun v => pmp3cfg_ref.(write_to) v s) (pmp3cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp2cfg" then option_map (fun v => pmp2cfg_ref.(write_to) v s) (pmp2cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp1cfg" then option_map (fun v => pmp1cfg_ref.(write_to) v s) (pmp1cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp0cfg" then option_map (fun v => pmp0cfg_ref.(write_to) v s) (pmp0cfg_ref.(of_regval) v) else
+ if string_dec reg_name "tselect" then option_map (fun v => tselect_ref.(write_to) v s) (tselect_ref.(of_regval) v) else
+ if string_dec reg_name "stval" then option_map (fun v => stval_ref.(write_to) v s) (stval_ref.(of_regval) v) else
+ if string_dec reg_name "scause" then option_map (fun v => scause_ref.(write_to) v s) (scause_ref.(of_regval) v) else
+ if string_dec reg_name "sepc" then option_map (fun v => sepc_ref.(write_to) v s) (sepc_ref.(of_regval) v) else
+ if string_dec reg_name "sscratch" then option_map (fun v => sscratch_ref.(write_to) v s) (sscratch_ref.(of_regval) v) else
+ if string_dec reg_name "stvec" then option_map (fun v => stvec_ref.(write_to) v s) (stvec_ref.(of_regval) v) else
+ if string_dec reg_name "sideleg" then option_map (fun v => sideleg_ref.(write_to) v s) (sideleg_ref.(of_regval) v) else
+ if string_dec reg_name "sedeleg" then option_map (fun v => sedeleg_ref.(write_to) v s) (sedeleg_ref.(of_regval) v) else
+ if string_dec reg_name "mhartid" then option_map (fun v => mhartid_ref.(write_to) v s) (mhartid_ref.(of_regval) v) else
+ if string_dec reg_name "marchid" then option_map (fun v => marchid_ref.(write_to) v s) (marchid_ref.(of_regval) v) else
+ if string_dec reg_name "mimpid" then option_map (fun v => mimpid_ref.(write_to) v s) (mimpid_ref.(of_regval) v) else
+ if string_dec reg_name "mvendorid" then option_map (fun v => mvendorid_ref.(write_to) v s) (mvendorid_ref.(of_regval) v) else
+ if string_dec reg_name "minstret_written" then option_map (fun v => minstret_written_ref.(write_to) v s) (minstret_written_ref.(of_regval) v) else
+ if string_dec reg_name "minstret" then option_map (fun v => minstret_ref.(write_to) v s) (minstret_ref.(of_regval) v) else
+ if string_dec reg_name "mtime" then option_map (fun v => mtime_ref.(write_to) v s) (mtime_ref.(of_regval) v) else
+ if string_dec reg_name "mcycle" then option_map (fun v => mcycle_ref.(write_to) v s) (mcycle_ref.(of_regval) v) else
+ if string_dec reg_name "scounteren" then option_map (fun v => scounteren_ref.(write_to) v s) (scounteren_ref.(of_regval) v) else
+ if string_dec reg_name "mcounteren" then option_map (fun v => mcounteren_ref.(write_to) v s) (mcounteren_ref.(of_regval) v) else
+ if string_dec reg_name "mscratch" then option_map (fun v => mscratch_ref.(write_to) v s) (mscratch_ref.(of_regval) v) else
+ if string_dec reg_name "mtval" then option_map (fun v => mtval_ref.(write_to) v s) (mtval_ref.(of_regval) v) else
+ if string_dec reg_name "mepc" then option_map (fun v => mepc_ref.(write_to) v s) (mepc_ref.(of_regval) v) else
+ if string_dec reg_name "mcause" then option_map (fun v => mcause_ref.(write_to) v s) (mcause_ref.(of_regval) v) else
+ if string_dec reg_name "mtvec" then option_map (fun v => mtvec_ref.(write_to) v s) (mtvec_ref.(of_regval) v) else
+ if string_dec reg_name "medeleg" then option_map (fun v => medeleg_ref.(write_to) v s) (medeleg_ref.(of_regval) v) else
+ if string_dec reg_name "mideleg" then option_map (fun v => mideleg_ref.(write_to) v s) (mideleg_ref.(of_regval) v) else
+ if string_dec reg_name "mie" then option_map (fun v => mie_ref.(write_to) v s) (mie_ref.(of_regval) v) else
+ if string_dec reg_name "mip" then option_map (fun v => mip_ref.(write_to) v s) (mip_ref.(of_regval) v) else
+ if string_dec reg_name "mstatus" then option_map (fun v => mstatus_ref.(write_to) v s) (mstatus_ref.(of_regval) v) else
+ if string_dec reg_name "misa" then option_map (fun v => misa_ref.(write_to) v s) (misa_ref.(of_regval) v) else
+ if string_dec reg_name "cur_inst" then option_map (fun v => cur_inst_ref.(write_to) v s) (cur_inst_ref.(of_regval) v) else
+ if string_dec reg_name "cur_privilege" then option_map (fun v => cur_privilege_ref.(write_to) v s) (cur_privilege_ref.(of_regval) v) else
+ if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else
+ if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else
+ if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else
+ if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else
+ if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else
+ if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else
+ if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else
+ if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else
+ if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else
+ if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else
+ if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else
+ if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else
+ if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else
+ if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else
+ if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else
+ if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else
+ if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else
+ if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else
+ if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else
+ if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else
+ if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else
+ if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else
+ if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else
+ if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else
+ if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else
+ if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else
+ if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else
+ if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else
+ if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else
+ if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else
+ if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else
+ if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else
+ if string_dec reg_name "instbits" then option_map (fun v => instbits_ref.(write_to) v s) (instbits_ref.(of_regval) v) else
+ if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+ if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+ None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r exception.
+Definition M a := monad register_value a exception.
diff --git a/prover_snapshots/coq/RV64/riscv.v b/prover_snapshots/coq/RV64/riscv.v
new file mode 100644
index 0000000..fc0e61d
--- /dev/null
+++ b/prover_snapshots/coq/RV64/riscv.v
@@ -0,0 +1,43007 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Require Import riscv_types.
+Require Import riscv_extras.
+Import ListNotations.
+Open Scope string.
+Open Scope bool.
+Section Content.
+
+Definition is_none {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => true | None => false end.
+
+Definition eq_unit (_ : unit) (_ : unit)
+: {_bool : bool & ArithFact (_bool = true)} :=
+
+ build_ex(true).
+
+Definition neq_int (x : Z) (y : Z)
+: {_bool : bool & ArithFact (iff (_bool = true) (x <> y))} :=
+
+ build_ex(negb (Z.eqb x y)).
+
+Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y).
+
+Definition __id (x : Z) : {_retval : Z & ArithFact (_retval = x)} := build_ex(x).
+
+Definition concat_str_bits {n : Z} (str : string) (x : mword n)
+: string :=
+
+ String.append str (string_of_bits x).
+
+Definition concat_str_dec (str : string) (x : Z) : string := String.append str (dec_str x).
+
+
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)}
+: mword len :=
+
+ if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len
+ else zero_extend v len.
+
+Definition sail_ones (n : Z) `{ArithFact (n >= 0)} : mword n := not_vec (zeros n).
+
+Definition slice_mask (n : Z) (i : Z) (l : Z) `{ArithFact (n >= 0)}
+: mword n :=
+
+ if sumbool_of_bool ((Z.geb l n)) then shiftl (sail_ones n) i
+ else
+ let one : bits n := sail_mask n ((vec_of_bits [B1] : mword 1) : bits 1) in
+ shiftl (sub_vec (shiftl one l) one) i.
+
+Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)}
+: read_kind :=
+
+ let l__196 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__196 0)) then Read_plain
+ else if sumbool_of_bool ((Z.eqb l__196 1)) then Read_reserve
+ else if sumbool_of_bool ((Z.eqb l__196 2)) then Read_acquire
+ else if sumbool_of_bool ((Z.eqb l__196 3)) then Read_exclusive
+ else if sumbool_of_bool ((Z.eqb l__196 4)) then Read_exclusive_acquire
+ else if sumbool_of_bool ((Z.eqb l__196 5)) then Read_stream
+ else if sumbool_of_bool ((Z.eqb l__196 6)) then Read_RISCV_acquire
+ else if sumbool_of_bool ((Z.eqb l__196 7)) then Read_RISCV_strong_acquire
+ else if sumbool_of_bool ((Z.eqb l__196 8)) then Read_RISCV_reserved
+ else if sumbool_of_bool ((Z.eqb l__196 9)) then Read_RISCV_reserved_acquire
+ else if sumbool_of_bool ((Z.eqb l__196 10)) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked.
+
+Definition num_of_read_kind (arg_ : read_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 11)} :=
+
+ build_ex(match arg_ with
+ | Read_plain => 0
+ | Read_reserve => 1
+ | Read_acquire => 2
+ | Read_exclusive => 3
+ | Read_exclusive_acquire => 4
+ | Read_stream => 5
+ | Read_RISCV_acquire => 6
+ | Read_RISCV_strong_acquire => 7
+ | Read_RISCV_reserved => 8
+ | Read_RISCV_reserved_acquire => 9
+ | Read_RISCV_reserved_strong_acquire => 10
+ | Read_X86_locked => 11
+ end).
+
+Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: write_kind :=
+
+ let l__186 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__186 0)) then Write_plain
+ else if sumbool_of_bool ((Z.eqb l__186 1)) then Write_conditional
+ else if sumbool_of_bool ((Z.eqb l__186 2)) then Write_release
+ else if sumbool_of_bool ((Z.eqb l__186 3)) then Write_exclusive
+ else if sumbool_of_bool ((Z.eqb l__186 4)) then Write_exclusive_release
+ else if sumbool_of_bool ((Z.eqb l__186 5)) then Write_RISCV_release
+ else if sumbool_of_bool ((Z.eqb l__186 6)) then Write_RISCV_strong_release
+ else if sumbool_of_bool ((Z.eqb l__186 7)) then Write_RISCV_conditional
+ else if sumbool_of_bool ((Z.eqb l__186 8)) then Write_RISCV_conditional_release
+ else if sumbool_of_bool ((Z.eqb l__186 9)) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked.
+
+Definition num_of_write_kind (arg_ : write_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Write_plain => 0
+ | Write_conditional => 1
+ | Write_release => 2
+ | Write_exclusive => 3
+ | Write_exclusive_release => 4
+ | Write_RISCV_release => 5
+ | Write_RISCV_strong_release => 6
+ | Write_RISCV_conditional => 7
+ | Write_RISCV_conditional_release => 8
+ | Write_RISCV_conditional_strong_release => 9
+ | Write_X86_locked => 10
+ end).
+
+Definition a64_barrier_domain_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: a64_barrier_domain :=
+
+ let l__183 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__183 0)) then A64_FullShare
+ else if sumbool_of_bool ((Z.eqb l__183 1)) then A64_InnerShare
+ else if sumbool_of_bool ((Z.eqb l__183 2)) then A64_OuterShare
+ else A64_NonShare.
+
+Definition num_of_a64_barrier_domain (arg_ : a64_barrier_domain)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with
+ | A64_FullShare => 0
+ | A64_InnerShare => 1
+ | A64_OuterShare => 2
+ | A64_NonShare => 3
+ end).
+
+Definition a64_barrier_type_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: a64_barrier_type :=
+
+ let l__181 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__181 0)) then A64_barrier_all
+ else if sumbool_of_bool ((Z.eqb l__181 1)) then A64_barrier_LD
+ else A64_barrier_ST.
+
+Definition num_of_a64_barrier_type (arg_ : a64_barrier_type)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | A64_barrier_all => 0 | A64_barrier_LD => 1 | A64_barrier_ST => 2 end).
+
+Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: trans_kind :=
+
+ let l__179 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__179 0)) then Transaction_start
+ else if sumbool_of_bool ((Z.eqb l__179 1)) then Transaction_commit
+ else Transaction_abort.
+
+Definition num_of_trans_kind (arg_ : trans_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with
+ | Transaction_start => 0
+ | Transaction_commit => 1
+ | Transaction_abort => 2
+ end).
+
+Definition cache_op_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: cache_op_kind :=
+
+ let l__169 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__169 0)) then Cache_op_D_IVAC
+ else if sumbool_of_bool ((Z.eqb l__169 1)) then Cache_op_D_ISW
+ else if sumbool_of_bool ((Z.eqb l__169 2)) then Cache_op_D_CSW
+ else if sumbool_of_bool ((Z.eqb l__169 3)) then Cache_op_D_CISW
+ else if sumbool_of_bool ((Z.eqb l__169 4)) then Cache_op_D_ZVA
+ else if sumbool_of_bool ((Z.eqb l__169 5)) then Cache_op_D_CVAC
+ else if sumbool_of_bool ((Z.eqb l__169 6)) then Cache_op_D_CVAU
+ else if sumbool_of_bool ((Z.eqb l__169 7)) then Cache_op_D_CIVAC
+ else if sumbool_of_bool ((Z.eqb l__169 8)) then Cache_op_I_IALLUIS
+ else if sumbool_of_bool ((Z.eqb l__169 9)) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU.
+
+Definition num_of_cache_op_kind (arg_ : cache_op_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Cache_op_D_IVAC => 0
+ | Cache_op_D_ISW => 1
+ | Cache_op_D_CSW => 2
+ | Cache_op_D_CISW => 3
+ | Cache_op_D_ZVA => 4
+ | Cache_op_D_CVAC => 5
+ | Cache_op_D_CVAU => 6
+ | Cache_op_D_CIVAC => 7
+ | Cache_op_I_IALLUIS => 8
+ | Cache_op_I_IALLU => 9
+ | Cache_op_I_IVAU => 10
+ end).
+
+Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+
+
+
+Definition cast_unit_vec (b : bitU)
+: M (mword 1) :=
+
+ (match b with
+ | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ | _ => exit tt : M (mword 1)
+ end)
+ : M (mword 1).
+
+Definition get_config_print_instr '(tt : unit) : bool := false.
+
+Definition get_config_print_reg '(tt : unit) : bool := false.
+
+Definition get_config_print_mem '(tt : unit) : bool := false.
+
+Definition get_config_print_platform '(tt : unit) : bool := false.
+
+Definition EXTS {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := sign_extend v m.
+
+Definition EXTZ {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := zero_extend v m.
+
+Definition zeros_implicit (n : Z) `{ArithFact (n >= 0)} : mword n := zeros n.
+
+Definition ones (n : Z) `{ArithFact (n >= 0)} : mword n := sail_ones n.
+
+Definition bool_to_bits (x : bool)
+: mword 1 :=
+
+ if sumbool_of_bool (x) then (vec_of_bits [B1] : mword 1)
+ else (vec_of_bits [B0] : mword 1).
+
+Definition bit_to_bool (b : bitU)
+: M (bool) :=
+
+ (match b with
+ | B1 => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | B0 => returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool).
+
+Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0.
+
+Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.ltb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.geb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.ltb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.geb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.leb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition shift_right_arith64 (v : mword 64) (shift : mword 6)
+: mword 64 :=
+
+ let v128 : bits 128 := EXTS 128 v in
+ subrange_vec_dec (shift_bits_right v128 shift) 63 0.
+
+Definition shift_right_arith32 (v : mword 32) (shift : mword 5)
+: mword 32 :=
+
+ let v64 : bits 64 := EXTS 64 v in
+ subrange_vec_dec (shift_bits_right v64 shift) 31 0.
+
+Fixpoint _rec_n_leading_spaces (s : string) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M ({n : Z & ArithFact (n >= 0)}) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let p0_ := s in
+ (if ((generic_eq p0_ "")) then returnm (build_ex (0 : Z))
+ else
+ let p0_ := string_take s 1 in
+ (if ((generic_eq p0_ " ")) then
+ (_rec_n_leading_spaces (string_drop s 1) (Z.sub _reclimit 1) (_limit_reduces _acc)) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >=
+ 0)}) =>
+ returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.add 1 w__0)
+ : {_atom : Z & ArithFact (exists ex98922_ , _atom = (1 + ex98922_) /\ 0 <= ex98922_)})))
+ else returnm (build_ex (0 : Z)))
+ : M ({n : Z & ArithFact (n >= 0)}))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition n_leading_spaces (s : string)
+: M ({n : Z & ArithFact (n >= 0)}) :=
+
+ (_rec_n_leading_spaces s ((projT1 (string_length s)) : Z) (Zwf_guarded _))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition spc_forwards '(tt : unit) : string := " ".
+
+Definition spc_backwards (s : string) : unit := tt.
+
+Definition spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ n _) =>
+ let l__168 := n in
+ returnm ((if sumbool_of_bool ((Z.eqb l__168 0)) then None
+ else Some ((tt, build_ex n)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition opt_spc_forwards '(tt : unit) : string := "".
+
+Definition opt_spc_backwards (s : string) : unit := tt.
+
+Definition opt_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= 0)}) =>
+ returnm ((Some
+ ((tt, build_ex
+ w__0)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition def_spc_forwards '(tt : unit) : string := " ".
+
+Definition def_spc_backwards (s : string) : unit := tt.
+
+Definition def_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (opt_spc_matches_prefix s)
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition hex_bits_1_forwards_matches (bv : mword 1) : bool := true.
+
+Definition hex_bits_1_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_1_matches_prefix s) with
+ | Some ((g__258, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_1_backwards (s : string)
+: M (mword 1) :=
+
+ (match (hex_bits_1_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 1)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt)
+ : M (mword 1)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 1).
+
+Definition hex_bits_2_forwards_matches (bv : mword 2) : bool := true.
+
+Definition hex_bits_2_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_2_matches_prefix s) with
+ | Some ((g__257, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_2_backwards (s : string)
+: M (mword 2) :=
+
+ (match (hex_bits_2_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 2)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt)
+ : M (mword 2)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 2).
+
+Definition hex_bits_3_forwards_matches (bv : mword 3) : bool := true.
+
+Definition hex_bits_3_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_3_matches_prefix s) with
+ | Some ((g__256, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_3_backwards (s : string)
+: M (mword 3) :=
+
+ (match (hex_bits_3_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 3)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt)
+ : M (mword 3)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 3).
+
+Definition hex_bits_4_forwards_matches (bv : mword 4) : bool := true.
+
+Definition hex_bits_4_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_4_matches_prefix s) with
+ | Some ((g__255, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_4_backwards (s : string)
+: M (mword 4) :=
+
+ (match (hex_bits_4_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 4)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt)
+ : M (mword 4)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 4).
+
+Definition hex_bits_5_forwards_matches (bv : mword 5) : bool := true.
+
+Definition hex_bits_5_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_5_matches_prefix s) with
+ | Some ((g__254, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_5_backwards (s : string)
+: M (mword 5) :=
+
+ (match (hex_bits_5_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 5)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt)
+ : M (mword 5)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 5).
+
+Definition hex_bits_6_forwards_matches (bv : mword 6) : bool := true.
+
+Definition hex_bits_6_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_6_matches_prefix s) with
+ | Some ((g__253, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_6_backwards (s : string)
+: M (mword 6) :=
+
+ (match (hex_bits_6_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 6)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt)
+ : M (mword 6)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 6).
+
+Definition hex_bits_7_forwards_matches (bv : mword 7) : bool := true.
+
+Definition hex_bits_7_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_7_matches_prefix s) with
+ | Some ((g__252, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_7_backwards (s : string)
+: M (mword 7) :=
+
+ (match (hex_bits_7_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 7)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt)
+ : M (mword 7)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 7).
+
+Definition hex_bits_8_forwards_matches (bv : mword 8) : bool := true.
+
+Definition hex_bits_8_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_8_matches_prefix s) with
+ | Some ((g__251, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_8_backwards (s : string)
+: M (mword 8) :=
+
+ (match (hex_bits_8_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 8)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt)
+ : M (mword 8)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 8).
+
+Definition hex_bits_9_forwards_matches (bv : mword 9) : bool := true.
+
+Definition hex_bits_9_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_9_matches_prefix s) with
+ | Some ((g__250, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_9_backwards (s : string)
+: M (mword 9) :=
+
+ (match (hex_bits_9_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 9)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt)
+ : M (mword 9)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 9).
+
+Definition hex_bits_10_forwards_matches (bv : mword 10) : bool := true.
+
+Definition hex_bits_10_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_10_matches_prefix s) with
+ | Some ((g__249, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_10_backwards (s : string)
+: M (mword 10) :=
+
+ (match (hex_bits_10_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 10)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt)
+ : M (mword 10)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 10).
+
+Definition hex_bits_11_forwards_matches (bv : mword 11) : bool := true.
+
+Definition hex_bits_11_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_11_matches_prefix s) with
+ | Some ((g__248, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_11_backwards (s : string)
+: M (mword 11) :=
+
+ (match (hex_bits_11_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 11)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt)
+ : M (mword 11)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 11).
+
+Definition hex_bits_12_forwards_matches (bv : mword 12) : bool := true.
+
+Definition hex_bits_12_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_12_matches_prefix s) with
+ | Some ((g__247, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_12_backwards (s : string)
+: M (mword 12) :=
+
+ (match (hex_bits_12_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 12)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt)
+ : M (mword 12)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 12).
+
+Definition hex_bits_13_forwards_matches (bv : mword 13) : bool := true.
+
+Definition hex_bits_13_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_13_matches_prefix s) with
+ | Some ((g__246, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_13_backwards (s : string)
+: M (mword 13) :=
+
+ (match (hex_bits_13_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 13)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt)
+ : M (mword 13)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 13).
+
+Definition hex_bits_14_forwards_matches (bv : mword 14) : bool := true.
+
+Definition hex_bits_14_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_14_matches_prefix s) with
+ | Some ((g__245, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_14_backwards (s : string)
+: M (mword 14) :=
+
+ (match (hex_bits_14_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 14)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt)
+ : M (mword 14)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 14).
+
+Definition hex_bits_15_forwards_matches (bv : mword 15) : bool := true.
+
+Definition hex_bits_15_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_15_matches_prefix s) with
+ | Some ((g__244, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_15_backwards (s : string)
+: M (mword 15) :=
+
+ (match (hex_bits_15_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 15)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt)
+ : M (mword 15)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 15).
+
+Definition hex_bits_16_forwards_matches (bv : mword 16) : bool := true.
+
+Definition hex_bits_16_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_16_matches_prefix s) with
+ | Some ((g__243, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_16_backwards (s : string)
+: M (mword 16) :=
+
+ (match (hex_bits_16_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 16)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt)
+ : M (mword 16)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 16).
+
+Definition hex_bits_17_forwards_matches (bv : mword 17) : bool := true.
+
+Definition hex_bits_17_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_17_matches_prefix s) with
+ | Some ((g__242, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_17_backwards (s : string)
+: M (mword 17) :=
+
+ (match (hex_bits_17_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 17)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt)
+ : M (mword 17)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 17).
+
+Definition hex_bits_18_forwards_matches (bv : mword 18) : bool := true.
+
+Definition hex_bits_18_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_18_matches_prefix s) with
+ | Some ((g__241, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_18_backwards (s : string)
+: M (mword 18) :=
+
+ (match (hex_bits_18_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 18)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt)
+ : M (mword 18)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 18).
+
+Definition hex_bits_19_forwards_matches (bv : mword 19) : bool := true.
+
+Definition hex_bits_19_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_19_matches_prefix s) with
+ | Some ((g__240, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_19_backwards (s : string)
+: M (mword 19) :=
+
+ (match (hex_bits_19_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 19)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt)
+ : M (mword 19)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 19).
+
+Definition hex_bits_20_forwards_matches (bv : mword 20) : bool := true.
+
+Definition hex_bits_20_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_20_matches_prefix s) with
+ | Some ((g__239, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_20_backwards (s : string)
+: M (mword 20) :=
+
+ (match (hex_bits_20_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 20)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt)
+ : M (mword 20)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 20).
+
+Definition hex_bits_21_forwards_matches (bv : mword 21) : bool := true.
+
+Definition hex_bits_21_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_21_matches_prefix s) with
+ | Some ((g__238, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_21_backwards (s : string)
+: M (mword 21) :=
+
+ (match (hex_bits_21_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 21)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt)
+ : M (mword 21)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 21).
+
+Definition hex_bits_22_forwards_matches (bv : mword 22) : bool := true.
+
+Definition hex_bits_22_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_22_matches_prefix s) with
+ | Some ((g__237, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_22_backwards (s : string)
+: M (mword 22) :=
+
+ (match (hex_bits_22_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 22)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt)
+ : M (mword 22)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 22).
+
+Definition hex_bits_23_forwards_matches (bv : mword 23) : bool := true.
+
+Definition hex_bits_23_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_23_matches_prefix s) with
+ | Some ((g__236, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_23_backwards (s : string)
+: M (mword 23) :=
+
+ (match (hex_bits_23_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 23)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt)
+ : M (mword 23)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 23).
+
+Definition hex_bits_24_forwards_matches (bv : mword 24) : bool := true.
+
+Definition hex_bits_24_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_24_matches_prefix s) with
+ | Some ((g__235, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_24_backwards (s : string)
+: M (mword 24) :=
+
+ (match (hex_bits_24_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 24)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt)
+ : M (mword 24)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 24).
+
+Definition hex_bits_25_forwards_matches (bv : mword 25) : bool := true.
+
+Definition hex_bits_25_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_25_matches_prefix s) with
+ | Some ((g__234, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_25_backwards (s : string)
+: M (mword 25) :=
+
+ (match (hex_bits_25_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 25)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt)
+ : M (mword 25)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 25).
+
+Definition hex_bits_26_forwards_matches (bv : mword 26) : bool := true.
+
+Definition hex_bits_26_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_26_matches_prefix s) with
+ | Some ((g__233, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_26_backwards (s : string)
+: M (mword 26) :=
+
+ (match (hex_bits_26_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 26)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt)
+ : M (mword 26)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 26).
+
+Definition hex_bits_27_forwards_matches (bv : mword 27) : bool := true.
+
+Definition hex_bits_27_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_27_matches_prefix s) with
+ | Some ((g__232, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_27_backwards (s : string)
+: M (mword 27) :=
+
+ (match (hex_bits_27_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 27)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt)
+ : M (mword 27)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 27).
+
+Definition hex_bits_28_forwards_matches (bv : mword 28) : bool := true.
+
+Definition hex_bits_28_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_28_matches_prefix s) with
+ | Some ((g__231, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_28_backwards (s : string)
+: M (mword 28) :=
+
+ (match (hex_bits_28_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 28)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt)
+ : M (mword 28)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 28).
+
+Definition hex_bits_29_forwards_matches (bv : mword 29) : bool := true.
+
+Definition hex_bits_29_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_29_matches_prefix s) with
+ | Some ((g__230, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_29_backwards (s : string)
+: M (mword 29) :=
+
+ (match (hex_bits_29_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 29)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt)
+ : M (mword 29)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 29).
+
+Definition hex_bits_30_forwards_matches (bv : mword 30) : bool := true.
+
+Definition hex_bits_30_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_30_matches_prefix s) with
+ | Some ((g__229, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_30_backwards (s : string)
+: M (mword 30) :=
+
+ (match (hex_bits_30_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 30)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt)
+ : M (mword 30)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 30).
+
+Definition hex_bits_31_forwards_matches (bv : mword 31) : bool := true.
+
+Definition hex_bits_31_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_31_matches_prefix s) with
+ | Some ((g__228, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_31_backwards (s : string)
+: M (mword 31) :=
+
+ (match (hex_bits_31_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 31)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt)
+ : M (mword 31)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 31).
+
+Definition hex_bits_32_forwards_matches (bv : mword 32) : bool := true.
+
+Definition hex_bits_32_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_32_matches_prefix s) with
+ | Some ((g__227, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_32_backwards (s : string)
+: M (mword 32) :=
+
+ (match (hex_bits_32_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 32)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt)
+ : M (mword 32)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 32).
+
+Definition hex_bits_33_forwards_matches (bv : mword 33) : bool := true.
+
+Definition hex_bits_33_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_33_matches_prefix s) with
+ | Some ((g__226, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_33_backwards (s : string)
+: M (mword 33) :=
+
+ (match (hex_bits_33_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 33)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt)
+ : M (mword 33)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 33).
+
+Definition hex_bits_48_forwards_matches (bv : mword 48) : bool := true.
+
+Definition hex_bits_48_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_48_matches_prefix s) with
+ | Some ((g__225, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_48_backwards (s : string)
+: M (mword 48) :=
+
+ (match (hex_bits_48_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 48)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt)
+ : M (mword 48)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 48).
+
+Definition hex_bits_64_forwards_matches (bv : mword 64) : bool := true.
+
+Definition hex_bits_64_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_64_matches_prefix s) with
+ | Some ((g__224, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_64_backwards (s : string)
+: M (mword 64) :=
+
+ (match (hex_bits_64_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 64)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt)
+ : M (mword 64)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 64).
+
+Definition default_meta : mem_meta := tt.
+Hint Unfold default_meta : sail.
+Definition __WriteRAM_Meta (addr : mword 64) (width : Z) (meta : unit)
+: M (unit) :=
+
+ returnm (tt
+ : unit).
+
+Definition __ReadRAM_Meta (addr : mword 64) (width : Z) : M (unit) := returnm (tt : unit).
+
+Definition write_ram
+(wk : write_kind) (addr : mword 64) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (bool) :=
+
+ (write_mem wk 64 addr width data) >>= fun ret : bool =>
+ (if sumbool_of_bool (ret) then (__WriteRAM_Meta addr width meta) : M (unit)
+ else returnm (tt : unit)) >>
+ returnm (ret
+ : bool).
+
+Definition write_ram_ea (wk : write_kind) (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (unit) :=
+
+ (write_mem_ea wk 64 addr width)
+ : M (unit).
+
+Definition read_ram (rk : read_kind) (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (mword (8 * width)) :=
+
+ (read_mem rk 64 addr width)
+ : M (mword (8 * width)).
+
+Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Definition xlen_val := 64.
+Hint Unfold xlen_val : sail.
+Definition xlen_max_unsigned := Z.sub (projT1 (pow2 64)) 1.
+Hint Unfold xlen_max_unsigned : sail.
+Definition xlen_max_signed := Z.sub (projT1 (pow2 (Z.sub 64 1))) 1.
+Hint Unfold xlen_max_signed : sail.
+Definition xlen_min_signed := Z.sub 0 (projT1 (pow2 (Z.sub 64 1))).
+Hint Unfold xlen_min_signed : sail.
+Definition regidx_to_regno (b : mword 5)
+: {n : Z & ArithFact (0 <= n /\ n < 32)} :=
+
+ build_ex(let 'r := projT1 (uint b) in
+ r).
+
+Definition creg2reg_idx (creg : mword 3)
+: mword 5 :=
+
+ concat_vec (vec_of_bits [B0;B1] : mword 2) creg.
+
+Definition zreg : regidx := (vec_of_bits [B0;B0;B0;B0;B0] : mword 5).
+Hint Unfold zreg : sail.
+Definition ra : regidx := (vec_of_bits [B0;B0;B0;B0;B1] : mword 5).
+Hint Unfold ra : sail.
+Definition sp : regidx := (vec_of_bits [B0;B0;B0;B1;B0] : mword 5).
+Hint Unfold sp : sail.
+Definition Architecture_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: Architecture :=
+
+ let l__166 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__166 0)) then RV32
+ else if sumbool_of_bool ((Z.eqb l__166 1)) then RV64
+ else RV128.
+
+Definition num_of_Architecture (arg_ : Architecture)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RV32 => 0 | RV64 => 1 | RV128 => 2 end).
+
+Definition architecture (a : mword 2)
+: option Architecture :=
+
+ let b__0 := a in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Some (RV32)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Some (RV64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then Some (RV128)
+ else None.
+
+Definition arch_to_bits (a : Architecture)
+: mword 2 :=
+
+ match a with
+ | RV32 => (vec_of_bits [B0;B1] : mword 2)
+ | RV64 => (vec_of_bits [B1;B0] : mword 2)
+ | RV128 => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition Privilege_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: Privilege :=
+
+ let l__164 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__164 0)) then User
+ else if sumbool_of_bool ((Z.eqb l__164 1)) then Supervisor
+ else Machine.
+
+Definition num_of_Privilege (arg_ : Privilege)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | User => 0 | Supervisor => 1 | Machine => 2 end).
+
+Definition privLevel_to_bits (p : Privilege)
+: mword 2 :=
+
+ match p with
+ | User => (vec_of_bits [B0;B0] : mword 2)
+ | Supervisor => (vec_of_bits [B0;B1] : mword 2)
+ | Machine => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition privLevel_of_bits (p : mword 2)
+: M (Privilege) :=
+
+ let b__0 := p in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (User : Privilege)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (Supervisor : Privilege)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (Machine : Privilege)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_types.sail 78:2 - 82:3" >>= fun _ =>
+ exit tt)
+ : M (Privilege).
+
+Definition privLevel_to_str (p : Privilege)
+: string :=
+
+ match p with | User => "U" | Supervisor => "S" | Machine => "M" end.
+
+Definition Retired_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)}
+: Retired :=
+
+ let l__163 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__163 0)) then RETIRE_SUCCESS
+ else RETIRE_FAIL.
+
+Definition num_of_Retired (arg_ : Retired)
+: {e : Z & ArithFact (0 <= e /\ e <= 1)} :=
+
+ build_ex(match arg_ with | RETIRE_SUCCESS => 0 | RETIRE_FAIL => 1 end).
+
+Definition AccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: AccessType :=
+
+ let l__160 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__160 0)) then Read
+ else if sumbool_of_bool ((Z.eqb l__160 1)) then Write
+ else if sumbool_of_bool ((Z.eqb l__160 2)) then ReadWrite
+ else Execute.
+
+Definition num_of_AccessType (arg_ : AccessType)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Read => 0 | Write => 1 | ReadWrite => 2 | Execute => 3 end).
+
+Definition accessType_to_str (a : AccessType)
+: string :=
+
+ match a with | Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" end.
+
+Definition word_width_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: word_width :=
+
+ let l__157 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__157 0)) then BYTE
+ else if sumbool_of_bool ((Z.eqb l__157 1)) then HALF
+ else if sumbool_of_bool ((Z.eqb l__157 2)) then WORD
+ else DOUBLE.
+
+Definition num_of_word_width (arg_ : word_width)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | BYTE => 0 | HALF => 1 | WORD => 2 | DOUBLE => 3 end).
+
+Definition InterruptType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)}
+: InterruptType :=
+
+ let l__149 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__149 0)) then I_U_Software
+ else if sumbool_of_bool ((Z.eqb l__149 1)) then I_S_Software
+ else if sumbool_of_bool ((Z.eqb l__149 2)) then I_M_Software
+ else if sumbool_of_bool ((Z.eqb l__149 3)) then I_U_Timer
+ else if sumbool_of_bool ((Z.eqb l__149 4)) then I_S_Timer
+ else if sumbool_of_bool ((Z.eqb l__149 5)) then I_M_Timer
+ else if sumbool_of_bool ((Z.eqb l__149 6)) then I_U_External
+ else if sumbool_of_bool ((Z.eqb l__149 7)) then I_S_External
+ else I_M_External.
+
+Definition num_of_InterruptType (arg_ : InterruptType)
+: {e : Z & ArithFact (0 <= e /\ e <= 8)} :=
+
+ build_ex(match arg_ with
+ | I_U_Software => 0
+ | I_S_Software => 1
+ | I_M_Software => 2
+ | I_U_Timer => 3
+ | I_S_Timer => 4
+ | I_M_Timer => 5
+ | I_U_External => 6
+ | I_S_External => 7
+ | I_M_External => 8
+ end).
+
+Definition interruptType_to_bits (i : InterruptType)
+: mword 8 :=
+
+ match i with
+ | I_U_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)
+ | I_S_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8)
+ | I_M_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8)
+ | I_U_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8)
+ | I_S_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8)
+ | I_M_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8)
+ | I_U_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8)
+ | I_S_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8)
+ | I_M_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8)
+ end.
+
+Definition ExceptionType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 16)}
+: ExceptionType :=
+
+ let l__133 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__133 0)) then E_Fetch_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__133 1)) then E_Fetch_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__133 2)) then E_Illegal_Instr
+ else if sumbool_of_bool ((Z.eqb l__133 3)) then E_Breakpoint
+ else if sumbool_of_bool ((Z.eqb l__133 4)) then E_Load_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__133 5)) then E_Load_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__133 6)) then E_SAMO_Addr_Align
+ else if sumbool_of_bool ((Z.eqb l__133 7)) then E_SAMO_Access_Fault
+ else if sumbool_of_bool ((Z.eqb l__133 8)) then E_U_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__133 9)) then E_S_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__133 10)) then E_Reserved_10
+ else if sumbool_of_bool ((Z.eqb l__133 11)) then E_M_EnvCall
+ else if sumbool_of_bool ((Z.eqb l__133 12)) then E_Fetch_Page_Fault
+ else if sumbool_of_bool ((Z.eqb l__133 13)) then E_Load_Page_Fault
+ else if sumbool_of_bool ((Z.eqb l__133 14)) then E_Reserved_14
+ else if sumbool_of_bool ((Z.eqb l__133 15)) then E_SAMO_Page_Fault
+ else E_CHERI.
+
+Definition num_of_ExceptionType (arg_ : ExceptionType)
+: {e : Z & ArithFact (0 <= e /\ e <= 16)} :=
+
+ build_ex(match arg_ with
+ | E_Fetch_Addr_Align => 0
+ | E_Fetch_Access_Fault => 1
+ | E_Illegal_Instr => 2
+ | E_Breakpoint => 3
+ | E_Load_Addr_Align => 4
+ | E_Load_Access_Fault => 5
+ | E_SAMO_Addr_Align => 6
+ | E_SAMO_Access_Fault => 7
+ | E_U_EnvCall => 8
+ | E_S_EnvCall => 9
+ | E_Reserved_10 => 10
+ | E_M_EnvCall => 11
+ | E_Fetch_Page_Fault => 12
+ | E_Load_Page_Fault => 13
+ | E_Reserved_14 => 14
+ | E_SAMO_Page_Fault => 15
+ | E_CHERI => 16
+ end).
+
+Definition exceptionType_to_bits (e : ExceptionType)
+: mword 8 :=
+
+ match e with
+ | E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)
+ | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8)
+ | E_Illegal_Instr => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8)
+ | E_Breakpoint => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8)
+ | E_Load_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8)
+ | E_Load_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8)
+ | E_SAMO_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : mword 8)
+ | E_SAMO_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8)
+ | E_U_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8)
+ | E_S_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8)
+ | E_Reserved_10 => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8)
+ | E_M_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8)
+ | E_Fetch_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8)
+ | E_Load_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8)
+ | E_Reserved_14 => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B0] : mword 8)
+ | E_SAMO_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1] : mword 8)
+ | E_CHERI => (vec_of_bits [B0;B0;B1;B0;B0;B0;B0;B0] : mword 8)
+ end.
+
+Definition exceptionType_to_str (e : ExceptionType)
+: string :=
+
+ match e with
+ | E_Fetch_Addr_Align => "misaligned-fetch"
+ | E_Fetch_Access_Fault => "fetch-access-fault"
+ | E_Illegal_Instr => "illegal-instruction"
+ | E_Breakpoint => "breakpoint"
+ | E_Load_Addr_Align => "misaligned-load"
+ | E_Load_Access_Fault => "load-access-fault"
+ | E_SAMO_Addr_Align => "misaliged-store/amo"
+ | E_SAMO_Access_Fault => "store/amo-access-fault"
+ | E_U_EnvCall => "u-call"
+ | E_S_EnvCall => "s-call"
+ | E_Reserved_10 => "reserved-0"
+ | E_M_EnvCall => "m-call"
+ | E_Fetch_Page_Fault => "fetch-page-fault"
+ | E_Load_Page_Fault => "load-page-fault"
+ | E_Reserved_14 => "reserved-1"
+ | E_SAMO_Page_Fault => "store/amo-page-fault"
+ | E_CHERI => "CHERI"
+ end.
+
+Definition not_implemented {a : Type} (message : string)
+: M (a) :=
+
+ throw (Error_not_implemented
+ (message)).
+
+Definition internal_error {a : Type} (s : string)
+: M (a) :=
+
+ assert_exp' false s >>= fun _ => exit tt.
+
+Definition TrapVectorMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: TrapVectorMode :=
+
+ let l__131 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__131 0)) then TV_Direct
+ else if sumbool_of_bool ((Z.eqb l__131 1)) then TV_Vector
+ else TV_Reserved.
+
+Definition num_of_TrapVectorMode (arg_ : TrapVectorMode)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | TV_Direct => 0 | TV_Vector => 1 | TV_Reserved => 2 end).
+
+Definition trapVectorMode_of_bits (m : mword 2)
+: TrapVectorMode :=
+
+ let b__0 := m in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then TV_Direct
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then TV_Vector
+ else TV_Reserved.
+
+Definition ExtStatus_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: ExtStatus :=
+
+ let l__128 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__128 0)) then Off
+ else if sumbool_of_bool ((Z.eqb l__128 1)) then Initial
+ else if sumbool_of_bool ((Z.eqb l__128 2)) then Clean
+ else Dirty.
+
+Definition num_of_ExtStatus (arg_ : ExtStatus)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 end).
+
+Definition extStatus_to_bits (e : ExtStatus)
+: mword 2 :=
+
+ match e with
+ | Off => (vec_of_bits [B0;B0] : mword 2)
+ | Initial => (vec_of_bits [B0;B1] : mword 2)
+ | Clean => (vec_of_bits [B1;B0] : mword 2)
+ | Dirty => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition extStatus_of_bits (e : mword 2)
+: M (ExtStatus) :=
+
+ let b__0 := e in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (Off : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (Initial : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (Clean : ExtStatus)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (Dirty : ExtStatus)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_types.sail 264:2 - 269:3" >>= fun _ =>
+ exit tt)
+ : M (ExtStatus).
+
+Definition SATPMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: SATPMode :=
+
+ let l__125 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__125 0)) then Sbare
+ else if sumbool_of_bool ((Z.eqb l__125 1)) then Sv32
+ else if sumbool_of_bool ((Z.eqb l__125 2)) then Sv39
+ else Sv48.
+
+Definition num_of_SATPMode (arg_ : SATPMode)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | Sbare => 0 | Sv32 => 1 | Sv39 => 2 | Sv48 => 3 end).
+
+Definition satp64Mode_of_bits (a : Architecture) (m : mword 4)
+: option SATPMode :=
+
+ match (a, m) with
+ | (g__223, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0] : mword 4))) then Some (Sbare)
+ else
+ match (g__223, b__0) with
+ | (RV32, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1] : mword 4))) then Some (Sv32)
+ else match (RV32, b__0) with | (_, _) => None end
+ | (RV64, b__0) =>
+ if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0] : mword 4))) then Some (Sv39)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1] : mword 4))) then Some (Sv48)
+ else match (RV64, b__0) with | (_, _) => None end
+ | (_, _) => None
+ end
+ end.
+
+Definition uop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)}
+: uop :=
+
+ let l__124 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__124 0)) then RISCV_LUI
+ else RISCV_AUIPC.
+
+Definition num_of_uop (arg_ : uop)
+: {e : Z & ArithFact (0 <= e /\ e <= 1)} :=
+
+ build_ex(match arg_ with | RISCV_LUI => 0 | RISCV_AUIPC => 1 end).
+
+Definition bop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)}
+: bop :=
+
+ let l__119 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__119 0)) then RISCV_BEQ
+ else if sumbool_of_bool ((Z.eqb l__119 1)) then RISCV_BNE
+ else if sumbool_of_bool ((Z.eqb l__119 2)) then RISCV_BLT
+ else if sumbool_of_bool ((Z.eqb l__119 3)) then RISCV_BGE
+ else if sumbool_of_bool ((Z.eqb l__119 4)) then RISCV_BLTU
+ else RISCV_BGEU.
+
+Definition num_of_bop (arg_ : bop)
+: {e : Z & ArithFact (0 <= e /\ e <= 5)} :=
+
+ build_ex(match arg_ with
+ | RISCV_BEQ => 0
+ | RISCV_BNE => 1
+ | RISCV_BLT => 2
+ | RISCV_BGE => 3
+ | RISCV_BLTU => 4
+ | RISCV_BGEU => 5
+ end).
+
+Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)}
+: iop :=
+
+ let l__114 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__114 0)) then RISCV_ADDI
+ else if sumbool_of_bool ((Z.eqb l__114 1)) then RISCV_SLTI
+ else if sumbool_of_bool ((Z.eqb l__114 2)) then RISCV_SLTIU
+ else if sumbool_of_bool ((Z.eqb l__114 3)) then RISCV_XORI
+ else if sumbool_of_bool ((Z.eqb l__114 4)) then RISCV_ORI
+ else RISCV_ANDI.
+
+Definition num_of_iop (arg_ : iop)
+: {e : Z & ArithFact (0 <= e /\ e <= 5)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADDI => 0
+ | RISCV_SLTI => 1
+ | RISCV_SLTIU => 2
+ | RISCV_XORI => 3
+ | RISCV_ORI => 4
+ | RISCV_ANDI => 5
+ end).
+
+Definition sop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: sop :=
+
+ let l__112 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__112 0)) then RISCV_SLLI
+ else if sumbool_of_bool ((Z.eqb l__112 1)) then RISCV_SRLI
+ else RISCV_SRAI.
+
+Definition num_of_sop (arg_ : sop)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RISCV_SLLI => 0 | RISCV_SRLI => 1 | RISCV_SRAI => 2 end).
+
+Definition rop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 9)}
+: rop :=
+
+ let l__103 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__103 0)) then RISCV_ADD
+ else if sumbool_of_bool ((Z.eqb l__103 1)) then RISCV_SUB
+ else if sumbool_of_bool ((Z.eqb l__103 2)) then RISCV_SLL
+ else if sumbool_of_bool ((Z.eqb l__103 3)) then RISCV_SLT
+ else if sumbool_of_bool ((Z.eqb l__103 4)) then RISCV_SLTU
+ else if sumbool_of_bool ((Z.eqb l__103 5)) then RISCV_XOR
+ else if sumbool_of_bool ((Z.eqb l__103 6)) then RISCV_SRL
+ else if sumbool_of_bool ((Z.eqb l__103 7)) then RISCV_SRA
+ else if sumbool_of_bool ((Z.eqb l__103 8)) then RISCV_OR
+ else RISCV_AND.
+
+Definition num_of_rop (arg_ : rop)
+: {e : Z & ArithFact (0 <= e /\ e <= 9)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADD => 0
+ | RISCV_SUB => 1
+ | RISCV_SLL => 2
+ | RISCV_SLT => 3
+ | RISCV_SLTU => 4
+ | RISCV_XOR => 5
+ | RISCV_SRL => 6
+ | RISCV_SRA => 7
+ | RISCV_OR => 8
+ | RISCV_AND => 9
+ end).
+
+Definition ropw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)}
+: ropw :=
+
+ let l__99 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__99 0)) then RISCV_ADDW
+ else if sumbool_of_bool ((Z.eqb l__99 1)) then RISCV_SUBW
+ else if sumbool_of_bool ((Z.eqb l__99 2)) then RISCV_SLLW
+ else if sumbool_of_bool ((Z.eqb l__99 3)) then RISCV_SRLW
+ else RISCV_SRAW.
+
+Definition num_of_ropw (arg_ : ropw)
+: {e : Z & ArithFact (0 <= e /\ e <= 4)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADDW => 0
+ | RISCV_SUBW => 1
+ | RISCV_SLLW => 2
+ | RISCV_SRLW => 3
+ | RISCV_SRAW => 4
+ end).
+
+Definition sopw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: sopw :=
+
+ let l__97 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__97 0)) then RISCV_SLLIW
+ else if sumbool_of_bool ((Z.eqb l__97 1)) then RISCV_SRLIW
+ else RISCV_SRAIW.
+
+Definition num_of_sopw (arg_ : sopw)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | RISCV_SLLIW => 0 | RISCV_SRLIW => 1 | RISCV_SRAIW => 2 end).
+
+Definition amoop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)}
+: amoop :=
+
+ let l__89 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__89 0)) then AMOSWAP
+ else if sumbool_of_bool ((Z.eqb l__89 1)) then AMOADD
+ else if sumbool_of_bool ((Z.eqb l__89 2)) then AMOXOR
+ else if sumbool_of_bool ((Z.eqb l__89 3)) then AMOAND
+ else if sumbool_of_bool ((Z.eqb l__89 4)) then AMOOR
+ else if sumbool_of_bool ((Z.eqb l__89 5)) then AMOMIN
+ else if sumbool_of_bool ((Z.eqb l__89 6)) then AMOMAX
+ else if sumbool_of_bool ((Z.eqb l__89 7)) then AMOMINU
+ else AMOMAXU.
+
+Definition num_of_amoop (arg_ : amoop)
+: {e : Z & ArithFact (0 <= e /\ e <= 8)} :=
+
+ build_ex(match arg_ with
+ | AMOSWAP => 0
+ | AMOADD => 1
+ | AMOXOR => 2
+ | AMOAND => 3
+ | AMOOR => 4
+ | AMOMIN => 5
+ | AMOMAX => 6
+ | AMOMINU => 7
+ | AMOMAXU => 8
+ end).
+
+Definition csrop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: csrop :=
+
+ let l__87 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__87 0)) then CSRRW
+ else if sumbool_of_bool ((Z.eqb l__87 1)) then CSRRS
+ else CSRRC.
+
+Definition num_of_csrop (arg_ : csrop)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | CSRRW => 0 | CSRRS => 1 | CSRRC => 2 end).
+
+Definition sep_forwards (arg_ : unit)
+: string :=
+
+ match arg_ with
+ | tt =>
+ string_append (opt_spc_forwards tt)
+ (string_append "," (string_append (def_spc_forwards tt) ""))
+ end.
+
+Definition _s0_ (_s1_ : string)
+: M (option unit) :=
+
+ (match _s1_ with
+ | _s2_ =>
+ (opt_spc_matches_prefix _s2_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3_ _)) =>
+ let _s4_ := string_drop _s2_ _s3_ in
+ (if ((string_startswith _s4_ ",")) then
+ (match (string_drop _s4_ (projT1 (string_length ","))) with
+ | _s5_ =>
+ (def_spc_matches_prefix _s5_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s6_ _)) =>
+ let p0_ := string_drop _s5_ _s6_ in
+ if ((generic_eq p0_ "")) then Some (tt)
+ else None
+ | _ => None
+ end)
+ : option unit)
+ end)
+ : M (option unit)
+ else returnm (None : option unit))
+ : M (option unit)
+ | _ => returnm (None : option unit)
+ end)
+ : M (option unit)
+ end)
+ : M (option unit).
+
+Definition sep_backwards (arg_ : string)
+: M (unit) :=
+
+ let _s7_ := arg_ in
+ (_s0_ _s7_) >>= fun w__0 : option unit =>
+ (if ((match w__0 with | Some (tt) => true | _ => false end)) then
+ (_s0_ _s7_) >>= fun w__1 : option unit =>
+ (match w__1 with | Some (tt) => returnm (tt : unit) | _ => exit tt : M (unit) end)
+ : M (unit)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (unit).
+
+Definition sep_forwards_matches (arg_ : unit) : bool := match arg_ with | tt => true end.
+
+Definition _s8_ (_s9_ : string)
+: M (option unit) :=
+
+ (match _s9_ with
+ | _s10_ =>
+ (opt_spc_matches_prefix _s10_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s11_ _)) =>
+ let _s12_ := string_drop _s10_ _s11_ in
+ (if ((string_startswith _s12_ ",")) then
+ (match (string_drop _s12_ (projT1 (string_length ","))) with
+ | _s13_ =>
+ (def_spc_matches_prefix _s13_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s14_ _)) =>
+ let p0_ := string_drop _s13_ _s14_ in
+ if ((generic_eq p0_ "")) then Some (tt)
+ else None
+ | _ => None
+ end)
+ : option unit)
+ end)
+ : M (option unit)
+ else returnm (None : option unit))
+ : M (option unit)
+ | _ => returnm (None : option unit)
+ end)
+ : M (option unit)
+ end)
+ : M (option unit).
+
+Definition sep_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s15_ := arg_ in
+ (_s8_ _s15_) >>= fun w__0 : option unit =>
+ (if ((match w__0 with | Some (tt) => true | _ => false end)) then
+ (_s8_ _s15_) >>= fun w__1 : option unit =>
+ (match w__1 with
+ | Some (tt) => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition _s16_ (_s17_ : string)
+: M (option string) :=
+
+ (match _s17_ with
+ | _s18_ =>
+ (opt_spc_matches_prefix _s18_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s19_ _)) =>
+ let _s20_ := string_drop _s18_ _s19_ in
+ (if ((string_startswith _s20_ ",")) then
+ (match (string_drop _s20_ (projT1 (string_length ","))) with
+ | _s21_ =>
+ (def_spc_matches_prefix _s21_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((tt, existT _ _s22_ _)) =>
+ match (string_drop _s21_ _s22_) with | s_ => Some (s_) end
+ | _ => None
+ end)
+ : option string)
+ end)
+ : M (option string)
+ else returnm (None : option string))
+ : M (option string)
+ | _ => returnm (None : option string)
+ end)
+ : M (option string)
+ end)
+ : M (option string).
+
+Definition sep_matches_prefix (arg_ : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s23_ := arg_ in
+ (_s16_ _s23_) >>= fun w__0 : option string =>
+ (if ((match w__0 with | Some (s_) => true | _ => false end)) then
+ (_s16_ _s23_) >>= fun w__1 : option string =>
+ (match w__1 with
+ | Some (s_) =>
+ returnm ((Some
+ ((tt, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((unit * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((unit * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((unit * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bool_bits_forwards (arg_ : bool)
+: mword 1 :=
+
+ match arg_ with
+ | true => (vec_of_bits [B1] : mword 1)
+ | false => (vec_of_bits [B0] : mword 1)
+ end.
+
+Definition bool_bits_backwards (arg_ : mword 1)
+: M (bool) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition bool_bits_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition bool_bits_backwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bool_not_bits_forwards (arg_ : bool)
+: mword 1 :=
+
+ match arg_ with
+ | true => (vec_of_bits [B0] : mword 1)
+ | false => (vec_of_bits [B1] : mword 1)
+ end.
+
+Definition bool_not_bits_backwards (arg_ : mword 1)
+: M (bool) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition bool_not_bits_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition bool_not_bits_backwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else false.
+
+Definition size_bits_forwards (arg_ : word_width)
+: mword 2 :=
+
+ match arg_ with
+ | BYTE => (vec_of_bits [B0;B0] : mword 2)
+ | HALF => (vec_of_bits [B0;B1] : mword 2)
+ | WORD => (vec_of_bits [B1;B0] : mword 2)
+ | DOUBLE => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition size_bits_backwards (arg_ : mword 2)
+: M (word_width) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (BYTE : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (HALF : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (WORD : word_width)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (DOUBLE : word_width)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (word_width).
+
+Definition size_bits_forwards_matches (arg_ : word_width)
+: bool :=
+
+ match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end.
+
+Definition size_bits_backwards_matches (arg_ : mword 2)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true
+ else false.
+
+Definition size_mnemonic_forwards (arg_ : word_width)
+: string :=
+
+ match arg_ with | BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" end.
+
+Definition size_mnemonic_backwards (arg_ : string)
+: M (word_width) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "b")) then returnm (BYTE : word_width)
+ else if ((generic_eq p0_ "h")) then returnm (HALF : word_width)
+ else if ((generic_eq p0_ "w")) then returnm (WORD : word_width)
+ else if ((generic_eq p0_ "d")) then returnm (DOUBLE : word_width)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (word_width).
+
+Definition size_mnemonic_forwards_matches (arg_ : word_width)
+: bool :=
+
+ match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end.
+
+Definition size_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "b")) then true
+ else if ((generic_eq p0_ "h")) then true
+ else if ((generic_eq p0_ "w")) then true
+ else if ((generic_eq p0_ "d")) then true
+ else false.
+
+Definition _s36_ (_s37_ : string)
+: option string :=
+
+ let _s38_ := _s37_ in
+ if ((string_startswith _s38_ "d")) then
+ match (string_drop _s38_ (projT1 (string_length "d"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s32_ (_s33_ : string)
+: option string :=
+
+ let _s34_ := _s33_ in
+ if ((string_startswith _s34_ "w")) then
+ match (string_drop _s34_ (projT1 (string_length "w"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s28_ (_s29_ : string)
+: option string :=
+
+ let _s30_ := _s29_ in
+ if ((string_startswith _s30_ "h")) then
+ match (string_drop _s30_ (projT1 (string_length "h"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s24_ (_s25_ : string)
+: option string :=
+
+ let _s26_ := _s25_ in
+ if ((string_startswith _s26_ "b")) then
+ match (string_drop _s26_ (projT1 (string_length "b"))) with | s_ => Some (s_) end
+ else None.
+
+Definition size_mnemonic_matches_prefix (arg_ : string)
+: M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s27_ := arg_ in
+ (if ((match (_s24_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s24_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((BYTE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s28_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s28_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((HALF, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s32_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s32_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((WORD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s36_ _s27_) with | Some (s_) => true | _ => false end)) then
+ (match (_s36_ _s27_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((DOUBLE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((word_width * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))).
+
+Definition word_width_bytes (width : word_width)
+: {s : Z & ArithFact (s = 1 \/ s = 2 \/ s = 4 \/ s = 8)} :=
+
+ build_ex(match width with | BYTE => 1 | HALF => 2 | WORD => 4 | DOUBLE => 8 end).
+
+Definition zero_reg : regtype := EXTZ 64 (vec_of_bits [B0;B0;B0;B0] : mword 4).
+Hint Unfold zero_reg : sail.
+Definition RegStr (r : mword 64) : string := string_of_bits r.
+
+Definition regval_from_reg (r : mword 64) : mword 64 := r.
+
+Definition regval_into_reg (v : mword 64) : mword 64 := v.
+
+Definition rX (r : Z) `{ArithFact (0 <= r /\ r < 32)}
+: M (mword 64) :=
+
+ let l__55 := r in
+ (if sumbool_of_bool ((Z.eqb l__55 0)) then returnm (zero_reg : mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 1)) then
+ ((read_reg x1_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 2)) then
+ ((read_reg x2_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 3)) then
+ ((read_reg x3_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 4)) then
+ ((read_reg x4_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 5)) then
+ ((read_reg x5_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 6)) then
+ ((read_reg x6_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 7)) then
+ ((read_reg x7_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 8)) then
+ ((read_reg x8_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 9)) then
+ ((read_reg x9_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 10)) then
+ ((read_reg x10_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 11)) then
+ ((read_reg x11_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 12)) then
+ ((read_reg x12_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 13)) then
+ ((read_reg x13_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 14)) then
+ ((read_reg x14_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 15)) then
+ ((read_reg x15_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 16)) then
+ ((read_reg x16_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 17)) then
+ ((read_reg x17_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 18)) then
+ ((read_reg x18_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 19)) then
+ ((read_reg x19_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 20)) then
+ ((read_reg x20_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 21)) then
+ ((read_reg x21_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 22)) then
+ ((read_reg x22_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 23)) then
+ ((read_reg x23_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 24)) then
+ ((read_reg x24_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 25)) then
+ ((read_reg x25_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 26)) then
+ ((read_reg x26_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 27)) then
+ ((read_reg x27_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 28)) then
+ ((read_reg x28_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 29)) then
+ ((read_reg x29_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 30)) then
+ ((read_reg x30_ref) : M (mword 64))
+ : M (mword 64)
+ else if sumbool_of_bool ((Z.eqb l__55 31)) then
+ ((read_reg x31_ref) : M (mword 64))
+ : M (mword 64)
+ else assert_exp' false "invalid register number" >>= fun _ => exit tt) >>= fun v : regtype =>
+ returnm ((regval_from_reg v)
+ : mword 64).
+
+Definition rvfi_wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ r < 32)} : unit := tt.
+
+Definition wX (r : Z) (in_v : mword 64) `{ArithFact (0 <= r /\ r < 32)}
+: M (unit) :=
+
+ let v := regval_into_reg in_v in
+ let l__23 := r in
+ (if sumbool_of_bool ((Z.eqb l__23 0)) then returnm (tt : unit)
+ else if sumbool_of_bool ((Z.eqb l__23 1)) then write_reg x1_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 2)) then write_reg x2_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 3)) then write_reg x3_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 4)) then write_reg x4_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 5)) then write_reg x5_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 6)) then write_reg x6_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 7)) then write_reg x7_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 8)) then write_reg x8_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 9)) then write_reg x9_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 10)) then write_reg x10_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 11)) then write_reg x11_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 12)) then write_reg x12_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 13)) then write_reg x13_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 14)) then write_reg x14_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 15)) then write_reg x15_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 16)) then write_reg x16_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 17)) then write_reg x17_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 18)) then write_reg x18_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 19)) then write_reg x19_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 20)) then write_reg x20_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 21)) then write_reg x21_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 22)) then write_reg x22_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 23)) then write_reg x23_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 24)) then write_reg x24_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 25)) then write_reg x25_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 26)) then write_reg x26_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 27)) then write_reg x27_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 28)) then write_reg x28_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 29)) then write_reg x29_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 30)) then write_reg x30_ref v : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__23 31)) then write_reg x31_ref v : M (unit)
+ else assert_exp' false "invalid register number" >>= fun _ => exit tt) >>
+ returnm ((if sumbool_of_bool ((projT1 (neq_int r 0))) then
+ let '_ := (rvfi_wX r in_v) : unit in
+ if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "x"
+ (String.append (string_of_int r) (String.append " <- " (RegStr v))))
+ else tt
+ else tt)
+ : unit).
+
+Definition reg_name_abi (r : mword 5)
+: M (string) :=
+
+ let b__0 := r in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm ("zero" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm ("ra" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then returnm ("sp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then returnm ("gp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm ("tp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then returnm ("t0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then returnm ("t1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then returnm ("t2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm ("fp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then returnm ("a5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm ("a6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then returnm ("a7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then returnm ("s2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then returnm ("s3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm ("s4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then returnm ("s5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then returnm ("s6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then returnm ("s7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then returnm ("s8" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then returnm ("s9" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then returnm ("s10" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then returnm ("s11" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then returnm ("t3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then returnm ("t4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then returnm ("t5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then returnm ("t6" : string)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_regs.sail 149:2 - 182:3" >>= fun _ =>
+ exit tt)
+ : M (string).
+
+Definition reg_name_forwards (arg_ : mword 5)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm ("zero" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm ("ra" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then returnm ("sp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then returnm ("gp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm ("tp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then returnm ("t0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then returnm ("t1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then returnm ("t2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm ("fp" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then returnm ("a5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm ("a6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then returnm ("a7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then returnm ("s2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then returnm ("s3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm ("s4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then returnm ("s5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then returnm ("s6" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then returnm ("s7" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then returnm ("s8" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then returnm ("s9" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then returnm ("s10" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then returnm ("s11" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then returnm ("t3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then returnm ("t4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then returnm ("t5" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then returnm ("t6" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition reg_name_backwards (arg_ : string)
+: M (mword 5) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "zero")) then returnm ((vec_of_bits [B0;B0;B0;B0;B0] : mword 5) : mword 5)
+ else if ((generic_eq p0_ "ra")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "sp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "gp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "tp")) then
+ returnm ((vec_of_bits [B0;B0;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "fp")) then
+ returnm ((vec_of_bits [B0;B1;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s1")) then
+ returnm ((vec_of_bits [B0;B1;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a0")) then
+ returnm ((vec_of_bits [B0;B1;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a1")) then
+ returnm ((vec_of_bits [B0;B1;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a2")) then
+ returnm ((vec_of_bits [B0;B1;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a3")) then
+ returnm ((vec_of_bits [B0;B1;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a4")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a5")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a6")) then
+ returnm ((vec_of_bits [B1;B0;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "a7")) then
+ returnm ((vec_of_bits [B1;B0;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s2")) then
+ returnm ((vec_of_bits [B1;B0;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s3")) then
+ returnm ((vec_of_bits [B1;B0;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s4")) then
+ returnm ((vec_of_bits [B1;B0;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s5")) then
+ returnm ((vec_of_bits [B1;B0;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s6")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s7")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s8")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s9")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s10")) then
+ returnm ((vec_of_bits [B1;B1;B0;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "s11")) then
+ returnm ((vec_of_bits [B1;B1;B0;B1;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t3")) then
+ returnm ((vec_of_bits [B1;B1;B1;B0;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t4")) then
+ returnm ((vec_of_bits [B1;B1;B1;B0;B1] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t5")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0] : mword 5)
+ : mword 5)
+ else if ((generic_eq p0_ "t6")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B1] : mword 5)
+ : mword 5)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 5).
+
+Definition reg_name_forwards_matches (arg_ : mword 5)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))) then true
+ else false.
+
+Definition reg_name_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "zero")) then true
+ else if ((generic_eq p0_ "ra")) then true
+ else if ((generic_eq p0_ "sp")) then true
+ else if ((generic_eq p0_ "gp")) then true
+ else if ((generic_eq p0_ "tp")) then true
+ else if ((generic_eq p0_ "t0")) then true
+ else if ((generic_eq p0_ "t1")) then true
+ else if ((generic_eq p0_ "t2")) then true
+ else if ((generic_eq p0_ "fp")) then true
+ else if ((generic_eq p0_ "s1")) then true
+ else if ((generic_eq p0_ "a0")) then true
+ else if ((generic_eq p0_ "a1")) then true
+ else if ((generic_eq p0_ "a2")) then true
+ else if ((generic_eq p0_ "a3")) then true
+ else if ((generic_eq p0_ "a4")) then true
+ else if ((generic_eq p0_ "a5")) then true
+ else if ((generic_eq p0_ "a6")) then true
+ else if ((generic_eq p0_ "a7")) then true
+ else if ((generic_eq p0_ "s2")) then true
+ else if ((generic_eq p0_ "s3")) then true
+ else if ((generic_eq p0_ "s4")) then true
+ else if ((generic_eq p0_ "s5")) then true
+ else if ((generic_eq p0_ "s6")) then true
+ else if ((generic_eq p0_ "s7")) then true
+ else if ((generic_eq p0_ "s8")) then true
+ else if ((generic_eq p0_ "s9")) then true
+ else if ((generic_eq p0_ "s10")) then true
+ else if ((generic_eq p0_ "s11")) then true
+ else if ((generic_eq p0_ "t3")) then true
+ else if ((generic_eq p0_ "t4")) then true
+ else if ((generic_eq p0_ "t5")) then true
+ else if ((generic_eq p0_ "t6")) then true
+ else false.
+
+Definition _s164_ (_s165_ : string)
+: option string :=
+
+ let _s166_ := _s165_ in
+ if ((string_startswith _s166_ "t6")) then
+ match (string_drop _s166_ (projT1 (string_length "t6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s160_ (_s161_ : string)
+: option string :=
+
+ let _s162_ := _s161_ in
+ if ((string_startswith _s162_ "t5")) then
+ match (string_drop _s162_ (projT1 (string_length "t5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s156_ (_s157_ : string)
+: option string :=
+
+ let _s158_ := _s157_ in
+ if ((string_startswith _s158_ "t4")) then
+ match (string_drop _s158_ (projT1 (string_length "t4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s152_ (_s153_ : string)
+: option string :=
+
+ let _s154_ := _s153_ in
+ if ((string_startswith _s154_ "t3")) then
+ match (string_drop _s154_ (projT1 (string_length "t3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s148_ (_s149_ : string)
+: option string :=
+
+ let _s150_ := _s149_ in
+ if ((string_startswith _s150_ "s11")) then
+ match (string_drop _s150_ (projT1 (string_length "s11"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s144_ (_s145_ : string)
+: option string :=
+
+ let _s146_ := _s145_ in
+ if ((string_startswith _s146_ "s10")) then
+ match (string_drop _s146_ (projT1 (string_length "s10"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s140_ (_s141_ : string)
+: option string :=
+
+ let _s142_ := _s141_ in
+ if ((string_startswith _s142_ "s9")) then
+ match (string_drop _s142_ (projT1 (string_length "s9"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s136_ (_s137_ : string)
+: option string :=
+
+ let _s138_ := _s137_ in
+ if ((string_startswith _s138_ "s8")) then
+ match (string_drop _s138_ (projT1 (string_length "s8"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s132_ (_s133_ : string)
+: option string :=
+
+ let _s134_ := _s133_ in
+ if ((string_startswith _s134_ "s7")) then
+ match (string_drop _s134_ (projT1 (string_length "s7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s128_ (_s129_ : string)
+: option string :=
+
+ let _s130_ := _s129_ in
+ if ((string_startswith _s130_ "s6")) then
+ match (string_drop _s130_ (projT1 (string_length "s6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s124_ (_s125_ : string)
+: option string :=
+
+ let _s126_ := _s125_ in
+ if ((string_startswith _s126_ "s5")) then
+ match (string_drop _s126_ (projT1 (string_length "s5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s120_ (_s121_ : string)
+: option string :=
+
+ let _s122_ := _s121_ in
+ if ((string_startswith _s122_ "s4")) then
+ match (string_drop _s122_ (projT1 (string_length "s4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s116_ (_s117_ : string)
+: option string :=
+
+ let _s118_ := _s117_ in
+ if ((string_startswith _s118_ "s3")) then
+ match (string_drop _s118_ (projT1 (string_length "s3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s112_ (_s113_ : string)
+: option string :=
+
+ let _s114_ := _s113_ in
+ if ((string_startswith _s114_ "s2")) then
+ match (string_drop _s114_ (projT1 (string_length "s2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s108_ (_s109_ : string)
+: option string :=
+
+ let _s110_ := _s109_ in
+ if ((string_startswith _s110_ "a7")) then
+ match (string_drop _s110_ (projT1 (string_length "a7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s104_ (_s105_ : string)
+: option string :=
+
+ let _s106_ := _s105_ in
+ if ((string_startswith _s106_ "a6")) then
+ match (string_drop _s106_ (projT1 (string_length "a6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s100_ (_s101_ : string)
+: option string :=
+
+ let _s102_ := _s101_ in
+ if ((string_startswith _s102_ "a5")) then
+ match (string_drop _s102_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s96_ (_s97_ : string)
+: option string :=
+
+ let _s98_ := _s97_ in
+ if ((string_startswith _s98_ "a4")) then
+ match (string_drop _s98_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s92_ (_s93_ : string)
+: option string :=
+
+ let _s94_ := _s93_ in
+ if ((string_startswith _s94_ "a3")) then
+ match (string_drop _s94_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s88_ (_s89_ : string)
+: option string :=
+
+ let _s90_ := _s89_ in
+ if ((string_startswith _s90_ "a2")) then
+ match (string_drop _s90_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s84_ (_s85_ : string)
+: option string :=
+
+ let _s86_ := _s85_ in
+ if ((string_startswith _s86_ "a1")) then
+ match (string_drop _s86_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s80_ (_s81_ : string)
+: option string :=
+
+ let _s82_ := _s81_ in
+ if ((string_startswith _s82_ "a0")) then
+ match (string_drop _s82_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s76_ (_s77_ : string)
+: option string :=
+
+ let _s78_ := _s77_ in
+ if ((string_startswith _s78_ "s1")) then
+ match (string_drop _s78_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s72_ (_s73_ : string)
+: option string :=
+
+ let _s74_ := _s73_ in
+ if ((string_startswith _s74_ "fp")) then
+ match (string_drop _s74_ (projT1 (string_length "fp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s68_ (_s69_ : string)
+: option string :=
+
+ let _s70_ := _s69_ in
+ if ((string_startswith _s70_ "t2")) then
+ match (string_drop _s70_ (projT1 (string_length "t2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s64_ (_s65_ : string)
+: option string :=
+
+ let _s66_ := _s65_ in
+ if ((string_startswith _s66_ "t1")) then
+ match (string_drop _s66_ (projT1 (string_length "t1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s60_ (_s61_ : string)
+: option string :=
+
+ let _s62_ := _s61_ in
+ if ((string_startswith _s62_ "t0")) then
+ match (string_drop _s62_ (projT1 (string_length "t0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s56_ (_s57_ : string)
+: option string :=
+
+ let _s58_ := _s57_ in
+ if ((string_startswith _s58_ "tp")) then
+ match (string_drop _s58_ (projT1 (string_length "tp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s52_ (_s53_ : string)
+: option string :=
+
+ let _s54_ := _s53_ in
+ if ((string_startswith _s54_ "gp")) then
+ match (string_drop _s54_ (projT1 (string_length "gp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s48_ (_s49_ : string)
+: option string :=
+
+ let _s50_ := _s49_ in
+ if ((string_startswith _s50_ "sp")) then
+ match (string_drop _s50_ (projT1 (string_length "sp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s44_ (_s45_ : string)
+: option string :=
+
+ let _s46_ := _s45_ in
+ if ((string_startswith _s46_ "ra")) then
+ match (string_drop _s46_ (projT1 (string_length "ra"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s40_ (_s41_ : string)
+: option string :=
+
+ let _s42_ := _s41_ in
+ if ((string_startswith _s42_ "zero")) then
+ match (string_drop _s42_ (projT1 (string_length "zero"))) with | s_ => Some (s_) end
+ else None.
+
+Definition reg_name_matches_prefix (arg_ : string)
+: M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s43_ := arg_ in
+ (if ((match (_s40_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s40_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s44_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s44_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s48_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s48_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s52_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s52_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s56_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s56_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s60_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s60_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s64_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s64_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s68_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s68_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s72_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s72_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s76_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s76_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s80_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s80_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s84_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s84_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s88_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s88_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s92_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s92_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s96_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s96_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s100_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s100_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s104_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s104_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s108_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s108_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s112_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s112_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s116_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s116_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s120_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s120_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s124_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s124_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s128_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s128_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s132_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s132_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s136_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s136_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s140_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s140_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s144_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s144_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s148_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s148_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s152_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s152_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B0;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s156_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s156_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B0;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s160_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s160_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s164_ _s43_) with | Some (s_) => true | _ => false end)) then
+ (match (_s164_ _s43_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B1] : mword 5), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition creg_name_forwards (arg_ : mword 3)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm ("s0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm ("s1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm ("a0" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm ("a1" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm ("a2" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm ("a3" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm ("a4" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm ("a5" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition creg_name_backwards (arg_ : string)
+: M (mword 3) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "s0")) then returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "s1")) then returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a0")) then returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a1")) then returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a2")) then returnm ((vec_of_bits [B1;B0;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a3")) then returnm ((vec_of_bits [B1;B0;B1] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a4")) then returnm ((vec_of_bits [B1;B1;B0] : mword 3) : mword 3)
+ else if ((generic_eq p0_ "a5")) then returnm ((vec_of_bits [B1;B1;B1] : mword 3) : mword 3)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 3).
+
+Definition creg_name_forwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else false.
+
+Definition creg_name_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "s0")) then true
+ else if ((generic_eq p0_ "s1")) then true
+ else if ((generic_eq p0_ "a0")) then true
+ else if ((generic_eq p0_ "a1")) then true
+ else if ((generic_eq p0_ "a2")) then true
+ else if ((generic_eq p0_ "a3")) then true
+ else if ((generic_eq p0_ "a4")) then true
+ else if ((generic_eq p0_ "a5")) then true
+ else false.
+
+Definition _s196_ (_s197_ : string)
+: option string :=
+
+ let _s198_ := _s197_ in
+ if ((string_startswith _s198_ "a5")) then
+ match (string_drop _s198_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s192_ (_s193_ : string)
+: option string :=
+
+ let _s194_ := _s193_ in
+ if ((string_startswith _s194_ "a4")) then
+ match (string_drop _s194_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s188_ (_s189_ : string)
+: option string :=
+
+ let _s190_ := _s189_ in
+ if ((string_startswith _s190_ "a3")) then
+ match (string_drop _s190_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s184_ (_s185_ : string)
+: option string :=
+
+ let _s186_ := _s185_ in
+ if ((string_startswith _s186_ "a2")) then
+ match (string_drop _s186_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s180_ (_s181_ : string)
+: option string :=
+
+ let _s182_ := _s181_ in
+ if ((string_startswith _s182_ "a1")) then
+ match (string_drop _s182_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s176_ (_s177_ : string)
+: option string :=
+
+ let _s178_ := _s177_ in
+ if ((string_startswith _s178_ "a0")) then
+ match (string_drop _s178_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s172_ (_s173_ : string)
+: option string :=
+
+ let _s174_ := _s173_ in
+ if ((string_startswith _s174_ "s1")) then
+ match (string_drop _s174_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s168_ (_s169_ : string)
+: option string :=
+
+ let _s170_ := _s169_ in
+ if ((string_startswith _s170_ "s0")) then
+ match (string_drop _s170_ (projT1 (string_length "s0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition creg_name_matches_prefix (arg_ : string)
+: M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s171_ := arg_ in
+ (if ((match (_s168_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s168_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s172_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s172_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s176_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s176_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s180_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s180_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s184_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s184_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s188_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s188_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s192_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s192_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s196_ _s171_) with | Some (s_) => true | _ => false end)) then
+ (match (_s196_ _s171_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1] : mword 3), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition init_base_regs '(tt : unit)
+: M (unit) :=
+
+ write_reg x1_ref zero_reg >>
+ write_reg x2_ref zero_reg >>
+ write_reg x3_ref zero_reg >>
+ write_reg x4_ref zero_reg >>
+ write_reg x5_ref zero_reg >>
+ write_reg x6_ref zero_reg >>
+ write_reg x7_ref zero_reg >>
+ write_reg x8_ref zero_reg >>
+ write_reg x9_ref zero_reg >>
+ write_reg x10_ref zero_reg >>
+ write_reg x11_ref zero_reg >>
+ write_reg x12_ref zero_reg >>
+ write_reg x13_ref zero_reg >>
+ write_reg x14_ref zero_reg >>
+ write_reg x15_ref zero_reg >>
+ write_reg x16_ref zero_reg >>
+ write_reg x17_ref zero_reg >>
+ write_reg x18_ref zero_reg >>
+ write_reg x19_ref zero_reg >>
+ write_reg x20_ref zero_reg >>
+ write_reg x21_ref zero_reg >>
+ write_reg x22_ref zero_reg >>
+ write_reg x23_ref zero_reg >>
+ write_reg x24_ref zero_reg >>
+ write_reg x25_ref zero_reg >>
+ write_reg x26_ref zero_reg >>
+ write_reg x27_ref zero_reg >>
+ write_reg x28_ref zero_reg >>
+ write_reg x29_ref zero_reg >>
+ write_reg x30_ref zero_reg >> write_reg x31_ref zero_reg : M (unit).
+
+Definition get_arch_pc '(tt : unit)
+: M (mword 64) :=
+
+ ((read_reg PC_ref) : M (mword 64))
+ : M (mword 64).
+
+Definition get_next_pc '(tt : unit)
+: M (mword 64) :=
+
+ ((read_reg nextPC_ref) : M (mword 64))
+ : M (mword 64).
+
+Definition set_next_pc (pc : mword 64) : M (unit) := write_reg nextPC_ref pc : M (unit).
+
+Definition tick_pc '(tt : unit)
+: M (unit) :=
+
+ ((read_reg nextPC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ write_reg PC_ref w__0
+ : M (unit).
+
+Definition Mk_Misa (v : mword 64) : Misa := {| Misa_Misa_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Misa_bits (v : Misa) : mword 64 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0.
+
+Definition _set_Misa_bits (r_ref : register_ref regstate register_value Misa) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_bits (v : Misa) (x : mword 64)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Misa_MXL (v : Misa) : mword 2 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62.
+
+Definition _set_Misa_MXL (r_ref : register_ref regstate register_value Misa) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec v 1 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_MXL (v : Misa) (x : mword 2)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Misa_Z (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25.
+
+Definition _set_Misa_Z (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Z (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_Y (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24.
+
+Definition _set_Misa_Y (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Y (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_X (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23.
+
+Definition _set_Misa_X (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_X (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_W (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22.
+
+Definition _set_Misa_W (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_W (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_V (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21.
+
+Definition _set_Misa_V (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_V (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_U (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20.
+
+Definition _set_Misa_U (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_U (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_T (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19.
+
+Definition _set_Misa_T (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_T (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_S (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18.
+
+Definition _set_Misa_S (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_S (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_R (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17.
+
+Definition _set_Misa_R (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_R (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_Q (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16.
+
+Definition _set_Misa_Q (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_Q (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_P (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15.
+
+Definition _set_Misa_P (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_P (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_O (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14.
+
+Definition _set_Misa_O (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_O (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_N (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13.
+
+Definition _set_Misa_N (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_N (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_M (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12.
+
+Definition _set_Misa_M (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_M (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_L (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11.
+
+Definition _set_Misa_L (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_L (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_K (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10.
+
+Definition _set_Misa_K (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_K (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_J (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9.
+
+Definition _set_Misa_J (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_J (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_I (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8.
+
+Definition _set_Misa_I (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_I (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_H (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7.
+
+Definition _set_Misa_H (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_H (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_G (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6.
+
+Definition _set_Misa_G (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_G (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_F (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5.
+
+Definition _set_Misa_F (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_F (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_E (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4.
+
+Definition _set_Misa_E (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_E (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_D (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3.
+
+Definition _set_Misa_D (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_D (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_C (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2.
+
+Definition _set_Misa_C (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_C (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_B (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1.
+
+Definition _set_Misa_B (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_B (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Misa_A (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0.
+
+Definition _set_Misa_A (r_ref : register_ref regstate register_value Misa) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Misa in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Misa_A (v : Misa) (x : mword 1)
+: Misa :=
+
+ {[ v with
+ Misa_Misa_chunk_0 :=
+ (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_misa (m : Misa) (v : mword 64)
+: M (Misa) :=
+
+ (if ((sys_enable_writable_misa tt)) then
+ let v := Mk_Misa v in
+ (and_boolM (returnm ((eq_vec (_get_Misa_C v) ((bool_to_bits false) : mword 1)) : bool))
+ (((read_reg nextPC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ (bit_to_bool (access_vec_dec w__0 1)) >>= fun w__1 : bool =>
+ returnm ((Bool.eqb w__1 true)
+ : bool))) >>= fun w__2 : bool =>
+ returnm ((if sumbool_of_bool (w__2) then m
+ else _update_Misa_C m (_get_Misa_C v))
+ : Misa)
+ else returnm (m : Misa))
+ : M (Misa).
+
+Definition haveAtomics '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_A w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveRVC '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveMulDiv '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_M w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveSupMode '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_S w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveUsrMode '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_U w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition haveNExt '(tt : unit)
+: M (bool) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_N w__0) ((bool_to_bits true) : mword 1))
+ : bool).
+
+Definition Mk_Mstatus (v : mword 64)
+: Mstatus :=
+
+ {| Mstatus_Mstatus_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Mstatus_bits (v : Mstatus)
+: mword 64 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0.
+
+Definition _set_Mstatus_bits (r_ref : register_ref regstate register_value Mstatus) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_bits (v : Mstatus) (x : mword 64)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Mstatus_SD (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63.
+
+Definition _set_Mstatus_SD (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SD (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TSR (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22.
+
+Definition _set_Mstatus_TSR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TSR (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TW (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21.
+
+Definition _set_Mstatus_TW (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TW (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_TVM (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20.
+
+Definition _set_Mstatus_TVM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_TVM (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MXR (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19.
+
+Definition _set_Mstatus_MXR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MXR (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SUM (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18.
+
+Definition _set_Mstatus_SUM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SUM (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MPRV (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17.
+
+Definition _set_Mstatus_MPRV (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPRV (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_XS (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15.
+
+Definition _set_Mstatus_XS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_XS (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_FS (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13.
+
+Definition _set_Mstatus_FS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_FS (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_MPP (v : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11.
+
+Definition _set_Mstatus_MPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec v 1 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPP (v : Mstatus) (x : mword 2)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Mstatus_SPP (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8.
+
+Definition _set_Mstatus_SPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SPP (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7.
+
+Definition _set_Mstatus_MPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5.
+
+Definition _set_Mstatus_SPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_UPIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4.
+
+Definition _set_Mstatus_UPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_UPIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_MIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3.
+
+Definition _set_Mstatus_MIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_MIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_SIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1.
+
+Definition _set_Mstatus_SIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_SIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mstatus_UIE (v : Mstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0.
+
+Definition _set_Mstatus_UIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Mstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mstatus_UIE (v : Mstatus) (x : mword 1)
+: Mstatus :=
+
+ {[ v with
+ Mstatus_Mstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition effectivePrivilege (m : Mstatus) (priv : Privilege)
+: M (Privilege) :=
+
+ (if ((eq_vec (_get_Mstatus_MPRV m) ((bool_to_bits true) : mword 1))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (privLevel_of_bits (_get_Mstatus_MPP w__0))
+ : M (Privilege)
+ else read_reg cur_privilege_ref : M (Privilege))
+ : M (Privilege).
+
+Definition get_mstatus_SXL (m : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec (_get_Mstatus_bits m) 35 34.
+
+Definition set_mstatus_SXL (m : Mstatus) (a : mword 2)
+: Mstatus :=
+
+ let m := update_subrange_vec_dec (_get_Mstatus_bits m) 35 34 a in
+ Mk_Mstatus m.
+
+Definition get_mstatus_UXL (m : Mstatus)
+: mword 2 :=
+
+ subrange_vec_dec (_get_Mstatus_bits m) 33 32.
+
+Definition set_mstatus_UXL (m : Mstatus) (a : mword 2)
+: Mstatus :=
+
+ let m := update_subrange_vec_dec (_get_Mstatus_bits m) 33 32 a in
+ Mk_Mstatus m.
+
+Definition legalize_mstatus (o : Mstatus) (v : mword 64)
+: M (Mstatus) :=
+
+ let m : Mstatus := Mk_Mstatus v in
+ let m := _update_Mstatus_XS m (extStatus_to_bits Off) in
+ (or_boolM
+ ((extStatus_of_bits (_get_Mstatus_FS m)) >>= fun w__0 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__0) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))
+ ((extStatus_of_bits (_get_Mstatus_XS m)) >>= fun w__1 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__1) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))) >>= fun w__2 : bool =>
+ let m := _update_Mstatus_SD m ((bool_to_bits w__2) : mword 1) in
+ let m := set_mstatus_SXL m (get_mstatus_SXL o) in
+ let m := set_mstatus_UXL m (get_mstatus_UXL o) in
+ let m := _update_Mstatus_UPIE m ((bool_to_bits false) : mword 1) in
+ let m := _update_Mstatus_UIE m ((bool_to_bits false) : mword 1) in
+ returnm (m
+ : Mstatus).
+
+Definition cur_Architecture '(tt : unit)
+: M (Architecture) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | Machine => read_reg misa_ref >>= fun w__1 : Misa => returnm ((_get_Misa_MXL w__1) : mword 2)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus => returnm ((get_mstatus_SXL w__2) : mword 2)
+ | User =>
+ read_reg mstatus_ref >>= fun w__3 : Mstatus => returnm ((get_mstatus_UXL w__3) : mword 2)
+ end) >>= fun a : arch_xlen =>
+ (match (architecture a) with
+ | Some (a) => returnm (a : Architecture)
+ | None => (internal_error "Invalid current architecture") : M (Architecture)
+ end)
+ : M (Architecture).
+
+Definition in32BitMode '(tt : unit)
+: M (bool) :=
+
+ (cur_Architecture tt) >>= fun w__0 : Architecture => returnm ((generic_eq w__0 RV32) : bool).
+
+Definition Mk_Minterrupts (v : mword 64)
+: Minterrupts :=
+
+ {| Minterrupts_Minterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Minterrupts_bits (v : Minterrupts)
+: mword 64 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0.
+
+Definition _set_Minterrupts_bits
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_bits (v : Minterrupts) (x : mword 64)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Minterrupts_MEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11.
+
+Definition _set_Minterrupts_MEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_SEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9.
+
+Definition _set_Minterrupts_SEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_SEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_UEI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8.
+
+Definition _set_Minterrupts_UEI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_UEI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_MTI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7.
+
+Definition _set_Minterrupts_MTI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MTI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_STI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5.
+
+Definition _set_Minterrupts_STI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_STI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_UTI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4.
+
+Definition _set_Minterrupts_UTI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_UTI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_MSI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3.
+
+Definition _set_Minterrupts_MSI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_MSI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_SSI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1.
+
+Definition _set_Minterrupts_SSI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_SSI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Minterrupts_USI (v : Minterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0.
+
+Definition _set_Minterrupts_USI
+(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Minterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Minterrupts_USI (v : Minterrupts) (x : mword 1)
+: Minterrupts :=
+
+ {[ v with
+ Minterrupts_Minterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_mip (o : Minterrupts) (v : mword 64)
+: M (Minterrupts) :=
+
+ let v := Mk_Minterrupts v in
+ let m := _update_Minterrupts_SEI o (_get_Minterrupts_SEI v) in
+ let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in
+ let m := _update_Minterrupts_SSI m (_get_Minterrupts_SSI v) in
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m := _update_Minterrupts_UEI m (_get_Minterrupts_UEI v) in
+ let m := _update_Minterrupts_UTI m (_get_Minterrupts_UTI v) in
+ _update_Minterrupts_USI m (_get_Minterrupts_USI v)
+ else m)
+ : Minterrupts).
+
+Definition legalize_mie (o : Minterrupts) (v : mword 64)
+: M (Minterrupts) :=
+
+ let v := Mk_Minterrupts v in
+ let m := _update_Minterrupts_MEI o (_get_Minterrupts_MEI v) in
+ let m := _update_Minterrupts_MTI m (_get_Minterrupts_MTI v) in
+ let m := _update_Minterrupts_MSI m (_get_Minterrupts_MSI v) in
+ let m := _update_Minterrupts_SEI m (_get_Minterrupts_SEI v) in
+ let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in
+ let m := _update_Minterrupts_SSI m (_get_Minterrupts_SSI v) in
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m := _update_Minterrupts_UEI m (_get_Minterrupts_UEI v) in
+ let m := _update_Minterrupts_UTI m (_get_Minterrupts_UTI v) in
+ _update_Minterrupts_USI m (_get_Minterrupts_USI v)
+ else m)
+ : Minterrupts).
+
+Definition legalize_mideleg (o : Minterrupts) (v : mword 64)
+: Minterrupts :=
+
+ let m := Mk_Minterrupts v in
+ let m := _update_Minterrupts_MEI m ((bool_to_bits false) : mword 1) in
+ let m := _update_Minterrupts_MTI m ((bool_to_bits false) : mword 1) in
+ _update_Minterrupts_MSI m ((bool_to_bits false) : mword 1).
+
+Definition Mk_Medeleg (v : mword 64)
+: Medeleg :=
+
+ {| Medeleg_Medeleg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Medeleg_bits (v : Medeleg)
+: mword 64 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0.
+
+Definition _set_Medeleg_bits (r_ref : register_ref regstate register_value Medeleg) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_bits (v : Medeleg) (x : mword 64)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15.
+
+Definition _set_Medeleg_SAMO_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13.
+
+Definition _set_Medeleg_Load_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Page_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12.
+
+Definition _set_Medeleg_Fetch_Page_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Page_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_MEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10.
+
+Definition _set_Medeleg_MEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_MEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9.
+
+Definition _set_Medeleg_SEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_UEnvCall (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8.
+
+Definition _set_Medeleg_UEnvCall
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_UEnvCall (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7.
+
+Definition _set_Medeleg_SAMO_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_SAMO_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6.
+
+Definition _set_Medeleg_SAMO_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_SAMO_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5.
+
+Definition _set_Medeleg_Load_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Load_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4.
+
+Definition _set_Medeleg_Load_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Load_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Breakpoint (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3.
+
+Definition _set_Medeleg_Breakpoint
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Breakpoint (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Illegal_Instr (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2.
+
+Definition _set_Medeleg_Illegal_Instr
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Illegal_Instr (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Access_Fault (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1.
+
+Definition _set_Medeleg_Fetch_Access_Fault
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Access_Fault (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Medeleg_Fetch_Addr_Align (v : Medeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0.
+
+Definition _set_Medeleg_Fetch_Addr_Align
+(r_ref : register_ref regstate register_value Medeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Medeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Medeleg_Fetch_Addr_Align (v : Medeleg) (x : mword 1)
+: Medeleg :=
+
+ {[ v with
+ Medeleg_Medeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_medeleg (o : Medeleg) (v : mword 64)
+: Medeleg :=
+
+ let m := Mk_Medeleg v in
+ _update_Medeleg_MEnvCall m ((bool_to_bits false) : mword 1).
+
+Definition Mk_Mtvec (v : mword 64)
+: Mtvec :=
+
+ {| Mtvec_Mtvec_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Mtvec_bits (v : Mtvec)
+: mword 64 :=
+
+ subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0.
+
+Definition _set_Mtvec_bits (r_ref : register_ref regstate register_value Mtvec) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_bits (v : Mtvec) (x : mword 64)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Mtvec_Base (v : Mtvec)
+: mword 62 :=
+
+ subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2.
+
+Definition _set_Mtvec_Base (r_ref : register_ref regstate register_value Mtvec) (v : mword 62)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec v 61 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_Base (v : Mtvec) (x : mword 62)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec x 61 0)) ]}.
+
+Definition _get_Mtvec_Mode (v : Mtvec) : mword 2 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0.
+
+Definition _set_Mtvec_Mode (r_ref : register_ref regstate register_value Mtvec) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec v 1 0)) ]}
+ : Mtvec in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mtvec_Mode (v : Mtvec) (x : mword 2)
+: Mtvec :=
+
+ {[ v with
+ Mtvec_Mtvec_chunk_0 :=
+ (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec x 1 0)) ]}.
+
+Definition legalize_tvec (o : Mtvec) (v : mword 64)
+: Mtvec :=
+
+ let v := Mk_Mtvec v in
+ match (trapVectorMode_of_bits (_get_Mtvec_Mode v)) with
+ | TV_Direct => v
+ | TV_Vector => v
+ | _ => _update_Mtvec_Mode v (_get_Mtvec_Mode o)
+ end.
+
+Definition Mk_Mcause (v : mword 64)
+: Mcause :=
+
+ {| Mcause_Mcause_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Mcause_bits (v : Mcause)
+: mword 64 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0.
+
+Definition _set_Mcause_bits (r_ref : register_ref regstate register_value Mcause) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_bits (v : Mcause) (x : mword 64)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Mcause_IsInterrupt (v : Mcause)
+: mword 1 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63.
+
+Definition _set_Mcause_IsInterrupt
+(r_ref : register_ref regstate register_value Mcause) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_IsInterrupt (v : Mcause) (x : mword 1)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Mcause_Cause (v : Mcause)
+: mword 63 :=
+
+ subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0.
+
+Definition _set_Mcause_Cause (r_ref : register_ref regstate register_value Mcause) (v : mword 63)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec v 62 0)) ]}
+ : Mcause in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Mcause_Cause (v : Mcause) (x : mword 63)
+: Mcause :=
+
+ {[ v with
+ Mcause_Mcause_chunk_0 :=
+ (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec x 62 0)) ]}.
+
+Definition tvec_addr (m : Mtvec) (c : Mcause)
+: option (mword 64) :=
+
+ let base : xlenbits := concat_vec (_get_Mtvec_Base m) (vec_of_bits [B0;B0] : mword 2) in
+ match (trapVectorMode_of_bits (_get_Mtvec_Mode m)) with
+ | TV_Direct => Some (base)
+ | TV_Vector =>
+ if ((eq_vec (_get_Mcause_IsInterrupt c) ((bool_to_bits true) : mword 1))) then
+ Some
+ (add_vec base (shiftl (EXTZ 64 (_get_Mcause_Cause c)) 2))
+ else Some (base)
+ | TV_Reserved => None
+ end.
+
+Definition legalize_xepc (v : mword 64)
+: M (mword 64) :=
+
+ (or_boolM (returnm ((sys_enable_writable_misa tt) : bool))
+ (read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))
+ : bool))) >>= fun w__1 : bool =>
+ returnm ((if sumbool_of_bool (w__1) then update_vec_dec v 0 B0
+ else and_vec v (EXTS 64 (vec_of_bits [B1;B0;B0] : mword 3)))
+ : mword 64).
+
+Definition pc_alignment_mask '(tt : unit)
+: M (mword 64) :=
+
+ read_reg misa_ref >>= fun w__0 : Misa =>
+ returnm ((not_vec
+ (EXTZ 64
+ (if ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))) then
+ (vec_of_bits [B0;B0] : mword 2)
+ else (vec_of_bits [B1;B0] : mword 2))))
+ : mword 64).
+
+Definition Mk_Counteren (v : mword 32)
+: Counteren :=
+
+ {| Counteren_Counteren_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Counteren_bits (v : Counteren)
+: mword 32 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0.
+
+Definition _set_Counteren_bits
+(r_ref : register_ref regstate register_value Counteren) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_bits (v : Counteren) (x : mword 32)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Counteren_HPM (v : Counteren)
+: mword 29 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3.
+
+Definition _set_Counteren_HPM
+(r_ref : register_ref regstate register_value Counteren) (v : mword 29)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec v 28 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_HPM (v : Counteren) (x : mword 29)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec x 28 0)) ]}.
+
+Definition _get_Counteren_IR (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2.
+
+Definition _set_Counteren_IR (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_IR (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Counteren_TM (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1.
+
+Definition _set_Counteren_TM (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_TM (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Counteren_CY (v : Counteren)
+: mword 1 :=
+
+ subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0.
+
+Definition _set_Counteren_CY (r_ref : register_ref regstate register_value Counteren) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Counteren in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Counteren_CY (v : Counteren) (x : mword 1)
+: Counteren :=
+
+ {[ v with
+ Counteren_Counteren_chunk_0 :=
+ (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_mcounteren (c : Counteren) (v : mword 64)
+: M (Counteren) :=
+
+ (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 =>
+ let c := _update_Counteren_IR c (w__0 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 =>
+ let c := _update_Counteren_TM c (w__1 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 =>
+ let c := _update_Counteren_CY c (w__2 : mword 1) in
+ returnm (c
+ : Counteren).
+
+Definition legalize_scounteren (c : Counteren) (v : mword 64)
+: M (Counteren) :=
+
+ (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 =>
+ let c := _update_Counteren_IR c (w__0 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 =>
+ let c := _update_Counteren_TM c (w__1 : mword 1) in
+ (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 =>
+ let c := _update_Counteren_CY c (w__2 : mword 1) in
+ returnm (c
+ : Counteren).
+
+Definition retire_instruction '(tt : unit)
+: M (unit) :=
+
+ read_reg minstret_written_ref >>= fun w__0 : bool =>
+ (if ((Bool.eqb w__0 true)) then write_reg minstret_written_ref false : M (unit)
+ else
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg minstret_ref (add_vec_int w__1 1)
+ : M (unit))
+ : M (unit).
+
+Definition Mk_Sstatus (v : mword 64)
+: Sstatus :=
+
+ {| Sstatus_Sstatus_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Sstatus_bits (v : Sstatus)
+: mword 64 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0.
+
+Definition _set_Sstatus_bits (r_ref : register_ref regstate register_value Sstatus) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_bits (v : Sstatus) (x : mword 64)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Sstatus_SD (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63.
+
+Definition _set_Sstatus_SD (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SD (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_MXR (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19.
+
+Definition _set_Sstatus_MXR (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_MXR (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SUM (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18.
+
+Definition _set_Sstatus_SUM (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SUM (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_XS (v : Sstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15.
+
+Definition _set_Sstatus_XS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_XS (v : Sstatus) (x : mword 2)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Sstatus_FS (v : Sstatus)
+: mword 2 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13.
+
+Definition _set_Sstatus_FS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_FS (v : Sstatus) (x : mword 2)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Sstatus_SPP (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8.
+
+Definition _set_Sstatus_SPP (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SPP (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SPIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5.
+
+Definition _set_Sstatus_SPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SPIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_UPIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4.
+
+Definition _set_Sstatus_UPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_UPIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_SIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1.
+
+Definition _set_Sstatus_SIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_SIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sstatus_UIE (v : Sstatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0.
+
+Definition _set_Sstatus_UIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sstatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sstatus_UIE (v : Sstatus) (x : mword 1)
+: Sstatus :=
+
+ {[ v with
+ Sstatus_Sstatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition get_sstatus_UXL (s : Sstatus)
+: mword 2 :=
+
+ let m := Mk_Mstatus (_get_Sstatus_bits s) in
+ get_mstatus_UXL m.
+
+Definition set_sstatus_UXL (s : Sstatus) (a : mword 2)
+: Sstatus :=
+
+ let m := Mk_Mstatus (_get_Sstatus_bits s) in
+ let m := set_mstatus_UXL m a in
+ Mk_Sstatus (_get_Mstatus_bits m).
+
+Definition lower_mstatus (m : Mstatus)
+: Sstatus :=
+
+ let s := Mk_Sstatus (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sstatus_SD s (_get_Mstatus_SD m) in
+ let s := set_sstatus_UXL s (get_mstatus_UXL m) in
+ let s := _update_Sstatus_MXR s (_get_Mstatus_MXR m) in
+ let s := _update_Sstatus_SUM s (_get_Mstatus_SUM m) in
+ let s := _update_Sstatus_XS s (_get_Mstatus_XS m) in
+ let s := _update_Sstatus_FS s (_get_Mstatus_FS m) in
+ let s := _update_Sstatus_SPP s (_get_Mstatus_SPP m) in
+ let s := _update_Sstatus_SPIE s (_get_Mstatus_SPIE m) in
+ let s := _update_Sstatus_UPIE s (_get_Mstatus_UPIE m) in
+ let s := _update_Sstatus_SIE s (_get_Mstatus_SIE m) in
+ _update_Sstatus_UIE s (_get_Mstatus_UIE m).
+
+Definition lift_sstatus (m : Mstatus) (s : Sstatus)
+: M (Mstatus) :=
+
+ let m := _update_Mstatus_MXR m (_get_Sstatus_MXR s) in
+ let m := _update_Mstatus_SUM m (_get_Sstatus_SUM s) in
+ let m := _update_Mstatus_XS m (_get_Sstatus_XS s) in
+ let m := _update_Mstatus_FS m (_get_Sstatus_FS s) in
+ (or_boolM
+ ((extStatus_of_bits (_get_Mstatus_FS m)) >>= fun w__0 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__0) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))
+ ((extStatus_of_bits (_get_Mstatus_XS m)) >>= fun w__1 : ExtStatus =>
+ returnm ((eq_vec (extStatus_to_bits w__1) ((extStatus_to_bits Dirty) : mword 2))
+ : bool))) >>= fun w__2 : bool =>
+ let m := _update_Mstatus_SD m ((bool_to_bits w__2) : mword 1) in
+ let m := _update_Mstatus_SPP m (_get_Sstatus_SPP s) in
+ let m := _update_Mstatus_SPIE m (_get_Sstatus_SPIE s) in
+ let m := _update_Mstatus_UPIE m (_get_Sstatus_UPIE s) in
+ let m := _update_Mstatus_SIE m (_get_Sstatus_SIE s) in
+ let m := _update_Mstatus_UIE m (_get_Sstatus_UIE s) in
+ returnm (m
+ : Mstatus).
+
+Definition legalize_sstatus (m : Mstatus) (v : mword 64)
+: M (Mstatus) :=
+
+ (lift_sstatus m (Mk_Sstatus v))
+ : M (Mstatus).
+
+Definition Mk_Sedeleg (v : mword 64)
+: Sedeleg :=
+
+ {| Sedeleg_Sedeleg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Sedeleg_bits (v : Sedeleg)
+: mword 64 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0.
+
+Definition _set_Sedeleg_bits (r_ref : register_ref regstate register_value Sedeleg) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_bits (v : Sedeleg) (x : mword 64)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Sedeleg_UEnvCall (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8.
+
+Definition _set_Sedeleg_UEnvCall
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_UEnvCall (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_SAMO_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7.
+
+Definition _set_Sedeleg_SAMO_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_SAMO_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_SAMO_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6.
+
+Definition _set_Sedeleg_SAMO_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_SAMO_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Load_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5.
+
+Definition _set_Sedeleg_Load_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Load_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Load_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4.
+
+Definition _set_Sedeleg_Load_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Load_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Breakpoint (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3.
+
+Definition _set_Sedeleg_Breakpoint
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Breakpoint (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Illegal_Instr (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2.
+
+Definition _set_Sedeleg_Illegal_Instr
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Illegal_Instr (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Fetch_Access_Fault (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1.
+
+Definition _set_Sedeleg_Fetch_Access_Fault
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Fetch_Access_Fault (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sedeleg_Fetch_Addr_Align (v : Sedeleg)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0.
+
+Definition _set_Sedeleg_Fetch_Addr_Align
+(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sedeleg in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sedeleg_Fetch_Addr_Align (v : Sedeleg) (x : mword 1)
+: Sedeleg :=
+
+ {[ v with
+ Sedeleg_Sedeleg_chunk_0 :=
+ (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition legalize_sedeleg (s : Sedeleg) (v : mword 64)
+: Sedeleg :=
+
+ Mk_Sedeleg (EXTZ 64 (subrange_vec_dec v 8 0)).
+
+Definition Mk_Sinterrupts (v : mword 64)
+: Sinterrupts :=
+
+ {| Sinterrupts_Sinterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Sinterrupts_bits (v : Sinterrupts)
+: mword 64 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0.
+
+Definition _set_Sinterrupts_bits
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_bits (v : Sinterrupts) (x : mword 64)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Sinterrupts_SEI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9.
+
+Definition _set_Sinterrupts_SEI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_SEI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_UEI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8.
+
+Definition _set_Sinterrupts_UEI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_UEI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_STI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5.
+
+Definition _set_Sinterrupts_STI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_STI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_UTI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4.
+
+Definition _set_Sinterrupts_UTI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_UTI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_SSI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1.
+
+Definition _set_Sinterrupts_SSI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_SSI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Sinterrupts_USI (v : Sinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0.
+
+Definition _set_Sinterrupts_USI
+(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Sinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Sinterrupts_USI (v : Sinterrupts) (x : mword 1)
+: Sinterrupts :=
+
+ {[ v with
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_mip (m : Minterrupts) (d : Minterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in
+ let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in
+ let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in
+ let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in
+ let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in
+ _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)).
+
+Definition lower_mie (m : Minterrupts) (d : Minterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in
+ let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in
+ let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in
+ let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in
+ let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in
+ _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)).
+
+Definition lift_sip (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts)
+: M (Minterrupts) :=
+
+ let m : Minterrupts := o in
+ let m := _update_Minterrupts_SSI m (and_vec (_get_Sinterrupts_SSI s) (_get_Minterrupts_SSI d)) in
+ (haveNExt tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s)
+ else m in
+ if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_USI m (_get_Sinterrupts_USI s)
+ else m
+ else m)
+ : Minterrupts).
+
+Definition legalize_sip (m : Minterrupts) (d : Minterrupts) (v : mword 64)
+: M (Minterrupts) :=
+
+ (lift_sip m d (Mk_Sinterrupts v))
+ : M (Minterrupts).
+
+Definition lift_sie (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts)
+: M (Minterrupts) :=
+
+ let m : Minterrupts := o in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_SEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_SEI m (_get_Sinterrupts_SEI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_STI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_STI m (_get_Sinterrupts_STI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_SSI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_SSI m (_get_Sinterrupts_SSI s)
+ else m in
+ (haveNExt tt) >>= fun w__0 : bool =>
+ returnm ((if sumbool_of_bool (w__0) then
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s)
+ else m in
+ let m :=
+ if ((eq_vec (_get_Minterrupts_UTI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_UTI m (_get_Sinterrupts_UTI s)
+ else m in
+ if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Minterrupts_USI m (_get_Sinterrupts_USI s)
+ else m
+ else m)
+ : Minterrupts).
+
+Definition legalize_sie (m : Minterrupts) (d : Minterrupts) (v : mword 64)
+: M (Minterrupts) :=
+
+ (lift_sie m d (Mk_Sinterrupts v))
+ : M (Minterrupts).
+
+Definition Mk_Satp64 (v : mword 64)
+: Satp64 :=
+
+ {| Satp64_Satp64_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Satp64_bits (v : Satp64)
+: mword 64 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0.
+
+Definition _set_Satp64_bits (r_ref : register_ref regstate register_value Satp64) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_bits (v : Satp64) (x : mword 64)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Satp64_Mode (v : Satp64)
+: mword 4 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60.
+
+Definition _set_Satp64_Mode (r_ref : register_ref regstate register_value Satp64) (v : mword 4)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec v 3 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_Mode (v : Satp64) (x : mword 4)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec x 3 0)) ]}.
+
+Definition _get_Satp64_Asid (v : Satp64)
+: mword 16 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44.
+
+Definition _set_Satp64_Asid (r_ref : register_ref regstate register_value Satp64) (v : mword 16)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec v 15 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_Asid (v : Satp64) (x : mword 16)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec x 15 0)) ]}.
+
+Definition _get_Satp64_PPN (v : Satp64)
+: mword 44 :=
+
+ subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0.
+
+Definition _set_Satp64_PPN (r_ref : register_ref regstate register_value Satp64) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec v 43 0)) ]}
+ : Satp64 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp64_PPN (v : Satp64) (x : mword 44)
+: Satp64 :=
+
+ {[ v with
+ Satp64_Satp64_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec x 43 0)) ]}.
+
+Definition legalize_satp64 (a : Architecture) (o : mword 64) (v : mword 64)
+: mword 64 :=
+
+ let s := Mk_Satp64 v in
+ match (satp64Mode_of_bits a (_get_Satp64_Mode s)) with
+ | None => o
+ | Some (Sv32) => o
+ | Some (_) => _get_Satp64_bits s
+ end.
+
+Definition Mk_Satp32 (v : mword 32)
+: Satp32 :=
+
+ {| Satp32_Satp32_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_Satp32_bits (v : Satp32)
+: mword 32 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 0.
+
+Definition _set_Satp32_bits (r_ref : register_ref regstate register_value Satp32) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_bits (v : Satp32) (x : mword 32)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_Satp32_Mode (v : Satp32)
+: mword 1 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 31.
+
+Definition _set_Satp32_Mode (r_ref : register_ref regstate register_value Satp32) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_Mode (v : Satp32) (x : mword 1)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Satp32_Asid (v : Satp32)
+: mword 9 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 30 22.
+
+Definition _set_Satp32_Asid (r_ref : register_ref regstate register_value Satp32) (v : mword 9)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 30 22 (subrange_vec_dec v 8 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_Asid (v : Satp32) (x : mword 9)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 30 22 (subrange_vec_dec x 8 0)) ]}.
+
+Definition _get_Satp32_PPN (v : Satp32)
+: mword 22 :=
+
+ subrange_vec_dec v.(Satp32_Satp32_chunk_0) 21 0.
+
+Definition _set_Satp32_PPN (r_ref : register_ref regstate register_value Satp32) (v : mword 22)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec r.(Satp32_Satp32_chunk_0) 21 0 (subrange_vec_dec v 21 0)) ]}
+ : Satp32 in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Satp32_PPN (v : Satp32) (x : mword 22)
+: Satp32 :=
+
+ {[ v with
+ Satp32_Satp32_chunk_0 :=
+ (update_subrange_vec_dec v.(Satp32_Satp32_chunk_0) 21 0 (subrange_vec_dec x 21 0)) ]}.
+
+Definition legalize_satp32 (a : Architecture) (o : mword 32) (v : mword 32) : mword 32 := v.
+
+Definition PmpAddrMatchType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: PmpAddrMatchType :=
+
+ let l__20 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__20 0)) then OFF
+ else if sumbool_of_bool ((Z.eqb l__20 1)) then TOR
+ else if sumbool_of_bool ((Z.eqb l__20 2)) then NA4
+ else NAPOT.
+
+Definition num_of_PmpAddrMatchType (arg_ : PmpAddrMatchType)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with | OFF => 0 | TOR => 1 | NA4 => 2 | NAPOT => 3 end).
+
+Definition pmpAddrMatchType_of_bits (bs : mword 2)
+: M (PmpAddrMatchType) :=
+
+ let b__0 := bs in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then returnm (OFF : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (TOR : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (NA4 : PmpAddrMatchType)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then
+ returnm (NAPOT
+ : PmpAddrMatchType)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3" >>= fun _ =>
+ exit tt)
+ : M (PmpAddrMatchType).
+
+Definition pmpAddrMatchType_to_bits (bs : PmpAddrMatchType)
+: mword 2 :=
+
+ match bs with
+ | OFF => (vec_of_bits [B0;B0] : mword 2)
+ | TOR => (vec_of_bits [B0;B1] : mword 2)
+ | NA4 => (vec_of_bits [B1;B0] : mword 2)
+ | NAPOT => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition Mk_Pmpcfg_ent (v : mword 8)
+: Pmpcfg_ent :=
+
+ {| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := (subrange_vec_dec v 7 0) |}.
+
+Definition _get_Pmpcfg_ent_bits (v : Pmpcfg_ent)
+: mword 8 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0.
+
+Definition _set_Pmpcfg_ent_bits
+(r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_bits (v : Pmpcfg_ent) (x : mword 8)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_Pmpcfg_ent_L (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7.
+
+Definition _set_Pmpcfg_ent_L (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_L (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_A (v : Pmpcfg_ent)
+: mword 2 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3.
+
+Definition _set_Pmpcfg_ent_A (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 2)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_A (v : Pmpcfg_ent) (x : mword 2)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_Pmpcfg_ent_X (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2.
+
+Definition _set_Pmpcfg_ent_X (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_X (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_W (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1.
+
+Definition _set_Pmpcfg_ent_W (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_W (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Pmpcfg_ent_R (v : Pmpcfg_ent)
+: mword 1 :=
+
+ subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0.
+
+Definition _set_Pmpcfg_ent_R (r_ref : register_ref regstate register_value Pmpcfg_ent) (v : mword 1)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec r.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Pmpcfg_ent in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Pmpcfg_ent_R (v : Pmpcfg_ent) (x : mword 1)
+: Pmpcfg_ent :=
+
+ {[ v with
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ (update_subrange_vec_dec v.(Pmpcfg_ent_Pmpcfg_ent_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition pmpReadCfgReg (n : Z) `{ArithFact (0 <= n /\ n < 4)}
+: M (mword 64) :=
+
+ let l__18 := n in
+ (if sumbool_of_bool ((Z.eqb l__18 0)) then
+ read_reg pmp7cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ read_reg pmp6cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ read_reg pmp5cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ read_reg pmp4cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ read_reg pmp3cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ read_reg pmp2cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ read_reg pmp1cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ read_reg pmp0cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__0)
+ (concat_vec (_get_Pmpcfg_ent_bits w__1)
+ (concat_vec (_get_Pmpcfg_ent_bits w__2)
+ (concat_vec (_get_Pmpcfg_ent_bits w__3)
+ (concat_vec (_get_Pmpcfg_ent_bits w__4)
+ (concat_vec (_get_Pmpcfg_ent_bits w__5)
+ (concat_vec (_get_Pmpcfg_ent_bits w__6) (_get_Pmpcfg_ent_bits w__7))))))))
+ : mword (8 + (8 + (8 + (8 + (8 + (8 + (8 + 8))))))))
+ else if sumbool_of_bool ((Z.eqb l__18 2)) then
+ read_reg pmp15cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ read_reg pmp14cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ read_reg pmp13cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ read_reg pmp12cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ read_reg pmp11cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ read_reg pmp10cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ read_reg pmp9cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ read_reg pmp8cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ returnm ((concat_vec (_get_Pmpcfg_ent_bits w__8)
+ (concat_vec (_get_Pmpcfg_ent_bits w__9)
+ (concat_vec (_get_Pmpcfg_ent_bits w__10)
+ (concat_vec (_get_Pmpcfg_ent_bits w__11)
+ (concat_vec (_get_Pmpcfg_ent_bits w__12)
+ (concat_vec (_get_Pmpcfg_ent_bits w__13)
+ (concat_vec (_get_Pmpcfg_ent_bits w__14)
+ (_get_Pmpcfg_ent_bits w__15))))))))
+ : mword (8 + (8 + (8 + (8 + (8 + (8 + (8 + 8))))))))
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8" >>= fun _ =>
+ exit tt)
+ : M (mword 64).
+
+Definition pmpWriteCfg (cfg : Pmpcfg_ent) (v : mword 8)
+: Pmpcfg_ent :=
+
+ if ((eq_vec (_get_Pmpcfg_ent_L cfg) ((bool_to_bits true) : mword 1))) then cfg
+ else Mk_Pmpcfg_ent v.
+
+Definition pmpWriteCfgReg (n : Z) (v : mword 64) `{ArithFact (0 <= n /\ n < 4)}
+: M (unit) :=
+
+ let l__16 := n in
+ (if sumbool_of_bool ((Z.eqb l__16 0)) then
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ write_reg pmp0cfg_ref (pmpWriteCfg w__0 (subrange_vec_dec v 7 0)) >>
+ read_reg pmp1cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ write_reg pmp1cfg_ref (pmpWriteCfg w__1 (subrange_vec_dec v 15 8)) >>
+ read_reg pmp2cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ write_reg pmp2cfg_ref (pmpWriteCfg w__2 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp3cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ write_reg pmp3cfg_ref (pmpWriteCfg w__3 (subrange_vec_dec v 31 24)) >>
+ read_reg pmp4cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ write_reg pmp4cfg_ref (pmpWriteCfg w__4 (subrange_vec_dec v 39 32)) >>
+ read_reg pmp5cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ write_reg pmp5cfg_ref (pmpWriteCfg w__5 (subrange_vec_dec v 47 40)) >>
+ read_reg pmp6cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ write_reg pmp6cfg_ref (pmpWriteCfg w__6 (subrange_vec_dec v 55 48)) >>
+ read_reg pmp7cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ write_reg pmp7cfg_ref (pmpWriteCfg w__7 (subrange_vec_dec v 63 56))
+ : M (unit)
+ else if sumbool_of_bool ((Z.eqb l__16 2)) then
+ read_reg pmp8cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ let pmp8cfg8 := pmpWriteCfg w__8 (subrange_vec_dec v 7 0) in
+ read_reg pmp9cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ let pmp9cfg9 := pmpWriteCfg w__9 (subrange_vec_dec v 15 8) in
+ read_reg pmp10cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ write_reg pmp10cfg_ref (pmpWriteCfg w__10 (subrange_vec_dec v 23 16)) >>
+ read_reg pmp11cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ write_reg pmp11cfg_ref (pmpWriteCfg w__11 (subrange_vec_dec v 31 24)) >>
+ read_reg pmp12cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ write_reg pmp12cfg_ref (pmpWriteCfg w__12 (subrange_vec_dec v 39 32)) >>
+ read_reg pmp13cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ write_reg pmp13cfg_ref (pmpWriteCfg w__13 (subrange_vec_dec v 47 40)) >>
+ read_reg pmp14cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ write_reg pmp14cfg_ref (pmpWriteCfg w__14 (subrange_vec_dec v 55 48)) >>
+ read_reg pmp15cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ write_reg pmp15cfg_ref (pmpWriteCfg w__15 (subrange_vec_dec v 63 56))
+ : M (unit)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8" >>= fun _ =>
+ exit tt)
+ : M (unit).
+
+Definition pmpWriteAddr (cfg : Pmpcfg_ent) (reg : mword 64) (v : mword 64)
+: mword 64 :=
+
+ if ((eq_vec (_get_Pmpcfg_ent_L cfg) ((bool_to_bits true) : mword 1))) then reg
+ else EXTZ 64 (subrange_vec_dec v 53 0).
+
+Definition pmpAddrRange (cfg : Pmpcfg_ent) (pmpaddr : mword 64) (prev_pmpaddr : mword 64)
+: M (option ((mword 64 * mword 64))) :=
+
+ (pmpAddrMatchType_of_bits (_get_Pmpcfg_ent_A cfg)) >>= fun w__0 : PmpAddrMatchType =>
+ returnm ((match w__0 with
+ | OFF => None
+ | TOR => Some ((shiftl prev_pmpaddr 2, shiftl pmpaddr 2))
+ | NA4 =>
+ let lo := shiftl pmpaddr 2 in
+ Some
+ ((lo, add_vec_int lo 4))
+ | NAPOT =>
+ let mask := xor_vec pmpaddr (add_vec_int pmpaddr 1) in
+ let lo := and_vec pmpaddr (not_vec mask) in
+ let len := add_vec_int mask 1 in
+ Some
+ ((shiftl lo 2, shiftl (add_vec lo len) 2))
+ end)
+ : option ((mword 64 * mword 64))).
+
+Definition pmpCheckRWX (ent : Pmpcfg_ent) (acc : AccessType)
+: bool :=
+
+ match acc with
+ | Read => eq_vec (_get_Pmpcfg_ent_R ent) ((bool_to_bits true) : mword 1)
+ | Write => eq_vec (_get_Pmpcfg_ent_W ent) ((bool_to_bits true) : mword 1)
+ | ReadWrite =>
+ andb (eq_vec (_get_Pmpcfg_ent_R ent) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_Pmpcfg_ent_W ent) ((bool_to_bits true) : mword 1))
+ | Execute => eq_vec (_get_Pmpcfg_ent_X ent) ((bool_to_bits true) : mword 1)
+ end.
+
+Definition pmpCheckPerms (ent : Pmpcfg_ent) (acc : AccessType) (priv : Privilege)
+: bool :=
+
+ match priv with
+ | Machine =>
+ if ((eq_vec (_get_Pmpcfg_ent_L ent) ((bool_to_bits true) : mword 1))) then
+ pmpCheckRWX ent acc
+ else true
+ | _ => pmpCheckRWX ent acc
+ end.
+
+Definition pmpAddrMatch_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: pmpAddrMatch :=
+
+ let l__14 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__14 0)) then PMP_NoMatch
+ else if sumbool_of_bool ((Z.eqb l__14 1)) then PMP_PartialMatch
+ else PMP_Match.
+
+Definition num_of_pmpAddrMatch (arg_ : pmpAddrMatch)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | PMP_NoMatch => 0 | PMP_PartialMatch => 1 | PMP_Match => 2 end).
+
+Definition pmpMatchAddr (addr : mword 64) (width : mword 64) (rng : option ((mword 64 * mword 64)))
+: pmpAddrMatch :=
+
+ match rng with
+ | None => PMP_NoMatch
+ | Some ((lo, hi)) =>
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if ((orb (zopz0zI_u (add_vec addr width) lo) (zopz0zI_u hi addr))) then PMP_NoMatch
+ else if ((andb (zopz0zIzJ_u lo addr) (zopz0zIzJ_u (add_vec addr width) hi))) then PMP_Match
+ else PMP_PartialMatch
+ end.
+
+Definition pmpMatch_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: pmpMatch :=
+
+ let l__12 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__12 0)) then PMP_Success
+ else if sumbool_of_bool ((Z.eqb l__12 1)) then PMP_Continue
+ else PMP_Fail.
+
+Definition num_of_pmpMatch (arg_ : pmpMatch)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | PMP_Success => 0 | PMP_Continue => 1 | PMP_Fail => 2 end).
+
+Definition pmpMatchEntry
+(addr : mword 64) (width : mword 64) (acc : AccessType) (priv : Privilege) (ent : Pmpcfg_ent)
+(pmpaddr : mword 64) (prev_pmpaddr : mword 64)
+: M (pmpMatch) :=
+
+ (pmpAddrRange ent pmpaddr prev_pmpaddr) >>= fun rng =>
+ returnm ((match (pmpMatchAddr addr width rng) with
+ | PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc priv)) then PMP_Success else PMP_Fail
+ end)
+ : pmpMatch).
+
+Definition pmpCheck (addr : mword 64) (width : Z) (acc : AccessType) (priv : Privilege)
+`{ArithFact (width > 0)}
+: M (option ExceptionType) :=
+
+ let width : xlenbits := to_bits 64 width in
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__0 w__1 (zeros_implicit 64)) >>= fun w__2 : pmpMatch =>
+ (match w__2 with
+ | PMP_Success => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp1cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ ((read_reg pmpaddr1_ref) : M (mword 64)) >>= fun w__4 : mword 64 =>
+ ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__5 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__3 w__4 w__5) >>= fun w__6 : pmpMatch =>
+ (match w__6 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp2cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ ((read_reg pmpaddr2_ref) : M (mword 64)) >>= fun w__8 : mword 64 =>
+ ((read_reg pmpaddr1_ref) : M (mword 64)) >>= fun w__9 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__7 w__8 w__9) >>= fun w__10 : pmpMatch =>
+ (match w__10 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp3cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ ((read_reg pmpaddr3_ref) : M (mword 64)) >>= fun w__12 : mword 64 =>
+ ((read_reg pmpaddr2_ref) : M (mword 64)) >>= fun w__13 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__11 w__12 w__13) >>= fun w__14 : pmpMatch =>
+ (match w__14 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp4cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ ((read_reg pmpaddr4_ref) : M (mword 64)) >>= fun w__16 : mword 64 =>
+ ((read_reg pmpaddr3_ref) : M (mword 64)) >>= fun w__17 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__15 w__16 w__17) >>= fun w__18 : pmpMatch =>
+ (match w__18 with
+ | PMP_Success =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp5cfg_ref >>= fun w__19 : Pmpcfg_ent =>
+ ((read_reg pmpaddr5_ref) : M (mword 64)) >>= fun w__20 : mword 64 =>
+ ((read_reg pmpaddr4_ref) : M (mword 64)) >>= fun w__21 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__19 w__20 w__21) >>= fun w__22 : pmpMatch =>
+ (match w__22 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp6cfg_ref >>= fun w__23 : Pmpcfg_ent =>
+ ((read_reg pmpaddr6_ref) : M (mword 64)) >>= fun w__24 : mword 64 =>
+ ((read_reg pmpaddr5_ref) : M (mword 64)) >>= fun w__25 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__23 w__24 w__25) >>= fun w__26 : pmpMatch =>
+ (match w__26 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp7cfg_ref >>= fun w__27 : Pmpcfg_ent =>
+ ((read_reg pmpaddr7_ref) : M (mword 64)) >>= fun w__28 : mword 64 =>
+ ((read_reg pmpaddr6_ref) : M (mword 64)) >>= fun w__29 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__27 w__28 w__29) >>= fun w__30 : pmpMatch =>
+ (match w__30 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp8cfg_ref >>= fun w__31 : Pmpcfg_ent =>
+ ((read_reg pmpaddr8_ref) : M (mword 64)) >>= fun w__32 : mword 64 =>
+ ((read_reg pmpaddr7_ref) : M (mword 64)) >>= fun w__33 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__31 w__32 w__33) >>= fun w__34 : pmpMatch =>
+ (match w__34 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp9cfg_ref >>= fun w__35 : Pmpcfg_ent =>
+ ((read_reg pmpaddr9_ref) : M (mword 64)) >>= fun w__36 : mword 64 =>
+ ((read_reg pmpaddr8_ref) : M (mword 64)) >>= fun w__37 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__35 w__36 w__37) >>= fun w__38 : pmpMatch =>
+ (match w__38 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp10cfg_ref >>= fun w__39 : Pmpcfg_ent =>
+ ((read_reg pmpaddr10_ref) : M (mword 64)) >>= fun w__40 : mword 64 =>
+ ((read_reg pmpaddr9_ref) : M (mword 64)) >>= fun w__41 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__39 w__40 w__41) >>= fun w__42 : pmpMatch =>
+ (match w__42 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp11cfg_ref >>= fun w__43 : Pmpcfg_ent =>
+ ((read_reg pmpaddr11_ref) : M (mword 64)) >>= fun w__44 : mword 64 =>
+ ((read_reg pmpaddr10_ref) : M (mword 64)) >>= fun w__45 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__43 w__44 w__45) >>= fun w__46 : pmpMatch =>
+ (match w__46 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ | PMP_Continue =>
+ read_reg pmp12cfg_ref >>= fun w__47 : Pmpcfg_ent =>
+ ((read_reg pmpaddr12_ref) : M (mword 64)) >>= fun w__48 : mword 64 =>
+ ((read_reg pmpaddr11_ref) : M (mword 64)) >>= fun w__49 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__47 w__48
+ w__49) >>= fun w__50 : pmpMatch =>
+ (match w__50 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp13cfg_ref >>= fun w__51 : Pmpcfg_ent =>
+ ((read_reg pmpaddr13_ref) : M (mword 64)) >>= fun w__52 : mword 64 =>
+ ((read_reg pmpaddr12_ref) : M (mword 64)) >>= fun w__53 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__51
+ w__52 w__53) >>= fun w__54 : pmpMatch =>
+ (match w__54 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp14cfg_ref >>= fun w__55 : Pmpcfg_ent =>
+ ((read_reg pmpaddr14_ref) : M (mword 64)) >>= fun w__56 : mword 64 =>
+ ((read_reg pmpaddr13_ref) : M (mword 64)) >>= fun w__57 : mword 64 =>
+ (pmpMatchEntry addr width acc priv w__55
+ w__56 w__57) >>= fun w__58 : pmpMatch =>
+ (match w__58 with
+ | PMP_Success =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | PMP_Fail =>
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))}))
+ | PMP_Continue =>
+ read_reg pmp15cfg_ref >>= fun w__59 : Pmpcfg_ent =>
+ ((read_reg pmpaddr15_ref)
+ : M (mword 64)) >>= fun w__60 : mword 64 =>
+ ((read_reg pmpaddr14_ref)
+ : M (mword 64)) >>= fun w__61 : mword 64 =>
+ (pmpMatchEntry addr width acc priv
+ w__59 w__60 w__61) >>= fun w__62 : pmpMatch =>
+ returnm ((match w__62 with
+ | PMP_Success => true
+ | PMP_Fail => false
+ | PMP_Continue =>
+ match priv with
+ | Machine => true
+ | _ => false
+ end
+ end)
+ : bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end)
+ : M (bool)
+ end) >>= fun check' : bool =>
+ returnm ((if sumbool_of_bool (check') then None
+ else
+ match acc with
+ | Read => Some (E_Load_Access_Fault)
+ | Write => Some (E_SAMO_Access_Fault)
+ | ReadWrite => Some (E_SAMO_Access_Fault)
+ | Execute => Some (E_Fetch_Access_Fault)
+ end)
+ : option ExceptionType).
+
+Definition init_pmp '(tt : unit)
+: M (unit) :=
+
+ read_reg pmp0cfg_ref >>= fun w__0 : Pmpcfg_ent =>
+ write_reg pmp0cfg_ref (_update_Pmpcfg_ent_A w__0 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp1cfg_ref >>= fun w__1 : Pmpcfg_ent =>
+ write_reg pmp1cfg_ref (_update_Pmpcfg_ent_A w__1 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp2cfg_ref >>= fun w__2 : Pmpcfg_ent =>
+ write_reg pmp2cfg_ref (_update_Pmpcfg_ent_A w__2 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp3cfg_ref >>= fun w__3 : Pmpcfg_ent =>
+ write_reg pmp3cfg_ref (_update_Pmpcfg_ent_A w__3 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp4cfg_ref >>= fun w__4 : Pmpcfg_ent =>
+ write_reg pmp4cfg_ref (_update_Pmpcfg_ent_A w__4 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp5cfg_ref >>= fun w__5 : Pmpcfg_ent =>
+ write_reg pmp5cfg_ref (_update_Pmpcfg_ent_A w__5 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp6cfg_ref >>= fun w__6 : Pmpcfg_ent =>
+ write_reg pmp6cfg_ref (_update_Pmpcfg_ent_A w__6 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp7cfg_ref >>= fun w__7 : Pmpcfg_ent =>
+ write_reg pmp7cfg_ref (_update_Pmpcfg_ent_A w__7 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp8cfg_ref >>= fun w__8 : Pmpcfg_ent =>
+ write_reg pmp8cfg_ref (_update_Pmpcfg_ent_A w__8 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp9cfg_ref >>= fun w__9 : Pmpcfg_ent =>
+ write_reg pmp9cfg_ref (_update_Pmpcfg_ent_A w__9 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp10cfg_ref >>= fun w__10 : Pmpcfg_ent =>
+ write_reg pmp10cfg_ref (_update_Pmpcfg_ent_A w__10 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp11cfg_ref >>= fun w__11 : Pmpcfg_ent =>
+ write_reg pmp11cfg_ref (_update_Pmpcfg_ent_A w__11 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp12cfg_ref >>= fun w__12 : Pmpcfg_ent =>
+ write_reg pmp12cfg_ref (_update_Pmpcfg_ent_A w__12 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp13cfg_ref >>= fun w__13 : Pmpcfg_ent =>
+ write_reg pmp13cfg_ref (_update_Pmpcfg_ent_A w__13 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp14cfg_ref >>= fun w__14 : Pmpcfg_ent =>
+ write_reg pmp14cfg_ref (_update_Pmpcfg_ent_A w__14 (pmpAddrMatchType_to_bits OFF)) >>
+ read_reg pmp15cfg_ref >>= fun w__15 : Pmpcfg_ent =>
+ write_reg pmp15cfg_ref (_update_Pmpcfg_ent_A w__15 (pmpAddrMatchType_to_bits OFF))
+ : M (unit).
+
+Definition ext_init_regs '(tt : unit) : M (unit) := returnm (tt : unit).
+
+Definition ext_rvfi_init '(tt : unit) : M (unit) := returnm (tt : unit).
+
+Definition ext_fetch_check_pc (start_pc : mword 64) (pc : mword 64)
+: Ext_FetchAddr_Check unit :=
+
+ Ext_FetchAddr_OK
+ (pc).
+
+Definition ext_handle_fetch_check_error (err : unit) : unit := tt.
+
+Definition ext_control_check_addr (pc : mword 64)
+: Ext_ControlAddr_Check unit :=
+
+ Ext_ControlAddr_OK
+ (pc).
+
+Definition ext_control_check_pc (pc : mword 64)
+: Ext_ControlAddr_Check unit :=
+
+ Ext_ControlAddr_OK
+ (pc).
+
+Definition ext_handle_control_check_error (err : unit) : unit := tt.
+
+Definition ext_data_get_addr
+(base : mword 5) (offset : mword 64) (acc : AccessType) (width : word_width)
+: M (Ext_DataAddr_Check unit) :=
+
+ (rX (projT1 (regidx_to_regno base))) >>= fun w__0 : mword 64 =>
+ let addr := add_vec w__0 offset in
+ returnm ((Ext_DataAddr_OK
+ (addr))
+ : Ext_DataAddr_Check unit).
+
+Definition ext_handle_data_check_error (err : unit) : unit := tt.
+
+Definition csr_name (csr : mword 12)
+: string :=
+
+ let b__0 := csr in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "uie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "utvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "uscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "uepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "ucause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "utval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "uip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "fflags"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "frm"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "fcsr"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "cycle"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "time"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "instret"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "cycleh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "timeh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "instreth"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "sstatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "sedeleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "sideleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "sie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "stvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ "scounteren"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "sscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "sepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "scause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "stval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "sip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "satp"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ "mvendorid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ "marchid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ "mimpid"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ "mhartid"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mstatus"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "misa"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "medeleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "mideleg"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "mie"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ "mtvec"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ "mcounteren"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mscratch"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ "mepc"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "mcause"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ "mtval"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ "mip"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ "pmpcfg0"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ "pmpaddr0"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mcycle"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "minstret"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ "mcycleh"
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ "minstreth"
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ "tselect"
+ else "UNKNOWN".
+
+Definition csr_name_map_forwards (arg_ : mword 12)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("ustatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("uie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("utvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("uscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("uepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("ucause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("utval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("uip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("fflags"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("frm"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("fcsr"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("cycle"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("time"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("instret"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("cycleh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("timeh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("instreth"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("sstatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("sedeleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("sideleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("sie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("stvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ("scounteren"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("sscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("sepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("scause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("stval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("sip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("satp"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ("mvendorid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ("marchid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mimpid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mhartid"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mstatus"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("misa"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("medeleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mideleg"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mie"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ("mtvec"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ("mcounteren"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mscratch"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("mepc"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("mcause"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("mtval"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ("mip"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("pmpcfg0"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("pmpcfg1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("pmpcfg2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("pmpcfg3"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ returnm ("pmpaddr0"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ("pmpaddr1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ("pmpaddr2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ("pmpaddr3"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ("pmpaddr4"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ returnm ("pmpaddr5"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ returnm ("pmpaddr6"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ returnm ("pmpaddr7"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ returnm ("pmpaddr8"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ returnm ("pmpaddr9"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ returnm ("pmpaddr10"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ returnm ("pmpaddr11"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ returnm ("pmpaddr12"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ returnm ("pmpaddr13"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ returnm ("pmpaddr14"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ returnm ("pmpaddr15"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mcycle"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("minstret"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("mcycleh"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("minstreth"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ("tselect"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ("tdata1"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ("tdata2"
+ : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ("tdata3"
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition csr_name_map_backwards (arg_ : string)
+: M (mword 12) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "ustatus")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uie")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "utvec")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uscratch")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uepc")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "ucause")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "utval")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "uip")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "fflags")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "frm")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "fcsr")) then
+ returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "cycle")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "time")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "instret")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "cycleh")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "timeh")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "instreth")) then
+ returnm ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sstatus")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sedeleg")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sideleg")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sie")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "stvec")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "scounteren")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sscratch")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sepc")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "scause")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "stval")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "sip")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "satp")) then
+ returnm ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mvendorid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "marchid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mimpid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mhartid")) then
+ returnm ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mstatus")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "misa")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "medeleg")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mideleg")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mie")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mtvec")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcounteren")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mscratch")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mepc")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcause")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mtval")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mip")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpcfg3")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr0")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr1")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr2")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr3")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr4")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr5")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr6")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr7")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr8")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr9")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr10")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr11")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr12")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr13")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr14")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "pmpaddr15")) then
+ returnm ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcycle")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "minstret")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "mcycleh")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "minstreth")) then
+ returnm ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tselect")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata1")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata2")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12)
+ : mword 12)
+ else if ((generic_eq p0_ "tdata3")) then
+ returnm ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12)
+ : mword 12)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 12).
+
+Definition csr_name_map_forwards_matches (arg_ : mword 12)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true
+ else false.
+
+Definition csr_name_map_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "ustatus")) then true
+ else if ((generic_eq p0_ "uie")) then true
+ else if ((generic_eq p0_ "utvec")) then true
+ else if ((generic_eq p0_ "uscratch")) then true
+ else if ((generic_eq p0_ "uepc")) then true
+ else if ((generic_eq p0_ "ucause")) then true
+ else if ((generic_eq p0_ "utval")) then true
+ else if ((generic_eq p0_ "uip")) then true
+ else if ((generic_eq p0_ "fflags")) then true
+ else if ((generic_eq p0_ "frm")) then true
+ else if ((generic_eq p0_ "fcsr")) then true
+ else if ((generic_eq p0_ "cycle")) then true
+ else if ((generic_eq p0_ "time")) then true
+ else if ((generic_eq p0_ "instret")) then true
+ else if ((generic_eq p0_ "cycleh")) then true
+ else if ((generic_eq p0_ "timeh")) then true
+ else if ((generic_eq p0_ "instreth")) then true
+ else if ((generic_eq p0_ "sstatus")) then true
+ else if ((generic_eq p0_ "sedeleg")) then true
+ else if ((generic_eq p0_ "sideleg")) then true
+ else if ((generic_eq p0_ "sie")) then true
+ else if ((generic_eq p0_ "stvec")) then true
+ else if ((generic_eq p0_ "scounteren")) then true
+ else if ((generic_eq p0_ "sscratch")) then true
+ else if ((generic_eq p0_ "sepc")) then true
+ else if ((generic_eq p0_ "scause")) then true
+ else if ((generic_eq p0_ "stval")) then true
+ else if ((generic_eq p0_ "sip")) then true
+ else if ((generic_eq p0_ "satp")) then true
+ else if ((generic_eq p0_ "mvendorid")) then true
+ else if ((generic_eq p0_ "marchid")) then true
+ else if ((generic_eq p0_ "mimpid")) then true
+ else if ((generic_eq p0_ "mhartid")) then true
+ else if ((generic_eq p0_ "mstatus")) then true
+ else if ((generic_eq p0_ "misa")) then true
+ else if ((generic_eq p0_ "medeleg")) then true
+ else if ((generic_eq p0_ "mideleg")) then true
+ else if ((generic_eq p0_ "mie")) then true
+ else if ((generic_eq p0_ "mtvec")) then true
+ else if ((generic_eq p0_ "mcounteren")) then true
+ else if ((generic_eq p0_ "mscratch")) then true
+ else if ((generic_eq p0_ "mepc")) then true
+ else if ((generic_eq p0_ "mcause")) then true
+ else if ((generic_eq p0_ "mtval")) then true
+ else if ((generic_eq p0_ "mip")) then true
+ else if ((generic_eq p0_ "pmpcfg0")) then true
+ else if ((generic_eq p0_ "pmpcfg1")) then true
+ else if ((generic_eq p0_ "pmpcfg2")) then true
+ else if ((generic_eq p0_ "pmpcfg3")) then true
+ else if ((generic_eq p0_ "pmpaddr0")) then true
+ else if ((generic_eq p0_ "pmpaddr1")) then true
+ else if ((generic_eq p0_ "pmpaddr2")) then true
+ else if ((generic_eq p0_ "pmpaddr3")) then true
+ else if ((generic_eq p0_ "pmpaddr4")) then true
+ else if ((generic_eq p0_ "pmpaddr5")) then true
+ else if ((generic_eq p0_ "pmpaddr6")) then true
+ else if ((generic_eq p0_ "pmpaddr7")) then true
+ else if ((generic_eq p0_ "pmpaddr8")) then true
+ else if ((generic_eq p0_ "pmpaddr9")) then true
+ else if ((generic_eq p0_ "pmpaddr10")) then true
+ else if ((generic_eq p0_ "pmpaddr11")) then true
+ else if ((generic_eq p0_ "pmpaddr12")) then true
+ else if ((generic_eq p0_ "pmpaddr13")) then true
+ else if ((generic_eq p0_ "pmpaddr14")) then true
+ else if ((generic_eq p0_ "pmpaddr15")) then true
+ else if ((generic_eq p0_ "mcycle")) then true
+ else if ((generic_eq p0_ "minstret")) then true
+ else if ((generic_eq p0_ "mcycleh")) then true
+ else if ((generic_eq p0_ "minstreth")) then true
+ else if ((generic_eq p0_ "tselect")) then true
+ else if ((generic_eq p0_ "tdata1")) then true
+ else if ((generic_eq p0_ "tdata2")) then true
+ else if ((generic_eq p0_ "tdata3")) then true
+ else false.
+
+Definition _s488_ (_s489_ : string)
+: option string :=
+
+ let _s490_ := _s489_ in
+ if ((string_startswith _s490_ "tdata3")) then
+ match (string_drop _s490_ (projT1 (string_length "tdata3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s484_ (_s485_ : string)
+: option string :=
+
+ let _s486_ := _s485_ in
+ if ((string_startswith _s486_ "tdata2")) then
+ match (string_drop _s486_ (projT1 (string_length "tdata2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s480_ (_s481_ : string)
+: option string :=
+
+ let _s482_ := _s481_ in
+ if ((string_startswith _s482_ "tdata1")) then
+ match (string_drop _s482_ (projT1 (string_length "tdata1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s476_ (_s477_ : string)
+: option string :=
+
+ let _s478_ := _s477_ in
+ if ((string_startswith _s478_ "tselect")) then
+ match (string_drop _s478_ (projT1 (string_length "tselect"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s472_ (_s473_ : string)
+: option string :=
+
+ let _s474_ := _s473_ in
+ if ((string_startswith _s474_ "minstreth")) then
+ match (string_drop _s474_ (projT1 (string_length "minstreth"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s468_ (_s469_ : string)
+: option string :=
+
+ let _s470_ := _s469_ in
+ if ((string_startswith _s470_ "mcycleh")) then
+ match (string_drop _s470_ (projT1 (string_length "mcycleh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s464_ (_s465_ : string)
+: option string :=
+
+ let _s466_ := _s465_ in
+ if ((string_startswith _s466_ "minstret")) then
+ match (string_drop _s466_ (projT1 (string_length "minstret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s460_ (_s461_ : string)
+: option string :=
+
+ let _s462_ := _s461_ in
+ if ((string_startswith _s462_ "mcycle")) then
+ match (string_drop _s462_ (projT1 (string_length "mcycle"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s456_ (_s457_ : string)
+: option string :=
+
+ let _s458_ := _s457_ in
+ if ((string_startswith _s458_ "pmpaddr15")) then
+ match (string_drop _s458_ (projT1 (string_length "pmpaddr15"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s452_ (_s453_ : string)
+: option string :=
+
+ let _s454_ := _s453_ in
+ if ((string_startswith _s454_ "pmpaddr14")) then
+ match (string_drop _s454_ (projT1 (string_length "pmpaddr14"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s448_ (_s449_ : string)
+: option string :=
+
+ let _s450_ := _s449_ in
+ if ((string_startswith _s450_ "pmpaddr13")) then
+ match (string_drop _s450_ (projT1 (string_length "pmpaddr13"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s444_ (_s445_ : string)
+: option string :=
+
+ let _s446_ := _s445_ in
+ if ((string_startswith _s446_ "pmpaddr12")) then
+ match (string_drop _s446_ (projT1 (string_length "pmpaddr12"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s440_ (_s441_ : string)
+: option string :=
+
+ let _s442_ := _s441_ in
+ if ((string_startswith _s442_ "pmpaddr11")) then
+ match (string_drop _s442_ (projT1 (string_length "pmpaddr11"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s436_ (_s437_ : string)
+: option string :=
+
+ let _s438_ := _s437_ in
+ if ((string_startswith _s438_ "pmpaddr10")) then
+ match (string_drop _s438_ (projT1 (string_length "pmpaddr10"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s432_ (_s433_ : string)
+: option string :=
+
+ let _s434_ := _s433_ in
+ if ((string_startswith _s434_ "pmpaddr9")) then
+ match (string_drop _s434_ (projT1 (string_length "pmpaddr9"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s428_ (_s429_ : string)
+: option string :=
+
+ let _s430_ := _s429_ in
+ if ((string_startswith _s430_ "pmpaddr8")) then
+ match (string_drop _s430_ (projT1 (string_length "pmpaddr8"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s424_ (_s425_ : string)
+: option string :=
+
+ let _s426_ := _s425_ in
+ if ((string_startswith _s426_ "pmpaddr7")) then
+ match (string_drop _s426_ (projT1 (string_length "pmpaddr7"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s420_ (_s421_ : string)
+: option string :=
+
+ let _s422_ := _s421_ in
+ if ((string_startswith _s422_ "pmpaddr6")) then
+ match (string_drop _s422_ (projT1 (string_length "pmpaddr6"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s416_ (_s417_ : string)
+: option string :=
+
+ let _s418_ := _s417_ in
+ if ((string_startswith _s418_ "pmpaddr5")) then
+ match (string_drop _s418_ (projT1 (string_length "pmpaddr5"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s412_ (_s413_ : string)
+: option string :=
+
+ let _s414_ := _s413_ in
+ if ((string_startswith _s414_ "pmpaddr4")) then
+ match (string_drop _s414_ (projT1 (string_length "pmpaddr4"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s408_ (_s409_ : string)
+: option string :=
+
+ let _s410_ := _s409_ in
+ if ((string_startswith _s410_ "pmpaddr3")) then
+ match (string_drop _s410_ (projT1 (string_length "pmpaddr3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s404_ (_s405_ : string)
+: option string :=
+
+ let _s406_ := _s405_ in
+ if ((string_startswith _s406_ "pmpaddr2")) then
+ match (string_drop _s406_ (projT1 (string_length "pmpaddr2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s400_ (_s401_ : string)
+: option string :=
+
+ let _s402_ := _s401_ in
+ if ((string_startswith _s402_ "pmpaddr1")) then
+ match (string_drop _s402_ (projT1 (string_length "pmpaddr1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s396_ (_s397_ : string)
+: option string :=
+
+ let _s398_ := _s397_ in
+ if ((string_startswith _s398_ "pmpaddr0")) then
+ match (string_drop _s398_ (projT1 (string_length "pmpaddr0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s392_ (_s393_ : string)
+: option string :=
+
+ let _s394_ := _s393_ in
+ if ((string_startswith _s394_ "pmpcfg3")) then
+ match (string_drop _s394_ (projT1 (string_length "pmpcfg3"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s388_ (_s389_ : string)
+: option string :=
+
+ let _s390_ := _s389_ in
+ if ((string_startswith _s390_ "pmpcfg2")) then
+ match (string_drop _s390_ (projT1 (string_length "pmpcfg2"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s384_ (_s385_ : string)
+: option string :=
+
+ let _s386_ := _s385_ in
+ if ((string_startswith _s386_ "pmpcfg1")) then
+ match (string_drop _s386_ (projT1 (string_length "pmpcfg1"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s380_ (_s381_ : string)
+: option string :=
+
+ let _s382_ := _s381_ in
+ if ((string_startswith _s382_ "pmpcfg0")) then
+ match (string_drop _s382_ (projT1 (string_length "pmpcfg0"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s376_ (_s377_ : string)
+: option string :=
+
+ let _s378_ := _s377_ in
+ if ((string_startswith _s378_ "mip")) then
+ match (string_drop _s378_ (projT1 (string_length "mip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s372_ (_s373_ : string)
+: option string :=
+
+ let _s374_ := _s373_ in
+ if ((string_startswith _s374_ "mtval")) then
+ match (string_drop _s374_ (projT1 (string_length "mtval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s368_ (_s369_ : string)
+: option string :=
+
+ let _s370_ := _s369_ in
+ if ((string_startswith _s370_ "mcause")) then
+ match (string_drop _s370_ (projT1 (string_length "mcause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s364_ (_s365_ : string)
+: option string :=
+
+ let _s366_ := _s365_ in
+ if ((string_startswith _s366_ "mepc")) then
+ match (string_drop _s366_ (projT1 (string_length "mepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s360_ (_s361_ : string)
+: option string :=
+
+ let _s362_ := _s361_ in
+ if ((string_startswith _s362_ "mscratch")) then
+ match (string_drop _s362_ (projT1 (string_length "mscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s356_ (_s357_ : string)
+: option string :=
+
+ let _s358_ := _s357_ in
+ if ((string_startswith _s358_ "mcounteren")) then
+ match (string_drop _s358_ (projT1 (string_length "mcounteren"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s352_ (_s353_ : string)
+: option string :=
+
+ let _s354_ := _s353_ in
+ if ((string_startswith _s354_ "mtvec")) then
+ match (string_drop _s354_ (projT1 (string_length "mtvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s348_ (_s349_ : string)
+: option string :=
+
+ let _s350_ := _s349_ in
+ if ((string_startswith _s350_ "mie")) then
+ match (string_drop _s350_ (projT1 (string_length "mie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s344_ (_s345_ : string)
+: option string :=
+
+ let _s346_ := _s345_ in
+ if ((string_startswith _s346_ "mideleg")) then
+ match (string_drop _s346_ (projT1 (string_length "mideleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s340_ (_s341_ : string)
+: option string :=
+
+ let _s342_ := _s341_ in
+ if ((string_startswith _s342_ "medeleg")) then
+ match (string_drop _s342_ (projT1 (string_length "medeleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s336_ (_s337_ : string)
+: option string :=
+
+ let _s338_ := _s337_ in
+ if ((string_startswith _s338_ "misa")) then
+ match (string_drop _s338_ (projT1 (string_length "misa"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s332_ (_s333_ : string)
+: option string :=
+
+ let _s334_ := _s333_ in
+ if ((string_startswith _s334_ "mstatus")) then
+ match (string_drop _s334_ (projT1 (string_length "mstatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s328_ (_s329_ : string)
+: option string :=
+
+ let _s330_ := _s329_ in
+ if ((string_startswith _s330_ "mhartid")) then
+ match (string_drop _s330_ (projT1 (string_length "mhartid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s324_ (_s325_ : string)
+: option string :=
+
+ let _s326_ := _s325_ in
+ if ((string_startswith _s326_ "mimpid")) then
+ match (string_drop _s326_ (projT1 (string_length "mimpid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s320_ (_s321_ : string)
+: option string :=
+
+ let _s322_ := _s321_ in
+ if ((string_startswith _s322_ "marchid")) then
+ match (string_drop _s322_ (projT1 (string_length "marchid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s316_ (_s317_ : string)
+: option string :=
+
+ let _s318_ := _s317_ in
+ if ((string_startswith _s318_ "mvendorid")) then
+ match (string_drop _s318_ (projT1 (string_length "mvendorid"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s312_ (_s313_ : string)
+: option string :=
+
+ let _s314_ := _s313_ in
+ if ((string_startswith _s314_ "satp")) then
+ match (string_drop _s314_ (projT1 (string_length "satp"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s308_ (_s309_ : string)
+: option string :=
+
+ let _s310_ := _s309_ in
+ if ((string_startswith _s310_ "sip")) then
+ match (string_drop _s310_ (projT1 (string_length "sip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s304_ (_s305_ : string)
+: option string :=
+
+ let _s306_ := _s305_ in
+ if ((string_startswith _s306_ "stval")) then
+ match (string_drop _s306_ (projT1 (string_length "stval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s300_ (_s301_ : string)
+: option string :=
+
+ let _s302_ := _s301_ in
+ if ((string_startswith _s302_ "scause")) then
+ match (string_drop _s302_ (projT1 (string_length "scause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s296_ (_s297_ : string)
+: option string :=
+
+ let _s298_ := _s297_ in
+ if ((string_startswith _s298_ "sepc")) then
+ match (string_drop _s298_ (projT1 (string_length "sepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s292_ (_s293_ : string)
+: option string :=
+
+ let _s294_ := _s293_ in
+ if ((string_startswith _s294_ "sscratch")) then
+ match (string_drop _s294_ (projT1 (string_length "sscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s288_ (_s289_ : string)
+: option string :=
+
+ let _s290_ := _s289_ in
+ if ((string_startswith _s290_ "scounteren")) then
+ match (string_drop _s290_ (projT1 (string_length "scounteren"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s284_ (_s285_ : string)
+: option string :=
+
+ let _s286_ := _s285_ in
+ if ((string_startswith _s286_ "stvec")) then
+ match (string_drop _s286_ (projT1 (string_length "stvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s280_ (_s281_ : string)
+: option string :=
+
+ let _s282_ := _s281_ in
+ if ((string_startswith _s282_ "sie")) then
+ match (string_drop _s282_ (projT1 (string_length "sie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s276_ (_s277_ : string)
+: option string :=
+
+ let _s278_ := _s277_ in
+ if ((string_startswith _s278_ "sideleg")) then
+ match (string_drop _s278_ (projT1 (string_length "sideleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s272_ (_s273_ : string)
+: option string :=
+
+ let _s274_ := _s273_ in
+ if ((string_startswith _s274_ "sedeleg")) then
+ match (string_drop _s274_ (projT1 (string_length "sedeleg"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s268_ (_s269_ : string)
+: option string :=
+
+ let _s270_ := _s269_ in
+ if ((string_startswith _s270_ "sstatus")) then
+ match (string_drop _s270_ (projT1 (string_length "sstatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s264_ (_s265_ : string)
+: option string :=
+
+ let _s266_ := _s265_ in
+ if ((string_startswith _s266_ "instreth")) then
+ match (string_drop _s266_ (projT1 (string_length "instreth"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s260_ (_s261_ : string)
+: option string :=
+
+ let _s262_ := _s261_ in
+ if ((string_startswith _s262_ "timeh")) then
+ match (string_drop _s262_ (projT1 (string_length "timeh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s256_ (_s257_ : string)
+: option string :=
+
+ let _s258_ := _s257_ in
+ if ((string_startswith _s258_ "cycleh")) then
+ match (string_drop _s258_ (projT1 (string_length "cycleh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s252_ (_s253_ : string)
+: option string :=
+
+ let _s254_ := _s253_ in
+ if ((string_startswith _s254_ "instret")) then
+ match (string_drop _s254_ (projT1 (string_length "instret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s248_ (_s249_ : string)
+: option string :=
+
+ let _s250_ := _s249_ in
+ if ((string_startswith _s250_ "time")) then
+ match (string_drop _s250_ (projT1 (string_length "time"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s244_ (_s245_ : string)
+: option string :=
+
+ let _s246_ := _s245_ in
+ if ((string_startswith _s246_ "cycle")) then
+ match (string_drop _s246_ (projT1 (string_length "cycle"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s240_ (_s241_ : string)
+: option string :=
+
+ let _s242_ := _s241_ in
+ if ((string_startswith _s242_ "fcsr")) then
+ match (string_drop _s242_ (projT1 (string_length "fcsr"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s236_ (_s237_ : string)
+: option string :=
+
+ let _s238_ := _s237_ in
+ if ((string_startswith _s238_ "frm")) then
+ match (string_drop _s238_ (projT1 (string_length "frm"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s232_ (_s233_ : string)
+: option string :=
+
+ let _s234_ := _s233_ in
+ if ((string_startswith _s234_ "fflags")) then
+ match (string_drop _s234_ (projT1 (string_length "fflags"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s228_ (_s229_ : string)
+: option string :=
+
+ let _s230_ := _s229_ in
+ if ((string_startswith _s230_ "uip")) then
+ match (string_drop _s230_ (projT1 (string_length "uip"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s224_ (_s225_ : string)
+: option string :=
+
+ let _s226_ := _s225_ in
+ if ((string_startswith _s226_ "utval")) then
+ match (string_drop _s226_ (projT1 (string_length "utval"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s220_ (_s221_ : string)
+: option string :=
+
+ let _s222_ := _s221_ in
+ if ((string_startswith _s222_ "ucause")) then
+ match (string_drop _s222_ (projT1 (string_length "ucause"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s216_ (_s217_ : string)
+: option string :=
+
+ let _s218_ := _s217_ in
+ if ((string_startswith _s218_ "uepc")) then
+ match (string_drop _s218_ (projT1 (string_length "uepc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s212_ (_s213_ : string)
+: option string :=
+
+ let _s214_ := _s213_ in
+ if ((string_startswith _s214_ "uscratch")) then
+ match (string_drop _s214_ (projT1 (string_length "uscratch"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s208_ (_s209_ : string)
+: option string :=
+
+ let _s210_ := _s209_ in
+ if ((string_startswith _s210_ "utvec")) then
+ match (string_drop _s210_ (projT1 (string_length "utvec"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s204_ (_s205_ : string)
+: option string :=
+
+ let _s206_ := _s205_ in
+ if ((string_startswith _s206_ "uie")) then
+ match (string_drop _s206_ (projT1 (string_length "uie"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s200_ (_s201_ : string)
+: option string :=
+
+ let _s202_ := _s201_ in
+ if ((string_startswith _s202_ "ustatus")) then
+ match (string_drop _s202_ (projT1 (string_length "ustatus"))) with | s_ => Some (s_) end
+ else None.
+
+Definition csr_name_map_matches_prefix (arg_ : string)
+: M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s203_ := arg_ in
+ (if ((match (_s200_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s200_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s204_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s204_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s208_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s208_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s212_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s212_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s216_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s216_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s220_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s220_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s224_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s224_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s228_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s228_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s232_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s232_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s236_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s236_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s240_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s240_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s244_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s244_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s248_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s248_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s252_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s252_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s256_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s256_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s260_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s260_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s264_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s264_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s268_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s268_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s272_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s272_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s276_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s276_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s280_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s280_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s284_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s284_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s288_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s288_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s292_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s292_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s296_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s296_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s300_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s300_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s304_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s304_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s308_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s308_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s312_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s312_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s316_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s316_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s320_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s320_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s324_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s324_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s328_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s328_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s332_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s332_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s336_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s336_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s340_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s340_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s344_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s344_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s348_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s348_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s352_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s352_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s356_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s356_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s360_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s360_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s364_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s364_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s368_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s368_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s372_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s372_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s376_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s376_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s380_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s380_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s384_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s384_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s388_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s388_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s392_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s392_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s396_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s396_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s400_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s400_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s404_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s404_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s408_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s408_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s412_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s412_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s416_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s416_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s420_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s420_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s424_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s424_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s428_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s428_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s432_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s432_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s436_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s436_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s440_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s440_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s444_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s444_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s448_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s448_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s452_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s452_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s456_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s456_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s460_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s460_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s464_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s464_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s468_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s468_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s472_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s472_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s476_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s476_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s480_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s480_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s484_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s484_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s488_ _s203_) with | Some (s_) => true | _ => false end)) then
+ (match (_s488_ _s203_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition Mk_Ustatus (v : mword 64)
+: Ustatus :=
+
+ {| Ustatus_Ustatus_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Ustatus_bits (v : Ustatus)
+: mword 64 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 63 0.
+
+Definition _set_Ustatus_bits (r_ref : register_ref regstate register_value Ustatus) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_bits (v : Ustatus) (x : mword 64)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Ustatus_UPIE (v : Ustatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 4 4.
+
+Definition _set_Ustatus_UPIE (r_ref : register_ref regstate register_value Ustatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_UPIE (v : Ustatus) (x : mword 1)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Ustatus_UIE (v : Ustatus)
+: mword 1 :=
+
+ subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 0 0.
+
+Definition _set_Ustatus_UIE (r_ref : register_ref regstate register_value Ustatus) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec r.(Ustatus_Ustatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Ustatus in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Ustatus_UIE (v : Ustatus) (x : mword 1)
+: Ustatus :=
+
+ {[ v with
+ Ustatus_Ustatus_chunk_0 :=
+ (update_subrange_vec_dec v.(Ustatus_Ustatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_sstatus (s : Sstatus)
+: Ustatus :=
+
+ let u := Mk_Ustatus (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Ustatus_UPIE u (_get_Sstatus_UPIE s) in
+ _update_Ustatus_UIE u (_get_Sstatus_UIE s).
+
+Definition lift_ustatus (s : Sstatus) (u : Ustatus)
+: Sstatus :=
+
+ let s := _update_Sstatus_UPIE s (_get_Ustatus_UPIE u) in
+ _update_Sstatus_UIE s (_get_Ustatus_UIE u).
+
+Definition legalize_ustatus (m : Mstatus) (v : mword 64)
+: M (Mstatus) :=
+
+ let u := Mk_Ustatus v in
+ let s := lower_mstatus m in
+ let s := lift_ustatus s u in
+ (lift_sstatus m s)
+ : M (Mstatus).
+
+Definition Mk_Uinterrupts (v : mword 64)
+: Uinterrupts :=
+
+ {| Uinterrupts_Uinterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_Uinterrupts_bits (v : Uinterrupts)
+: mword 64 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 63 0.
+
+Definition _set_Uinterrupts_bits
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 64)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_bits (v : Uinterrupts) (x : mword 64)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_Uinterrupts_UEI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 8 8.
+
+Definition _set_Uinterrupts_UEI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_UEI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Uinterrupts_UTI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 4 4.
+
+Definition _set_Uinterrupts_UTI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_UTI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_Uinterrupts_USI (v : Uinterrupts)
+: mword 1 :=
+
+ subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 0 0.
+
+Definition _set_Uinterrupts_USI
+(r_ref : register_ref regstate register_value Uinterrupts) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec r.(Uinterrupts_Uinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : Uinterrupts in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_Uinterrupts_USI (v : Uinterrupts) (x : mword 1)
+: Uinterrupts :=
+
+ {[ v with
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ (update_subrange_vec_dec v.(Uinterrupts_Uinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition lower_sip (s : Sinterrupts) (d : Sinterrupts)
+: Uinterrupts :=
+
+ let u : Uinterrupts := Mk_Uinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Uinterrupts_UEI u (and_vec (_get_Sinterrupts_UEI s) (_get_Sinterrupts_UEI d)) in
+ let u := _update_Uinterrupts_UTI u (and_vec (_get_Sinterrupts_UTI s) (_get_Sinterrupts_UTI d)) in
+ _update_Uinterrupts_USI u (and_vec (_get_Sinterrupts_USI s) (_get_Sinterrupts_USI d)).
+
+Definition lower_sie (s : Sinterrupts) (d : Sinterrupts)
+: Uinterrupts :=
+
+ let u : Uinterrupts := Mk_Uinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in
+ let u := _update_Uinterrupts_UEI u (and_vec (_get_Sinterrupts_UEI s) (_get_Sinterrupts_UEI d)) in
+ let u := _update_Uinterrupts_UTI u (and_vec (_get_Sinterrupts_UTI s) (_get_Sinterrupts_UTI d)) in
+ _update_Uinterrupts_USI u (and_vec (_get_Sinterrupts_USI s) (_get_Sinterrupts_USI d)).
+
+Definition lift_uip (o : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := o in
+ if ((eq_vec (_get_Sinterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_USI s (_get_Uinterrupts_USI u)
+ else s.
+
+Definition legalize_uip (s : Sinterrupts) (d : Sinterrupts) (v : mword 64)
+: Sinterrupts :=
+
+ lift_uip s d (Mk_Uinterrupts v).
+
+Definition lift_uie (o : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)
+: Sinterrupts :=
+
+ let s : Sinterrupts := o in
+ let s :=
+ if ((eq_vec (_get_Sinterrupts_UEI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_UEI s (_get_Uinterrupts_UEI u)
+ else s in
+ let s :=
+ if ((eq_vec (_get_Sinterrupts_UTI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_UTI s (_get_Uinterrupts_UTI u)
+ else s in
+ if ((eq_vec (_get_Sinterrupts_USI d) ((bool_to_bits true) : mword 1))) then
+ _update_Sinterrupts_USI s (_get_Uinterrupts_USI u)
+ else s.
+
+Definition legalize_uie (s : Sinterrupts) (d : Sinterrupts) (v : mword 64)
+: Sinterrupts :=
+
+ lift_uie s d (Mk_Uinterrupts v).
+
+Definition handle_trap_extension (p : Privilege) (pc : mword 64) (u : option unit) : unit := tt.
+
+Definition prepare_trap_vector (p : Privilege) (cause : Mcause)
+: M (mword 64) :=
+
+ (match p with
+ | Machine => read_reg mtvec_ref : M (Mtvec)
+ | Supervisor => read_reg stvec_ref : M (Mtvec)
+ | User => read_reg utvec_ref : M (Mtvec)
+ end) >>= fun tvec : Mtvec =>
+ (match (tvec_addr tvec cause) with
+ | Some (epc) => returnm (epc : mword 64)
+ | None => (internal_error "Invalid tvec mode") : M (mword 64)
+ end)
+ : M (mword 64).
+
+Definition get_xret_target (p : Privilege)
+: M (mword 64) :=
+
+ (match p with
+ | Machine => ((read_reg mepc_ref) : M (mword 64)) : M (mword 64)
+ | Supervisor => ((read_reg sepc_ref) : M (mword 64)) : M (mword 64)
+ | User => ((read_reg uepc_ref) : M (mword 64)) : M (mword 64)
+ end)
+ : M (mword 64).
+
+Definition set_xret_target (p : Privilege) (value : mword 64)
+: M (mword 64) :=
+
+ (legalize_xepc value) >>= fun target =>
+ (match p with
+ | Machine => write_reg mepc_ref target : M (unit)
+ | Supervisor => write_reg sepc_ref target : M (unit)
+ | User => write_reg uepc_ref target : M (unit)
+ end) >>
+ returnm (target
+ : mword 64).
+
+Definition prepare_xret_target (p : Privilege)
+: M (mword 64) :=
+
+ (get_xret_target p)
+ : M (mword 64).
+
+Definition get_mtvec '(tt : unit)
+: M (mword 64) :=
+
+ read_reg mtvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 64).
+
+Definition get_stvec '(tt : unit)
+: M (mword 64) :=
+
+ read_reg stvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 64).
+
+Definition get_utvec '(tt : unit)
+: M (mword 64) :=
+
+ read_reg utvec_ref >>= fun w__0 : Mtvec => returnm ((_get_Mtvec_bits w__0) : mword 64).
+
+Definition set_mtvec (value : mword 64)
+: M (mword 64) :=
+
+ read_reg mtvec_ref >>= fun w__0 : Mtvec =>
+ write_reg mtvec_ref (legalize_tvec w__0 value) >>
+ read_reg mtvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 64).
+
+Definition set_stvec (value : mword 64)
+: M (mword 64) :=
+
+ read_reg stvec_ref >>= fun w__0 : Mtvec =>
+ write_reg stvec_ref (legalize_tvec w__0 value) >>
+ read_reg stvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 64).
+
+Definition set_utvec (value : mword 64)
+: M (mword 64) :=
+
+ read_reg utvec_ref >>= fun w__0 : Mtvec =>
+ write_reg utvec_ref (legalize_tvec w__0 value) >>
+ read_reg utvec_ref >>= fun w__1 : Mtvec => returnm ((_get_Mtvec_bits w__1) : mword 64).
+
+Definition is_NExt_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (haveUsrMode tt)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition read_NExt_CSR (csr : mword 12)
+: M (option (mword 64)) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ returnm ((Some
+ (_get_Ustatus_bits (lower_sstatus (lower_mstatus w__0))))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__1 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__2 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__3 : Sinterrupts =>
+ returnm ((Some
+ (_get_Uinterrupts_bits (lower_sie (lower_mie w__1 w__2) w__3)))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_utvec tt) >>= fun w__4 : mword 64 => returnm ((Some (w__4)) : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg uscratch_ref) : M (mword 64)) >>= fun w__5 : mword 64 =>
+ returnm ((Some
+ (w__5))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target User) >>= fun w__6 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__7 : mword 64 =>
+ returnm ((Some
+ (and_vec w__6 w__7))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg ucause_ref >>= fun w__8 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__8))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg utval_ref) : M (mword 64)) >>= fun w__9 : mword 64 =>
+ returnm ((Some
+ (w__9))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__10 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__11 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__12 : Sinterrupts =>
+ returnm ((Some
+ (_get_Uinterrupts_bits (lower_sip (lower_mip w__10 w__11) w__12)))
+ : option (mword 64))
+ else returnm (None : option (mword 64)))
+ : M (option xlenbits).
+
+Definition write_NExt_CSR (csr : mword 12) (value : mword 64)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (legalize_ustatus w__0 value) >>= fun w__1 : Mstatus =>
+ write_reg mstatus_ref w__1 >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__2))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__3 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__4 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__5 : Sinterrupts =>
+ let sie := legalize_uie (lower_mie w__3 w__4) w__5 value in
+ read_reg mie_ref >>= fun w__6 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__7 : Minterrupts =>
+ (lift_sie w__6 w__7 sie) >>= fun w__8 : Minterrupts =>
+ write_reg mie_ref w__8 >>
+ read_reg mie_ref >>= fun w__9 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__9))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_utvec value) >>= fun w__10 : mword 64 => returnm ((Some (w__10)) : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg uscratch_ref value >>
+ ((read_reg uscratch_ref) : M (mword 64)) >>= fun w__11 : mword 64 =>
+ returnm ((Some
+ (w__11))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target User value) >>= fun w__12 : mword 64 =>
+ returnm ((Some
+ (w__12))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits ucause_ref value) >>
+ read_reg ucause_ref >>= fun w__13 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__13))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg utval_ref value >>
+ ((read_reg utval_ref) : M (mword 64)) >>= fun w__14 : mword 64 =>
+ returnm ((Some
+ (w__14))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__15 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__16 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__17 : Sinterrupts =>
+ let sip := legalize_uip (lower_mip w__15 w__16) w__17 value in
+ read_reg mip_ref >>= fun w__18 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__19 : Minterrupts =>
+ (lift_sip w__18 w__19 sip) >>= fun w__20 : Minterrupts =>
+ write_reg mip_ref w__20 >>
+ read_reg mip_ref >>= fun w__21 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__21))
+ : option (mword 64))
+ else returnm (None : option (mword 64))) >>= fun res : option xlenbits =>
+ returnm ((match res with
+ | Some (v) =>
+ let '_ :=
+ (if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr)
+ (String.append " <- "
+ (String.append (string_of_bits v)
+ (String.append " (input: "
+ (String.append (string_of_bits value) ")"))))))
+ else tt)
+ : unit in
+ true
+ | None => false
+ end)
+ : bool).
+
+Definition ext_is_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (is_NExt_CSR_defined csr p)
+ : M (bool).
+
+Definition ext_read_CSR (csr : mword 12)
+: M (option (mword 64)) :=
+
+ (read_NExt_CSR csr)
+ : M (option (mword 64)).
+
+Definition ext_write_CSR (csr : mword 12) (value : mword 64)
+: M (bool) :=
+
+ (write_NExt_CSR csr value)
+ : M (bool).
+
+Definition csrAccess (csr : mword 12) : mword 2 := subrange_vec_dec csr 11 10.
+
+Definition csrPriv (csr : mword 12) : mword 2 := subrange_vec_dec csr 9 8.
+
+Definition is_CSR_defined (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ let b__0 := csr in
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM ((haveSupMode tt) : M (bool))
+ (returnm ((orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2))
+ (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)))
+ : bool)))
+ : M (bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ returnm (projT1
+ (build_ex
+ (andb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits User) : mword 2)) (Z.eqb 64 32))
+ : {_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (simp_0 = true /\ 64 = 32))}))
+ else (ext_is_CSR_defined csr p) : M (bool))
+ : M (bool).
+
+Definition check_CSR_access (csrrw : mword 2) (csrpr : mword 2) (p : Privilege) (isWrite : bool)
+: bool :=
+
+ andb (negb (andb (Bool.eqb isWrite true) (eq_vec csrrw (vec_of_bits [B1;B1] : mword 2))))
+ (zopz0zKzJ_u (privLevel_to_bits p) csrpr).
+
+Definition check_TVM_SATP (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (and_boolM
+ (returnm ((eq_vec csr (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_TVM w__0) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun w__2 : bool =>
+ returnm ((negb w__2)
+ : bool).
+
+Definition check_Counteren (csr : mword 12) (p : Privilege)
+: M (bool) :=
+
+ (match (csr, p) with
+ | (b__0, Supervisor) =>
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__0 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__0) ((bool_to_bits true) : mword 1))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__1 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__1) ((bool_to_bits true) : mword 1))
+ : bool)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__2 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__2) ((bool_to_bits true) : mword 1))
+ : bool)
+ else
+ returnm ((match (b__0, Supervisor) with
+ | (_, _) =>
+ if ((andb
+ (zopz0zIzJ_u
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12))))
+ then
+ false
+ else true
+ end)
+ : bool))
+ : M (bool)
+ | (b__3, User) =>
+ (if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__6 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__6) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__7 : bool => returnm ((negb w__7) : bool))
+ (read_reg scounteren_ref >>= fun w__8 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_CY w__8) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__11 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__11) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__12 : bool => returnm ((negb w__12) : bool))
+ (read_reg scounteren_ref >>= fun w__13 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_TM w__13) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (and_boolM
+ (read_reg mcounteren_ref >>= fun w__16 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__16) ((bool_to_bits true) : mword 1))
+ : bool))
+ ((or_boolM ((haveSupMode tt) >>= fun w__17 : bool => returnm ((negb w__17) : bool))
+ (read_reg scounteren_ref >>= fun w__18 : Counteren =>
+ returnm ((eq_vec (_get_Counteren_IR w__18) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ else
+ returnm ((match (b__3, User) with
+ | (_, _) =>
+ if ((andb
+ (zopz0zIzJ_u
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12))))
+ then
+ false
+ else true
+ end)
+ : bool))
+ : M (bool)
+ | (_, _) =>
+ returnm ((if ((andb
+ (zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12)
+ csr)
+ (zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) then
+ false
+ else true)
+ : bool)
+ end)
+ : M (bool).
+
+Definition check_CSR (csr : mword 12) (p : Privilege) (isWrite : bool)
+: M (bool) :=
+
+ (and_boolM ((is_CSR_defined csr p) : M (bool))
+ ((and_boolM (returnm ((check_CSR_access (csrAccess csr) (csrPriv csr) p isWrite) : bool))
+ ((and_boolM ((check_TVM_SATP csr p) : M (bool)) ((check_Counteren csr p) : M (bool)))
+ : M (bool)))
+ : M (bool)))
+ : M (bool).
+
+Axiom speculate_conditional : forall (_ : unit) , M (bool).
+
+Axiom load_reservation : forall (_ : mword 64) , unit.
+
+Axiom match_reservation : forall (_ : mword 64) , bool.
+
+Axiom cancel_reservation : forall (_ : unit) , unit.
+
+Definition exception_delegatee (e : ExceptionType) (p : Privilege)
+: M (Privilege) :=
+
+ let idx := projT1 (num_of_ExceptionType e) in
+ read_reg medeleg_ref >>= fun w__0 : Medeleg =>
+ let super := access_vec_dec (_get_Medeleg_bits w__0) idx in
+ (haveSupMode tt) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (and_boolM ((bit_to_bool super) : M (bool))
+ ((and_boolM ((haveNExt tt) : M (bool))
+ (read_reg sedeleg_ref >>= fun w__4 : Sedeleg =>
+ (bit_to_bool (access_vec_dec (_get_Sedeleg_bits w__4) idx))
+ : M (bool)))
+ : M (bool)))
+ : M (bool)
+ else (and_boolM ((bit_to_bool super) : M (bool)) ((haveNExt tt) : M (bool))) : M (bool)) >>= fun user =>
+ (and_boolMP (build_trivial_ex ((haveUsrMode tt) : M (bool)))
+ ((returnm (build_ex
+ user)) : M ({_bool : bool & ArithFact (iff (_bool = true) (user = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (user = true /\ simp_0 = true))})) >>= fun '(existT _ w__12 _) =>
+ (if sumbool_of_bool (w__12) then returnm (User : Privilege)
+ else
+ (and_boolM ((haveSupMode tt) : M (bool)) ((bit_to_bool super) : M (bool))) >>= fun w__15 : bool =>
+ returnm ((if sumbool_of_bool (w__15) then Supervisor
+ else Machine)
+ : Privilege)) >>= fun deleg =>
+ returnm ((if ((zopz0zI_u (privLevel_to_bits deleg) (privLevel_to_bits p))) then p
+ else deleg)
+ : Privilege).
+
+Definition findPendingInterrupt (ip : mword 64)
+: option InterruptType :=
+
+ let ip := Mk_Minterrupts ip in
+ if ((eq_vec (_get_Minterrupts_MEI ip) ((bool_to_bits true) : mword 1))) then Some (I_M_External)
+ else if ((eq_vec (_get_Minterrupts_MSI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_M_Software)
+ else if ((eq_vec (_get_Minterrupts_MTI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_M_Timer)
+ else if ((eq_vec (_get_Minterrupts_SEI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_External)
+ else if ((eq_vec (_get_Minterrupts_SSI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_Software)
+ else if ((eq_vec (_get_Minterrupts_STI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_S_Timer)
+ else if ((eq_vec (_get_Minterrupts_UEI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_External)
+ else if ((eq_vec (_get_Minterrupts_USI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_Software)
+ else if ((eq_vec (_get_Minterrupts_UTI ip) ((bool_to_bits true) : mword 1))) then
+ Some
+ (I_U_Timer)
+ else None.
+
+Definition processPending
+(xip : Minterrupts) (xie : Minterrupts) (xideleg : mword 64) (priv_enabled : bool)
+: interrupt_set :=
+
+ let effective_pend :=
+ and_vec (_get_Minterrupts_bits xip) (and_vec (_get_Minterrupts_bits xie) (not_vec xideleg)) in
+ let effective_delg := and_vec (_get_Minterrupts_bits xip) xideleg in
+ if sumbool_of_bool ((andb priv_enabled
+ (neq_vec effective_pend (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then
+ Ints_Pending
+ (effective_pend)
+ else if ((neq_vec effective_delg (EXTZ 64 (vec_of_bits [B0] : mword 1)))) then
+ Ints_Delegated
+ (effective_delg)
+ else Ints_Empty (tt).
+
+Definition getPendingSet (priv : Privilege)
+: M (option ((mword 64 * Privilege))) :=
+
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ assert_exp' w__0 "no user mode: M/U or M/S/U system required" >>= fun _ =>
+ read_reg mip_ref >>= fun w__1 : Minterrupts =>
+ read_reg mie_ref >>= fun w__2 : Minterrupts =>
+ let effective_pending := and_vec (_get_Minterrupts_bits w__1) (_get_Minterrupts_bits w__2) in
+ (if ((eq_vec effective_pending (EXTZ 64 (vec_of_bits [B0] : mword 1)))) then
+ returnm (None
+ : option ((mword 64 * Privilege)))
+ else
+ (or_boolM
+ (returnm ((neq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__3 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_MIE w__3) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun mIE =>
+ (and_boolM ((haveSupMode tt) : M (bool))
+ ((or_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2))
+ : bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv)
+ ((privLevel_to_bits Supervisor)
+ : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__6 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_SIE w__6) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool)))
+ : M (bool))) >>= fun sIE =>
+ (and_boolM ((haveNExt tt) : M (bool))
+ ((and_boolM
+ (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2))
+ : bool))
+ (read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_UIE w__10) ((bool_to_bits true) : mword 1))
+ : bool)))
+ : M (bool))) >>= fun uIE =>
+ read_reg mip_ref >>= fun w__12 : Minterrupts =>
+ read_reg mie_ref >>= fun w__13 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__14 : Minterrupts =>
+ (match (processPending w__12 w__13 (_get_Minterrupts_bits w__14) mIE) with
+ | Ints_Empty (tt) => returnm (None : option ((mword 64 * Privilege)))
+ | Ints_Pending (p) =>
+ let r := (p, Machine) in
+ returnm ((Some
+ (r))
+ : option ((mword 64 * Privilege)))
+ | Ints_Delegated (d) =>
+ (haveSupMode tt) >>= fun w__15 : bool =>
+ (if sumbool_of_bool ((negb w__15)) then
+ returnm ((if sumbool_of_bool (uIE) then
+ let r := (d, User) in
+ Some
+ (r)
+ else None)
+ : option ((mword 64 * Privilege)))
+ else
+ read_reg mie_ref >>= fun w__16 : Minterrupts =>
+ read_reg sideleg_ref >>= fun w__17 : Sinterrupts =>
+ returnm ((match (processPending (Mk_Minterrupts d) w__16 (_get_Sinterrupts_bits w__17)
+ sIE) with
+ | Ints_Empty (tt) => None
+ | Ints_Pending (p) =>
+ let r := (p, Supervisor) in
+ Some
+ (r)
+ | Ints_Delegated (d) =>
+ if sumbool_of_bool (uIE) then
+ let r := (d, User) in
+ Some
+ (r)
+ else None
+ end)
+ : option ((mword 64 * Privilege))))
+ : M (option ((mword 64 * Privilege)))
+ end)
+ : M (option ((mword 64 * Privilege))))
+ : M (option ((mword 64 * Privilege))).
+
+Definition dispatchInterrupt (priv : Privilege)
+: M (option ((InterruptType * Privilege))) :=
+
+ (or_boolM ((haveUsrMode tt) >>= fun w__0 : bool => returnm ((negb w__0) : bool))
+ ((and_boolM ((haveSupMode tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))
+ ((haveNExt tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool)))
+ : M (bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ assert_exp (eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) "invalid current privilege" >>
+ read_reg mip_ref >>= fun w__5 : Minterrupts =>
+ read_reg mie_ref >>= fun w__6 : Minterrupts =>
+ let enabled_pending := and_vec (_get_Minterrupts_bits w__5) (_get_Minterrupts_bits w__6) in
+ returnm ((match (findPendingInterrupt enabled_pending) with
+ | Some (i) =>
+ let r := (i, Machine) in
+ Some
+ (r)
+ | None => None
+ end)
+ : option ((InterruptType * Privilege)))
+ else
+ (getPendingSet priv) >>= fun w__7 : option ((mword 64 * Privilege)) =>
+ returnm ((match w__7 with
+ | None => None
+ | Some ((ip, p)) =>
+ match (findPendingInterrupt ip) with
+ | None => None
+ | Some (i) =>
+ let r := (i, p) in
+ Some
+ (r)
+ end
+ end)
+ : option ((InterruptType * Privilege))))
+ : M (option ((InterruptType * Privilege))).
+
+Definition tval (excinfo : option (mword 64))
+: mword 64 :=
+
+ match excinfo with | Some (e) => e | None => EXTZ 64 (vec_of_bits [B0] : mword 1) end.
+
+Definition rvfi_trap '(tt : unit) : unit := tt.
+
+Definition trap_handler
+(del_priv : Privilege) (intr : bool) (c : mword 8) (pc : mword 64) (info : option (mword 64))
+(ext : option unit)
+: M (mword 64) :=
+
+ let '_ := (rvfi_trap tt) : unit in
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "handling "
+ (String.append (if sumbool_of_bool (intr) then "int#" else "exc#")
+ (String.append (string_of_bits c)
+ (String.append " at priv "
+ (String.append (privLevel_to_str del_priv)
+ (String.append " with tval " (string_of_bits (tval info))))))))
+ else tt)
+ : unit in
+ let '_ := (cancel_reservation tt) : unit in
+ (match del_priv with
+ | Machine =>
+ (_set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause mcause_ref (EXTZ 63 c)) >>
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (_set_Mstatus_MPIE mstatus_ref (_get_Mstatus_MIE w__0)) >>
+ (_set_Mstatus_MIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits w__1)) >>
+ write_reg mtval_ref (tval info) >>
+ write_reg mepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__2))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg mcause_ref >>= fun w__3 : Mcause =>
+ (prepare_trap_vector del_priv w__3)
+ : M (mword 64)
+ | Supervisor =>
+ (haveSupMode tt) >>= fun w__5 : bool =>
+ assert_exp' w__5 "no supervisor mode present for delegation" >>= fun _ =>
+ (_set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause scause_ref (EXTZ 63 c)) >>
+ read_reg mstatus_ref >>= fun w__6 : Mstatus =>
+ (_set_Mstatus_SPIE mstatus_ref (_get_Mstatus_SIE w__6)) >>
+ (_set_Mstatus_SIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ read_reg cur_privilege_ref >>= fun w__7 : Privilege =>
+ (match w__7 with
+ | User => returnm ((bool_to_bits false) : mword 1)
+ | Supervisor => returnm ((bool_to_bits true) : mword 1)
+ | Machine => (internal_error "invalid privilege for s-mode trap") : M (mword 1)
+ end) >>= fun w__9 : mword 1 =>
+ (_set_Mstatus_SPP mstatus_ref w__9) >>
+ write_reg stval_ref (tval info) >>
+ write_reg sepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__10))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg scause_ref >>= fun w__11 : Mcause =>
+ (prepare_trap_vector del_priv w__11)
+ : M (mword 64)
+ | User =>
+ (haveUsrMode tt) >>= fun w__13 : bool =>
+ assert_exp' w__13 "no user mode present for delegation" >>= fun _ =>
+ (_set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr) : mword 1)) >>
+ (_set_Mcause_Cause ucause_ref (EXTZ 63 c)) >>
+ read_reg mstatus_ref >>= fun w__14 : Mstatus =>
+ (_set_Mstatus_UPIE mstatus_ref (_get_Mstatus_UIE w__14)) >>
+ (_set_Mstatus_UIE mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ write_reg utval_ref (tval info) >>
+ write_reg uepc_ref pc >>
+ write_reg cur_privilege_ref del_priv >>
+ let '_ := (handle_trap_extension del_priv pc ext) : unit in
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__15 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__15))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg ucause_ref >>= fun w__16 : Mcause =>
+ (prepare_trap_vector del_priv w__16)
+ : M (mword 64)
+ end)
+ : M (mword 64).
+
+Definition exception_handler (cur_priv : Privilege) (ctl : ctl_result) (pc : mword 64)
+: M (mword 64) :=
+
+ (match (cur_priv, ctl) with
+ | (_, CTL_TRAP (e)) =>
+ (exception_delegatee e.(sync_exception_trap) cur_priv) >>= fun del_priv =>
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "trapping from "
+ (String.append (privLevel_to_str cur_priv)
+ (String.append " to "
+ (String.append (privLevel_to_str del_priv)
+ (String.append " to handle "
+ (exceptionType_to_str e.(sync_exception_trap)))))))
+ else tt)
+ : unit in
+ (trap_handler del_priv false ((exceptionType_to_bits e.(sync_exception_trap)) : mword 8) pc
+ e.(sync_exception_excinfo) e.(sync_exception_ext))
+ : M (mword 64)
+ | (_, CTL_MRET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ (_set_Mstatus_MIE mstatus_ref (_get_Mstatus_MPIE w__1)) >>
+ (_set_Mstatus_MPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ (privLevel_of_bits (_get_Mstatus_MPP w__2)) >>= fun w__3 : Privilege =>
+ write_reg cur_privilege_ref w__3 >>
+ (haveUsrMode tt) >>= fun w__4 : bool =>
+ (_set_Mstatus_MPP mstatus_ref
+ (privLevel_to_bits (if sumbool_of_bool (w__4) then User else Machine))) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__5 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__5))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__6 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__6)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target Machine) >>= fun w__7 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__8 : mword 64 => returnm ((and_vec w__7 w__8) : mword 64)
+ | (_, CTL_SRET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__9 : Mstatus =>
+ (_set_Mstatus_SIE mstatus_ref (_get_Mstatus_SPIE w__9)) >>
+ (_set_Mstatus_SPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__10 : Mstatus =>
+ write_reg
+ cur_privilege_ref
+ (if ((eq_vec (_get_Mstatus_SPP w__10) ((bool_to_bits true) : mword 1))) then Supervisor
+ else User) >>
+ (_set_Mstatus_SPP mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__11 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__11))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__12 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__12)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target Supervisor) >>= fun w__13 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__14 : mword 64 =>
+ returnm ((and_vec w__13 w__14)
+ : mword 64)
+ | (_, CTL_URET (tt)) =>
+ read_reg cur_privilege_ref >>= fun prev_priv =>
+ read_reg mstatus_ref >>= fun w__15 : Mstatus =>
+ (_set_Mstatus_UIE mstatus_ref (_get_Mstatus_UPIE w__15)) >>
+ (_set_Mstatus_UPIE mstatus_ref ((bool_to_bits true) : mword 1)) >>
+ write_reg cur_privilege_ref User >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__16 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- " (string_of_bits (_get_Mstatus_bits w__16))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if ((get_config_print_platform tt)) then
+ read_reg cur_privilege_ref >>= fun w__17 : Privilege =>
+ returnm ((print_endline
+ (String.append "ret-ing from "
+ (String.append (privLevel_to_str prev_priv)
+ (String.append " to " (privLevel_to_str w__17)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ let '_ := (cancel_reservation tt) : unit in
+ (prepare_xret_target User) >>= fun w__18 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__19 : mword 64 =>
+ returnm ((and_vec w__18 w__19)
+ : mword 64)
+ end)
+ : M (mword 64).
+
+Definition handle_mem_exception (addr : mword 64) (e : ExceptionType)
+: M (unit) :=
+
+ let t : sync_exception :=
+ {| sync_exception_trap := e;
+ sync_exception_excinfo := (Some (addr));
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ (exception_handler w__0 (CTL_TRAP (t)) w__1) >>= fun w__2 : mword 64 =>
+ (set_next_pc w__2)
+ : M (unit).
+
+Definition handle_interrupt (i : InterruptType) (del_priv : Privilege)
+: M (unit) :=
+
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ (trap_handler del_priv true ((interruptType_to_bits i) : mword 8) w__0 None None) >>= fun w__1 : mword 64 =>
+ (set_next_pc w__1)
+ : M (unit).
+
+Definition init_sys '(tt : unit)
+: M (unit) :=
+
+ write_reg cur_privilege_ref Machine >>
+ write_reg mhartid_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ (_set_Misa_MXL misa_ref (arch_to_bits RV64)) >>
+ (_set_Misa_A misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_C misa_ref ((bool_to_bits (sys_enable_rvc tt)) : mword 1)) >>
+ (_set_Misa_I misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_M misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_U misa_ref ((bool_to_bits true) : mword 1)) >>
+ (_set_Misa_S misa_ref ((bool_to_bits true) : mword 1)) >>
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ read_reg misa_ref >>= fun w__1 : Misa =>
+ write_reg mstatus_ref (set_mstatus_SXL w__0 (_get_Misa_MXL w__1)) >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ read_reg misa_ref >>= fun w__3 : Misa =>
+ write_reg mstatus_ref (set_mstatus_UXL w__2 (_get_Misa_MXL w__3)) >>
+ (_set_Mstatus_SD mstatus_ref ((bool_to_bits false) : mword 1)) >>
+ (_set_Minterrupts_bits mip_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Minterrupts_bits mie_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Minterrupts_bits mideleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Medeleg_bits medeleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Mtvec_bits mtvec_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ (_set_Mcause_bits mcause_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ write_reg mepc_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mtval_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mscratch_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mcycle_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg mtime_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ (_set_Counteren_bits mcounteren_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >>
+ write_reg minstret_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg minstret_written_ref false >>
+ (init_pmp tt) >>
+ (if ((get_config_print_reg tt)) then
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ returnm ((print_endline
+ (String.append "CSR mstatus <- "
+ (String.append (string_of_bits (_get_Mstatus_bits w__4))
+ (String.append " (input: "
+ (String.append
+ (string_of_bits ((EXTZ 64 (vec_of_bits [B0] : mword 1)) : xlenbits))
+ ")")))))
+ : unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Axiom elf_tohost : forall (_ : unit) , Z.
+
+Axiom elf_entry : forall (_ : unit) , Z.
+
+Axiom plat_ram_base : forall (_ : unit) , mword 64.
+
+Axiom plat_ram_size : forall (_ : unit) , mword 64.
+
+Axiom plat_enable_pmp : forall (_ : unit) , bool.
+
+Axiom plat_enable_dirty_update : forall (_ : unit) , bool.
+
+Axiom plat_enable_misaligned_access : forall (_ : unit) , bool.
+
+Axiom plat_mtval_has_illegal_inst_bits : forall (_ : unit) , bool.
+
+Axiom plat_rom_base : forall (_ : unit) , mword 64.
+
+Axiom plat_rom_size : forall (_ : unit) , mword 64.
+
+Axiom plat_clint_base : forall (_ : unit) , mword 64.
+
+Axiom plat_clint_size : forall (_ : unit) , mword 64.
+
+Definition plat_htif_tohost '(tt : unit) : mword 64 := to_bits 64 (elf_tohost tt).
+
+Definition phys_mem_segments '(tt : unit)
+: list ((mword 64 * mword 64)) :=
+
+ (plat_rom_base tt, plat_rom_size tt) :: (plat_ram_base tt, plat_ram_size tt) :: [].
+
+Definition within_phys_mem (addr : mword 64) (width : Z) `{ArithFact (width <= 16)}
+: bool :=
+
+ let addr_int := projT1 (uint addr) in
+ let ram_base_int := projT1 (uint (plat_ram_base tt)) in
+ let rom_base_int := projT1 (uint (plat_rom_base tt)) in
+ let ram_size_int := projT1 (uint (plat_ram_size tt)) in
+ let rom_size_int := projT1 (uint (plat_rom_size tt)) in
+ if sumbool_of_bool ((andb (Z.leb ram_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width)))
+ (Z.add ram_base_int ram_size_int)))) then
+ true
+ else if sumbool_of_bool ((andb (Z.leb rom_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width)))
+ (Z.add rom_base_int rom_size_int)))) then
+ true
+ else
+ let '_ :=
+ (print_endline
+ (String.append "within_phys_mem: "
+ (String.append (string_of_bits addr) " not within phys-mem:")))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_rom_base: " (string_of_bits (plat_rom_base tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_rom_size: " (string_of_bits (plat_rom_size tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_ram_base: " (string_of_bits (plat_ram_base tt))))
+ : unit in
+ let '_ :=
+ (print_endline (String.append " plat_ram_size: " (string_of_bits (plat_ram_size tt))))
+ : unit in
+ false.
+
+Definition within_clint (addr : mword 64) (width : Z) `{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ let addr_int := projT1 (uint addr) in
+ let clint_base_int := projT1 (uint (plat_clint_base tt)) in
+ let clint_size_int := projT1 (uint (plat_clint_size tt)) in
+ andb (Z.leb clint_base_int addr_int)
+ (Z.leb (Z.add addr_int (projT1 (__id width))) (Z.add clint_base_int clint_size_int)).
+
+Definition within_htif_writable (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (eq_vec (plat_htif_tohost tt) addr)
+ (andb (eq_vec (add_vec_int (plat_htif_tohost tt) 4) addr) (Z.eqb width 4)).
+
+Definition within_htif_readable (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (eq_vec (plat_htif_tohost tt) addr)
+ (andb (eq_vec (add_vec_int (plat_htif_tohost tt) 4) addr) (Z.eqb width 4)).
+
+Axiom plat_insns_per_tick : forall (_ : unit) , Z.
+
+Definition MSIP_BASE : xlenbits :=
+EXTZ 64 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 20).
+Hint Unfold MSIP_BASE : sail.
+Definition MTIMECMP_BASE : xlenbits :=
+EXTZ 64 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 20).
+Hint Unfold MTIMECMP_BASE : sail.
+Definition MTIMECMP_BASE_HI : xlenbits :=
+EXTZ 64 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 20).
+Hint Unfold MTIMECMP_BASE_HI : sail.
+Definition MTIME_BASE : xlenbits :=
+EXTZ 64 (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0] : mword 20).
+Hint Unfold MTIME_BASE : sail.
+Definition MTIME_BASE_HI : xlenbits :=
+EXTZ 64 (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0] : mword 20).
+Hint Unfold MTIME_BASE_HI : sail.
+Definition clint_load (addr : mword 64) (width : Z) `{ArithFact (width > 0)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ let addr := sub_vec addr (plat_clint_base tt) in
+ (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE)
+ (orb (Z.eqb (projT1 (__id width)) 8) (Z.eqb (projT1 (__id width)) 4))))
+ then
+ (if ((get_config_print_platform tt)) then
+ read_reg mip_ref >>= fun w__0 : Minterrupts =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (_get_Minterrupts_MSI w__0))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ read_reg mip_ref >>= fun w__1 : Minterrupts =>
+ returnm ((MemValue
+ (zero_extend (_get_Minterrupts_MSI w__1) (Z.mul 8 (projT1 (__id width)))))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (subrange_vec_dec w__2 31 0))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__3 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 8)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__4 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint<8>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__4)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__5 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__5 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__6 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint-hi<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits (subrange_vec_dec w__6 63 32))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__7 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__7 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb (projT1 (__id width)) 4))) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__8 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__8)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__9 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__9 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb (projT1 (__id width)) 8))) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__10 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__10)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__11 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__11 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__12 : mword 64 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__12)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__13 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__13 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint[" (String.append (string_of_bits addr) "] -> <not-mapped>"))
+ else tt)
+ : unit in
+ returnm ((MemException
+ (E_Load_Access_Fault))
+ : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition clint_dispatch '(tt : unit)
+: M (unit) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline (String.append "clint::tick mtime <- " (string_of_bits w__0)))
+ : unit)
+ else returnm (tt : unit)) >>
+ (_set_Minterrupts_MTI mip_ref ((bool_to_bits false) : mword 1)) >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (if ((zopz0zIzJ_u w__1 w__2)) then
+ (if ((get_config_print_platform tt)) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((print_endline
+ (String.append " clint timer pending at mtime " (string_of_bits w__3)))
+ : unit)
+ else returnm (tt : unit)) >>
+ (_set_Minterrupts_MTI mip_ref ((bool_to_bits true) : mword 1))
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Definition clint_store (addr : mword 64) (width : Z) (data : mword (8 * width))
+`{ArithFact (width > 0)}
+: M (MemoryOpResult bool) :=
+
+ let addr := sub_vec addr (plat_clint_base tt) in
+ (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE)
+ (orb (Z.eqb (projT1 (__id width)) 8) (Z.eqb (projT1 (__id width)) 4))))
+ then
+ (if ((get_config_print_platform tt)) then
+ (cast_unit_vec (access_vec_dec data 0)) >>= fun w__0 : mword 1 =>
+ returnm ((print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] <- "
+ (String.append (string_of_bits data)
+ (String.append " (mip.MSI <- "
+ (String.append (string_of_bits w__0) ")")))))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (cast_unit_vec (access_vec_dec data 0)) >>= fun w__1 : mword 1 =>
+ (_set_Minterrupts_MSI mip_ref
+ ((bool_to_bits (eq_vec w__1 (vec_of_bits [B1] : mword 1)))
+ : mword 1)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 8)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<8>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ write_reg mtimecmp_ref (zero_extend data 64) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ write_reg mtimecmp_ref (update_subrange_vec_dec w__2 31 0 (zero_extend data 32)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE_HI) (Z.eqb (projT1 (__id width)) 4)))
+ then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint<4>["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))
+ else tt)
+ : unit in
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ write_reg mtimecmp_ref (update_subrange_vec_dec w__3 63 32 (zero_extend data 32)) >>
+ (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool)
+ else
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "clint["
+ (String.append (string_of_bits addr)
+ (String.append "] <- " (String.append (string_of_bits data) " (<unmapped>)"))))
+ else tt)
+ : unit in
+ returnm ((MemException
+ (E_SAMO_Access_Fault))
+ : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition tick_clock '(tt : unit)
+: M (unit) :=
+
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ write_reg mcycle_ref (add_vec_int w__0 1) >>
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg mtime_ref (add_vec_int w__1 1) >> (clint_dispatch tt) : M (unit).
+
+Axiom plat_term_write : forall (_ : mword 8) , unit.
+
+Axiom plat_term_read : forall (_ : unit) , mword 8.
+
+Definition Mk_htif_cmd (v : mword 64)
+: htif_cmd :=
+
+ {| htif_cmd_htif_cmd_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_htif_cmd_bits (v : htif_cmd)
+: mword 64 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0.
+
+Definition _set_htif_cmd_bits (r_ref : register_ref regstate register_value htif_cmd) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_bits (v : htif_cmd) (x : mword 64)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_htif_cmd_device (v : htif_cmd)
+: mword 8 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56.
+
+Definition _set_htif_cmd_device
+(r_ref : register_ref regstate register_value htif_cmd) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec v 7 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_device (v : htif_cmd) (x : mword 8)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_htif_cmd_cmd (v : htif_cmd)
+: mword 8 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48.
+
+Definition _set_htif_cmd_cmd (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec v 7 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_cmd (v : htif_cmd) (x : mword 8)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_htif_cmd_payload (v : htif_cmd)
+: mword 48 :=
+
+ subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0.
+
+Definition _set_htif_cmd_payload
+(r_ref : register_ref regstate register_value htif_cmd) (v : mword 48)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]}
+ : htif_cmd in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_htif_cmd_payload (v : htif_cmd) (x : mword 48)
+: htif_cmd :=
+
+ {[ v with
+ htif_cmd_htif_cmd_chunk_0 :=
+ (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}.
+
+Definition htif_load (addr : mword 64) (width : Z) `{ArithFact (width > 0)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline
+ (String.append "htif["
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits w__0)))))
+ : unit)
+ else returnm (tt : unit)) >>
+ (if sumbool_of_bool ((andb (Z.eqb width 8) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend w__1 _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (Z.eqb width 4) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__2 31 0) _))
+ : MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (Z.eqb width 4)
+ (eq_vec addr (add_vec_int (plat_htif_tohost tt) 4)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ returnm ((MemValue
+ (zero_extend (subrange_vec_dec w__3 63 32) _))
+ : MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition htif_store (addr : mword 64) (width : Z) (data : mword (8 * width))
+`{ArithFact (0 < width /\ width <= 8)}
+: M (MemoryOpResult bool) :=
+
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif["
+ (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))
+ else tt)
+ : unit in
+ (if sumbool_of_bool ((Z.eqb width 8)) then write_reg htif_tohost_ref (EXTZ 64 data) : M (unit)
+ else if sumbool_of_bool ((andb (Z.eqb width 4) (eq_vec addr (plat_htif_tohost tt)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ write_reg htif_tohost_ref (update_subrange_vec_dec w__0 31 0 (autocast (autocast data)))
+ : M (unit)
+ else if sumbool_of_bool ((andb (Z.eqb width 4)
+ (eq_vec addr (add_vec_int (plat_htif_tohost tt) 4)))) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ write_reg htif_tohost_ref (update_subrange_vec_dec w__1 63 32 (autocast (autocast data)))
+ : M (unit)
+ else write_reg htif_tohost_ref (EXTZ 64 data) : M (unit)) >>
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ let cmd := Mk_htif_cmd w__2 in
+ let b__0 := _get_htif_cmd_device cmd in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif-syscall-proxy cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))
+ else tt)
+ : unit in
+ (cast_unit_vec (access_vec_dec (_get_htif_cmd_payload cmd) 0)) >>= fun w__3 : mword 1 =>
+ (if ((eq_vec w__3 (vec_of_bits [B1] : mword 1))) then
+ write_reg htif_done_ref true >>
+ write_reg htif_exit_code_ref (shiftr (zero_extend (_get_htif_cmd_payload cmd) 64) 1)
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit)
+ else
+ returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then
+ let '_ :=
+ (if ((get_config_print_platform tt)) then
+ print_endline
+ (String.append "htif-term cmd: "
+ (string_of_bits (_get_htif_cmd_payload cmd)))
+ else tt)
+ : unit in
+ let b__2 := _get_htif_cmd_cmd cmd in
+ if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then tt
+ else if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then
+ plat_term_write (subrange_vec_dec (_get_htif_cmd_payload cmd) 7 0)
+ else print_endline (String.append "Unknown term cmd: " (string_of_bits b__2))
+ else print_endline (String.append "htif-???? cmd: " (string_of_bits data)))
+ : unit)) >>
+ returnm ((MemValue
+ (true))
+ : MemoryOpResult bool).
+
+Definition htif_tick '(tt : unit)
+: M (unit) :=
+
+ (if ((get_config_print_platform tt)) then
+ ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((print_endline (String.append "htif::tick " (string_of_bits w__0)))
+ : unit)
+ else returnm (tt : unit)) >>
+ write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))
+ : M (unit).
+
+Definition within_mmio_readable (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (within_clint addr width)
+ (andb (within_htif_readable addr width) (Z.leb 1 (projT1 (__id width)))).
+
+Definition within_mmio_writable (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: bool :=
+
+ orb (within_clint addr width)
+ (andb (within_htif_writable addr width) (Z.leb (projT1 (__id width)) 8)).
+
+Definition mmio_read (addr : mword 64) (width : Z) `{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((within_clint addr width)) then
+ (clint_load addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else if sumbool_of_bool ((andb (within_htif_readable addr width) (Z.leb 1 (projT1 (__id width)))))
+ then
+ (htif_load addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition mmio_write (addr : mword 64) (width : Z) (data : mword (8 * width))
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((within_clint addr width)) then (clint_store addr width data) : M (MemoryOpResult bool)
+ else if sumbool_of_bool ((andb (within_htif_writable addr width) (Z.leb (projT1 (__id width)) 8)))
+ then
+ (htif_store addr width data)
+ : M (MemoryOpResult bool)
+ else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition init_platform '(tt : unit)
+: M (unit) :=
+
+ write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >>
+ write_reg htif_done_ref false >>
+ write_reg htif_exit_code_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))
+ : M (unit).
+
+Definition tick_platform '(tt : unit) : M (unit) := (htif_tick tt) : M (unit).
+
+Definition handle_illegal '(tt : unit)
+: M (unit) :=
+
+ (if ((plat_mtval_has_illegal_inst_bits tt)) then
+ ((read_reg instbits_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm ((Some
+ (w__0))
+ : option (mword 64))
+ else returnm (None : option (mword 64))) >>= fun info =>
+ let t : sync_exception :=
+ {| sync_exception_trap := E_Illegal_Instr;
+ sync_exception_excinfo := info;
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (exception_handler w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 =>
+ (set_next_pc w__3)
+ : M (unit).
+
+Definition platform_wfi '(tt : unit)
+: M (unit) :=
+
+ let '_ := (cancel_reservation tt) : unit in
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ (if ((zopz0zI_u w__0 w__1)) then
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ write_reg mtime_ref w__2 >>
+ ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : mword 64 =>
+ write_reg mcycle_ref w__3
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Definition is_aligned_addr (addr : mword 64) (width : Z)
+: bool :=
+
+ Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) width)) 0.
+
+Definition phys_mem_read
+(t : AccessType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (match (aq, rl, res) with
+ | (false, false, false) =>
+ (read_ram Read_plain addr width) >>= fun w__0 : mword (8 * width) =>
+ returnm ((Some
+ (w__0))
+ : option (mword (8 * width)))
+ | (true, false, false) =>
+ (read_ram Read_RISCV_acquire addr width) >>= fun w__1 : mword (8 * width) =>
+ returnm ((Some
+ (w__1))
+ : option (mword (8 * width)))
+ | (true, true, false) =>
+ (read_ram Read_RISCV_strong_acquire addr width) >>= fun w__2 : mword (8 * width) =>
+ returnm ((Some
+ (w__2))
+ : option (mword (8 * width)))
+ | (false, false, true) =>
+ (read_ram Read_RISCV_reserved addr width) >>= fun w__3 : mword (8 * width) =>
+ returnm ((Some
+ (w__3))
+ : option (mword (8 * width)))
+ | (true, false, true) =>
+ (read_ram Read_RISCV_reserved_acquire addr width) >>= fun w__4 : mword (8 * width) =>
+ returnm ((Some
+ (w__4))
+ : option (mword (8 * width)))
+ | (true, true, true) =>
+ (read_ram Read_RISCV_reserved_strong_acquire addr width) >>= fun w__5 : mword (8 * width) =>
+ returnm ((Some
+ (w__5))
+ : option (mword (8 * width)))
+ | (false, true, false) => returnm (None : option (mword (8 * width)))
+ | (false, true, true) => returnm (None : option (mword (8 * width)))
+ end) >>= fun w__6 : option (mword (8 * width)) =>
+ let result := w__6 : option (bits (8 * width)) in
+ returnm ((match (t, result) with
+ | (Execute, None) => MemException (E_Fetch_Access_Fault)
+ | (Read, None) => MemException (E_Load_Access_Fault)
+ | (_, None) => MemException (E_SAMO_Access_Fault)
+ | (_, Some (v)) =>
+ let '_ :=
+ (if ((get_config_print_mem tt)) then
+ print_endline
+ (String.append "mem["
+ (String.append (accessType_to_str t)
+ (String.append ","
+ (String.append (string_of_bits addr)
+ (String.append "] -> " (string_of_bits v))))))
+ else tt)
+ : unit in
+ MemValue
+ (v)
+ end)
+ : MemoryOpResult (mword (8 * width))).
+
+Definition checked_mem_read
+(t : AccessType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((within_mmio_readable addr width)) then
+ (mmio_read addr width)
+ : M (MemoryOpResult (mword (8 * width)))
+ else if ((within_phys_mem addr width)) then
+ (phys_mem_read t addr width aq rl res)
+ : M (MemoryOpResult (mword (8 * width)))
+ else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition pmp_mem_read
+(t : AccessType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if ((negb (plat_enable_pmp tt))) then
+ (checked_mem_read t addr width aq rl res)
+ : M (MemoryOpResult (mword (8 * width)))
+ else
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2) >>= fun w__3 : Privilege =>
+ (pmpCheck addr width t w__3) >>= fun w__4 : option ExceptionType =>
+ (match w__4 with
+ | None => (checked_mem_read t addr width aq rl res) : M (MemoryOpResult (mword (8 * width)))
+ | Some (e) => returnm ((MemException (e)) : MemoryOpResult (mword (8 * width)))
+ end)
+ : M (MemoryOpResult (mword (8 * width))))
+ : M (MemoryOpResult (mword (8 * width))).
+
+Definition rvfi_read (addr : mword 64) (width : Z) (value : MemoryOpResult (mword (8 * width)))
+`{ArithFact (width > 0)}
+: unit :=
+
+ tt.
+
+Definition mem_read
+(typ : AccessType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult (mword (8 * width))) :=
+
+ (if sumbool_of_bool ((andb (orb aq res) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_Load_Addr_Align))
+ : MemoryOpResult (mword (8 * width)))
+ else
+ (match (aq, rl, res) with
+ | (false, true, false) => throw (Error_not_implemented ("load.rl"))
+ | (false, true, true) => throw (Error_not_implemented ("lr.rl"))
+ | (_, _, _) =>
+ (pmp_mem_read typ addr width aq rl res) : M (MemoryOpResult (mword (8 * width)))
+ end)
+ : M (MemoryOpResult (mword (8 * width)))) >>= fun result : MemoryOpResult (bits (8 * width)) =>
+ let '_ := (rvfi_read addr width result) : unit in
+ returnm (result
+ : MemoryOpResult (mword (8 * width))).
+
+Definition mem_write_ea (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (con : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult unit) :=
+
+ (if sumbool_of_bool ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_SAMO_Addr_Align))
+ : MemoryOpResult unit)
+ else
+ (match (aq, rl, con) with
+ | (false, false, false) =>
+ (write_ram_ea Write_plain addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit)
+ | (false, true, false) =>
+ (write_ram_ea Write_RISCV_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (false, false, true) =>
+ (write_ram_ea Write_RISCV_conditional addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (false, true, true) =>
+ (write_ram_ea Write_RISCV_conditional_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (true, false, false) => throw (Error_not_implemented ("store.aq"))
+ | (true, true, false) =>
+ (write_ram_ea Write_RISCV_strong_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ | (true, false, true) => throw (Error_not_implemented ("sc.aq"))
+ | (true, true, true) =>
+ (write_ram_ea Write_RISCV_conditional_strong_release addr width) >>
+ returnm ((MemValue
+ (tt))
+ : MemoryOpResult unit)
+ end)
+ : M (MemoryOpResult unit))
+ : M (MemoryOpResult unit).
+
+Definition rvfi_write (addr : mword 64) (width : Z) (value : mword (8 * width))
+`{ArithFact (width > 0)}
+: unit :=
+
+ tt.
+
+Definition phys_mem_write
+(wk : write_kind) (addr : mword 64) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ let '_ := (rvfi_write addr width data) : unit in
+ (write_ram wk addr width data meta) >>= fun w__0 : bool =>
+ let result := MemValue (w__0) in
+ let '_ :=
+ (if ((get_config_print_mem tt)) then
+ print_endline
+ (String.append "mem["
+ (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))
+ else tt)
+ : unit in
+ returnm (result
+ : MemoryOpResult bool).
+
+Definition checked_mem_write
+(wk : write_kind) (addr : mword 64) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((within_mmio_writable addr width)) then
+ (mmio_write addr width data)
+ : M (MemoryOpResult bool)
+ else if ((within_phys_mem addr width)) then
+ (phys_mem_write wk addr width data meta)
+ : M (MemoryOpResult bool)
+ else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition pmp_mem_write
+(wk : write_kind) (addr : mword 64) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (if ((negb (plat_enable_pmp tt))) then
+ (checked_mem_write wk addr width data meta)
+ : M (MemoryOpResult bool)
+ else
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2) >>= fun w__3 : Privilege =>
+ (pmpCheck addr width Write w__3) >>= fun w__4 : option ExceptionType =>
+ (match w__4 with
+ | None => (checked_mem_write wk addr width data meta) : M (MemoryOpResult bool)
+ | Some (e) => returnm ((MemException (e)) : MemoryOpResult bool)
+ end)
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition mem_write_value_meta
+(addr : mword 64) (width : Z) (value : mword (8 * width)) (meta : unit) (aq : bool) (rl : bool)
+(con : bool) `{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ let '_ := (rvfi_write addr width value) : unit in
+ (if sumbool_of_bool ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then
+ returnm ((MemException
+ (E_SAMO_Addr_Align))
+ : MemoryOpResult bool)
+ else
+ (match (aq, rl, con) with
+ | (false, false, false) =>
+ (pmp_mem_write Write_plain addr width value meta) : M (MemoryOpResult bool)
+ | (false, true, false) =>
+ (pmp_mem_write Write_RISCV_release addr width value meta) : M (MemoryOpResult bool)
+ | (false, false, true) =>
+ (pmp_mem_write Write_RISCV_conditional addr width value meta) : M (MemoryOpResult bool)
+ | (false, true, true) =>
+ (pmp_mem_write Write_RISCV_conditional_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, true, false) =>
+ (pmp_mem_write Write_RISCV_strong_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, true, true) =>
+ (pmp_mem_write Write_RISCV_conditional_strong_release addr width value meta)
+ : M (MemoryOpResult bool)
+ | (true, false, false) => throw (Error_not_implemented ("store.aq"))
+ | (true, false, true) => throw (Error_not_implemented ("sc.aq"))
+ end)
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool).
+
+Definition mem_write_value
+(addr : mword 64) (width : Z) (value : mword (8 * width)) (aq : bool) (rl : bool) (con : bool)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (MemoryOpResult bool) :=
+
+ (mem_write_value_meta addr width value default_meta aq rl con)
+ : M (MemoryOpResult bool).
+
+Definition PAGESIZE_BITS := 12.
+Hint Unfold PAGESIZE_BITS : sail.
+Definition Mk_PTE_Bits (v : mword 8)
+: PTE_Bits :=
+
+ {| PTE_Bits_PTE_Bits_chunk_0 := (subrange_vec_dec v 7 0) |}.
+
+Definition _get_PTE_Bits_bits (v : PTE_Bits)
+: mword 8 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0.
+
+Definition _set_PTE_Bits_bits (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_bits (v : PTE_Bits) (x : mword 8)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_PTE_Bits_D (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7.
+
+Definition _set_PTE_Bits_D (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_D (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_A (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6.
+
+Definition _set_PTE_Bits_A (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_A (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_G (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5.
+
+Definition _set_PTE_Bits_G (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_G (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_U (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4.
+
+Definition _set_PTE_Bits_U (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_U (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_X (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3.
+
+Definition _set_PTE_Bits_X (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_X (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_W (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2.
+
+Definition _set_PTE_Bits_W (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_W (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_R (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1.
+
+Definition _set_PTE_Bits_R (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_R (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_PTE_Bits_V (v : PTE_Bits)
+: mword 1 :=
+
+ subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0.
+
+Definition _set_PTE_Bits_V (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+ : PTE_Bits in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_PTE_Bits_V (v : PTE_Bits) (x : mword 1)
+: PTE_Bits :=
+
+ {[ v with
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition isPTEPtr (p : mword 8)
+: bool :=
+
+ let a := Mk_PTE_Bits p in
+ andb (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits false) : mword 1))
+ (eq_vec (_get_PTE_Bits_X a) ((bool_to_bits false) : mword 1))).
+
+Definition isInvalidPTE (p : mword 8)
+: bool :=
+
+ let a := Mk_PTE_Bits p in
+ orb (eq_vec (_get_PTE_Bits_V a) ((bool_to_bits false) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))).
+
+Definition checkPTEPermission
+(ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits)
+: M (bool) :=
+
+ (match (ac, priv) with
+ | (Read, User) =>
+ returnm (andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))
+ | (Write, User) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (ReadWrite, User) =>
+ returnm (andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))))
+ | (Execute, User) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1))
+ (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (Read, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))
+ | (Write, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)))
+ | (ReadWrite, Supervisor) =>
+ returnm (andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum)
+ (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))
+ (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1))
+ (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))))
+ | (Execute, Supervisor) =>
+ returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1))
+ (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)))
+ : bool)
+ | (_, Machine) => (internal_error "m-mode mem perm check") : M (bool)
+ end)
+ : M (bool).
+
+Definition update_PTE_Bits (p : PTE_Bits) (a : AccessType)
+: option PTE_Bits :=
+
+ let update_d :=
+ andb (orb (generic_eq a Write) (generic_eq a ReadWrite))
+ (eq_vec (_get_PTE_Bits_D p) ((bool_to_bits false) : mword 1)) in
+ let update_a := eq_vec (_get_PTE_Bits_A p) ((bool_to_bits false) : mword 1) in
+ if sumbool_of_bool ((orb update_d update_a)) then
+ let np := _update_PTE_Bits_A p ((bool_to_bits true) : mword 1) in
+ let np :=
+ if sumbool_of_bool (update_d) then _update_PTE_Bits_D np ((bool_to_bits true) : mword 1)
+ else np in
+ Some
+ (np)
+ else None.
+
+Definition PTW_Error_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)}
+: PTW_Error :=
+
+ let l__8 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__8 0)) then PTW_Access
+ else if sumbool_of_bool ((Z.eqb l__8 1)) then PTW_Invalid_PTE
+ else if sumbool_of_bool ((Z.eqb l__8 2)) then PTW_No_Permission
+ else if sumbool_of_bool ((Z.eqb l__8 3)) then PTW_Misaligned
+ else PTW_PTE_Update.
+
+Definition num_of_PTW_Error (arg_ : PTW_Error)
+: {e : Z & ArithFact (0 <= e /\ e <= 4)} :=
+
+ build_ex(match arg_ with
+ | PTW_Access => 0
+ | PTW_Invalid_PTE => 1
+ | PTW_No_Permission => 2
+ | PTW_Misaligned => 3
+ | PTW_PTE_Update => 4
+ end).
+
+Definition ptw_error_to_str (e : PTW_Error)
+: string :=
+
+ match e with
+ | PTW_Access => "mem-access-error"
+ | PTW_Invalid_PTE => "invalid-pte"
+ | PTW_No_Permission => "no-permission"
+ | PTW_Misaligned => "misaligned-superpage"
+ | PTW_PTE_Update => "pte-update-needed"
+ end.
+
+Definition translationException (a : AccessType) (f : PTW_Error)
+: ExceptionType :=
+
+ match (a, f) with
+ | (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+ | (ReadWrite, _) => E_SAMO_Page_Fault
+ | (Read, PTW_Access) => E_Load_Access_Fault
+ | (Read, _) => E_Load_Page_Fault
+ | (Write, PTW_Access) => E_SAMO_Access_Fault
+ | (Write, _) => E_SAMO_Page_Fault
+ | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+ | (Fetch, _) => E_Fetch_Page_Fault
+ end.
+
+Definition curAsid32 (satp : mword 32)
+: mword 9 :=
+
+ let s := Mk_Satp32 satp in
+ _get_Satp32_Asid s.
+
+Definition curPTB32 (satp : mword 32)
+: mword 34 :=
+
+ let s : Satp32 := Mk_Satp32 satp in
+ shiftl (EXTZ 34 (_get_Satp32_PPN s)) PAGESIZE_BITS.
+
+Definition SV32_LEVEL_BITS := 10.
+Hint Unfold SV32_LEVEL_BITS : sail.
+Definition SV32_LEVELS := 2.
+Hint Unfold SV32_LEVELS : sail.
+Definition PTE32_LOG_SIZE := 2.
+Hint Unfold PTE32_LOG_SIZE : sail.
+Definition PTE32_SIZE := 4.
+Hint Unfold PTE32_SIZE : sail.
+Definition Mk_SV32_Vaddr (v : mword 32)
+: SV32_Vaddr :=
+
+ {| SV32_Vaddr_SV32_Vaddr_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_SV32_Vaddr_bits (v : SV32_Vaddr)
+: mword 32 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0.
+
+Definition _set_SV32_Vaddr_bits
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 32)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_bits (v : SV32_Vaddr) (x : mword 32)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_SV32_Vaddr_VPNi (v : SV32_Vaddr)
+: mword 20 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12.
+
+Definition _set_SV32_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 20)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12 (subrange_vec_dec v 19 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_VPNi (v : SV32_Vaddr) (x : mword 20)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 31 12 (subrange_vec_dec x 19 0)) ]}.
+
+Definition _get_SV32_Vaddr_PgOfs (v : SV32_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV32_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV32_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV32_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Vaddr_PgOfs (v : SV32_Vaddr) (x : mword 12)
+: SV32_Vaddr :=
+
+ {[ v with
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Vaddr_SV32_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV32_Paddr (v : mword 34)
+: SV32_Paddr :=
+
+ {| SV32_Paddr_SV32_Paddr_chunk_0 := (subrange_vec_dec v 33 0) |}.
+
+Definition _get_SV32_Paddr_bits (v : SV32_Paddr)
+: mword 34 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0.
+
+Definition _set_SV32_Paddr_bits
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 34)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0 (subrange_vec_dec v 33 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_bits (v : SV32_Paddr) (x : mword 34)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 0 (subrange_vec_dec x 33 0)) ]}.
+
+Definition _get_SV32_Paddr_PPNi (v : SV32_Paddr)
+: mword 22 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12.
+
+Definition _set_SV32_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 22)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12 (subrange_vec_dec v 21 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_PPNi (v : SV32_Paddr) (x : mword 22)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 33 12 (subrange_vec_dec x 21 0)) ]}.
+
+Definition _get_SV32_Paddr_PgOfs (v : SV32_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0.
+
+Definition _set_SV32_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV32_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV32_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_Paddr_PgOfs (v : SV32_Paddr) (x : mword 12)
+: SV32_Paddr :=
+
+ {[ v with
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_Paddr_SV32_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV32_PTE (v : mword 32)
+: SV32_PTE :=
+
+ {| SV32_PTE_SV32_PTE_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_SV32_PTE_bits (v : SV32_PTE)
+: mword 32 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 0.
+
+Definition _set_SV32_PTE_bits (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 32)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_bits (v : SV32_PTE) (x : mword 32)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_SV32_PTE_PPNi (v : SV32_PTE)
+: mword 22 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 10.
+
+Definition _set_SV32_PTE_PPNi (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 22)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 31 10 (subrange_vec_dec v 21 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_PPNi (v : SV32_PTE) (x : mword 22)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 31 10 (subrange_vec_dec x 21 0)) ]}.
+
+Definition _get_SV32_PTE_RSW (v : SV32_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 9 8.
+
+Definition _set_SV32_PTE_RSW (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_RSW (v : SV32_PTE) (x : mword 2)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV32_PTE_BITS (v : SV32_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 7 0.
+
+Definition _set_SV32_PTE_BITS (r_ref : register_ref regstate register_value SV32_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV32_PTE_SV32_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV32_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV32_PTE_BITS (v : SV32_PTE) (x : mword 8)
+: SV32_PTE :=
+
+ {[ v with
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV32_PTE_SV32_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition curAsid64 (satp : mword 64)
+: mword 16 :=
+
+ let s := Mk_Satp64 satp in
+ _get_Satp64_Asid s.
+
+Definition curPTB64 (satp : mword 64)
+: mword 56 :=
+
+ let s := Mk_Satp64 satp in
+ shiftl (EXTZ 56 (_get_Satp64_PPN s)) PAGESIZE_BITS.
+
+Definition SV39_LEVEL_BITS := 9.
+Hint Unfold SV39_LEVEL_BITS : sail.
+Definition SV39_LEVELS := 3.
+Hint Unfold SV39_LEVELS : sail.
+Definition PTE39_LOG_SIZE := 3.
+Hint Unfold PTE39_LOG_SIZE : sail.
+Definition PTE39_SIZE := 8.
+Hint Unfold PTE39_SIZE : sail.
+Definition Mk_SV39_Vaddr (v : mword 39)
+: SV39_Vaddr :=
+
+ {| SV39_Vaddr_SV39_Vaddr_chunk_0 := (subrange_vec_dec v 38 0) |}.
+
+Definition _get_SV39_Vaddr_bits (v : SV39_Vaddr)
+: mword 39 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0.
+
+Definition _set_SV39_Vaddr_bits
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 39)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec v 38 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_bits (v : SV39_Vaddr) (x : mword 39)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec x 38 0)) ]}.
+
+Definition _get_SV39_Vaddr_VPNi (v : SV39_Vaddr)
+: mword 27 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12.
+
+Definition _set_SV39_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 27)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_VPNi (v : SV39_Vaddr) (x : mword 27)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_SV39_Vaddr_PgOfs (v : SV39_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV39_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV39_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Vaddr_PgOfs (v : SV39_Vaddr) (x : mword 12)
+: SV39_Vaddr :=
+
+ {[ v with
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV39_Paddr (v : mword 56)
+: SV39_Paddr :=
+
+ {| SV39_Paddr_SV39_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}.
+
+Definition _get_SV39_Paddr_bits (v : SV39_Paddr)
+: mword 56 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0.
+
+Definition _set_SV39_Paddr_bits
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 56)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_bits (v : SV39_Paddr) (x : mword 56)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}.
+
+Definition _get_SV39_Paddr_PPNi (v : SV39_Paddr)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12.
+
+Definition _set_SV39_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_PPNi (v : SV39_Paddr) (x : mword 44)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV39_Paddr_PgOfs (v : SV39_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0.
+
+Definition _set_SV39_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV39_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_Paddr_PgOfs (v : SV39_Paddr) (x : mword 12)
+: SV39_Paddr :=
+
+ {[ v with
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV39_PTE (v : mword 64)
+: SV39_PTE :=
+
+ {| SV39_PTE_SV39_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_SV39_PTE_bits (v : SV39_PTE)
+: mword 64 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0.
+
+Definition _set_SV39_PTE_bits (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_bits (v : SV39_PTE) (x : mword 64)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_SV39_PTE_PPNi (v : SV39_PTE)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10.
+
+Definition _set_SV39_PTE_PPNi (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 44)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_PPNi (v : SV39_PTE) (x : mword 44)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV39_PTE_RSW (v : SV39_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8.
+
+Definition _set_SV39_PTE_RSW (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_RSW (v : SV39_PTE) (x : mword 2)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV39_PTE_BITS (v : SV39_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0.
+
+Definition _set_SV39_PTE_BITS (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV39_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV39_PTE_BITS (v : SV39_PTE) (x : mword 8)
+: SV39_PTE :=
+
+ {[ v with
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition SV48_LEVEL_BITS := 9.
+Hint Unfold SV48_LEVEL_BITS : sail.
+Definition SV48_LEVELS := 4.
+Hint Unfold SV48_LEVELS : sail.
+Definition PTE48_LOG_SIZE := 3.
+Hint Unfold PTE48_LOG_SIZE : sail.
+Definition PTE48_SIZE := 8.
+Hint Unfold PTE48_SIZE : sail.
+Definition Mk_SV48_Vaddr (v : mword 48)
+: SV48_Vaddr :=
+
+ {| SV48_Vaddr_SV48_Vaddr_chunk_0 := (subrange_vec_dec v 47 0) |}.
+
+Definition _get_SV48_Vaddr_bits (v : SV48_Vaddr)
+: mword 48 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0.
+
+Definition _set_SV48_Vaddr_bits
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 48)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_bits (v : SV48_Vaddr) (x : mword 48)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}.
+
+Definition _get_SV48_Vaddr_VPNi (v : SV48_Vaddr)
+: mword 27 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12.
+
+Definition _set_SV48_Vaddr_VPNi
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 27)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_VPNi (v : SV48_Vaddr) (x : mword 27)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_SV48_Vaddr_PgOfs (v : SV48_Vaddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0.
+
+Definition _set_SV48_Vaddr_PgOfs
+(r_ref : register_ref regstate register_value SV48_Vaddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV48_Vaddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Vaddr_PgOfs (v : SV48_Vaddr) (x : mword 12)
+: SV48_Vaddr :=
+
+ {[ v with
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Vaddr_SV48_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV48_Paddr (v : mword 56)
+: SV48_Paddr :=
+
+ {| SV48_Paddr_SV48_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}.
+
+Definition _get_SV48_Paddr_bits (v : SV48_Paddr)
+: mword 56 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0.
+
+Definition _set_SV48_Paddr_bits
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 56)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_bits (v : SV48_Paddr) (x : mword 56)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}.
+
+Definition _get_SV48_Paddr_PPNi (v : SV48_Paddr)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12.
+
+Definition _set_SV48_Paddr_PPNi
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 44)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_PPNi (v : SV48_Paddr) (x : mword 44)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV48_Paddr_PgOfs (v : SV48_Paddr)
+: mword 12 :=
+
+ subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0.
+
+Definition _set_SV48_Paddr_PgOfs
+(r_ref : register_ref regstate register_value SV48_Paddr) (v : mword 12)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]}
+ : SV48_Paddr in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_Paddr_PgOfs (v : SV48_Paddr) (x : mword 12)
+: SV48_Paddr :=
+
+ {[ v with
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_Paddr_SV48_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}.
+
+Definition Mk_SV48_PTE (v : mword 64)
+: SV48_PTE :=
+
+ {| SV48_PTE_SV48_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_SV48_PTE_bits (v : SV48_PTE)
+: mword 64 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 63 0.
+
+Definition _set_SV48_PTE_bits (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 64)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_bits (v : SV48_PTE) (x : mword 64)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_SV48_PTE_PPNi (v : SV48_PTE)
+: mword 44 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 53 10.
+
+Definition _set_SV48_PTE_PPNi (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 44)
+
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_PPNi (v : SV48_PTE) (x : mword 44)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}.
+
+Definition _get_SV48_PTE_RSW (v : SV48_PTE)
+: mword 2 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 9 8.
+
+Definition _set_SV48_PTE_RSW (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 2)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_RSW (v : SV48_PTE) (x : mword 2)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_SV48_PTE_BITS (v : SV48_PTE)
+: mword 8 :=
+
+ subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 7 0.
+
+Definition _set_SV48_PTE_BITS (r_ref : register_ref regstate register_value SV48_PTE) (v : mword 8)
+: M (unit) :=
+
+ (reg_deref r_ref) >>= fun r =>
+ let r :=
+ {[ r with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec r.(SV48_PTE_SV48_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]}
+ : SV48_PTE in
+ write_reg r_ref r
+ : M (unit).
+
+Definition _update_SV48_PTE_BITS (v : SV48_PTE) (x : mword 8)
+: SV48_PTE :=
+
+ {[ v with
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ (update_subrange_vec_dec v.(SV48_PTE_SV48_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition make_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(asid : mword asidlen) (global : bool) (vAddr : mword valen) (pAddr : mword palen)
+(pte : mword ptelen) (level : Z) (pteAddr : mword palen) (levelBitSize : Z) `{ArithFact (valen > 0)}
+`{ArithFact (0 <= level)} `{ArithFact (0 <= levelBitSize)}
+: M (TLB_Entry asidlen valen palen ptelen) :=
+
+ let shift := Z.add PAGESIZE_BITS (Z.mul level levelBitSize) in
+ let vAddrMask : bits valen :=
+ sub_vec_int
+ (shiftl
+ (xor_vec vAddr (xor_vec vAddr (EXTZ (length_mword vAddr) (vec_of_bits [B1] : mword 1))))
+ shift) 1 in
+ let vMatchMask : bits valen := not_vec vAddrMask in
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ returnm (({| TLB_Entry_asid := asid;
+ TLB_Entry_global := global;
+ TLB_Entry_pte := pte;
+ TLB_Entry_pteAddr := pteAddr;
+ TLB_Entry_vAddrMask := vAddrMask;
+ TLB_Entry_vMatchMask := vMatchMask;
+ TLB_Entry_vAddr := (and_vec vAddr vMatchMask);
+ TLB_Entry_pAddr := (shiftl (shiftr pAddr shift) shift);
+ TLB_Entry_age := w__0 |})
+ : TLB_Entry asidlen valen palen ptelen).
+
+Definition match_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(ent : TLB_Entry asidlen valen palen ptelen) (asid : mword asidlen) (vaddr : mword valen)
+: bool :=
+
+ andb (orb ent.(TLB_Entry_global) (eq_vec ent.(TLB_Entry_asid) asid))
+ (eq_vec ent.(TLB_Entry_vAddr) (and_vec ent.(TLB_Entry_vMatchMask) vaddr)).
+
+Definition flush_TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z}
+(e : TLB_Entry asidlen valen palen ptelen) (asid : option (mword asidlen))
+(addr : option (mword valen))
+: bool :=
+
+ match (asid, addr) with
+ | (None, None) => true
+ | (None, Some (a)) => eq_vec e.(TLB_Entry_vAddr) (and_vec e.(TLB_Entry_vMatchMask) a)
+ | (Some (i), None) => andb (eq_vec e.(TLB_Entry_asid) i) (negb e.(TLB_Entry_global))
+ | (Some (i), Some (a)) =>
+ andb (eq_vec e.(TLB_Entry_asid) i)
+ (andb (eq_vec e.(TLB_Entry_vAddr) (and_vec a e.(TLB_Entry_vMatchMask)))
+ (negb e.(TLB_Entry_global)))
+ end.
+
+Fixpoint _rec_walk39
+(vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool)
+(ptb : mword 56) (level : Z) (global : bool) (_reclimit : Z) `{ArithFact (0 <= level)}
+(_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M (PTW_Result (mword 56) SV39_PTE) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let va := Mk_SV39_Vaddr vaddr in
+ let pt_ofs : paddr64 :=
+ shiftl
+ (EXTZ 56
+ (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul level SV39_LEVEL_BITS))
+ (Z.sub SV39_LEVEL_BITS 1) 0)) PTE39_LOG_SIZE in
+ let pte_addr := add_vec ptb pt_ofs in
+ (mem_read ac (EXTZ 64 pte_addr) 8 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 8)) =>
+ (match w__0 with
+ | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result (mword 56) SV39_PTE)
+ | MemValue (v) =>
+ let pte := Mk_SV39_PTE v in
+ let pbits := _get_SV39_PTE_BITS pte in
+ let pattr := Mk_PTE_Bits pbits in
+ let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in
+ (if ((isInvalidPTE pbits)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 56) SV39_PTE)
+ else if ((isPTEPtr pbits)) then
+ (if sumbool_of_bool ((Z.eqb level 0)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 56) SV39_PTE)
+ else
+ (_rec_walk39 vaddr ac priv mxr do_sum
+ (shiftl (EXTZ 56 (_get_SV39_PTE_PPNi pte)) PAGESIZE_BITS) (Z.sub level 1) is_global
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (PTW_Result (mword 56) SV39_PTE))
+ : M (PTW_Result (mword 56) SV39_PTE)
+ else
+ (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool =>
+ returnm ((if sumbool_of_bool ((negb w__3)) then PTW_Failure (PTW_No_Permission)
+ else if sumbool_of_bool ((Z.gtb level 0)) then
+ let mask :=
+ sub_vec_int
+ (shiftl
+ (xor_vec (_get_SV39_PTE_PPNi pte)
+ (xor_vec (_get_SV39_PTE_PPNi pte)
+ (EXTZ 44 (vec_of_bits [B1] : mword 1))))
+ (Z.mul level SV39_LEVEL_BITS)) 1 in
+ if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask)
+ (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then
+ PTW_Failure
+ (PTW_Misaligned)
+ else
+ let ppn :=
+ or_vec (_get_SV39_PTE_PPNi pte)
+ (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in
+ PTW_Success
+ ((concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global))
+ else
+ PTW_Success
+ ((concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global)))
+ : PTW_Result (mword 56) SV39_PTE))
+ : M (PTW_Result (mword 56) SV39_PTE)
+ end)
+ : M (PTW_Result (mword 56) SV39_PTE).
+
+Definition walk39
+(_arg0 : mword 39) (_arg1 : AccessType) (_arg2 : Privilege) (_arg3 : bool) (_arg4 : bool)
+(_arg5 : mword 56) (level : Z) (_arg7 : bool) `{ArithFact (0 <= level)}
+: M (PTW_Result (mword 56) SV39_PTE) :=
+
+ (_rec_walk39 _arg0 _arg1 _arg2 _arg3 _arg4 _arg5 level _arg7 (level : Z) (Zwf_guarded _))
+ : M (PTW_Result (mword 56) SV39_PTE).
+
+Definition lookup_TLB39 (asid : mword 16) (vaddr : mword 39)
+: M (option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 16 39 56 64))) :=
+
+ read_reg tlb39_ref >>= fun w__0 : option (TLB_Entry 16 39 56 64) =>
+ returnm ((match w__0 with
+ | None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((build_ex 0, e)) else None
+ end)
+ : option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 16 39 56 64))).
+
+Definition add_to_TLB39
+(asid : mword 16) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (pteAddr : mword 56)
+(level : Z) (global : bool) `{ArithFact (0 <= level)}
+: M (unit) :=
+
+ (make_TLB_Entry asid global vAddr pAddr (_get_SV39_PTE_bits pte) level pteAddr SV39_LEVEL_BITS) >>= fun ent : TLB39_Entry =>
+ write_reg tlb39_ref (Some (ent))
+ : M (unit).
+
+Definition write_TLB39 (idx : Z) (ent : TLB_Entry 16 39 56 64) `{ArithFact (0 <= idx)}
+: M (unit) :=
+
+ write_reg tlb39_ref (Some (ent))
+ : M (unit).
+
+Definition flush_TLB39 (asid : option (mword 16)) (addr : option (mword 39))
+: M (unit) :=
+
+ read_reg tlb39_ref >>= fun w__0 : option (TLB_Entry 16 39 56 64) =>
+ (match w__0 with
+ | None => returnm (tt : unit)
+ | Some (e) =>
+ (if ((flush_TLB_Entry e asid addr)) then write_reg tlb39_ref None : M (unit)
+ else returnm (tt : unit))
+ : M (unit)
+ end)
+ : M (unit).
+
+Definition translate39
+(asid : mword 16) (ptb : mword 56) (vAddr : mword 39) (ac : AccessType) (priv : Privilege)
+(mxr : bool) (do_sum : bool) (level : Z) `{ArithFact (0 <= level)}
+: M (TR_Result (mword 56) PTW_Error) :=
+
+ (lookup_TLB39 asid vAddr) >>= fun w__0 : option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 16 39 56 64)) =>
+ (match w__0 with
+ | Some ((existT _ idx _, ent)) =>
+ let pte := Mk_SV39_PTE ent.(TLB_Entry_pte) in
+ let pteBits := Mk_PTE_Bits (_get_SV39_PTE_BITS pte) in
+ (checkPTEPermission ac priv mxr do_sum pteBits) >>= fun w__1 : bool =>
+ (if sumbool_of_bool ((negb w__1)) then
+ returnm ((TR_Failure
+ (PTW_No_Permission))
+ : TR_Result (mword 56) PTW_Error)
+ else
+ (match (update_PTE_Bits pteBits ac) with
+ | None =>
+ returnm ((TR_Address
+ (or_vec ent.(TLB_Entry_pAddr)
+ (EXTZ 56 (and_vec vAddr ent.(TLB_Entry_vAddrMask)))))
+ : TR_Result (mword 56) PTW_Error)
+ | Some (pbits) =>
+ (if ((negb (plat_enable_dirty_update tt))) then
+ returnm ((TR_Failure
+ (PTW_PTE_Update))
+ : TR_Result (mword 56) PTW_Error)
+ else
+ let n_pte := _update_SV39_PTE_BITS pte (_get_PTE_Bits_bits pbits) in
+ let n_ent : TLB39_Entry := ent in
+ let n_ent :=
+ {[ n_ent with TLB_Entry_pte := (_get_SV39_PTE_bits n_pte) ]}
+ : TLB_Entry 16 39 56 64 in
+ (write_TLB39 idx n_ent) >>
+ (mem_write_value (EXTZ 64 ent.(TLB_Entry_pteAddr)) 8 (_get_SV39_PTE_bits n_pte)
+ false false false) >>= fun w__2 : MemoryOpResult bool =>
+ (match w__2 with
+ | MemValue (_) => returnm (tt : unit)
+ | MemException (e) =>
+ (internal_error "invalid physical address in TLB") : M (unit)
+ end) >>
+ returnm ((TR_Address
+ (or_vec ent.(TLB_Entry_pAddr)
+ (EXTZ 56 (and_vec vAddr ent.(TLB_Entry_vAddrMask)))))
+ : TR_Result (mword 56) PTW_Error))
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error))
+ : M (TR_Result (mword 56) PTW_Error)
+ | None =>
+ (walk39 vAddr ac priv mxr do_sum ptb level false) >>= fun w__6 : PTW_Result (mword 56) SV39_PTE =>
+ (match w__6 with
+ | PTW_Failure (f) => returnm ((TR_Failure (f)) : TR_Result (mword 56) PTW_Error)
+ | PTW_Success ((pAddr, pte, pteAddr, existT _ level _, global)) =>
+ (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV39_PTE_BITS pte)) ac) with
+ | None =>
+ (add_to_TLB39 asid vAddr pAddr pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 56) PTW_Error)
+ | Some (pbits) =>
+ (if ((negb (plat_enable_dirty_update tt))) then
+ returnm ((TR_Failure
+ (PTW_PTE_Update))
+ : TR_Result (mword 56) PTW_Error)
+ else
+ let w_pte : SV39_PTE := _update_SV39_PTE_BITS pte (_get_PTE_Bits_bits pbits) in
+ (mem_write_value (EXTZ 64 pteAddr) 8 (_get_SV39_PTE_bits w_pte) false false false) >>= fun w__7 : MemoryOpResult bool =>
+ (match w__7 with
+ | MemValue (_) =>
+ (add_to_TLB39 asid vAddr pAddr w_pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 56) PTW_Error)
+ | MemException (e) =>
+ returnm ((TR_Failure (PTW_Access)) : TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error))
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error).
+
+Definition init_vmem_sv39 '(tt : unit) : M (unit) := write_reg tlb39_ref None : M (unit).
+
+Fixpoint _rec_walk48
+(vaddr : mword 48) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool)
+(ptb : mword 56) (level : Z) (global : bool) (_reclimit : Z) `{ArithFact (0 <= level)}
+(_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M (PTW_Result (mword 56) SV48_PTE) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let va := Mk_SV48_Vaddr vaddr in
+ let pt_ofs : paddr64 :=
+ shiftl
+ (EXTZ 56
+ (subrange_vec_dec (shiftr (_get_SV48_Vaddr_VPNi va) (Z.mul level SV48_LEVEL_BITS))
+ (Z.sub SV48_LEVEL_BITS 1) 0)) PTE48_LOG_SIZE in
+ let pte_addr := add_vec ptb pt_ofs in
+ (mem_read ac (EXTZ 64 pte_addr) 8 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 8)) =>
+ (match w__0 with
+ | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result (mword 56) SV48_PTE)
+ | MemValue (v) =>
+ let pte := Mk_SV48_PTE v in
+ let pbits := _get_SV48_PTE_BITS pte in
+ let pattr := Mk_PTE_Bits pbits in
+ let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in
+ (if ((isInvalidPTE pbits)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 56) SV48_PTE)
+ else if ((isPTEPtr pbits)) then
+ (if sumbool_of_bool ((Z.eqb level 0)) then
+ returnm ((PTW_Failure
+ (PTW_Invalid_PTE))
+ : PTW_Result (mword 56) SV48_PTE)
+ else
+ (_rec_walk48 vaddr ac priv mxr do_sum
+ (shiftl (EXTZ 56 (_get_SV48_PTE_PPNi pte)) PAGESIZE_BITS) (Z.sub level 1) is_global
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (PTW_Result (mword 56) SV48_PTE))
+ : M (PTW_Result (mword 56) SV48_PTE)
+ else
+ (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool =>
+ returnm ((if sumbool_of_bool ((negb w__3)) then PTW_Failure (PTW_No_Permission)
+ else if sumbool_of_bool ((Z.gtb level 0)) then
+ let mask :=
+ sub_vec_int
+ (shiftl
+ (xor_vec (_get_SV48_PTE_PPNi pte)
+ (xor_vec (_get_SV48_PTE_PPNi pte)
+ (EXTZ 44 (vec_of_bits [B1] : mword 1))))
+ (Z.mul level SV48_LEVEL_BITS)) 1 in
+ if ((neq_vec (and_vec (_get_SV48_PTE_PPNi pte) mask)
+ (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then
+ PTW_Failure
+ (PTW_Misaligned)
+ else
+ let ppn :=
+ or_vec (_get_SV48_PTE_PPNi pte)
+ (and_vec (EXTZ 44 (_get_SV48_Vaddr_VPNi va)) mask) in
+ PTW_Success
+ ((concat_vec ppn (_get_SV48_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global))
+ else
+ PTW_Success
+ ((concat_vec (_get_SV48_PTE_PPNi pte) (_get_SV48_Vaddr_PgOfs va), pte, pte_addr, build_ex
+ level, is_global)))
+ : PTW_Result (mword 56) SV48_PTE))
+ : M (PTW_Result (mword 56) SV48_PTE)
+ end)
+ : M (PTW_Result (mword 56) SV48_PTE).
+
+Definition walk48
+(_arg0 : mword 48) (_arg1 : AccessType) (_arg2 : Privilege) (_arg3 : bool) (_arg4 : bool)
+(_arg5 : mword 56) (level : Z) (_arg7 : bool) `{ArithFact (0 <= level)}
+: M (PTW_Result (mword 56) SV48_PTE) :=
+
+ (_rec_walk48 _arg0 _arg1 _arg2 _arg3 _arg4 _arg5 level _arg7 (level : Z) (Zwf_guarded _))
+ : M (PTW_Result (mword 56) SV48_PTE).
+
+Definition lookup_TLB48 (asid : mword 16) (vaddr : mword 48)
+: M (option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 16 48 56 64))) :=
+
+ read_reg tlb48_ref >>= fun w__0 : option (TLB_Entry 16 48 56 64) =>
+ returnm ((match w__0 with
+ | None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((build_ex 0, e)) else None
+ end)
+ : option (({n : Z & ArithFact (n >= 0)} * TLB_Entry 16 48 56 64))).
+
+Definition add_to_TLB48
+(asid : mword 16) (vAddr : mword 48) (pAddr : mword 56) (pte : SV48_PTE) (pteAddr : mword 56)
+(level : Z) (global : bool) `{ArithFact (0 <= level)}
+: M (unit) :=
+
+ (make_TLB_Entry asid global vAddr pAddr (_get_SV48_PTE_bits pte) level pteAddr SV48_LEVEL_BITS) >>= fun ent : TLB48_Entry =>
+ write_reg tlb48_ref (Some (ent))
+ : M (unit).
+
+Definition write_TLB48 (idx : Z) (ent : TLB_Entry 16 48 56 64) `{ArithFact (0 <= idx)}
+: M (unit) :=
+
+ write_reg tlb48_ref (Some (ent))
+ : M (unit).
+
+Definition flush_TLB48 (asid : option (mword 16)) (addr : option (mword 48))
+: M (unit) :=
+
+ read_reg tlb48_ref >>= fun w__0 : option (TLB_Entry 16 48 56 64) =>
+ (match w__0 with
+ | None => returnm (tt : unit)
+ | Some (e) =>
+ (if ((flush_TLB_Entry e asid addr)) then write_reg tlb48_ref None : M (unit)
+ else returnm (tt : unit))
+ : M (unit)
+ end)
+ : M (unit).
+
+Definition translate48
+(asid : mword 16) (ptb : mword 56) (vAddr : mword 48) (ac : AccessType) (priv : Privilege)
+(mxr : bool) (do_sum : bool) (level : Z) `{ArithFact (0 <= level)}
+: M (TR_Result (mword 56) PTW_Error) :=
+
+ (walk48 vAddr ac priv mxr do_sum ptb level false) >>= fun w__0 : PTW_Result (mword 56) SV48_PTE =>
+ (match w__0 with
+ | PTW_Failure (f) => returnm ((TR_Failure (f)) : TR_Result (mword 56) PTW_Error)
+ | PTW_Success ((pAddr, pte, pteAddr, existT _ level _, global)) =>
+ (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV48_PTE_BITS pte)) ac) with
+ | None =>
+ (add_to_TLB48 asid vAddr pAddr pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 56) PTW_Error)
+ | Some (pbits) =>
+ (if ((negb (plat_enable_dirty_update tt))) then
+ returnm ((TR_Failure
+ (PTW_PTE_Update))
+ : TR_Result (mword 56) PTW_Error)
+ else
+ let w_pte : SV48_PTE := _update_SV48_PTE_BITS pte (_get_PTE_Bits_bits pbits) in
+ (mem_write_value (EXTZ 64 pteAddr) 8 (_get_SV48_PTE_bits w_pte) false false false) >>= fun w__1 : MemoryOpResult bool =>
+ (match w__1 with
+ | MemValue (_) =>
+ (add_to_TLB48 asid vAddr pAddr w_pte pteAddr level global) >>
+ returnm ((TR_Address
+ (pAddr))
+ : TR_Result (mword 56) PTW_Error)
+ | MemException (e) =>
+ returnm ((TR_Failure (PTW_Access)) : TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error))
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error)
+ end)
+ : M (TR_Result (mword 56) PTW_Error).
+
+Definition init_vmem_sv48 '(tt : unit) : M (unit) := write_reg tlb48_ref None : M (unit).
+
+Definition legalize_satp (a : Architecture) (o : mword 64) (v : mword 64)
+: mword 64 :=
+
+ legalize_satp64 a o v.
+
+Definition translationMode (priv : Privilege)
+: M (SATPMode) :=
+
+ (if ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))) then
+ returnm (Sbare
+ : SATPMode)
+ else
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ let arch := architecture (get_mstatus_SXL w__0) in
+ (match arch with
+ | Some (RV64) =>
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ let mbits : satp_mode := _get_Satp64_Mode (Mk_Satp64 w__1) in
+ (match (satp64Mode_of_bits RV64 mbits) with
+ | Some (m) => returnm (m : SATPMode)
+ | None => (internal_error "invalid RV64 translation mode in satp") : M (SATPMode)
+ end)
+ : M (SATPMode)
+ | Some (RV32) =>
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__4 : mword 64 =>
+ let s := Mk_Satp32 (subrange_vec_dec w__4 31 0) in
+ returnm ((if ((eq_vec (_get_Satp32_Mode s) ((bool_to_bits false) : mword 1))) then Sbare
+ else Sv32)
+ : SATPMode)
+ | _ => (internal_error "unsupported address translation arch") : M (SATPMode)
+ end)
+ : M (SATPMode))
+ : M (SATPMode).
+
+Definition translateAddr (vAddr : mword 64) (ac : AccessType)
+: M (TR_Result (mword 64) ExceptionType) :=
+
+ (match ac with
+ | Execute => read_reg cur_privilege_ref : M (Privilege)
+ | _ =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (effectivePrivilege w__1 w__2)
+ : M (Privilege)
+ end) >>= fun effPriv : Privilege =>
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ let mxr : bool := eq_vec (_get_Mstatus_MXR w__4) ((bool_to_bits true) : mword 1) in
+ read_reg mstatus_ref >>= fun w__5 : Mstatus =>
+ let do_sum : bool := eq_vec (_get_Mstatus_SUM w__5) ((bool_to_bits true) : mword 1) in
+ (translationMode effPriv) >>= fun mode : SATPMode =>
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__6 : mword 64 =>
+ let asid := curAsid64 w__6 in
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__7 : mword 64 =>
+ let ptb := curPTB64 w__7 in
+ (match mode with
+ | Sbare => returnm ((TR_Address (vAddr)) : TR_Result (mword 64) ExceptionType)
+ | Sv39 =>
+ (translate39 asid ptb (subrange_vec_dec vAddr 38 0) ac effPriv mxr do_sum
+ (Z.sub SV39_LEVELS 1)) >>= fun w__8 : TR_Result (mword 56) PTW_Error =>
+ returnm ((match w__8 with
+ | TR_Address (pa) => TR_Address (EXTZ 64 pa)
+ | TR_Failure (f) => TR_Failure (translationException ac f)
+ end)
+ : TR_Result (mword 64) ExceptionType)
+ | Sv48 =>
+ (translate48 asid ptb (subrange_vec_dec vAddr 47 0) ac effPriv mxr do_sum
+ (Z.sub SV48_LEVELS 1)) >>= fun w__9 : TR_Result (mword 56) PTW_Error =>
+ returnm ((match w__9 with
+ | TR_Address (pa) => TR_Address (EXTZ 64 pa)
+ | TR_Failure (f) => TR_Failure (translationException ac f)
+ end)
+ : TR_Result (mword 64) ExceptionType)
+ | _ =>
+ (internal_error "unsupported address translation scheme")
+ : M (TR_Result (mword 64) ExceptionType)
+ end)
+ : M (TR_Result (mword 64) ExceptionType).
+
+Definition flush_TLB (asid_xlen : option (mword 64)) (addr_xlen : option (mword 64))
+: M (unit) :=
+
+ let '(addr39, addr48) :=
+ (match addr_xlen with
+ | None => (None, None)
+ | Some (a) => (Some (subrange_vec_dec a 38 0), Some (subrange_vec_dec a 47 0))
+ end)
+ : (option vaddr39 * option vaddr48) in
+ let asid : option asid64 :=
+ match asid_xlen with | None => None | Some (a) => Some (subrange_vec_dec a 15 0) end in
+ (flush_TLB39 asid addr39) >> (flush_TLB48 asid addr48) : M (unit).
+
+Definition init_vmem '(tt : unit)
+: M (unit) :=
+
+ (init_vmem_sv39 tt) >> (init_vmem_sv48 tt) : M (unit).
+
+Definition encdec_uop_forwards (arg_ : uop)
+: mword 7 :=
+
+ match arg_ with
+ | RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7)
+ | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7)
+ end.
+
+Definition encdec_uop_backwards (arg_ : mword 7)
+: M (uop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then
+ returnm (RISCV_LUI
+ : uop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then
+ returnm (RISCV_AUIPC
+ : uop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (uop).
+
+Definition encdec_uop_forwards_matches (arg_ : uop)
+: bool :=
+
+ match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end.
+
+Definition encdec_uop_backwards_matches (arg_ : mword 7)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then true
+ else false.
+
+Definition utype_mnemonic_forwards (arg_ : uop)
+: string :=
+
+ match arg_ with | RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" end.
+
+Definition utype_mnemonic_backwards (arg_ : string)
+: M (uop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "lui")) then returnm (RISCV_LUI : uop)
+ else if ((generic_eq p0_ "auipc")) then returnm (RISCV_AUIPC : uop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (uop).
+
+Definition utype_mnemonic_forwards_matches (arg_ : uop)
+: bool :=
+
+ match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end.
+
+Definition utype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "lui")) then true
+ else if ((generic_eq p0_ "auipc")) then true
+ else false.
+
+Definition _s496_ (_s497_ : string)
+: option string :=
+
+ let _s498_ := _s497_ in
+ if ((string_startswith _s498_ "auipc")) then
+ match (string_drop _s498_ (projT1 (string_length "auipc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s492_ (_s493_ : string)
+: option string :=
+
+ let _s494_ := _s493_ in
+ if ((string_startswith _s494_ "lui")) then
+ match (string_drop _s494_ (projT1 (string_length "lui"))) with | s_ => Some (s_) end
+ else None.
+
+Definition utype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((uop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s495_ := arg_ in
+ (if ((match (_s492_ _s495_) with | Some (s_) => true | _ => false end)) then
+ (match (_s492_ _s495_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_LUI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((uop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s496_ _s495_) with | Some (s_) => true | _ => false end)) then
+ (match (_s496_ _s495_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_AUIPC, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((uop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((uop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((uop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_bop_forwards (arg_ : bop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_BEQ => (vec_of_bits [B0;B0;B0] : mword 3)
+ | RISCV_BNE => (vec_of_bits [B0;B0;B1] : mword 3)
+ | RISCV_BLT => (vec_of_bits [B1;B0;B0] : mword 3)
+ | RISCV_BGE => (vec_of_bits [B1;B0;B1] : mword 3)
+ | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : mword 3)
+ | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : mword 3)
+ end.
+
+Definition encdec_bop_backwards (arg_ : mword 3)
+: M (bop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (RISCV_BEQ : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (RISCV_BNE : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm (RISCV_BLT : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_BGE : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm (RISCV_BLTU : bop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm (RISCV_BGEU : bop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bop).
+
+Definition encdec_bop_forwards_matches (arg_ : bop)
+: bool :=
+
+ match arg_ with
+ | RISCV_BEQ => true
+ | RISCV_BNE => true
+ | RISCV_BLT => true
+ | RISCV_BGE => true
+ | RISCV_BLTU => true
+ | RISCV_BGEU => true
+ end.
+
+Definition encdec_bop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else false.
+
+Definition btype_mnemonic_forwards (arg_ : bop)
+: string :=
+
+ match arg_ with
+ | RISCV_BEQ => "beq"
+ | RISCV_BNE => "bne"
+ | RISCV_BLT => "blt"
+ | RISCV_BGE => "bge"
+ | RISCV_BLTU => "bltu"
+ | RISCV_BGEU => "bgeu"
+ end.
+
+Definition btype_mnemonic_backwards (arg_ : string)
+: M (bop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "beq")) then returnm (RISCV_BEQ : bop)
+ else if ((generic_eq p0_ "bne")) then returnm (RISCV_BNE : bop)
+ else if ((generic_eq p0_ "blt")) then returnm (RISCV_BLT : bop)
+ else if ((generic_eq p0_ "bge")) then returnm (RISCV_BGE : bop)
+ else if ((generic_eq p0_ "bltu")) then returnm (RISCV_BLTU : bop)
+ else if ((generic_eq p0_ "bgeu")) then returnm (RISCV_BGEU : bop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bop).
+
+Definition btype_mnemonic_forwards_matches (arg_ : bop)
+: bool :=
+
+ match arg_ with
+ | RISCV_BEQ => true
+ | RISCV_BNE => true
+ | RISCV_BLT => true
+ | RISCV_BGE => true
+ | RISCV_BLTU => true
+ | RISCV_BGEU => true
+ end.
+
+Definition btype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "beq")) then true
+ else if ((generic_eq p0_ "bne")) then true
+ else if ((generic_eq p0_ "blt")) then true
+ else if ((generic_eq p0_ "bge")) then true
+ else if ((generic_eq p0_ "bltu")) then true
+ else if ((generic_eq p0_ "bgeu")) then true
+ else false.
+
+Definition _s520_ (_s521_ : string)
+: option string :=
+
+ let _s522_ := _s521_ in
+ if ((string_startswith _s522_ "bgeu")) then
+ match (string_drop _s522_ (projT1 (string_length "bgeu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s516_ (_s517_ : string)
+: option string :=
+
+ let _s518_ := _s517_ in
+ if ((string_startswith _s518_ "bltu")) then
+ match (string_drop _s518_ (projT1 (string_length "bltu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s512_ (_s513_ : string)
+: option string :=
+
+ let _s514_ := _s513_ in
+ if ((string_startswith _s514_ "bge")) then
+ match (string_drop _s514_ (projT1 (string_length "bge"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s508_ (_s509_ : string)
+: option string :=
+
+ let _s510_ := _s509_ in
+ if ((string_startswith _s510_ "blt")) then
+ match (string_drop _s510_ (projT1 (string_length "blt"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s504_ (_s505_ : string)
+: option string :=
+
+ let _s506_ := _s505_ in
+ if ((string_startswith _s506_ "bne")) then
+ match (string_drop _s506_ (projT1 (string_length "bne"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s500_ (_s501_ : string)
+: option string :=
+
+ let _s502_ := _s501_ in
+ if ((string_startswith _s502_ "beq")) then
+ match (string_drop _s502_ (projT1 (string_length "beq"))) with | s_ => Some (s_) end
+ else None.
+
+Definition btype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((bop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s503_ := arg_ in
+ (if ((match (_s500_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s500_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BEQ, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s504_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s504_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BNE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s508_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s508_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BLT, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s512_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s512_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BGE, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s516_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s516_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BLTU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s520_ _s503_) with | Some (s_) => true | _ => false end)) then
+ (match (_s520_ _s503_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_BGEU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_iop_forwards (arg_ : iop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_ADDI => (vec_of_bits [B0;B0;B0] : mword 3)
+ | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : mword 3)
+ | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : mword 3)
+ | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : mword 3)
+ | RISCV_ORI => (vec_of_bits [B1;B1;B0] : mword 3)
+ | RISCV_XORI => (vec_of_bits [B1;B0;B0] : mword 3)
+ end.
+
+Definition encdec_iop_backwards (arg_ : mword 3)
+: M (iop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (RISCV_ADDI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm (RISCV_SLTI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm (RISCV_SLTIU : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then returnm (RISCV_ANDI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then returnm (RISCV_ORI : iop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then returnm (RISCV_XORI : iop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (iop).
+
+Definition encdec_iop_forwards_matches (arg_ : iop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDI => true
+ | RISCV_SLTI => true
+ | RISCV_SLTIU => true
+ | RISCV_ANDI => true
+ | RISCV_ORI => true
+ | RISCV_XORI => true
+ end.
+
+Definition encdec_iop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true
+ else false.
+
+Definition itype_mnemonic_forwards (arg_ : iop)
+: string :=
+
+ match arg_ with
+ | RISCV_ADDI => "addi"
+ | RISCV_SLTI => "slti"
+ | RISCV_SLTIU => "sltiu"
+ | RISCV_XORI => "xori"
+ | RISCV_ORI => "ori"
+ | RISCV_ANDI => "andi"
+ end.
+
+Definition itype_mnemonic_backwards (arg_ : string)
+: M (iop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "addi")) then returnm (RISCV_ADDI : iop)
+ else if ((generic_eq p0_ "slti")) then returnm (RISCV_SLTI : iop)
+ else if ((generic_eq p0_ "sltiu")) then returnm (RISCV_SLTIU : iop)
+ else if ((generic_eq p0_ "xori")) then returnm (RISCV_XORI : iop)
+ else if ((generic_eq p0_ "ori")) then returnm (RISCV_ORI : iop)
+ else if ((generic_eq p0_ "andi")) then returnm (RISCV_ANDI : iop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (iop).
+
+Definition itype_mnemonic_forwards_matches (arg_ : iop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDI => true
+ | RISCV_SLTI => true
+ | RISCV_SLTIU => true
+ | RISCV_XORI => true
+ | RISCV_ORI => true
+ | RISCV_ANDI => true
+ end.
+
+Definition itype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "addi")) then true
+ else if ((generic_eq p0_ "slti")) then true
+ else if ((generic_eq p0_ "sltiu")) then true
+ else if ((generic_eq p0_ "xori")) then true
+ else if ((generic_eq p0_ "ori")) then true
+ else if ((generic_eq p0_ "andi")) then true
+ else false.
+
+Definition _s544_ (_s545_ : string)
+: option string :=
+
+ let _s546_ := _s545_ in
+ if ((string_startswith _s546_ "andi")) then
+ match (string_drop _s546_ (projT1 (string_length "andi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s540_ (_s541_ : string)
+: option string :=
+
+ let _s542_ := _s541_ in
+ if ((string_startswith _s542_ "ori")) then
+ match (string_drop _s542_ (projT1 (string_length "ori"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s536_ (_s537_ : string)
+: option string :=
+
+ let _s538_ := _s537_ in
+ if ((string_startswith _s538_ "xori")) then
+ match (string_drop _s538_ (projT1 (string_length "xori"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s532_ (_s533_ : string)
+: option string :=
+
+ let _s534_ := _s533_ in
+ if ((string_startswith _s534_ "sltiu")) then
+ match (string_drop _s534_ (projT1 (string_length "sltiu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s528_ (_s529_ : string)
+: option string :=
+
+ let _s530_ := _s529_ in
+ if ((string_startswith _s530_ "slti")) then
+ match (string_drop _s530_ (projT1 (string_length "slti"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s524_ (_s525_ : string)
+: option string :=
+
+ let _s526_ := _s525_ in
+ if ((string_startswith _s526_ "addi")) then
+ match (string_drop _s526_ (projT1 (string_length "addi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition itype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((iop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s527_ := arg_ in
+ (if ((match (_s524_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s524_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADDI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s528_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s528_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s532_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s532_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTIU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s536_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s536_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_XORI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s540_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s540_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ORI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s544_ _s527_) with | Some (s_) => true | _ => false end)) then
+ (match (_s544_ _s527_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ANDI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((iop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((iop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((iop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_sop_forwards (arg_ : sop)
+: mword 3 :=
+
+ match arg_ with
+ | RISCV_SLLI => (vec_of_bits [B0;B0;B1] : mword 3)
+ | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : mword 3)
+ | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : mword 3)
+ end.
+
+Definition encdec_sop_backwards (arg_ : mword 3)
+: M (sop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (RISCV_SLLI : sop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_SRLI : sop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition encdec_sop_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition encdec_sop_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true
+ else false.
+
+Definition shiftiop_mnemonic_forwards (arg_ : sop)
+: string :=
+
+ match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end.
+
+Definition shiftiop_mnemonic_backwards (arg_ : string)
+: M (sop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slli")) then returnm (RISCV_SLLI : sop)
+ else if ((generic_eq p0_ "srli")) then returnm (RISCV_SRLI : sop)
+ else if ((generic_eq p0_ "srai")) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition shiftiop_mnemonic_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition shiftiop_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slli")) then true
+ else if ((generic_eq p0_ "srli")) then true
+ else if ((generic_eq p0_ "srai")) then true
+ else false.
+
+Definition _s556_ (_s557_ : string)
+: option string :=
+
+ let _s558_ := _s557_ in
+ if ((string_startswith _s558_ "srai")) then
+ match (string_drop _s558_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s552_ (_s553_ : string)
+: option string :=
+
+ let _s554_ := _s553_ in
+ if ((string_startswith _s554_ "srli")) then
+ match (string_drop _s554_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s548_ (_s549_ : string)
+: option string :=
+
+ let _s550_ := _s549_ in
+ if ((string_startswith _s550_ "slli")) then
+ match (string_drop _s550_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftiop_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s551_ := arg_ in
+ (if ((match (_s548_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s548_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s552_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s552_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s556_ _s551_) with | Some (s_) => true | _ => false end)) then
+ (match (_s556_ _s551_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition rtype_mnemonic_forwards (arg_ : rop)
+: string :=
+
+ match arg_ with
+ | RISCV_ADD => "add"
+ | RISCV_SLT => "slt"
+ | RISCV_SLTU => "sltu"
+ | RISCV_AND => "and"
+ | RISCV_OR => "or"
+ | RISCV_XOR => "xor"
+ | RISCV_SLL => "sll"
+ | RISCV_SRL => "srl"
+ | RISCV_SUB => "sub"
+ | RISCV_SRA => "sra"
+ end.
+
+Definition rtype_mnemonic_backwards (arg_ : string)
+: M (rop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "add")) then returnm (RISCV_ADD : rop)
+ else if ((generic_eq p0_ "slt")) then returnm (RISCV_SLT : rop)
+ else if ((generic_eq p0_ "sltu")) then returnm (RISCV_SLTU : rop)
+ else if ((generic_eq p0_ "and")) then returnm (RISCV_AND : rop)
+ else if ((generic_eq p0_ "or")) then returnm (RISCV_OR : rop)
+ else if ((generic_eq p0_ "xor")) then returnm (RISCV_XOR : rop)
+ else if ((generic_eq p0_ "sll")) then returnm (RISCV_SLL : rop)
+ else if ((generic_eq p0_ "srl")) then returnm (RISCV_SRL : rop)
+ else if ((generic_eq p0_ "sub")) then returnm (RISCV_SUB : rop)
+ else if ((generic_eq p0_ "sra")) then returnm (RISCV_SRA : rop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (rop).
+
+Definition rtype_mnemonic_forwards_matches (arg_ : rop)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADD => true
+ | RISCV_SLT => true
+ | RISCV_SLTU => true
+ | RISCV_AND => true
+ | RISCV_OR => true
+ | RISCV_XOR => true
+ | RISCV_SLL => true
+ | RISCV_SRL => true
+ | RISCV_SUB => true
+ | RISCV_SRA => true
+ end.
+
+Definition rtype_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "add")) then true
+ else if ((generic_eq p0_ "slt")) then true
+ else if ((generic_eq p0_ "sltu")) then true
+ else if ((generic_eq p0_ "and")) then true
+ else if ((generic_eq p0_ "or")) then true
+ else if ((generic_eq p0_ "xor")) then true
+ else if ((generic_eq p0_ "sll")) then true
+ else if ((generic_eq p0_ "srl")) then true
+ else if ((generic_eq p0_ "sub")) then true
+ else if ((generic_eq p0_ "sra")) then true
+ else false.
+
+Definition _s596_ (_s597_ : string)
+: option string :=
+
+ let _s598_ := _s597_ in
+ if ((string_startswith _s598_ "sra")) then
+ match (string_drop _s598_ (projT1 (string_length "sra"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s592_ (_s593_ : string)
+: option string :=
+
+ let _s594_ := _s593_ in
+ if ((string_startswith _s594_ "sub")) then
+ match (string_drop _s594_ (projT1 (string_length "sub"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s588_ (_s589_ : string)
+: option string :=
+
+ let _s590_ := _s589_ in
+ if ((string_startswith _s590_ "srl")) then
+ match (string_drop _s590_ (projT1 (string_length "srl"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s584_ (_s585_ : string)
+: option string :=
+
+ let _s586_ := _s585_ in
+ if ((string_startswith _s586_ "sll")) then
+ match (string_drop _s586_ (projT1 (string_length "sll"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s580_ (_s581_ : string)
+: option string :=
+
+ let _s582_ := _s581_ in
+ if ((string_startswith _s582_ "xor")) then
+ match (string_drop _s582_ (projT1 (string_length "xor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s576_ (_s577_ : string)
+: option string :=
+
+ let _s578_ := _s577_ in
+ if ((string_startswith _s578_ "or")) then
+ match (string_drop _s578_ (projT1 (string_length "or"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s572_ (_s573_ : string)
+: option string :=
+
+ let _s574_ := _s573_ in
+ if ((string_startswith _s574_ "and")) then
+ match (string_drop _s574_ (projT1 (string_length "and"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s568_ (_s569_ : string)
+: option string :=
+
+ let _s570_ := _s569_ in
+ if ((string_startswith _s570_ "sltu")) then
+ match (string_drop _s570_ (projT1 (string_length "sltu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s564_ (_s565_ : string)
+: option string :=
+
+ let _s566_ := _s565_ in
+ if ((string_startswith _s566_ "slt")) then
+ match (string_drop _s566_ (projT1 (string_length "slt"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s560_ (_s561_ : string)
+: option string :=
+
+ let _s562_ := _s561_ in
+ if ((string_startswith _s562_ "add")) then
+ match (string_drop _s562_ (projT1 (string_length "add"))) with | s_ => Some (s_) end
+ else None.
+
+Definition rtype_mnemonic_matches_prefix (arg_ : string)
+: M (option ((rop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s563_ := arg_ in
+ (if ((match (_s560_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s560_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s564_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s564_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLT, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s568_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s568_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLTU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s572_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s572_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_AND, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s576_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s576_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_OR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s580_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s580_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_XOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s584_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s584_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLL, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s588_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s588_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRL, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s592_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s592_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SUB, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s596_ _s563_) with | Some (s_) => true | _ => false end)) then
+ (match (_s596_ _s563_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRA, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((rop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((rop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((rop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition extend_value {n : Z} (is_unsigned : bool) (value : MemoryOpResult (mword (8 * n)))
+`{ArithFact (0 < n /\ n <= 8)}
+: MemoryOpResult (mword 64) :=
+
+ match value with
+ | MemValue (v) =>
+ MemValue (if sumbool_of_bool (is_unsigned) then EXTZ 64 v else (EXTS 64 v) : xlenbits)
+ | MemException (e) => MemException (e)
+ end.
+
+Definition process_load {n : Z}
+(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool)
+`{ArithFact (0 < n /\ n <= 8)}
+: M (Retired) :=
+
+ (match (extend_value is_unsigned value) with
+ | MemValue (result) =>
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ | MemException (e) => (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition check_misaligned (vaddr : mword 64) (width : word_width)
+: M (bool) :=
+
+ (if ((plat_enable_misaligned_access tt)) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else
+ (match width with
+ | BYTE =>
+ returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | HALF =>
+ (bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__0 : bool =>
+ returnm ((Bool.eqb w__0 true)
+ : bool)
+ | WORD =>
+ (or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__1 : bool =>
+ returnm ((Bool.eqb w__1 true)
+ : bool))
+ ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__2 : bool =>
+ returnm ((Bool.eqb w__2 true)
+ : bool)))
+ : M (bool)
+ | DOUBLE =>
+ (or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__4 : bool =>
+ returnm ((Bool.eqb w__4 true)
+ : bool))
+ ((or_boolM
+ ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__5 : bool =>
+ returnm ((Bool.eqb w__5 true)
+ : bool))
+ ((bit_to_bool (access_vec_dec vaddr 2)) >>= fun w__6 : bool =>
+ returnm ((Bool.eqb w__6 true)
+ : bool)))
+ : M (bool)))
+ : M (bool)
+ end)
+ : M (bool))
+ : M (bool).
+
+Definition maybe_aq_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => ".aq" | false => "" end.
+
+Definition maybe_aq_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ ".aq")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_aq_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_aq_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ ".aq")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s604_ (_s605_ : string)
+: option string :=
+
+ let _s606_ := _s605_ in
+ if ((string_startswith _s606_ "")) then
+ match (string_drop _s606_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s600_ (_s601_ : string)
+: option string :=
+
+ let _s602_ := _s601_ in
+ if ((string_startswith _s602_ ".aq")) then
+ match (string_drop _s602_ (projT1 (string_length ".aq"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_aq_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s603_ := arg_ in
+ (if ((match (_s600_ _s603_) with | Some (s_) => true | _ => false end)) then
+ (match (_s600_ _s603_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s604_ _s603_) with | Some (s_) => true | _ => false end)) then
+ (match (_s604_ _s603_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_rl_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => ".rl" | false => "" end.
+
+Definition maybe_rl_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ ".rl")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_rl_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_rl_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ ".rl")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s612_ (_s613_ : string)
+: option string :=
+
+ let _s614_ := _s613_ in
+ if ((string_startswith _s614_ "")) then
+ match (string_drop _s614_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s608_ (_s609_ : string)
+: option string :=
+
+ let _s610_ := _s609_ in
+ if ((string_startswith _s610_ ".rl")) then
+ match (string_drop _s610_ (projT1 (string_length ".rl"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_rl_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s611_ := arg_ in
+ (if ((match (_s608_ _s611_) with | Some (s_) => true | _ => false end)) then
+ (match (_s608_ _s611_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s612_ _s611_) with | Some (s_) => true | _ => false end)) then
+ (match (_s612_ _s611_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_u_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => "u" | false => "" end.
+
+Definition maybe_u_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "u")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_u_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_u_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "u")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s620_ (_s621_ : string)
+: option string :=
+
+ let _s622_ := _s621_ in
+ if ((string_startswith _s622_ "")) then
+ match (string_drop _s622_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s616_ (_s617_ : string)
+: option string :=
+
+ let _s618_ := _s617_ in
+ if ((string_startswith _s618_ "u")) then
+ match (string_drop _s618_ (projT1 (string_length "u"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_u_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s619_ := arg_ in
+ (if ((match (_s616_ _s619_) with | Some (s_) => true | _ => false end)) then
+ (match (_s616_ _s619_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s620_ _s619_) with | Some (s_) => true | _ => false end)) then
+ (match (_s620_ _s619_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition shiftw_mnemonic_forwards (arg_ : sop)
+: string :=
+
+ match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end.
+
+Definition shiftw_mnemonic_backwards (arg_ : string)
+: M (sop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slli")) then returnm (RISCV_SLLI : sop)
+ else if ((generic_eq p0_ "srli")) then returnm (RISCV_SRLI : sop)
+ else if ((generic_eq p0_ "srai")) then returnm (RISCV_SRAI : sop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sop).
+
+Definition shiftw_mnemonic_forwards_matches (arg_ : sop)
+: bool :=
+
+ match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end.
+
+Definition shiftw_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slli")) then true
+ else if ((generic_eq p0_ "srli")) then true
+ else if ((generic_eq p0_ "srai")) then true
+ else false.
+
+Definition _s632_ (_s633_ : string)
+: option string :=
+
+ let _s634_ := _s633_ in
+ if ((string_startswith _s634_ "srai")) then
+ match (string_drop _s634_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s628_ (_s629_ : string)
+: option string :=
+
+ let _s630_ := _s629_ in
+ if ((string_startswith _s630_ "srli")) then
+ match (string_drop _s630_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s624_ (_s625_ : string)
+: option string :=
+
+ let _s626_ := _s625_ in
+ if ((string_startswith _s626_ "slli")) then
+ match (string_drop _s626_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftw_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s627_ := arg_ in
+ (if ((match (_s624_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s624_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s628_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s628_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s632_ _s627_) with | Some (s_) => true | _ => false end)) then
+ (match (_s632_ _s627_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAI, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition rtypew_mnemonic_forwards (arg_ : ropw)
+: string :=
+
+ match arg_ with
+ | RISCV_ADDW => "addw"
+ | RISCV_SUBW => "subw"
+ | RISCV_SLLW => "sllw"
+ | RISCV_SRLW => "srlw"
+ | RISCV_SRAW => "sraw"
+ end.
+
+Definition rtypew_mnemonic_backwards (arg_ : string)
+: M (ropw) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "addw")) then returnm (RISCV_ADDW : ropw)
+ else if ((generic_eq p0_ "subw")) then returnm (RISCV_SUBW : ropw)
+ else if ((generic_eq p0_ "sllw")) then returnm (RISCV_SLLW : ropw)
+ else if ((generic_eq p0_ "srlw")) then returnm (RISCV_SRLW : ropw)
+ else if ((generic_eq p0_ "sraw")) then returnm (RISCV_SRAW : ropw)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (ropw).
+
+Definition rtypew_mnemonic_forwards_matches (arg_ : ropw)
+: bool :=
+
+ match arg_ with
+ | RISCV_ADDW => true
+ | RISCV_SUBW => true
+ | RISCV_SLLW => true
+ | RISCV_SRLW => true
+ | RISCV_SRAW => true
+ end.
+
+Definition rtypew_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "addw")) then true
+ else if ((generic_eq p0_ "subw")) then true
+ else if ((generic_eq p0_ "sllw")) then true
+ else if ((generic_eq p0_ "srlw")) then true
+ else if ((generic_eq p0_ "sraw")) then true
+ else false.
+
+Definition _s652_ (_s653_ : string)
+: option string :=
+
+ let _s654_ := _s653_ in
+ if ((string_startswith _s654_ "sraw")) then
+ match (string_drop _s654_ (projT1 (string_length "sraw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s648_ (_s649_ : string)
+: option string :=
+
+ let _s650_ := _s649_ in
+ if ((string_startswith _s650_ "srlw")) then
+ match (string_drop _s650_ (projT1 (string_length "srlw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s644_ (_s645_ : string)
+: option string :=
+
+ let _s646_ := _s645_ in
+ if ((string_startswith _s646_ "sllw")) then
+ match (string_drop _s646_ (projT1 (string_length "sllw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s640_ (_s641_ : string)
+: option string :=
+
+ let _s642_ := _s641_ in
+ if ((string_startswith _s642_ "subw")) then
+ match (string_drop _s642_ (projT1 (string_length "subw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s636_ (_s637_ : string)
+: option string :=
+
+ let _s638_ := _s637_ in
+ if ((string_startswith _s638_ "addw")) then
+ match (string_drop _s638_ (projT1 (string_length "addw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition rtypew_mnemonic_matches_prefix (arg_ : string)
+: M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s639_ := arg_ in
+ (if ((match (_s636_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s636_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_ADDW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s640_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s640_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SUBW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s644_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s644_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s648_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s648_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s652_ _s639_) with | Some (s_) => true | _ => false end)) then
+ (match (_s652_ _s639_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((ropw * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))).
+
+Definition shiftiwop_mnemonic_forwards (arg_ : sopw)
+: string :=
+
+ match arg_ with | RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" end.
+
+Definition shiftiwop_mnemonic_backwards (arg_ : string)
+: M (sopw) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "slliw")) then returnm (RISCV_SLLIW : sopw)
+ else if ((generic_eq p0_ "srliw")) then returnm (RISCV_SRLIW : sopw)
+ else if ((generic_eq p0_ "sraiw")) then returnm (RISCV_SRAIW : sopw)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (sopw).
+
+Definition shiftiwop_mnemonic_forwards_matches (arg_ : sopw)
+: bool :=
+
+ match arg_ with | RISCV_SLLIW => true | RISCV_SRLIW => true | RISCV_SRAIW => true end.
+
+Definition shiftiwop_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "slliw")) then true
+ else if ((generic_eq p0_ "srliw")) then true
+ else if ((generic_eq p0_ "sraiw")) then true
+ else false.
+
+Definition _s664_ (_s665_ : string)
+: option string :=
+
+ let _s666_ := _s665_ in
+ if ((string_startswith _s666_ "sraiw")) then
+ match (string_drop _s666_ (projT1 (string_length "sraiw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s660_ (_s661_ : string)
+: option string :=
+
+ let _s662_ := _s661_ in
+ if ((string_startswith _s662_ "srliw")) then
+ match (string_drop _s662_ (projT1 (string_length "srliw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s656_ (_s657_ : string)
+: option string :=
+
+ let _s658_ := _s657_ in
+ if ((string_startswith _s658_ "slliw")) then
+ match (string_drop _s658_ (projT1 (string_length "slliw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition shiftiwop_mnemonic_matches_prefix (arg_ : string)
+: M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s659_ := arg_ in
+ (if ((match (_s656_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s656_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SLLIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s660_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s660_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRLIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s664_ _s659_) with | Some (s_) => true | _ => false end)) then
+ (match (_s664_ _s659_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((RISCV_SRAIW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((sopw * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_r_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("r" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_r_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "r")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_r_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_r_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "r")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s672_ (_s673_ : string)
+: option string :=
+
+ let _s674_ := _s673_ in
+ if ((string_startswith _s674_ "")) then
+ match (string_drop _s674_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s668_ (_s669_ : string)
+: option string :=
+
+ let _s670_ := _s669_ in
+ if ((string_startswith _s670_ "r")) then
+ match (string_drop _s670_ (projT1 (string_length "r"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_r_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s671_ := arg_ in
+ (if ((match (_s668_ _s671_) with | Some (s_) => true | _ => false end)) then
+ (match (_s668_ _s671_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s672_ _s671_) with | Some (s_) => true | _ => false end)) then
+ (match (_s672_ _s671_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_w_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("w" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_w_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "w")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_w_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_w_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "w")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s680_ (_s681_ : string)
+: option string :=
+
+ let _s682_ := _s681_ in
+ if ((string_startswith _s682_ "")) then
+ match (string_drop _s682_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s676_ (_s677_ : string)
+: option string :=
+
+ let _s678_ := _s677_ in
+ if ((string_startswith _s678_ "w")) then
+ match (string_drop _s678_ (projT1 (string_length "w"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_w_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s679_ := arg_ in
+ (if ((match (_s676_ _s679_) with | Some (s_) => true | _ => false end)) then
+ (match (_s676_ _s679_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s680_ _s679_) with | Some (s_) => true | _ => false end)) then
+ (match (_s680_ _s679_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_i_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("i" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_i_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "i")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_i_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_i_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "i")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s688_ (_s689_ : string)
+: option string :=
+
+ let _s690_ := _s689_ in
+ if ((string_startswith _s690_ "")) then
+ match (string_drop _s690_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s684_ (_s685_ : string)
+: option string :=
+
+ let _s686_ := _s685_ in
+ if ((string_startswith _s686_ "i")) then
+ match (string_drop _s686_ (projT1 (string_length "i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_i_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s687_ := arg_ in
+ (if ((match (_s684_ _s687_) with | Some (s_) => true | _ => false end)) then
+ (match (_s684_ _s687_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s688_ _s687_) with | Some (s_) => true | _ => false end)) then
+ (match (_s688_ _s687_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition bit_maybe_o_forwards (arg_ : mword 1)
+: M (string) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then returnm ("o" : string)
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then returnm ("" : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string).
+
+Definition bit_maybe_o_backwards (arg_ : string)
+: M (mword 1) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "o")) then returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ else if ((generic_eq p0_ "")) then returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 1).
+
+Definition bit_maybe_o_forwards_matches (arg_ : mword 1)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true
+ else false.
+
+Definition bit_maybe_o_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "o")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s696_ (_s697_ : string)
+: option string :=
+
+ let _s698_ := _s697_ in
+ if ((string_startswith _s698_ "")) then
+ match (string_drop _s698_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s692_ (_s693_ : string)
+: option string :=
+
+ let _s694_ := _s693_ in
+ if ((string_startswith _s694_ "o")) then
+ match (string_drop _s694_ (projT1 (string_length "o"))) with | s_ => Some (s_) end
+ else None.
+
+Definition bit_maybe_o_matches_prefix (arg_ : string)
+: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s695_ := arg_ in
+ (if ((match (_s692_ _s695_) with | Some (s_) => true | _ => false end)) then
+ (match (_s692_ _s695_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B1] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s696_ _s695_) with | Some (s_) => true | _ => false end)) then
+ (match (_s696_ _s695_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((vec_of_bits [B0] : mword 1), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition fence_bits_forwards (arg_ : mword 4)
+: M (string) :=
+
+ (match arg_ with
+ | v__0 =>
+ let i : bits 1 := subrange_vec_dec v__0 3 3 in
+ let w : bits 1 := subrange_vec_dec v__0 0 0 in
+ let r : bits 1 := subrange_vec_dec v__0 1 1 in
+ let o : bits 1 := subrange_vec_dec v__0 2 2 in
+ let i : bits 1 := subrange_vec_dec v__0 3 3 in
+ (bit_maybe_i_forwards i) >>= fun w__0 : string =>
+ (bit_maybe_o_forwards o) >>= fun w__1 : string =>
+ (bit_maybe_r_forwards r) >>= fun w__2 : string =>
+ (bit_maybe_w_forwards w) >>= fun w__3 : string =>
+ returnm ((string_append w__0
+ (string_append w__1 (string_append w__2 (string_append w__3 ""))))
+ : string)
+ end)
+ : M (string).
+
+Definition _s700_ (_s701_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) :=
+
+ (match _s701_ with
+ | _s702_ =>
+ (bit_maybe_i_matches_prefix _s702_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s703_ _)) =>
+ (match (string_drop _s702_ _s703_) with
+ | _s704_ =>
+ (bit_maybe_o_matches_prefix _s704_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s705_ _)) =>
+ (match (string_drop _s704_ _s705_) with
+ | _s706_ =>
+ (bit_maybe_r_matches_prefix _s706_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s707_ _)) =>
+ (match (string_drop _s706_ _s707_) with
+ | _s708_ =>
+ (bit_maybe_w_matches_prefix _s708_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s709_ _)) =>
+ let p0_ := string_drop _s708_ _s709_ in
+ if ((generic_eq p0_ "")) then Some ((i, o, r, w))
+ else None
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1))).
+
+Definition fence_bits_backwards (arg_ : string)
+: M (mword 4) :=
+
+ let _s710_ := arg_ in
+ (_s700_ _s710_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (if ((match w__0 with | Some ((i, o, r, w)) => true | _ => false end)) then
+ (_s700_ _s710_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (match w__1 with
+ | Some ((i, o, r, w)) =>
+ returnm ((concat_vec (i : bits 1)
+ (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))))
+ : mword (1 + (1 + (1 + 1))))
+ | _ => exit tt : M (mword 4)
+ end)
+ : M (mword 4)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 4).
+
+Definition fence_bits_forwards_matches (arg_ : mword 4)
+: bool :=
+
+ match arg_ with | v__1 => true end.
+
+Definition _s711_ (_s712_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) :=
+
+ (match _s712_ with
+ | _s713_ =>
+ (bit_maybe_i_matches_prefix _s713_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s714_ _)) =>
+ (match (string_drop _s713_ _s714_) with
+ | _s715_ =>
+ (bit_maybe_o_matches_prefix _s715_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s716_ _)) =>
+ (match (string_drop _s715_ _s716_) with
+ | _s717_ =>
+ (bit_maybe_r_matches_prefix _s717_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s718_ _)) =>
+ (match (string_drop _s717_ _s718_) with
+ | _s719_ =>
+ (bit_maybe_w_matches_prefix _s719_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s720_ _)) =>
+ let p0_ := string_drop _s719_ _s720_ in
+ if ((generic_eq p0_ "")) then Some ((i, o, r, w))
+ else None
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1))).
+
+Definition fence_bits_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s721_ := arg_ in
+ (_s711_ _s721_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (if ((match w__0 with | Some ((i, o, r, w)) => true | _ => false end)) then
+ (_s711_ _s721_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) =>
+ (match w__1 with
+ | Some ((i, o, r, w)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool).
+
+Definition _s722_ (_s723_ : string)
+: M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) :=
+
+ (match _s723_ with
+ | _s724_ =>
+ (bit_maybe_i_matches_prefix _s724_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((i, existT _ _s725_ _)) =>
+ (match (string_drop _s724_ _s725_) with
+ | _s726_ =>
+ (bit_maybe_o_matches_prefix _s726_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((o, existT _ _s727_ _)) =>
+ (match (string_drop _s726_ _s727_) with
+ | _s728_ =>
+ (bit_maybe_r_matches_prefix _s728_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((r, existT _ _s729_ _)) =>
+ (match (string_drop _s728_ _s729_) with
+ | _s730_ =>
+ (bit_maybe_w_matches_prefix _s730_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((w, existT _ _s731_ _)) =>
+ match (string_drop _s730_ _s731_) with
+ | s_ => Some ((i, o, r, w, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string)))
+ end)
+ : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))).
+
+Definition fence_bits_matches_prefix (arg_ : string)
+: M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s732_ := arg_ in
+ (_s722_ _s732_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) =>
+ (if ((match w__0 with | Some ((i, o, r, w, s_)) => true | _ => false end)) then
+ (_s722_ _s732_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) =>
+ (match w__1 with
+ | Some ((i, o, r, w, s_)) =>
+ returnm ((Some
+ ((concat_vec (i : bits 1)
+ (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((mword 4 * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))).
+
+Definition aqrl_str (aq : bool) (rl : bool)
+: string :=
+
+ match (aq, rl) with
+ | (false, false) => ""
+ | (false, true) => ".rl"
+ | (true, false) => ".aq"
+ | (true, true) => ".aqrl"
+ end.
+
+Definition lrsc_width_str (width : word_width)
+: string :=
+
+ match width with | BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" end.
+
+Definition process_loadres {n : Z}
+(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool)
+`{ArithFact (0 < n /\ n <= 8)}
+: M (Retired) :=
+
+ (match (extend_value is_unsigned value) with
+ | MemValue (result) =>
+ let '_ := (load_reservation addr) : unit in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ | MemException (e) => (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition encdec_amoop_forwards (arg_ : amoop)
+: mword 5 :=
+
+ match arg_ with
+ | AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)
+ | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)
+ | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)
+ | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)
+ | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)
+ | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)
+ | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : mword 5)
+ | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : mword 5)
+ end.
+
+Definition encdec_amoop_backwards (arg_ : mword 5)
+: M (amoop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm (AMOSWAP : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (AMOADD : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then returnm (AMOXOR : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then returnm (AMOAND : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then returnm (AMOOR : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then returnm (AMOMIN : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then returnm (AMOMAX : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then
+ returnm (AMOMINU
+ : amoop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then
+ returnm (AMOMAXU
+ : amoop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (amoop).
+
+Definition encdec_amoop_forwards_matches (arg_ : amoop)
+: bool :=
+
+ match arg_ with
+ | AMOSWAP => true
+ | AMOADD => true
+ | AMOXOR => true
+ | AMOAND => true
+ | AMOOR => true
+ | AMOMIN => true
+ | AMOMAX => true
+ | AMOMINU => true
+ | AMOMAXU => true
+ end.
+
+Definition encdec_amoop_backwards_matches (arg_ : mword 5)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))) then true
+ else false.
+
+Definition amo_mnemonic_forwards (arg_ : amoop)
+: string :=
+
+ match arg_ with
+ | AMOSWAP => "amoswap"
+ | AMOADD => "amoadd"
+ | AMOXOR => "amoxor"
+ | AMOAND => "amoand"
+ | AMOOR => "amoor"
+ | AMOMIN => "amomin"
+ | AMOMAX => "amomax"
+ | AMOMINU => "amominu"
+ | AMOMAXU => "amomaxu"
+ end.
+
+Definition amo_mnemonic_backwards (arg_ : string)
+: M (amoop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "amoswap")) then returnm (AMOSWAP : amoop)
+ else if ((generic_eq p0_ "amoadd")) then returnm (AMOADD : amoop)
+ else if ((generic_eq p0_ "amoxor")) then returnm (AMOXOR : amoop)
+ else if ((generic_eq p0_ "amoand")) then returnm (AMOAND : amoop)
+ else if ((generic_eq p0_ "amoor")) then returnm (AMOOR : amoop)
+ else if ((generic_eq p0_ "amomin")) then returnm (AMOMIN : amoop)
+ else if ((generic_eq p0_ "amomax")) then returnm (AMOMAX : amoop)
+ else if ((generic_eq p0_ "amominu")) then returnm (AMOMINU : amoop)
+ else if ((generic_eq p0_ "amomaxu")) then returnm (AMOMAXU : amoop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (amoop).
+
+Definition amo_mnemonic_forwards_matches (arg_ : amoop)
+: bool :=
+
+ match arg_ with
+ | AMOSWAP => true
+ | AMOADD => true
+ | AMOXOR => true
+ | AMOAND => true
+ | AMOOR => true
+ | AMOMIN => true
+ | AMOMAX => true
+ | AMOMINU => true
+ | AMOMAXU => true
+ end.
+
+Definition amo_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "amoswap")) then true
+ else if ((generic_eq p0_ "amoadd")) then true
+ else if ((generic_eq p0_ "amoxor")) then true
+ else if ((generic_eq p0_ "amoand")) then true
+ else if ((generic_eq p0_ "amoor")) then true
+ else if ((generic_eq p0_ "amomin")) then true
+ else if ((generic_eq p0_ "amomax")) then true
+ else if ((generic_eq p0_ "amominu")) then true
+ else if ((generic_eq p0_ "amomaxu")) then true
+ else false.
+
+Definition _s765_ (_s766_ : string)
+: option string :=
+
+ let _s767_ := _s766_ in
+ if ((string_startswith _s767_ "amomaxu")) then
+ match (string_drop _s767_ (projT1 (string_length "amomaxu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s761_ (_s762_ : string)
+: option string :=
+
+ let _s763_ := _s762_ in
+ if ((string_startswith _s763_ "amominu")) then
+ match (string_drop _s763_ (projT1 (string_length "amominu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s757_ (_s758_ : string)
+: option string :=
+
+ let _s759_ := _s758_ in
+ if ((string_startswith _s759_ "amomax")) then
+ match (string_drop _s759_ (projT1 (string_length "amomax"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s753_ (_s754_ : string)
+: option string :=
+
+ let _s755_ := _s754_ in
+ if ((string_startswith _s755_ "amomin")) then
+ match (string_drop _s755_ (projT1 (string_length "amomin"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s749_ (_s750_ : string)
+: option string :=
+
+ let _s751_ := _s750_ in
+ if ((string_startswith _s751_ "amoor")) then
+ match (string_drop _s751_ (projT1 (string_length "amoor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s745_ (_s746_ : string)
+: option string :=
+
+ let _s747_ := _s746_ in
+ if ((string_startswith _s747_ "amoand")) then
+ match (string_drop _s747_ (projT1 (string_length "amoand"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s741_ (_s742_ : string)
+: option string :=
+
+ let _s743_ := _s742_ in
+ if ((string_startswith _s743_ "amoxor")) then
+ match (string_drop _s743_ (projT1 (string_length "amoxor"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s737_ (_s738_ : string)
+: option string :=
+
+ let _s739_ := _s738_ in
+ if ((string_startswith _s739_ "amoadd")) then
+ match (string_drop _s739_ (projT1 (string_length "amoadd"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s733_ (_s734_ : string)
+: option string :=
+
+ let _s735_ := _s734_ in
+ if ((string_startswith _s735_ "amoswap")) then
+ match (string_drop _s735_ (projT1 (string_length "amoswap"))) with | s_ => Some (s_) end
+ else None.
+
+Definition amo_mnemonic_matches_prefix (arg_ : string)
+: M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s736_ := arg_ in
+ (if ((match (_s733_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s733_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOSWAP, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s737_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s737_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOADD, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s741_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s741_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOXOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s745_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s745_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOAND, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s749_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s749_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOOR, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s753_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s753_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMIN, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s757_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s757_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMAX, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s761_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s761_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMINU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s765_ _s736_) with | Some (s_) => true | _ => false end)) then
+ (match (_s765_ _s736_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((AMOMAXU, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((amoop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_mul_op_forwards (arg_ : (bool * bool * bool))
+: M (mword 3) :=
+
+ (match arg_ with
+ | (false, true, true) => returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3)
+ | (true, true, true) => returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3)
+ | (true, true, false) => returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3)
+ | (true, false, false) => returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3)
+ | _ => exit tt : M (mword 3)
+ end)
+ : M (mword 3).
+
+Definition encdec_mul_op_backwards (arg_ : mword 3)
+: M ((bool * bool * bool)) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then returnm (false, true, true)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then returnm (true, true, true)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then returnm (true, true, false)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then returnm (true, false, false)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M ((bool * bool * bool)).
+
+Definition encdec_mul_op_forwards_matches (arg_ : (bool * bool * bool))
+: bool :=
+
+ match arg_ with
+ | (false, true, true) => true
+ | (true, true, true) => true
+ | (true, true, false) => true
+ | (true, false, false) => true
+ | _ => false
+ end.
+
+Definition encdec_mul_op_backwards_matches (arg_ : mword 3)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true
+ else false.
+
+Definition mul_mnemonic_forwards (arg_ : (bool * bool * bool))
+: M (string) :=
+
+ (match arg_ with
+ | (false, true, true) => returnm ("mul" : string)
+ | (true, true, true) => returnm ("mulh" : string)
+ | (true, true, false) => returnm ("mulhsu" : string)
+ | (true, false, false) => returnm ("mulhu" : string)
+ | _ => exit tt : M (string)
+ end)
+ : M (string).
+
+Definition mul_mnemonic_backwards (arg_ : string)
+: M ((bool * bool * bool)) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "mul")) then returnm (false, true, true)
+ else if ((generic_eq p0_ "mulh")) then returnm (true, true, true)
+ else if ((generic_eq p0_ "mulhsu")) then returnm (true, true, false)
+ else if ((generic_eq p0_ "mulhu")) then returnm (true, false, false)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M ((bool * bool * bool)).
+
+Definition mul_mnemonic_forwards_matches (arg_ : (bool * bool * bool))
+: bool :=
+
+ match arg_ with
+ | (false, true, true) => true
+ | (true, true, true) => true
+ | (true, true, false) => true
+ | (true, false, false) => true
+ | _ => false
+ end.
+
+Definition mul_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "mul")) then true
+ else if ((generic_eq p0_ "mulh")) then true
+ else if ((generic_eq p0_ "mulhsu")) then true
+ else if ((generic_eq p0_ "mulhu")) then true
+ else false.
+
+Definition _s781_ (_s782_ : string)
+: option string :=
+
+ let _s783_ := _s782_ in
+ if ((string_startswith _s783_ "mulhu")) then
+ match (string_drop _s783_ (projT1 (string_length "mulhu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s777_ (_s778_ : string)
+: option string :=
+
+ let _s779_ := _s778_ in
+ if ((string_startswith _s779_ "mulhsu")) then
+ match (string_drop _s779_ (projT1 (string_length "mulhsu"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s773_ (_s774_ : string)
+: option string :=
+
+ let _s775_ := _s774_ in
+ if ((string_startswith _s775_ "mulh")) then
+ match (string_drop _s775_ (projT1 (string_length "mulh"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s769_ (_s770_ : string)
+: option string :=
+
+ let _s771_ := _s770_ in
+ if ((string_startswith _s771_ "mul")) then
+ match (string_drop _s771_ (projT1 (string_length "mul"))) with | s_ => Some (s_) end
+ else None.
+
+Definition mul_mnemonic_matches_prefix (arg_ : string)
+: M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s772_ := arg_ in
+ (if ((match (_s769_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s769_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((false, true, true), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s773_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s773_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, true, true), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s777_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s777_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, true, false), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s781_ _s772_) with | Some (s_) => true | _ => false end)) then
+ (match (_s781_ _s772_) with
+ | Some (s_) =>
+ returnm ((Some
+ (((true, false, false), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))))
+ : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))).
+
+Definition maybe_not_u_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | false => "u" | true => "" end.
+
+Definition maybe_not_u_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "u")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_not_u_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | false => true | true => true end.
+
+Definition maybe_not_u_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "u")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s789_ (_s790_ : string)
+: option string :=
+
+ let _s791_ := _s790_ in
+ if ((string_startswith _s791_ "")) then
+ match (string_drop _s791_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s785_ (_s786_ : string)
+: option string :=
+
+ let _s787_ := _s786_ in
+ if ((string_startswith _s787_ "u")) then
+ match (string_drop _s787_ (projT1 (string_length "u"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_not_u_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s788_ := arg_ in
+ (if ((match (_s785_ _s788_) with | Some (s_) => true | _ => false end)) then
+ (match (_s785_ _s788_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s789_ _s788_) with | Some (s_) => true | _ => false end)) then
+ (match (_s789_ _s788_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_csrop_forwards (arg_ : csrop)
+: mword 2 :=
+
+ match arg_ with
+ | CSRRW => (vec_of_bits [B0;B1] : mword 2)
+ | CSRRS => (vec_of_bits [B1;B0] : mword 2)
+ | CSRRC => (vec_of_bits [B1;B1] : mword 2)
+ end.
+
+Definition encdec_csrop_backwards (arg_ : mword 2)
+: M (csrop) :=
+
+ let b__0 := arg_ in
+ (if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then returnm (CSRRW : csrop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then returnm (CSRRS : csrop)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then returnm (CSRRC : csrop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (csrop).
+
+Definition encdec_csrop_forwards_matches (arg_ : csrop)
+: bool :=
+
+ match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end.
+
+Definition encdec_csrop_backwards_matches (arg_ : mword 2)
+: bool :=
+
+ let b__0 := arg_ in
+ if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true
+ else false.
+
+Definition readCSR (csr : mword 12)
+: M (mword 64) :=
+
+ (match (csr, 64) with
+ | (b__0, g__222) =>
+ (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg mvendorid_ref) : M (mword 32)) >>= fun w__0 : mword 32 =>
+ returnm ((EXTZ 64 w__0)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg marchid_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg mimpid_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then
+ ((read_reg mhartid_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ returnm ((_get_Mstatus_bits w__4)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg misa_ref >>= fun w__5 : Misa => returnm ((_get_Misa_bits w__5) : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg medeleg_ref >>= fun w__6 : Medeleg =>
+ returnm ((_get_Medeleg_bits w__6)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg mideleg_ref >>= fun w__7 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__7)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__8 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__8)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_mtvec tt)
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__10 : Counteren =>
+ returnm ((EXTZ 64 (_get_Counteren_bits w__10))
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mscratch_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target Machine) >>= fun w__12 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__13 : mword 64 =>
+ returnm ((and_vec w__12 w__13)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg mcause_ref >>= fun w__14 : Mcause =>
+ returnm ((_get_Mcause_bits w__14)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg mtval_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__16 : Minterrupts =>
+ returnm ((_get_Minterrupts_bits w__16)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ (pmpReadCfgReg 0)
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ (pmpReadCfgReg 2)
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr0_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr1_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr2_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr3_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr4_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr5_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr6_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr7_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr8_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr9_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr10_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr11_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ ((read_reg pmpaddr12_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ ((read_reg pmpaddr13_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ ((read_reg pmpaddr14_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ ((read_reg pmpaddr15_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__35 : mword 64 =>
+ returnm ((subrange_vec_dec w__35 (Z.sub 64 1) 0)
+ : mword (63 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__36 : mword 64 =>
+ returnm ((subrange_vec_dec w__36 (Z.sub 64 1) 0)
+ : mword (63 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg tselect_ref) : M (mword 64)) >>= fun w__37 : mword 64 =>
+ returnm ((not_vec w__37)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__38 : Mstatus =>
+ returnm ((_get_Sstatus_bits (lower_mstatus w__38))
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg sedeleg_ref >>= fun w__39 : Sedeleg =>
+ returnm ((_get_Sedeleg_bits w__39)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg sideleg_ref >>= fun w__40 : Sinterrupts =>
+ returnm ((_get_Sinterrupts_bits w__40)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__41 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__42 : Minterrupts =>
+ returnm ((_get_Sinterrupts_bits (lower_mie w__41 w__42))
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (get_stvec tt)
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg scounteren_ref >>= fun w__44 : Counteren =>
+ returnm ((EXTZ 64 (_get_Counteren_bits w__44))
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg sscratch_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (get_xret_target Supervisor) >>= fun w__46 : mword 64 =>
+ (pc_alignment_mask tt) >>= fun w__47 : mword 64 =>
+ returnm ((and_vec w__46 w__47)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg scause_ref >>= fun w__48 : Mcause =>
+ returnm ((_get_Mcause_bits w__48)
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ ((read_reg stval_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__50 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__51 : Minterrupts =>
+ returnm ((_get_Sinterrupts_bits (lower_mip w__50 w__51))
+ : mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg satp_ref) : M (mword 64))
+ : M (mword 64)
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__53 : mword 64 =>
+ returnm ((subrange_vec_dec w__53 (Z.sub 64 1) 0)
+ : mword (63 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ ((read_reg mtime_ref) : M (mword 64)) >>= fun w__54 : mword 64 =>
+ returnm ((subrange_vec_dec w__54 (Z.sub 64 1) 0)
+ : mword (63 - 0 + 1))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__55 : mword 64 =>
+ returnm ((subrange_vec_dec w__55 (Z.sub 64 1) 0)
+ : mword (63 - 0 + 1))
+ else
+ (ext_read_CSR csr) >>= fun w__56 : option (mword 64) =>
+ returnm ((match w__56 with
+ | Some (res) => res
+ | None =>
+ let '_ := (print_bits "unhandled read to CSR " csr) : unit in
+ EXTZ 64 (vec_of_bits [B0;B0;B0;B0] : mword 4)
+ end)
+ : mword 64))
+ : M (mword 64)
+ end) >>= fun res : xlenbits =>
+ let '_ :=
+ (if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr) (String.append " -> " (string_of_bits res))))
+ else tt)
+ : unit in
+ returnm (res
+ : mword 64).
+
+Definition writeCSR (csr : mword 12) (value : mword 64)
+: M (unit) :=
+
+ (match (csr, 64) with
+ | (b__0, g__221) =>
+ (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__0 : Mstatus =>
+ (legalize_mstatus w__0 value) >>= fun w__1 : Mstatus =>
+ write_reg mstatus_ref w__1 >>
+ read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__2))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ read_reg misa_ref >>= fun w__3 : Misa =>
+ (legalize_misa w__3 value) >>= fun w__4 : Misa =>
+ write_reg misa_ref w__4 >>
+ read_reg misa_ref >>= fun w__5 : Misa =>
+ returnm ((Some
+ (_get_Misa_bits w__5))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg medeleg_ref >>= fun w__6 : Medeleg =>
+ write_reg medeleg_ref (legalize_medeleg w__6 value) >>
+ read_reg medeleg_ref >>= fun w__7 : Medeleg =>
+ returnm ((Some
+ (_get_Medeleg_bits w__7))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ read_reg mideleg_ref >>= fun w__8 : Minterrupts =>
+ write_reg mideleg_ref (legalize_mideleg w__8 value) >>
+ read_reg mideleg_ref >>= fun w__9 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__9))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__10 : Minterrupts =>
+ (legalize_mie w__10 value) >>= fun w__11 : Minterrupts =>
+ write_reg mie_ref w__11 >>
+ read_reg mie_ref >>= fun w__12 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__12))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_mtvec value) >>= fun w__13 : mword 64 =>
+ returnm ((Some
+ (w__13))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg mcounteren_ref >>= fun w__14 : Counteren =>
+ (legalize_mcounteren w__14 value) >>= fun w__15 : Counteren =>
+ write_reg mcounteren_ref w__15 >>
+ read_reg mcounteren_ref >>= fun w__16 : Counteren =>
+ returnm ((Some
+ (EXTZ 64 (_get_Counteren_bits w__16)))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg mscratch_ref value >>
+ ((read_reg mscratch_ref) : M (mword 64)) >>= fun w__17 : mword 64 =>
+ returnm ((Some
+ (w__17))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target Machine value) >>= fun w__18 : mword 64 =>
+ returnm ((Some
+ (w__18))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits mcause_ref value) >>
+ read_reg mcause_ref >>= fun w__19 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__19))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg mtval_ref value >>
+ ((read_reg mtval_ref) : M (mword 64)) >>= fun w__20 : mword 64 =>
+ returnm ((Some
+ (w__20))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__21 : Minterrupts =>
+ (legalize_mip w__21 value) >>= fun w__22 : Minterrupts =>
+ write_reg mip_ref w__22 >>
+ read_reg mip_ref >>= fun w__23 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__23))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ (pmpWriteCfgReg 0 value) >> returnm ((Some (value)) : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then
+ (pmpWriteCfgReg 2 value) >> returnm ((Some (value)) : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then
+ read_reg pmp0cfg_ref >>= fun w__24 : Pmpcfg_ent =>
+ ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__25 : mword 64 =>
+ write_reg pmpaddr0_ref (pmpWriteAddr w__24 w__25 value) >>
+ ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__26 : mword 64 =>
+ returnm ((Some
+ (w__26))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then
+ read_reg pmp1cfg_ref >>= fun w__27 : Pmpcfg_ent =>
+ ((read_reg pmpaddr1_ref) : M (mword 64)) >>= fun w__28 : mword 64 =>
+ write_reg pmpaddr1_ref (pmpWriteAddr w__27 w__28 value) >>
+ ((read_reg pmpaddr1_ref) : M (mword 64)) >>= fun w__29 : mword 64 =>
+ returnm ((Some
+ (w__29))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then
+ read_reg pmp2cfg_ref >>= fun w__30 : Pmpcfg_ent =>
+ ((read_reg pmpaddr2_ref) : M (mword 64)) >>= fun w__31 : mword 64 =>
+ write_reg pmpaddr2_ref (pmpWriteAddr w__30 w__31 value) >>
+ ((read_reg pmpaddr2_ref) : M (mword 64)) >>= fun w__32 : mword 64 =>
+ returnm ((Some
+ (w__32))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then
+ read_reg pmp3cfg_ref >>= fun w__33 : Pmpcfg_ent =>
+ ((read_reg pmpaddr3_ref) : M (mword 64)) >>= fun w__34 : mword 64 =>
+ write_reg pmpaddr3_ref (pmpWriteAddr w__33 w__34 value) >>
+ ((read_reg pmpaddr3_ref) : M (mword 64)) >>= fun w__35 : mword 64 =>
+ returnm ((Some
+ (w__35))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then
+ read_reg pmp4cfg_ref >>= fun w__36 : Pmpcfg_ent =>
+ ((read_reg pmpaddr4_ref) : M (mword 64)) >>= fun w__37 : mword 64 =>
+ write_reg pmpaddr4_ref (pmpWriteAddr w__36 w__37 value) >>
+ ((read_reg pmpaddr4_ref) : M (mword 64)) >>= fun w__38 : mword 64 =>
+ returnm ((Some
+ (w__38))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then
+ read_reg pmp5cfg_ref >>= fun w__39 : Pmpcfg_ent =>
+ ((read_reg pmpaddr5_ref) : M (mword 64)) >>= fun w__40 : mword 64 =>
+ write_reg pmpaddr5_ref (pmpWriteAddr w__39 w__40 value) >>
+ ((read_reg pmpaddr5_ref) : M (mword 64)) >>= fun w__41 : mword 64 =>
+ returnm ((Some
+ (w__41))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then
+ read_reg pmp6cfg_ref >>= fun w__42 : Pmpcfg_ent =>
+ ((read_reg pmpaddr6_ref) : M (mword 64)) >>= fun w__43 : mword 64 =>
+ write_reg pmpaddr6_ref (pmpWriteAddr w__42 w__43 value) >>
+ ((read_reg pmpaddr6_ref) : M (mword 64)) >>= fun w__44 : mword 64 =>
+ returnm ((Some
+ (w__44))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then
+ read_reg pmp7cfg_ref >>= fun w__45 : Pmpcfg_ent =>
+ ((read_reg pmpaddr7_ref) : M (mword 64)) >>= fun w__46 : mword 64 =>
+ write_reg pmpaddr7_ref (pmpWriteAddr w__45 w__46 value) >>
+ ((read_reg pmpaddr7_ref) : M (mword 64)) >>= fun w__47 : mword 64 =>
+ returnm ((Some
+ (w__47))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then
+ read_reg pmp8cfg_ref >>= fun w__48 : Pmpcfg_ent =>
+ ((read_reg pmpaddr8_ref) : M (mword 64)) >>= fun w__49 : mword 64 =>
+ write_reg pmpaddr8_ref (pmpWriteAddr w__48 w__49 value) >>
+ ((read_reg pmpaddr8_ref) : M (mword 64)) >>= fun w__50 : mword 64 =>
+ returnm ((Some
+ (w__50))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then
+ read_reg pmp9cfg_ref >>= fun w__51 : Pmpcfg_ent =>
+ ((read_reg pmpaddr9_ref) : M (mword 64)) >>= fun w__52 : mword 64 =>
+ write_reg pmpaddr9_ref (pmpWriteAddr w__51 w__52 value) >>
+ ((read_reg pmpaddr9_ref) : M (mword 64)) >>= fun w__53 : mword 64 =>
+ returnm ((Some
+ (w__53))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then
+ read_reg pmp10cfg_ref >>= fun w__54 : Pmpcfg_ent =>
+ ((read_reg pmpaddr10_ref) : M (mword 64)) >>= fun w__55 : mword 64 =>
+ write_reg pmpaddr10_ref (pmpWriteAddr w__54 w__55 value) >>
+ ((read_reg pmpaddr10_ref) : M (mword 64)) >>= fun w__56 : mword 64 =>
+ returnm ((Some
+ (w__56))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then
+ read_reg pmp11cfg_ref >>= fun w__57 : Pmpcfg_ent =>
+ ((read_reg pmpaddr11_ref) : M (mword 64)) >>= fun w__58 : mword 64 =>
+ write_reg pmpaddr11_ref (pmpWriteAddr w__57 w__58 value) >>
+ ((read_reg pmpaddr11_ref) : M (mword 64)) >>= fun w__59 : mword 64 =>
+ returnm ((Some
+ (w__59))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then
+ read_reg pmp12cfg_ref >>= fun w__60 : Pmpcfg_ent =>
+ ((read_reg pmpaddr12_ref) : M (mword 64)) >>= fun w__61 : mword 64 =>
+ write_reg pmpaddr12_ref (pmpWriteAddr w__60 w__61 value) >>
+ ((read_reg pmpaddr12_ref) : M (mword 64)) >>= fun w__62 : mword 64 =>
+ returnm ((Some
+ (w__62))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then
+ read_reg pmp13cfg_ref >>= fun w__63 : Pmpcfg_ent =>
+ ((read_reg pmpaddr13_ref) : M (mword 64)) >>= fun w__64 : mword 64 =>
+ write_reg pmpaddr13_ref (pmpWriteAddr w__63 w__64 value) >>
+ ((read_reg pmpaddr13_ref) : M (mword 64)) >>= fun w__65 : mword 64 =>
+ returnm ((Some
+ (w__65))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then
+ read_reg pmp14cfg_ref >>= fun w__66 : Pmpcfg_ent =>
+ ((read_reg pmpaddr14_ref) : M (mword 64)) >>= fun w__67 : mword 64 =>
+ write_reg pmpaddr14_ref (pmpWriteAddr w__66 w__67 value) >>
+ ((read_reg pmpaddr14_ref) : M (mword 64)) >>= fun w__68 : mword 64 =>
+ returnm ((Some
+ (w__68))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then
+ read_reg pmp15cfg_ref >>= fun w__69 : Pmpcfg_ent =>
+ ((read_reg pmpaddr15_ref) : M (mword 64)) >>= fun w__70 : mword 64 =>
+ write_reg pmpaddr15_ref (pmpWriteAddr w__69 w__70 value) >>
+ ((read_reg pmpaddr15_ref) : M (mword 64)) >>= fun w__71 : mword 64 =>
+ returnm ((Some
+ (w__71))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__72 : mword 64 =>
+ write_reg mcycle_ref (update_subrange_vec_dec w__72 (Z.sub 64 1) 0 value) >>
+ returnm ((Some
+ (value))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ ((read_reg minstret_ref) : M (mword 64)) >>= fun w__73 : mword 64 =>
+ write_reg minstret_ref (update_subrange_vec_dec w__73 (Z.sub 64 1) 0 value) >>
+ write_reg minstret_written_ref true >> returnm ((Some (value)) : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg tselect_ref value >>
+ ((read_reg tselect_ref) : M (mword 64)) >>= fun w__74 : mword 64 =>
+ returnm ((Some
+ (w__74))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ read_reg mstatus_ref >>= fun w__75 : Mstatus =>
+ (legalize_sstatus w__75 value) >>= fun w__76 : Mstatus =>
+ write_reg mstatus_ref w__76 >>
+ read_reg mstatus_ref >>= fun w__77 : Mstatus =>
+ returnm ((Some
+ (_get_Mstatus_bits w__77))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ read_reg sedeleg_ref >>= fun w__78 : Sedeleg =>
+ write_reg sedeleg_ref (legalize_sedeleg w__78 value) >>
+ read_reg sedeleg_ref >>= fun w__79 : Sedeleg =>
+ returnm ((Some
+ (_get_Sedeleg_bits w__79))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ (_set_Sinterrupts_bits sideleg_ref value) >>
+ read_reg sideleg_ref >>= fun w__80 : Sinterrupts =>
+ returnm ((Some
+ (_get_Sinterrupts_bits w__80))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mie_ref >>= fun w__81 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__82 : Minterrupts =>
+ (legalize_sie w__81 w__82 value) >>= fun w__83 : Minterrupts =>
+ write_reg mie_ref w__83 >>
+ read_reg mie_ref >>= fun w__84 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__84))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then
+ (set_stvec value) >>= fun w__85 : mword 64 =>
+ returnm ((Some
+ (w__85))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then
+ read_reg scounteren_ref >>= fun w__86 : Counteren =>
+ (legalize_scounteren w__86 value) >>= fun w__87 : Counteren =>
+ write_reg scounteren_ref w__87 >>
+ read_reg scounteren_ref >>= fun w__88 : Counteren =>
+ returnm ((Some
+ (EXTZ 64 (_get_Counteren_bits w__88)))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ write_reg sscratch_ref value >>
+ ((read_reg sscratch_ref) : M (mword 64)) >>= fun w__89 : mword 64 =>
+ returnm ((Some
+ (w__89))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then
+ (set_xret_target Supervisor value) >>= fun w__90 : mword 64 =>
+ returnm ((Some
+ (w__90))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then
+ (_set_Mcause_bits scause_ref value) >>
+ read_reg scause_ref >>= fun w__91 : Mcause =>
+ returnm ((Some
+ (_get_Mcause_bits w__91))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then
+ write_reg stval_ref value >>
+ ((read_reg stval_ref) : M (mword 64)) >>= fun w__92 : mword 64 =>
+ returnm ((Some
+ (w__92))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then
+ read_reg mip_ref >>= fun w__93 : Minterrupts =>
+ read_reg mideleg_ref >>= fun w__94 : Minterrupts =>
+ (legalize_sip w__93 w__94 value) >>= fun w__95 : Minterrupts =>
+ write_reg mip_ref w__95 >>
+ read_reg mip_ref >>= fun w__96 : Minterrupts =>
+ returnm ((Some
+ (_get_Minterrupts_bits w__96))
+ : option (mword 64))
+ else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then
+ (cur_Architecture tt) >>= fun w__97 : Architecture =>
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__98 : mword 64 =>
+ write_reg satp_ref (legalize_satp w__97 w__98 value) >>
+ ((read_reg satp_ref) : M (mword 64)) >>= fun w__99 : mword 64 =>
+ returnm ((Some
+ (w__99))
+ : option (mword 64))
+ else returnm (None : option (mword 64)))
+ : M (option (mword 64))
+ end) >>= fun res : option xlenbits =>
+ (match res with
+ | Some (v) =>
+ returnm ((if ((get_config_print_reg tt)) then
+ print_endline
+ (String.append "CSR "
+ (String.append (csr_name csr)
+ (String.append " <- "
+ (String.append (string_of_bits v)
+ (String.append " (input: "
+ (String.append (string_of_bits value) ")"))))))
+ else tt)
+ : unit)
+ | None =>
+ (ext_write_CSR csr value) >>= fun w__145 : bool =>
+ returnm ((if sumbool_of_bool (w__145) then tt
+ else print_bits "unhandled write to CSR " csr)
+ : unit)
+ end)
+ : M (unit).
+
+Definition maybe_i_forwards (arg_ : bool)
+: string :=
+
+ match arg_ with | true => "i" | false => "" end.
+
+Definition maybe_i_backwards (arg_ : string)
+: M (bool) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "i")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq p0_ "")) then
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))}))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (bool).
+
+Definition maybe_i_forwards_matches (arg_ : bool)
+: bool :=
+
+ match arg_ with | true => true | false => true end.
+
+Definition maybe_i_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "i")) then true
+ else if ((generic_eq p0_ "")) then true
+ else false.
+
+Definition _s797_ (_s798_ : string)
+: option string :=
+
+ let _s799_ := _s798_ in
+ if ((string_startswith _s799_ "")) then
+ match (string_drop _s799_ (projT1 (string_length ""))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s793_ (_s794_ : string)
+: option string :=
+
+ let _s795_ := _s794_ in
+ if ((string_startswith _s795_ "i")) then
+ match (string_drop _s795_ (projT1 (string_length "i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition maybe_i_matches_prefix (arg_ : string)
+: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s796_ := arg_ in
+ (if ((match (_s793_ _s796_) with | Some (s_) => true | _ => false end)) then
+ (match (_s793_ _s796_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((true, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s797_ _s796_) with | Some (s_) => true | _ => false end)) then
+ (match (_s797_ _s796_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((false, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((bool * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((bool * {n : Z & ArithFact (n >= 0)}))).
+
+Definition csr_mnemonic_forwards (arg_ : csrop)
+: string :=
+
+ match arg_ with | CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" end.
+
+Definition csr_mnemonic_backwards (arg_ : string)
+: M (csrop) :=
+
+ let p0_ := arg_ in
+ (if ((generic_eq p0_ "csrrw")) then returnm (CSRRW : csrop)
+ else if ((generic_eq p0_ "csrrs")) then returnm (CSRRS : csrop)
+ else if ((generic_eq p0_ "csrrc")) then returnm (CSRRC : csrop)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (csrop).
+
+Definition csr_mnemonic_forwards_matches (arg_ : csrop)
+: bool :=
+
+ match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end.
+
+Definition csr_mnemonic_backwards_matches (arg_ : string)
+: bool :=
+
+ let p0_ := arg_ in
+ if ((generic_eq p0_ "csrrw")) then true
+ else if ((generic_eq p0_ "csrrs")) then true
+ else if ((generic_eq p0_ "csrrc")) then true
+ else false.
+
+Definition _s809_ (_s810_ : string)
+: option string :=
+
+ let _s811_ := _s810_ in
+ if ((string_startswith _s811_ "csrrc")) then
+ match (string_drop _s811_ (projT1 (string_length "csrrc"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s805_ (_s806_ : string)
+: option string :=
+
+ let _s807_ := _s806_ in
+ if ((string_startswith _s807_ "csrrs")) then
+ match (string_drop _s807_ (projT1 (string_length "csrrs"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s801_ (_s802_ : string)
+: option string :=
+
+ let _s803_ := _s802_ in
+ if ((string_startswith _s803_ "csrrw")) then
+ match (string_drop _s803_ (projT1 (string_length "csrrw"))) with | s_ => Some (s_) end
+ else None.
+
+Definition csr_mnemonic_matches_prefix (arg_ : string)
+: M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s804_ := arg_ in
+ (if ((match (_s801_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s801_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRW, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s805_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s805_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRS, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s809_ _s804_) with | Some (s_) => true | _ => false end)) then
+ (match (_s809_ _s804_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((CSRRC, build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)})))
+ else returnm (None : option ((csrop * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))).
+
+Definition encdec_forwards (arg_ : ast)
+: M (mword 32) :=
+
+ (match arg_ with
+ | UTYPE ((imm, rd, op)) =>
+ returnm ((concat_vec (imm : mword 20) (concat_vec (rd : mword 5) (encdec_uop_forwards op)))
+ : mword (20 + (5 + 7)))
+ | RISCV_JAL ((v__2, rd)) =>
+ (if ((eq_vec (subrange_vec_dec v__2 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in
+ let imm_8 : bits 1 := subrange_vec_dec v__2 11 11 in
+ let imm_7_0 : bits 8 := subrange_vec_dec v__2 19 12 in
+ let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in
+ let imm_18_13 : bits 6 := subrange_vec_dec v__2 10 5 in
+ let imm_12_9 : bits 4 := subrange_vec_dec v__2 4 1 in
+ returnm ((concat_vec (imm_19 : bits 1)
+ (concat_vec (imm_18_13 : bits 6)
+ (concat_vec (imm_12_9 : bits 4)
+ (concat_vec (imm_8 : bits 1)
+ (concat_vec (imm_7_0 : bits 8)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | BTYPE ((v__4, rs2, rs1, op)) =>
+ (if ((eq_vec (subrange_vec_dec v__4 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in
+ let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in
+ let imm7_5_0 : bits 6 := subrange_vec_dec v__4 10 5 in
+ let imm5_4_1 : bits 4 := subrange_vec_dec v__4 4 1 in
+ let imm5_0 : bits 1 := subrange_vec_dec v__4 11 11 in
+ returnm ((concat_vec (imm7_6 : bits 1)
+ (concat_vec (imm7_5_0 : bits 6)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (encdec_bop_forwards op)
+ (concat_vec (imm5_4_1 : bits 4)
+ (concat_vec (imm5_0 : bits 1)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7))))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | ITYPE ((imm, rs1, rd, op)) =>
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (encdec_iop_forwards op)
+ (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6)
+ (concat_vec (shamt : mword 6)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (6 + (6 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) =>
+ (if sumbool_of_bool ((orb (Z.ltb (projT1 (word_width_bytes size)) 8)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)))) then
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (bool_bits_forwards is_unsigned)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7))))))
+ : mword (12 + (5 + (1 + (2 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | STORE ((v__6, rs2, rs1, size, false, false)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then
+ let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in
+ let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in
+ let imm5 : bits 5 := subrange_vec_dec v__6 4 0 in
+ returnm ((concat_vec (imm7 : bits 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (imm5 : bits 5)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7)))))))
+ : mword 32)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | ADDIW ((imm, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (imm : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (shamt : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | FENCE ((pred, succ)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4)
+ (concat_vec (pred : mword 4)
+ (concat_vec (succ : mword 4)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword (4 + (4 + (4 + (5 + (3 + (5 + 7)))))))
+ | FENCE_TSO ((pred, succ)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0;B0] : mword 4)
+ (concat_vec (pred : mword 4)
+ (concat_vec (succ : mword 4)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))))
+ : mword (4 + (4 + (4 + (5 + (3 + (5 + 7)))))))
+ | FENCEI (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | ECALL (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | MRET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | SRET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | EBREAK (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | WFI (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))
+ : mword (12 + (5 + (3 + (5 + 7)))))
+ | SFENCE_VMA ((rs1, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | AMO ((op, aq, rl, rs2, rs1, size, rd)) =>
+ (if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then
+ returnm ((concat_vec (encdec_amoop_forwards op)
+ (concat_vec (bool_bits_forwards aq)
+ (concat_vec (bool_bits_forwards rl)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (size_bits_forwards size)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7)))))))))
+ : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7)))))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (encdec_mul_op_forwards (high, signed1, signed2)) >>= fun w__38 : mword 3 =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (w__38 : bits 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | DIV ((rs2, rs1, rd, s)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ | REM ((rs2, rs1, rd, s)) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ | MULW ((rs2, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | DIVW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | REMW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7)
+ (concat_vec (rs2 : mword 5)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (bool_not_bits_forwards s)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))))
+ : mword (7 + (5 + (5 + (2 + (1 + (5 + 7)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 32)
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ returnm ((concat_vec (csr : mword 12)
+ (concat_vec (rs1 : mword 5)
+ (concat_vec (bool_bits_forwards is_imm)
+ (concat_vec (encdec_csrop_forwards op)
+ (concat_vec (rd : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (12 + (5 + (1 + (2 + (5 + 7))))))
+ | URET (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))))
+ : mword (7 + (5 + (5 + (3 + (5 + 7))))))
+ | ILLEGAL (s) => returnm (s : mword 32)
+ | _ => assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt
+ end)
+ : M (mword 32).
+
+Definition encdec_backwards (arg_ : mword 32)
+: M (ast) :=
+
+ let v__7 := arg_ in
+ let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in
+ (and_boolM (returnm ((encdec_uop_backwards_matches _mappingpatterns_23_) : bool))
+ ((if ((encdec_uop_backwards_matches _mappingpatterns_23_)) then
+ (encdec_uop_backwards _mappingpatterns_23_) >>= fun op => returnm ((true : bool) : bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ let imm : mword 20 := subrange_vec_dec v__7 31 12 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 20 := subrange_vec_dec v__7 31 12 in
+ let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in
+ (encdec_uop_backwards _mappingpatterns_23_) >>= fun op =>
+ returnm ((UTYPE
+ ((imm, rd, op)))
+ : ast)
+ else if ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then
+ let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm_8 : bits 1 := subrange_vec_dec v__7 20 20 in
+ let imm_7_0 : bits 8 := subrange_vec_dec v__7 19 12 in
+ let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let imm_18_13 : bits 6 := subrange_vec_dec v__7 30 25 in
+ let imm_12_9 : bits 4 := subrange_vec_dec v__7 24 21 in
+ returnm ((RISCV_JAL
+ ((concat_vec (imm_19 : bits 1)
+ (concat_vec (imm_7_0 : bits 8)
+ (concat_vec (imm_8 : bits 1)
+ (concat_vec (imm_18_13 : bits 6)
+ (concat_vec (imm_12_9 : bits 4) (vec_of_bits [B0] : mword 1))))), rd)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ returnm ((RISCV_JALR
+ ((imm, rs1, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (and_boolM (returnm ((encdec_bop_backwards_matches _mappingpatterns_24_) : bool))
+ ((if ((encdec_bop_backwards_matches _mappingpatterns_24_)) then
+ (encdec_bop_backwards _mappingpatterns_24_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in
+ let imm7_5_0 : bits 6 := subrange_vec_dec v__7 30 25 in
+ let imm5_4_1 : bits 4 := subrange_vec_dec v__7 11 8 in
+ let imm5_0 : bits 1 := subrange_vec_dec v__7 7 7 in
+ let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (encdec_bop_backwards _mappingpatterns_24_) >>= fun op =>
+ returnm ((BTYPE
+ ((concat_vec (imm7_6 : bits 1)
+ (concat_vec (imm5_0 : bits 1)
+ (concat_vec (imm7_5_0 : bits 6)
+ (concat_vec (imm5_4_1 : bits 4) (vec_of_bits [B0] : mword 1)))), rs2, rs1, op)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (and_boolM (returnm ((encdec_iop_backwards_matches _mappingpatterns_25_) : bool))
+ ((if ((encdec_iop_backwards_matches _mappingpatterns_25_)) then
+ (encdec_iop_backwards _mappingpatterns_25_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__7 : bool =>
+ (if sumbool_of_bool (w__7) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in
+ (encdec_iop_backwards _mappingpatterns_25_) >>= fun op =>
+ returnm ((ITYPE
+ ((imm, rs1, rd, op)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__8 : bool =>
+ returnm ((Bool.eqb w__8 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool = true) (simp_0 =
+ true /\
+ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__10 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__10) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SLLI)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__11 : bool =>
+ returnm ((Bool.eqb w__11 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__13 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__13) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SRLI)))
+ : ast)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__14 : bool =>
+ returnm ((Bool.eqb w__14 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 26)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__16 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__16) then
+ let shamt : mword 6 := subrange_vec_dec v__7 25 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIOP
+ ((shamt, rs1, rd, RISCV_SRAI)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_ADD)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLT)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLTU)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_AND)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_OR)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_XOR)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SLL)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SRL)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SUB)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPE
+ ((rs2, rs1, rd, RISCV_SRA)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_27_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_27_)) then
+ (size_bits_backwards _mappingpatterns_27_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_26_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_26_)) then
+ (bool_bits_backwards _mappingpatterns_26_) >>= fun is_unsigned =>
+ returnm (((orb (Z.ltb (projT1 (word_width_bytes size)) 8)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)))
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__18 : bool =>
+ returnm ((w__18
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__21 : bool =>
+ (if sumbool_of_bool (w__21) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in
+ (size_bits_backwards _mappingpatterns_27_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_26_) >>= fun is_unsigned =>
+ returnm ((LOAD
+ ((imm, rs1, rd, is_unsigned, size, false, false)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_28_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_28_)) then
+ (size_bits_backwards _mappingpatterns_28_) >>= fun size =>
+ returnm (((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__24 : bool =>
+ (if sumbool_of_bool (w__24) then
+ let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in
+ let imm5 : bits 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ (size_bits_backwards _mappingpatterns_28_) >>= fun size =>
+ returnm ((STORE
+ ((concat_vec (imm7 : bits 7) (imm5 : bits 5), rs2, rs1, size, false, false)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))) then
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let imm : mword 12 := subrange_vec_dec v__7 31 20 in
+ returnm ((ADDIW
+ ((imm, rs1, rd)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SLLI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SRLI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTW
+ ((shamt, rs1, rd, RISCV_SRAI)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_ADDW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SUBW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SLLW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SRLW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((RTYPEW
+ ((rs2, rs1, rd, RISCV_SRAW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SLLIW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SRLIW)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ let shamt : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((SHIFTIWOP
+ ((shamt, rs1, rd, RISCV_SRAIW)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 28)
+ (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__7 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ let succ : mword 4 := subrange_vec_dec v__7 23 20 in
+ let pred : mword 4 := subrange_vec_dec v__7 27 24 in
+ returnm ((FENCE
+ ((pred, succ)))
+ : ast)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 28)
+ (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__7 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ let succ : mword 4 := subrange_vec_dec v__7 23 20 in
+ let pred : mword 4 := subrange_vec_dec v__7 27 24 in
+ returnm ((FENCE_TSO
+ ((pred, succ)))
+ : ast)
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword 32))) then
+ returnm ((FENCEI
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((ECALL
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((MRET
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((SRET
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((EBREAK
+ (tt))
+ : ast )
+ else if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm ((WFI
+ (tt))
+ : ast )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__7 14 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword (14 - 0 + 1))))) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ returnm ((SFENCE_VMA
+ ((rs1, rs2)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_31_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_29_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_31_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_31_)) then
+ (size_bits_backwards _mappingpatterns_31_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_30_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_30_))
+ then
+ (bool_bits_backwards _mappingpatterns_30_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_29_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_29_)) then
+ (bool_bits_backwards _mappingpatterns_29_) >>= fun aq =>
+ returnm (((Z.leb (projT1 (word_width_bytes size))
+ 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__26 : bool =>
+ returnm ((w__26
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__28 : bool =>
+ returnm ((w__28
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 24 20)
+ (vec_of_bits [B0;B0;B0;B0;B0]
+ : mword (24 - 20 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))))
+ : bool))) >>= fun w__31 : bool =>
+ (if sumbool_of_bool (w__31) then
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_31_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_29_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (size_bits_backwards _mappingpatterns_31_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_30_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_29_) >>= fun aq =>
+ returnm ((LOADRES
+ ((aq, rl, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_34_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_34_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_34_)) then
+ (size_bits_backwards _mappingpatterns_34_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_33_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_33_))
+ then
+ (bool_bits_backwards _mappingpatterns_33_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_32_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_32_)) then
+ (bool_bits_backwards _mappingpatterns_32_) >>= fun aq =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size)) 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__33 : bool =>
+ returnm ((w__33
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__35 : bool =>
+ returnm ((w__35
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B1]
+ : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__38 : bool =>
+ (if sumbool_of_bool (w__38) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_34_ : mword 2 := subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 26 26 in
+ (size_bits_backwards _mappingpatterns_34_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_33_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_32_) >>= fun aq =>
+ returnm ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ let _mappingpatterns_38_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_37_ : mword 1 :=
+ subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_36_ : mword 1 :=
+ subrange_vec_dec v__7 26 26 in
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_38_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_38_))
+ then
+ (size_bits_backwards _mappingpatterns_38_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_37_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_37_)) then
+ (bool_bits_backwards _mappingpatterns_37_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_36_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_36_)) then
+ (bool_bits_backwards _mappingpatterns_36_) >>= fun aq =>
+ (and_boolM
+ (returnm ((encdec_amoop_backwards_matches
+ _mappingpatterns_35_)
+ : bool))
+ ((if ((encdec_amoop_backwards_matches
+ _mappingpatterns_35_)) then
+ (encdec_amoop_backwards
+ _mappingpatterns_35_) >>= fun op =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size))
+ 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__40 : bool =>
+ returnm ((w__40
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__42 : bool =>
+ returnm ((w__42
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__44 : bool =>
+ returnm ((w__44
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__47 : bool =>
+ (if sumbool_of_bool (w__47) then
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_38_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_37_ : mword 1 :=
+ subrange_vec_dec v__7 25 25 in
+ let _mappingpatterns_36_ : mword 1 :=
+ subrange_vec_dec v__7 26 26 in
+ let _mappingpatterns_35_ : mword 5 :=
+ subrange_vec_dec v__7 31 27 in
+ (size_bits_backwards _mappingpatterns_38_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_37_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_36_) >>= fun aq =>
+ (encdec_amoop_backwards _mappingpatterns_35_) >>= fun op =>
+ returnm ((AMO
+ ((op, aq, rl, rs2, rs1, size, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_39_ : mword 3 :=
+ subrange_vec_dec v__7 14 12 in
+ (and_boolM
+ (returnm ((encdec_mul_op_backwards_matches
+ _mappingpatterns_39_)
+ : bool))
+ ((if ((encdec_mul_op_backwards_matches
+ _mappingpatterns_39_)) then
+ (encdec_mul_op_backwards _mappingpatterns_39_) >>= fun '(high, signed1, signed2) =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__50 : bool =>
+ (if sumbool_of_bool (w__50) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_39_ : mword 3 :=
+ subrange_vec_dec v__7 14 12 in
+ (encdec_mul_op_backwards _mappingpatterns_39_) >>= fun '(high, signed1, signed2) =>
+ returnm ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_40_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_40_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_40_)) then
+ (bool_not_bits_backwards _mappingpatterns_40_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__53 : bool =>
+ (if sumbool_of_bool (w__53) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_40_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_40_) >>= fun s =>
+ returnm ((DIV
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_41_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_41_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_41_)) then
+ (bool_not_bits_backwards _mappingpatterns_41_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__56 : bool =>
+ (if sumbool_of_bool (w__56) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_41_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_41_) >>= fun s =>
+ returnm ((REM
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7
+ 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__7 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec
+ (subrange_vec_dec
+ v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))))
+ then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ returnm ((MULW
+ ((rs2, rs1, rd)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_42_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_42_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_42_)) then
+ (bool_not_bits_backwards _mappingpatterns_42_) >>= fun s =>
+ returnm (((Z.eqb 64 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__59 : bool =>
+ (if sumbool_of_bool (w__59) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_42_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_42_) >>= fun s =>
+ returnm ((DIVW
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_43_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_43_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_43_)) then
+ (bool_not_bits_backwards
+ _mappingpatterns_43_) >>= fun s =>
+ returnm (((Z.eqb 64 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec
+ (subrange_vec_dec v__7 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__7 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__62 : bool =>
+ (if sumbool_of_bool (w__62) then
+ let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in
+ let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let _mappingpatterns_43_ : mword 1 :=
+ subrange_vec_dec v__7 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_43_) >>= fun s =>
+ returnm ((REMW
+ ((rs2, rs1, rd, s)))
+ : ast)
+ else
+ (and_boolM
+ (let _mappingpatterns_45_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_44_ : mword 1 :=
+ subrange_vec_dec v__7 14 14 in
+ (and_boolM
+ (returnm ((encdec_csrop_backwards_matches
+ _mappingpatterns_45_)
+ : bool))
+ ((if ((encdec_csrop_backwards_matches
+ _mappingpatterns_45_)) then
+ (encdec_csrop_backwards
+ _mappingpatterns_45_) >>= fun op =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_44_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_44_)) then
+ (bool_bits_backwards
+ _mappingpatterns_44_) >>= fun is_imm =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__64 : bool =>
+ returnm ((w__64
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__7 6 0)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__67 : bool =>
+ (if sumbool_of_bool (w__67) then
+ let csr : mword 12 :=
+ subrange_vec_dec v__7 31 20 in
+ let rs1 : mword 5 :=
+ subrange_vec_dec v__7 19 15 in
+ let rd : mword 5 := subrange_vec_dec v__7 11 7 in
+ let csr : mword 12 :=
+ subrange_vec_dec v__7 31 20 in
+ let _mappingpatterns_45_ : mword 2 :=
+ subrange_vec_dec v__7 13 12 in
+ let _mappingpatterns_44_ : mword 1 :=
+ subrange_vec_dec v__7 14 14 in
+ (encdec_csrop_backwards _mappingpatterns_45_) >>= fun op =>
+ (bool_bits_backwards _mappingpatterns_44_) >>= fun is_imm =>
+ returnm ((CSR
+ ((csr, rs1, rd, is_imm, op)))
+ : ast)
+ else
+ returnm ((if ((eq_vec v__7
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ URET
+ (tt)
+ else ILLEGAL (v__7))
+ : ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast).
+
+Definition encdec_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | UTYPE ((imm, rd, op)) => true
+ | RISCV_JAL ((v__220, rd)) =>
+ if ((eq_vec (subrange_vec_dec v__220 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true
+ else false
+ | RISCV_JALR ((imm, rs1, rd)) => true
+ | BTYPE ((v__222, rs2, rs1, op)) =>
+ if ((eq_vec (subrange_vec_dec v__222 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true
+ else false
+ | ITYPE ((imm, rs1, rd, op)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) => true
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) => true
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) => true
+ | LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) =>
+ if sumbool_of_bool ((orb (Z.ltb (projT1 (word_width_bytes size)) 8)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)))) then
+ true
+ else false
+ | STORE ((v__224, rs2, rs1, size, false, false)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then true else false
+ | ADDIW ((imm, rs1, rd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | FENCE ((pred, succ)) => true
+ | FENCE_TSO ((pred, succ)) => true
+ | FENCEI (tt) => true
+ | ECALL (tt) => true
+ | MRET (tt) => true
+ | SRET (tt) => true
+ | EBREAK (tt) => true
+ | WFI (tt) => true
+ | SFENCE_VMA ((rs1, rs2)) => true
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then true else false
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then true else false
+ | AMO ((op, aq, rl, rs2, rs1, size, rd)) =>
+ if sumbool_of_bool ((Z.leb (projT1 (word_width_bytes size)) 8)) then true else false
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => true
+ | DIV ((rs2, rs1, rd, s)) => true
+ | REM ((rs2, rs1, rd, s)) => true
+ | MULW ((rs2, rs1, rd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | DIVW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | REMW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | CSR ((csr, rs1, rd, is_imm, op)) => true
+ | URET (tt) => true
+ | ILLEGAL (s) => true
+ | _ => false
+ end.
+
+Definition encdec_backwards_matches (arg_ : mword 32)
+: M (bool) :=
+
+ let v__225 := arg_ in
+ let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__225 6 0 in
+ (and_boolM (returnm ((encdec_uop_backwards_matches _mappingpatterns_0_) : bool))
+ ((if ((encdec_uop_backwards_matches _mappingpatterns_0_)) then
+ (encdec_uop_backwards _mappingpatterns_0_) >>= fun op => returnm ((true : bool) : bool)
+ else returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__225 6 0 in
+ (encdec_uop_backwards _mappingpatterns_0_) >>= fun op => returnm (true : bool)
+ else if ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (and_boolM (returnm ((encdec_bop_backwards_matches _mappingpatterns_1_) : bool))
+ ((if ((encdec_bop_backwards_matches _mappingpatterns_1_)) then
+ (encdec_bop_backwards _mappingpatterns_1_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__4 : bool =>
+ (if sumbool_of_bool (w__4) then
+ let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (encdec_bop_backwards _mappingpatterns_1_) >>= fun op => returnm (true : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (and_boolM (returnm ((encdec_iop_backwards_matches _mappingpatterns_2_) : bool))
+ ((if ((encdec_iop_backwards_matches _mappingpatterns_2_)) then
+ (encdec_iop_backwards _mappingpatterns_2_) >>= fun op =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__7 : bool =>
+ (if sumbool_of_bool (w__7) then
+ let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__225 14 12 in
+ (encdec_iop_backwards _mappingpatterns_2_) >>= fun op => returnm (true : bool)
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__8 : bool =>
+ returnm ((Bool.eqb w__8 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool = true) (simp_0 =
+ true /\
+ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__10 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__10) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__11 : bool =>
+ returnm ((Bool.eqb w__11 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 =
+ 64 \/
+ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__13 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__13) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolMP
+ ((let shamt : mword 6 := subrange_vec_dec v__225 25 20 in
+ (or_boolMP
+ ((returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.eqb 64 64)
+ : {_bool : bool & ArithFact (iff (_bool = true) (64 = 64))})))) : M ({_bool : bool & ArithFact (iff (_bool =
+ true) (64 = 64))}))
+ (build_trivial_ex
+ ((bit_to_bool (access_vec_dec shamt 5)) >>= fun w__14 : bool =>
+ returnm ((Bool.eqb w__14 false)
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool = true) (64 = 64 \/
+ simp_0 = true))})) : M ({_bool : bool & ArithFact (exists simp_0 , iff (_bool =
+ true) (64 = 64 \/ simp_0 = true))}))
+ (build_trivial_ex
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 26)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))
+ : bool))) : M ({_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))})) >>= fun '(existT _ w__16 _ : {_bool : bool & ArithFact (exists simp_0 simp_1 , iff (_bool =
+ true) (simp_0 = true /\ (64 = 64 \/ simp_1 = true)))}) =>
+ (if sumbool_of_bool (w__16) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__225 14 14 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_4_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_4_)) then
+ (size_bits_backwards _mappingpatterns_4_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_3_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_3_)) then
+ (bool_bits_backwards _mappingpatterns_3_) >>= fun is_unsigned =>
+ returnm (((orb (Z.ltb (projT1 (word_width_bytes size)) 8)
+ (andb (negb is_unsigned)
+ ((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)))
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__18 : bool =>
+ returnm ((w__18
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__21 : bool =>
+ (if sumbool_of_bool (w__21) then
+ let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__225 14 14 in
+ (size_bits_backwards _mappingpatterns_4_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_3_) >>= fun is_unsigned =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_5_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_5_)) then
+ (size_bits_backwards _mappingpatterns_5_) >>= fun size =>
+ returnm (((Z.leb (projT1 (word_width_bytes size)) 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__24 : bool =>
+ (if sumbool_of_bool (w__24) then
+ let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ (size_bits_backwards _mappingpatterns_5_) >>= fun size =>
+ returnm (true
+ : bool)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B0;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 12)
+ (vec_of_bits [B1;B0;B1]
+ : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1))))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 28)
+ (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__225 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 28)
+ (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1)))
+ (eq_vec (subrange_vec_dec v__225 19 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword (19 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__225 14 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword (14 - 0 + 1))))) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_8_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_6_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_8_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_8_)) then
+ (size_bits_backwards _mappingpatterns_8_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches _mappingpatterns_7_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_7_))
+ then
+ (bool_bits_backwards _mappingpatterns_7_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_6_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_6_)) then
+ (bool_bits_backwards _mappingpatterns_6_) >>= fun aq =>
+ returnm (((Z.leb (projT1 (word_width_bytes size))
+ 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__26 : bool =>
+ returnm ((w__26
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__28 : bool =>
+ returnm ((w__28
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 24 20)
+ (vec_of_bits [B0;B0;B0;B0;B0]
+ : mword (24 - 20 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))))
+ : bool))) >>= fun w__31 : bool =>
+ (if sumbool_of_bool (w__31) then
+ let _mappingpatterns_8_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_6_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ (size_bits_backwards _mappingpatterns_8_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_7_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_6_) >>= fun aq =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_11_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_11_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_11_)) then
+ (size_bits_backwards _mappingpatterns_11_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_10_)
+ : bool))
+ ((if ((bool_bits_backwards_matches _mappingpatterns_10_))
+ then
+ (bool_bits_backwards _mappingpatterns_10_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_9_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_9_)) then
+ (bool_bits_backwards _mappingpatterns_9_) >>= fun aq =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size)) 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__33 : bool =>
+ returnm ((w__33
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__35 : bool =>
+ returnm ((w__35
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 27)
+ (vec_of_bits [B0;B0;B0;B1;B1]
+ : mword (31 - 27 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__38 : bool =>
+ (if sumbool_of_bool (w__38) then
+ let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_11_ : mword 2 := subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__225 25 25 in
+ (size_bits_backwards _mappingpatterns_11_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_10_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_9_) >>= fun aq =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ let _mappingpatterns_15_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_14_ : mword 1 :=
+ subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_13_ : mword 1 :=
+ subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ (and_boolM
+ (returnm ((size_bits_backwards_matches _mappingpatterns_15_)
+ : bool))
+ ((if ((size_bits_backwards_matches _mappingpatterns_15_))
+ then
+ (size_bits_backwards _mappingpatterns_15_) >>= fun size =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_14_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_14_)) then
+ (bool_bits_backwards _mappingpatterns_14_) >>= fun rl =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_13_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_13_)) then
+ (bool_bits_backwards _mappingpatterns_13_) >>= fun aq =>
+ (and_boolM
+ (returnm ((encdec_amoop_backwards_matches
+ _mappingpatterns_12_)
+ : bool))
+ ((if ((encdec_amoop_backwards_matches
+ _mappingpatterns_12_)) then
+ (encdec_amoop_backwards
+ _mappingpatterns_12_) >>= fun op =>
+ returnm (((Z.leb
+ (projT1
+ (word_width_bytes size))
+ 8)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__40 : bool =>
+ returnm ((w__40
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__42 : bool =>
+ returnm ((w__42
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool))) >>= fun w__44 : bool =>
+ returnm ((w__44
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 14 14)
+ (vec_of_bits [B0] : mword (14 - 14 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__47 : bool =>
+ (if sumbool_of_bool (w__47) then
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ let _mappingpatterns_15_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_14_ : mword 1 :=
+ subrange_vec_dec v__225 25 25 in
+ let _mappingpatterns_13_ : mword 1 :=
+ subrange_vec_dec v__225 26 26 in
+ let _mappingpatterns_12_ : mword 5 :=
+ subrange_vec_dec v__225 31 27 in
+ (size_bits_backwards _mappingpatterns_15_) >>= fun size =>
+ (bool_bits_backwards _mappingpatterns_14_) >>= fun rl =>
+ (bool_bits_backwards _mappingpatterns_13_) >>= fun aq =>
+ (encdec_amoop_backwards _mappingpatterns_12_) >>= fun op =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_16_ : mword 3 :=
+ subrange_vec_dec v__225 14 12 in
+ (and_boolM
+ (returnm ((encdec_mul_op_backwards_matches
+ _mappingpatterns_16_)
+ : bool))
+ ((if ((encdec_mul_op_backwards_matches
+ _mappingpatterns_16_)) then
+ (encdec_mul_op_backwards _mappingpatterns_16_) >>= fun '(high, signed1, signed2) =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1))))
+ : bool))) >>= fun w__50 : bool =>
+ (if sumbool_of_bool (w__50) then
+ let _mappingpatterns_16_ : mword 3 :=
+ subrange_vec_dec v__225 14 12 in
+ (encdec_mul_op_backwards _mappingpatterns_16_) >>= fun '(high, signed1, signed2) =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_17_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_17_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_17_)) then
+ (bool_not_bits_backwards _mappingpatterns_17_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__53 : bool =>
+ (if sumbool_of_bool (w__53) then
+ let _mappingpatterns_17_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_17_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_18_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_18_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_18_)) then
+ (bool_not_bits_backwards _mappingpatterns_18_) >>= fun s =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool = true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__56 : bool =>
+ (if sumbool_of_bool (w__56) then
+ let _mappingpatterns_18_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_18_) >>= fun s =>
+ returnm (true
+ : bool)
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec
+ v__225 14 12)
+ (vec_of_bits [B0;B0;B0]
+ : mword (14 - 12 + 1)))
+ (eq_vec
+ (subrange_vec_dec
+ v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (and_boolM
+ (let _mappingpatterns_19_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_19_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_19_)) then
+ (bool_not_bits_backwards _mappingpatterns_19_) >>= fun s =>
+ returnm (((Z.eqb 64 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B0]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__59 : bool =>
+ (if sumbool_of_bool (w__59) then
+ let _mappingpatterns_19_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_19_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_20_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (and_boolM
+ (returnm ((bool_not_bits_backwards_matches
+ _mappingpatterns_20_)
+ : bool))
+ ((if ((bool_not_bits_backwards_matches
+ _mappingpatterns_20_)) then
+ (bool_not_bits_backwards
+ _mappingpatterns_20_) >>= fun s =>
+ returnm (((Z.eqb 64 64)
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((andb
+ (eq_vec
+ (subrange_vec_dec v__225 31 25)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]
+ : mword (31 - 25 + 1)))
+ (andb
+ (eq_vec
+ (subrange_vec_dec v__225 14 13)
+ (vec_of_bits [B1;B1]
+ : mword (14 - 13 + 1)))
+ (eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]
+ : mword (6 - 0 + 1)))))
+ : bool))) >>= fun w__62 : bool =>
+ (if sumbool_of_bool (w__62) then
+ let _mappingpatterns_20_ : mword 1 :=
+ subrange_vec_dec v__225 12 12 in
+ (bool_not_bits_backwards _mappingpatterns_20_) >>= fun s =>
+ returnm (true
+ : bool)
+ else
+ (and_boolM
+ (let _mappingpatterns_22_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_21_ : mword 1 :=
+ subrange_vec_dec v__225 14 14 in
+ (and_boolM
+ (returnm ((encdec_csrop_backwards_matches
+ _mappingpatterns_22_)
+ : bool))
+ ((if ((encdec_csrop_backwards_matches
+ _mappingpatterns_22_)) then
+ (encdec_csrop_backwards
+ _mappingpatterns_22_) >>= fun op =>
+ (and_boolM
+ (returnm ((bool_bits_backwards_matches
+ _mappingpatterns_21_)
+ : bool))
+ ((if ((bool_bits_backwards_matches
+ _mappingpatterns_21_)) then
+ (bool_bits_backwards
+ _mappingpatterns_21_) >>= fun is_imm =>
+ returnm ((true
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))) >>= fun w__64 : bool =>
+ returnm ((w__64
+ : bool)
+ : bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool)))
+ : M (bool))
+ (returnm ((eq_vec
+ (subrange_vec_dec v__225 6 0)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]
+ : mword (6 - 0 + 1)))
+ : bool))) >>= fun w__67 : bool =>
+ (if sumbool_of_bool (w__67) then
+ let _mappingpatterns_22_ : mword 2 :=
+ subrange_vec_dec v__225 13 12 in
+ let _mappingpatterns_21_ : mword 1 :=
+ subrange_vec_dec v__225 14 14 in
+ (encdec_csrop_backwards _mappingpatterns_22_) >>= fun op =>
+ (bool_bits_backwards _mappingpatterns_21_) >>= fun is_imm =>
+ returnm (true
+ : bool)
+ else
+ returnm ((if ((eq_vec v__225
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : mword 32))) then
+ true
+ else true)
+ : bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool).
+
+Definition encdec_compressed_forwards (arg_ : ast)
+: M (mword 16) :=
+
+ (match arg_ with
+ | C_NOP (tt) =>
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B0;B1] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ | C_ADDI4SPN ((rd, v__438)) =>
+ (if ((let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__438 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__438 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__438 0 0 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__438 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__438 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__438 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__438 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nz54 : bits 2)
+ (concat_vec (nz96 : bits 4)
+ (concat_vec (nz2 : bits 1)
+ (concat_vec (nz3 : bits 1)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LW ((v__439, rs1, rd)) =>
+ let ui6 : bits 1 := subrange_vec_dec v__439 4 4 in
+ let ui6 : bits 1 := subrange_vec_dec v__439 4 4 in
+ let ui53 : bits 3 := subrange_vec_dec v__439 3 1 in
+ let ui2 : bits 1 := subrange_vec_dec v__439 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui2 : bits 1)
+ (concat_vec (ui6 : bits 1)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ | C_LD ((v__440, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ let ui76 : bits 2 := subrange_vec_dec v__440 4 3 in
+ let ui76 : bits 2 := subrange_vec_dec v__440 4 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__440 2 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rd : cregidx) (vec_of_bits [B0;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SW ((v__441, rs1, rs2)) =>
+ let ui6 : bits 1 := subrange_vec_dec v__441 4 4 in
+ let ui6 : bits 1 := subrange_vec_dec v__441 4 4 in
+ let ui53 : bits 3 := subrange_vec_dec v__441 3 1 in
+ let ui2 : bits 1 := subrange_vec_dec v__441 0 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : cregidx)
+ (concat_vec (ui2 : bits 1)
+ (concat_vec (ui6 : bits 1)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B0] : mword 2)))))))
+ : mword 16)
+ | C_SD ((v__442, rs1, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ let ui76 : bits 2 := subrange_vec_dec v__442 4 3 in
+ let ui76 : bits 2 := subrange_vec_dec v__442 4 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__442 2 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (rs1 : bits 3)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rs2 : bits 3) (vec_of_bits [B0;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDI ((v__443, rsd)) =>
+ (if ((let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__443 4 0 in
+ andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__443 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__443 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nzi5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (nzi40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JAL (v__444) =>
+ (if sumbool_of_bool ((Z.eqb 64 32)) then
+ let i11 : bits 1 := subrange_vec_dec v__444 10 10 in
+ let i98 : bits 2 := subrange_vec_dec v__444 8 7 in
+ let i7 : bits 1 := subrange_vec_dec v__444 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__444 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__444 4 4 in
+ let i4 : bits 1 := subrange_vec_dec v__444 3 3 in
+ let i31 : bits 3 := subrange_vec_dec v__444 2 0 in
+ let i11 : bits 1 := subrange_vec_dec v__444 10 10 in
+ let i10 : bits 1 := subrange_vec_dec v__444 9 9 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i4 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i31 : bits 3)
+ (concat_vec (i5 : bits 1)
+ (vec_of_bits [B0;B1] : mword 2))))))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDIW ((v__445, rsd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))) then
+ let imm5 : bits 1 := subrange_vec_dec v__445 5 5 in
+ let imm5 : bits 1 := subrange_vec_dec v__445 5 5 in
+ let imm40 : bits 5 := subrange_vec_dec v__445 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3)
+ (concat_vec (imm5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LI ((v__446, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ let imm5 : bits 1 := subrange_vec_dec v__446 5 5 in
+ let imm5 : bits 1 := subrange_vec_dec v__446 5 5 in
+ let imm40 : bits 5 := subrange_vec_dec v__446 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (imm5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDI16SP (v__447) =>
+ (if ((let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__447 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__447 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__447 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__447 0 0 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__447 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__447 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__447 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__447 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__447 0 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (nzi9 : bits 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)
+ (concat_vec (nzi4 : bits 1)
+ (concat_vec (nzi6 : bits 1)
+ (concat_vec (nzi87 : bits 2)
+ (concat_vec (nzi5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LUI ((v__448, rd)) =>
+ (if sumbool_of_bool ((let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__448 4 0 in
+ andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))) then
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__448 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__448 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (imm17 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (imm1612 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SRLI ((v__449, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__449 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ then
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__449 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__449 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SRAI ((v__450, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__450 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ then
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__450 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__450 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ANDI ((v__451, rsd)) =>
+ let i5 : bits 1 := subrange_vec_dec v__451 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__451 5 5 in
+ let i40 : bits 5 := subrange_vec_dec v__451 4 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (i5 : bits 1)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (i40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))))
+ : mword 16)
+ | C_SUB ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_XOR ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_OR ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B1;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_AND ((rsd, rs2)) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ | C_SUBW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ADDW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B1;B1] : mword 2)
+ (concat_vec (rsd : cregidx)
+ (concat_vec (vec_of_bits [B0;B1] : mword 2)
+ (concat_vec (rs2 : cregidx) (vec_of_bits [B0;B1] : mword 2)))))))
+ : mword (3 + (1 + (2 + (3 + (2 + (3 + 2)))))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_J (v__452) =>
+ let i11 : bits 1 := subrange_vec_dec v__452 10 10 in
+ let i98 : bits 2 := subrange_vec_dec v__452 8 7 in
+ let i7 : bits 1 := subrange_vec_dec v__452 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__452 5 5 in
+ let i5 : bits 1 := subrange_vec_dec v__452 4 4 in
+ let i4 : bits 1 := subrange_vec_dec v__452 3 3 in
+ let i31 : bits 3 := subrange_vec_dec v__452 2 0 in
+ let i11 : bits 1 := subrange_vec_dec v__452 10 10 in
+ let i10 : bits 1 := subrange_vec_dec v__452 9 9 in
+ returnm ((concat_vec (vec_of_bits [B1;B0;B1] : mword 3)
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i4 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i31 : bits 3)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))))
+ : mword 16)
+ | C_BEQZ ((v__453, rs)) =>
+ let i8 : bits 1 := subrange_vec_dec v__453 7 7 in
+ let i8 : bits 1 := subrange_vec_dec v__453 7 7 in
+ let i76 : bits 2 := subrange_vec_dec v__453 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__453 4 4 in
+ let i43 : bits 2 := subrange_vec_dec v__453 3 2 in
+ let i21 : bits 2 := subrange_vec_dec v__453 1 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (i8 : bits 1)
+ (concat_vec (i43 : bits 2)
+ (concat_vec (rs : cregidx)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i21 : bits 2)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ | C_BNEZ ((v__454, rs)) =>
+ let i8 : bits 1 := subrange_vec_dec v__454 7 7 in
+ let i8 : bits 1 := subrange_vec_dec v__454 7 7 in
+ let i76 : bits 2 := subrange_vec_dec v__454 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__454 4 4 in
+ let i43 : bits 2 := subrange_vec_dec v__454 3 2 in
+ let i21 : bits 2 := subrange_vec_dec v__454 1 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (i8 : bits 1)
+ (concat_vec (i43 : bits 2)
+ (concat_vec (rs : cregidx)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i21 : bits 2)
+ (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2))))))))
+ : mword 16)
+ | C_SLLI ((v__455, rsd)) =>
+ (if ((let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__455 4 0 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 64 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))) then
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__455 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__455 4 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3)
+ (concat_vec (nzui5 : bits 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (nzui40 : bits 5) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LWSP ((v__456, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ let ui76 : bits 2 := subrange_vec_dec v__456 5 4 in
+ let ui76 : bits 2 := subrange_vec_dec v__456 5 4 in
+ let ui5 : bits 1 := subrange_vec_dec v__456 3 3 in
+ let ui42 : bits 3 := subrange_vec_dec v__456 2 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3)
+ (concat_vec (ui5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (ui42 : bits 3)
+ (concat_vec (ui76 : bits 2) (vec_of_bits [B1;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_LDSP ((v__457, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))) then
+ let ui86 : bits 3 := subrange_vec_dec v__457 5 3 in
+ let ui86 : bits 3 := subrange_vec_dec v__457 5 3 in
+ let ui5 : bits 1 := subrange_vec_dec v__457 2 2 in
+ let ui43 : bits 2 := subrange_vec_dec v__457 1 0 in
+ returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3)
+ (concat_vec (ui5 : bits 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (ui43 : bits 2)
+ (concat_vec (ui86 : bits 3) (vec_of_bits [B1;B0] : mword 2))))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_SWSP ((v__458, rs2)) =>
+ let ui76 : bits 2 := subrange_vec_dec v__458 5 4 in
+ let ui76 : bits 2 := subrange_vec_dec v__458 5 4 in
+ let ui52 : bits 4 := subrange_vec_dec v__458 3 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3)
+ (concat_vec (ui52 : bits 4)
+ (concat_vec (ui76 : bits 2)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ | C_SDSP ((v__459, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ let ui86 : bits 3 := subrange_vec_dec v__459 5 3 in
+ let ui86 : bits 3 := subrange_vec_dec v__459 5 3 in
+ let ui53 : bits 3 := subrange_vec_dec v__459 2 0 in
+ returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3)
+ (concat_vec (ui53 : bits 3)
+ (concat_vec (ui86 : bits 3)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword 16)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (rs1 : regidx)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_JALR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (rs1 : regidx)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_MV ((rd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B0] : mword 1)
+ (concat_vec (rd : regidx)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_EBREAK (tt) =>
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)
+ (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ | C_ADD ((rsd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3)
+ (concat_vec (vec_of_bits [B1] : mword 1)
+ (concat_vec (rsd : regidx)
+ (concat_vec (rs2 : regidx) (vec_of_bits [B1;B0] : mword 2)))))
+ : mword (3 + (1 + (5 + (5 + 2)))))
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (mword 16)
+ | C_ILLEGAL (s) => returnm (s : mword 16)
+ | _ => assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt
+ end)
+ : M (mword 16).
+
+Definition encdec_compressed_backwards (arg_ : mword 16)
+: ast :=
+
+ let v__460 := arg_ in
+ if ((eq_vec v__460 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))
+ then
+ C_NOP
+ (tt)
+ else if ((andb
+ (let nz96 : bits 4 := subrange_vec_dec v__460 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__460 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))))
+ then
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ let nz96 : bits 4 := subrange_vec_dec v__460 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__460 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ C_ADDI4SPN
+ ((rd, concat_vec (nz96 : bits 4)
+ (concat_vec (nz54 : bits 2) (concat_vec (nz3 : bits 1) (nz2 : bits 1)))))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let ui2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ C_LW
+ ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rd))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ let rd : cregidx := subrange_vec_dec v__460 4 2 in
+ C_LD
+ ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let ui2 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ let rs1 : cregidx := subrange_vec_dec v__460 9 7 in
+ C_SW
+ ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs2 : bits 3 := subrange_vec_dec v__460 4 2 in
+ let rs1 : bits 3 := subrange_vec_dec v__460 9 7 in
+ C_SD
+ ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rs2))
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ADDI
+ ((concat_vec (nzi5 : bits 1) (nzi40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb (Z.eqb 64 32)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let i98 : bits 2 := subrange_vec_dec v__460 10 9 in
+ let i7 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__460 7 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i4 : bits 1 := subrange_vec_dec v__460 11 11 in
+ let i31 : bits 3 := subrange_vec_dec v__460 5 3 in
+ let i11 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i10 : bits 1 := subrange_vec_dec v__460 8 8 in
+ C_JAL
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3))))))))
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ADDIW
+ ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_LI
+ ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rd))
+ else if ((andb
+ (let nzi9 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__460 6 6 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 7)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (11 - 7 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let nzi9 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__460 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__460 6 6 in
+ C_ADDI16SP
+ (concat_vec (nzi9 : bits 1)
+ (concat_vec (nzi87 : bits 2)
+ (concat_vec (nzi6 : bits 1) (concat_vec (nzi5 : bits 1) (nzi4 : bits 1)))))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_LUI
+ ((concat_vec (imm17 : bits 1) (imm1612 : bits 5), rd))
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B0;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SRLI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B0;B1] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SRAI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 11 10)
+ (vec_of_bits [B1;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_ANDI
+ ((concat_vec (i5 : bits 1) (i40 : bits 5), rsd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_SUB
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_XOR
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_OR
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_AND
+ ((rsd, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5)
+ (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_SUBW
+ ((rsd, rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 6 5)
+ (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ let rsd : cregidx := subrange_vec_dec v__460 9 7 in
+ let rs2 : cregidx := subrange_vec_dec v__460 4 2 in
+ C_ADDW
+ ((rsd, rs2))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let i98 : bits 2 := subrange_vec_dec v__460 10 9 in
+ let i7 : bits 1 := subrange_vec_dec v__460 6 6 in
+ let i6 : bits 1 := subrange_vec_dec v__460 7 7 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i4 : bits 1 := subrange_vec_dec v__460 11 11 in
+ let i31 : bits 3 := subrange_vec_dec v__460 5 3 in
+ let i11 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i10 : bits 1 := subrange_vec_dec v__460 8 8 in
+ C_J
+ (concat_vec (i11 : bits 1)
+ (concat_vec (i10 : bits 1)
+ (concat_vec (i98 : bits 2)
+ (concat_vec (i7 : bits 1)
+ (concat_vec (i6 : bits 1)
+ (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3))))))))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let rs : cregidx := subrange_vec_dec v__460 9 7 in
+ let i8 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i43 : bits 2 := subrange_vec_dec v__460 11 10 in
+ let i21 : bits 2 := subrange_vec_dec v__460 4 3 in
+ C_BEQZ
+ ((concat_vec (i8 : bits 1)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ let rs : cregidx := subrange_vec_dec v__460 9 7 in
+ let i8 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let i76 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let i5 : bits 1 := subrange_vec_dec v__460 2 2 in
+ let i43 : bits 2 := subrange_vec_dec v__460 11 10 in
+ let i21 : bits 2 := subrange_vec_dec v__460 4 3 in
+ C_BNEZ
+ ((concat_vec (i8 : bits 1)
+ (concat_vec (i76 : bits 2)
+ (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs))
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 64 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))))
+ then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__460 6 2 in
+ C_SLLI
+ ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui76 : bits 2 := subrange_vec_dec v__460 3 2 in
+ let ui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let ui42 : bits 3 := subrange_vec_dec v__460 6 4 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_LWSP
+ ((concat_vec (ui76 : bits 2) (concat_vec (ui5 : bits 1) (ui42 : bits 3)), rd))
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui86 : bits 3 := subrange_vec_dec v__460 4 2 in
+ let ui5 : bits 1 := subrange_vec_dec v__460 12 12 in
+ let ui43 : bits 2 := subrange_vec_dec v__460 6 5 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_LDSP
+ ((concat_vec (ui86 : bits 3) (concat_vec (ui5 : bits 1) (ui43 : bits 2)), rd))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ let ui76 : bits 2 := subrange_vec_dec v__460 8 7 in
+ let ui52 : bits 4 := subrange_vec_dec v__460 12 9 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_SWSP
+ ((concat_vec (ui76 : bits 2) (ui52 : bits 4), rs2))
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let ui86 : bits 3 := subrange_vec_dec v__460 9 7 in
+ let ui53 : bits 3 := subrange_vec_dec v__460 12 10 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_SDSP
+ ((concat_vec (ui86 : bits 3) (ui53 : bits 3), rs2))
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ C_JR
+ (rs1)
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ let rs1 : regidx := subrange_vec_dec v__460 11 7 in
+ C_JALR
+ (rs1)
+ else if sumbool_of_bool ((andb
+ (let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ let rd : regidx := subrange_vec_dec v__460 11 7 in
+ C_MV
+ ((rd, rs2))
+ else if ((eq_vec v__460
+ (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then
+ C_EBREAK
+ (tt)
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__460 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__460 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ let rsd : regidx := subrange_vec_dec v__460 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__460 6 2 in
+ C_ADD
+ ((rsd, rs2))
+ else C_ILLEGAL (v__460).
+
+Definition encdec_compressed_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | C_NOP (tt) => true
+ | C_ADDI4SPN ((rd, v__596)) =>
+ if ((let nz96 : bits 4 := subrange_vec_dec v__596 7 4 in
+ let nz96 : bits 4 := subrange_vec_dec v__596 7 4 in
+ let nz54 : bits 2 := subrange_vec_dec v__596 3 2 in
+ let nz3 : bits 1 := subrange_vec_dec v__596 1 1 in
+ let nz2 : bits 1 := subrange_vec_dec v__596 0 0 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then
+ true
+ else false
+ | C_LW ((v__597, rs1, rd)) => true
+ | C_LD ((v__598, rs1, rd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_SW ((v__599, rs1, rs2)) => true
+ | C_SD ((v__600, rs1, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_ADDI ((v__601, rsd)) =>
+ if ((let nzi5 : bits 1 := subrange_vec_dec v__601 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__601 5 5 in
+ let nzi40 : bits 5 := subrange_vec_dec v__601 4 0 in
+ andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_JAL (v__602) => if sumbool_of_bool ((Z.eqb 64 32)) then true else false
+ | C_ADDIW ((v__603, rsd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))) then
+ true
+ else false
+ | C_LI ((v__604, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_ADDI16SP (v__605) =>
+ if ((let nzi9 : bits 1 := subrange_vec_dec v__605 5 5 in
+ let nzi9 : bits 1 := subrange_vec_dec v__605 5 5 in
+ let nzi87 : bits 2 := subrange_vec_dec v__605 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__605 2 2 in
+ let nzi5 : bits 1 := subrange_vec_dec v__605 1 1 in
+ let nzi4 : bits 1 := subrange_vec_dec v__605 0 0 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then
+ true
+ else false
+ | C_LUI ((v__606, rd)) =>
+ if sumbool_of_bool ((let imm17 : bits 1 := subrange_vec_dec v__606 5 5 in
+ let imm17 : bits 1 := subrange_vec_dec v__606 5 5 in
+ let imm1612 : bits 5 := subrange_vec_dec v__606 4 0 in
+ andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))) then
+ true
+ else false
+ | C_SRLI ((v__607, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__607 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__607 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__607 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then
+ true
+ else false
+ | C_SRAI ((v__608, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__608 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__608 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__608 4 0 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then
+ true
+ else false
+ | C_ANDI ((v__609, rsd)) => true
+ | C_SUB ((rsd, rs2)) => true
+ | C_XOR ((rsd, rs2)) => true
+ | C_OR ((rsd, rs2)) => true
+ | C_AND ((rsd, rs2)) => true
+ | C_SUBW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_ADDW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_J (v__610) => true
+ | C_BEQZ ((v__611, rs)) => true
+ | C_BNEZ ((v__612, rs)) => true
+ | C_SLLI ((v__613, rsd)) =>
+ if ((let nzui5 : bits 1 := subrange_vec_dec v__613 5 5 in
+ let nzui5 : bits 1 := subrange_vec_dec v__613 5 5 in
+ let nzui40 : bits 5 := subrange_vec_dec v__613 4 0 in
+ andb (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb (projT1 (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 64 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))) then
+ true
+ else false
+ | C_LWSP ((v__614, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_LDSP ((v__615, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ (Z.eqb 64 64))) then
+ true
+ else false
+ | C_SWSP ((v__616, rs2)) => true
+ | C_SDSP ((v__617, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_JR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_JALR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_MV ((rd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_EBREAK (tt) => true
+ | C_ADD ((rsd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_ILLEGAL (s) => true
+ | _ => false
+ end.
+
+Definition encdec_compressed_backwards_matches (arg_ : mword 16)
+: bool :=
+
+ let v__618 := arg_ in
+ if ((eq_vec v__618 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))
+ then
+ true
+ else if ((andb
+ (let nz96 : bits 4 := subrange_vec_dec v__618 10 7 in
+ let nz54 : bits 2 := subrange_vec_dec v__618 12 11 in
+ let nz3 : bits 1 := subrange_vec_dec v__618 5 5 in
+ let nz2 : bits 1 := subrange_vec_dec v__618 6 6 in
+ neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2)))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let nzi5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzi40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 32)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let nzi9 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzi87 : bits 2 := subrange_vec_dec v__618 4 3 in
+ let nzi6 : bits 1 := subrange_vec_dec v__618 5 5 in
+ let nzi5 : bits 1 := subrange_vec_dec v__618 2 2 in
+ let nzi4 : bits 1 := subrange_vec_dec v__618 6 6 in
+ neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4))))
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 7)
+ (vec_of_bits [B0;B0;B0;B1;B0] : mword (11 - 7 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ let imm17 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let imm1612 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec (concat_vec imm17 imm1612)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B0;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B0;B1] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 11 10)
+ (vec_of_bits [B1;B0] : mword (11 - 10 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5)
+ (vec_of_bits [B0;B0] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 10)
+ (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1)))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 6 5)
+ (vec_of_bits [B0;B1] : mword (6 - 5 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let nzui5 : bits 1 := subrange_vec_dec v__618 12 12 in
+ let nzui40 : bits 5 := subrange_vec_dec v__618 6 2 in
+ andb
+ (neq_vec (concat_vec nzui5 nzui40)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ (orb (Z.eqb 64 64) (eq_vec nzui5 ((bool_to_bits false) : mword 1))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ true
+ else if sumbool_of_bool ((andb (Z.eqb 64 64)
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 13)
+ (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs1 : regidx := subrange_vec_dec v__618 11 7 in
+ projT1
+ (neq_int (projT1 (regidx_to_regno rs1))
+ (projT1
+ (regidx_to_regno zreg))))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1))))))
+ then
+ true
+ else if sumbool_of_bool ((andb
+ (let rs2 : regidx := subrange_vec_dec v__618 6 2 in
+ let rd : regidx := subrange_vec_dec v__618 11 7 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else if ((eq_vec v__618
+ (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then
+ true
+ else if sumbool_of_bool ((andb
+ (let rsd : regidx := subrange_vec_dec v__618 11 7 in
+ let rs2 : regidx := subrange_vec_dec v__618 6 2 in
+ andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))
+ (andb
+ (eq_vec (subrange_vec_dec v__618 15 12)
+ (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__618 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) then
+ true
+ else true.
+
+Definition execute_WFI '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | Machine => (platform_wfi tt) >> returnm (RETIRE_SUCCESS : Retired)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__1 : Mstatus =>
+ (if ((eq_vec (_get_Mstatus_TW w__1) ((bool_to_bits true) : mword 1))) then
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else (platform_wfi tt) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ | User => (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired).
+
+Definition execute_UTYPE (imm : mword 20) (rd : mword 5) (op : uop)
+: M (Retired) :=
+
+ let off : xlenbits :=
+ EXTS 64 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)) in
+ (match op with
+ | RISCV_LUI => returnm (off : mword 64)
+ | RISCV_AUIPC =>
+ (get_arch_pc tt) >>= fun w__0 : mword 64 => returnm ((add_vec w__0 off) : mword 64)
+ end) >>= fun ret : xlenbits =>
+ (wX (projT1 (regidx_to_regno rd)) ret) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_URET '(tt : unit)
+: M (Retired) :=
+
+ (haveUsrMode tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool ((negb w__0)) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (exception_handler w__1 (CTL_URET (tt)) w__2) >>= fun w__3 : mword 64 =>
+ (set_next_pc w__3)
+ : M (unit)) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_STORECON
+(aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5)
+: M (Retired) :=
+
+ (speculate_conditional tt) >>= fun w__0 : bool =>
+ (if ((Bool.eqb w__0 false)) then
+ (wX (projT1 (regidx_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else
+ (haveAtomics tt) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (ext_data_get_addr rs1 (zeros_implicit 64) Write width) >>= fun w__2 : Ext_DataAddr_Check unit =>
+ (match w__2 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (match width with
+ | BYTE =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | HALF =>
+ (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__3 : mword 1 =>
+ returnm ((eq_vec w__3 (vec_of_bits [B0] : mword 1))
+ : bool)
+ | WORD =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ : bool)
+ | DOUBLE =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 2 0)
+ (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))
+ : bool)
+ end) >>= fun aligned : bool =>
+ (if sumbool_of_bool ((negb aligned)) then
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else if ((Bool.eqb (match_reservation vaddr) false)) then
+ (wX (projT1 (regidx_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else
+ (translateAddr vaddr Write) >>= fun w__4 : TR_Result (mword 64) ExceptionType =>
+ (match w__4 with
+ | TR_Failure (e) =>
+ (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 64) with
+ | (WORD, g__217) => (mem_write_ea addr 4 aq rl true) : M (MemoryOpResult unit)
+ | (DOUBLE, l__4) =>
+ (if sumbool_of_bool ((Z.eqb l__4 64)) then
+ (mem_write_ea addr 8 aq rl true)
+ : M (MemoryOpResult unit)
+ else
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult unit))
+ : M (MemoryOpResult unit)
+ | _ =>
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ (match (width, 64) with
+ | (WORD, g__216) =>
+ (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl true)
+ : M (MemoryOpResult bool)
+ | (DOUBLE, l__3) =>
+ (if sumbool_of_bool ((Z.eqb l__3 64)) then
+ (mem_write_value addr 8 rs2_val aq rl true)
+ : M (MemoryOpResult bool)
+ else
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool)
+ | _ =>
+ (internal_error "STORECON expected word or double")
+ : M (MemoryOpResult bool)
+ end) >>= fun res : MemoryOpResult bool =>
+ (match res with
+ | MemValue (true) =>
+ (wX (projT1 (regidx_to_regno rd))
+ (EXTZ 64 (vec_of_bits [B0] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemValue (false) =>
+ (wX (projT1 (regidx_to_regno rd))
+ (EXTZ 64 (vec_of_bits [B1] : mword 1))) >>
+ let '_ := (cancel_reservation tt) : unit in
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired))
+ : M (Retired).
+
+Definition execute_STORE
+(imm : mword 12) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (aq : bool) (rl : bool)
+: M (Retired) :=
+
+ let offset : xlenbits := EXTS 64 imm in
+ (ext_data_get_addr rs1 offset Write width) >>= fun w__0 : Ext_DataAddr_Check unit =>
+ (match w__0 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (check_misaligned vaddr width) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Write) >>= fun w__2 : TR_Result (mword 64) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match width with
+ | BYTE => (mem_write_ea addr 1 aq rl false) : M (MemoryOpResult unit)
+ | HALF => (mem_write_ea addr 2 aq rl false) : M (MemoryOpResult unit)
+ | WORD => (mem_write_ea addr 4 aq rl false) : M (MemoryOpResult unit)
+ | DOUBLE => (mem_write_ea addr 8 aq rl false) : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ (match (width, 64) with
+ | (BYTE, g__210) =>
+ (mem_write_value addr 1 (subrange_vec_dec rs2_val 7 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | (HALF, g__211) =>
+ (mem_write_value addr 2 (subrange_vec_dec rs2_val 15 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | (WORD, g__212) =>
+ (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl false)
+ : M (MemoryOpResult bool)
+ | (DOUBLE, l__1) =>
+ (if sumbool_of_bool ((Z.eqb l__1 64)) then
+ (mem_write_value addr 8 rs2_val aq rl false)
+ : M (MemoryOpResult bool)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_insts_base.sail 394:47 - 399:15" >>= fun _ =>
+ exit tt)
+ : M (MemoryOpResult bool)
+ end) >>= fun res : MemoryOpResult bool =>
+ (match res with
+ | MemValue (true) => returnm (RETIRE_SUCCESS : Retired)
+ | MemValue (false) =>
+ (internal_error "store got false from mem_write_value") : M (Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_SRET '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (match w__0 with
+ | User => (handle_illegal tt) : M (unit)
+ | Supervisor =>
+ (or_boolM ((haveSupMode tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))
+ (read_reg mstatus_ref >>= fun w__2 : Mstatus =>
+ returnm ((eq_vec (_get_Mstatus_TSR w__2) ((bool_to_bits true) : mword 1))
+ : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__4 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__5 : mword 64 =>
+ (exception_handler w__4 (CTL_SRET (tt)) w__5) >>= fun w__6 : mword 64 =>
+ (set_next_pc w__6)
+ : M (unit))
+ : M (unit)
+ | Machine =>
+ (haveSupMode tt) >>= fun w__7 : bool =>
+ (if sumbool_of_bool ((negb w__7)) then (handle_illegal tt) : M (unit)
+ else
+ read_reg cur_privilege_ref >>= fun w__8 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__9 : mword 64 =>
+ (exception_handler w__8 (CTL_SRET (tt)) w__9) >>= fun w__10 : mword 64 =>
+ (set_next_pc w__10)
+ : M (unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_SHIFTW (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ let rs1_val := subrange_vec_dec w__0 31 0 in
+ let result : bits 32 :=
+ match op with
+ | RISCV_SLLI => shift_bits_left rs1_val shamt
+ | RISCV_SRLI => shift_bits_right rs1_val shamt
+ | RISCV_SRAI => shift_right_arith32 rs1_val shamt
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SHIFTIWOP (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sopw)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let result : bits 32 :=
+ match op with
+ | RISCV_SLLIW => shift_bits_left (subrange_vec_dec rs1_val 31 0) shamt
+ | RISCV_SRLIW => shift_bits_right (subrange_vec_dec rs1_val 31 0) shamt
+ | RISCV_SRAIW => shift_right_arith32 (subrange_vec_dec rs1_val 31 0) shamt
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SHIFTIOP (shamt : mword 6) (rs1 : mword 5) (rd : mword 5) (op : sop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let result : xlenbits :=
+ match op with
+ | RISCV_SLLI => shift_bits_left rs1_val shamt
+ | RISCV_SRLI => shift_bits_right rs1_val shamt
+ | RISCV_SRAI => shift_right_arith64 rs1_val shamt
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_SFENCE_VMA (rs1 : mword 5) (rs2 : mword 5)
+: M (Retired) :=
+
+ (if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then
+ returnm (None
+ : option (mword 64))
+ else
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ returnm ((Some
+ (w__0))
+ : option (mword 64))) >>= fun addr : option xlenbits =>
+ (if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then
+ returnm (None
+ : option (mword 64))
+ else
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__1 : mword 64 =>
+ returnm ((Some
+ (w__1))
+ : option (mword 64))) >>= fun asid : option xlenbits =>
+ read_reg cur_privilege_ref >>= fun w__2 : Privilege =>
+ (match w__2 with
+ | User => (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ | Supervisor =>
+ read_reg mstatus_ref >>= fun w__3 : Mstatus =>
+ read_reg mstatus_ref >>= fun w__4 : Mstatus =>
+ let p__214 := (architecture (get_mstatus_SXL w__3), _get_Mstatus_TVM w__4) in
+ (match p__214 with
+ | (Some (g__213), v_0) =>
+ (if ((eq_vec v_0 ((bool_to_bits true) : mword 1))) then
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else if ((eq_vec v_0 ((bool_to_bits false) : mword 1))) then
+ (flush_TLB asid addr) >> returnm (RETIRE_SUCCESS : Retired)
+ else
+ (match (Some
+ (g__213), v_0) with
+ | (_, _) => (internal_error "unimplemented sfence architecture") : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ | (_, _) => (internal_error "unimplemented sfence architecture") : M (Retired)
+ end)
+ : M (Retired)
+ | Machine => (flush_TLB asid addr) >> returnm (RETIRE_SUCCESS : Retired)
+ end)
+ : M (Retired).
+
+Definition execute_RTYPEW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : ropw)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ let rs1_val := subrange_vec_dec w__0 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__1 : mword 64 =>
+ let rs2_val := subrange_vec_dec w__1 31 0 in
+ let result : bits 32 :=
+ match op with
+ | RISCV_ADDW => add_vec rs1_val rs2_val
+ | RISCV_SUBW => sub_vec rs1_val rs2_val
+ | RISCV_SLLW => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SRLW => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0)
+ | RISCV_SRAW => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0)
+ end in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 result)) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_RTYPE (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : rop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let result : xlenbits :=
+ match op with
+ | RISCV_ADD => add_vec rs1_val rs2_val
+ | RISCV_SLT => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val rs2_val))
+ | RISCV_SLTU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val rs2_val))
+ | RISCV_AND => and_vec rs1_val rs2_val
+ | RISCV_OR => or_vec rs1_val rs2_val
+ | RISCV_XOR => xor_vec rs1_val rs2_val
+ | RISCV_SLL => shift_bits_left rs1_val (subrange_vec_dec rs2_val 5 0)
+ | RISCV_SRL => shift_bits_right rs1_val (subrange_vec_dec rs2_val 5 0)
+ | RISCV_SUB => sub_vec rs1_val rs2_val
+ | RISCV_SRA => shift_right_arith64 rs1_val (subrange_vec_dec rs2_val 5 0)
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_RISCV_JALR (imm : mword 12) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ let t : xlenbits := add_vec w__0 (EXTS 64 imm) in
+ (match (ext_control_check_addr t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (addr) =>
+ let target := update_vec_dec addr 0 B0 in
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (get_next_pc tt) >>= fun w__4 : mword 64 =>
+ (wX (projT1 (regidx_to_regno rd)) w__4) >>
+ (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_RISCV_JAL (imm : mword 21) (rd : mword 5)
+: M (Retired) :=
+
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ let t : xlenbits := add_vec w__0 (EXTS 64 imm) in
+ (match (ext_control_check_pc t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (target) =>
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (get_next_pc tt) >>= fun w__4 : mword 64 =>
+ (wX (projT1 (regidx_to_regno rd)) w__4) >>
+ (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_REMW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 64 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 64 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let r : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int else Z.rem rs1_int rs2_int in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 (to_bits 32 r))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_REM (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let r : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int else Z.rem rs1_int rs2_int in
+ (wX (projT1 (regidx_to_regno rd)) (to_bits 64 r)) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MULW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 64 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 64 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z := projT1 (sint rs1_val) in
+ let rs2_int : Z := projT1 (sint rs2_val) in
+ let result32 := subrange_vec_dec (to_bits 64 (Z.mul rs1_int rs2_int)) 31 0 in
+ let result : xlenbits := EXTS 64 result32 in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MUL
+(rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (high : bool) (signed1 : bool) (signed2 : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (signed1) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (signed2) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let result_wide := to_bits (Z.mul 2 64) (Z.mul rs1_int rs2_int) in
+ let result :=
+ if sumbool_of_bool (high) then subrange_vec_dec result_wide (Z.sub (Z.mul 2 64) 1) 64
+ else subrange_vec_dec result_wide (Z.sub 64 1) 0 in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_MRET '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits Machine) : mword 2))) then
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (exception_handler w__1 (CTL_MRET (tt)) w__2) >>= fun w__3 : mword 64 =>
+ (set_next_pc w__3)
+ : M (unit)
+ else (handle_illegal tt) : M (unit)) >>
+ returnm (RETIRE_FAIL
+ : Retired).
+
+Definition execute_LOADRES
+(aq : bool) (rl : bool) (rs1 : mword 5) (width : word_width) (rd : mword 5)
+: M (Retired) :=
+
+ (haveAtomics tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (ext_data_get_addr rs1 (zeros_implicit 64) Read width) >>= fun w__1 : Ext_DataAddr_Check unit =>
+ (match w__1 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (match width with
+ | BYTE => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | HALF =>
+ (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__2 : mword 1 =>
+ returnm ((eq_vec w__2 (vec_of_bits [B0] : mword 1))
+ : bool)
+ | WORD =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ : bool)
+ | DOUBLE =>
+ returnm ((eq_vec (subrange_vec_dec vaddr 2 0)
+ (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))
+ : bool)
+ end) >>= fun aligned : bool =>
+ (if sumbool_of_bool ((negb aligned)) then
+ (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Read) >>= fun w__3 : TR_Result (mword 64) ExceptionType =>
+ (match w__3 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 64) with
+ | (WORD, g__215) =>
+ (mem_read Read addr 4 aq rl true) >>= fun w__4 : MemoryOpResult (mword (8 * 4)) =>
+ (process_loadres rd vaddr w__4 false)
+ : M (Retired)
+ | (DOUBLE, l__2) =>
+ (if sumbool_of_bool ((Z.eqb l__2 64)) then
+ (mem_read Read addr 8 aq rl true) >>= fun w__6 : MemoryOpResult (mword (8 * 8)) =>
+ (process_loadres rd vaddr w__6 false)
+ : M (Retired)
+ else (internal_error "LOADRES expected WORD or DOUBLE") : M (Retired))
+ : M (Retired)
+ | _ => (internal_error "LOADRES expected WORD or DOUBLE") : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_LOAD
+(imm : mword 12) (rs1 : mword 5) (rd : mword 5) (is_unsigned : bool) (width : word_width)
+(aq : bool) (rl : bool)
+: M (Retired) :=
+
+ let offset : xlenbits := EXTS 64 imm in
+ (ext_data_get_addr rs1 offset Read width) >>= fun w__0 : Ext_DataAddr_Check unit =>
+ (match w__0 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (check_misaligned vaddr width) >>= fun w__1 : bool =>
+ (if sumbool_of_bool (w__1) then
+ (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (translateAddr vaddr Read) >>= fun w__2 : TR_Result (mword 64) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 64) with
+ | (BYTE, g__207) =>
+ (mem_read Read addr 1 aq rl false) >>= fun w__3 : MemoryOpResult (mword (8 * 1)) =>
+ (process_load rd vaddr w__3 is_unsigned)
+ : M (Retired)
+ | (HALF, g__208) =>
+ (mem_read Read addr 2 aq rl false) >>= fun w__5 : MemoryOpResult (mword (8 * 2)) =>
+ (process_load rd vaddr w__5 is_unsigned)
+ : M (Retired)
+ | (WORD, g__209) =>
+ (mem_read Read addr 4 aq rl false) >>= fun w__7 : MemoryOpResult (mword (8 * 4)) =>
+ (process_load rd vaddr w__7 is_unsigned)
+ : M (Retired)
+ | (DOUBLE, l__0) =>
+ (if sumbool_of_bool ((Z.eqb l__0 64)) then
+ (mem_read Read addr 8 aq rl false) >>= fun w__9 : MemoryOpResult (mword (8 * 8)) =>
+ (process_load rd vaddr w__9 is_unsigned)
+ : M (Retired)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_insts_base.sail 329:10 - 338:11" >>= fun _ =>
+ exit tt)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired))
+ : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute_ITYPE (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (op : iop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ let immext : xlenbits := EXTS 64 imm in
+ let result : xlenbits :=
+ match op with
+ | RISCV_ADDI => add_vec rs1_val immext
+ | RISCV_SLTI => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val immext))
+ | RISCV_SLTIU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val immext))
+ | RISCV_ANDI => and_vec rs1_val immext
+ | RISCV_ORI => or_vec rs1_val immext
+ | RISCV_XORI => xor_vec rs1_val immext
+ end in
+ (wX (projT1 (regidx_to_regno rd)) result) >> returnm (RETIRE_SUCCESS : Retired).
+
+Definition execute_ILLEGAL (s : mword 32)
+: M (Retired) :=
+
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_FENCE_TSO (pred : mword 4) (succ : mword 4)
+: M (Retired) :=
+
+ (match (pred, succ) with
+ | (v__794, v__795) =>
+ (if ((andb (eq_vec (subrange_vec_dec v__794 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__795 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_tso (tt)))
+ : M (unit)
+ else
+ returnm ((if ((andb
+ (eq_vec (subrange_vec_dec v__794 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__795 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then
+ tt
+ else
+ let '_ := (print_endline "FIXME: unsupported fence") : unit in
+ tt)
+ : unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition execute_FENCEI '(tt : unit) : Retired := RETIRE_SUCCESS.
+
+Definition execute_FENCE (pred : mword 4) (succ : mword 4)
+: M (Retired) :=
+
+ (match (pred, succ) with
+ | (v__754, v__755) =>
+ (if ((andb (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_r (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_rw (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_rw_r (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_r_w (tt)))
+ : M (unit)
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))
+ then
+ (barrier (Barrier_RISCV_w_r (tt)))
+ : M (unit)
+ else
+ returnm ((if ((andb
+ (eq_vec (subrange_vec_dec v__754 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__755 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then
+ tt
+ else
+ let '_ := (print_endline "FIXME: unsupported fence") : unit in
+ tt)
+ : unit))
+ : M (unit)
+ end) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition execute_ECALL '(tt : unit)
+: M (Retired) :=
+
+ read_reg cur_privilege_ref >>= fun w__0 : Privilege =>
+ let t : sync_exception :=
+ {| sync_exception_trap :=
+ (match w__0 with
+ | User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ end);
+ sync_exception_excinfo := (None : option xlenbits);
+ sync_exception_ext := None |} in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : mword 64 =>
+ (exception_handler w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 =>
+ (set_next_pc w__3) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_EBREAK '(tt : unit)
+: M (Retired) :=
+
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ (handle_mem_exception w__0 E_Breakpoint) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_DIVW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__1 : mword 64 =>
+ let rs1_val := subrange_vec_dec w__1 31 0 in
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun w__2 : mword 64 =>
+ let rs2_val := subrange_vec_dec w__2 31 0 in
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) else Z.quot rs1_int rs2_int in
+ let q' : Z :=
+ if sumbool_of_bool ((andb s (Z.gtb q (Z.sub (projT1 (pow2 31)) 1)))) then Z.sub 0 (pow 2 31)
+ else q in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 (to_bits 32 q'))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_DIV (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool)
+: M (Retired) :=
+
+ (haveMulDiv tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let rs1_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs1_val)
+ else projT1 (uint rs1_val) in
+ let rs2_int : Z :=
+ if sumbool_of_bool (s) then projT1 (sint rs2_val)
+ else projT1 (uint rs2_val) in
+ let q : Z := if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) else Z.quot rs1_int rs2_int in
+ let q' : Z :=
+ if sumbool_of_bool ((andb s (Z.gtb q xlen_max_signed))) then xlen_min_signed
+ else q in
+ (wX (projT1 (regidx_to_regno rd)) (to_bits 64 q')) >> returnm (RETIRE_SUCCESS : Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_C_NOP '(tt : unit) : Retired := RETIRE_SUCCESS.
+
+Definition execute_C_ILLEGAL (s : mword 16)
+: M (Retired) :=
+
+ (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired).
+
+Definition execute_CSR (csr : mword 12) (rs1 : mword 5) (rd : mword 5) (is_imm : bool) (op : csrop)
+: M (Retired) :=
+
+ (if sumbool_of_bool (is_imm) then returnm ((EXTZ 64 rs1) : mword 64)
+ else (rX (projT1 (regidx_to_regno rs1))) : M (mword 64)) >>= fun rs1_val : xlenbits =>
+ let isWrite : bool :=
+ match op with
+ | CSRRW => true
+ | _ =>
+ if sumbool_of_bool (is_imm) then projT1 (neq_int (projT1 (uint rs1_val)) 0)
+ else projT1 (neq_int (projT1 (uint rs1)) 0)
+ end in
+ read_reg cur_privilege_ref >>= fun w__1 : Privilege =>
+ (check_CSR csr w__1 isWrite) >>= fun w__2 : bool =>
+ (if sumbool_of_bool ((negb w__2)) then (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired)
+ else
+ (readCSR csr) >>= fun csr_val =>
+ (if sumbool_of_bool (isWrite) then
+ let new_val : xlenbits :=
+ match op with
+ | CSRRW => rs1_val
+ | CSRRS => or_vec csr_val rs1_val
+ | CSRRC => and_vec csr_val (not_vec rs1_val)
+ end in
+ (writeCSR csr new_val)
+ : M (unit)
+ else returnm (tt : unit)) >>
+ (wX (projT1 (regidx_to_regno rd)) csr_val) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired).
+
+Definition execute_BTYPE (imm : mword 13) (rs2 : mword 5) (rs1 : mword 5) (op : bop)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun rs1_val =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val =>
+ let taken : bool :=
+ match op with
+ | RISCV_BEQ => eq_vec rs1_val rs2_val
+ | RISCV_BNE => neq_vec rs1_val rs2_val
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ end in
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ let t : xlenbits := add_vec w__0 (EXTS 64 imm) in
+ (if sumbool_of_bool (taken) then
+ (match (ext_control_check_pc t) with
+ | Ext_ControlAddr_Error (e) =>
+ let '_ := (ext_handle_control_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_ControlAddr_OK (target) =>
+ (and_boolM ((bit_to_bool (access_vec_dec target 1)) : M (bool))
+ ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool =>
+ (if sumbool_of_bool (w__3) then
+ (handle_mem_exception target E_Fetch_Addr_Align) >> returnm (RETIRE_FAIL : Retired)
+ else (set_next_pc target) >> returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired)
+ end)
+ : M (Retired)
+ else returnm (RETIRE_SUCCESS : Retired))
+ : M (Retired).
+
+Definition execute_AMO
+(op : amoop) (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width)
+(rd : mword 5)
+: M (Retired) :=
+
+ (haveAtomics tt) >>= fun w__0 : bool =>
+ (if sumbool_of_bool (w__0) then
+ (ext_data_get_addr rs1 (zeros_implicit 64) ReadWrite width) >>= fun w__1 : Ext_DataAddr_Check unit =>
+ (match w__1 with
+ | Ext_DataAddr_Error (e) =>
+ let '_ := (ext_handle_data_check_error e) : unit in
+ returnm (RETIRE_FAIL
+ : Retired)
+ | Ext_DataAddr_OK (vaddr) =>
+ (translateAddr vaddr ReadWrite) >>= fun w__2 : TR_Result (mword 64) ExceptionType =>
+ (match w__2 with
+ | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (RETIRE_FAIL : Retired)
+ | TR_Address (addr) =>
+ (match (width, 64) with
+ | (WORD, g__220) =>
+ (mem_write_ea addr 4 (andb aq rl) rl true) : M (MemoryOpResult unit)
+ | (DOUBLE, l__7) =>
+ (if sumbool_of_bool ((Z.eqb l__7 64)) then
+ (mem_write_ea addr 8 (andb aq rl) rl true)
+ : M (MemoryOpResult unit)
+ else (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit))
+ : M (MemoryOpResult unit)
+ | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit)
+ end) >>= fun eares : MemoryOpResult unit =>
+ (rX (projT1 (regidx_to_regno rs2))) >>= fun rs2_val : xlenbits =>
+ (match eares with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (_) =>
+ (match (width, 64) with
+ | (WORD, g__219) =>
+ (mem_read ReadWrite addr 4 aq (andb aq rl) true) >>= fun w__8 : MemoryOpResult (mword (8 * 4)) =>
+ returnm ((extend_value false w__8)
+ : MemoryOpResult (mword 64))
+ | (DOUBLE, l__6) =>
+ (if sumbool_of_bool ((Z.eqb l__6 64)) then
+ (mem_read ReadWrite addr 8 aq (andb aq rl) true) >>= fun w__9 : MemoryOpResult (mword (8 * 8)) =>
+ returnm ((extend_value false w__9)
+ : MemoryOpResult (mword 64))
+ else
+ (internal_error "AMO expected WORD or DOUBLE")
+ : M (MemoryOpResult (mword 64)))
+ : M (MemoryOpResult (mword 64))
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE")
+ : M (MemoryOpResult (mword 64))
+ end) >>= fun rval : MemoryOpResult xlenbits =>
+ (match rval with
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ | MemValue (loaded) =>
+ let result : xlenbits :=
+ match op with
+ | AMOSWAP => rs2_val
+ | AMOADD => add_vec rs2_val loaded
+ | AMOXOR => xor_vec rs2_val loaded
+ | AMOAND => and_vec rs2_val loaded
+ | AMOOR => or_vec rs2_val loaded
+ | AMOMIN =>
+ to_bits 64 (Z.min (projT1 (sint rs2_val)) (projT1 (sint loaded)))
+ | AMOMAX =>
+ to_bits 64 (Z.max (projT1 (sint rs2_val)) (projT1 (sint loaded)))
+ | AMOMINU =>
+ to_bits 64
+ (projT1
+ (min_nat (projT1 (uint rs2_val)) (projT1 (uint loaded))))
+ | AMOMAXU =>
+ to_bits 64
+ (projT1
+ (max_nat (projT1 (uint rs2_val)) (projT1 (uint loaded))))
+ end in
+ (match (width, 64) with
+ | (WORD, g__218) =>
+ (mem_write_value addr 4 (subrange_vec_dec result 31 0) (andb aq rl) rl
+ true)
+ : M (MemoryOpResult bool)
+ | (DOUBLE, l__5) =>
+ (if sumbool_of_bool ((Z.eqb l__5 64)) then
+ (mem_write_value addr 8 result (andb aq rl) rl true)
+ : M (MemoryOpResult bool)
+ else
+ (internal_error "AMO expected WORD or DOUBLE")
+ : M (MemoryOpResult bool))
+ : M (MemoryOpResult bool)
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult bool)
+ end) >>= fun wval : MemoryOpResult bool =>
+ (match wval with
+ | MemValue (true) =>
+ (wX (projT1 (regidx_to_regno rd)) loaded) >>
+ returnm (RETIRE_SUCCESS
+ : Retired)
+ | MemValue (false) =>
+ (internal_error "AMO got false from mem_write_value") : M (Retired)
+ | MemException (e) =>
+ (handle_mem_exception addr e) >> returnm (RETIRE_FAIL : Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ end)
+ : M (Retired)
+ else (handle_illegal tt) >> returnm (RETIRE_FAIL : Retired))
+ : M (Retired).
+
+Definition execute_ADDIW (imm : mword 12) (rs1 : mword 5) (rd : mword 5)
+: M (Retired) :=
+
+ (rX (projT1 (regidx_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ let result : xlenbits := add_vec (EXTS 64 imm) w__0 in
+ (wX (projT1 (regidx_to_regno rd)) (EXTS 64 (subrange_vec_dec result 31 0))) >>
+ returnm (RETIRE_SUCCESS
+ : Retired).
+
+Definition compressed_measure (instr : ast)
+: Z :=
+
+ match instr with
+ | C_ADDI4SPN ((rdc, nzimm)) => 1
+ | C_LW ((uimm, rsc, rdc)) => 1
+ | C_LD ((uimm, rsc, rdc)) => 1
+ | C_SW ((uimm, rsc1, rsc2)) => 1
+ | C_SD ((uimm, rsc1, rsc2)) => 1
+ | C_ADDI ((nzi, rsd)) => 1
+ | C_JAL (imm) => 1
+ | C_LI ((imm, rd)) => 1
+ | C_ADDI16SP (imm) => 1
+ | C_LUI ((imm, rd)) => 1
+ | C_SRLI ((shamt, rsd)) => 1
+ | C_SRAI ((shamt, rsd)) => 1
+ | C_ANDI ((imm, rsd)) => 1
+ | C_SUB ((rsd, rs2)) => 1
+ | C_XOR ((rsd, rs2)) => 1
+ | C_OR ((rsd, rs2)) => 1
+ | C_AND ((rsd, rs2)) => 1
+ | C_SUBW ((rsd, rs2)) => 1
+ | C_ADDW ((rsd, rs2)) => 1
+ | C_J (imm) => 1
+ | C_BEQZ ((imm, rs)) => 1
+ | C_BNEZ ((imm, rs)) => 1
+ | C_SLLI ((shamt, rsd)) => 1
+ | C_LWSP ((uimm, rd)) => 1
+ | C_LDSP ((uimm, rd)) => 1
+ | C_SWSP ((uimm, rs2)) => 1
+ | C_SDSP ((uimm, rs2)) => 1
+ | C_JR (rs1) => 1
+ | C_JALR (rs1) => 1
+ | C_MV ((rd, rs2)) => 1
+ | C_EBREAK (tt') => 1
+ | C_ADD ((rsd, rs2)) => 1
+ | _ => 0
+ end.
+
+Fixpoint _rec_execute (merge_var : ast) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M (Retired) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ (match merge_var with
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ let imm : bits 12 :=
+ concat_vec (vec_of_bits [B0;B0] : mword 2)
+ (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rd := creg2reg_idx rdc in
+ (_rec_execute (ITYPE ((imm, sp, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LW ((uimm, rsc, rdc)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rd := creg2reg_idx rdc in
+ let rs := creg2reg_idx rsc in
+ (_rec_execute (LOAD ((imm, rs, rd, false, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LD ((uimm, rsc, rdc)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ let rd := creg2reg_idx rdc in
+ let rs := creg2reg_idx rsc in
+ (_rec_execute (LOAD ((imm, rs, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ let rs1 := creg2reg_idx rsc1 in
+ let rs2 := creg2reg_idx rsc2 in
+ (_rec_execute (STORE ((imm, rs2, rs1, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ let rs1 := creg2reg_idx rsc1 in
+ let rs2 := creg2reg_idx rsc2 in
+ (_rec_execute (STORE ((imm, rs2, rs1, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDI ((nzi, rsd)) =>
+ let imm : bits 12 := EXTS 12 nzi in
+ (_rec_execute (ITYPE ((imm, rsd, rsd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_JAL (imm) =>
+ (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDIW ((imm, rsd)) =>
+ (_rec_execute (ADDIW ((EXTS 12 imm, rsd, rsd))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LI ((imm, rd)) =>
+ let imm : bits 12 := EXTS 12 imm in
+ (_rec_execute (ITYPE ((imm, zreg, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDI16SP (imm) =>
+ let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in
+ (_rec_execute (ITYPE ((imm, sp, sp, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_LUI ((imm, rd)) =>
+ let res : bits 20 := EXTS 20 imm in
+ (_rec_execute (UTYPE ((res, rd, RISCV_LUI))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SRLI ((shamt, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SRAI ((shamt, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ANDI ((imm, rsd)) =>
+ let rsd := creg2reg_idx rsd in
+ (_rec_execute (ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SUB ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_SUB))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_XOR ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_XOR))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_OR ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_OR))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_AND ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_AND))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SUBW ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_SUBW))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_ADDW ((rsd, rs2)) =>
+ let rsd := creg2reg_idx rsd in
+ let rs2 := creg2reg_idx rs2 in
+ (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_ADDW))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_J (imm) =>
+ (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_BEQZ ((imm, rs)) =>
+ (_rec_execute
+ (BTYPE
+ ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_idx rs, RISCV_BEQ)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_BNEZ ((imm, rs)) =>
+ (_rec_execute
+ (BTYPE
+ ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_idx rs, RISCV_BNE)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_SLLI ((shamt, rsd)) =>
+ (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LWSP ((uimm, rd)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ (_rec_execute (LOAD ((imm, sp, rd, false, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_LDSP ((uimm, rd)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ (_rec_execute (LOAD ((imm, sp, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SWSP ((uimm, rs2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in
+ (_rec_execute (STORE ((imm, rs2, sp, WORD, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_SDSP ((uimm, rs2)) =>
+ let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in
+ (_rec_execute (STORE ((imm, rs2, sp, DOUBLE, false, false))) (Z.sub _reclimit 1)
+ (_limit_reduces _acc))
+ : M (Retired)
+ | C_JR (rs1) =>
+ (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_JALR (rs1) =>
+ (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra)))
+ (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_MV ((rd, rs2)) =>
+ (_rec_execute (RTYPE ((rs2, zreg, rd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | C_EBREAK (tt) =>
+ (_rec_execute (EBREAK (tt)) (Z.sub _reclimit 1) (_limit_reduces _acc)) : M (Retired)
+ | C_ADD ((rsd, rs2)) =>
+ (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc))
+ : M (Retired)
+ | UTYPE ((imm, rd, op)) => (execute_UTYPE imm rd op) : M (Retired)
+ | RISCV_JAL ((imm, rd)) => (execute_RISCV_JAL imm rd) : M (Retired)
+ | BTYPE ((imm, rs2, rs1, op)) => (execute_BTYPE imm rs2 rs1 op) : M (Retired)
+ | ITYPE ((imm, rs1, rd, op)) => (execute_ITYPE imm rs1 rd op) : M (Retired)
+ | SHIFTIOP ((shamt, rs1, rd, op)) => (execute_SHIFTIOP shamt rs1 rd op) : M (Retired)
+ | RTYPE ((rs2, rs1, rd, op)) => (execute_RTYPE rs2 rs1 rd op) : M (Retired)
+ | LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl)) =>
+ (execute_LOAD imm rs1 rd is_unsigned width aq rl) : M (Retired)
+ | STORE ((imm, rs2, rs1, width, aq, rl)) =>
+ (execute_STORE imm rs2 rs1 width aq rl) : M (Retired)
+ | ADDIW ((imm, rs1, rd)) => (execute_ADDIW imm rs1 rd) : M (Retired)
+ | SHIFTW ((shamt, rs1, rd, op)) => (execute_SHIFTW shamt rs1 rd op) : M (Retired)
+ | RTYPEW ((rs2, rs1, rd, op)) => (execute_RTYPEW rs2 rs1 rd op) : M (Retired)
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => (execute_SHIFTIWOP shamt rs1 rd op) : M (Retired)
+ | FENCE ((pred, succ)) => (execute_FENCE pred succ) : M (Retired)
+ | FENCE_TSO ((pred, succ)) => (execute_FENCE_TSO pred succ) : M (Retired)
+ | FENCEI (arg0) => returnm ((execute_FENCEI arg0) : Retired)
+ | ECALL (arg0) => (execute_ECALL arg0) : M (Retired)
+ | MRET (arg0) => (execute_MRET arg0) : M (Retired)
+ | SRET (arg0) => (execute_SRET arg0) : M (Retired)
+ | EBREAK (arg0) => (execute_EBREAK arg0) : M (Retired)
+ | WFI (arg0) => (execute_WFI arg0) : M (Retired)
+ | SFENCE_VMA ((rs1, rs2)) => (execute_SFENCE_VMA rs1 rs2) : M (Retired)
+ | LOADRES ((aq, rl, rs1, width, rd)) => (execute_LOADRES aq rl rs1 width rd) : M (Retired)
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) =>
+ (execute_STORECON aq rl rs2 rs1 width rd) : M (Retired)
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ (execute_AMO op aq rl rs2 rs1 width rd) : M (Retired)
+ | C_NOP (arg0) => returnm ((execute_C_NOP arg0) : Retired)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (execute_MUL rs2 rs1 rd high signed1 signed2) : M (Retired)
+ | DIV ((rs2, rs1, rd, s)) => (execute_DIV rs2 rs1 rd s) : M (Retired)
+ | REM ((rs2, rs1, rd, s)) => (execute_REM rs2 rs1 rd s) : M (Retired)
+ | MULW ((rs2, rs1, rd)) => (execute_MULW rs2 rs1 rd) : M (Retired)
+ | DIVW ((rs2, rs1, rd, s)) => (execute_DIVW rs2 rs1 rd s) : M (Retired)
+ | REMW ((rs2, rs1, rd, s)) => (execute_REMW rs2 rs1 rd s) : M (Retired)
+ | CSR ((csr, rs1, rd, is_imm, op)) => (execute_CSR csr rs1 rd is_imm op) : M (Retired)
+ | URET (arg0) => (execute_URET arg0) : M (Retired)
+ | RISCV_JALR ((imm, rs1, rd)) => (execute_RISCV_JALR imm rs1 rd) : M (Retired)
+ | ILLEGAL (s) => (execute_ILLEGAL s) : M (Retired)
+ | C_ILLEGAL (s) => (execute_C_ILLEGAL s) : M (Retired)
+ end)
+ : M (Retired).
+
+Definition execute (i : ast)
+: M (Retired) :=
+
+ (_rec_execute i ((compressed_measure i) : Z) (Zwf_guarded _))
+ : M (Retired).
+
+Definition assembly_forwards (arg_ : ast)
+: M (string) :=
+
+ (match arg_ with
+ | UTYPE ((imm, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__0 : string =>
+ returnm ((string_append (utype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__0
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | RISCV_JAL ((imm, rd)) =>
+ (reg_name_forwards rd) >>= fun w__1 : string =>
+ returnm ((string_append "jal"
+ (string_append (spc_forwards tt)
+ (string_append w__1
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ (reg_name_forwards rd) >>= fun w__2 : string =>
+ (reg_name_forwards rs1) >>= fun w__3 : string =>
+ returnm ((string_append "jalr"
+ (string_append (spc_forwards tt)
+ (string_append w__2
+ (string_append (sep_forwards tt)
+ (string_append w__3
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | BTYPE ((imm, rs2, rs1, op)) =>
+ (reg_name_forwards rs1) >>= fun w__4 : string =>
+ (reg_name_forwards rs2) >>= fun w__5 : string =>
+ returnm ((string_append (btype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__4
+ (string_append (sep_forwards tt)
+ (string_append w__5
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | ITYPE ((imm, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__6 : string =>
+ (reg_name_forwards rs1) >>= fun w__7 : string =>
+ returnm ((string_append (itype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__6
+ (string_append (sep_forwards tt)
+ (string_append w__7
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ | SHIFTIOP ((shamt, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__8 : string =>
+ (reg_name_forwards rs1) >>= fun w__9 : string =>
+ returnm ((string_append (shiftiop_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__8
+ (string_append (sep_forwards tt)
+ (string_append w__9
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ | RTYPE ((rs2, rs1, rd, op)) =>
+ (reg_name_forwards rd) >>= fun w__10 : string =>
+ (reg_name_forwards rs1) >>= fun w__11 : string =>
+ (reg_name_forwards rs2) >>= fun w__12 : string =>
+ returnm ((string_append (rtype_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__10
+ (string_append (sep_forwards tt)
+ (string_append w__11
+ (string_append (sep_forwards tt) (string_append w__12 "")))))))
+ : string)
+ | LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl)) =>
+ (reg_name_forwards rd) >>= fun w__13 : string =>
+ (reg_name_forwards rs1) >>= fun w__14 : string =>
+ returnm ((string_append "l"
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_u_forwards is_unsigned)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__13
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm)
+ (string_append (opt_spc_forwards tt)
+ (string_append "("
+ (string_append (opt_spc_forwards tt)
+ (string_append w__14
+ (string_append (opt_spc_forwards tt)
+ (string_append ")" "")))))))))))))))
+ : string)
+ | STORE ((imm, rs2, rs1, size, aq, rl)) =>
+ (reg_name_forwards rs2) >>= fun w__15 : string =>
+ (reg_name_forwards rs1) >>= fun w__16 : string =>
+ returnm ((string_append "s"
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__15
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm)
+ (string_append (opt_spc_forwards tt)
+ (string_append "("
+ (string_append (opt_spc_forwards tt)
+ (string_append w__16
+ (string_append (opt_spc_forwards tt)
+ (string_append ")" ""))))))))))))))
+ : string)
+ | ADDIW ((imm, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__17 : string =>
+ (reg_name_forwards rs1) >>= fun w__18 : string =>
+ returnm ((string_append "addiw"
+ (string_append (spc_forwards tt)
+ (string_append w__17
+ (string_append (sep_forwards tt)
+ (string_append w__18
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__21 : string =>
+ (reg_name_forwards rs1) >>= fun w__22 : string =>
+ returnm ((string_append (shiftw_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__21
+ (string_append (sep_forwards tt)
+ (string_append w__22
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__25 : string =>
+ (reg_name_forwards rs1) >>= fun w__26 : string =>
+ (reg_name_forwards rs2) >>= fun w__27 : string =>
+ returnm ((string_append (rtypew_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__25
+ (string_append (sep_forwards tt)
+ (string_append w__26
+ (string_append (sep_forwards tt) (string_append w__27 "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__30 : string =>
+ (reg_name_forwards rs1) >>= fun w__31 : string =>
+ returnm ((string_append (shiftiwop_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__30
+ (string_append (sep_forwards tt)
+ (string_append w__31
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | FENCE ((pred, succ)) =>
+ (fence_bits_forwards pred) >>= fun w__34 : string =>
+ (fence_bits_forwards succ) >>= fun w__35 : string =>
+ returnm ((string_append "fence"
+ (string_append (spc_forwards tt)
+ (string_append w__34
+ (string_append (sep_forwards tt) (string_append w__35 "")))))
+ : string)
+ | FENCE_TSO ((pred, succ)) =>
+ (fence_bits_forwards pred) >>= fun w__36 : string =>
+ (fence_bits_forwards succ) >>= fun w__37 : string =>
+ returnm ((string_append "fence.tso"
+ (string_append (spc_forwards tt)
+ (string_append w__36
+ (string_append (sep_forwards tt) (string_append w__37 "")))))
+ : string)
+ | FENCEI (tt) => returnm ("fence.i" : string)
+ | ECALL (tt) => returnm ("ecall" : string)
+ | MRET (tt) => returnm ("mret" : string)
+ | SRET (tt) => returnm ("sret" : string)
+ | EBREAK (tt) => returnm ("ebreak" : string)
+ | WFI (tt) => returnm ("wfi" : string)
+ | SFENCE_VMA ((rs1, rs2)) =>
+ (reg_name_forwards rs1) >>= fun w__38 : string =>
+ (reg_name_forwards rs2) >>= fun w__39 : string =>
+ returnm ((string_append "sfence.vma"
+ (string_append (spc_forwards tt)
+ (string_append w__38
+ (string_append (sep_forwards tt) (string_append w__39 "")))))
+ : string)
+ | LOADRES ((aq, rl, rs1, size, rd)) =>
+ (reg_name_forwards rd) >>= fun w__40 : string =>
+ (reg_name_forwards rs1) >>= fun w__41 : string =>
+ returnm ((string_append "lr."
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__40
+ (string_append (sep_forwards tt) (string_append w__41 ""))))))))
+ : string)
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) =>
+ (reg_name_forwards rd) >>= fun w__42 : string =>
+ (reg_name_forwards rs1) >>= fun w__43 : string =>
+ (reg_name_forwards rs2) >>= fun w__44 : string =>
+ returnm ((string_append "sc."
+ (string_append (size_mnemonic_forwards size)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__42
+ (string_append (sep_forwards tt)
+ (string_append w__43
+ (string_append (sep_forwards tt) (string_append w__44 ""))))))))))
+ : string)
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ (reg_name_forwards rd) >>= fun w__45 : string =>
+ (reg_name_forwards rs1) >>= fun w__46 : string =>
+ (reg_name_forwards rs2) >>= fun w__47 : string =>
+ returnm ((string_append (amo_mnemonic_forwards op)
+ (string_append "."
+ (string_append (size_mnemonic_forwards width)
+ (string_append (maybe_aq_forwards aq)
+ (string_append (maybe_rl_forwards rl)
+ (string_append (spc_forwards tt)
+ (string_append w__45
+ (string_append (sep_forwards tt)
+ (string_append w__46
+ (string_append (sep_forwards tt) (string_append w__47 "")))))))))))
+ : string)
+ | C_NOP (tt) => returnm ("c.nop" : string)
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ (if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then
+ (creg_name_forwards rdc) >>= fun w__48 : string =>
+ returnm ((string_append "c.addi4spn"
+ (string_append (spc_forwards tt)
+ (string_append w__48
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (nzimm : mword 8) (vec_of_bits [B0;B0] : mword 2)))
+ "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LW ((uimm, rsc, rdc)) =>
+ (creg_name_forwards rdc) >>= fun w__51 : string =>
+ (creg_name_forwards rsc) >>= fun w__52 : string =>
+ returnm ((string_append "c.lw"
+ (string_append (spc_forwards tt)
+ (string_append w__51
+ (string_append (sep_forwards tt)
+ (string_append w__52
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0] : mword 2))) "")))))))
+ : string)
+ | C_LD ((uimm, rsc, rdc)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (creg_name_forwards rdc) >>= fun w__53 : string =>
+ (creg_name_forwards rsc) >>= fun w__54 : string =>
+ returnm ((string_append "c.ld"
+ (string_append (spc_forwards tt)
+ (string_append w__53
+ (string_append (sep_forwards tt)
+ (string_append w__54
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0;B0] : mword 3))) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ (creg_name_forwards rsc1) >>= fun w__57 : string =>
+ (creg_name_forwards rsc2) >>= fun w__58 : string =>
+ returnm ((string_append "c.sw"
+ (string_append (spc_forwards tt)
+ (string_append w__57
+ (string_append (sep_forwards tt)
+ (string_append w__58
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0] : mword 2))) "")))))))
+ : string)
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (creg_name_forwards rsc1) >>= fun w__59 : string =>
+ (creg_name_forwards rsc2) >>= fun w__60 : string =>
+ returnm ((string_append "c.sd"
+ (string_append (spc_forwards tt)
+ (string_append w__59
+ (string_append (sep_forwards tt)
+ (string_append w__60
+ (string_append (sep_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (uimm : mword 5)
+ (vec_of_bits [B0;B0;B0] : mword 3))) "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDI ((nzi, rsd)) =>
+ (if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__63 : string =>
+ returnm ((string_append "c.addi"
+ (string_append (spc_forwards tt)
+ (string_append w__63
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits nzi) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JAL (imm) =>
+ (if sumbool_of_bool ((Z.eqb 64 32)) then
+ returnm ((string_append "c.jal"
+ (string_append (spc_forwards tt)
+ (string_append
+ (decimal_string_of_bits
+ (concat_vec (imm : mword 11) (vec_of_bits [B0] : mword 1))) "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDIW ((imm, rsd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rsd) >>= fun w__68 : string =>
+ returnm ((string_append "c.addiw"
+ (string_append (spc_forwards tt)
+ (string_append w__68
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LI ((imm, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rd) >>= fun w__71 : string =>
+ returnm ((string_append "c.li"
+ (string_append (spc_forwards tt)
+ (string_append w__71
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDI16SP (imm) =>
+ (if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ returnm ((string_append "c.addi16sp"
+ (string_append (spc_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LUI ((imm, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))
+ : bool))) then
+ (reg_name_forwards rd) >>= fun w__76 : string =>
+ returnm ((string_append "c.lui"
+ (string_append (spc_forwards tt)
+ (string_append w__76
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SRLI ((shamt, rsd)) =>
+ (if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ (creg_name_forwards rsd) >>= fun w__79 : string =>
+ returnm ((string_append "c.srli"
+ (string_append (spc_forwards tt)
+ (string_append w__79
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SRAI ((shamt, rsd)) =>
+ (if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then
+ (creg_name_forwards rsd) >>= fun w__82 : string =>
+ returnm ((string_append "c.srai"
+ (string_append (spc_forwards tt)
+ (string_append w__82
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ANDI ((imm, rsd)) =>
+ (creg_name_forwards rsd) >>= fun w__85 : string =>
+ returnm ((string_append "c.andi"
+ (string_append (spc_forwards tt)
+ (string_append w__85
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_SUB ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__86 : string =>
+ (creg_name_forwards rs2) >>= fun w__87 : string =>
+ returnm ((string_append "c.sub"
+ (string_append (spc_forwards tt)
+ (string_append w__86
+ (string_append (sep_forwards tt) (string_append w__87 "")))))
+ : string)
+ | C_XOR ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__88 : string =>
+ (creg_name_forwards rs2) >>= fun w__89 : string =>
+ returnm ((string_append "c.xor"
+ (string_append (spc_forwards tt)
+ (string_append w__88
+ (string_append (sep_forwards tt) (string_append w__89 "")))))
+ : string)
+ | C_OR ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__90 : string =>
+ (creg_name_forwards rs2) >>= fun w__91 : string =>
+ returnm ((string_append "c.or"
+ (string_append (spc_forwards tt)
+ (string_append w__90
+ (string_append (sep_forwards tt) (string_append w__91 "")))))
+ : string)
+ | C_AND ((rsd, rs2)) =>
+ (creg_name_forwards rsd) >>= fun w__92 : string =>
+ (creg_name_forwards rs2) >>= fun w__93 : string =>
+ returnm ((string_append "c.and"
+ (string_append (spc_forwards tt)
+ (string_append w__92
+ (string_append (sep_forwards tt) (string_append w__93 "")))))
+ : string)
+ | C_SUBW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (creg_name_forwards rsd) >>= fun w__94 : string =>
+ (creg_name_forwards rs2) >>= fun w__95 : string =>
+ returnm ((string_append "c.subw"
+ (string_append (spc_forwards tt)
+ (string_append w__94
+ (string_append (sep_forwards tt) (string_append w__95 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_ADDW ((rsd, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (creg_name_forwards rsd) >>= fun w__98 : string =>
+ (creg_name_forwards rs2) >>= fun w__99 : string =>
+ returnm ((string_append "c.addw"
+ (string_append (spc_forwards tt)
+ (string_append w__98
+ (string_append (sep_forwards tt) (string_append w__99 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_J (imm) =>
+ returnm ((string_append "c.j"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) "")))
+ : string)
+ | C_BEQZ ((imm, rs)) =>
+ (creg_name_forwards rs) >>= fun w__102 : string =>
+ returnm ((string_append "c.beqz"
+ (string_append (spc_forwards tt)
+ (string_append w__102
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_BNEZ ((imm, rs)) =>
+ (creg_name_forwards rs) >>= fun w__103 : string =>
+ returnm ((string_append "c.bnez"
+ (string_append (spc_forwards tt)
+ (string_append w__103
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits imm) "")))))
+ : string)
+ | C_SLLI ((shamt, rsd)) =>
+ (if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__104 : string =>
+ returnm ((string_append "c.slli"
+ (string_append (spc_forwards tt)
+ (string_append w__104
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits shamt) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LWSP ((uimm, rd)) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rd) >>= fun w__107 : string =>
+ returnm ((string_append "c.lwsp"
+ (string_append (spc_forwards tt)
+ (string_append w__107
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_LDSP ((uimm, rd)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg)))) (Z.eqb 64 64))) then
+ (reg_name_forwards rd) >>= fun w__110 : string =>
+ returnm ((string_append "c.ldsp"
+ (string_append (spc_forwards tt)
+ (string_append w__110
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_SWSP ((uimm, rd)) =>
+ (reg_name_forwards rd) >>= fun w__113 : string =>
+ returnm ((string_append "c.swsp"
+ (string_append (spc_forwards tt)
+ (string_append w__113
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ | C_SDSP ((uimm, rs2)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rs2) >>= fun w__114 : string =>
+ returnm ((string_append "c.sdsp"
+ (string_append (spc_forwards tt)
+ (string_append w__114
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits uimm) "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rs1) >>= fun w__117 : string =>
+ returnm ((string_append "c.jr" (string_append (spc_forwards tt) (string_append w__117 "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_JALR (rs1) =>
+ (if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ (reg_name_forwards rs1) >>= fun w__120 : string =>
+ returnm ((string_append "c.jalr"
+ (string_append (spc_forwards tt) (string_append w__120 "")))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_MV ((rd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rd) >>= fun w__123 : string =>
+ (reg_name_forwards rs2) >>= fun w__124 : string =>
+ returnm ((string_append "c.mv"
+ (string_append (spc_forwards tt)
+ (string_append w__123
+ (string_append (sep_forwards tt) (string_append w__124 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | C_EBREAK (tt) => returnm ("c.ebreak" : string)
+ | C_ADD ((rsd, rs2)) =>
+ (if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ (reg_name_forwards rsd) >>= fun w__127 : string =>
+ (reg_name_forwards rs2) >>= fun w__128 : string =>
+ returnm ((string_append "c.add"
+ (string_append (spc_forwards tt)
+ (string_append w__127
+ (string_append (sep_forwards tt) (string_append w__128 "")))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ (mul_mnemonic_forwards (high, signed1, signed2)) >>= fun w__131 : string =>
+ (reg_name_forwards rd) >>= fun w__132 : string =>
+ (reg_name_forwards rs1) >>= fun w__133 : string =>
+ (reg_name_forwards rs2) >>= fun w__134 : string =>
+ returnm ((string_append w__131
+ (string_append (spc_forwards tt)
+ (string_append w__132
+ (string_append (sep_forwards tt)
+ (string_append w__133
+ (string_append (sep_forwards tt) (string_append w__134 "")))))))
+ : string)
+ | DIV ((rs2, rs1, rd, s)) =>
+ (reg_name_forwards rd) >>= fun w__135 : string =>
+ (reg_name_forwards rs1) >>= fun w__136 : string =>
+ (reg_name_forwards rs2) >>= fun w__137 : string =>
+ returnm ((string_append "div"
+ (string_append (maybe_not_u_forwards s)
+ (string_append (spc_forwards tt)
+ (string_append w__135
+ (string_append (sep_forwards tt)
+ (string_append w__136
+ (string_append (sep_forwards tt) (string_append w__137 ""))))))))
+ : string)
+ | REM ((rs2, rs1, rd, s)) =>
+ (reg_name_forwards rd) >>= fun w__138 : string =>
+ (reg_name_forwards rs1) >>= fun w__139 : string =>
+ (reg_name_forwards rs2) >>= fun w__140 : string =>
+ returnm ((string_append "rem"
+ (string_append (maybe_not_u_forwards s)
+ (string_append (spc_forwards tt)
+ (string_append w__138
+ (string_append (sep_forwards tt)
+ (string_append w__139
+ (string_append (sep_forwards tt) (string_append w__140 ""))))))))
+ : string)
+ | MULW ((rs2, rs1, rd)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__141 : string =>
+ (reg_name_forwards rs1) >>= fun w__142 : string =>
+ (reg_name_forwards rs2) >>= fun w__143 : string =>
+ returnm ((string_append "mulw"
+ (string_append (spc_forwards tt)
+ (string_append w__141
+ (string_append (sep_forwards tt)
+ (string_append w__142
+ (string_append (sep_forwards tt) (string_append w__143 "")))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | DIVW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__146 : string =>
+ (reg_name_forwards rs1) >>= fun w__147 : string =>
+ (reg_name_forwards rs2) >>= fun w__148 : string =>
+ returnm ((string_append "div"
+ (string_append (maybe_not_u_forwards s)
+ (string_append "w"
+ (string_append (spc_forwards tt)
+ (string_append w__146
+ (string_append (sep_forwards tt)
+ (string_append w__147
+ (string_append (sep_forwards tt) (string_append w__148 "")))))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | REMW ((rs2, rs1, rd, s)) =>
+ (if sumbool_of_bool ((Z.eqb 64 64)) then
+ (reg_name_forwards rd) >>= fun w__151 : string =>
+ (reg_name_forwards rs1) >>= fun w__152 : string =>
+ (reg_name_forwards rs2) >>= fun w__153 : string =>
+ returnm ((string_append "rem"
+ (string_append (maybe_not_u_forwards s)
+ (string_append "w"
+ (string_append (spc_forwards tt)
+ (string_append w__151
+ (string_append (sep_forwards tt)
+ (string_append w__152
+ (string_append (sep_forwards tt) (string_append w__153 "")))))))))
+ : string)
+ else assert_exp' false "Pattern match failure at unknown location" >>= fun _ => exit tt)
+ : M (string)
+ | CSR ((csr, rs1, rd, true, op)) =>
+ (reg_name_forwards rd) >>= fun w__156 : string =>
+ (csr_name_map_forwards csr) >>= fun w__157 : string =>
+ returnm ((string_append (csr_mnemonic_forwards op)
+ (string_append "i"
+ (string_append (spc_forwards tt)
+ (string_append w__156
+ (string_append (sep_forwards tt)
+ (string_append (decimal_string_of_bits rs1)
+ (string_append (sep_forwards tt) (string_append w__157 ""))))))))
+ : string)
+ | CSR ((csr, rs1, rd, false, op)) =>
+ (reg_name_forwards rd) >>= fun w__158 : string =>
+ (reg_name_forwards rs1) >>= fun w__159 : string =>
+ (csr_name_map_forwards csr) >>= fun w__160 : string =>
+ returnm ((string_append (csr_mnemonic_forwards op)
+ (string_append (spc_forwards tt)
+ (string_append w__158
+ (string_append (sep_forwards tt)
+ (string_append w__159
+ (string_append (sep_forwards tt) (string_append w__160 "")))))))
+ : string)
+ | URET (tt) => returnm ("uret" : string)
+ | ILLEGAL (s) =>
+ returnm ((string_append "illegal"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) "")))
+ : string)
+ | C_ILLEGAL (s) =>
+ returnm ((string_append "c.illegal"
+ (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) "")))
+ : string)
+ end)
+ : M (string).
+
+Definition _s1677_ (_s1678_ : string)
+: M (option (mword 16)) :=
+
+ let _s1679_ := _s1678_ in
+ (if ((string_startswith _s1679_ "c.illegal")) then
+ (match (string_drop _s1679_ (projT1 (string_length "c.illegal"))) with
+ | _s1680_ =>
+ (spc_matches_prefix _s1680_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1681_ _)) =>
+ match (string_drop _s1680_ _s1681_) with
+ | _s1682_ =>
+ match (hex_bits_16_matches_prefix _s1682_) with
+ | Some ((s, existT _ _s1683_ _)) =>
+ let p0_ := string_drop _s1682_ _s1683_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 16))
+ end)
+ : M (option (mword 16))
+ else returnm (None : option (mword 16)))
+ : M (option (mword 16)).
+
+Definition _s1669_ (_s1670_ : string)
+: M (option (mword 32)) :=
+
+ let _s1671_ := _s1670_ in
+ (if ((string_startswith _s1671_ "illegal")) then
+ (match (string_drop _s1671_ (projT1 (string_length "illegal"))) with
+ | _s1672_ =>
+ (spc_matches_prefix _s1672_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1673_ _)) =>
+ match (string_drop _s1672_ _s1673_) with
+ | _s1674_ =>
+ match (hex_bits_32_matches_prefix _s1674_) with
+ | Some ((s, existT _ _s1675_ _)) =>
+ let p0_ := string_drop _s1674_ _s1675_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 32))
+ end)
+ : M (option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option (mword 32)).
+
+Definition _s1652_ (_s1653_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1653_ with
+ | _s1654_ =>
+ (csr_mnemonic_matches_prefix _s1654_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1655_ _)) =>
+ (match (string_drop _s1654_ _s1655_) with
+ | _s1656_ =>
+ (spc_matches_prefix _s1656_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1657_ _)) =>
+ (match (string_drop _s1656_ _s1657_) with
+ | _s1658_ =>
+ (reg_name_matches_prefix _s1658_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1659_ _)) =>
+ (match (string_drop _s1658_ _s1659_) with
+ | _s1660_ =>
+ (sep_matches_prefix _s1660_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1661_ _)) =>
+ (match (string_drop _s1660_ _s1661_) with
+ | _s1662_ =>
+ (reg_name_matches_prefix _s1662_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1663_ _)) =>
+ (match (string_drop _s1662_ _s1663_) with
+ | _s1664_ =>
+ (sep_matches_prefix _s1664_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1665_ _)) =>
+ (match (string_drop _s1664_ _s1665_) with
+ | _s1666_ =>
+ (csr_name_map_matches_prefix _s1666_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s1667_ _)) =>
+ let p0_ :=
+ string_drop _s1666_ _s1667_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1634_ (_s1635_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1635_ with
+ | _s1636_ =>
+ (csr_mnemonic_matches_prefix _s1636_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1637_ _)) =>
+ let _s1638_ := string_drop _s1636_ _s1637_ in
+ (if ((string_startswith _s1638_ "i")) then
+ (match (string_drop _s1638_ (projT1 (string_length "i"))) with
+ | _s1639_ =>
+ (spc_matches_prefix _s1639_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1640_ _)) =>
+ (match (string_drop _s1639_ _s1640_) with
+ | _s1641_ =>
+ (reg_name_matches_prefix _s1641_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1642_ _)) =>
+ (match (string_drop _s1641_ _s1642_) with
+ | _s1643_ =>
+ (sep_matches_prefix _s1643_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1644_ _)) =>
+ (match (string_drop _s1643_ _s1644_) with
+ | _s1645_ =>
+ (match (hex_bits_5_matches_prefix _s1645_) with
+ | Some ((rs1, existT _ _s1646_ _)) =>
+ (match (string_drop _s1645_ _s1646_) with
+ | _s1647_ =>
+ (sep_matches_prefix _s1647_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1648_ _)) =>
+ (match (string_drop _s1647_ _s1648_) with
+ | _s1649_ =>
+ (csr_name_map_matches_prefix _s1649_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s1650_ _)) =>
+ let p0_ :=
+ string_drop _s1649_ _s1650_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1615_ (_s1616_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1617_ := _s1616_ in
+ (if ((string_startswith _s1617_ "rem")) then
+ (match (string_drop _s1617_ (projT1 (string_length "rem"))) with
+ | _s1618_ =>
+ (maybe_not_u_matches_prefix _s1618_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1619_ _)) =>
+ let _s1620_ := string_drop _s1618_ _s1619_ in
+ (if ((string_startswith _s1620_ "w")) then
+ (match (string_drop _s1620_ (projT1 (string_length "w"))) with
+ | _s1621_ =>
+ (spc_matches_prefix _s1621_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1622_ _)) =>
+ (match (string_drop _s1621_ _s1622_) with
+ | _s1623_ =>
+ (reg_name_matches_prefix _s1623_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1624_ _)) =>
+ (match (string_drop _s1623_ _s1624_) with
+ | _s1625_ =>
+ (sep_matches_prefix _s1625_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1626_ _)) =>
+ (match (string_drop _s1625_ _s1626_) with
+ | _s1627_ =>
+ (reg_name_matches_prefix _s1627_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1628_ _)) =>
+ (match (string_drop _s1627_ _s1628_) with
+ | _s1629_ =>
+ (sep_matches_prefix _s1629_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1630_ _)) =>
+ (match (string_drop _s1629_ _s1630_) with
+ | _s1631_ =>
+ (reg_name_matches_prefix _s1631_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1632_ _)) =>
+ let p0_ :=
+ string_drop _s1631_
+ _s1632_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1596_ (_s1597_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1598_ := _s1597_ in
+ (if ((string_startswith _s1598_ "div")) then
+ (match (string_drop _s1598_ (projT1 (string_length "div"))) with
+ | _s1599_ =>
+ (maybe_not_u_matches_prefix _s1599_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1600_ _)) =>
+ let _s1601_ := string_drop _s1599_ _s1600_ in
+ (if ((string_startswith _s1601_ "w")) then
+ (match (string_drop _s1601_ (projT1 (string_length "w"))) with
+ | _s1602_ =>
+ (spc_matches_prefix _s1602_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1603_ _)) =>
+ (match (string_drop _s1602_ _s1603_) with
+ | _s1604_ =>
+ (reg_name_matches_prefix _s1604_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1605_ _)) =>
+ (match (string_drop _s1604_ _s1605_) with
+ | _s1606_ =>
+ (sep_matches_prefix _s1606_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1607_ _)) =>
+ (match (string_drop _s1606_ _s1607_) with
+ | _s1608_ =>
+ (reg_name_matches_prefix _s1608_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1609_ _)) =>
+ (match (string_drop _s1608_ _s1609_) with
+ | _s1610_ =>
+ (sep_matches_prefix _s1610_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1611_ _)) =>
+ (match (string_drop _s1610_ _s1611_) with
+ | _s1612_ =>
+ (reg_name_matches_prefix _s1612_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1613_ _)) =>
+ let p0_ :=
+ string_drop _s1612_
+ _s1613_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1580_ (_s1581_ : string)
+: M (option ((mword 5 * mword 5 * mword 5))) :=
+
+ let _s1582_ := _s1581_ in
+ (if ((string_startswith _s1582_ "mulw")) then
+ (match (string_drop _s1582_ (projT1 (string_length "mulw"))) with
+ | _s1583_ =>
+ (spc_matches_prefix _s1583_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1584_ _)) =>
+ (match (string_drop _s1583_ _s1584_) with
+ | _s1585_ =>
+ (reg_name_matches_prefix _s1585_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1586_ _)) =>
+ (match (string_drop _s1585_ _s1586_) with
+ | _s1587_ =>
+ (sep_matches_prefix _s1587_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1588_ _)) =>
+ (match (string_drop _s1587_ _s1588_) with
+ | _s1589_ =>
+ (reg_name_matches_prefix _s1589_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1590_ _)) =>
+ (match (string_drop _s1589_ _s1590_) with
+ | _s1591_ =>
+ (sep_matches_prefix _s1591_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1592_ _)) =>
+ (match (string_drop _s1591_ _s1592_) with
+ | _s1593_ =>
+ (reg_name_matches_prefix _s1593_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s1594_ _)) =>
+ let p0_ :=
+ string_drop _s1593_ _s1594_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5 * mword 5))).
+
+Definition _s1562_ (_s1563_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1564_ := _s1563_ in
+ (if ((string_startswith _s1564_ "rem")) then
+ (match (string_drop _s1564_ (projT1 (string_length "rem"))) with
+ | _s1565_ =>
+ (maybe_not_u_matches_prefix _s1565_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1566_ _)) =>
+ (match (string_drop _s1565_ _s1566_) with
+ | _s1567_ =>
+ (spc_matches_prefix _s1567_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1568_ _)) =>
+ (match (string_drop _s1567_ _s1568_) with
+ | _s1569_ =>
+ (reg_name_matches_prefix _s1569_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1570_ _)) =>
+ (match (string_drop _s1569_ _s1570_) with
+ | _s1571_ =>
+ (sep_matches_prefix _s1571_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1572_ _)) =>
+ (match (string_drop _s1571_ _s1572_) with
+ | _s1573_ =>
+ (reg_name_matches_prefix _s1573_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1574_ _)) =>
+ (match (string_drop _s1573_ _s1574_) with
+ | _s1575_ =>
+ (sep_matches_prefix _s1575_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1576_ _)) =>
+ (match (string_drop _s1575_ _s1576_) with
+ | _s1577_ =>
+ (reg_name_matches_prefix _s1577_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1578_ _)) =>
+ let p0_ :=
+ string_drop _s1577_ _s1578_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1544_ (_s1545_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1546_ := _s1545_ in
+ (if ((string_startswith _s1546_ "div")) then
+ (match (string_drop _s1546_ (projT1 (string_length "div"))) with
+ | _s1547_ =>
+ (maybe_not_u_matches_prefix _s1547_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s1548_ _)) =>
+ (match (string_drop _s1547_ _s1548_) with
+ | _s1549_ =>
+ (spc_matches_prefix _s1549_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1550_ _)) =>
+ (match (string_drop _s1549_ _s1550_) with
+ | _s1551_ =>
+ (reg_name_matches_prefix _s1551_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1552_ _)) =>
+ (match (string_drop _s1551_ _s1552_) with
+ | _s1553_ =>
+ (sep_matches_prefix _s1553_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1554_ _)) =>
+ (match (string_drop _s1553_ _s1554_) with
+ | _s1555_ =>
+ (reg_name_matches_prefix _s1555_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1556_ _)) =>
+ (match (string_drop _s1555_ _s1556_) with
+ | _s1557_ =>
+ (sep_matches_prefix _s1557_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1558_ _)) =>
+ (match (string_drop _s1557_ _s1558_) with
+ | _s1559_ =>
+ (reg_name_matches_prefix _s1559_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s1560_ _)) =>
+ let p0_ :=
+ string_drop _s1559_ _s1560_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1527_ (_s1528_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1528_ with
+ | _s1529_ =>
+ (mul_mnemonic_matches_prefix _s1529_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s1530_ _)) =>
+ (match (string_drop _s1529_ _s1530_) with
+ | _s1531_ =>
+ (spc_matches_prefix _s1531_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1532_ _)) =>
+ (match (string_drop _s1531_ _s1532_) with
+ | _s1533_ =>
+ (reg_name_matches_prefix _s1533_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1534_ _)) =>
+ (match (string_drop _s1533_ _s1534_) with
+ | _s1535_ =>
+ (sep_matches_prefix _s1535_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1536_ _)) =>
+ (match (string_drop _s1535_ _s1536_) with
+ | _s1537_ =>
+ (reg_name_matches_prefix _s1537_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1538_ _)) =>
+ (match (string_drop _s1537_ _s1538_) with
+ | _s1539_ =>
+ (sep_matches_prefix _s1539_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1540_ _)) =>
+ (match (string_drop _s1539_ _s1540_) with
+ | _s1541_ =>
+ (reg_name_matches_prefix _s1541_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1542_ _)) =>
+ let p0_ :=
+ string_drop _s1541_ _s1542_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1515_ (_s1516_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1517_ := _s1516_ in
+ (if ((string_startswith _s1517_ "c.add")) then
+ (match (string_drop _s1517_ (projT1 (string_length "c.add"))) with
+ | _s1518_ =>
+ (spc_matches_prefix _s1518_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1519_ _)) =>
+ (match (string_drop _s1518_ _s1519_) with
+ | _s1520_ =>
+ (reg_name_matches_prefix _s1520_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1521_ _)) =>
+ (match (string_drop _s1520_ _s1521_) with
+ | _s1522_ =>
+ (sep_matches_prefix _s1522_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1523_ _)) =>
+ (match (string_drop _s1522_ _s1523_) with
+ | _s1524_ =>
+ (reg_name_matches_prefix _s1524_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1525_ _)) =>
+ let p0_ := string_drop _s1524_ _s1525_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1503_ (_s1504_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1505_ := _s1504_ in
+ (if ((string_startswith _s1505_ "c.mv")) then
+ (match (string_drop _s1505_ (projT1 (string_length "c.mv"))) with
+ | _s1506_ =>
+ (spc_matches_prefix _s1506_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1507_ _)) =>
+ (match (string_drop _s1506_ _s1507_) with
+ | _s1508_ =>
+ (reg_name_matches_prefix _s1508_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1509_ _)) =>
+ (match (string_drop _s1508_ _s1509_) with
+ | _s1510_ =>
+ (sep_matches_prefix _s1510_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1511_ _)) =>
+ (match (string_drop _s1510_ _s1511_) with
+ | _s1512_ =>
+ (reg_name_matches_prefix _s1512_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1513_ _)) =>
+ let p0_ := string_drop _s1512_ _s1513_ in
+ if ((generic_eq p0_ "")) then Some ((rd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1495_ (_s1496_ : string)
+: M (option (mword 5)) :=
+
+ let _s1497_ := _s1496_ in
+ (if ((string_startswith _s1497_ "c.jalr")) then
+ (match (string_drop _s1497_ (projT1 (string_length "c.jalr"))) with
+ | _s1498_ =>
+ (spc_matches_prefix _s1498_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1499_ _)) =>
+ (match (string_drop _s1498_ _s1499_) with
+ | _s1500_ =>
+ (reg_name_matches_prefix _s1500_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s1501_ _)) =>
+ let p0_ := string_drop _s1500_ _s1501_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s1487_ (_s1488_ : string)
+: M (option (mword 5)) :=
+
+ let _s1489_ := _s1488_ in
+ (if ((string_startswith _s1489_ "c.jr")) then
+ (match (string_drop _s1489_ (projT1 (string_length "c.jr"))) with
+ | _s1490_ =>
+ (spc_matches_prefix _s1490_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1491_ _)) =>
+ (match (string_drop _s1490_ _s1491_) with
+ | _s1492_ =>
+ (reg_name_matches_prefix _s1492_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s1493_ _)) =>
+ let p0_ := string_drop _s1492_ _s1493_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s1475_ (_s1476_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1477_ := _s1476_ in
+ (if ((string_startswith _s1477_ "c.sdsp")) then
+ (match (string_drop _s1477_ (projT1 (string_length "c.sdsp"))) with
+ | _s1478_ =>
+ (spc_matches_prefix _s1478_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1479_ _)) =>
+ (match (string_drop _s1478_ _s1479_) with
+ | _s1480_ =>
+ (reg_name_matches_prefix _s1480_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s1481_ _)) =>
+ (match (string_drop _s1480_ _s1481_) with
+ | _s1482_ =>
+ (sep_matches_prefix _s1482_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1483_ _)) =>
+ match (string_drop _s1482_ _s1483_) with
+ | _s1484_ =>
+ match (hex_bits_6_matches_prefix _s1484_) with
+ | Some ((uimm, existT _ _s1485_ _)) =>
+ let p0_ := string_drop _s1484_ _s1485_ in
+ if ((generic_eq p0_ "")) then Some ((rs2, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1463_ (_s1464_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1465_ := _s1464_ in
+ (if ((string_startswith _s1465_ "c.swsp")) then
+ (match (string_drop _s1465_ (projT1 (string_length "c.swsp"))) with
+ | _s1466_ =>
+ (spc_matches_prefix _s1466_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1467_ _)) =>
+ (match (string_drop _s1466_ _s1467_) with
+ | _s1468_ =>
+ (reg_name_matches_prefix _s1468_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1469_ _)) =>
+ (match (string_drop _s1468_ _s1469_) with
+ | _s1470_ =>
+ (sep_matches_prefix _s1470_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1471_ _)) =>
+ match (string_drop _s1470_ _s1471_) with
+ | _s1472_ =>
+ match (hex_bits_6_matches_prefix _s1472_) with
+ | Some ((uimm, existT _ _s1473_ _)) =>
+ let p0_ := string_drop _s1472_ _s1473_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1451_ (_s1452_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1453_ := _s1452_ in
+ (if ((string_startswith _s1453_ "c.ldsp")) then
+ (match (string_drop _s1453_ (projT1 (string_length "c.ldsp"))) with
+ | _s1454_ =>
+ (spc_matches_prefix _s1454_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1455_ _)) =>
+ (match (string_drop _s1454_ _s1455_) with
+ | _s1456_ =>
+ (reg_name_matches_prefix _s1456_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1457_ _)) =>
+ (match (string_drop _s1456_ _s1457_) with
+ | _s1458_ =>
+ (sep_matches_prefix _s1458_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1459_ _)) =>
+ match (string_drop _s1458_ _s1459_) with
+ | _s1460_ =>
+ match (hex_bits_6_matches_prefix _s1460_) with
+ | Some ((uimm, existT _ _s1461_ _)) =>
+ let p0_ := string_drop _s1460_ _s1461_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1439_ (_s1440_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1441_ := _s1440_ in
+ (if ((string_startswith _s1441_ "c.lwsp")) then
+ (match (string_drop _s1441_ (projT1 (string_length "c.lwsp"))) with
+ | _s1442_ =>
+ (spc_matches_prefix _s1442_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1443_ _)) =>
+ (match (string_drop _s1442_ _s1443_) with
+ | _s1444_ =>
+ (reg_name_matches_prefix _s1444_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1445_ _)) =>
+ (match (string_drop _s1444_ _s1445_) with
+ | _s1446_ =>
+ (sep_matches_prefix _s1446_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1447_ _)) =>
+ match (string_drop _s1446_ _s1447_) with
+ | _s1448_ =>
+ match (hex_bits_6_matches_prefix _s1448_) with
+ | Some ((uimm, existT _ _s1449_ _)) =>
+ let p0_ := string_drop _s1448_ _s1449_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1427_ (_s1428_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1429_ := _s1428_ in
+ (if ((string_startswith _s1429_ "c.slli")) then
+ (match (string_drop _s1429_ (projT1 (string_length "c.slli"))) with
+ | _s1430_ =>
+ (spc_matches_prefix _s1430_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1431_ _)) =>
+ (match (string_drop _s1430_ _s1431_) with
+ | _s1432_ =>
+ (reg_name_matches_prefix _s1432_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1433_ _)) =>
+ (match (string_drop _s1432_ _s1433_) with
+ | _s1434_ =>
+ (sep_matches_prefix _s1434_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1435_ _)) =>
+ match (string_drop _s1434_ _s1435_) with
+ | _s1436_ =>
+ match (hex_bits_6_matches_prefix _s1436_) with
+ | Some ((shamt, existT _ _s1437_ _)) =>
+ let p0_ := string_drop _s1436_ _s1437_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1415_ (_s1416_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1417_ := _s1416_ in
+ (if ((string_startswith _s1417_ "c.bnez")) then
+ (match (string_drop _s1417_ (projT1 (string_length "c.bnez"))) with
+ | _s1418_ =>
+ (spc_matches_prefix _s1418_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1419_ _)) =>
+ (match (string_drop _s1418_ _s1419_) with
+ | _s1420_ =>
+ (creg_name_matches_prefix _s1420_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s1421_ _)) =>
+ (match (string_drop _s1420_ _s1421_) with
+ | _s1422_ =>
+ (sep_matches_prefix _s1422_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1423_ _)) =>
+ match (string_drop _s1422_ _s1423_) with
+ | _s1424_ =>
+ match (hex_bits_8_matches_prefix _s1424_) with
+ | Some ((imm, existT _ _s1425_ _)) =>
+ let p0_ := string_drop _s1424_ _s1425_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1403_ (_s1404_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1405_ := _s1404_ in
+ (if ((string_startswith _s1405_ "c.beqz")) then
+ (match (string_drop _s1405_ (projT1 (string_length "c.beqz"))) with
+ | _s1406_ =>
+ (spc_matches_prefix _s1406_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1407_ _)) =>
+ (match (string_drop _s1406_ _s1407_) with
+ | _s1408_ =>
+ (creg_name_matches_prefix _s1408_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s1409_ _)) =>
+ (match (string_drop _s1408_ _s1409_) with
+ | _s1410_ =>
+ (sep_matches_prefix _s1410_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1411_ _)) =>
+ match (string_drop _s1410_ _s1411_) with
+ | _s1412_ =>
+ match (hex_bits_8_matches_prefix _s1412_) with
+ | Some ((imm, existT _ _s1413_ _)) =>
+ let p0_ := string_drop _s1412_ _s1413_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1395_ (_s1396_ : string)
+: M (option (mword 11)) :=
+
+ let _s1397_ := _s1396_ in
+ (if ((string_startswith _s1397_ "c.j")) then
+ (match (string_drop _s1397_ (projT1 (string_length "c.j"))) with
+ | _s1398_ =>
+ (spc_matches_prefix _s1398_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1399_ _)) =>
+ match (string_drop _s1398_ _s1399_) with
+ | _s1400_ =>
+ match (hex_bits_11_matches_prefix _s1400_) with
+ | Some ((imm, existT _ _s1401_ _)) =>
+ let p0_ := string_drop _s1400_ _s1401_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s1383_ (_s1384_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1385_ := _s1384_ in
+ (if ((string_startswith _s1385_ "c.addw")) then
+ (match (string_drop _s1385_ (projT1 (string_length "c.addw"))) with
+ | _s1386_ =>
+ (spc_matches_prefix _s1386_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1387_ _)) =>
+ (match (string_drop _s1386_ _s1387_) with
+ | _s1388_ =>
+ (creg_name_matches_prefix _s1388_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1389_ _)) =>
+ (match (string_drop _s1388_ _s1389_) with
+ | _s1390_ =>
+ (sep_matches_prefix _s1390_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1391_ _)) =>
+ (match (string_drop _s1390_ _s1391_) with
+ | _s1392_ =>
+ (creg_name_matches_prefix _s1392_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1393_ _)) =>
+ let p0_ := string_drop _s1392_ _s1393_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1371_ (_s1372_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1373_ := _s1372_ in
+ (if ((string_startswith _s1373_ "c.subw")) then
+ (match (string_drop _s1373_ (projT1 (string_length "c.subw"))) with
+ | _s1374_ =>
+ (spc_matches_prefix _s1374_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1375_ _)) =>
+ (match (string_drop _s1374_ _s1375_) with
+ | _s1376_ =>
+ (creg_name_matches_prefix _s1376_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1377_ _)) =>
+ (match (string_drop _s1376_ _s1377_) with
+ | _s1378_ =>
+ (sep_matches_prefix _s1378_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1379_ _)) =>
+ (match (string_drop _s1378_ _s1379_) with
+ | _s1380_ =>
+ (creg_name_matches_prefix _s1380_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1381_ _)) =>
+ let p0_ := string_drop _s1380_ _s1381_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1359_ (_s1360_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1361_ := _s1360_ in
+ (if ((string_startswith _s1361_ "c.and")) then
+ (match (string_drop _s1361_ (projT1 (string_length "c.and"))) with
+ | _s1362_ =>
+ (spc_matches_prefix _s1362_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1363_ _)) =>
+ (match (string_drop _s1362_ _s1363_) with
+ | _s1364_ =>
+ (creg_name_matches_prefix _s1364_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1365_ _)) =>
+ (match (string_drop _s1364_ _s1365_) with
+ | _s1366_ =>
+ (sep_matches_prefix _s1366_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1367_ _)) =>
+ (match (string_drop _s1366_ _s1367_) with
+ | _s1368_ =>
+ (creg_name_matches_prefix _s1368_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1369_ _)) =>
+ let p0_ := string_drop _s1368_ _s1369_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1347_ (_s1348_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1349_ := _s1348_ in
+ (if ((string_startswith _s1349_ "c.or")) then
+ (match (string_drop _s1349_ (projT1 (string_length "c.or"))) with
+ | _s1350_ =>
+ (spc_matches_prefix _s1350_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1351_ _)) =>
+ (match (string_drop _s1350_ _s1351_) with
+ | _s1352_ =>
+ (creg_name_matches_prefix _s1352_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1353_ _)) =>
+ (match (string_drop _s1352_ _s1353_) with
+ | _s1354_ =>
+ (sep_matches_prefix _s1354_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1355_ _)) =>
+ (match (string_drop _s1354_ _s1355_) with
+ | _s1356_ =>
+ (creg_name_matches_prefix _s1356_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1357_ _)) =>
+ let p0_ := string_drop _s1356_ _s1357_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1335_ (_s1336_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1337_ := _s1336_ in
+ (if ((string_startswith _s1337_ "c.xor")) then
+ (match (string_drop _s1337_ (projT1 (string_length "c.xor"))) with
+ | _s1338_ =>
+ (spc_matches_prefix _s1338_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1339_ _)) =>
+ (match (string_drop _s1338_ _s1339_) with
+ | _s1340_ =>
+ (creg_name_matches_prefix _s1340_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1341_ _)) =>
+ (match (string_drop _s1340_ _s1341_) with
+ | _s1342_ =>
+ (sep_matches_prefix _s1342_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1343_ _)) =>
+ (match (string_drop _s1342_ _s1343_) with
+ | _s1344_ =>
+ (creg_name_matches_prefix _s1344_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1345_ _)) =>
+ let p0_ := string_drop _s1344_ _s1345_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1323_ (_s1324_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s1325_ := _s1324_ in
+ (if ((string_startswith _s1325_ "c.sub")) then
+ (match (string_drop _s1325_ (projT1 (string_length "c.sub"))) with
+ | _s1326_ =>
+ (spc_matches_prefix _s1326_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1327_ _)) =>
+ (match (string_drop _s1326_ _s1327_) with
+ | _s1328_ =>
+ (creg_name_matches_prefix _s1328_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1329_ _)) =>
+ (match (string_drop _s1328_ _s1329_) with
+ | _s1330_ =>
+ (sep_matches_prefix _s1330_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1331_ _)) =>
+ (match (string_drop _s1330_ _s1331_) with
+ | _s1332_ =>
+ (creg_name_matches_prefix _s1332_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1333_ _)) =>
+ let p0_ := string_drop _s1332_ _s1333_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s1311_ (_s1312_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1313_ := _s1312_ in
+ (if ((string_startswith _s1313_ "c.andi")) then
+ (match (string_drop _s1313_ (projT1 (string_length "c.andi"))) with
+ | _s1314_ =>
+ (spc_matches_prefix _s1314_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1315_ _)) =>
+ (match (string_drop _s1314_ _s1315_) with
+ | _s1316_ =>
+ (creg_name_matches_prefix _s1316_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1317_ _)) =>
+ (match (string_drop _s1316_ _s1317_) with
+ | _s1318_ =>
+ (sep_matches_prefix _s1318_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1319_ _)) =>
+ match (string_drop _s1318_ _s1319_) with
+ | _s1320_ =>
+ match (hex_bits_6_matches_prefix _s1320_) with
+ | Some ((imm, existT _ _s1321_ _)) =>
+ let p0_ := string_drop _s1320_ _s1321_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1299_ (_s1300_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1301_ := _s1300_ in
+ (if ((string_startswith _s1301_ "c.srai")) then
+ (match (string_drop _s1301_ (projT1 (string_length "c.srai"))) with
+ | _s1302_ =>
+ (spc_matches_prefix _s1302_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1303_ _)) =>
+ (match (string_drop _s1302_ _s1303_) with
+ | _s1304_ =>
+ (creg_name_matches_prefix _s1304_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1305_ _)) =>
+ (match (string_drop _s1304_ _s1305_) with
+ | _s1306_ =>
+ (sep_matches_prefix _s1306_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1307_ _)) =>
+ match (string_drop _s1306_ _s1307_) with
+ | _s1308_ =>
+ match (hex_bits_6_matches_prefix _s1308_) with
+ | Some ((shamt, existT _ _s1309_ _)) =>
+ let p0_ := string_drop _s1308_ _s1309_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1287_ (_s1288_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s1289_ := _s1288_ in
+ (if ((string_startswith _s1289_ "c.srli")) then
+ (match (string_drop _s1289_ (projT1 (string_length "c.srli"))) with
+ | _s1290_ =>
+ (spc_matches_prefix _s1290_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1291_ _)) =>
+ (match (string_drop _s1290_ _s1291_) with
+ | _s1292_ =>
+ (creg_name_matches_prefix _s1292_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1293_ _)) =>
+ (match (string_drop _s1292_ _s1293_) with
+ | _s1294_ =>
+ (sep_matches_prefix _s1294_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1295_ _)) =>
+ match (string_drop _s1294_ _s1295_) with
+ | _s1296_ =>
+ match (hex_bits_6_matches_prefix _s1296_) with
+ | Some ((shamt, existT _ _s1297_ _)) =>
+ let p0_ := string_drop _s1296_ _s1297_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s1275_ (_s1276_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1277_ := _s1276_ in
+ (if ((string_startswith _s1277_ "c.lui")) then
+ (match (string_drop _s1277_ (projT1 (string_length "c.lui"))) with
+ | _s1278_ =>
+ (spc_matches_prefix _s1278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1279_ _)) =>
+ (match (string_drop _s1278_ _s1279_) with
+ | _s1280_ =>
+ (reg_name_matches_prefix _s1280_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1281_ _)) =>
+ (match (string_drop _s1280_ _s1281_) with
+ | _s1282_ =>
+ (sep_matches_prefix _s1282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1283_ _)) =>
+ match (string_drop _s1282_ _s1283_) with
+ | _s1284_ =>
+ match (hex_bits_6_matches_prefix _s1284_) with
+ | Some ((imm, existT _ _s1285_ _)) =>
+ let p0_ := string_drop _s1284_ _s1285_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1267_ (_s1268_ : string)
+: M (option (mword 6)) :=
+
+ let _s1269_ := _s1268_ in
+ (if ((string_startswith _s1269_ "c.addi16sp")) then
+ (match (string_drop _s1269_ (projT1 (string_length "c.addi16sp"))) with
+ | _s1270_ =>
+ (spc_matches_prefix _s1270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1271_ _)) =>
+ match (string_drop _s1270_ _s1271_) with
+ | _s1272_ =>
+ match (hex_bits_6_matches_prefix _s1272_) with
+ | Some ((imm, existT _ _s1273_ _)) =>
+ let p0_ := string_drop _s1272_ _s1273_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 6))
+ end)
+ : M (option (mword 6))
+ else returnm (None : option (mword 6)))
+ : M (option (mword 6)).
+
+Definition _s1255_ (_s1256_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1257_ := _s1256_ in
+ (if ((string_startswith _s1257_ "c.li")) then
+ (match (string_drop _s1257_ (projT1 (string_length "c.li"))) with
+ | _s1258_ =>
+ (spc_matches_prefix _s1258_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1259_ _)) =>
+ (match (string_drop _s1258_ _s1259_) with
+ | _s1260_ =>
+ (reg_name_matches_prefix _s1260_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1261_ _)) =>
+ (match (string_drop _s1260_ _s1261_) with
+ | _s1262_ =>
+ (sep_matches_prefix _s1262_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1263_ _)) =>
+ match (string_drop _s1262_ _s1263_) with
+ | _s1264_ =>
+ match (hex_bits_6_matches_prefix _s1264_) with
+ | Some ((imm, existT _ _s1265_ _)) =>
+ let p0_ := string_drop _s1264_ _s1265_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1243_ (_s1244_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1245_ := _s1244_ in
+ (if ((string_startswith _s1245_ "c.addiw")) then
+ (match (string_drop _s1245_ (projT1 (string_length "c.addiw"))) with
+ | _s1246_ =>
+ (spc_matches_prefix _s1246_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1247_ _)) =>
+ (match (string_drop _s1246_ _s1247_) with
+ | _s1248_ =>
+ (reg_name_matches_prefix _s1248_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1249_ _)) =>
+ (match (string_drop _s1248_ _s1249_) with
+ | _s1250_ =>
+ (sep_matches_prefix _s1250_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1251_ _)) =>
+ match (string_drop _s1250_ _s1251_) with
+ | _s1252_ =>
+ match (hex_bits_6_matches_prefix _s1252_) with
+ | Some ((imm, existT _ _s1253_ _)) =>
+ let p0_ := string_drop _s1252_ _s1253_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1235_ (_s1236_ : string)
+: M (option (mword 11)) :=
+
+ let _s1237_ := _s1236_ in
+ (if ((string_startswith _s1237_ "c.jal")) then
+ (match (string_drop _s1237_ (projT1 (string_length "c.jal"))) with
+ | _s1238_ =>
+ (spc_matches_prefix _s1238_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s1239_ _)) =>
+ match (string_drop _s1238_ _s1239_) with
+ | _s1240_ =>
+ match (hex_bits_12_matches_prefix _s1240_) with
+ | Some ((v__802, existT _ _s1241_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__802 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__802 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__802 11 1 in
+ let p0_ := string_drop _s1240_ _s1241_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s1223_ (_s1224_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s1225_ := _s1224_ in
+ (if ((string_startswith _s1225_ "c.addi")) then
+ (match (string_drop _s1225_ (projT1 (string_length "c.addi"))) with
+ | _s1226_ =>
+ (spc_matches_prefix _s1226_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1227_ _)) =>
+ (match (string_drop _s1226_ _s1227_) with
+ | _s1228_ =>
+ (reg_name_matches_prefix _s1228_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s1229_ _)) =>
+ (match (string_drop _s1228_ _s1229_) with
+ | _s1230_ =>
+ (sep_matches_prefix _s1230_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1231_ _)) =>
+ match (string_drop _s1230_ _s1231_) with
+ | _s1232_ =>
+ match (hex_bits_6_matches_prefix _s1232_) with
+ | Some ((nzi, existT _ _s1233_ _)) =>
+ let p0_ := string_drop _s1232_ _s1233_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, nzi))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s1207_ (_s1208_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1209_ := _s1208_ in
+ (if ((string_startswith _s1209_ "c.sd")) then
+ (match (string_drop _s1209_ (projT1 (string_length "c.sd"))) with
+ | _s1210_ =>
+ (spc_matches_prefix _s1210_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1211_ _)) =>
+ (match (string_drop _s1210_ _s1211_) with
+ | _s1212_ =>
+ (creg_name_matches_prefix _s1212_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s1213_ _)) =>
+ (match (string_drop _s1212_ _s1213_) with
+ | _s1214_ =>
+ (sep_matches_prefix _s1214_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1215_ _)) =>
+ (match (string_drop _s1214_ _s1215_) with
+ | _s1216_ =>
+ (creg_name_matches_prefix _s1216_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s1217_ _)) =>
+ (match (string_drop _s1216_ _s1217_) with
+ | _s1218_ =>
+ (sep_matches_prefix _s1218_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1219_ _)) =>
+ match (string_drop _s1218_ _s1219_) with
+ | _s1220_ =>
+ match (hex_bits_8_matches_prefix _s1220_) with
+ | Some ((v__804, existT _ _s1221_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__804 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__804 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__804 7 3 in
+ let p0_ :=
+ string_drop _s1220_ _s1221_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1191_ (_s1192_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1193_ := _s1192_ in
+ (if ((string_startswith _s1193_ "c.sw")) then
+ (match (string_drop _s1193_ (projT1 (string_length "c.sw"))) with
+ | _s1194_ =>
+ (spc_matches_prefix _s1194_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1195_ _)) =>
+ (match (string_drop _s1194_ _s1195_) with
+ | _s1196_ =>
+ (creg_name_matches_prefix _s1196_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s1197_ _)) =>
+ (match (string_drop _s1196_ _s1197_) with
+ | _s1198_ =>
+ (sep_matches_prefix _s1198_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1199_ _)) =>
+ (match (string_drop _s1198_ _s1199_) with
+ | _s1200_ =>
+ (creg_name_matches_prefix _s1200_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s1201_ _)) =>
+ (match (string_drop _s1200_ _s1201_) with
+ | _s1202_ =>
+ (sep_matches_prefix _s1202_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1203_ _)) =>
+ match (string_drop _s1202_ _s1203_) with
+ | _s1204_ =>
+ match (hex_bits_7_matches_prefix _s1204_) with
+ | Some ((v__806, existT _ _s1205_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__806 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__806 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__806 6 2 in
+ let p0_ :=
+ string_drop _s1204_ _s1205_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1175_ (_s1176_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1177_ := _s1176_ in
+ (if ((string_startswith _s1177_ "c.ld")) then
+ (match (string_drop _s1177_ (projT1 (string_length "c.ld"))) with
+ | _s1178_ =>
+ (spc_matches_prefix _s1178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1179_ _)) =>
+ (match (string_drop _s1178_ _s1179_) with
+ | _s1180_ =>
+ (creg_name_matches_prefix _s1180_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1181_ _)) =>
+ (match (string_drop _s1180_ _s1181_) with
+ | _s1182_ =>
+ (sep_matches_prefix _s1182_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1183_ _)) =>
+ (match (string_drop _s1182_ _s1183_) with
+ | _s1184_ =>
+ (creg_name_matches_prefix _s1184_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s1185_ _)) =>
+ (match (string_drop _s1184_ _s1185_) with
+ | _s1186_ =>
+ (sep_matches_prefix _s1186_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1187_ _)) =>
+ match (string_drop _s1186_ _s1187_) with
+ | _s1188_ =>
+ match (hex_bits_8_matches_prefix _s1188_) with
+ | Some ((v__808, existT _ _s1189_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__808 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__808 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__808 7 3 in
+ let p0_ :=
+ string_drop _s1188_ _s1189_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1159_ (_s1160_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s1161_ := _s1160_ in
+ (if ((string_startswith _s1161_ "c.lw")) then
+ (match (string_drop _s1161_ (projT1 (string_length "c.lw"))) with
+ | _s1162_ =>
+ (spc_matches_prefix _s1162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1163_ _)) =>
+ (match (string_drop _s1162_ _s1163_) with
+ | _s1164_ =>
+ (creg_name_matches_prefix _s1164_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1165_ _)) =>
+ (match (string_drop _s1164_ _s1165_) with
+ | _s1166_ =>
+ (sep_matches_prefix _s1166_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1167_ _)) =>
+ (match (string_drop _s1166_ _s1167_) with
+ | _s1168_ =>
+ (creg_name_matches_prefix _s1168_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s1169_ _)) =>
+ (match (string_drop _s1168_ _s1169_) with
+ | _s1170_ =>
+ (sep_matches_prefix _s1170_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1171_ _)) =>
+ match (string_drop _s1170_ _s1171_) with
+ | _s1172_ =>
+ match (hex_bits_7_matches_prefix _s1172_) with
+ | Some ((v__810, existT _ _s1173_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__810 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__810 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__810 6 2 in
+ let p0_ :=
+ string_drop _s1172_ _s1173_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s1147_ (_s1148_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s1149_ := _s1148_ in
+ (if ((string_startswith _s1149_ "c.addi4spn")) then
+ (match (string_drop _s1149_ (projT1 (string_length "c.addi4spn"))) with
+ | _s1150_ =>
+ (spc_matches_prefix _s1150_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1151_ _)) =>
+ (match (string_drop _s1150_ _s1151_) with
+ | _s1152_ =>
+ (creg_name_matches_prefix _s1152_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s1153_ _)) =>
+ (match (string_drop _s1152_ _s1153_) with
+ | _s1154_ =>
+ (sep_matches_prefix _s1154_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1155_ _)) =>
+ match (string_drop _s1154_ _s1155_) with
+ | _s1156_ =>
+ match (hex_bits_10_matches_prefix _s1156_) with
+ | Some ((v__812, existT _ _s1157_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__812 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__812 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__812 9 2 in
+ let p0_ := string_drop _s1156_ _s1157_ in
+ if ((generic_eq p0_ "")) then Some ((rdc, nzimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1123_ (_s1124_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1124_ with
+ | _s1125_ =>
+ (amo_mnemonic_matches_prefix _s1125_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1126_ _)) =>
+ let _s1127_ := string_drop _s1125_ _s1126_ in
+ (if ((string_startswith _s1127_ ".")) then
+ (match (string_drop _s1127_ (projT1 (string_length "."))) with
+ | _s1128_ =>
+ (size_mnemonic_matches_prefix _s1128_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s1129_ _)) =>
+ (match (string_drop _s1128_ _s1129_) with
+ | _s1130_ =>
+ (maybe_aq_matches_prefix _s1130_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s1131_ _)) =>
+ (match (string_drop _s1130_ _s1131_) with
+ | _s1132_ =>
+ (maybe_rl_matches_prefix _s1132_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s1133_ _)) =>
+ (match (string_drop _s1132_ _s1133_) with
+ | _s1134_ =>
+ (spc_matches_prefix _s1134_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1135_ _)) =>
+ (match (string_drop _s1134_ _s1135_) with
+ | _s1136_ =>
+ (reg_name_matches_prefix _s1136_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s1137_ _)) =>
+ (match (string_drop _s1136_ _s1137_) with
+ | _s1138_ =>
+ (sep_matches_prefix _s1138_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1139_ _)) =>
+ (match (string_drop _s1138_ _s1139_) with
+ | _s1140_ =>
+ (reg_name_matches_prefix _s1140_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s1141_ _)) =>
+ (match (string_drop _s1140_
+ _s1141_) with
+ | _s1142_ =>
+ (sep_matches_prefix
+ _s1142_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s1143_ _)) =>
+ (match (string_drop
+ _s1142_
+ _s1143_) with
+ | _s1144_ =>
+ (reg_name_matches_prefix
+ _s1144_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s1145_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1144_
+ _s1145_ in
+ if ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2))
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1101_ (_s1102_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1103_ := _s1102_ in
+ (if ((string_startswith _s1103_ "sc.")) then
+ (match (string_drop _s1103_ (projT1 (string_length "sc."))) with
+ | _s1104_ =>
+ (size_mnemonic_matches_prefix _s1104_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1105_ _)) =>
+ (match (string_drop _s1104_ _s1105_) with
+ | _s1106_ =>
+ (maybe_aq_matches_prefix _s1106_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1107_ _)) =>
+ (match (string_drop _s1106_ _s1107_) with
+ | _s1108_ =>
+ (maybe_rl_matches_prefix _s1108_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1109_ _)) =>
+ (match (string_drop _s1108_ _s1109_) with
+ | _s1110_ =>
+ (spc_matches_prefix _s1110_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1111_ _)) =>
+ (match (string_drop _s1110_ _s1111_) with
+ | _s1112_ =>
+ (reg_name_matches_prefix _s1112_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1113_ _)) =>
+ (match (string_drop _s1112_ _s1113_) with
+ | _s1114_ =>
+ (sep_matches_prefix _s1114_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1115_ _)) =>
+ (match (string_drop _s1114_ _s1115_) with
+ | _s1116_ =>
+ (reg_name_matches_prefix _s1116_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s1117_ _)) =>
+ (match (string_drop _s1116_ _s1117_) with
+ | _s1118_ =>
+ (sep_matches_prefix _s1118_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s1119_ _)) =>
+ (match (string_drop _s1118_
+ _s1119_) with
+ | _s1120_ =>
+ (reg_name_matches_prefix
+ _s1120_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s1121_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1120_
+ _s1121_ in
+ if ((generic_eq
+ p0_ ""))
+ then
+ Some
+ ((size, aq, rl, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1083_ (_s1084_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5))) :=
+
+ let _s1085_ := _s1084_ in
+ (if ((string_startswith _s1085_ "lr.")) then
+ (match (string_drop _s1085_ (projT1 (string_length "lr."))) with
+ | _s1086_ =>
+ (size_mnemonic_matches_prefix _s1086_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1087_ _)) =>
+ (match (string_drop _s1086_ _s1087_) with
+ | _s1088_ =>
+ (maybe_aq_matches_prefix _s1088_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1089_ _)) =>
+ (match (string_drop _s1088_ _s1089_) with
+ | _s1090_ =>
+ (maybe_rl_matches_prefix _s1090_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1091_ _)) =>
+ (match (string_drop _s1090_ _s1091_) with
+ | _s1092_ =>
+ (spc_matches_prefix _s1092_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1093_ _)) =>
+ (match (string_drop _s1092_ _s1093_) with
+ | _s1094_ =>
+ (reg_name_matches_prefix _s1094_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1095_ _)) =>
+ (match (string_drop _s1094_ _s1095_) with
+ | _s1096_ =>
+ (sep_matches_prefix _s1096_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1097_ _)) =>
+ (match (string_drop _s1096_ _s1097_) with
+ | _s1098_ =>
+ (reg_name_matches_prefix _s1098_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s1099_ _)) =>
+ let p0_ :=
+ string_drop _s1098_ _s1099_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((size, aq, rl, rd, rs1))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5))).
+
+Definition _s1071_ (_s1072_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1073_ := _s1072_ in
+ (if ((string_startswith _s1073_ "sfence.vma")) then
+ (match (string_drop _s1073_ (projT1 (string_length "sfence.vma"))) with
+ | _s1074_ =>
+ (spc_matches_prefix _s1074_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1075_ _)) =>
+ (match (string_drop _s1074_ _s1075_) with
+ | _s1076_ =>
+ (reg_name_matches_prefix _s1076_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s1077_ _)) =>
+ (match (string_drop _s1076_ _s1077_) with
+ | _s1078_ =>
+ (sep_matches_prefix _s1078_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1079_ _)) =>
+ (match (string_drop _s1078_ _s1079_) with
+ | _s1080_ =>
+ (reg_name_matches_prefix _s1080_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1081_ _)) =>
+ let p0_ := string_drop _s1080_ _s1081_ in
+ if ((generic_eq p0_ "")) then Some ((rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1059_ (_s1060_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1061_ := _s1060_ in
+ (if ((string_startswith _s1061_ "fence.tso")) then
+ (match (string_drop _s1061_ (projT1 (string_length "fence.tso"))) with
+ | _s1062_ =>
+ (spc_matches_prefix _s1062_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1063_ _)) =>
+ (match (string_drop _s1062_ _s1063_) with
+ | _s1064_ =>
+ (fence_bits_matches_prefix _s1064_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1065_ _)) =>
+ (match (string_drop _s1064_ _s1065_) with
+ | _s1066_ =>
+ (sep_matches_prefix _s1066_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1067_ _)) =>
+ (match (string_drop _s1066_ _s1067_) with
+ | _s1068_ =>
+ (fence_bits_matches_prefix _s1068_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1069_ _)) =>
+ let p0_ := string_drop _s1068_ _s1069_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1047_ (_s1048_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1049_ := _s1048_ in
+ (if ((string_startswith _s1049_ "fence")) then
+ (match (string_drop _s1049_ (projT1 (string_length "fence"))) with
+ | _s1050_ =>
+ (spc_matches_prefix _s1050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1051_ _)) =>
+ (match (string_drop _s1050_ _s1051_) with
+ | _s1052_ =>
+ (fence_bits_matches_prefix _s1052_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1053_ _)) =>
+ (match (string_drop _s1052_ _s1053_) with
+ | _s1054_ =>
+ (sep_matches_prefix _s1054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1055_ _)) =>
+ (match (string_drop _s1054_ _s1055_) with
+ | _s1056_ =>
+ (fence_bits_matches_prefix _s1056_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1057_ _)) =>
+ let p0_ := string_drop _s1056_ _s1057_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1030_ (_s1031_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1031_ with
+ | _s1032_ =>
+ (shiftiwop_mnemonic_matches_prefix _s1032_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1033_ _)) =>
+ (match (string_drop _s1032_ _s1033_) with
+ | _s1034_ =>
+ (spc_matches_prefix _s1034_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1035_ _)) =>
+ (match (string_drop _s1034_ _s1035_) with
+ | _s1036_ =>
+ (reg_name_matches_prefix _s1036_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1037_ _)) =>
+ (match (string_drop _s1036_ _s1037_) with
+ | _s1038_ =>
+ (sep_matches_prefix _s1038_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1039_ _)) =>
+ (match (string_drop _s1038_ _s1039_) with
+ | _s1040_ =>
+ (reg_name_matches_prefix _s1040_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1041_ _)) =>
+ (match (string_drop _s1040_ _s1041_) with
+ | _s1042_ =>
+ (sep_matches_prefix _s1042_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1043_ _)) =>
+ match (string_drop _s1042_ _s1043_) with
+ | _s1044_ =>
+ match (hex_bits_5_matches_prefix
+ _s1044_) with
+ | Some ((shamt, existT _ _s1045_ _)) =>
+ let p0_ :=
+ string_drop _s1044_ _s1045_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1013_ (_s1014_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1014_ with
+ | _s1015_ =>
+ (rtypew_mnemonic_matches_prefix _s1015_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1016_ _)) =>
+ (match (string_drop _s1015_ _s1016_) with
+ | _s1017_ =>
+ (spc_matches_prefix _s1017_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1018_ _)) =>
+ (match (string_drop _s1017_ _s1018_) with
+ | _s1019_ =>
+ (reg_name_matches_prefix _s1019_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1020_ _)) =>
+ (match (string_drop _s1019_ _s1020_) with
+ | _s1021_ =>
+ (sep_matches_prefix _s1021_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1022_ _)) =>
+ (match (string_drop _s1021_ _s1022_) with
+ | _s1023_ =>
+ (reg_name_matches_prefix _s1023_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1024_ _)) =>
+ (match (string_drop _s1023_ _s1024_) with
+ | _s1025_ =>
+ (sep_matches_prefix _s1025_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1026_ _)) =>
+ (match (string_drop _s1025_ _s1026_) with
+ | _s1027_ =>
+ (reg_name_matches_prefix _s1027_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1028_ _)) =>
+ let p0_ :=
+ string_drop _s1027_ _s1028_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5))).
+
+Definition _s996_ (_s997_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s997_ with
+ | _s998_ =>
+ (shiftw_mnemonic_matches_prefix _s998_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s999_ _)) =>
+ (match (string_drop _s998_ _s999_) with
+ | _s1000_ =>
+ (spc_matches_prefix _s1000_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1001_ _)) =>
+ (match (string_drop _s1000_ _s1001_) with
+ | _s1002_ =>
+ (reg_name_matches_prefix _s1002_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1003_ _)) =>
+ (match (string_drop _s1002_ _s1003_) with
+ | _s1004_ =>
+ (sep_matches_prefix _s1004_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1005_ _)) =>
+ (match (string_drop _s1004_ _s1005_) with
+ | _s1006_ =>
+ (reg_name_matches_prefix _s1006_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1007_ _)) =>
+ (match (string_drop _s1006_ _s1007_) with
+ | _s1008_ =>
+ (sep_matches_prefix _s1008_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1009_ _)) =>
+ match (string_drop _s1008_ _s1009_) with
+ | _s1010_ =>
+ match (hex_bits_5_matches_prefix
+ _s1010_) with
+ | Some ((shamt, existT _ _s1011_ _)) =>
+ let p0_ :=
+ string_drop _s1010_ _s1011_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5))).
+
+Definition _s980_ (_s981_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s982_ := _s981_ in
+ (if ((string_startswith _s982_ "addiw")) then
+ (match (string_drop _s982_ (projT1 (string_length "addiw"))) with
+ | _s983_ =>
+ (spc_matches_prefix _s983_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s984_ _)) =>
+ (match (string_drop _s983_ _s984_) with
+ | _s985_ =>
+ (reg_name_matches_prefix _s985_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s986_ _)) =>
+ (match (string_drop _s985_ _s986_) with
+ | _s987_ =>
+ (sep_matches_prefix _s987_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s988_ _)) =>
+ (match (string_drop _s987_ _s988_) with
+ | _s989_ =>
+ (reg_name_matches_prefix _s989_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s990_ _)) =>
+ (match (string_drop _s989_ _s990_) with
+ | _s991_ =>
+ (sep_matches_prefix _s991_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s992_ _)) =>
+ match (string_drop _s991_ _s992_) with
+ | _s993_ =>
+ match (hex_bits_12_matches_prefix _s993_) with
+ | Some ((imm, existT _ _s994_ _)) =>
+ let p0_ := string_drop _s993_ _s994_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s952_ (_s953_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s954_ := _s953_ in
+ (if ((string_startswith _s954_ "s")) then
+ (match (string_drop _s954_ (projT1 (string_length "s"))) with
+ | _s955_ =>
+ (size_mnemonic_matches_prefix _s955_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s956_ _)) =>
+ (match (string_drop _s955_ _s956_) with
+ | _s957_ =>
+ (maybe_aq_matches_prefix _s957_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s958_ _)) =>
+ (match (string_drop _s957_ _s958_) with
+ | _s959_ =>
+ (maybe_rl_matches_prefix _s959_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s960_ _)) =>
+ (match (string_drop _s959_ _s960_) with
+ | _s961_ =>
+ (spc_matches_prefix _s961_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s962_ _)) =>
+ (match (string_drop _s961_ _s962_) with
+ | _s963_ =>
+ (reg_name_matches_prefix _s963_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s964_ _)) =>
+ (match (string_drop _s963_ _s964_) with
+ | _s965_ =>
+ (sep_matches_prefix _s965_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s966_ _)) =>
+ (match (string_drop _s965_ _s966_) with
+ | _s967_ =>
+ (match (hex_bits_12_matches_prefix _s967_) with
+ | Some ((imm, existT _ _s968_ _)) =>
+ (match (string_drop _s967_ _s968_) with
+ | _s969_ =>
+ (opt_spc_matches_prefix _s969_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s970_ _)) =>
+ let _s971_ :=
+ string_drop _s969_ _s970_ in
+ (if ((string_startswith _s971_
+ "(")) then
+ (match (string_drop _s971_
+ (projT1
+ (string_length
+ "("))) with
+ | _s972_ =>
+ (opt_spc_matches_prefix
+ _s972_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s973_ _)) =>
+ (match (string_drop
+ _s972_
+ _s973_) with
+ | _s974_ =>
+ (reg_name_matches_prefix
+ _s974_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s975_ _)) =>
+ (match (string_drop
+ _s974_
+ _s975_) with
+ | _s976_ =>
+ (opt_spc_matches_prefix
+ _s976_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s977_ _)) =>
+ let _s978_ :=
+ string_drop
+ _s976_
+ _s977_ in
+ if
+ ((string_startswith
+ _s978_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s978_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, aq, rl, rs2, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s922_ (_s923_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s924_ := _s923_ in
+ (if ((string_startswith _s924_ "l")) then
+ (match (string_drop _s924_ (projT1 (string_length "l"))) with
+ | _s925_ =>
+ (size_mnemonic_matches_prefix _s925_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s926_ _)) =>
+ (match (string_drop _s925_ _s926_) with
+ | _s927_ =>
+ (maybe_u_matches_prefix _s927_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s928_ _)) =>
+ (match (string_drop _s927_ _s928_) with
+ | _s929_ =>
+ (maybe_aq_matches_prefix _s929_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s930_ _)) =>
+ (match (string_drop _s929_ _s930_) with
+ | _s931_ =>
+ (maybe_rl_matches_prefix _s931_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s932_ _)) =>
+ (match (string_drop _s931_ _s932_) with
+ | _s933_ =>
+ (spc_matches_prefix _s933_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s934_ _)) =>
+ (match (string_drop _s933_ _s934_) with
+ | _s935_ =>
+ (reg_name_matches_prefix _s935_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s936_ _)) =>
+ (match (string_drop _s935_ _s936_) with
+ | _s937_ =>
+ (sep_matches_prefix _s937_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s938_ _)) =>
+ (match (string_drop _s937_ _s938_) with
+ | _s939_ =>
+ (match (hex_bits_12_matches_prefix
+ _s939_) with
+ | Some ((imm, existT _ _s940_ _)) =>
+ (match (string_drop _s939_
+ _s940_) with
+ | _s941_ =>
+ (opt_spc_matches_prefix
+ _s941_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s942_ _)) =>
+ let _s943_ :=
+ string_drop _s941_
+ _s942_ in
+ (if ((string_startswith
+ _s943_ "("))
+ then
+ (match (string_drop
+ _s943_
+ (projT1
+ (string_length
+ "("))) with
+ | _s944_ =>
+ (opt_spc_matches_prefix
+ _s944_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s945_ _)) =>
+ (match (string_drop
+ _s944_
+ _s945_) with
+ | _s946_ =>
+ (reg_name_matches_prefix
+ _s946_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s947_ _)) =>
+ (match (string_drop
+ _s946_
+ _s947_) with
+ | _s948_ =>
+ (opt_spc_matches_prefix
+ _s948_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s949_ _)) =>
+ let _s950_ :=
+ string_drop
+ _s948_
+ _s949_ in
+ if
+ ((string_startswith
+ _s950_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s950_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s905_ (_s906_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s906_ with
+ | _s907_ =>
+ (rtype_mnemonic_matches_prefix _s907_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s908_ _)) =>
+ (match (string_drop _s907_ _s908_) with
+ | _s909_ =>
+ (spc_matches_prefix _s909_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s910_ _)) =>
+ (match (string_drop _s909_ _s910_) with
+ | _s911_ =>
+ (reg_name_matches_prefix _s911_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s912_ _)) =>
+ (match (string_drop _s911_ _s912_) with
+ | _s913_ =>
+ (sep_matches_prefix _s913_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s914_ _)) =>
+ (match (string_drop _s913_ _s914_) with
+ | _s915_ =>
+ (reg_name_matches_prefix _s915_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s916_ _)) =>
+ (match (string_drop _s915_ _s916_) with
+ | _s917_ =>
+ (sep_matches_prefix _s917_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s918_ _)) =>
+ (match (string_drop _s917_ _s918_) with
+ | _s919_ =>
+ (reg_name_matches_prefix _s919_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s920_ _)) =>
+ let p0_ :=
+ string_drop _s919_ _s920_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5))).
+
+Definition _s888_ (_s889_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6))) :=
+
+ (match _s889_ with
+ | _s890_ =>
+ (shiftiop_mnemonic_matches_prefix _s890_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s891_ _)) =>
+ (match (string_drop _s890_ _s891_) with
+ | _s892_ =>
+ (spc_matches_prefix _s892_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s893_ _)) =>
+ (match (string_drop _s892_ _s893_) with
+ | _s894_ =>
+ (reg_name_matches_prefix _s894_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s895_ _)) =>
+ (match (string_drop _s894_ _s895_) with
+ | _s896_ =>
+ (sep_matches_prefix _s896_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s897_ _)) =>
+ (match (string_drop _s896_ _s897_) with
+ | _s898_ =>
+ (reg_name_matches_prefix _s898_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s899_ _)) =>
+ (match (string_drop _s898_ _s899_) with
+ | _s900_ =>
+ (sep_matches_prefix _s900_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s901_ _)) =>
+ match (string_drop _s900_ _s901_) with
+ | _s902_ =>
+ match (hex_bits_6_matches_prefix
+ _s902_) with
+ | Some ((shamt, existT _ _s903_ _)) =>
+ let p0_ :=
+ string_drop _s902_ _s903_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6))).
+
+Definition _s871_ (_s872_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s872_ with
+ | _s873_ =>
+ (itype_mnemonic_matches_prefix _s873_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s874_ _)) =>
+ (match (string_drop _s873_ _s874_) with
+ | _s875_ =>
+ (spc_matches_prefix _s875_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s876_ _)) =>
+ (match (string_drop _s875_ _s876_) with
+ | _s877_ =>
+ (reg_name_matches_prefix _s877_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s878_ _)) =>
+ (match (string_drop _s877_ _s878_) with
+ | _s879_ =>
+ (sep_matches_prefix _s879_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s880_ _)) =>
+ (match (string_drop _s879_ _s880_) with
+ | _s881_ =>
+ (reg_name_matches_prefix _s881_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s882_ _)) =>
+ (match (string_drop _s881_ _s882_) with
+ | _s883_ =>
+ (sep_matches_prefix _s883_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s884_ _)) =>
+ match (string_drop _s883_ _s884_) with
+ | _s885_ =>
+ match (hex_bits_12_matches_prefix
+ _s885_) with
+ | Some ((imm, existT _ _s886_ _)) =>
+ let p0_ :=
+ string_drop _s885_ _s886_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12))).
+
+Definition _s854_ (_s855_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13))) :=
+
+ (match _s855_ with
+ | _s856_ =>
+ (btype_mnemonic_matches_prefix _s856_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s857_ _)) =>
+ (match (string_drop _s856_ _s857_) with
+ | _s858_ =>
+ (spc_matches_prefix _s858_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s859_ _)) =>
+ (match (string_drop _s858_ _s859_) with
+ | _s860_ =>
+ (reg_name_matches_prefix _s860_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s861_ _)) =>
+ (match (string_drop _s860_ _s861_) with
+ | _s862_ =>
+ (sep_matches_prefix _s862_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s863_ _)) =>
+ (match (string_drop _s862_ _s863_) with
+ | _s864_ =>
+ (reg_name_matches_prefix _s864_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s865_ _)) =>
+ (match (string_drop _s864_ _s865_) with
+ | _s866_ =>
+ (sep_matches_prefix _s866_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s867_ _)) =>
+ match (string_drop _s866_ _s867_) with
+ | _s868_ =>
+ match (hex_bits_13_matches_prefix
+ _s868_) with
+ | Some ((imm, existT _ _s869_ _)) =>
+ let p0_ :=
+ string_drop _s868_ _s869_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rs1, rs2, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13))).
+
+Definition _s838_ (_s839_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s840_ := _s839_ in
+ (if ((string_startswith _s840_ "jalr")) then
+ (match (string_drop _s840_ (projT1 (string_length "jalr"))) with
+ | _s841_ =>
+ (spc_matches_prefix _s841_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s842_ _)) =>
+ (match (string_drop _s841_ _s842_) with
+ | _s843_ =>
+ (reg_name_matches_prefix _s843_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s844_ _)) =>
+ (match (string_drop _s843_ _s844_) with
+ | _s845_ =>
+ (sep_matches_prefix _s845_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s846_ _)) =>
+ (match (string_drop _s845_ _s846_) with
+ | _s847_ =>
+ (reg_name_matches_prefix _s847_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s848_ _)) =>
+ (match (string_drop _s847_ _s848_) with
+ | _s849_ =>
+ (sep_matches_prefix _s849_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s850_ _)) =>
+ match (string_drop _s849_ _s850_) with
+ | _s851_ =>
+ match (hex_bits_12_matches_prefix _s851_) with
+ | Some ((imm, existT _ _s852_ _)) =>
+ let p0_ := string_drop _s851_ _s852_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s826_ (_s827_ : string)
+: M (option ((mword 5 * mword 21))) :=
+
+ let _s828_ := _s827_ in
+ (if ((string_startswith _s828_ "jal")) then
+ (match (string_drop _s828_ (projT1 (string_length "jal"))) with
+ | _s829_ =>
+ (spc_matches_prefix _s829_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s830_ _)) =>
+ (match (string_drop _s829_ _s830_) with
+ | _s831_ =>
+ (reg_name_matches_prefix _s831_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s832_ _)) =>
+ (match (string_drop _s831_ _s832_) with
+ | _s833_ =>
+ (sep_matches_prefix _s833_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s834_ _)) =>
+ match (string_drop _s833_ _s834_) with
+ | _s835_ =>
+ match (hex_bits_21_matches_prefix _s835_) with
+ | Some ((imm, existT _ _s836_ _)) =>
+ let p0_ := string_drop _s835_ _s836_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ else returnm (None : option ((mword 5 * mword 21))))
+ : M (option ((mword 5 * mword 21))).
+
+Definition _s813_ (_s814_ : string)
+: M (option ((uop * mword 5 * mword 20))) :=
+
+ (match _s814_ with
+ | _s815_ =>
+ (utype_mnemonic_matches_prefix _s815_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s816_ _)) =>
+ (match (string_drop _s815_ _s816_) with
+ | _s817_ =>
+ (spc_matches_prefix _s817_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s818_ _)) =>
+ (match (string_drop _s817_ _s818_) with
+ | _s819_ =>
+ (reg_name_matches_prefix _s819_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s820_ _)) =>
+ (match (string_drop _s819_ _s820_) with
+ | _s821_ =>
+ (sep_matches_prefix _s821_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s822_ _)) =>
+ match (string_drop _s821_ _s822_) with
+ | _s823_ =>
+ match (hex_bits_20_matches_prefix _s823_) with
+ | Some ((imm, existT _ _s824_ _)) =>
+ let p0_ := string_drop _s823_ _s824_ in
+ if ((generic_eq p0_ "")) then Some ((op, rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20))).
+
+Definition assembly_backwards (arg_ : string)
+: M (ast) :=
+
+ let _s825_ := arg_ in
+ (_s813_ _s825_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) =>
+ (if ((match w__0 with | Some ((op, rd, imm)) => true | _ => false end)) then
+ (_s813_ _s825_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) =>
+ (match w__1 with
+ | Some ((op, rd, imm)) => returnm ((UTYPE ((imm, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s826_ _s825_) >>= fun w__4 : option ((mword 5 * mword 21)) =>
+ (if ((match w__4 with | Some ((rd, imm)) => true | _ => false end)) then
+ (_s826_ _s825_) >>= fun w__5 : option ((mword 5 * mword 21)) =>
+ (match w__5 with
+ | Some ((rd, imm)) => returnm ((RISCV_JAL ((imm, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s838_ _s825_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm)) => true | _ => false end)) then
+ (_s838_ _s825_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm)) => returnm ((RISCV_JALR ((imm, rs1, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s854_ _s825_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm)) => true | _ => false end)) then
+ (_s854_ _s825_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm)) => returnm ((BTYPE ((imm, rs2, rs1, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s871_ _s825_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm)) => true | _ => false end)) then
+ (_s871_ _s825_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm)) => returnm ((ITYPE ((imm, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s888_ _s825_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt)) => true | _ => false end))
+ then
+ (_s888_ _s825_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTIOP ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s905_ _s825_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2)) => true | _ => false end))
+ then
+ (_s905_ _s825_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm ((RTYPE ((rs2, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s922_ _s825_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s922_ _s825_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) =>
+ returnm ((LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s952_ _s825_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s952_ _s825_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) =>
+ returnm ((STORE ((imm, rs2, rs1, size, aq, rl))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s980_ _s825_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s980_ _s825_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm)) =>
+ returnm ((ADDIW ((imm, rs1, rd))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s996_ _s825_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s996_ _s825_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTW ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1013_ _s825_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1013_ _s825_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm ((RTYPEW ((rs2, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1030_ _s825_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1030_ _s825_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm ((SHIFTIWOP ((shamt, rs1, rd, op))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1047_ _s825_) >>= fun w__52 : option ((mword 4 * mword 4)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1047_ _s825_) >>= fun w__53 : option ((mword 4 * mword 4)) =>
+ (match w__53 with
+ | Some ((pred, succ)) =>
+ returnm ((FENCE ((pred, succ))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1059_ _s825_) >>= fun w__56 : option ((mword 4 * mword 4)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1059_ _s825_) >>= fun w__57 : option ((mword 4 * mword 4)) =>
+ (match w__57 with
+ | Some ((pred, succ)) =>
+ returnm ((FENCE_TSO ((pred, succ))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else if ((generic_eq _s825_ "fence.i")) then
+ returnm ((FENCEI
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "ecall")) then
+ returnm ((ECALL
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "mret")) then
+ returnm ((MRET
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "sret")) then
+ returnm ((SRET
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "ebreak")) then
+ returnm ((EBREAK
+ (tt))
+ : ast )
+ else if ((generic_eq _s825_ "wfi")) then
+ returnm ((WFI
+ (tt))
+ : ast )
+ else
+ (_s1071_ _s825_) >>= fun w__60 : option ((mword 5 * mword 5)) =>
+ (if ((match w__60 with
+ | Some ((rs1, rs2)) => true
+ | _ => false
+ end)) then
+ (_s1071_ _s825_) >>= fun w__61 : option ((mword 5 * mword 5)) =>
+ (match w__61 with
+ | Some ((rs1, rs2)) =>
+ returnm ((SFENCE_VMA ((rs1, rs2))) : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1083_ _s825_) >>= fun w__64 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (if ((match w__64 with
+ | Some ((size, aq, rl, rd, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1083_ _s825_) >>= fun w__65 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (match w__65 with
+ | Some ((size, aq, rl, rd, rs1)) =>
+ returnm ((LOADRES
+ ((aq, rl, rs1, size, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1101_ _s825_) >>= fun w__68 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__68 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1101_ _s825_) >>= fun w__69 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__69 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ returnm ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1123_ _s825_) >>= fun w__72 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__72 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1123_ _s825_) >>= fun w__73 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__73 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ returnm ((AMO
+ ((op, aq, rl, rs2, rs1, width, rd)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else if ((generic_eq _s825_ "c.nop")) then
+ returnm ((C_NOP
+ (tt))
+ : ast )
+ else
+ (_s1147_ _s825_) >>= fun w__76 : option ((mword 3 * mword 8)) =>
+ (if ((match w__76 with
+ | Some ((rdc, nzimm)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s1147_ _s825_) >>= fun w__77 : option ((mword 3 * mword 8)) =>
+ (match w__77 with
+ | Some ((rdc, nzimm)) =>
+ returnm ((C_ADDI4SPN
+ ((rdc, nzimm)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1159_ _s825_) >>= fun w__80 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__80 with
+ | Some ((rdc, rsc, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1159_ _s825_) >>= fun w__81 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__81 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm ((C_LW
+ ((uimm, rsc, rdc)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1175_ _s825_) >>= fun w__84 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__84 with
+ | Some ((rdc, rsc, uimm)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1175_ _s825_) >>= fun w__85 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__85 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm ((C_LD
+ ((uimm, rsc, rdc)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1191_ _s825_) >>= fun w__88 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__88 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1191_ _s825_) >>= fun w__89 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__89 with
+ | Some ((rsc1, rsc2, uimm)) =>
+ returnm ((C_SW
+ ((uimm, rsc1, rsc2)))
+ : ast )
+ | _ => exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1207_ _s825_) >>= fun w__92 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__92 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1207_ _s825_) >>= fun w__93 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__93 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ returnm ((C_SD
+ ((uimm, rsc1, rsc2)))
+ : ast )
+ | _ =>
+ exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1223_ _s825_) >>= fun w__96 : option ((mword 5 * mword 6)) =>
+ (if ((match w__96 with
+ | Some ((rsd, nzi)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s1223_ _s825_) >>= fun w__97 : option ((mword 5 * mword 6)) =>
+ (match w__97 with
+ | Some ((rsd, nzi)) =>
+ returnm ((C_ADDI
+ ((nzi, rsd)))
+ : ast )
+ | _ =>
+ exit tt : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1235_ _s825_) >>= fun w__100 : option (mword 11) =>
+ (if ((match w__100 with
+ | Some (imm) =>
+ Z.eqb 64 32
+ | _ => false
+ end)) then
+ (_s1235_ _s825_) >>= fun w__101 : option (mword 11) =>
+ (match w__101 with
+ | Some (imm) =>
+ returnm ((C_JAL
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1243_ _s825_) >>= fun w__104 : option ((mword 5 * mword 6)) =>
+ (if ((match w__104 with
+ | Some
+ ((rsd, imm)) =>
+ Z.eqb 64
+ 64
+ | _ => false
+ end)) then
+ (_s1243_ _s825_) >>= fun w__105 : option ((mword 5 * mword 6)) =>
+ (match w__105 with
+ | Some
+ ((rsd, imm)) =>
+ returnm ((C_ADDIW
+ ((imm, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1255_ _s825_) >>= fun w__108 : option ((mword 5 * mword 6)) =>
+ (if ((match w__108 with
+ | Some
+ ((rd, imm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s1255_
+ _s825_) >>= fun w__109 : option ((mword 5 * mword 6)) =>
+ (match w__109 with
+ | Some
+ ((rd, imm)) =>
+ returnm ((C_LI
+ ((imm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1267_
+ _s825_) >>= fun w__112 : option (mword 6) =>
+ (if ((match w__112 with
+ | Some
+ (imm) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1267_
+ _s825_) >>= fun w__113 : option (mword 6) =>
+ (match w__113 with
+ | Some
+ (imm) =>
+ returnm ((C_ADDI16SP
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1275_
+ _s825_) >>= fun w__116 : option ((mword 5 * mword 6)) =>
+ (if ((match w__116 with
+ | Some
+ ((rd, imm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1275_
+ _s825_) >>= fun w__117 : option ((mword 5 * mword 6)) =>
+ (match w__117 with
+ | Some
+ ((rd, imm)) =>
+ returnm ((C_LUI
+ ((imm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1287_
+ _s825_) >>= fun w__120 : option ((mword 3 * mword 6)) =>
+ (if ((match w__120 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1287_
+ _s825_) >>= fun w__121 : option ((mword 3 * mword 6)) =>
+ (match w__121 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SRLI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1299_
+ _s825_) >>= fun w__124 : option ((mword 3 * mword 6)) =>
+ (if ((match w__124 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s1299_
+ _s825_) >>= fun w__125 : option ((mword 3 * mword 6)) =>
+ (match w__125 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SRAI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1311_
+ _s825_) >>= fun w__128 : option ((mword 3 * mword 6)) =>
+ (if
+ ((match w__128 with
+ | Some
+ ((rsd, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1311_
+ _s825_) >>= fun w__129 : option ((mword 3 * mword 6)) =>
+ (match w__129 with
+ | Some
+ ((rsd, imm)) =>
+ returnm ((C_ANDI
+ ((imm, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1323_
+ _s825_) >>= fun w__132 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__132 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1323_
+ _s825_) >>= fun w__133 : option ((mword 3 * mword 3)) =>
+ (match w__133 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_SUB
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1335_
+ _s825_) >>= fun w__136 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__136 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1335_
+ _s825_) >>= fun w__137 : option ((mword 3 * mword 3)) =>
+ (match w__137 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_XOR
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1347_
+ _s825_) >>= fun w__140 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__140 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1347_
+ _s825_) >>= fun w__141 : option ((mword 3 * mword 3)) =>
+ (match w__141 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_OR
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1359_
+ _s825_) >>= fun w__144 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__144 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1359_
+ _s825_) >>= fun w__145 : option ((mword 3 * mword 3)) =>
+ (match w__145 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_AND
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1371_
+ _s825_) >>= fun w__148 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__148 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1371_
+ _s825_) >>= fun w__149 : option ((mword 3 * mword 3)) =>
+ (match w__149 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_SUBW
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1383_
+ _s825_) >>= fun w__152 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__152 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1383_
+ _s825_) >>= fun w__153 : option ((mword 3 * mword 3)) =>
+ (match w__153 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_ADDW
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1395_
+ _s825_) >>= fun w__156 : option (mword 11) =>
+ (if
+ ((match w__156 with
+ | Some
+ (imm) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1395_
+ _s825_) >>= fun w__157 : option (mword 11) =>
+ (match w__157 with
+ | Some
+ (imm) =>
+ returnm ((C_J
+ (imm))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1403_
+ _s825_) >>= fun w__160 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__160 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1403_
+ _s825_) >>= fun w__161 : option ((mword 3 * mword 8)) =>
+ (match w__161 with
+ | Some
+ ((rs, imm)) =>
+ returnm ((C_BEQZ
+ ((imm, rs)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1415_
+ _s825_) >>= fun w__164 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__164 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1415_
+ _s825_) >>= fun w__165 : option ((mword 3 * mword 8)) =>
+ (match w__165 with
+ | Some
+ ((rs, imm)) =>
+ returnm ((C_BNEZ
+ ((imm, rs)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1427_
+ _s825_) >>= fun w__168 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__168 with
+ | Some
+ ((rsd, shamt)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1427_
+ _s825_) >>= fun w__169 : option ((mword 5 * mword 6)) =>
+ (match w__169 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm ((C_SLLI
+ ((shamt, rsd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1439_
+ _s825_) >>= fun w__172 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__172 with
+ | Some
+ ((rd, uimm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1439_
+ _s825_) >>= fun w__173 : option ((mword 5 * mword 6)) =>
+ (match w__173 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_LWSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1451_
+ _s825_) >>= fun w__176 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__176 with
+ | Some
+ ((rd, uimm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 64
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s1451_
+ _s825_) >>= fun w__177 : option ((mword 5 * mword 6)) =>
+ (match w__177 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_LDSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1463_
+ _s825_) >>= fun w__180 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__180 with
+ | Some
+ ((rd, uimm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1463_
+ _s825_) >>= fun w__181 : option ((mword 5 * mword 6)) =>
+ (match w__181 with
+ | Some
+ ((rd, uimm)) =>
+ returnm ((C_SWSP
+ ((uimm, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1475_
+ _s825_) >>= fun w__184 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__184 with
+ | Some
+ ((rs2, uimm)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1475_
+ _s825_) >>= fun w__185 : option ((mword 5 * mword 6)) =>
+ (match w__185 with
+ | Some
+ ((rs2, uimm)) =>
+ returnm ((C_SDSP
+ ((uimm, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1487_
+ _s825_) >>= fun w__188 : option (mword 5) =>
+ (if
+ ((match w__188 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1487_
+ _s825_) >>= fun w__189 : option (mword 5) =>
+ (match w__189 with
+ | Some
+ (rs1) =>
+ returnm ((C_JR
+ (rs1))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1495_
+ _s825_) >>= fun w__192 : option (mword 5) =>
+ (if
+ ((match w__192 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s1495_
+ _s825_) >>= fun w__193 : option (mword 5) =>
+ (match w__193 with
+ | Some
+ (rs1) =>
+ returnm ((C_JALR
+ (rs1))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1503_
+ _s825_) >>= fun w__196 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__196 with
+ | Some
+ ((rd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1503_
+ _s825_) >>= fun w__197 : option ((mword 5 * mword 5)) =>
+ (match w__197 with
+ | Some
+ ((rd, rs2)) =>
+ returnm ((C_MV
+ ((rd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else if
+ ((generic_eq
+ _s825_
+ "c.ebreak"))
+ then
+ returnm ((C_EBREAK
+ (tt))
+ : ast )
+ else
+ (_s1515_
+ _s825_) >>= fun w__200 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__200 with
+ | Some
+ ((rsd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s1515_
+ _s825_) >>= fun w__201 : option ((mword 5 * mword 5)) =>
+ (match w__201 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm ((C_ADD
+ ((rsd, rs2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1527_
+ _s825_) >>= fun w__204 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__204 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1527_
+ _s825_) >>= fun w__205 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__205 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ returnm ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1544_
+ _s825_) >>= fun w__208 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__208 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1544_
+ _s825_) >>= fun w__209 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__209 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((DIV
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1562_
+ _s825_) >>= fun w__212 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__212 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1562_
+ _s825_) >>= fun w__213 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__213 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((REM
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1580_
+ _s825_) >>= fun w__216 : option ((mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1580_
+ _s825_) >>= fun w__217 : option ((mword 5 * mword 5 * mword 5)) =>
+ (match w__217 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ returnm ((MULW
+ ((rs2, rs1, rd)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1596_
+ _s825_) >>= fun w__220 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1596_
+ _s825_) >>= fun w__221 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__221 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((DIVW
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1615_
+ _s825_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s1615_
+ _s825_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm ((REMW
+ ((rs2, rs1, rd, s)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1634_
+ _s825_) >>= fun w__228 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1634_
+ _s825_) >>= fun w__229 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__229 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm ((CSR
+ ((csr, rs1, rd, true, op)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1652_
+ _s825_) >>= fun w__232 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1652_
+ _s825_) >>= fun w__233 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__233 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm ((CSR
+ ((csr, rs1, rd, false, op)))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else if
+ ((generic_eq
+ _s825_
+ "uret"))
+ then
+ returnm ((URET
+ (tt))
+ : ast )
+ else
+ (_s1669_
+ _s825_) >>= fun w__236 : option (mword 32) =>
+ (if
+ ((match w__236 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1669_
+ _s825_) >>= fun w__237 : option (mword 32) =>
+ (match w__237 with
+ | Some
+ (s) =>
+ returnm ((ILLEGAL
+ (s))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ (_s1677_
+ _s825_) >>= fun w__240 : option (mword 16) =>
+ (if
+ ((match w__240 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s1677_
+ _s825_) >>= fun w__241 : option (mword 16) =>
+ (match w__241 with
+ | Some
+ (s) =>
+ returnm ((C_ILLEGAL
+ (s))
+ : ast )
+ | _ =>
+ exit tt
+ : M (ast)
+ end)
+ : M (ast)
+ else
+ assert_exp' false "Pattern match failure at unknown location" >>= fun _ =>
+ exit tt)
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast))
+ : M (ast).
+
+Definition assembly_forwards_matches (arg_ : ast)
+: bool :=
+
+ match arg_ with
+ | UTYPE ((imm, rd, op)) => true
+ | RISCV_JAL ((imm, rd)) => true
+ | RISCV_JALR ((imm, rs1, rd)) => true
+ | BTYPE ((imm, rs2, rs1, op)) => true
+ | ITYPE ((imm, rs1, rd, op)) => true
+ | SHIFTIOP ((shamt, rs1, rd, op)) => true
+ | RTYPE ((rs2, rs1, rd, op)) => true
+ | LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl)) => true
+ | STORE ((imm, rs2, rs1, size, aq, rl)) => true
+ | ADDIW ((imm, rs1, rd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTW ((shamt, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | RTYPEW ((rs2, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | FENCE ((pred, succ)) => true
+ | FENCE_TSO ((pred, succ)) => true
+ | FENCEI (tt) => true
+ | ECALL (tt) => true
+ | MRET (tt) => true
+ | SRET (tt) => true
+ | EBREAK (tt) => true
+ | WFI (tt) => true
+ | SFENCE_VMA ((rs1, rs2)) => true
+ | LOADRES ((aq, rl, rs1, size, rd)) => true
+ | STORECON ((aq, rl, rs2, rs1, size, rd)) => true
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => true
+ | C_NOP (tt) => true
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then true else false
+ | C_LW ((uimm, rsc, rdc)) => true
+ | C_LD ((uimm, rsc, rdc)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_SW ((uimm, rsc1, rsc2)) => true
+ | C_SD ((uimm, rsc1, rsc2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_ADDI ((nzi, rsd)) =>
+ if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_JAL (imm) => if sumbool_of_bool ((Z.eqb 64 32)) then true else false
+ | C_ADDIW ((imm, rsd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_LI ((imm, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_ADDI16SP (imm) =>
+ if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_LUI ((imm, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd))
+ (projT1
+ (regidx_to_regno sp))))
+ (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))
+ : bool))) then
+ true
+ else false
+ | C_SRLI ((shamt, rsd)) =>
+ if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_SRAI ((shamt, rsd)) =>
+ if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true else false
+ | C_ANDI ((imm, rsd)) => true
+ | C_SUB ((rsd, rs2)) => true
+ | C_XOR ((rsd, rs2)) => true
+ | C_OR ((rsd, rs2)) => true
+ | C_AND ((rsd, rs2)) => true
+ | C_SUBW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_ADDW ((rsd, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_J (imm) => true
+ | C_BEQZ ((imm, rs)) => true
+ | C_BNEZ ((imm, rs)) => true
+ | C_SLLI ((shamt, rsd)) =>
+ if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rsd)) (projT1 (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_LWSP ((uimm, rd)) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_LDSP ((uimm, rd)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ (Z.eqb 64 64))) then
+ true
+ else false
+ | C_SWSP ((uimm, rd)) => true
+ | C_SDSP ((uimm, rs2)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | C_JR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_JALR (rs1) =>
+ if sumbool_of_bool ((projT1
+ (neq_int (projT1 (regidx_to_regno rs1)) (projT1 (regidx_to_regno zreg)))))
+ then
+ true
+ else false
+ | C_MV ((rd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rd)) (projT1 (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | C_EBREAK (tt) => true
+ | C_ADD ((rsd, rs2)) =>
+ if sumbool_of_bool ((andb
+ (projT1
+ (neq_int (projT1 (regidx_to_regno rsd))
+ (projT1
+ (regidx_to_regno zreg))))
+ ((projT1
+ (neq_int (projT1 (regidx_to_regno rs2))
+ (projT1
+ (regidx_to_regno zreg))))
+ : bool))) then
+ true
+ else false
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => true
+ | DIV ((rs2, rs1, rd, s)) => true
+ | REM ((rs2, rs1, rd, s)) => true
+ | MULW ((rs2, rs1, rd)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | DIVW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | REMW ((rs2, rs1, rd, s)) => if sumbool_of_bool ((Z.eqb 64 64)) then true else false
+ | CSR ((csr, rs1, rd, true, op)) => true
+ | CSR ((csr, rs1, rd, false, op)) => true
+ | URET (tt) => true
+ | ILLEGAL (s) => true
+ | C_ILLEGAL (s) => true
+ end.
+
+Definition _s2549_ (_s2550_ : string)
+: M (option (mword 16)) :=
+
+ let _s2551_ := _s2550_ in
+ (if ((string_startswith _s2551_ "c.illegal")) then
+ (match (string_drop _s2551_ (projT1 (string_length "c.illegal"))) with
+ | _s2552_ =>
+ (spc_matches_prefix _s2552_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2553_ _)) =>
+ match (string_drop _s2552_ _s2553_) with
+ | _s2554_ =>
+ match (hex_bits_16_matches_prefix _s2554_) with
+ | Some ((s, existT _ _s2555_ _)) =>
+ let p0_ := string_drop _s2554_ _s2555_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 16))
+ end)
+ : M (option (mword 16))
+ else returnm (None : option (mword 16)))
+ : M (option (mword 16)).
+
+Definition _s2541_ (_s2542_ : string)
+: M (option (mword 32)) :=
+
+ let _s2543_ := _s2542_ in
+ (if ((string_startswith _s2543_ "illegal")) then
+ (match (string_drop _s2543_ (projT1 (string_length "illegal"))) with
+ | _s2544_ =>
+ (spc_matches_prefix _s2544_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2545_ _)) =>
+ match (string_drop _s2544_ _s2545_) with
+ | _s2546_ =>
+ match (hex_bits_32_matches_prefix _s2546_) with
+ | Some ((s, existT _ _s2547_ _)) =>
+ let p0_ := string_drop _s2546_ _s2547_ in
+ if ((generic_eq p0_ "")) then Some (s)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 32))
+ end)
+ : M (option (mword 32))
+ else returnm (None : option (mword 32)))
+ : M (option (mword 32)).
+
+Definition _s2524_ (_s2525_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s2525_ with
+ | _s2526_ =>
+ (csr_mnemonic_matches_prefix _s2526_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2527_ _)) =>
+ (match (string_drop _s2526_ _s2527_) with
+ | _s2528_ =>
+ (spc_matches_prefix _s2528_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2529_ _)) =>
+ (match (string_drop _s2528_ _s2529_) with
+ | _s2530_ =>
+ (reg_name_matches_prefix _s2530_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2531_ _)) =>
+ (match (string_drop _s2530_ _s2531_) with
+ | _s2532_ =>
+ (sep_matches_prefix _s2532_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2533_ _)) =>
+ (match (string_drop _s2532_ _s2533_) with
+ | _s2534_ =>
+ (reg_name_matches_prefix _s2534_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2535_ _)) =>
+ (match (string_drop _s2534_ _s2535_) with
+ | _s2536_ =>
+ (sep_matches_prefix _s2536_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2537_ _)) =>
+ (match (string_drop _s2536_ _s2537_) with
+ | _s2538_ =>
+ (csr_name_map_matches_prefix _s2538_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s2539_ _)) =>
+ let p0_ :=
+ string_drop _s2538_ _s2539_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s2506_ (_s2507_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s2507_ with
+ | _s2508_ =>
+ (csr_mnemonic_matches_prefix _s2508_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2509_ _)) =>
+ let _s2510_ := string_drop _s2508_ _s2509_ in
+ (if ((string_startswith _s2510_ "i")) then
+ (match (string_drop _s2510_ (projT1 (string_length "i"))) with
+ | _s2511_ =>
+ (spc_matches_prefix _s2511_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2512_ _)) =>
+ (match (string_drop _s2511_ _s2512_) with
+ | _s2513_ =>
+ (reg_name_matches_prefix _s2513_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2514_ _)) =>
+ (match (string_drop _s2513_ _s2514_) with
+ | _s2515_ =>
+ (sep_matches_prefix _s2515_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2516_ _)) =>
+ (match (string_drop _s2515_ _s2516_) with
+ | _s2517_ =>
+ (match (hex_bits_5_matches_prefix _s2517_) with
+ | Some ((rs1, existT _ _s2518_ _)) =>
+ (match (string_drop _s2517_ _s2518_) with
+ | _s2519_ =>
+ (sep_matches_prefix _s2519_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2520_ _)) =>
+ (match (string_drop _s2519_ _s2520_) with
+ | _s2521_ =>
+ (csr_name_map_matches_prefix _s2521_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s2522_ _)) =>
+ let p0_ :=
+ string_drop _s2521_ _s2522_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, csr))
+ else None
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12))).
+
+Definition _s2487_ (_s2488_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2489_ := _s2488_ in
+ (if ((string_startswith _s2489_ "rem")) then
+ (match (string_drop _s2489_ (projT1 (string_length "rem"))) with
+ | _s2490_ =>
+ (maybe_not_u_matches_prefix _s2490_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2491_ _)) =>
+ let _s2492_ := string_drop _s2490_ _s2491_ in
+ (if ((string_startswith _s2492_ "w")) then
+ (match (string_drop _s2492_ (projT1 (string_length "w"))) with
+ | _s2493_ =>
+ (spc_matches_prefix _s2493_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2494_ _)) =>
+ (match (string_drop _s2493_ _s2494_) with
+ | _s2495_ =>
+ (reg_name_matches_prefix _s2495_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2496_ _)) =>
+ (match (string_drop _s2495_ _s2496_) with
+ | _s2497_ =>
+ (sep_matches_prefix _s2497_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2498_ _)) =>
+ (match (string_drop _s2497_ _s2498_) with
+ | _s2499_ =>
+ (reg_name_matches_prefix _s2499_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2500_ _)) =>
+ (match (string_drop _s2499_ _s2500_) with
+ | _s2501_ =>
+ (sep_matches_prefix _s2501_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2502_ _)) =>
+ (match (string_drop _s2501_ _s2502_) with
+ | _s2503_ =>
+ (reg_name_matches_prefix _s2503_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2504_ _)) =>
+ let p0_ :=
+ string_drop _s2503_
+ _s2504_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2468_ (_s2469_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2470_ := _s2469_ in
+ (if ((string_startswith _s2470_ "div")) then
+ (match (string_drop _s2470_ (projT1 (string_length "div"))) with
+ | _s2471_ =>
+ (maybe_not_u_matches_prefix _s2471_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2472_ _)) =>
+ let _s2473_ := string_drop _s2471_ _s2472_ in
+ (if ((string_startswith _s2473_ "w")) then
+ (match (string_drop _s2473_ (projT1 (string_length "w"))) with
+ | _s2474_ =>
+ (spc_matches_prefix _s2474_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2475_ _)) =>
+ (match (string_drop _s2474_ _s2475_) with
+ | _s2476_ =>
+ (reg_name_matches_prefix _s2476_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2477_ _)) =>
+ (match (string_drop _s2476_ _s2477_) with
+ | _s2478_ =>
+ (sep_matches_prefix _s2478_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2479_ _)) =>
+ (match (string_drop _s2478_ _s2479_) with
+ | _s2480_ =>
+ (reg_name_matches_prefix _s2480_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2481_ _)) =>
+ (match (string_drop _s2480_ _s2481_) with
+ | _s2482_ =>
+ (sep_matches_prefix _s2482_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2483_ _)) =>
+ (match (string_drop _s2482_ _s2483_) with
+ | _s2484_ =>
+ (reg_name_matches_prefix _s2484_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2485_ _)) =>
+ let p0_ :=
+ string_drop _s2484_
+ _s2485_ in
+ if ((generic_eq p0_ ""))
+ then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2452_ (_s2453_ : string)
+: M (option ((mword 5 * mword 5 * mword 5))) :=
+
+ let _s2454_ := _s2453_ in
+ (if ((string_startswith _s2454_ "mulw")) then
+ (match (string_drop _s2454_ (projT1 (string_length "mulw"))) with
+ | _s2455_ =>
+ (spc_matches_prefix _s2455_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2456_ _)) =>
+ (match (string_drop _s2455_ _s2456_) with
+ | _s2457_ =>
+ (reg_name_matches_prefix _s2457_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2458_ _)) =>
+ (match (string_drop _s2457_ _s2458_) with
+ | _s2459_ =>
+ (sep_matches_prefix _s2459_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2460_ _)) =>
+ (match (string_drop _s2459_ _s2460_) with
+ | _s2461_ =>
+ (reg_name_matches_prefix _s2461_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2462_ _)) =>
+ (match (string_drop _s2461_ _s2462_) with
+ | _s2463_ =>
+ (sep_matches_prefix _s2463_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2464_ _)) =>
+ (match (string_drop _s2463_ _s2464_) with
+ | _s2465_ =>
+ (reg_name_matches_prefix _s2465_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s2466_ _)) =>
+ let p0_ :=
+ string_drop _s2465_ _s2466_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5 * mword 5))).
+
+Definition _s2434_ (_s2435_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2436_ := _s2435_ in
+ (if ((string_startswith _s2436_ "rem")) then
+ (match (string_drop _s2436_ (projT1 (string_length "rem"))) with
+ | _s2437_ =>
+ (maybe_not_u_matches_prefix _s2437_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2438_ _)) =>
+ (match (string_drop _s2437_ _s2438_) with
+ | _s2439_ =>
+ (spc_matches_prefix _s2439_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2440_ _)) =>
+ (match (string_drop _s2439_ _s2440_) with
+ | _s2441_ =>
+ (reg_name_matches_prefix _s2441_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2442_ _)) =>
+ (match (string_drop _s2441_ _s2442_) with
+ | _s2443_ =>
+ (sep_matches_prefix _s2443_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2444_ _)) =>
+ (match (string_drop _s2443_ _s2444_) with
+ | _s2445_ =>
+ (reg_name_matches_prefix _s2445_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2446_ _)) =>
+ (match (string_drop _s2445_ _s2446_) with
+ | _s2447_ =>
+ (sep_matches_prefix _s2447_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2448_ _)) =>
+ (match (string_drop _s2447_ _s2448_) with
+ | _s2449_ =>
+ (reg_name_matches_prefix _s2449_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2450_ _)) =>
+ let p0_ :=
+ string_drop _s2449_ _s2450_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2416_ (_s2417_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s2418_ := _s2417_ in
+ (if ((string_startswith _s2418_ "div")) then
+ (match (string_drop _s2418_ (projT1 (string_length "div"))) with
+ | _s2419_ =>
+ (maybe_not_u_matches_prefix _s2419_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s2420_ _)) =>
+ (match (string_drop _s2419_ _s2420_) with
+ | _s2421_ =>
+ (spc_matches_prefix _s2421_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2422_ _)) =>
+ (match (string_drop _s2421_ _s2422_) with
+ | _s2423_ =>
+ (reg_name_matches_prefix _s2423_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2424_ _)) =>
+ (match (string_drop _s2423_ _s2424_) with
+ | _s2425_ =>
+ (sep_matches_prefix _s2425_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2426_ _)) =>
+ (match (string_drop _s2425_ _s2426_) with
+ | _s2427_ =>
+ (reg_name_matches_prefix _s2427_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2428_ _)) =>
+ (match (string_drop _s2427_ _s2428_) with
+ | _s2429_ =>
+ (sep_matches_prefix _s2429_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2430_ _)) =>
+ (match (string_drop _s2429_ _s2430_) with
+ | _s2431_ =>
+ (reg_name_matches_prefix _s2431_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s2432_ _)) =>
+ let p0_ :=
+ string_drop _s2431_ _s2432_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((s, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2399_ (_s2400_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s2400_ with
+ | _s2401_ =>
+ (mul_mnemonic_matches_prefix _s2401_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s2402_ _)) =>
+ (match (string_drop _s2401_ _s2402_) with
+ | _s2403_ =>
+ (spc_matches_prefix _s2403_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2404_ _)) =>
+ (match (string_drop _s2403_ _s2404_) with
+ | _s2405_ =>
+ (reg_name_matches_prefix _s2405_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2406_ _)) =>
+ (match (string_drop _s2405_ _s2406_) with
+ | _s2407_ =>
+ (sep_matches_prefix _s2407_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2408_ _)) =>
+ (match (string_drop _s2407_ _s2408_) with
+ | _s2409_ =>
+ (reg_name_matches_prefix _s2409_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2410_ _)) =>
+ (match (string_drop _s2409_ _s2410_) with
+ | _s2411_ =>
+ (sep_matches_prefix _s2411_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2412_ _)) =>
+ (match (string_drop _s2411_ _s2412_) with
+ | _s2413_ =>
+ (reg_name_matches_prefix _s2413_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2414_ _)) =>
+ let p0_ :=
+ string_drop _s2413_ _s2414_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s2387_ (_s2388_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s2389_ := _s2388_ in
+ (if ((string_startswith _s2389_ "c.add")) then
+ (match (string_drop _s2389_ (projT1 (string_length "c.add"))) with
+ | _s2390_ =>
+ (spc_matches_prefix _s2390_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2391_ _)) =>
+ (match (string_drop _s2390_ _s2391_) with
+ | _s2392_ =>
+ (reg_name_matches_prefix _s2392_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2393_ _)) =>
+ (match (string_drop _s2392_ _s2393_) with
+ | _s2394_ =>
+ (sep_matches_prefix _s2394_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2395_ _)) =>
+ (match (string_drop _s2394_ _s2395_) with
+ | _s2396_ =>
+ (reg_name_matches_prefix _s2396_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2397_ _)) =>
+ let p0_ := string_drop _s2396_ _s2397_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s2375_ (_s2376_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s2377_ := _s2376_ in
+ (if ((string_startswith _s2377_ "c.mv")) then
+ (match (string_drop _s2377_ (projT1 (string_length "c.mv"))) with
+ | _s2378_ =>
+ (spc_matches_prefix _s2378_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2379_ _)) =>
+ (match (string_drop _s2378_ _s2379_) with
+ | _s2380_ =>
+ (reg_name_matches_prefix _s2380_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2381_ _)) =>
+ (match (string_drop _s2380_ _s2381_) with
+ | _s2382_ =>
+ (sep_matches_prefix _s2382_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2383_ _)) =>
+ (match (string_drop _s2382_ _s2383_) with
+ | _s2384_ =>
+ (reg_name_matches_prefix _s2384_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2385_ _)) =>
+ let p0_ := string_drop _s2384_ _s2385_ in
+ if ((generic_eq p0_ "")) then Some ((rd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s2367_ (_s2368_ : string)
+: M (option (mword 5)) :=
+
+ let _s2369_ := _s2368_ in
+ (if ((string_startswith _s2369_ "c.jalr")) then
+ (match (string_drop _s2369_ (projT1 (string_length "c.jalr"))) with
+ | _s2370_ =>
+ (spc_matches_prefix _s2370_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2371_ _)) =>
+ (match (string_drop _s2370_ _s2371_) with
+ | _s2372_ =>
+ (reg_name_matches_prefix _s2372_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s2373_ _)) =>
+ let p0_ := string_drop _s2372_ _s2373_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s2359_ (_s2360_ : string)
+: M (option (mword 5)) :=
+
+ let _s2361_ := _s2360_ in
+ (if ((string_startswith _s2361_ "c.jr")) then
+ (match (string_drop _s2361_ (projT1 (string_length "c.jr"))) with
+ | _s2362_ =>
+ (spc_matches_prefix _s2362_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2363_ _)) =>
+ (match (string_drop _s2362_ _s2363_) with
+ | _s2364_ =>
+ (reg_name_matches_prefix _s2364_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s2365_ _)) =>
+ let p0_ := string_drop _s2364_ _s2365_ in
+ if ((generic_eq p0_ "")) then Some (rs1)
+ else None
+ | _ => None
+ end)
+ : option (mword 5))
+ end)
+ : M (option (mword 5))
+ | _ => returnm (None : option (mword 5))
+ end)
+ : M (option (mword 5))
+ end)
+ : M (option (mword 5))
+ else returnm (None : option (mword 5)))
+ : M (option (mword 5)).
+
+Definition _s2347_ (_s2348_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2349_ := _s2348_ in
+ (if ((string_startswith _s2349_ "c.sdsp")) then
+ (match (string_drop _s2349_ (projT1 (string_length "c.sdsp"))) with
+ | _s2350_ =>
+ (spc_matches_prefix _s2350_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2351_ _)) =>
+ (match (string_drop _s2350_ _s2351_) with
+ | _s2352_ =>
+ (reg_name_matches_prefix _s2352_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s2353_ _)) =>
+ (match (string_drop _s2352_ _s2353_) with
+ | _s2354_ =>
+ (sep_matches_prefix _s2354_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2355_ _)) =>
+ match (string_drop _s2354_ _s2355_) with
+ | _s2356_ =>
+ match (hex_bits_6_matches_prefix _s2356_) with
+ | Some ((uimm, existT _ _s2357_ _)) =>
+ let p0_ := string_drop _s2356_ _s2357_ in
+ if ((generic_eq p0_ "")) then Some ((rs2, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2335_ (_s2336_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2337_ := _s2336_ in
+ (if ((string_startswith _s2337_ "c.swsp")) then
+ (match (string_drop _s2337_ (projT1 (string_length "c.swsp"))) with
+ | _s2338_ =>
+ (spc_matches_prefix _s2338_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2339_ _)) =>
+ (match (string_drop _s2338_ _s2339_) with
+ | _s2340_ =>
+ (reg_name_matches_prefix _s2340_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2341_ _)) =>
+ (match (string_drop _s2340_ _s2341_) with
+ | _s2342_ =>
+ (sep_matches_prefix _s2342_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2343_ _)) =>
+ match (string_drop _s2342_ _s2343_) with
+ | _s2344_ =>
+ match (hex_bits_6_matches_prefix _s2344_) with
+ | Some ((uimm, existT _ _s2345_ _)) =>
+ let p0_ := string_drop _s2344_ _s2345_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2323_ (_s2324_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2325_ := _s2324_ in
+ (if ((string_startswith _s2325_ "c.ldsp")) then
+ (match (string_drop _s2325_ (projT1 (string_length "c.ldsp"))) with
+ | _s2326_ =>
+ (spc_matches_prefix _s2326_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2327_ _)) =>
+ (match (string_drop _s2326_ _s2327_) with
+ | _s2328_ =>
+ (reg_name_matches_prefix _s2328_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2329_ _)) =>
+ (match (string_drop _s2328_ _s2329_) with
+ | _s2330_ =>
+ (sep_matches_prefix _s2330_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2331_ _)) =>
+ match (string_drop _s2330_ _s2331_) with
+ | _s2332_ =>
+ match (hex_bits_6_matches_prefix _s2332_) with
+ | Some ((uimm, existT _ _s2333_ _)) =>
+ let p0_ := string_drop _s2332_ _s2333_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2311_ (_s2312_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2313_ := _s2312_ in
+ (if ((string_startswith _s2313_ "c.lwsp")) then
+ (match (string_drop _s2313_ (projT1 (string_length "c.lwsp"))) with
+ | _s2314_ =>
+ (spc_matches_prefix _s2314_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2315_ _)) =>
+ (match (string_drop _s2314_ _s2315_) with
+ | _s2316_ =>
+ (reg_name_matches_prefix _s2316_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2317_ _)) =>
+ (match (string_drop _s2316_ _s2317_) with
+ | _s2318_ =>
+ (sep_matches_prefix _s2318_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2319_ _)) =>
+ match (string_drop _s2318_ _s2319_) with
+ | _s2320_ =>
+ match (hex_bits_6_matches_prefix _s2320_) with
+ | Some ((uimm, existT _ _s2321_ _)) =>
+ let p0_ := string_drop _s2320_ _s2321_ in
+ if ((generic_eq p0_ "")) then Some ((rd, uimm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2299_ (_s2300_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2301_ := _s2300_ in
+ (if ((string_startswith _s2301_ "c.slli")) then
+ (match (string_drop _s2301_ (projT1 (string_length "c.slli"))) with
+ | _s2302_ =>
+ (spc_matches_prefix _s2302_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2303_ _)) =>
+ (match (string_drop _s2302_ _s2303_) with
+ | _s2304_ =>
+ (reg_name_matches_prefix _s2304_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2305_ _)) =>
+ (match (string_drop _s2304_ _s2305_) with
+ | _s2306_ =>
+ (sep_matches_prefix _s2306_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2307_ _)) =>
+ match (string_drop _s2306_ _s2307_) with
+ | _s2308_ =>
+ match (hex_bits_6_matches_prefix _s2308_) with
+ | Some ((shamt, existT _ _s2309_ _)) =>
+ let p0_ := string_drop _s2308_ _s2309_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2287_ (_s2288_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2289_ := _s2288_ in
+ (if ((string_startswith _s2289_ "c.bnez")) then
+ (match (string_drop _s2289_ (projT1 (string_length "c.bnez"))) with
+ | _s2290_ =>
+ (spc_matches_prefix _s2290_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2291_ _)) =>
+ (match (string_drop _s2290_ _s2291_) with
+ | _s2292_ =>
+ (creg_name_matches_prefix _s2292_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s2293_ _)) =>
+ (match (string_drop _s2292_ _s2293_) with
+ | _s2294_ =>
+ (sep_matches_prefix _s2294_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2295_ _)) =>
+ match (string_drop _s2294_ _s2295_) with
+ | _s2296_ =>
+ match (hex_bits_8_matches_prefix _s2296_) with
+ | Some ((imm, existT _ _s2297_ _)) =>
+ let p0_ := string_drop _s2296_ _s2297_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s2275_ (_s2276_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2277_ := _s2276_ in
+ (if ((string_startswith _s2277_ "c.beqz")) then
+ (match (string_drop _s2277_ (projT1 (string_length "c.beqz"))) with
+ | _s2278_ =>
+ (spc_matches_prefix _s2278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2279_ _)) =>
+ (match (string_drop _s2278_ _s2279_) with
+ | _s2280_ =>
+ (creg_name_matches_prefix _s2280_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s2281_ _)) =>
+ (match (string_drop _s2280_ _s2281_) with
+ | _s2282_ =>
+ (sep_matches_prefix _s2282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2283_ _)) =>
+ match (string_drop _s2282_ _s2283_) with
+ | _s2284_ =>
+ match (hex_bits_8_matches_prefix _s2284_) with
+ | Some ((imm, existT _ _s2285_ _)) =>
+ let p0_ := string_drop _s2284_ _s2285_ in
+ if ((generic_eq p0_ "")) then Some ((rs, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s2267_ (_s2268_ : string)
+: M (option (mword 11)) :=
+
+ let _s2269_ := _s2268_ in
+ (if ((string_startswith _s2269_ "c.j")) then
+ (match (string_drop _s2269_ (projT1 (string_length "c.j"))) with
+ | _s2270_ =>
+ (spc_matches_prefix _s2270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2271_ _)) =>
+ match (string_drop _s2270_ _s2271_) with
+ | _s2272_ =>
+ match (hex_bits_11_matches_prefix _s2272_) with
+ | Some ((imm, existT _ _s2273_ _)) =>
+ let p0_ := string_drop _s2272_ _s2273_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s2255_ (_s2256_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2257_ := _s2256_ in
+ (if ((string_startswith _s2257_ "c.addw")) then
+ (match (string_drop _s2257_ (projT1 (string_length "c.addw"))) with
+ | _s2258_ =>
+ (spc_matches_prefix _s2258_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2259_ _)) =>
+ (match (string_drop _s2258_ _s2259_) with
+ | _s2260_ =>
+ (creg_name_matches_prefix _s2260_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2261_ _)) =>
+ (match (string_drop _s2260_ _s2261_) with
+ | _s2262_ =>
+ (sep_matches_prefix _s2262_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2263_ _)) =>
+ (match (string_drop _s2262_ _s2263_) with
+ | _s2264_ =>
+ (creg_name_matches_prefix _s2264_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2265_ _)) =>
+ let p0_ := string_drop _s2264_ _s2265_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2243_ (_s2244_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2245_ := _s2244_ in
+ (if ((string_startswith _s2245_ "c.subw")) then
+ (match (string_drop _s2245_ (projT1 (string_length "c.subw"))) with
+ | _s2246_ =>
+ (spc_matches_prefix _s2246_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2247_ _)) =>
+ (match (string_drop _s2246_ _s2247_) with
+ | _s2248_ =>
+ (creg_name_matches_prefix _s2248_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2249_ _)) =>
+ (match (string_drop _s2248_ _s2249_) with
+ | _s2250_ =>
+ (sep_matches_prefix _s2250_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2251_ _)) =>
+ (match (string_drop _s2250_ _s2251_) with
+ | _s2252_ =>
+ (creg_name_matches_prefix _s2252_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2253_ _)) =>
+ let p0_ := string_drop _s2252_ _s2253_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2231_ (_s2232_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2233_ := _s2232_ in
+ (if ((string_startswith _s2233_ "c.and")) then
+ (match (string_drop _s2233_ (projT1 (string_length "c.and"))) with
+ | _s2234_ =>
+ (spc_matches_prefix _s2234_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2235_ _)) =>
+ (match (string_drop _s2234_ _s2235_) with
+ | _s2236_ =>
+ (creg_name_matches_prefix _s2236_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2237_ _)) =>
+ (match (string_drop _s2236_ _s2237_) with
+ | _s2238_ =>
+ (sep_matches_prefix _s2238_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2239_ _)) =>
+ (match (string_drop _s2238_ _s2239_) with
+ | _s2240_ =>
+ (creg_name_matches_prefix _s2240_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2241_ _)) =>
+ let p0_ := string_drop _s2240_ _s2241_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2219_ (_s2220_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2221_ := _s2220_ in
+ (if ((string_startswith _s2221_ "c.or")) then
+ (match (string_drop _s2221_ (projT1 (string_length "c.or"))) with
+ | _s2222_ =>
+ (spc_matches_prefix _s2222_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2223_ _)) =>
+ (match (string_drop _s2222_ _s2223_) with
+ | _s2224_ =>
+ (creg_name_matches_prefix _s2224_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2225_ _)) =>
+ (match (string_drop _s2224_ _s2225_) with
+ | _s2226_ =>
+ (sep_matches_prefix _s2226_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2227_ _)) =>
+ (match (string_drop _s2226_ _s2227_) with
+ | _s2228_ =>
+ (creg_name_matches_prefix _s2228_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2229_ _)) =>
+ let p0_ := string_drop _s2228_ _s2229_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2207_ (_s2208_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2209_ := _s2208_ in
+ (if ((string_startswith _s2209_ "c.xor")) then
+ (match (string_drop _s2209_ (projT1 (string_length "c.xor"))) with
+ | _s2210_ =>
+ (spc_matches_prefix _s2210_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2211_ _)) =>
+ (match (string_drop _s2210_ _s2211_) with
+ | _s2212_ =>
+ (creg_name_matches_prefix _s2212_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2213_ _)) =>
+ (match (string_drop _s2212_ _s2213_) with
+ | _s2214_ =>
+ (sep_matches_prefix _s2214_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2215_ _)) =>
+ (match (string_drop _s2214_ _s2215_) with
+ | _s2216_ =>
+ (creg_name_matches_prefix _s2216_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2217_ _)) =>
+ let p0_ := string_drop _s2216_ _s2217_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2195_ (_s2196_ : string)
+: M (option ((mword 3 * mword 3))) :=
+
+ let _s2197_ := _s2196_ in
+ (if ((string_startswith _s2197_ "c.sub")) then
+ (match (string_drop _s2197_ (projT1 (string_length "c.sub"))) with
+ | _s2198_ =>
+ (spc_matches_prefix _s2198_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2199_ _)) =>
+ (match (string_drop _s2198_ _s2199_) with
+ | _s2200_ =>
+ (creg_name_matches_prefix _s2200_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2201_ _)) =>
+ (match (string_drop _s2200_ _s2201_) with
+ | _s2202_ =>
+ (sep_matches_prefix _s2202_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2203_ _)) =>
+ (match (string_drop _s2202_ _s2203_) with
+ | _s2204_ =>
+ (creg_name_matches_prefix _s2204_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2205_ _)) =>
+ let p0_ := string_drop _s2204_ _s2205_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ | _ => returnm (None : option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ end)
+ : M (option ((mword 3 * mword 3)))
+ else returnm (None : option ((mword 3 * mword 3))))
+ : M (option ((mword 3 * mword 3))).
+
+Definition _s2183_ (_s2184_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2185_ := _s2184_ in
+ (if ((string_startswith _s2185_ "c.andi")) then
+ (match (string_drop _s2185_ (projT1 (string_length "c.andi"))) with
+ | _s2186_ =>
+ (spc_matches_prefix _s2186_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2187_ _)) =>
+ (match (string_drop _s2186_ _s2187_) with
+ | _s2188_ =>
+ (creg_name_matches_prefix _s2188_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2189_ _)) =>
+ (match (string_drop _s2188_ _s2189_) with
+ | _s2190_ =>
+ (sep_matches_prefix _s2190_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2191_ _)) =>
+ match (string_drop _s2190_ _s2191_) with
+ | _s2192_ =>
+ match (hex_bits_6_matches_prefix _s2192_) with
+ | Some ((imm, existT _ _s2193_ _)) =>
+ let p0_ := string_drop _s2192_ _s2193_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2171_ (_s2172_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2173_ := _s2172_ in
+ (if ((string_startswith _s2173_ "c.srai")) then
+ (match (string_drop _s2173_ (projT1 (string_length "c.srai"))) with
+ | _s2174_ =>
+ (spc_matches_prefix _s2174_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2175_ _)) =>
+ (match (string_drop _s2174_ _s2175_) with
+ | _s2176_ =>
+ (creg_name_matches_prefix _s2176_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2177_ _)) =>
+ (match (string_drop _s2176_ _s2177_) with
+ | _s2178_ =>
+ (sep_matches_prefix _s2178_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2179_ _)) =>
+ match (string_drop _s2178_ _s2179_) with
+ | _s2180_ =>
+ match (hex_bits_6_matches_prefix _s2180_) with
+ | Some ((shamt, existT _ _s2181_ _)) =>
+ let p0_ := string_drop _s2180_ _s2181_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2159_ (_s2160_ : string)
+: M (option ((mword 3 * mword 6))) :=
+
+ let _s2161_ := _s2160_ in
+ (if ((string_startswith _s2161_ "c.srli")) then
+ (match (string_drop _s2161_ (projT1 (string_length "c.srli"))) with
+ | _s2162_ =>
+ (spc_matches_prefix _s2162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2163_ _)) =>
+ (match (string_drop _s2162_ _s2163_) with
+ | _s2164_ =>
+ (creg_name_matches_prefix _s2164_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2165_ _)) =>
+ (match (string_drop _s2164_ _s2165_) with
+ | _s2166_ =>
+ (sep_matches_prefix _s2166_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2167_ _)) =>
+ match (string_drop _s2166_ _s2167_) with
+ | _s2168_ =>
+ match (hex_bits_6_matches_prefix _s2168_) with
+ | Some ((shamt, existT _ _s2169_ _)) =>
+ let p0_ := string_drop _s2168_ _s2169_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ | _ => returnm (None : option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ end)
+ : M (option ((mword 3 * mword 6)))
+ else returnm (None : option ((mword 3 * mword 6))))
+ : M (option ((mword 3 * mword 6))).
+
+Definition _s2147_ (_s2148_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2149_ := _s2148_ in
+ (if ((string_startswith _s2149_ "c.lui")) then
+ (match (string_drop _s2149_ (projT1 (string_length "c.lui"))) with
+ | _s2150_ =>
+ (spc_matches_prefix _s2150_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2151_ _)) =>
+ (match (string_drop _s2150_ _s2151_) with
+ | _s2152_ =>
+ (reg_name_matches_prefix _s2152_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2153_ _)) =>
+ (match (string_drop _s2152_ _s2153_) with
+ | _s2154_ =>
+ (sep_matches_prefix _s2154_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2155_ _)) =>
+ match (string_drop _s2154_ _s2155_) with
+ | _s2156_ =>
+ match (hex_bits_6_matches_prefix _s2156_) with
+ | Some ((imm, existT _ _s2157_ _)) =>
+ let p0_ := string_drop _s2156_ _s2157_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2139_ (_s2140_ : string)
+: M (option (mword 6)) :=
+
+ let _s2141_ := _s2140_ in
+ (if ((string_startswith _s2141_ "c.addi16sp")) then
+ (match (string_drop _s2141_ (projT1 (string_length "c.addi16sp"))) with
+ | _s2142_ =>
+ (spc_matches_prefix _s2142_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2143_ _)) =>
+ match (string_drop _s2142_ _s2143_) with
+ | _s2144_ =>
+ match (hex_bits_6_matches_prefix _s2144_) with
+ | Some ((imm, existT _ _s2145_ _)) =>
+ let p0_ := string_drop _s2144_ _s2145_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 6))
+ end)
+ : M (option (mword 6))
+ else returnm (None : option (mword 6)))
+ : M (option (mword 6)).
+
+Definition _s2127_ (_s2128_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2129_ := _s2128_ in
+ (if ((string_startswith _s2129_ "c.li")) then
+ (match (string_drop _s2129_ (projT1 (string_length "c.li"))) with
+ | _s2130_ =>
+ (spc_matches_prefix _s2130_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2131_ _)) =>
+ (match (string_drop _s2130_ _s2131_) with
+ | _s2132_ =>
+ (reg_name_matches_prefix _s2132_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2133_ _)) =>
+ (match (string_drop _s2132_ _s2133_) with
+ | _s2134_ =>
+ (sep_matches_prefix _s2134_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2135_ _)) =>
+ match (string_drop _s2134_ _s2135_) with
+ | _s2136_ =>
+ match (hex_bits_6_matches_prefix _s2136_) with
+ | Some ((imm, existT _ _s2137_ _)) =>
+ let p0_ := string_drop _s2136_ _s2137_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2115_ (_s2116_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2117_ := _s2116_ in
+ (if ((string_startswith _s2117_ "c.addiw")) then
+ (match (string_drop _s2117_ (projT1 (string_length "c.addiw"))) with
+ | _s2118_ =>
+ (spc_matches_prefix _s2118_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2119_ _)) =>
+ (match (string_drop _s2118_ _s2119_) with
+ | _s2120_ =>
+ (reg_name_matches_prefix _s2120_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2121_ _)) =>
+ (match (string_drop _s2120_ _s2121_) with
+ | _s2122_ =>
+ (sep_matches_prefix _s2122_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2123_ _)) =>
+ match (string_drop _s2122_ _s2123_) with
+ | _s2124_ =>
+ match (hex_bits_6_matches_prefix _s2124_) with
+ | Some ((imm, existT _ _s2125_ _)) =>
+ let p0_ := string_drop _s2124_ _s2125_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2107_ (_s2108_ : string)
+: M (option (mword 11)) :=
+
+ let _s2109_ := _s2108_ in
+ (if ((string_startswith _s2109_ "c.jal")) then
+ (match (string_drop _s2109_ (projT1 (string_length "c.jal"))) with
+ | _s2110_ =>
+ (spc_matches_prefix _s2110_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s2111_ _)) =>
+ match (string_drop _s2110_ _s2111_) with
+ | _s2112_ =>
+ match (hex_bits_12_matches_prefix _s2112_) with
+ | Some ((v__814, existT _ _s2113_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__814 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__814 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__814 11 1 in
+ let p0_ := string_drop _s2112_ _s2113_ in
+ if ((generic_eq p0_ "")) then Some (imm)
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option (mword 11))
+ end)
+ : M (option (mword 11))
+ else returnm (None : option (mword 11)))
+ : M (option (mword 11)).
+
+Definition _s2095_ (_s2096_ : string)
+: M (option ((mword 5 * mword 6))) :=
+
+ let _s2097_ := _s2096_ in
+ (if ((string_startswith _s2097_ "c.addi")) then
+ (match (string_drop _s2097_ (projT1 (string_length "c.addi"))) with
+ | _s2098_ =>
+ (spc_matches_prefix _s2098_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2099_ _)) =>
+ (match (string_drop _s2098_ _s2099_) with
+ | _s2100_ =>
+ (reg_name_matches_prefix _s2100_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s2101_ _)) =>
+ (match (string_drop _s2100_ _s2101_) with
+ | _s2102_ =>
+ (sep_matches_prefix _s2102_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2103_ _)) =>
+ match (string_drop _s2102_ _s2103_) with
+ | _s2104_ =>
+ match (hex_bits_6_matches_prefix _s2104_) with
+ | Some ((nzi, existT _ _s2105_ _)) =>
+ let p0_ := string_drop _s2104_ _s2105_ in
+ if ((generic_eq p0_ "")) then Some ((rsd, nzi))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ | _ => returnm (None : option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ end)
+ : M (option ((mword 5 * mword 6)))
+ else returnm (None : option ((mword 5 * mword 6))))
+ : M (option ((mword 5 * mword 6))).
+
+Definition _s2079_ (_s2080_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2081_ := _s2080_ in
+ (if ((string_startswith _s2081_ "c.sd")) then
+ (match (string_drop _s2081_ (projT1 (string_length "c.sd"))) with
+ | _s2082_ =>
+ (spc_matches_prefix _s2082_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2083_ _)) =>
+ (match (string_drop _s2082_ _s2083_) with
+ | _s2084_ =>
+ (creg_name_matches_prefix _s2084_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2085_ _)) =>
+ (match (string_drop _s2084_ _s2085_) with
+ | _s2086_ =>
+ (sep_matches_prefix _s2086_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2087_ _)) =>
+ (match (string_drop _s2086_ _s2087_) with
+ | _s2088_ =>
+ (creg_name_matches_prefix _s2088_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2089_ _)) =>
+ (match (string_drop _s2088_ _s2089_) with
+ | _s2090_ =>
+ (sep_matches_prefix _s2090_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2091_ _)) =>
+ match (string_drop _s2090_ _s2091_) with
+ | _s2092_ =>
+ match (hex_bits_8_matches_prefix _s2092_) with
+ | Some ((v__816, existT _ _s2093_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__816 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__816 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__816 7 3 in
+ let p0_ :=
+ string_drop _s2092_ _s2093_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2063_ (_s2064_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2065_ := _s2064_ in
+ (if ((string_startswith _s2065_ "c.sw")) then
+ (match (string_drop _s2065_ (projT1 (string_length "c.sw"))) with
+ | _s2066_ =>
+ (spc_matches_prefix _s2066_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2067_ _)) =>
+ (match (string_drop _s2066_ _s2067_) with
+ | _s2068_ =>
+ (creg_name_matches_prefix _s2068_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2069_ _)) =>
+ (match (string_drop _s2068_ _s2069_) with
+ | _s2070_ =>
+ (sep_matches_prefix _s2070_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2071_ _)) =>
+ (match (string_drop _s2070_ _s2071_) with
+ | _s2072_ =>
+ (creg_name_matches_prefix _s2072_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2073_ _)) =>
+ (match (string_drop _s2072_ _s2073_) with
+ | _s2074_ =>
+ (sep_matches_prefix _s2074_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2075_ _)) =>
+ match (string_drop _s2074_ _s2075_) with
+ | _s2076_ =>
+ match (hex_bits_7_matches_prefix _s2076_) with
+ | Some ((v__818, existT _ _s2077_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__818 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__818 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__818 6 2 in
+ let p0_ :=
+ string_drop _s2076_ _s2077_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rsc1, rsc2, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2047_ (_s2048_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2049_ := _s2048_ in
+ (if ((string_startswith _s2049_ "c.ld")) then
+ (match (string_drop _s2049_ (projT1 (string_length "c.ld"))) with
+ | _s2050_ =>
+ (spc_matches_prefix _s2050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2051_ _)) =>
+ (match (string_drop _s2050_ _s2051_) with
+ | _s2052_ =>
+ (creg_name_matches_prefix _s2052_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2053_ _)) =>
+ (match (string_drop _s2052_ _s2053_) with
+ | _s2054_ =>
+ (sep_matches_prefix _s2054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2055_ _)) =>
+ (match (string_drop _s2054_ _s2055_) with
+ | _s2056_ =>
+ (creg_name_matches_prefix _s2056_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2057_ _)) =>
+ (match (string_drop _s2056_ _s2057_) with
+ | _s2058_ =>
+ (sep_matches_prefix _s2058_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2059_ _)) =>
+ match (string_drop _s2058_ _s2059_) with
+ | _s2060_ =>
+ match (hex_bits_8_matches_prefix _s2060_) with
+ | Some ((v__820, existT _ _s2061_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__820 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__820 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__820 7 3 in
+ let p0_ :=
+ string_drop _s2060_ _s2061_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2031_ (_s2032_ : string)
+: M (option ((mword 3 * mword 3 * mword 5))) :=
+
+ let _s2033_ := _s2032_ in
+ (if ((string_startswith _s2033_ "c.lw")) then
+ (match (string_drop _s2033_ (projT1 (string_length "c.lw"))) with
+ | _s2034_ =>
+ (spc_matches_prefix _s2034_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2035_ _)) =>
+ (match (string_drop _s2034_ _s2035_) with
+ | _s2036_ =>
+ (creg_name_matches_prefix _s2036_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2037_ _)) =>
+ (match (string_drop _s2036_ _s2037_) with
+ | _s2038_ =>
+ (sep_matches_prefix _s2038_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2039_ _)) =>
+ (match (string_drop _s2038_ _s2039_) with
+ | _s2040_ =>
+ (creg_name_matches_prefix _s2040_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2041_ _)) =>
+ (match (string_drop _s2040_ _s2041_) with
+ | _s2042_ =>
+ (sep_matches_prefix _s2042_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2043_ _)) =>
+ match (string_drop _s2042_ _s2043_) with
+ | _s2044_ =>
+ match (hex_bits_7_matches_prefix _s2044_) with
+ | Some ((v__822, existT _ _s2045_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__822 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__822 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__822 6 2 in
+ let p0_ :=
+ string_drop _s2044_ _s2045_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rdc, rsc, uimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5))))
+ : M (option ((mword 3 * mword 3 * mword 5))).
+
+Definition _s2019_ (_s2020_ : string)
+: M (option ((mword 3 * mword 8))) :=
+
+ let _s2021_ := _s2020_ in
+ (if ((string_startswith _s2021_ "c.addi4spn")) then
+ (match (string_drop _s2021_ (projT1 (string_length "c.addi4spn"))) with
+ | _s2022_ =>
+ (spc_matches_prefix _s2022_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2023_ _)) =>
+ (match (string_drop _s2022_ _s2023_) with
+ | _s2024_ =>
+ (creg_name_matches_prefix _s2024_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2025_ _)) =>
+ (match (string_drop _s2024_ _s2025_) with
+ | _s2026_ =>
+ (sep_matches_prefix _s2026_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2027_ _)) =>
+ match (string_drop _s2026_ _s2027_) with
+ | _s2028_ =>
+ match (hex_bits_10_matches_prefix _s2028_) with
+ | Some ((v__824, existT _ _s2029_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__824 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__824 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__824 9 2 in
+ let p0_ := string_drop _s2028_ _s2029_ in
+ if ((generic_eq p0_ "")) then Some ((rdc, nzimm))
+ else None
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ | _ => returnm (None : option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ end)
+ : M (option ((mword 3 * mword 8)))
+ else returnm (None : option ((mword 3 * mword 8))))
+ : M (option ((mword 3 * mword 8))).
+
+Definition _s1995_ (_s1996_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1996_ with
+ | _s1997_ =>
+ (amo_mnemonic_matches_prefix _s1997_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1998_ _)) =>
+ let _s1999_ := string_drop _s1997_ _s1998_ in
+ (if ((string_startswith _s1999_ ".")) then
+ (match (string_drop _s1999_ (projT1 (string_length "."))) with
+ | _s2000_ =>
+ (size_mnemonic_matches_prefix _s2000_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s2001_ _)) =>
+ (match (string_drop _s2000_ _s2001_) with
+ | _s2002_ =>
+ (maybe_aq_matches_prefix _s2002_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2003_ _)) =>
+ (match (string_drop _s2002_ _s2003_) with
+ | _s2004_ =>
+ (maybe_rl_matches_prefix _s2004_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2005_ _)) =>
+ (match (string_drop _s2004_ _s2005_) with
+ | _s2006_ =>
+ (spc_matches_prefix _s2006_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2007_ _)) =>
+ (match (string_drop _s2006_ _s2007_) with
+ | _s2008_ =>
+ (reg_name_matches_prefix _s2008_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2009_ _)) =>
+ (match (string_drop _s2008_ _s2009_) with
+ | _s2010_ =>
+ (sep_matches_prefix _s2010_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2011_ _)) =>
+ (match (string_drop _s2010_ _s2011_) with
+ | _s2012_ =>
+ (reg_name_matches_prefix _s2012_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s2013_ _)) =>
+ (match (string_drop _s2012_
+ _s2013_) with
+ | _s2014_ =>
+ (sep_matches_prefix
+ _s2014_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2015_ _)) =>
+ (match (string_drop
+ _s2014_
+ _s2015_) with
+ | _s2016_ =>
+ (reg_name_matches_prefix
+ _s2016_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s2017_ _)) =>
+ let p0_ :=
+ string_drop
+ _s2016_
+ _s2017_ in
+ if ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2))
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1973_ (_s1974_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) :=
+
+ let _s1975_ := _s1974_ in
+ (if ((string_startswith _s1975_ "sc.")) then
+ (match (string_drop _s1975_ (projT1 (string_length "sc."))) with
+ | _s1976_ =>
+ (size_mnemonic_matches_prefix _s1976_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1977_ _)) =>
+ (match (string_drop _s1976_ _s1977_) with
+ | _s1978_ =>
+ (maybe_aq_matches_prefix _s1978_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1979_ _)) =>
+ (match (string_drop _s1978_ _s1979_) with
+ | _s1980_ =>
+ (maybe_rl_matches_prefix _s1980_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1981_ _)) =>
+ (match (string_drop _s1980_ _s1981_) with
+ | _s1982_ =>
+ (spc_matches_prefix _s1982_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1983_ _)) =>
+ (match (string_drop _s1982_ _s1983_) with
+ | _s1984_ =>
+ (reg_name_matches_prefix _s1984_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1985_ _)) =>
+ (match (string_drop _s1984_ _s1985_) with
+ | _s1986_ =>
+ (sep_matches_prefix _s1986_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1987_ _)) =>
+ (match (string_drop _s1986_ _s1987_) with
+ | _s1988_ =>
+ (reg_name_matches_prefix _s1988_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s1989_ _)) =>
+ (match (string_drop _s1988_ _s1989_) with
+ | _s1990_ =>
+ (sep_matches_prefix _s1990_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s1991_ _)) =>
+ (match (string_drop _s1990_
+ _s1991_) with
+ | _s1992_ =>
+ (reg_name_matches_prefix
+ _s1992_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s1993_ _)) =>
+ let p0_ :=
+ string_drop
+ _s1992_
+ _s1993_ in
+ if ((generic_eq
+ p0_ ""))
+ then
+ Some
+ ((size, aq, rl, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))).
+
+Definition _s1955_ (_s1956_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5))) :=
+
+ let _s1957_ := _s1956_ in
+ (if ((string_startswith _s1957_ "lr.")) then
+ (match (string_drop _s1957_ (projT1 (string_length "lr."))) with
+ | _s1958_ =>
+ (size_mnemonic_matches_prefix _s1958_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1959_ _)) =>
+ (match (string_drop _s1958_ _s1959_) with
+ | _s1960_ =>
+ (maybe_aq_matches_prefix _s1960_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1961_ _)) =>
+ (match (string_drop _s1960_ _s1961_) with
+ | _s1962_ =>
+ (maybe_rl_matches_prefix _s1962_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1963_ _)) =>
+ (match (string_drop _s1962_ _s1963_) with
+ | _s1964_ =>
+ (spc_matches_prefix _s1964_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1965_ _)) =>
+ (match (string_drop _s1964_ _s1965_) with
+ | _s1966_ =>
+ (reg_name_matches_prefix _s1966_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s1967_ _)) =>
+ (match (string_drop _s1966_ _s1967_) with
+ | _s1968_ =>
+ (sep_matches_prefix _s1968_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1969_ _)) =>
+ (match (string_drop _s1968_ _s1969_) with
+ | _s1970_ =>
+ (reg_name_matches_prefix _s1970_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s1971_ _)) =>
+ let p0_ :=
+ string_drop _s1970_ _s1971_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((size, aq, rl, rd, rs1))
+ else None
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5))).
+
+Definition _s1943_ (_s1944_ : string)
+: M (option ((mword 5 * mword 5))) :=
+
+ let _s1945_ := _s1944_ in
+ (if ((string_startswith _s1945_ "sfence.vma")) then
+ (match (string_drop _s1945_ (projT1 (string_length "sfence.vma"))) with
+ | _s1946_ =>
+ (spc_matches_prefix _s1946_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1947_ _)) =>
+ (match (string_drop _s1946_ _s1947_) with
+ | _s1948_ =>
+ (reg_name_matches_prefix _s1948_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s1949_ _)) =>
+ (match (string_drop _s1948_ _s1949_) with
+ | _s1950_ =>
+ (sep_matches_prefix _s1950_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1951_ _)) =>
+ (match (string_drop _s1950_ _s1951_) with
+ | _s1952_ =>
+ (reg_name_matches_prefix _s1952_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s1953_ _)) =>
+ let p0_ := string_drop _s1952_ _s1953_ in
+ if ((generic_eq p0_ "")) then Some ((rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ | _ => returnm (None : option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ end)
+ : M (option ((mword 5 * mword 5)))
+ else returnm (None : option ((mword 5 * mword 5))))
+ : M (option ((mword 5 * mword 5))).
+
+Definition _s1931_ (_s1932_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1933_ := _s1932_ in
+ (if ((string_startswith _s1933_ "fence.tso")) then
+ (match (string_drop _s1933_ (projT1 (string_length "fence.tso"))) with
+ | _s1934_ =>
+ (spc_matches_prefix _s1934_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1935_ _)) =>
+ (match (string_drop _s1934_ _s1935_) with
+ | _s1936_ =>
+ (fence_bits_matches_prefix _s1936_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1937_ _)) =>
+ (match (string_drop _s1936_ _s1937_) with
+ | _s1938_ =>
+ (sep_matches_prefix _s1938_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1939_ _)) =>
+ (match (string_drop _s1938_ _s1939_) with
+ | _s1940_ =>
+ (fence_bits_matches_prefix _s1940_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1941_ _)) =>
+ let p0_ := string_drop _s1940_ _s1941_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1919_ (_s1920_ : string)
+: M (option ((mword 4 * mword 4))) :=
+
+ let _s1921_ := _s1920_ in
+ (if ((string_startswith _s1921_ "fence")) then
+ (match (string_drop _s1921_ (projT1 (string_length "fence"))) with
+ | _s1922_ =>
+ (spc_matches_prefix _s1922_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1923_ _)) =>
+ (match (string_drop _s1922_ _s1923_) with
+ | _s1924_ =>
+ (fence_bits_matches_prefix _s1924_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s1925_ _)) =>
+ (match (string_drop _s1924_ _s1925_) with
+ | _s1926_ =>
+ (sep_matches_prefix _s1926_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1927_ _)) =>
+ (match (string_drop _s1926_ _s1927_) with
+ | _s1928_ =>
+ (fence_bits_matches_prefix _s1928_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s1929_ _)) =>
+ let p0_ := string_drop _s1928_ _s1929_ in
+ if ((generic_eq p0_ "")) then Some ((pred, succ))
+ else None
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ | _ => returnm (None : option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ end)
+ : M (option ((mword 4 * mword 4)))
+ else returnm (None : option ((mword 4 * mword 4))))
+ : M (option ((mword 4 * mword 4))).
+
+Definition _s1902_ (_s1903_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1903_ with
+ | _s1904_ =>
+ (shiftiwop_mnemonic_matches_prefix _s1904_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1905_ _)) =>
+ (match (string_drop _s1904_ _s1905_) with
+ | _s1906_ =>
+ (spc_matches_prefix _s1906_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1907_ _)) =>
+ (match (string_drop _s1906_ _s1907_) with
+ | _s1908_ =>
+ (reg_name_matches_prefix _s1908_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1909_ _)) =>
+ (match (string_drop _s1908_ _s1909_) with
+ | _s1910_ =>
+ (sep_matches_prefix _s1910_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1911_ _)) =>
+ (match (string_drop _s1910_ _s1911_) with
+ | _s1912_ =>
+ (reg_name_matches_prefix _s1912_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1913_ _)) =>
+ (match (string_drop _s1912_ _s1913_) with
+ | _s1914_ =>
+ (sep_matches_prefix _s1914_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1915_ _)) =>
+ match (string_drop _s1914_ _s1915_) with
+ | _s1916_ =>
+ match (hex_bits_5_matches_prefix
+ _s1916_) with
+ | Some ((shamt, existT _ _s1917_ _)) =>
+ let p0_ :=
+ string_drop _s1916_ _s1917_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1885_ (_s1886_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1886_ with
+ | _s1887_ =>
+ (rtypew_mnemonic_matches_prefix _s1887_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1888_ _)) =>
+ (match (string_drop _s1887_ _s1888_) with
+ | _s1889_ =>
+ (spc_matches_prefix _s1889_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1890_ _)) =>
+ (match (string_drop _s1889_ _s1890_) with
+ | _s1891_ =>
+ (reg_name_matches_prefix _s1891_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1892_ _)) =>
+ (match (string_drop _s1891_ _s1892_) with
+ | _s1893_ =>
+ (sep_matches_prefix _s1893_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1894_ _)) =>
+ (match (string_drop _s1893_ _s1894_) with
+ | _s1895_ =>
+ (reg_name_matches_prefix _s1895_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1896_ _)) =>
+ (match (string_drop _s1895_ _s1896_) with
+ | _s1897_ =>
+ (sep_matches_prefix _s1897_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1898_ _)) =>
+ (match (string_drop _s1897_ _s1898_) with
+ | _s1899_ =>
+ (reg_name_matches_prefix _s1899_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1900_ _)) =>
+ let p0_ :=
+ string_drop _s1899_ _s1900_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5))).
+
+Definition _s1868_ (_s1869_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1869_ with
+ | _s1870_ =>
+ (shiftw_mnemonic_matches_prefix _s1870_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1871_ _)) =>
+ (match (string_drop _s1870_ _s1871_) with
+ | _s1872_ =>
+ (spc_matches_prefix _s1872_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1873_ _)) =>
+ (match (string_drop _s1872_ _s1873_) with
+ | _s1874_ =>
+ (reg_name_matches_prefix _s1874_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1875_ _)) =>
+ (match (string_drop _s1874_ _s1875_) with
+ | _s1876_ =>
+ (sep_matches_prefix _s1876_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1877_ _)) =>
+ (match (string_drop _s1876_ _s1877_) with
+ | _s1878_ =>
+ (reg_name_matches_prefix _s1878_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1879_ _)) =>
+ (match (string_drop _s1878_ _s1879_) with
+ | _s1880_ =>
+ (sep_matches_prefix _s1880_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1881_ _)) =>
+ match (string_drop _s1880_ _s1881_) with
+ | _s1882_ =>
+ match (hex_bits_5_matches_prefix
+ _s1882_) with
+ | Some ((shamt, existT _ _s1883_ _)) =>
+ let p0_ :=
+ string_drop _s1882_ _s1883_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5))).
+
+Definition _s1852_ (_s1853_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s1854_ := _s1853_ in
+ (if ((string_startswith _s1854_ "addiw")) then
+ (match (string_drop _s1854_ (projT1 (string_length "addiw"))) with
+ | _s1855_ =>
+ (spc_matches_prefix _s1855_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1856_ _)) =>
+ (match (string_drop _s1855_ _s1856_) with
+ | _s1857_ =>
+ (reg_name_matches_prefix _s1857_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1858_ _)) =>
+ (match (string_drop _s1857_ _s1858_) with
+ | _s1859_ =>
+ (sep_matches_prefix _s1859_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1860_ _)) =>
+ (match (string_drop _s1859_ _s1860_) with
+ | _s1861_ =>
+ (reg_name_matches_prefix _s1861_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1862_ _)) =>
+ (match (string_drop _s1861_ _s1862_) with
+ | _s1863_ =>
+ (sep_matches_prefix _s1863_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1864_ _)) =>
+ match (string_drop _s1863_ _s1864_) with
+ | _s1865_ =>
+ match (hex_bits_12_matches_prefix _s1865_) with
+ | Some ((imm, existT _ _s1866_ _)) =>
+ let p0_ := string_drop _s1865_ _s1866_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s1824_ (_s1825_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s1826_ := _s1825_ in
+ (if ((string_startswith _s1826_ "s")) then
+ (match (string_drop _s1826_ (projT1 (string_length "s"))) with
+ | _s1827_ =>
+ (size_mnemonic_matches_prefix _s1827_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1828_ _)) =>
+ (match (string_drop _s1827_ _s1828_) with
+ | _s1829_ =>
+ (maybe_aq_matches_prefix _s1829_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s1830_ _)) =>
+ (match (string_drop _s1829_ _s1830_) with
+ | _s1831_ =>
+ (maybe_rl_matches_prefix _s1831_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s1832_ _)) =>
+ (match (string_drop _s1831_ _s1832_) with
+ | _s1833_ =>
+ (spc_matches_prefix _s1833_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1834_ _)) =>
+ (match (string_drop _s1833_ _s1834_) with
+ | _s1835_ =>
+ (reg_name_matches_prefix _s1835_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s1836_ _)) =>
+ (match (string_drop _s1835_ _s1836_) with
+ | _s1837_ =>
+ (sep_matches_prefix _s1837_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1838_ _)) =>
+ (match (string_drop _s1837_ _s1838_) with
+ | _s1839_ =>
+ (match (hex_bits_12_matches_prefix _s1839_) with
+ | Some ((imm, existT _ _s1840_ _)) =>
+ (match (string_drop _s1839_ _s1840_) with
+ | _s1841_ =>
+ (opt_spc_matches_prefix _s1841_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1842_ _)) =>
+ let _s1843_ :=
+ string_drop _s1841_ _s1842_ in
+ (if ((string_startswith
+ _s1843_ "(")) then
+ (match (string_drop _s1843_
+ (projT1
+ (string_length
+ "("))) with
+ | _s1844_ =>
+ (opt_spc_matches_prefix
+ _s1844_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s1845_ _)) =>
+ (match (string_drop
+ _s1844_
+ _s1845_) with
+ | _s1846_ =>
+ (reg_name_matches_prefix
+ _s1846_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s1847_ _)) =>
+ (match (string_drop
+ _s1846_
+ _s1847_) with
+ | _s1848_ =>
+ (opt_spc_matches_prefix
+ _s1848_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s1849_ _)) =>
+ let _s1850_ :=
+ string_drop
+ _s1848_
+ _s1849_ in
+ if
+ ((string_startswith
+ _s1850_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s1850_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, aq, rl, rs2, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s1794_ (_s1795_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))) :=
+
+ let _s1796_ := _s1795_ in
+ (if ((string_startswith _s1796_ "l")) then
+ (match (string_drop _s1796_ (projT1 (string_length "l"))) with
+ | _s1797_ =>
+ (size_mnemonic_matches_prefix _s1797_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s1798_ _)) =>
+ (match (string_drop _s1797_ _s1798_) with
+ | _s1799_ =>
+ (maybe_u_matches_prefix _s1799_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s1800_ _)) =>
+ (match (string_drop _s1799_ _s1800_) with
+ | _s1801_ =>
+ (maybe_aq_matches_prefix _s1801_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s1802_ _)) =>
+ (match (string_drop _s1801_ _s1802_) with
+ | _s1803_ =>
+ (maybe_rl_matches_prefix _s1803_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s1804_ _)) =>
+ (match (string_drop _s1803_ _s1804_) with
+ | _s1805_ =>
+ (spc_matches_prefix _s1805_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s1806_ _)) =>
+ (match (string_drop _s1805_ _s1806_) with
+ | _s1807_ =>
+ (reg_name_matches_prefix _s1807_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s1808_ _)) =>
+ (match (string_drop _s1807_ _s1808_) with
+ | _s1809_ =>
+ (sep_matches_prefix _s1809_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s1810_ _)) =>
+ (match (string_drop _s1809_ _s1810_) with
+ | _s1811_ =>
+ (match (hex_bits_12_matches_prefix
+ _s1811_) with
+ | Some
+ ((imm, existT _ _s1812_ _)) =>
+ (match (string_drop _s1811_
+ _s1812_) with
+ | _s1813_ =>
+ (opt_spc_matches_prefix
+ _s1813_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s1814_ _)) =>
+ let _s1815_ :=
+ string_drop _s1813_
+ _s1814_ in
+ (if ((string_startswith
+ _s1815_ "("))
+ then
+ (match (string_drop
+ _s1815_
+ (projT1
+ (string_length
+ "("))) with
+ | _s1816_ =>
+ (opt_spc_matches_prefix
+ _s1816_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s1817_ _)) =>
+ (match (string_drop
+ _s1816_
+ _s1817_) with
+ | _s1818_ =>
+ (reg_name_matches_prefix
+ _s1818_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s1819_ _)) =>
+ (match (string_drop
+ _s1818_
+ _s1819_) with
+ | _s1820_ =>
+ (opt_spc_matches_prefix
+ _s1820_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s1821_ _)) =>
+ let _s1822_ :=
+ string_drop
+ _s1820_
+ _s1821_ in
+ if
+ ((string_startswith
+ _s1822_
+ ")"))
+ then
+ let p0_ :=
+ string_drop
+ _s1822_
+ (projT1
+ (string_length
+ ")")) in
+ if
+ ((generic_eq
+ p0_
+ ""))
+ then
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1))
+ else
+ None
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)))
+ else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5))).
+
+Definition _s1777_ (_s1778_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5))) :=
+
+ (match _s1778_ with
+ | _s1779_ =>
+ (rtype_mnemonic_matches_prefix _s1779_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1780_ _)) =>
+ (match (string_drop _s1779_ _s1780_) with
+ | _s1781_ =>
+ (spc_matches_prefix _s1781_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1782_ _)) =>
+ (match (string_drop _s1781_ _s1782_) with
+ | _s1783_ =>
+ (reg_name_matches_prefix _s1783_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1784_ _)) =>
+ (match (string_drop _s1783_ _s1784_) with
+ | _s1785_ =>
+ (sep_matches_prefix _s1785_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1786_ _)) =>
+ (match (string_drop _s1785_ _s1786_) with
+ | _s1787_ =>
+ (reg_name_matches_prefix _s1787_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1788_ _)) =>
+ (match (string_drop _s1787_ _s1788_) with
+ | _s1789_ =>
+ (sep_matches_prefix _s1789_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s1790_ _)) =>
+ (match (string_drop _s1789_ _s1790_) with
+ | _s1791_ =>
+ (reg_name_matches_prefix _s1791_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s1792_ _)) =>
+ let p0_ :=
+ string_drop _s1791_ _s1792_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, rs2))
+ else None
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5))).
+
+Definition _s1760_ (_s1761_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6))) :=
+
+ (match _s1761_ with
+ | _s1762_ =>
+ (shiftiop_mnemonic_matches_prefix _s1762_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1763_ _)) =>
+ (match (string_drop _s1762_ _s1763_) with
+ | _s1764_ =>
+ (spc_matches_prefix _s1764_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1765_ _)) =>
+ (match (string_drop _s1764_ _s1765_) with
+ | _s1766_ =>
+ (reg_name_matches_prefix _s1766_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1767_ _)) =>
+ (match (string_drop _s1766_ _s1767_) with
+ | _s1768_ =>
+ (sep_matches_prefix _s1768_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1769_ _)) =>
+ (match (string_drop _s1768_ _s1769_) with
+ | _s1770_ =>
+ (reg_name_matches_prefix _s1770_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1771_ _)) =>
+ (match (string_drop _s1770_ _s1771_) with
+ | _s1772_ =>
+ (sep_matches_prefix _s1772_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1773_ _)) =>
+ match (string_drop _s1772_ _s1773_) with
+ | _s1774_ =>
+ match (hex_bits_6_matches_prefix
+ _s1774_) with
+ | Some ((shamt, existT _ _s1775_ _)) =>
+ let p0_ :=
+ string_drop _s1774_ _s1775_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, shamt))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6))).
+
+Definition _s1743_ (_s1744_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12))) :=
+
+ (match _s1744_ with
+ | _s1745_ =>
+ (itype_mnemonic_matches_prefix _s1745_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1746_ _)) =>
+ (match (string_drop _s1745_ _s1746_) with
+ | _s1747_ =>
+ (spc_matches_prefix _s1747_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1748_ _)) =>
+ (match (string_drop _s1747_ _s1748_) with
+ | _s1749_ =>
+ (reg_name_matches_prefix _s1749_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1750_ _)) =>
+ (match (string_drop _s1749_ _s1750_) with
+ | _s1751_ =>
+ (sep_matches_prefix _s1751_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1752_ _)) =>
+ (match (string_drop _s1751_ _s1752_) with
+ | _s1753_ =>
+ (reg_name_matches_prefix _s1753_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s1754_ _)) =>
+ (match (string_drop _s1753_ _s1754_) with
+ | _s1755_ =>
+ (sep_matches_prefix _s1755_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1756_ _)) =>
+ match (string_drop _s1755_ _s1756_) with
+ | _s1757_ =>
+ match (hex_bits_12_matches_prefix
+ _s1757_) with
+ | Some ((imm, existT _ _s1758_ _)) =>
+ let p0_ :=
+ string_drop _s1757_ _s1758_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12))).
+
+Definition _s1726_ (_s1727_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13))) :=
+
+ (match _s1727_ with
+ | _s1728_ =>
+ (btype_mnemonic_matches_prefix _s1728_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1729_ _)) =>
+ (match (string_drop _s1728_ _s1729_) with
+ | _s1730_ =>
+ (spc_matches_prefix _s1730_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1731_ _)) =>
+ (match (string_drop _s1730_ _s1731_) with
+ | _s1732_ =>
+ (reg_name_matches_prefix _s1732_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s1733_ _)) =>
+ (match (string_drop _s1732_ _s1733_) with
+ | _s1734_ =>
+ (sep_matches_prefix _s1734_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s1735_ _)) =>
+ (match (string_drop _s1734_ _s1735_) with
+ | _s1736_ =>
+ (reg_name_matches_prefix _s1736_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s1737_ _)) =>
+ (match (string_drop _s1736_ _s1737_) with
+ | _s1738_ =>
+ (sep_matches_prefix _s1738_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s1739_ _)) =>
+ match (string_drop _s1738_ _s1739_) with
+ | _s1740_ =>
+ match (hex_bits_13_matches_prefix
+ _s1740_) with
+ | Some ((imm, existT _ _s1741_ _)) =>
+ let p0_ :=
+ string_drop _s1740_ _s1741_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((op, rs1, rs2, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13))).
+
+Definition _s1710_ (_s1711_ : string)
+: M (option ((mword 5 * mword 5 * mword 12))) :=
+
+ let _s1712_ := _s1711_ in
+ (if ((string_startswith _s1712_ "jalr")) then
+ (match (string_drop _s1712_ (projT1 (string_length "jalr"))) with
+ | _s1713_ =>
+ (spc_matches_prefix _s1713_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1714_ _)) =>
+ (match (string_drop _s1713_ _s1714_) with
+ | _s1715_ =>
+ (reg_name_matches_prefix _s1715_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1716_ _)) =>
+ (match (string_drop _s1715_ _s1716_) with
+ | _s1717_ =>
+ (sep_matches_prefix _s1717_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s1718_ _)) =>
+ (match (string_drop _s1717_ _s1718_) with
+ | _s1719_ =>
+ (reg_name_matches_prefix _s1719_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s1720_ _)) =>
+ (match (string_drop _s1719_ _s1720_) with
+ | _s1721_ =>
+ (sep_matches_prefix _s1721_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s1722_ _)) =>
+ match (string_drop _s1721_ _s1722_) with
+ | _s1723_ =>
+ match (hex_bits_12_matches_prefix _s1723_) with
+ | Some ((imm, existT _ _s1724_ _)) =>
+ let p0_ := string_drop _s1723_ _s1724_ in
+ if ((generic_eq p0_ "")) then
+ Some
+ ((rd, rs1, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12))))
+ : M (option ((mword 5 * mword 5 * mword 12))).
+
+Definition _s1698_ (_s1699_ : string)
+: M (option ((mword 5 * mword 21))) :=
+
+ let _s1700_ := _s1699_ in
+ (if ((string_startswith _s1700_ "jal")) then
+ (match (string_drop _s1700_ (projT1 (string_length "jal"))) with
+ | _s1701_ =>
+ (spc_matches_prefix _s1701_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s1702_ _)) =>
+ (match (string_drop _s1701_ _s1702_) with
+ | _s1703_ =>
+ (reg_name_matches_prefix _s1703_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s1704_ _)) =>
+ (match (string_drop _s1703_ _s1704_) with
+ | _s1705_ =>
+ (sep_matches_prefix _s1705_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s1706_ _)) =>
+ match (string_drop _s1705_ _s1706_) with
+ | _s1707_ =>
+ match (hex_bits_21_matches_prefix _s1707_) with
+ | Some ((imm, existT _ _s1708_ _)) =>
+ let p0_ := string_drop _s1707_ _s1708_ in
+ if ((generic_eq p0_ "")) then Some ((rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ | _ => returnm (None : option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ end)
+ : M (option ((mword 5 * mword 21)))
+ else returnm (None : option ((mword 5 * mword 21))))
+ : M (option ((mword 5 * mword 21))).
+
+Definition _s1685_ (_s1686_ : string)
+: M (option ((uop * mword 5 * mword 20))) :=
+
+ (match _s1686_ with
+ | _s1687_ =>
+ (utype_mnemonic_matches_prefix _s1687_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s1688_ _)) =>
+ (match (string_drop _s1687_ _s1688_) with
+ | _s1689_ =>
+ (spc_matches_prefix _s1689_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s1690_ _)) =>
+ (match (string_drop _s1689_ _s1690_) with
+ | _s1691_ =>
+ (reg_name_matches_prefix _s1691_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s1692_ _)) =>
+ (match (string_drop _s1691_ _s1692_) with
+ | _s1693_ =>
+ (sep_matches_prefix _s1693_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s1694_ _)) =>
+ match (string_drop _s1693_ _s1694_) with
+ | _s1695_ =>
+ match (hex_bits_20_matches_prefix _s1695_) with
+ | Some ((imm, existT _ _s1696_ _)) =>
+ let p0_ := string_drop _s1695_ _s1696_ in
+ if ((generic_eq p0_ "")) then Some ((op, rd, imm))
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20)))
+ end)
+ : M (option ((uop * mword 5 * mword 20))).
+
+Definition assembly_backwards_matches (arg_ : string)
+: M (bool) :=
+
+ let _s1697_ := arg_ in
+ (_s1685_ _s1697_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) =>
+ (if ((match w__0 with | Some ((op, rd, imm)) => true | _ => false end)) then
+ (_s1685_ _s1697_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) =>
+ (match w__1 with
+ | Some ((op, rd, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1698_ _s1697_) >>= fun w__4 : option ((mword 5 * mword 21)) =>
+ (if ((match w__4 with | Some ((rd, imm)) => true | _ => false end)) then
+ (_s1698_ _s1697_) >>= fun w__5 : option ((mword 5 * mword 21)) =>
+ (match w__5 with
+ | Some ((rd, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1710_ _s1697_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm)) => true | _ => false end)) then
+ (_s1710_ _s1697_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1726_ _s1697_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm)) => true | _ => false end)) then
+ (_s1726_ _s1697_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1743_ _s1697_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm)) => true | _ => false end)) then
+ (_s1743_ _s1697_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm)) =>
+ returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1760_ _s1697_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt)) => true | _ => false end))
+ then
+ (_s1760_ _s1697_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1777_ _s1697_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2)) => true | _ => false end))
+ then
+ (_s1777_ _s1697_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1794_ _s1697_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1794_ _s1697_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1824_ _s1697_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1824_ _s1697_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1852_ _s1697_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1852_ _s1697_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1868_ _s1697_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1868_ _s1697_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1885_ _s1697_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1885_ _s1697_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1902_ _s1697_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s1902_ _s1697_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1919_ _s1697_) >>= fun w__52 : option ((mword 4 * mword 4)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1919_ _s1697_) >>= fun w__53 : option ((mword 4 * mword 4)) =>
+ (match w__53 with
+ | Some ((pred, succ)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1931_ _s1697_) >>= fun w__56 : option ((mword 4 * mword 4)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ)) => true
+ | _ => false
+ end)) then
+ (_s1931_ _s1697_) >>= fun w__57 : option ((mword 4 * mword 4)) =>
+ (match w__57 with
+ | Some ((pred, succ)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else if ((generic_eq _s1697_ "fence.i")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "ecall")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "mret")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "sret")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "ebreak")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else if ((generic_eq _s1697_ "wfi")) then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ else
+ (_s1943_ _s1697_) >>= fun w__60 : option ((mword 5 * mword 5)) =>
+ (if ((match w__60 with
+ | Some ((rs1, rs2)) => true
+ | _ => false
+ end)) then
+ (_s1943_ _s1697_) >>= fun w__61 : option ((mword 5 * mword 5)) =>
+ (match w__61 with
+ | Some ((rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1955_ _s1697_) >>= fun w__64 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (if ((match w__64 with
+ | Some ((size, aq, rl, rd, rs1)) => true
+ | _ => false
+ end)) then
+ (_s1955_ _s1697_) >>= fun w__65 : option ((word_width * bool * bool * mword 5 * mword 5)) =>
+ (match w__65 with
+ | Some ((size, aq, rl, rd, rs1)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool = true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1973_ _s1697_) >>= fun w__68 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__68 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1973_ _s1697_) >>= fun w__69 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__69 with
+ | Some ((size, aq, rl, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s1995_ _s1697_) >>= fun w__72 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if ((match w__72 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ true
+ | _ => false
+ end)) then
+ (_s1995_ _s1697_) >>= fun w__73 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__73 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else if ((generic_eq _s1697_ "c.nop"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2019_ _s1697_) >>= fun w__76 : option ((mword 3 * mword 8)) =>
+ (if ((match w__76 with
+ | Some ((rdc, nzimm)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s2019_ _s1697_) >>= fun w__77 : option ((mword 3 * mword 8)) =>
+ (match w__77 with
+ | Some ((rdc, nzimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2031_ _s1697_) >>= fun w__80 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__80 with
+ | Some ((rdc, rsc, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2031_ _s1697_) >>= fun w__81 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__81 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2047_ _s1697_) >>= fun w__84 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__84 with
+ | Some ((rdc, rsc, uimm)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2047_ _s1697_) >>= fun w__85 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__85 with
+ | Some ((rdc, rsc, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2063_ _s1697_) >>= fun w__88 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__88 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2063_ _s1697_) >>= fun w__89 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__89 with
+ | Some ((rsc1, rsc2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2079_ _s1697_) >>= fun w__92 : option ((mword 3 * mword 3 * mword 5)) =>
+ (if ((match w__92 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2079_ _s1697_) >>= fun w__93 : option ((mword 3 * mword 3 * mword 5)) =>
+ (match w__93 with
+ | Some
+ ((rsc1, rsc2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2095_ _s1697_) >>= fun w__96 : option ((mword 5 * mword 6)) =>
+ (if ((match w__96 with
+ | Some ((rsd, nzi)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s2095_ _s1697_) >>= fun w__97 : option ((mword 5 * mword 6)) =>
+ (match w__97 with
+ | Some ((rsd, nzi)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2107_ _s1697_) >>= fun w__100 : option (mword 11) =>
+ (if ((match w__100 with
+ | Some (imm) =>
+ Z.eqb 64 32
+ | _ => false
+ end)) then
+ (_s2107_ _s1697_) >>= fun w__101 : option (mword 11) =>
+ (match w__101 with
+ | Some (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2115_ _s1697_) >>= fun w__104 : option ((mword 5 * mword 6)) =>
+ (if ((match w__104 with
+ | Some
+ ((rsd, imm)) =>
+ Z.eqb 64
+ 64
+ | _ => false
+ end)) then
+ (_s2115_ _s1697_) >>= fun w__105 : option ((mword 5 * mword 6)) =>
+ (match w__105 with
+ | Some
+ ((rsd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2127_ _s1697_) >>= fun w__108 : option ((mword 5 * mword 6)) =>
+ (if ((match w__108 with
+ | Some
+ ((rd, imm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s2127_
+ _s1697_) >>= fun w__109 : option ((mword 5 * mword 6)) =>
+ (match w__109 with
+ | Some
+ ((rd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2139_
+ _s1697_) >>= fun w__112 : option (mword 6) =>
+ (if ((match w__112 with
+ | Some
+ (imm) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2139_
+ _s1697_) >>= fun w__113 : option (mword 6) =>
+ (match w__113 with
+ | Some
+ (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2147_
+ _s1697_) >>= fun w__116 : option ((mword 5 * mword 6)) =>
+ (if ((match w__116 with
+ | Some
+ ((rd, imm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2147_
+ _s1697_) >>= fun w__117 : option ((mword 5 * mword 6)) =>
+ (match w__117 with
+ | Some
+ ((rd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2159_
+ _s1697_) >>= fun w__120 : option ((mword 3 * mword 6)) =>
+ (if ((match w__120 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2159_
+ _s1697_) >>= fun w__121 : option ((mword 3 * mword 6)) =>
+ (match w__121 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2171_
+ _s1697_) >>= fun w__124 : option ((mword 3 * mword 6)) =>
+ (if ((match w__124 with
+ | Some
+ ((rsd, shamt)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s2171_
+ _s1697_) >>= fun w__125 : option ((mword 3 * mword 6)) =>
+ (match w__125 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2183_
+ _s1697_) >>= fun w__128 : option ((mword 3 * mword 6)) =>
+ (if
+ ((match w__128 with
+ | Some
+ ((rsd, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2183_
+ _s1697_) >>= fun w__129 : option ((mword 3 * mword 6)) =>
+ (match w__129 with
+ | Some
+ ((rsd, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2195_
+ _s1697_) >>= fun w__132 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__132 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2195_
+ _s1697_) >>= fun w__133 : option ((mword 3 * mword 3)) =>
+ (match w__133 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2207_
+ _s1697_) >>= fun w__136 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__136 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2207_
+ _s1697_) >>= fun w__137 : option ((mword 3 * mword 3)) =>
+ (match w__137 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2219_
+ _s1697_) >>= fun w__140 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__140 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2219_
+ _s1697_) >>= fun w__141 : option ((mword 3 * mword 3)) =>
+ (match w__141 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2231_
+ _s1697_) >>= fun w__144 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__144 with
+ | Some
+ ((rsd, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2231_
+ _s1697_) >>= fun w__145 : option ((mword 3 * mword 3)) =>
+ (match w__145 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2243_
+ _s1697_) >>= fun w__148 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__148 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2243_
+ _s1697_) >>= fun w__149 : option ((mword 3 * mword 3)) =>
+ (match w__149 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2255_
+ _s1697_) >>= fun w__152 : option ((mword 3 * mword 3)) =>
+ (if
+ ((match w__152 with
+ | Some
+ ((rsd, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2255_
+ _s1697_) >>= fun w__153 : option ((mword 3 * mword 3)) =>
+ (match w__153 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2267_
+ _s1697_) >>= fun w__156 : option (mword 11) =>
+ (if
+ ((match w__156 with
+ | Some
+ (imm) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2267_
+ _s1697_) >>= fun w__157 : option (mword 11) =>
+ (match w__157 with
+ | Some
+ (imm) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2275_
+ _s1697_) >>= fun w__160 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__160 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2275_
+ _s1697_) >>= fun w__161 : option ((mword 3 * mword 8)) =>
+ (match w__161 with
+ | Some
+ ((rs, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2287_
+ _s1697_) >>= fun w__164 : option ((mword 3 * mword 8)) =>
+ (if
+ ((match w__164 with
+ | Some
+ ((rs, imm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2287_
+ _s1697_) >>= fun w__165 : option ((mword 3 * mword 8)) =>
+ (match w__165 with
+ | Some
+ ((rs, imm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2299_
+ _s1697_) >>= fun w__168 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__168 with
+ | Some
+ ((rsd, shamt)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2299_
+ _s1697_) >>= fun w__169 : option ((mword 5 * mword 6)) =>
+ (match w__169 with
+ | Some
+ ((rsd, shamt)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2311_
+ _s1697_) >>= fun w__172 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__172 with
+ | Some
+ ((rd, uimm)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2311_
+ _s1697_) >>= fun w__173 : option ((mword 5 * mword 6)) =>
+ (match w__173 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2323_
+ _s1697_) >>= fun w__176 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__176 with
+ | Some
+ ((rd, uimm)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 64
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s2323_
+ _s1697_) >>= fun w__177 : option ((mword 5 * mword 6)) =>
+ (match w__177 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2335_
+ _s1697_) >>= fun w__180 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__180 with
+ | Some
+ ((rd, uimm)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2335_
+ _s1697_) >>= fun w__181 : option ((mword 5 * mword 6)) =>
+ (match w__181 with
+ | Some
+ ((rd, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2347_
+ _s1697_) >>= fun w__184 : option ((mword 5 * mword 6)) =>
+ (if
+ ((match w__184 with
+ | Some
+ ((rs2, uimm)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2347_
+ _s1697_) >>= fun w__185 : option ((mword 5 * mword 6)) =>
+ (match w__185 with
+ | Some
+ ((rs2, uimm)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2359_
+ _s1697_) >>= fun w__188 : option (mword 5) =>
+ (if
+ ((match w__188 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2359_
+ _s1697_) >>= fun w__189 : option (mword 5) =>
+ (match w__189 with
+ | Some
+ (rs1) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2367_
+ _s1697_) >>= fun w__192 : option (mword 5) =>
+ (if
+ ((match w__192 with
+ | Some
+ (rs1) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s2367_
+ _s1697_) >>= fun w__193 : option (mword 5) =>
+ (match w__193 with
+ | Some
+ (rs1) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2375_
+ _s1697_) >>= fun w__196 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__196 with
+ | Some
+ ((rd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2375_
+ _s1697_) >>= fun w__197 : option ((mword 5 * mword 5)) =>
+ (match w__197 with
+ | Some
+ ((rd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else if
+ ((generic_eq
+ _s1697_
+ "c.ebreak"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2387_
+ _s1697_) >>= fun w__200 : option ((mword 5 * mword 5)) =>
+ (if
+ ((match w__200 with
+ | Some
+ ((rsd, rs2)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s2387_
+ _s1697_) >>= fun w__201 : option ((mword 5 * mword 5)) =>
+ (match w__201 with
+ | Some
+ ((rsd, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2399_
+ _s1697_) >>= fun w__204 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__204 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2399_
+ _s1697_) >>= fun w__205 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__205 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2416_
+ _s1697_) >>= fun w__208 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__208 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2416_
+ _s1697_) >>= fun w__209 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__209 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2434_
+ _s1697_) >>= fun w__212 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__212 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2434_
+ _s1697_) >>= fun w__213 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__213 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2452_
+ _s1697_) >>= fun w__216 : option ((mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2452_
+ _s1697_) >>= fun w__217 : option ((mword 5 * mword 5 * mword 5)) =>
+ (match w__217 with
+ | Some
+ ((rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2468_
+ _s1697_) >>= fun w__220 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2468_
+ _s1697_) >>= fun w__221 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__221 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2487_
+ _s1697_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s2487_
+ _s1697_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2506_
+ _s1697_) >>= fun w__228 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2506_
+ _s1697_) >>= fun w__229 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__229 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2524_
+ _s1697_) >>= fun w__232 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2524_
+ _s1697_) >>= fun w__233 : option ((csrop * mword 5 * mword 5 * mword 12)) =>
+ (match w__233 with
+ | Some
+ ((op, rd, rs1, csr)) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else if
+ ((generic_eq
+ _s1697_
+ "uret"))
+ then
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ else
+ (_s2541_
+ _s1697_) >>= fun w__236 : option (mword 32) =>
+ (if
+ ((match w__236 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2541_
+ _s1697_) >>= fun w__237 : option (mword 32) =>
+ (match w__237 with
+ | Some
+ (s) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ (_s2549_
+ _s1697_) >>= fun w__240 : option (mword 16) =>
+ (if
+ ((match w__240 with
+ | Some
+ (s) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s2549_
+ _s1697_) >>= fun w__241 : option (mword 16) =>
+ (match w__241 with
+ | Some
+ (s) =>
+ returnm (projT1
+ (build_ex
+ true
+ : {_bool : bool & ArithFact (_bool =
+ true)}))
+ | _ =>
+ exit tt
+ : M (bool)
+ end)
+ : M (bool)
+ else
+ returnm (projT1
+ (build_ex
+ false
+ : {_bool : bool & ArithFact (not (_bool =
+ true))})))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool))
+ : M (bool).
+
+Definition _s3457_ (_s3458_ : string)
+: M (option ((mword 16 * string))) :=
+
+ let _s3459_ := _s3458_ in
+ (if ((string_startswith _s3459_ "c.illegal")) then
+ (match (string_drop _s3459_ (projT1 (string_length "c.illegal"))) with
+ | _s3460_ =>
+ (spc_matches_prefix _s3460_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3461_ _)) =>
+ match (string_drop _s3460_ _s3461_) with
+ | _s3462_ =>
+ match (hex_bits_16_matches_prefix _s3462_) with
+ | Some ((s, existT _ _s3463_ _)) =>
+ match (string_drop _s3462_ _s3463_) with | s_ => Some ((s, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 16 * string)))
+ end)
+ : M (option ((mword 16 * string)))
+ else returnm (None : option ((mword 16 * string))))
+ : M (option ((mword 16 * string))).
+
+Definition _s3449_ (_s3450_ : string)
+: M (option ((mword 32 * string))) :=
+
+ let _s3451_ := _s3450_ in
+ (if ((string_startswith _s3451_ "illegal")) then
+ (match (string_drop _s3451_ (projT1 (string_length "illegal"))) with
+ | _s3452_ =>
+ (spc_matches_prefix _s3452_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3453_ _)) =>
+ match (string_drop _s3452_ _s3453_) with
+ | _s3454_ =>
+ match (hex_bits_32_matches_prefix _s3454_) with
+ | Some ((s, existT _ _s3455_ _)) =>
+ match (string_drop _s3454_ _s3455_) with | s_ => Some ((s, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 32 * string)))
+ end)
+ : M (option ((mword 32 * string)))
+ else returnm (None : option ((mword 32 * string))))
+ : M (option ((mword 32 * string))).
+
+Definition _s3445_ (_s3446_ : string)
+: option string :=
+
+ let _s3447_ := _s3446_ in
+ if ((string_startswith _s3447_ "uret")) then
+ match (string_drop _s3447_ (projT1 (string_length "uret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s3428_ (_s3429_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s3429_ with
+ | _s3430_ =>
+ (csr_mnemonic_matches_prefix _s3430_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s3431_ _)) =>
+ (match (string_drop _s3430_ _s3431_) with
+ | _s3432_ =>
+ (spc_matches_prefix _s3432_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3433_ _)) =>
+ (match (string_drop _s3432_ _s3433_) with
+ | _s3434_ =>
+ (reg_name_matches_prefix _s3434_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3435_ _)) =>
+ (match (string_drop _s3434_ _s3435_) with
+ | _s3436_ =>
+ (sep_matches_prefix _s3436_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3437_ _)) =>
+ (match (string_drop _s3436_ _s3437_) with
+ | _s3438_ =>
+ (reg_name_matches_prefix _s3438_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3439_ _)) =>
+ (match (string_drop _s3438_ _s3439_) with
+ | _s3440_ =>
+ (sep_matches_prefix _s3440_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3441_ _)) =>
+ (match (string_drop _s3440_ _s3441_) with
+ | _s3442_ =>
+ (csr_name_map_matches_prefix _s3442_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((csr, existT _ _s3443_ _)) =>
+ match (string_drop _s3442_
+ _s3443_) with
+ | s_ =>
+ Some ((op, rd, rs1, csr, s_))
+ end
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s3410_ (_s3411_ : string)
+: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s3411_ with
+ | _s3412_ =>
+ (csr_mnemonic_matches_prefix _s3412_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s3413_ _)) =>
+ let _s3414_ := string_drop _s3412_ _s3413_ in
+ (if ((string_startswith _s3414_ "i")) then
+ (match (string_drop _s3414_ (projT1 (string_length "i"))) with
+ | _s3415_ =>
+ (spc_matches_prefix _s3415_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3416_ _)) =>
+ (match (string_drop _s3415_ _s3416_) with
+ | _s3417_ =>
+ (reg_name_matches_prefix _s3417_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3418_ _)) =>
+ (match (string_drop _s3417_ _s3418_) with
+ | _s3419_ =>
+ (sep_matches_prefix _s3419_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3420_ _)) =>
+ (match (string_drop _s3419_ _s3420_) with
+ | _s3421_ =>
+ (match (hex_bits_5_matches_prefix _s3421_) with
+ | Some ((rs1, existT _ _s3422_ _)) =>
+ (match (string_drop _s3421_ _s3422_) with
+ | _s3423_ =>
+ (sep_matches_prefix _s3423_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s3424_ _)) =>
+ (match (string_drop _s3423_ _s3424_) with
+ | _s3425_ =>
+ (csr_name_map_matches_prefix _s3425_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some
+ ((csr, existT _ _s3426_ _)) =>
+ match (string_drop _s3425_
+ _s3426_) with
+ | s_ =>
+ Some
+ ((op, rd, rs1, csr, s_))
+ end
+ | _ => None
+ end)
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s3391_ (_s3392_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3393_ := _s3392_ in
+ (if ((string_startswith _s3393_ "rem")) then
+ (match (string_drop _s3393_ (projT1 (string_length "rem"))) with
+ | _s3394_ =>
+ (maybe_not_u_matches_prefix _s3394_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3395_ _)) =>
+ let _s3396_ := string_drop _s3394_ _s3395_ in
+ (if ((string_startswith _s3396_ "w")) then
+ (match (string_drop _s3396_ (projT1 (string_length "w"))) with
+ | _s3397_ =>
+ (spc_matches_prefix _s3397_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3398_ _)) =>
+ (match (string_drop _s3397_ _s3398_) with
+ | _s3399_ =>
+ (reg_name_matches_prefix _s3399_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3400_ _)) =>
+ (match (string_drop _s3399_ _s3400_) with
+ | _s3401_ =>
+ (sep_matches_prefix _s3401_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3402_ _)) =>
+ (match (string_drop _s3401_ _s3402_) with
+ | _s3403_ =>
+ (reg_name_matches_prefix _s3403_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3404_ _)) =>
+ (match (string_drop _s3403_ _s3404_) with
+ | _s3405_ =>
+ (sep_matches_prefix _s3405_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3406_ _)) =>
+ (match (string_drop _s3405_ _s3406_) with
+ | _s3407_ =>
+ (reg_name_matches_prefix _s3407_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3408_ _)) =>
+ match (string_drop _s3407_
+ _s3408_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3372_ (_s3373_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3374_ := _s3373_ in
+ (if ((string_startswith _s3374_ "div")) then
+ (match (string_drop _s3374_ (projT1 (string_length "div"))) with
+ | _s3375_ =>
+ (maybe_not_u_matches_prefix _s3375_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3376_ _)) =>
+ let _s3377_ := string_drop _s3375_ _s3376_ in
+ (if ((string_startswith _s3377_ "w")) then
+ (match (string_drop _s3377_ (projT1 (string_length "w"))) with
+ | _s3378_ =>
+ (spc_matches_prefix _s3378_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3379_ _)) =>
+ (match (string_drop _s3378_ _s3379_) with
+ | _s3380_ =>
+ (reg_name_matches_prefix _s3380_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3381_ _)) =>
+ (match (string_drop _s3380_ _s3381_) with
+ | _s3382_ =>
+ (sep_matches_prefix _s3382_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3383_ _)) =>
+ (match (string_drop _s3382_ _s3383_) with
+ | _s3384_ =>
+ (reg_name_matches_prefix _s3384_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3385_ _)) =>
+ (match (string_drop _s3384_ _s3385_) with
+ | _s3386_ =>
+ (sep_matches_prefix _s3386_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3387_ _)) =>
+ (match (string_drop _s3386_ _s3387_) with
+ | _s3388_ =>
+ (reg_name_matches_prefix _s3388_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3389_ _)) =>
+ match (string_drop _s3388_
+ _s3389_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3356_ (_s3357_ : string)
+: M (option ((mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3358_ := _s3357_ in
+ (if ((string_startswith _s3358_ "mulw")) then
+ (match (string_drop _s3358_ (projT1 (string_length "mulw"))) with
+ | _s3359_ =>
+ (spc_matches_prefix _s3359_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3360_ _)) =>
+ (match (string_drop _s3359_ _s3360_) with
+ | _s3361_ =>
+ (reg_name_matches_prefix _s3361_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3362_ _)) =>
+ (match (string_drop _s3361_ _s3362_) with
+ | _s3363_ =>
+ (sep_matches_prefix _s3363_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3364_ _)) =>
+ (match (string_drop _s3363_ _s3364_) with
+ | _s3365_ =>
+ (reg_name_matches_prefix _s3365_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s3366_ _)) =>
+ (match (string_drop _s3365_ _s3366_) with
+ | _s3367_ =>
+ (sep_matches_prefix _s3367_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s3368_ _)) =>
+ (match (string_drop _s3367_ _s3368_) with
+ | _s3369_ =>
+ (reg_name_matches_prefix _s3369_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((rs2, existT _ _s3370_ _)) =>
+ match (string_drop _s3369_ _s3370_) with
+ | s_ => Some ((rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3338_ (_s3339_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3340_ := _s3339_ in
+ (if ((string_startswith _s3340_ "rem")) then
+ (match (string_drop _s3340_ (projT1 (string_length "rem"))) with
+ | _s3341_ =>
+ (maybe_not_u_matches_prefix _s3341_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3342_ _)) =>
+ (match (string_drop _s3341_ _s3342_) with
+ | _s3343_ =>
+ (spc_matches_prefix _s3343_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3344_ _)) =>
+ (match (string_drop _s3343_ _s3344_) with
+ | _s3345_ =>
+ (reg_name_matches_prefix _s3345_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3346_ _)) =>
+ (match (string_drop _s3345_ _s3346_) with
+ | _s3347_ =>
+ (sep_matches_prefix _s3347_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3348_ _)) =>
+ (match (string_drop _s3347_ _s3348_) with
+ | _s3349_ =>
+ (reg_name_matches_prefix _s3349_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3350_ _)) =>
+ (match (string_drop _s3349_ _s3350_) with
+ | _s3351_ =>
+ (sep_matches_prefix _s3351_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3352_ _)) =>
+ (match (string_drop _s3351_ _s3352_) with
+ | _s3353_ =>
+ (reg_name_matches_prefix _s3353_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3354_ _)) =>
+ match (string_drop _s3353_
+ _s3354_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3320_ (_s3321_ : string)
+: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s3322_ := _s3321_ in
+ (if ((string_startswith _s3322_ "div")) then
+ (match (string_drop _s3322_ (projT1 (string_length "div"))) with
+ | _s3323_ =>
+ (maybe_not_u_matches_prefix _s3323_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((s, existT _ _s3324_ _)) =>
+ (match (string_drop _s3323_ _s3324_) with
+ | _s3325_ =>
+ (spc_matches_prefix _s3325_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3326_ _)) =>
+ (match (string_drop _s3325_ _s3326_) with
+ | _s3327_ =>
+ (reg_name_matches_prefix _s3327_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3328_ _)) =>
+ (match (string_drop _s3327_ _s3328_) with
+ | _s3329_ =>
+ (sep_matches_prefix _s3329_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3330_ _)) =>
+ (match (string_drop _s3329_ _s3330_) with
+ | _s3331_ =>
+ (reg_name_matches_prefix _s3331_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3332_ _)) =>
+ (match (string_drop _s3331_ _s3332_) with
+ | _s3333_ =>
+ (sep_matches_prefix _s3333_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3334_ _)) =>
+ (match (string_drop _s3333_ _s3334_) with
+ | _s3335_ =>
+ (reg_name_matches_prefix _s3335_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs2, existT _ _s3336_ _)) =>
+ match (string_drop _s3335_
+ _s3336_) with
+ | s_ =>
+ Some
+ ((s, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string)))
+ else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3303_ (_s3304_ : string)
+: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s3304_ with
+ | _s3305_ =>
+ (mul_mnemonic_matches_prefix _s3305_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some (((high, signed1, signed2), existT _ _s3306_ _)) =>
+ (match (string_drop _s3305_ _s3306_) with
+ | _s3307_ =>
+ (spc_matches_prefix _s3307_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s3308_ _)) =>
+ (match (string_drop _s3307_ _s3308_) with
+ | _s3309_ =>
+ (reg_name_matches_prefix _s3309_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s3310_ _)) =>
+ (match (string_drop _s3309_ _s3310_) with
+ | _s3311_ =>
+ (sep_matches_prefix _s3311_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s3312_ _)) =>
+ (match (string_drop _s3311_ _s3312_) with
+ | _s3313_ =>
+ (reg_name_matches_prefix _s3313_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s3314_ _)) =>
+ (match (string_drop _s3313_ _s3314_) with
+ | _s3315_ =>
+ (sep_matches_prefix _s3315_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s3316_ _)) =>
+ (match (string_drop _s3315_ _s3316_) with
+ | _s3317_ =>
+ (reg_name_matches_prefix _s3317_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s3318_ _)) =>
+ match (string_drop _s3317_
+ _s3318_) with
+ | s_ =>
+ Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s3291_ (_s3292_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s3293_ := _s3292_ in
+ (if ((string_startswith _s3293_ "c.add")) then
+ (match (string_drop _s3293_ (projT1 (string_length "c.add"))) with
+ | _s3294_ =>
+ (spc_matches_prefix _s3294_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3295_ _)) =>
+ (match (string_drop _s3294_ _s3295_) with
+ | _s3296_ =>
+ (reg_name_matches_prefix _s3296_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3297_ _)) =>
+ (match (string_drop _s3296_ _s3297_) with
+ | _s3298_ =>
+ (sep_matches_prefix _s3298_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3299_ _)) =>
+ (match (string_drop _s3298_ _s3299_) with
+ | _s3300_ =>
+ (reg_name_matches_prefix _s3300_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3301_ _)) =>
+ match (string_drop _s3300_ _s3301_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s3287_ (_s3288_ : string)
+: option string :=
+
+ let _s3289_ := _s3288_ in
+ if ((string_startswith _s3289_ "c.ebreak")) then
+ match (string_drop _s3289_ (projT1 (string_length "c.ebreak"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s3275_ (_s3276_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s3277_ := _s3276_ in
+ (if ((string_startswith _s3277_ "c.mv")) then
+ (match (string_drop _s3277_ (projT1 (string_length "c.mv"))) with
+ | _s3278_ =>
+ (spc_matches_prefix _s3278_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3279_ _)) =>
+ (match (string_drop _s3278_ _s3279_) with
+ | _s3280_ =>
+ (reg_name_matches_prefix _s3280_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3281_ _)) =>
+ (match (string_drop _s3280_ _s3281_) with
+ | _s3282_ =>
+ (sep_matches_prefix _s3282_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3283_ _)) =>
+ (match (string_drop _s3282_ _s3283_) with
+ | _s3284_ =>
+ (reg_name_matches_prefix _s3284_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3285_ _)) =>
+ match (string_drop _s3284_ _s3285_) with
+ | s_ => Some ((rd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s3267_ (_s3268_ : string)
+: M (option ((mword 5 * string))) :=
+
+ let _s3269_ := _s3268_ in
+ (if ((string_startswith _s3269_ "c.jalr")) then
+ (match (string_drop _s3269_ (projT1 (string_length "c.jalr"))) with
+ | _s3270_ =>
+ (spc_matches_prefix _s3270_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3271_ _)) =>
+ (match (string_drop _s3270_ _s3271_) with
+ | _s3272_ =>
+ (reg_name_matches_prefix _s3272_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s3273_ _)) =>
+ match (string_drop _s3272_ _s3273_) with | s_ => Some ((rs1, s_)) end
+ | _ => None
+ end)
+ : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ else returnm (None : option ((mword 5 * string))))
+ : M (option ((mword 5 * string))).
+
+Definition _s3259_ (_s3260_ : string)
+: M (option ((mword 5 * string))) :=
+
+ let _s3261_ := _s3260_ in
+ (if ((string_startswith _s3261_ "c.jr")) then
+ (match (string_drop _s3261_ (projT1 (string_length "c.jr"))) with
+ | _s3262_ =>
+ (spc_matches_prefix _s3262_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3263_ _)) =>
+ (match (string_drop _s3262_ _s3263_) with
+ | _s3264_ =>
+ (reg_name_matches_prefix _s3264_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__1 with
+ | Some ((rs1, existT _ _s3265_ _)) =>
+ match (string_drop _s3264_ _s3265_) with | s_ => Some ((rs1, s_)) end
+ | _ => None
+ end)
+ : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ end)
+ : M (option ((mword 5 * string)))
+ else returnm (None : option ((mword 5 * string))))
+ : M (option ((mword 5 * string))).
+
+Definition _s3247_ (_s3248_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3249_ := _s3248_ in
+ (if ((string_startswith _s3249_ "c.sdsp")) then
+ (match (string_drop _s3249_ (projT1 (string_length "c.sdsp"))) with
+ | _s3250_ =>
+ (spc_matches_prefix _s3250_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3251_ _)) =>
+ (match (string_drop _s3250_ _s3251_) with
+ | _s3252_ =>
+ (reg_name_matches_prefix _s3252_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs2, existT _ _s3253_ _)) =>
+ (match (string_drop _s3252_ _s3253_) with
+ | _s3254_ =>
+ (sep_matches_prefix _s3254_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3255_ _)) =>
+ match (string_drop _s3254_ _s3255_) with
+ | _s3256_ =>
+ match (hex_bits_6_matches_prefix _s3256_) with
+ | Some ((uimm, existT _ _s3257_ _)) =>
+ match (string_drop _s3256_ _s3257_) with
+ | s_ => Some ((rs2, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3235_ (_s3236_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3237_ := _s3236_ in
+ (if ((string_startswith _s3237_ "c.swsp")) then
+ (match (string_drop _s3237_ (projT1 (string_length "c.swsp"))) with
+ | _s3238_ =>
+ (spc_matches_prefix _s3238_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3239_ _)) =>
+ (match (string_drop _s3238_ _s3239_) with
+ | _s3240_ =>
+ (reg_name_matches_prefix _s3240_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3241_ _)) =>
+ (match (string_drop _s3240_ _s3241_) with
+ | _s3242_ =>
+ (sep_matches_prefix _s3242_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3243_ _)) =>
+ match (string_drop _s3242_ _s3243_) with
+ | _s3244_ =>
+ match (hex_bits_6_matches_prefix _s3244_) with
+ | Some ((uimm, existT _ _s3245_ _)) =>
+ match (string_drop _s3244_ _s3245_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3223_ (_s3224_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3225_ := _s3224_ in
+ (if ((string_startswith _s3225_ "c.ldsp")) then
+ (match (string_drop _s3225_ (projT1 (string_length "c.ldsp"))) with
+ | _s3226_ =>
+ (spc_matches_prefix _s3226_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3227_ _)) =>
+ (match (string_drop _s3226_ _s3227_) with
+ | _s3228_ =>
+ (reg_name_matches_prefix _s3228_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3229_ _)) =>
+ (match (string_drop _s3228_ _s3229_) with
+ | _s3230_ =>
+ (sep_matches_prefix _s3230_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3231_ _)) =>
+ match (string_drop _s3230_ _s3231_) with
+ | _s3232_ =>
+ match (hex_bits_6_matches_prefix _s3232_) with
+ | Some ((uimm, existT _ _s3233_ _)) =>
+ match (string_drop _s3232_ _s3233_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3211_ (_s3212_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3213_ := _s3212_ in
+ (if ((string_startswith _s3213_ "c.lwsp")) then
+ (match (string_drop _s3213_ (projT1 (string_length "c.lwsp"))) with
+ | _s3214_ =>
+ (spc_matches_prefix _s3214_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3215_ _)) =>
+ (match (string_drop _s3214_ _s3215_) with
+ | _s3216_ =>
+ (reg_name_matches_prefix _s3216_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3217_ _)) =>
+ (match (string_drop _s3216_ _s3217_) with
+ | _s3218_ =>
+ (sep_matches_prefix _s3218_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3219_ _)) =>
+ match (string_drop _s3218_ _s3219_) with
+ | _s3220_ =>
+ match (hex_bits_6_matches_prefix _s3220_) with
+ | Some ((uimm, existT _ _s3221_ _)) =>
+ match (string_drop _s3220_ _s3221_) with
+ | s_ => Some ((rd, uimm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3199_ (_s3200_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3201_ := _s3200_ in
+ (if ((string_startswith _s3201_ "c.slli")) then
+ (match (string_drop _s3201_ (projT1 (string_length "c.slli"))) with
+ | _s3202_ =>
+ (spc_matches_prefix _s3202_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3203_ _)) =>
+ (match (string_drop _s3202_ _s3203_) with
+ | _s3204_ =>
+ (reg_name_matches_prefix _s3204_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3205_ _)) =>
+ (match (string_drop _s3204_ _s3205_) with
+ | _s3206_ =>
+ (sep_matches_prefix _s3206_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3207_ _)) =>
+ match (string_drop _s3206_ _s3207_) with
+ | _s3208_ =>
+ match (hex_bits_6_matches_prefix _s3208_) with
+ | Some ((shamt, existT _ _s3209_ _)) =>
+ match (string_drop _s3208_ _s3209_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3187_ (_s3188_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s3189_ := _s3188_ in
+ (if ((string_startswith _s3189_ "c.bnez")) then
+ (match (string_drop _s3189_ (projT1 (string_length "c.bnez"))) with
+ | _s3190_ =>
+ (spc_matches_prefix _s3190_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3191_ _)) =>
+ (match (string_drop _s3190_ _s3191_) with
+ | _s3192_ =>
+ (creg_name_matches_prefix _s3192_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s3193_ _)) =>
+ (match (string_drop _s3192_ _s3193_) with
+ | _s3194_ =>
+ (sep_matches_prefix _s3194_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3195_ _)) =>
+ match (string_drop _s3194_ _s3195_) with
+ | _s3196_ =>
+ match (hex_bits_8_matches_prefix _s3196_) with
+ | Some ((imm, existT _ _s3197_ _)) =>
+ match (string_drop _s3196_ _s3197_) with
+ | s_ => Some ((rs, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s3175_ (_s3176_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s3177_ := _s3176_ in
+ (if ((string_startswith _s3177_ "c.beqz")) then
+ (match (string_drop _s3177_ (projT1 (string_length "c.beqz"))) with
+ | _s3178_ =>
+ (spc_matches_prefix _s3178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3179_ _)) =>
+ (match (string_drop _s3178_ _s3179_) with
+ | _s3180_ =>
+ (creg_name_matches_prefix _s3180_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs, existT _ _s3181_ _)) =>
+ (match (string_drop _s3180_ _s3181_) with
+ | _s3182_ =>
+ (sep_matches_prefix _s3182_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3183_ _)) =>
+ match (string_drop _s3182_ _s3183_) with
+ | _s3184_ =>
+ match (hex_bits_8_matches_prefix _s3184_) with
+ | Some ((imm, existT _ _s3185_ _)) =>
+ match (string_drop _s3184_ _s3185_) with
+ | s_ => Some ((rs, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s3167_ (_s3168_ : string)
+: M (option ((mword 11 * string))) :=
+
+ let _s3169_ := _s3168_ in
+ (if ((string_startswith _s3169_ "c.j")) then
+ (match (string_drop _s3169_ (projT1 (string_length "c.j"))) with
+ | _s3170_ =>
+ (spc_matches_prefix _s3170_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3171_ _)) =>
+ match (string_drop _s3170_ _s3171_) with
+ | _s3172_ =>
+ match (hex_bits_11_matches_prefix _s3172_) with
+ | Some ((imm, existT _ _s3173_ _)) =>
+ match (string_drop _s3172_ _s3173_) with | s_ => Some ((imm, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 11 * string)))
+ end)
+ : M (option ((mword 11 * string)))
+ else returnm (None : option ((mword 11 * string))))
+ : M (option ((mword 11 * string))).
+
+Definition _s3155_ (_s3156_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3157_ := _s3156_ in
+ (if ((string_startswith _s3157_ "c.addw")) then
+ (match (string_drop _s3157_ (projT1 (string_length "c.addw"))) with
+ | _s3158_ =>
+ (spc_matches_prefix _s3158_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3159_ _)) =>
+ (match (string_drop _s3158_ _s3159_) with
+ | _s3160_ =>
+ (creg_name_matches_prefix _s3160_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3161_ _)) =>
+ (match (string_drop _s3160_ _s3161_) with
+ | _s3162_ =>
+ (sep_matches_prefix _s3162_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3163_ _)) =>
+ (match (string_drop _s3162_ _s3163_) with
+ | _s3164_ =>
+ (creg_name_matches_prefix _s3164_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3165_ _)) =>
+ match (string_drop _s3164_ _s3165_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3143_ (_s3144_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3145_ := _s3144_ in
+ (if ((string_startswith _s3145_ "c.subw")) then
+ (match (string_drop _s3145_ (projT1 (string_length "c.subw"))) with
+ | _s3146_ =>
+ (spc_matches_prefix _s3146_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3147_ _)) =>
+ (match (string_drop _s3146_ _s3147_) with
+ | _s3148_ =>
+ (creg_name_matches_prefix _s3148_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3149_ _)) =>
+ (match (string_drop _s3148_ _s3149_) with
+ | _s3150_ =>
+ (sep_matches_prefix _s3150_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3151_ _)) =>
+ (match (string_drop _s3150_ _s3151_) with
+ | _s3152_ =>
+ (creg_name_matches_prefix _s3152_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3153_ _)) =>
+ match (string_drop _s3152_ _s3153_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3131_ (_s3132_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3133_ := _s3132_ in
+ (if ((string_startswith _s3133_ "c.and")) then
+ (match (string_drop _s3133_ (projT1 (string_length "c.and"))) with
+ | _s3134_ =>
+ (spc_matches_prefix _s3134_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3135_ _)) =>
+ (match (string_drop _s3134_ _s3135_) with
+ | _s3136_ =>
+ (creg_name_matches_prefix _s3136_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3137_ _)) =>
+ (match (string_drop _s3136_ _s3137_) with
+ | _s3138_ =>
+ (sep_matches_prefix _s3138_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3139_ _)) =>
+ (match (string_drop _s3138_ _s3139_) with
+ | _s3140_ =>
+ (creg_name_matches_prefix _s3140_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3141_ _)) =>
+ match (string_drop _s3140_ _s3141_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3119_ (_s3120_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3121_ := _s3120_ in
+ (if ((string_startswith _s3121_ "c.or")) then
+ (match (string_drop _s3121_ (projT1 (string_length "c.or"))) with
+ | _s3122_ =>
+ (spc_matches_prefix _s3122_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3123_ _)) =>
+ (match (string_drop _s3122_ _s3123_) with
+ | _s3124_ =>
+ (creg_name_matches_prefix _s3124_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3125_ _)) =>
+ (match (string_drop _s3124_ _s3125_) with
+ | _s3126_ =>
+ (sep_matches_prefix _s3126_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3127_ _)) =>
+ (match (string_drop _s3126_ _s3127_) with
+ | _s3128_ =>
+ (creg_name_matches_prefix _s3128_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3129_ _)) =>
+ match (string_drop _s3128_ _s3129_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3107_ (_s3108_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3109_ := _s3108_ in
+ (if ((string_startswith _s3109_ "c.xor")) then
+ (match (string_drop _s3109_ (projT1 (string_length "c.xor"))) with
+ | _s3110_ =>
+ (spc_matches_prefix _s3110_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3111_ _)) =>
+ (match (string_drop _s3110_ _s3111_) with
+ | _s3112_ =>
+ (creg_name_matches_prefix _s3112_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3113_ _)) =>
+ (match (string_drop _s3112_ _s3113_) with
+ | _s3114_ =>
+ (sep_matches_prefix _s3114_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3115_ _)) =>
+ (match (string_drop _s3114_ _s3115_) with
+ | _s3116_ =>
+ (creg_name_matches_prefix _s3116_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3117_ _)) =>
+ match (string_drop _s3116_ _s3117_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3095_ (_s3096_ : string)
+: M (option ((mword 3 * mword 3 * string))) :=
+
+ let _s3097_ := _s3096_ in
+ (if ((string_startswith _s3097_ "c.sub")) then
+ (match (string_drop _s3097_ (projT1 (string_length "c.sub"))) with
+ | _s3098_ =>
+ (spc_matches_prefix _s3098_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3099_ _)) =>
+ (match (string_drop _s3098_ _s3099_) with
+ | _s3100_ =>
+ (creg_name_matches_prefix _s3100_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3101_ _)) =>
+ (match (string_drop _s3100_ _s3101_) with
+ | _s3102_ =>
+ (sep_matches_prefix _s3102_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s3103_ _)) =>
+ (match (string_drop _s3102_ _s3103_) with
+ | _s3104_ =>
+ (creg_name_matches_prefix _s3104_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s3105_ _)) =>
+ match (string_drop _s3104_ _s3105_) with
+ | s_ => Some ((rsd, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * string))))
+ : M (option ((mword 3 * mword 3 * string))).
+
+Definition _s3083_ (_s3084_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3085_ := _s3084_ in
+ (if ((string_startswith _s3085_ "c.andi")) then
+ (match (string_drop _s3085_ (projT1 (string_length "c.andi"))) with
+ | _s3086_ =>
+ (spc_matches_prefix _s3086_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3087_ _)) =>
+ (match (string_drop _s3086_ _s3087_) with
+ | _s3088_ =>
+ (creg_name_matches_prefix _s3088_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3089_ _)) =>
+ (match (string_drop _s3088_ _s3089_) with
+ | _s3090_ =>
+ (sep_matches_prefix _s3090_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3091_ _)) =>
+ match (string_drop _s3090_ _s3091_) with
+ | _s3092_ =>
+ match (hex_bits_6_matches_prefix _s3092_) with
+ | Some ((imm, existT _ _s3093_ _)) =>
+ match (string_drop _s3092_ _s3093_) with
+ | s_ => Some ((rsd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3071_ (_s3072_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3073_ := _s3072_ in
+ (if ((string_startswith _s3073_ "c.srai")) then
+ (match (string_drop _s3073_ (projT1 (string_length "c.srai"))) with
+ | _s3074_ =>
+ (spc_matches_prefix _s3074_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3075_ _)) =>
+ (match (string_drop _s3074_ _s3075_) with
+ | _s3076_ =>
+ (creg_name_matches_prefix _s3076_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3077_ _)) =>
+ (match (string_drop _s3076_ _s3077_) with
+ | _s3078_ =>
+ (sep_matches_prefix _s3078_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3079_ _)) =>
+ match (string_drop _s3078_ _s3079_) with
+ | _s3080_ =>
+ match (hex_bits_6_matches_prefix _s3080_) with
+ | Some ((shamt, existT _ _s3081_ _)) =>
+ match (string_drop _s3080_ _s3081_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3059_ (_s3060_ : string)
+: M (option ((mword 3 * mword 6 * string))) :=
+
+ let _s3061_ := _s3060_ in
+ (if ((string_startswith _s3061_ "c.srli")) then
+ (match (string_drop _s3061_ (projT1 (string_length "c.srli"))) with
+ | _s3062_ =>
+ (spc_matches_prefix _s3062_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3063_ _)) =>
+ (match (string_drop _s3062_ _s3063_) with
+ | _s3064_ =>
+ (creg_name_matches_prefix _s3064_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3065_ _)) =>
+ (match (string_drop _s3064_ _s3065_) with
+ | _s3066_ =>
+ (sep_matches_prefix _s3066_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3067_ _)) =>
+ match (string_drop _s3066_ _s3067_) with
+ | _s3068_ =>
+ match (hex_bits_6_matches_prefix _s3068_) with
+ | Some ((shamt, existT _ _s3069_ _)) =>
+ match (string_drop _s3068_ _s3069_) with
+ | s_ => Some ((rsd, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ end)
+ : M (option ((mword 3 * mword 6 * string)))
+ else returnm (None : option ((mword 3 * mword 6 * string))))
+ : M (option ((mword 3 * mword 6 * string))).
+
+Definition _s3047_ (_s3048_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3049_ := _s3048_ in
+ (if ((string_startswith _s3049_ "c.lui")) then
+ (match (string_drop _s3049_ (projT1 (string_length "c.lui"))) with
+ | _s3050_ =>
+ (spc_matches_prefix _s3050_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3051_ _)) =>
+ (match (string_drop _s3050_ _s3051_) with
+ | _s3052_ =>
+ (reg_name_matches_prefix _s3052_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3053_ _)) =>
+ (match (string_drop _s3052_ _s3053_) with
+ | _s3054_ =>
+ (sep_matches_prefix _s3054_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3055_ _)) =>
+ match (string_drop _s3054_ _s3055_) with
+ | _s3056_ =>
+ match (hex_bits_6_matches_prefix _s3056_) with
+ | Some ((imm, existT _ _s3057_ _)) =>
+ match (string_drop _s3056_ _s3057_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3039_ (_s3040_ : string)
+: M (option ((mword 6 * string))) :=
+
+ let _s3041_ := _s3040_ in
+ (if ((string_startswith _s3041_ "c.addi16sp")) then
+ (match (string_drop _s3041_ (projT1 (string_length "c.addi16sp"))) with
+ | _s3042_ =>
+ (spc_matches_prefix _s3042_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3043_ _)) =>
+ match (string_drop _s3042_ _s3043_) with
+ | _s3044_ =>
+ match (hex_bits_6_matches_prefix _s3044_) with
+ | Some ((imm, existT _ _s3045_ _)) =>
+ match (string_drop _s3044_ _s3045_) with | s_ => Some ((imm, s_)) end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 6 * string)))
+ end)
+ : M (option ((mword 6 * string)))
+ else returnm (None : option ((mword 6 * string))))
+ : M (option ((mword 6 * string))).
+
+Definition _s3027_ (_s3028_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3029_ := _s3028_ in
+ (if ((string_startswith _s3029_ "c.li")) then
+ (match (string_drop _s3029_ (projT1 (string_length "c.li"))) with
+ | _s3030_ =>
+ (spc_matches_prefix _s3030_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3031_ _)) =>
+ (match (string_drop _s3030_ _s3031_) with
+ | _s3032_ =>
+ (reg_name_matches_prefix _s3032_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s3033_ _)) =>
+ (match (string_drop _s3032_ _s3033_) with
+ | _s3034_ =>
+ (sep_matches_prefix _s3034_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3035_ _)) =>
+ match (string_drop _s3034_ _s3035_) with
+ | _s3036_ =>
+ match (hex_bits_6_matches_prefix _s3036_) with
+ | Some ((imm, existT _ _s3037_ _)) =>
+ match (string_drop _s3036_ _s3037_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3015_ (_s3016_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s3017_ := _s3016_ in
+ (if ((string_startswith _s3017_ "c.addiw")) then
+ (match (string_drop _s3017_ (projT1 (string_length "c.addiw"))) with
+ | _s3018_ =>
+ (spc_matches_prefix _s3018_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s3019_ _)) =>
+ (match (string_drop _s3018_ _s3019_) with
+ | _s3020_ =>
+ (reg_name_matches_prefix _s3020_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3021_ _)) =>
+ (match (string_drop _s3020_ _s3021_) with
+ | _s3022_ =>
+ (sep_matches_prefix _s3022_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3023_ _)) =>
+ match (string_drop _s3022_ _s3023_) with
+ | _s3024_ =>
+ match (hex_bits_6_matches_prefix _s3024_) with
+ | Some ((imm, existT _ _s3025_ _)) =>
+ match (string_drop _s3024_ _s3025_) with
+ | s_ => Some ((rsd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s3007_ (_s3008_ : string)
+: M (option ((mword 11 * string))) :=
+
+ let _s3009_ := _s3008_ in
+ (if ((string_startswith _s3009_ "c.jal")) then
+ (match (string_drop _s3009_ (projT1 (string_length "c.jal"))) with
+ | _s3010_ =>
+ (spc_matches_prefix _s3010_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ returnm ((match w__0 with
+ | Some ((tt, existT _ _s3011_ _)) =>
+ match (string_drop _s3010_ _s3011_) with
+ | _s3012_ =>
+ match (hex_bits_12_matches_prefix _s3012_) with
+ | Some ((v__826, existT _ _s3013_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__826 0 0)
+ (vec_of_bits [B0] : mword (0 - 0 + 1)))) then
+ let imm : mword 11 := subrange_vec_dec v__826 11 1 in
+ let imm : mword 11 := subrange_vec_dec v__826 11 1 in
+ match (string_drop _s3012_ _s3013_) with | s_ => Some ((imm, s_)) end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 11 * string)))
+ end)
+ : M (option ((mword 11 * string)))
+ else returnm (None : option ((mword 11 * string))))
+ : M (option ((mword 11 * string))).
+
+Definition _s2995_ (_s2996_ : string)
+: M (option ((mword 5 * mword 6 * string))) :=
+
+ let _s2997_ := _s2996_ in
+ (if ((string_startswith _s2997_ "c.addi")) then
+ (match (string_drop _s2997_ (projT1 (string_length "c.addi"))) with
+ | _s2998_ =>
+ (spc_matches_prefix _s2998_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2999_ _)) =>
+ (match (string_drop _s2998_ _s2999_) with
+ | _s3000_ =>
+ (reg_name_matches_prefix _s3000_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsd, existT _ _s3001_ _)) =>
+ (match (string_drop _s3000_ _s3001_) with
+ | _s3002_ =>
+ (sep_matches_prefix _s3002_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s3003_ _)) =>
+ match (string_drop _s3002_ _s3003_) with
+ | _s3004_ =>
+ match (hex_bits_6_matches_prefix _s3004_) with
+ | Some ((nzi, existT _ _s3005_ _)) =>
+ match (string_drop _s3004_ _s3005_) with
+ | s_ => Some ((rsd, nzi, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ end)
+ : M (option ((mword 5 * mword 6 * string)))
+ else returnm (None : option ((mword 5 * mword 6 * string))))
+ : M (option ((mword 5 * mword 6 * string))).
+
+Definition _s2979_ (_s2980_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2981_ := _s2980_ in
+ (if ((string_startswith _s2981_ "c.sd")) then
+ (match (string_drop _s2981_ (projT1 (string_length "c.sd"))) with
+ | _s2982_ =>
+ (spc_matches_prefix _s2982_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2983_ _)) =>
+ (match (string_drop _s2982_ _s2983_) with
+ | _s2984_ =>
+ (creg_name_matches_prefix _s2984_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2985_ _)) =>
+ (match (string_drop _s2984_ _s2985_) with
+ | _s2986_ =>
+ (sep_matches_prefix _s2986_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2987_ _)) =>
+ (match (string_drop _s2986_ _s2987_) with
+ | _s2988_ =>
+ (creg_name_matches_prefix _s2988_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2989_ _)) =>
+ (match (string_drop _s2988_ _s2989_) with
+ | _s2990_ =>
+ (sep_matches_prefix _s2990_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2991_ _)) =>
+ match (string_drop _s2990_ _s2991_) with
+ | _s2992_ =>
+ match (hex_bits_8_matches_prefix _s2992_) with
+ | Some ((v__828, existT _ _s2993_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__828 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__828 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__828 7 3 in
+ match (string_drop _s2992_ _s2993_) with
+ | s_ => Some ((rsc1, rsc2, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2963_ (_s2964_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2965_ := _s2964_ in
+ (if ((string_startswith _s2965_ "c.sw")) then
+ (match (string_drop _s2965_ (projT1 (string_length "c.sw"))) with
+ | _s2966_ =>
+ (spc_matches_prefix _s2966_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2967_ _)) =>
+ (match (string_drop _s2966_ _s2967_) with
+ | _s2968_ =>
+ (creg_name_matches_prefix _s2968_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rsc1, existT _ _s2969_ _)) =>
+ (match (string_drop _s2968_ _s2969_) with
+ | _s2970_ =>
+ (sep_matches_prefix _s2970_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2971_ _)) =>
+ (match (string_drop _s2970_ _s2971_) with
+ | _s2972_ =>
+ (creg_name_matches_prefix _s2972_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc2, existT _ _s2973_ _)) =>
+ (match (string_drop _s2972_ _s2973_) with
+ | _s2974_ =>
+ (sep_matches_prefix _s2974_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2975_ _)) =>
+ match (string_drop _s2974_ _s2975_) with
+ | _s2976_ =>
+ match (hex_bits_7_matches_prefix _s2976_) with
+ | Some ((v__830, existT _ _s2977_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__830 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__830 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__830 6 2 in
+ match (string_drop _s2976_ _s2977_) with
+ | s_ => Some ((rsc1, rsc2, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2947_ (_s2948_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2949_ := _s2948_ in
+ (if ((string_startswith _s2949_ "c.ld")) then
+ (match (string_drop _s2949_ (projT1 (string_length "c.ld"))) with
+ | _s2950_ =>
+ (spc_matches_prefix _s2950_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2951_ _)) =>
+ (match (string_drop _s2950_ _s2951_) with
+ | _s2952_ =>
+ (creg_name_matches_prefix _s2952_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2953_ _)) =>
+ (match (string_drop _s2952_ _s2953_) with
+ | _s2954_ =>
+ (sep_matches_prefix _s2954_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2955_ _)) =>
+ (match (string_drop _s2954_ _s2955_) with
+ | _s2956_ =>
+ (creg_name_matches_prefix _s2956_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2957_ _)) =>
+ (match (string_drop _s2956_ _s2957_) with
+ | _s2958_ =>
+ (sep_matches_prefix _s2958_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2959_ _)) =>
+ match (string_drop _s2958_ _s2959_) with
+ | _s2960_ =>
+ match (hex_bits_8_matches_prefix _s2960_) with
+ | Some ((v__832, existT _ _s2961_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__832 2 0)
+ (vec_of_bits [B0;B0;B0]
+ : mword (2 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__832 7 3 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__832 7 3 in
+ match (string_drop _s2960_ _s2961_) with
+ | s_ => Some ((rdc, rsc, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2931_ (_s2932_ : string)
+: M (option ((mword 3 * mword 3 * mword 5 * string))) :=
+
+ let _s2933_ := _s2932_ in
+ (if ((string_startswith _s2933_ "c.lw")) then
+ (match (string_drop _s2933_ (projT1 (string_length "c.lw"))) with
+ | _s2934_ =>
+ (spc_matches_prefix _s2934_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2935_ _)) =>
+ (match (string_drop _s2934_ _s2935_) with
+ | _s2936_ =>
+ (creg_name_matches_prefix _s2936_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2937_ _)) =>
+ (match (string_drop _s2936_ _s2937_) with
+ | _s2938_ =>
+ (sep_matches_prefix _s2938_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2939_ _)) =>
+ (match (string_drop _s2938_ _s2939_) with
+ | _s2940_ =>
+ (creg_name_matches_prefix _s2940_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rsc, existT _ _s2941_ _)) =>
+ (match (string_drop _s2940_ _s2941_) with
+ | _s2942_ =>
+ (sep_matches_prefix _s2942_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2943_ _)) =>
+ match (string_drop _s2942_ _s2943_) with
+ | _s2944_ =>
+ match (hex_bits_7_matches_prefix _s2944_) with
+ | Some ((v__834, existT _ _s2945_ _)) =>
+ if ((eq_vec
+ (subrange_vec_dec v__834 1 0)
+ (vec_of_bits [B0;B0]
+ : mword (1 - 0 + 1)))) then
+ let uimm : mword 5 :=
+ subrange_vec_dec v__834 6 2 in
+ let uimm : mword 5 :=
+ subrange_vec_dec v__834 6 2 in
+ match (string_drop _s2944_ _s2945_) with
+ | s_ => Some ((rdc, rsc, uimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ end)
+ : M (option ((mword 3 * mword 3 * mword 5 * string)))
+ else returnm (None : option ((mword 3 * mword 3 * mword 5 * string))))
+ : M (option ((mword 3 * mword 3 * mword 5 * string))).
+
+Definition _s2919_ (_s2920_ : string)
+: M (option ((mword 3 * mword 8 * string))) :=
+
+ let _s2921_ := _s2920_ in
+ (if ((string_startswith _s2921_ "c.addi4spn")) then
+ (match (string_drop _s2921_ (projT1 (string_length "c.addi4spn"))) with
+ | _s2922_ =>
+ (spc_matches_prefix _s2922_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2923_ _)) =>
+ (match (string_drop _s2922_ _s2923_) with
+ | _s2924_ =>
+ (creg_name_matches_prefix _s2924_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rdc, existT _ _s2925_ _)) =>
+ (match (string_drop _s2924_ _s2925_) with
+ | _s2926_ =>
+ (sep_matches_prefix _s2926_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2927_ _)) =>
+ match (string_drop _s2926_ _s2927_) with
+ | _s2928_ =>
+ match (hex_bits_10_matches_prefix _s2928_) with
+ | Some ((v__836, existT _ _s2929_ _)) =>
+ if ((eq_vec (subrange_vec_dec v__836 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))
+ then
+ let nzimm : mword 8 := subrange_vec_dec v__836 9 2 in
+ let nzimm : mword 8 := subrange_vec_dec v__836 9 2 in
+ match (string_drop _s2928_ _s2929_) with
+ | s_ => Some ((rdc, nzimm, s_))
+ end
+ else None
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ | _ => returnm (None : option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ end)
+ : M (option ((mword 3 * mword 8 * string)))
+ else returnm (None : option ((mword 3 * mword 8 * string))))
+ : M (option ((mword 3 * mword 8 * string))).
+
+Definition _s2915_ (_s2916_ : string)
+: option string :=
+
+ let _s2917_ := _s2916_ in
+ if ((string_startswith _s2917_ "c.nop")) then
+ match (string_drop _s2917_ (projT1 (string_length "c.nop"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2891_ (_s2892_ : string)
+: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2892_ with
+ | _s2893_ =>
+ (amo_mnemonic_matches_prefix _s2893_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2894_ _)) =>
+ let _s2895_ := string_drop _s2893_ _s2894_ in
+ (if ((string_startswith _s2895_ ".")) then
+ (match (string_drop _s2895_ (projT1 (string_length "."))) with
+ | _s2896_ =>
+ (size_mnemonic_matches_prefix _s2896_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((width, existT _ _s2897_ _)) =>
+ (match (string_drop _s2896_ _s2897_) with
+ | _s2898_ =>
+ (maybe_aq_matches_prefix _s2898_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2899_ _)) =>
+ (match (string_drop _s2898_ _s2899_) with
+ | _s2900_ =>
+ (maybe_rl_matches_prefix _s2900_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2901_ _)) =>
+ (match (string_drop _s2900_ _s2901_) with
+ | _s2902_ =>
+ (spc_matches_prefix _s2902_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2903_ _)) =>
+ (match (string_drop _s2902_ _s2903_) with
+ | _s2904_ =>
+ (reg_name_matches_prefix _s2904_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2905_ _)) =>
+ (match (string_drop _s2904_ _s2905_) with
+ | _s2906_ =>
+ (sep_matches_prefix _s2906_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2907_ _)) =>
+ (match (string_drop _s2906_ _s2907_) with
+ | _s2908_ =>
+ (reg_name_matches_prefix _s2908_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((rs1, existT _ _s2909_ _)) =>
+ (match (string_drop _s2908_
+ _s2909_) with
+ | _s2910_ =>
+ (sep_matches_prefix
+ _s2910_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2911_ _)) =>
+ (match (string_drop
+ _s2910_
+ _s2911_) with
+ | _s2912_ =>
+ (reg_name_matches_prefix
+ _s2912_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((rs2, existT _ _s2913_ _)) =>
+ match (string_drop
+ _s2912_
+ _s2913_) with
+ | s_ =>
+ Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_))
+ end
+ | _ =>
+ None
+ end)
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2869_ (_s2870_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) :=
+
+ let _s2871_ := _s2870_ in
+ (if ((string_startswith _s2871_ "sc.")) then
+ (match (string_drop _s2871_ (projT1 (string_length "sc."))) with
+ | _s2872_ =>
+ (size_mnemonic_matches_prefix _s2872_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2873_ _)) =>
+ (match (string_drop _s2872_ _s2873_) with
+ | _s2874_ =>
+ (maybe_aq_matches_prefix _s2874_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2875_ _)) =>
+ (match (string_drop _s2874_ _s2875_) with
+ | _s2876_ =>
+ (maybe_rl_matches_prefix _s2876_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2877_ _)) =>
+ (match (string_drop _s2876_ _s2877_) with
+ | _s2878_ =>
+ (spc_matches_prefix _s2878_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2879_ _)) =>
+ (match (string_drop _s2878_ _s2879_) with
+ | _s2880_ =>
+ (reg_name_matches_prefix _s2880_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s2881_ _)) =>
+ (match (string_drop _s2880_ _s2881_) with
+ | _s2882_ =>
+ (sep_matches_prefix _s2882_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2883_ _)) =>
+ (match (string_drop _s2882_ _s2883_) with
+ | _s2884_ =>
+ (reg_name_matches_prefix _s2884_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((rs1, existT _ _s2885_ _)) =>
+ (match (string_drop _s2884_ _s2885_) with
+ | _s2886_ =>
+ (sep_matches_prefix _s2886_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some ((tt, existT _ _s2887_ _)) =>
+ (match (string_drop _s2886_
+ _s2887_) with
+ | _s2888_ =>
+ (reg_name_matches_prefix
+ _s2888_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__8 with
+ | Some
+ ((rs2, existT _ _s2889_ _)) =>
+ match (string_drop
+ _s2888_
+ _s2889_) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2851_ (_s2852_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) :=
+
+ let _s2853_ := _s2852_ in
+ (if ((string_startswith _s2853_ "lr.")) then
+ (match (string_drop _s2853_ (projT1 (string_length "lr."))) with
+ | _s2854_ =>
+ (size_mnemonic_matches_prefix _s2854_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2855_ _)) =>
+ (match (string_drop _s2854_ _s2855_) with
+ | _s2856_ =>
+ (maybe_aq_matches_prefix _s2856_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2857_ _)) =>
+ (match (string_drop _s2856_ _s2857_) with
+ | _s2858_ =>
+ (maybe_rl_matches_prefix _s2858_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2859_ _)) =>
+ (match (string_drop _s2858_ _s2859_) with
+ | _s2860_ =>
+ (spc_matches_prefix _s2860_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2861_ _)) =>
+ (match (string_drop _s2860_ _s2861_) with
+ | _s2862_ =>
+ (reg_name_matches_prefix _s2862_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rd, existT _ _s2863_ _)) =>
+ (match (string_drop _s2862_ _s2863_) with
+ | _s2864_ =>
+ (sep_matches_prefix _s2864_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2865_ _)) =>
+ (match (string_drop _s2864_ _s2865_) with
+ | _s2866_ =>
+ (reg_name_matches_prefix _s2866_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some
+ ((rs1, existT _ _s2867_ _)) =>
+ match (string_drop _s2866_
+ _s2867_) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rd, rs1, s_))
+ end
+ | _ => None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string)))
+ else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))).
+
+Definition _s2839_ (_s2840_ : string)
+: M (option ((mword 5 * mword 5 * string))) :=
+
+ let _s2841_ := _s2840_ in
+ (if ((string_startswith _s2841_ "sfence.vma")) then
+ (match (string_drop _s2841_ (projT1 (string_length "sfence.vma"))) with
+ | _s2842_ =>
+ (spc_matches_prefix _s2842_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2843_ _)) =>
+ (match (string_drop _s2842_ _s2843_) with
+ | _s2844_ =>
+ (reg_name_matches_prefix _s2844_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rs1, existT _ _s2845_ _)) =>
+ (match (string_drop _s2844_ _s2845_) with
+ | _s2846_ =>
+ (sep_matches_prefix _s2846_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2847_ _)) =>
+ (match (string_drop _s2846_ _s2847_) with
+ | _s2848_ =>
+ (reg_name_matches_prefix _s2848_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((rs2, existT _ _s2849_ _)) =>
+ match (string_drop _s2848_ _s2849_) with
+ | s_ => Some ((rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * string))))
+ : M (option ((mword 5 * mword 5 * string))).
+
+Definition _s2835_ (_s2836_ : string)
+: option string :=
+
+ let _s2837_ := _s2836_ in
+ if ((string_startswith _s2837_ "wfi")) then
+ match (string_drop _s2837_ (projT1 (string_length "wfi"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2831_ (_s2832_ : string)
+: option string :=
+
+ let _s2833_ := _s2832_ in
+ if ((string_startswith _s2833_ "ebreak")) then
+ match (string_drop _s2833_ (projT1 (string_length "ebreak"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2827_ (_s2828_ : string)
+: option string :=
+
+ let _s2829_ := _s2828_ in
+ if ((string_startswith _s2829_ "sret")) then
+ match (string_drop _s2829_ (projT1 (string_length "sret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2823_ (_s2824_ : string)
+: option string :=
+
+ let _s2825_ := _s2824_ in
+ if ((string_startswith _s2825_ "mret")) then
+ match (string_drop _s2825_ (projT1 (string_length "mret"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2819_ (_s2820_ : string)
+: option string :=
+
+ let _s2821_ := _s2820_ in
+ if ((string_startswith _s2821_ "ecall")) then
+ match (string_drop _s2821_ (projT1 (string_length "ecall"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2815_ (_s2816_ : string)
+: option string :=
+
+ let _s2817_ := _s2816_ in
+ if ((string_startswith _s2817_ "fence.i")) then
+ match (string_drop _s2817_ (projT1 (string_length "fence.i"))) with | s_ => Some (s_) end
+ else None.
+
+Definition _s2803_ (_s2804_ : string)
+: M (option ((mword 4 * mword 4 * string))) :=
+
+ let _s2805_ := _s2804_ in
+ (if ((string_startswith _s2805_ "fence.tso")) then
+ (match (string_drop _s2805_ (projT1 (string_length "fence.tso"))) with
+ | _s2806_ =>
+ (spc_matches_prefix _s2806_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2807_ _)) =>
+ (match (string_drop _s2806_ _s2807_) with
+ | _s2808_ =>
+ (fence_bits_matches_prefix _s2808_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s2809_ _)) =>
+ (match (string_drop _s2808_ _s2809_) with
+ | _s2810_ =>
+ (sep_matches_prefix _s2810_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2811_ _)) =>
+ (match (string_drop _s2810_ _s2811_) with
+ | _s2812_ =>
+ (fence_bits_matches_prefix _s2812_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s2813_ _)) =>
+ match (string_drop _s2812_ _s2813_) with
+ | s_ => Some ((pred, succ, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ else returnm (None : option ((mword 4 * mword 4 * string))))
+ : M (option ((mword 4 * mword 4 * string))).
+
+Definition _s2791_ (_s2792_ : string)
+: M (option ((mword 4 * mword 4 * string))) :=
+
+ let _s2793_ := _s2792_ in
+ (if ((string_startswith _s2793_ "fence")) then
+ (match (string_drop _s2793_ (projT1 (string_length "fence"))) with
+ | _s2794_ =>
+ (spc_matches_prefix _s2794_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2795_ _)) =>
+ (match (string_drop _s2794_ _s2795_) with
+ | _s2796_ =>
+ (fence_bits_matches_prefix _s2796_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((pred, existT _ _s2797_ _)) =>
+ (match (string_drop _s2796_ _s2797_) with
+ | _s2798_ =>
+ (sep_matches_prefix _s2798_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2799_ _)) =>
+ (match (string_drop _s2798_ _s2799_) with
+ | _s2800_ =>
+ (fence_bits_matches_prefix _s2800_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((succ, existT _ _s2801_ _)) =>
+ match (string_drop _s2800_ _s2801_) with
+ | s_ => Some ((pred, succ, s_))
+ end
+ | _ => None
+ end)
+ : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ | _ => returnm (None : option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ end)
+ : M (option ((mword 4 * mword 4 * string)))
+ else returnm (None : option ((mword 4 * mword 4 * string))))
+ : M (option ((mword 4 * mword 4 * string))).
+
+Definition _s2774_ (_s2775_ : string)
+: M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2775_ with
+ | _s2776_ =>
+ (shiftiwop_mnemonic_matches_prefix _s2776_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2777_ _)) =>
+ (match (string_drop _s2776_ _s2777_) with
+ | _s2778_ =>
+ (spc_matches_prefix _s2778_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2779_ _)) =>
+ (match (string_drop _s2778_ _s2779_) with
+ | _s2780_ =>
+ (reg_name_matches_prefix _s2780_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2781_ _)) =>
+ (match (string_drop _s2780_ _s2781_) with
+ | _s2782_ =>
+ (sep_matches_prefix _s2782_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2783_ _)) =>
+ (match (string_drop _s2782_ _s2783_) with
+ | _s2784_ =>
+ (reg_name_matches_prefix _s2784_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2785_ _)) =>
+ (match (string_drop _s2784_ _s2785_) with
+ | _s2786_ =>
+ (sep_matches_prefix _s2786_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2787_ _)) =>
+ match (string_drop _s2786_ _s2787_) with
+ | _s2788_ =>
+ match (hex_bits_5_matches_prefix
+ _s2788_) with
+ | Some ((shamt, existT _ _s2789_ _)) =>
+ match (string_drop _s2788_ _s2789_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2757_ (_s2758_ : string)
+: M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2758_ with
+ | _s2759_ =>
+ (rtypew_mnemonic_matches_prefix _s2759_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2760_ _)) =>
+ (match (string_drop _s2759_ _s2760_) with
+ | _s2761_ =>
+ (spc_matches_prefix _s2761_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2762_ _)) =>
+ (match (string_drop _s2761_ _s2762_) with
+ | _s2763_ =>
+ (reg_name_matches_prefix _s2763_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2764_ _)) =>
+ (match (string_drop _s2763_ _s2764_) with
+ | _s2765_ =>
+ (sep_matches_prefix _s2765_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2766_ _)) =>
+ (match (string_drop _s2765_ _s2766_) with
+ | _s2767_ =>
+ (reg_name_matches_prefix _s2767_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2768_ _)) =>
+ (match (string_drop _s2767_ _s2768_) with
+ | _s2769_ =>
+ (sep_matches_prefix _s2769_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2770_ _)) =>
+ (match (string_drop _s2769_ _s2770_) with
+ | _s2771_ =>
+ (reg_name_matches_prefix _s2771_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2772_ _)) =>
+ match (string_drop _s2771_
+ _s2772_) with
+ | s_ =>
+ Some ((op, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2740_ (_s2741_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2741_ with
+ | _s2742_ =>
+ (shiftw_mnemonic_matches_prefix _s2742_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2743_ _)) =>
+ (match (string_drop _s2742_ _s2743_) with
+ | _s2744_ =>
+ (spc_matches_prefix _s2744_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2745_ _)) =>
+ (match (string_drop _s2744_ _s2745_) with
+ | _s2746_ =>
+ (reg_name_matches_prefix _s2746_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2747_ _)) =>
+ (match (string_drop _s2746_ _s2747_) with
+ | _s2748_ =>
+ (sep_matches_prefix _s2748_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2749_ _)) =>
+ (match (string_drop _s2748_ _s2749_) with
+ | _s2750_ =>
+ (reg_name_matches_prefix _s2750_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2751_ _)) =>
+ (match (string_drop _s2750_ _s2751_) with
+ | _s2752_ =>
+ (sep_matches_prefix _s2752_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2753_ _)) =>
+ match (string_drop _s2752_ _s2753_) with
+ | _s2754_ =>
+ match (hex_bits_5_matches_prefix
+ _s2754_) with
+ | Some ((shamt, existT _ _s2755_ _)) =>
+ match (string_drop _s2754_ _s2755_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2724_ (_s2725_ : string)
+: M (option ((mword 5 * mword 5 * mword 12 * string))) :=
+
+ let _s2726_ := _s2725_ in
+ (if ((string_startswith _s2726_ "addiw")) then
+ (match (string_drop _s2726_ (projT1 (string_length "addiw"))) with
+ | _s2727_ =>
+ (spc_matches_prefix _s2727_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2728_ _)) =>
+ (match (string_drop _s2727_ _s2728_) with
+ | _s2729_ =>
+ (reg_name_matches_prefix _s2729_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2730_ _)) =>
+ (match (string_drop _s2729_ _s2730_) with
+ | _s2731_ =>
+ (sep_matches_prefix _s2731_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2732_ _)) =>
+ (match (string_drop _s2731_ _s2732_) with
+ | _s2733_ =>
+ (reg_name_matches_prefix _s2733_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2734_ _)) =>
+ (match (string_drop _s2733_ _s2734_) with
+ | _s2735_ =>
+ (sep_matches_prefix _s2735_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2736_ _)) =>
+ match (string_drop _s2735_ _s2736_) with
+ | _s2737_ =>
+ match (hex_bits_12_matches_prefix _s2737_) with
+ | Some ((imm, existT _ _s2738_ _)) =>
+ match (string_drop _s2737_ _s2738_) with
+ | s_ => Some ((rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2696_ (_s2697_ : string)
+: M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))) :=
+
+ let _s2698_ := _s2697_ in
+ (if ((string_startswith _s2698_ "s")) then
+ (match (string_drop _s2698_ (projT1 (string_length "s"))) with
+ | _s2699_ =>
+ (size_mnemonic_matches_prefix _s2699_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2700_ _)) =>
+ (match (string_drop _s2699_ _s2700_) with
+ | _s2701_ =>
+ (maybe_aq_matches_prefix _s2701_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((aq, existT _ _s2702_ _)) =>
+ (match (string_drop _s2701_ _s2702_) with
+ | _s2703_ =>
+ (maybe_rl_matches_prefix _s2703_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rl, existT _ _s2704_ _)) =>
+ (match (string_drop _s2703_ _s2704_) with
+ | _s2705_ =>
+ (spc_matches_prefix _s2705_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2706_ _)) =>
+ (match (string_drop _s2705_ _s2706_) with
+ | _s2707_ =>
+ (reg_name_matches_prefix _s2707_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s2708_ _)) =>
+ (match (string_drop _s2707_ _s2708_) with
+ | _s2709_ =>
+ (sep_matches_prefix _s2709_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2710_ _)) =>
+ (match (string_drop _s2709_ _s2710_) with
+ | _s2711_ =>
+ (match (hex_bits_12_matches_prefix _s2711_) with
+ | Some ((imm, existT _ _s2712_ _)) =>
+ (match (string_drop _s2711_ _s2712_) with
+ | _s2713_ =>
+ (opt_spc_matches_prefix _s2713_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2714_ _)) =>
+ let _s2715_ :=
+ string_drop _s2713_ _s2714_ in
+ (if ((string_startswith
+ _s2715_ "(")) then
+ (match (string_drop _s2715_
+ (projT1
+ (string_length
+ "("))) with
+ | _s2716_ =>
+ (opt_spc_matches_prefix
+ _s2716_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s2717_ _)) =>
+ (match (string_drop
+ _s2716_
+ _s2717_) with
+ | _s2718_ =>
+ (reg_name_matches_prefix
+ _s2718_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((rs1, existT _ _s2719_ _)) =>
+ (match (string_drop
+ _s2718_
+ _s2719_) with
+ | _s2720_ =>
+ (opt_spc_matches_prefix
+ _s2720_) >>= fun w__9 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__9 with
+ | Some
+ ((tt, existT _ _s2721_ _)) =>
+ let _s2722_ :=
+ string_drop
+ _s2720_
+ _s2721_ in
+ if
+ ((string_startswith
+ _s2722_
+ ")"))
+ then
+ match (string_drop
+ _s2722_
+ (projT1
+ (string_length
+ ")"))) with
+ | s_ =>
+ Some
+ ((size, aq, rl, rs2, imm, rs1, s_))
+ end
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string))).
+
+Definition _s2666_ (_s2667_ : string)
+: M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))) :=
+
+ let _s2668_ := _s2667_ in
+ (if ((string_startswith _s2668_ "l")) then
+ (match (string_drop _s2668_ (projT1 (string_length "l"))) with
+ | _s2669_ =>
+ (size_mnemonic_matches_prefix _s2669_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((size, existT _ _s2670_ _)) =>
+ (match (string_drop _s2669_ _s2670_) with
+ | _s2671_ =>
+ (maybe_u_matches_prefix _s2671_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((is_unsigned, existT _ _s2672_ _)) =>
+ (match (string_drop _s2671_ _s2672_) with
+ | _s2673_ =>
+ (maybe_aq_matches_prefix _s2673_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((aq, existT _ _s2674_ _)) =>
+ (match (string_drop _s2673_ _s2674_) with
+ | _s2675_ =>
+ (maybe_rl_matches_prefix _s2675_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rl, existT _ _s2676_ _)) =>
+ (match (string_drop _s2675_ _s2676_) with
+ | _s2677_ =>
+ (spc_matches_prefix _s2677_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((tt, existT _ _s2678_ _)) =>
+ (match (string_drop _s2677_ _s2678_) with
+ | _s2679_ =>
+ (reg_name_matches_prefix _s2679_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((rd, existT _ _s2680_ _)) =>
+ (match (string_drop _s2679_ _s2680_) with
+ | _s2681_ =>
+ (sep_matches_prefix _s2681_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__6 with
+ | Some ((tt, existT _ _s2682_ _)) =>
+ (match (string_drop _s2681_ _s2682_) with
+ | _s2683_ =>
+ (match (hex_bits_12_matches_prefix
+ _s2683_) with
+ | Some
+ ((imm, existT _ _s2684_ _)) =>
+ (match (string_drop _s2683_
+ _s2684_) with
+ | _s2685_ =>
+ (opt_spc_matches_prefix
+ _s2685_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__7 with
+ | Some
+ ((tt, existT _ _s2686_ _)) =>
+ let _s2687_ :=
+ string_drop _s2685_
+ _s2686_ in
+ (if ((string_startswith
+ _s2687_ "("))
+ then
+ (match (string_drop
+ _s2687_
+ (projT1
+ (string_length
+ "("))) with
+ | _s2688_ =>
+ (opt_spc_matches_prefix
+ _s2688_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__8 with
+ | Some
+ ((tt, existT _ _s2689_ _)) =>
+ (match (string_drop
+ _s2688_
+ _s2689_) with
+ | _s2690_ =>
+ (reg_name_matches_prefix
+ _s2690_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__9 with
+ | Some
+ ((rs1, existT _ _s2691_ _)) =>
+ (match (string_drop
+ _s2690_
+ _s2691_) with
+ | _s2692_ =>
+ (opt_spc_matches_prefix
+ _s2692_) >>= fun w__10 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__10 with
+ | Some
+ ((tt, existT _ _s2693_ _)) =>
+ let _s2694_ :=
+ string_drop
+ _s2692_
+ _s2693_ in
+ if
+ ((string_startswith
+ _s2694_
+ ")"))
+ then
+ match (string_drop
+ _s2694_
+ (projT1
+ (string_length
+ ")"))) with
+ | s_ =>
+ Some
+ ((size, is_unsigned, aq, rl, rd, imm, rs1, s_))
+ end
+ else
+ None
+ | _ =>
+ None
+ end)
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ end)
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)))
+ else
+ returnm (None
+ : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))))
+ : M (option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string))).
+
+Definition _s2649_ (_s2650_ : string)
+: M (option ((rop * mword 5 * mword 5 * mword 5 * string))) :=
+
+ (match _s2650_ with
+ | _s2651_ =>
+ (rtype_mnemonic_matches_prefix _s2651_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2652_ _)) =>
+ (match (string_drop _s2651_ _s2652_) with
+ | _s2653_ =>
+ (spc_matches_prefix _s2653_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2654_ _)) =>
+ (match (string_drop _s2653_ _s2654_) with
+ | _s2655_ =>
+ (reg_name_matches_prefix _s2655_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2656_ _)) =>
+ (match (string_drop _s2655_ _s2656_) with
+ | _s2657_ =>
+ (sep_matches_prefix _s2657_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2658_ _)) =>
+ (match (string_drop _s2657_ _s2658_) with
+ | _s2659_ =>
+ (reg_name_matches_prefix _s2659_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2660_ _)) =>
+ (match (string_drop _s2659_ _s2660_) with
+ | _s2661_ =>
+ (sep_matches_prefix _s2661_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__5 with
+ | Some ((tt, existT _ _s2662_ _)) =>
+ (match (string_drop _s2661_ _s2662_) with
+ | _s2663_ =>
+ (reg_name_matches_prefix _s2663_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__6 with
+ | Some ((rs2, existT _ _s2664_ _)) =>
+ match (string_drop _s2663_
+ _s2664_) with
+ | s_ =>
+ Some ((op, rd, rs1, rs2, s_))
+ end
+ | _ => None
+ end)
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None
+ : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ =>
+ returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string)))
+ end)
+ : M (option ((rop * mword 5 * mword 5 * mword 5 * string))).
+
+Definition _s2632_ (_s2633_ : string)
+: M (option ((sop * mword 5 * mword 5 * mword 6 * string))) :=
+
+ (match _s2633_ with
+ | _s2634_ =>
+ (shiftiop_mnemonic_matches_prefix _s2634_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2635_ _)) =>
+ (match (string_drop _s2634_ _s2635_) with
+ | _s2636_ =>
+ (spc_matches_prefix _s2636_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2637_ _)) =>
+ (match (string_drop _s2636_ _s2637_) with
+ | _s2638_ =>
+ (reg_name_matches_prefix _s2638_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2639_ _)) =>
+ (match (string_drop _s2638_ _s2639_) with
+ | _s2640_ =>
+ (sep_matches_prefix _s2640_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2641_ _)) =>
+ (match (string_drop _s2640_ _s2641_) with
+ | _s2642_ =>
+ (reg_name_matches_prefix _s2642_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2643_ _)) =>
+ (match (string_drop _s2642_ _s2643_) with
+ | _s2644_ =>
+ (sep_matches_prefix _s2644_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2645_ _)) =>
+ match (string_drop _s2644_ _s2645_) with
+ | _s2646_ =>
+ match (hex_bits_6_matches_prefix
+ _s2646_) with
+ | Some ((shamt, existT _ _s2647_ _)) =>
+ match (string_drop _s2646_ _s2647_) with
+ | s_ =>
+ Some ((op, rd, rs1, shamt, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None
+ : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ =>
+ returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string)))
+ end)
+ : M (option ((sop * mword 5 * mword 5 * mword 6 * string))).
+
+Definition _s2615_ (_s2616_ : string)
+: M (option ((iop * mword 5 * mword 5 * mword 12 * string))) :=
+
+ (match _s2616_ with
+ | _s2617_ =>
+ (itype_mnemonic_matches_prefix _s2617_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2618_ _)) =>
+ (match (string_drop _s2617_ _s2618_) with
+ | _s2619_ =>
+ (spc_matches_prefix _s2619_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2620_ _)) =>
+ (match (string_drop _s2619_ _s2620_) with
+ | _s2621_ =>
+ (reg_name_matches_prefix _s2621_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2622_ _)) =>
+ (match (string_drop _s2621_ _s2622_) with
+ | _s2623_ =>
+ (sep_matches_prefix _s2623_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2624_ _)) =>
+ (match (string_drop _s2623_ _s2624_) with
+ | _s2625_ =>
+ (reg_name_matches_prefix _s2625_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs1, existT _ _s2626_ _)) =>
+ (match (string_drop _s2625_ _s2626_) with
+ | _s2627_ =>
+ (sep_matches_prefix _s2627_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2628_ _)) =>
+ match (string_drop _s2627_ _s2628_) with
+ | _s2629_ =>
+ match (hex_bits_12_matches_prefix
+ _s2629_) with
+ | Some ((imm, existT _ _s2630_ _)) =>
+ match (string_drop _s2629_ _s2630_) with
+ | s_ =>
+ Some ((op, rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((iop * mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2598_ (_s2599_ : string)
+: M (option ((bop * mword 5 * mword 5 * mword 13 * string))) :=
+
+ (match _s2599_ with
+ | _s2600_ =>
+ (btype_mnemonic_matches_prefix _s2600_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2601_ _)) =>
+ (match (string_drop _s2600_ _s2601_) with
+ | _s2602_ =>
+ (spc_matches_prefix _s2602_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2603_ _)) =>
+ (match (string_drop _s2602_ _s2603_) with
+ | _s2604_ =>
+ (reg_name_matches_prefix _s2604_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rs1, existT _ _s2605_ _)) =>
+ (match (string_drop _s2604_ _s2605_) with
+ | _s2606_ =>
+ (sep_matches_prefix _s2606_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((tt, existT _ _s2607_ _)) =>
+ (match (string_drop _s2606_ _s2607_) with
+ | _s2608_ =>
+ (reg_name_matches_prefix _s2608_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__4 with
+ | Some ((rs2, existT _ _s2609_ _)) =>
+ (match (string_drop _s2608_ _s2609_) with
+ | _s2610_ =>
+ (sep_matches_prefix _s2610_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__5 with
+ | Some ((tt, existT _ _s2611_ _)) =>
+ match (string_drop _s2610_ _s2611_) with
+ | _s2612_ =>
+ match (hex_bits_13_matches_prefix
+ _s2612_) with
+ | Some ((imm, existT _ _s2613_ _)) =>
+ match (string_drop _s2612_ _s2613_) with
+ | s_ =>
+ Some ((op, rs1, rs2, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None
+ : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ =>
+ returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string)))
+ end)
+ : M (option ((bop * mword 5 * mword 5 * mword 13 * string))).
+
+Definition _s2582_ (_s2583_ : string)
+: M (option ((mword 5 * mword 5 * mword 12 * string))) :=
+
+ let _s2584_ := _s2583_ in
+ (if ((string_startswith _s2584_ "jalr")) then
+ (match (string_drop _s2584_ (projT1 (string_length "jalr"))) with
+ | _s2585_ =>
+ (spc_matches_prefix _s2585_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2586_ _)) =>
+ (match (string_drop _s2585_ _s2586_) with
+ | _s2587_ =>
+ (reg_name_matches_prefix _s2587_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2588_ _)) =>
+ (match (string_drop _s2587_ _s2588_) with
+ | _s2589_ =>
+ (sep_matches_prefix _s2589_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((tt, existT _ _s2590_ _)) =>
+ (match (string_drop _s2589_ _s2590_) with
+ | _s2591_ =>
+ (reg_name_matches_prefix _s2591_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__3 with
+ | Some ((rs1, existT _ _s2592_ _)) =>
+ (match (string_drop _s2591_ _s2592_) with
+ | _s2593_ =>
+ (sep_matches_prefix _s2593_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__4 with
+ | Some ((tt, existT _ _s2594_ _)) =>
+ match (string_drop _s2593_ _s2594_) with
+ | _s2595_ =>
+ match (hex_bits_12_matches_prefix _s2595_) with
+ | Some ((imm, existT _ _s2596_ _)) =>
+ match (string_drop _s2595_ _s2596_) with
+ | s_ => Some ((rd, rs1, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ =>
+ returnm (None
+ : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ end)
+ : M (option ((mword 5 * mword 5 * mword 12 * string)))
+ else returnm (None : option ((mword 5 * mword 5 * mword 12 * string))))
+ : M (option ((mword 5 * mword 5 * mword 12 * string))).
+
+Definition _s2570_ (_s2571_ : string)
+: M (option ((mword 5 * mword 21 * string))) :=
+
+ let _s2572_ := _s2571_ in
+ (if ((string_startswith _s2572_ "jal")) then
+ (match (string_drop _s2572_ (projT1 (string_length "jal"))) with
+ | _s2573_ =>
+ (spc_matches_prefix _s2573_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) =>
+ (match w__0 with
+ | Some ((tt, existT _ _s2574_ _)) =>
+ (match (string_drop _s2573_ _s2574_) with
+ | _s2575_ =>
+ (reg_name_matches_prefix _s2575_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((rd, existT _ _s2576_ _)) =>
+ (match (string_drop _s2575_ _s2576_) with
+ | _s2577_ =>
+ (sep_matches_prefix _s2577_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__2 with
+ | Some ((tt, existT _ _s2578_ _)) =>
+ match (string_drop _s2577_ _s2578_) with
+ | _s2579_ =>
+ match (hex_bits_21_matches_prefix _s2579_) with
+ | Some ((imm, existT _ _s2580_ _)) =>
+ match (string_drop _s2579_ _s2580_) with
+ | s_ => Some ((rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ | _ => returnm (None : option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ end)
+ : M (option ((mword 5 * mword 21 * string)))
+ else returnm (None : option ((mword 5 * mword 21 * string))))
+ : M (option ((mword 5 * mword 21 * string))).
+
+Definition _s2557_ (_s2558_ : string)
+: M (option ((uop * mword 5 * mword 20 * string))) :=
+
+ (match _s2558_ with
+ | _s2559_ =>
+ (utype_mnemonic_matches_prefix _s2559_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__0 with
+ | Some ((op, existT _ _s2560_ _)) =>
+ (match (string_drop _s2559_ _s2560_) with
+ | _s2561_ =>
+ (spc_matches_prefix _s2561_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__1 with
+ | Some ((tt, existT _ _s2562_ _)) =>
+ (match (string_drop _s2561_ _s2562_) with
+ | _s2563_ =>
+ (reg_name_matches_prefix _s2563_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >=
+ 0)})) =>
+ (match w__2 with
+ | Some ((rd, existT _ _s2564_ _)) =>
+ (match (string_drop _s2563_ _s2564_) with
+ | _s2565_ =>
+ (sep_matches_prefix _s2565_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >=
+ 0)})) =>
+ returnm ((match w__3 with
+ | Some ((tt, existT _ _s2566_ _)) =>
+ match (string_drop _s2565_ _s2566_) with
+ | _s2567_ =>
+ match (hex_bits_20_matches_prefix _s2567_) with
+ | Some ((imm, existT _ _s2568_ _)) =>
+ match (string_drop _s2567_ _s2568_) with
+ | s_ => Some ((op, rd, imm, s_))
+ end
+ | _ => None
+ end
+ end
+ | _ => None
+ end)
+ : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ | _ => returnm (None : option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string)))
+ end)
+ : M (option ((uop * mword 5 * mword 20 * string))).
+
+Definition assembly_matches_prefix (arg_ : string)
+: M (option ((ast * {n : Z & ArithFact (n >= 0)}))) :=
+
+ let _s2569_ := arg_ in
+ (_s2557_ _s2569_) >>= fun w__0 : option ((uop * mword 5 * mword 20 * string)) =>
+ (if ((match w__0 with | Some ((op, rd, imm, s_)) => true | _ => false end)) then
+ (_s2557_ _s2569_) >>= fun w__1 : option ((uop * mword 5 * mword 20 * string)) =>
+ (match w__1 with
+ | Some ((op, rd, imm, s_)) =>
+ returnm ((Some
+ ((UTYPE
+ ((imm, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2570_ _s2569_) >>= fun w__4 : option ((mword 5 * mword 21 * string)) =>
+ (if ((match w__4 with | Some ((rd, imm, s_)) => true | _ => false end)) then
+ (_s2570_ _s2569_) >>= fun w__5 : option ((mword 5 * mword 21 * string)) =>
+ (match w__5 with
+ | Some ((rd, imm, s_)) =>
+ returnm ((Some
+ ((RISCV_JAL
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2582_ _s2569_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__8 with | Some ((rd, rs1, imm, s_)) => true | _ => false end)) then
+ (_s2582_ _s2569_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__9 with
+ | Some ((rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((RISCV_JALR
+ ((imm, rs1, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2598_ _s2569_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13 * string)) =>
+ (if ((match w__12 with | Some ((op, rs1, rs2, imm, s_)) => true | _ => false end)) then
+ (_s2598_ _s2569_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13 * string)) =>
+ (match w__13 with
+ | Some ((op, rs1, rs2, imm, s_)) =>
+ returnm ((Some
+ ((BTYPE
+ ((imm, rs2, rs1, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_)) (projT1 (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2615_ _s2569_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__16 with | Some ((op, rd, rs1, imm, s_)) => true | _ => false end))
+ then
+ (_s2615_ _s2569_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__17 with
+ | Some ((op, rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((ITYPE
+ ((imm, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2632_ _s2569_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6 * string)) =>
+ (if ((match w__20 with | Some ((op, rd, rs1, shamt, s_)) => true | _ => false end))
+ then
+ (_s2632_ _s2569_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6 * string)) =>
+ (match w__21 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTIOP
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2649_ _s2569_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__24 with | Some ((op, rd, rs1, rs2, s_)) => true | _ => false end))
+ then
+ (_s2649_ _s2569_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__25 with
+ | Some ((op, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((RTYPE
+ ((rs2, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2666_ _s2569_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (if ((match w__28 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1, s_)) => true
+ | _ => false
+ end)) then
+ (_s2666_ _s2569_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (match w__29 with
+ | Some ((size, is_unsigned, aq, rl, rd, imm, rs1, s_)) =>
+ returnm ((Some
+ ((LOAD
+ ((imm, rs1, rd, is_unsigned, size, aq, rl)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2696_ _s2569_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (if ((match w__32 with
+ | Some ((size, aq, rl, rs2, imm, rs1, s_)) => true
+ | _ => false
+ end)) then
+ (_s2696_ _s2569_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 12 * mword 5 * string)) =>
+ (match w__33 with
+ | Some ((size, aq, rl, rs2, imm, rs1, s_)) =>
+ returnm ((Some
+ ((STORE
+ ((imm, rs2, rs1, size, aq, rl)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2724_ _s2569_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (if ((match w__36 with
+ | Some ((rd, rs1, imm, s_)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2724_ _s2569_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__37 with
+ | Some ((rd, rs1, imm, s_)) =>
+ returnm ((Some
+ ((ADDIW
+ ((imm, rs1, rd)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2740_ _s2569_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__40 with
+ | Some ((op, rd, rs1, shamt, s_)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2740_ _s2569_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__41 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTW
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2757_ _s2569_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__44 with
+ | Some ((op, rd, rs1, rs2, s_)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2757_ _s2569_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__45 with
+ | Some ((op, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((RTYPEW
+ ((rs2, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2774_ _s2569_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__48 with
+ | Some ((op, rd, rs1, shamt, s_)) => Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2774_ _s2569_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__49 with
+ | Some ((op, rd, rs1, shamt, s_)) =>
+ returnm ((Some
+ ((SHIFTIWOP
+ ((shamt, rs1, rd, op)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2791_ _s2569_) >>= fun w__52 : option ((mword 4 * mword 4 * string)) =>
+ (if ((match w__52 with
+ | Some ((pred, succ, s_)) => true
+ | _ => false
+ end)) then
+ (_s2791_ _s2569_) >>= fun w__53 : option ((mword 4 * mword 4 * string)) =>
+ (match w__53 with
+ | Some ((pred, succ, s_)) =>
+ returnm ((Some
+ ((FENCE
+ ((pred, succ)), build_ex
+ (projT1
+ (sub_nat (projT1 (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2803_ _s2569_) >>= fun w__56 : option ((mword 4 * mword 4 * string)) =>
+ (if ((match w__56 with
+ | Some ((pred, succ, s_)) => true
+ | _ => false
+ end)) then
+ (_s2803_ _s2569_) >>= fun w__57 : option ((mword 4 * mword 4 * string)) =>
+ (match w__57 with
+ | Some ((pred, succ, s_)) =>
+ returnm ((Some
+ ((FENCE_TSO
+ ((pred, succ)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2815_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2815_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((FENCEI
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2819_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2819_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((ECALL
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2823_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2823_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((MRET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2827_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2827_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((SRET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2831_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2831_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((EBREAK
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else if ((match (_s2835_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2835_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((WFI
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2839_ _s2569_) >>= fun w__72 : option ((mword 5 * mword 5 * string)) =>
+ (if ((match w__72 with
+ | Some ((rs1, rs2, s_)) => true
+ | _ => false
+ end)) then
+ (_s2839_ _s2569_) >>= fun w__73 : option ((mword 5 * mword 5 * string)) =>
+ (match w__73 with
+ | Some ((rs1, rs2, s_)) =>
+ returnm ((Some
+ ((SFENCE_VMA
+ ((rs1, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >= 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)})))
+ else
+ (_s2851_ _s2569_) >>= fun w__76 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) =>
+ (if ((match w__76 with
+ | Some ((size, aq, rl, rd, rs1, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2851_ _s2569_) >>= fun w__77 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) =>
+ (match w__77 with
+ | Some ((size, aq, rl, rd, rs1, s_)) =>
+ returnm ((Some
+ ((LOADRES
+ ((aq, rl, rs1, size, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2869_ _s2569_) >>= fun w__80 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__80 with
+ | Some
+ ((size, aq, rl, rd, rs1, rs2, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2869_ _s2569_) >>= fun w__81 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__81 with
+ | Some ((size, aq, rl, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((STORECON
+ ((aq, rl, rs2, rs1, size, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2891_ _s2569_) >>= fun w__84 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if ((match w__84 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2891_ _s2569_) >>= fun w__85 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__85 with
+ | Some
+ ((op, width, aq, rl, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((AMO
+ ((op, aq, rl, rs2, rs1, width, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if ((match (_s2915_ _s2569_) with
+ | Some (s_) => true
+ | _ => false
+ end)) then
+ (match (_s2915_ _s2569_) with
+ | Some (s_) =>
+ returnm ((Some
+ ((C_NOP
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length arg_))
+ (projT1
+ (string_length s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2919_ _s2569_) >>= fun w__90 : option ((mword 3 * mword 8 * string)) =>
+ (if ((match w__90 with
+ | Some ((rdc, nzimm, s_)) =>
+ neq_vec nzimm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+ : mword 8)
+ | _ => false
+ end)) then
+ (_s2919_ _s2569_) >>= fun w__91 : option ((mword 3 * mword 8 * string)) =>
+ (match w__91 with
+ | Some ((rdc, nzimm, s_)) =>
+ returnm ((Some
+ ((C_ADDI4SPN
+ ((rdc, nzimm)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2931_ _s2569_) >>= fun w__94 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__94 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2931_ _s2569_) >>= fun w__95 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__95 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ returnm ((Some
+ ((C_LW
+ ((uimm, rsc, rdc)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2947_ _s2569_) >>= fun w__98 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__98 with
+ | Some
+ ((rdc, rsc, uimm, s_)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2947_ _s2569_) >>= fun w__99 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__99 with
+ | Some ((rdc, rsc, uimm, s_)) =>
+ returnm ((Some
+ ((C_LD
+ ((uimm, rsc, rdc)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2963_ _s2569_) >>= fun w__102 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__102 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ true
+ | _ => false
+ end)) then
+ (_s2963_ _s2569_) >>= fun w__103 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__103 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SW
+ ((uimm, rsc1, rsc2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2979_ _s2569_) >>= fun w__106 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (if ((match w__106 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ Z.eqb 64 64
+ | _ => false
+ end)) then
+ (_s2979_ _s2569_) >>= fun w__107 : option ((mword 3 * mword 3 * mword 5 * string)) =>
+ (match w__107 with
+ | Some
+ ((rsc1, rsc2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SD
+ ((uimm, rsc1, rsc2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s2995_ _s2569_) >>= fun w__110 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__110 with
+ | Some
+ ((rsd, nzi, s_)) =>
+ andb
+ (neq_vec nzi
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ => false
+ end)) then
+ (_s2995_ _s2569_) >>= fun w__111 : option ((mword 5 * mword 6 * string)) =>
+ (match w__111 with
+ | Some
+ ((rsd, nzi, s_)) =>
+ returnm ((Some
+ ((C_ADDI
+ ((nzi, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3007_ _s2569_) >>= fun w__114 : option ((mword 11 * string)) =>
+ (if ((match w__114 with
+ | Some
+ ((imm, s_)) =>
+ Z.eqb 64 32
+ | _ => false
+ end)) then
+ (_s3007_ _s2569_) >>= fun w__115 : option ((mword 11 * string)) =>
+ (match w__115 with
+ | Some ((imm, s_)) =>
+ returnm ((Some
+ ((C_JAL
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3015_ _s2569_) >>= fun w__118 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__118 with
+ | Some
+ ((rsd, imm, s_)) =>
+ Z.eqb 64
+ 64
+ | _ => false
+ end)) then
+ (_s3015_ _s2569_) >>= fun w__119 : option ((mword 5 * mword 6 * string)) =>
+ (match w__119 with
+ | Some
+ ((rsd, imm, s_)) =>
+ returnm ((Some
+ ((C_ADDIW
+ ((imm, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3027_ _s2569_) >>= fun w__122 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__122 with
+ | Some
+ ((rd, imm, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end)) then
+ (_s3027_
+ _s2569_) >>= fun w__123 : option ((mword 5 * mword 6 * string)) =>
+ (match w__123 with
+ | Some
+ ((rd, imm, s_)) =>
+ returnm ((Some
+ ((C_LI
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3039_
+ _s2569_) >>= fun w__126 : option ((mword 6 * string)) =>
+ (if ((match w__126 with
+ | Some
+ ((imm, s_)) =>
+ neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3039_
+ _s2569_) >>= fun w__127 : option ((mword 6 * string)) =>
+ (match w__127 with
+ | Some
+ ((imm, s_)) =>
+ returnm ((Some
+ ((C_ADDI16SP
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3047_
+ _s2569_) >>= fun w__130 : option ((mword 5 * mword 6 * string)) =>
+ (if ((match w__130 with
+ | Some
+ ((rd, imm, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ sp))))
+ (neq_vec
+ imm
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3047_
+ _s2569_) >>= fun w__131 : option ((mword 5 * mword 6 * string)) =>
+ (match w__131 with
+ | Some
+ ((rd, imm, s_)) =>
+ returnm ((Some
+ ((C_LUI
+ ((imm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3059_
+ _s2569_) >>= fun w__134 : option ((mword 3 * mword 6 * string)) =>
+ (if ((match w__134 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3059_
+ _s2569_) >>= fun w__135 : option ((mword 3 * mword 6 * string)) =>
+ (match w__135 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SRLI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3071_
+ _s2569_) >>= fun w__138 : option ((mword 3 * mword 6 * string)) =>
+ (if ((match w__138 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6)
+ | _ =>
+ false
+ end))
+ then
+ (_s3071_
+ _s2569_) >>= fun w__139 : option ((mword 3 * mword 6 * string)) =>
+ (match w__139 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SRAI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3083_
+ _s2569_) >>= fun w__142 : option ((mword 3 * mword 6 * string)) =>
+ (if
+ ((match w__142 with
+ | Some
+ ((rsd, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3083_
+ _s2569_) >>= fun w__143 : option ((mword 3 * mword 6 * string)) =>
+ (match w__143 with
+ | Some
+ ((rsd, imm, s_)) =>
+ returnm ((Some
+ ((C_ANDI
+ ((imm, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3095_
+ _s2569_) >>= fun w__146 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__146 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3095_
+ _s2569_) >>= fun w__147 : option ((mword 3 * mword 3 * string)) =>
+ (match w__147 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_SUB
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3107_
+ _s2569_) >>= fun w__150 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__150 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3107_
+ _s2569_) >>= fun w__151 : option ((mword 3 * mword 3 * string)) =>
+ (match w__151 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_XOR
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3119_
+ _s2569_) >>= fun w__154 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__154 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3119_
+ _s2569_) >>= fun w__155 : option ((mword 3 * mword 3 * string)) =>
+ (match w__155 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_OR
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3131_
+ _s2569_) >>= fun w__158 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__158 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3131_
+ _s2569_) >>= fun w__159 : option ((mword 3 * mword 3 * string)) =>
+ (match w__159 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_AND
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3143_
+ _s2569_) >>= fun w__162 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__162 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3143_
+ _s2569_) >>= fun w__163 : option ((mword 3 * mword 3 * string)) =>
+ (match w__163 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_SUBW
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3155_
+ _s2569_) >>= fun w__166 : option ((mword 3 * mword 3 * string)) =>
+ (if
+ ((match w__166 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3155_
+ _s2569_) >>= fun w__167 : option ((mword 3 * mword 3 * string)) =>
+ (match w__167 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_ADDW
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3167_
+ _s2569_) >>= fun w__170 : option ((mword 11 * string)) =>
+ (if
+ ((match w__170 with
+ | Some
+ ((imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3167_
+ _s2569_) >>= fun w__171 : option ((mword 11 * string)) =>
+ (match w__171 with
+ | Some
+ ((imm, s_)) =>
+ returnm ((Some
+ ((C_J
+ (imm), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3175_
+ _s2569_) >>= fun w__174 : option ((mword 3 * mword 8 * string)) =>
+ (if
+ ((match w__174 with
+ | Some
+ ((rs, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3175_
+ _s2569_) >>= fun w__175 : option ((mword 3 * mword 8 * string)) =>
+ (match w__175 with
+ | Some
+ ((rs, imm, s_)) =>
+ returnm ((Some
+ ((C_BEQZ
+ ((imm, rs)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3187_
+ _s2569_) >>= fun w__178 : option ((mword 3 * mword 8 * string)) =>
+ (if
+ ((match w__178 with
+ | Some
+ ((rs, imm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3187_
+ _s2569_) >>= fun w__179 : option ((mword 3 * mword 8 * string)) =>
+ (match w__179 with
+ | Some
+ ((rs, imm, s_)) =>
+ returnm ((Some
+ ((C_BNEZ
+ ((imm, rs)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3199_
+ _s2569_) >>= fun w__182 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__182 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ andb
+ (neq_vec
+ shamt
+ (vec_of_bits [B0;B0;B0;B0;B0;B0]
+ : mword 6))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3199_
+ _s2569_) >>= fun w__183 : option ((mword 5 * mword 6 * string)) =>
+ (match w__183 with
+ | Some
+ ((rsd, shamt, s_)) =>
+ returnm ((Some
+ ((C_SLLI
+ ((shamt, rsd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3211_
+ _s2569_) >>= fun w__186 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__186 with
+ | Some
+ ((rd, uimm, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3211_
+ _s2569_) >>= fun w__187 : option ((mword 5 * mword 6 * string)) =>
+ (match w__187 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_LWSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3223_
+ _s2569_) >>= fun w__190 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__190 with
+ | Some
+ ((rd, uimm, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ (Z.eqb
+ 64
+ 64)
+ | _ =>
+ false
+ end))
+ then
+ (_s3223_
+ _s2569_) >>= fun w__191 : option ((mword 5 * mword 6 * string)) =>
+ (match w__191 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_LDSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3235_
+ _s2569_) >>= fun w__194 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__194 with
+ | Some
+ ((rd, uimm, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3235_
+ _s2569_) >>= fun w__195 : option ((mword 5 * mword 6 * string)) =>
+ (match w__195 with
+ | Some
+ ((rd, uimm, s_)) =>
+ returnm ((Some
+ ((C_SWSP
+ ((uimm, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3247_
+ _s2569_) >>= fun w__198 : option ((mword 5 * mword 6 * string)) =>
+ (if
+ ((match w__198 with
+ | Some
+ ((rs2, uimm, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3247_
+ _s2569_) >>= fun w__199 : option ((mword 5 * mword 6 * string)) =>
+ (match w__199 with
+ | Some
+ ((rs2, uimm, s_)) =>
+ returnm ((Some
+ ((C_SDSP
+ ((uimm, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3259_
+ _s2569_) >>= fun w__202 : option ((mword 5 * string)) =>
+ (if
+ ((match w__202 with
+ | Some
+ ((rs1, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3259_
+ _s2569_) >>= fun w__203 : option ((mword 5 * string)) =>
+ (match w__203 with
+ | Some
+ ((rs1, s_)) =>
+ returnm ((Some
+ ((C_JR
+ (rs1), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3267_
+ _s2569_) >>= fun w__206 : option ((mword 5 * string)) =>
+ (if
+ ((match w__206 with
+ | Some
+ ((rs1, s_)) =>
+ projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs1))
+ (projT1
+ (regidx_to_regno
+ zreg)))
+ | _ =>
+ false
+ end))
+ then
+ (_s3267_
+ _s2569_) >>= fun w__207 : option ((mword 5 * string)) =>
+ (match w__207 with
+ | Some
+ ((rs1, s_)) =>
+ returnm ((Some
+ ((C_JALR
+ (rs1), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3275_
+ _s2569_) >>= fun w__210 : option ((mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__210 with
+ | Some
+ ((rd, rs2, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3275_
+ _s2569_) >>= fun w__211 : option ((mword 5 * mword 5 * string)) =>
+ (match w__211 with
+ | Some
+ ((rd, rs2, s_)) =>
+ returnm ((Some
+ ((C_MV
+ ((rd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if
+ ((match (_s3287_
+ _s2569_) with
+ | Some
+ (s_) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (match (_s3287_
+ _s2569_) with
+ | Some
+ (s_) =>
+ returnm ((Some
+ ((C_EBREAK
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3291_
+ _s2569_) >>= fun w__216 : option ((mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__216 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ andb
+ (projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rsd))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ ((projT1
+ (neq_int
+ (projT1
+ (regidx_to_regno
+ rs2))
+ (projT1
+ (regidx_to_regno
+ zreg))))
+ : bool)
+ | _ =>
+ false
+ end))
+ then
+ (_s3291_
+ _s2569_) >>= fun w__217 : option ((mword 5 * mword 5 * string)) =>
+ (match w__217 with
+ | Some
+ ((rsd, rs2, s_)) =>
+ returnm ((Some
+ ((C_ADD
+ ((rsd, rs2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3303_
+ _s2569_) >>= fun w__220 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__220 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3303_
+ _s2569_) >>= fun w__221 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__221 with
+ | Some
+ ((high, signed1, signed2, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((MUL
+ ((rs2, rs1, rd, high, signed1, signed2)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3320_
+ _s2569_) >>= fun w__224 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__224 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3320_
+ _s2569_) >>= fun w__225 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__225 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((DIV
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3338_
+ _s2569_) >>= fun w__228 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__228 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3338_
+ _s2569_) >>= fun w__229 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__229 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((REM
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3356_
+ _s2569_) >>= fun w__232 : option ((mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__232 with
+ | Some
+ ((rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3356_
+ _s2569_) >>= fun w__233 : option ((mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__233 with
+ | Some
+ ((rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((MULW
+ ((rs2, rs1, rd)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3372_
+ _s2569_) >>= fun w__236 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__236 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3372_
+ _s2569_) >>= fun w__237 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__237 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((DIVW
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3391_
+ _s2569_) >>= fun w__240 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (if
+ ((match w__240 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ Z.eqb
+ 64
+ 64
+ | _ =>
+ false
+ end))
+ then
+ (_s3391_
+ _s2569_) >>= fun w__241 : option ((bool * mword 5 * mword 5 * mword 5 * string)) =>
+ (match w__241 with
+ | Some
+ ((s, rd, rs1, rs2, s_)) =>
+ returnm ((Some
+ ((REMW
+ ((rs2, rs1, rd, s)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3410_
+ _s2569_) >>= fun w__244 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if
+ ((match w__244 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3410_
+ _s2569_) >>= fun w__245 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__245 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ returnm ((Some
+ ((CSR
+ ((csr, rs1, rd, true, op)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3428_
+ _s2569_) >>= fun w__248 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (if
+ ((match w__248 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3428_
+ _s2569_) >>= fun w__249 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) =>
+ (match w__249 with
+ | Some
+ ((op, rd, rs1, csr, s_)) =>
+ returnm ((Some
+ ((CSR
+ ((csr, rs1, rd, false, op)), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else if
+ ((match (_s3445_
+ _s2569_) with
+ | Some
+ (s_) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (match (_s3445_
+ _s2569_) with
+ | Some
+ (s_) =>
+ returnm ((Some
+ ((URET
+ (tt), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3449_
+ _s2569_) >>= fun w__254 : option ((mword 32 * string)) =>
+ (if
+ ((match w__254 with
+ | Some
+ ((s, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3449_
+ _s2569_) >>= fun w__255 : option ((mword 32 * string)) =>
+ (match w__255 with
+ | Some
+ ((s, s_)) =>
+ returnm ((Some
+ ((ILLEGAL
+ (s), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ (_s3457_
+ _s2569_) >>= fun w__258 : option ((mword 16 * string)) =>
+ (if
+ ((match w__258 with
+ | Some
+ ((s, s_)) =>
+ true
+ | _ =>
+ false
+ end))
+ then
+ (_s3457_
+ _s2569_) >>= fun w__259 : option ((mword 16 * string)) =>
+ (match w__259 with
+ | Some
+ ((s, s_)) =>
+ returnm ((Some
+ ((C_ILLEGAL
+ (s), build_ex
+ (projT1
+ (sub_nat
+ (projT1
+ (string_length
+ arg_))
+ (projT1
+ (string_length
+ s_)))))))
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ | _ =>
+ exit tt
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ end)
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)})))
+ else
+ returnm (None
+ : option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >=
+ 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))))
+ : M (option ((ast * {n : Z & ArithFact (n >= 0)}))).
+
+Definition print_insn (insn : ast) : M (string) := (assembly_forwards insn) : M (string).
+
+Definition decode (bv : mword 32) : M (ast) := (encdec_backwards bv) : M (ast).
+
+Definition decodeCompressed (bv : mword 16) : ast := encdec_compressed_backwards bv.
+
+Definition GPRstr : vec string 32 :=
+vec_of_list_len ["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";"x15";"x14";"x13";"x12";"x11";
+ "x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"].
+Hint Unfold GPRstr : sail.
+Definition CIA_fp := RFull ("CIA").
+Hint Unfold CIA_fp : sail.
+Definition NIA_fp := RFull ("NIA").
+Hint Unfold NIA_fp : sail.
+Definition initial_analysis (instr : ast)
+: M ((list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)) :=
+
+ let iR := [] : regfps in
+ let oR := [] : regfps in
+ let aR := [] : regfps in
+ let ik := (IK_simple (tt)) : instruction_kind in
+ let Nias := [NIAFP_successor (tt)] : niafps in
+ let Dia := (DIAFP_none (tt)) : diafp in
+ (match instr with
+ | EBREAK (tt) => returnm (Nias, aR, iR, ik, oR)
+ | UTYPE ((imm, rd, op)) =>
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | RISCV_JAL ((imm, rd)) =>
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ let offset : bits 64 := EXTS 64 imm in
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : mword 64 =>
+ let Nias : list niafp := [NIAFP_concrete_address (add_vec w__0 offset)] in
+ let ik : instruction_kind := IK_branch (tt) in
+ returnm (Nias, aR, iR, ik, oR)
+ | RISCV_JALR ((imm, rs, rd)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ let offset : bits 64 := EXTS 64 imm in
+ let Nias : list niafp := [NIAFP_indirect_address (tt)] in
+ let ik : instruction_kind := IK_branch (tt) in
+ returnm (Nias, aR, iR, ik, oR)
+ | BTYPE ((imm, rs2, rs1, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let ik := (IK_branch (tt)) : instruction_kind in
+ let offset : bits 64 := EXTS 64 imm in
+ ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : mword 64 =>
+ let Nias : list niafp := [NIAFP_concrete_address (add_vec w__1 offset);NIAFP_successor (tt)] in
+ returnm (Nias, aR, iR, ik, oR)
+ | ITYPE ((imm, rs, rd, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | SHIFTIOP ((imm, rs, rd, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | RTYPE ((rs2, rs1, rd, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ let isWrite : bool :=
+ match op with
+ | CSRRW => true
+ | _ =>
+ if sumbool_of_bool (is_imm) then projT1 (neq_int (projT1 (uint rs1)) 0)
+ else projT1 (neq_int (projT1 (uint rs1)) 0)
+ end in
+ let iR : list regfp := (RFull (csr_name csr)) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((negb is_imm)) then
+ (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR
+ else iR in
+ let oR : list regfp := if sumbool_of_bool (isWrite) then (RFull (csr_name csr)) :: oR else oR in
+ let oR : list regfp := (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | LOAD ((imm, rs, rd, unsign, width, aq, rl)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ let aR := iR : list regfp in
+ (match (aq, rl) with
+ | (false, false) => returnm ((IK_mem_read (Read_plain)) : instruction_kind )
+ | (true, false) => returnm ((IK_mem_read (Read_RISCV_acquire)) : instruction_kind )
+ | (true, true) => returnm ((IK_mem_read (Read_RISCV_strong_acquire)) : instruction_kind )
+ | _ =>
+ (internal_error "LOAD type not implemented in initial_analysis") : M (instruction_kind)
+ end) >>= fun w__3 : instruction_kind =>
+ let ik : instruction_kind := w__3 in
+ returnm (Nias, aR, iR, ik, oR)
+ | STORE ((imm, rs2, rs1, width, aq, rl)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let aR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then aR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: aR in
+ (match (aq, rl) with
+ | (false, false) => returnm ((IK_mem_write (Write_plain)) : instruction_kind )
+ | (false, true) => returnm ((IK_mem_write (Write_RISCV_release)) : instruction_kind )
+ | (true, true) => returnm ((IK_mem_write (Write_RISCV_strong_release)) : instruction_kind )
+ | _ =>
+ (internal_error "STORE type not implemented in initial_analysis") : M (instruction_kind)
+ end) >>= fun w__5 : instruction_kind =>
+ let ik : instruction_kind := w__5 in
+ returnm (Nias, aR, iR, ik, oR)
+ | ADDIW ((imm, rs, rd)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | SHIFTW ((imm, rs, rd, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ returnm (Nias, aR, iR, ik, oR)
+ | FENCE ((pred, succ)) =>
+ (match (pred, succ) with
+ | (v__838, v__839) =>
+ (if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ returnm ((IK_barrier
+ (Barrier_RISCV_rw_rw
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_r_rw
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_r_r
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_rw_w
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_w_w
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_w_rw
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_rw_r
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_r_w
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then
+ returnm ((IK_barrier
+ (Barrier_RISCV_w_r
+ (tt)))
+ : instruction_kind )
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__838 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__839 1 0)
+ (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then
+ returnm ((IK_simple
+ (tt))
+ : instruction_kind )
+ else
+ (internal_error "barrier type not implemented in initial_analysis")
+ : M (instruction_kind))
+ : M (instruction_kind)
+ end) >>= fun w__17 : instruction_kind =>
+ let ik : instruction_kind := w__17 in
+ returnm (Nias, aR, iR, ik, oR)
+ | FENCE_TSO ((pred, succ)) =>
+ (match (pred, succ) with
+ | (v__878, v__879) =>
+ (if ((andb
+ (eq_vec (subrange_vec_dec v__878 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))
+ (eq_vec (subrange_vec_dec v__879 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1)))))
+ then
+ returnm ((IK_barrier
+ (Barrier_RISCV_tso
+ (tt)))
+ : instruction_kind )
+ else
+ (internal_error "barrier type not implemented in initial_analysis")
+ : M (instruction_kind))
+ : M (instruction_kind)
+ end) >>= fun w__20 : instruction_kind =>
+ let ik : instruction_kind := w__20 in
+ returnm (Nias, aR, iR, ik, oR)
+ | FENCEI (tt) =>
+ let ik : instruction_kind := IK_simple (tt) in
+ returnm (Nias, aR, iR, ik, oR)
+ | LOADRES ((aq, rl, rs1, width, rd)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ let aR := iR : list regfp in
+ (match (aq, rl) with
+ | (false, false) => returnm ((IK_mem_read (Read_RISCV_reserved)) : instruction_kind )
+ | (true, false) =>
+ returnm ((IK_mem_read (Read_RISCV_reserved_acquire)) : instruction_kind )
+ | (true, true) =>
+ returnm ((IK_mem_read (Read_RISCV_reserved_strong_acquire)) : instruction_kind )
+ | (false, true) =>
+ (internal_error "LOADRES type not implemented in initial_analysis")
+ : M (instruction_kind)
+ end) >>= fun w__22 : instruction_kind =>
+ let ik : instruction_kind := w__22 in
+ returnm (Nias, aR, iR, ik, oR)
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let aR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then aR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: aR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ (match (aq, rl) with
+ | (false, false) => returnm ((IK_mem_write (Write_RISCV_conditional)) : instruction_kind )
+ | (false, true) =>
+ returnm ((IK_mem_write (Write_RISCV_conditional_release)) : instruction_kind )
+ | (true, true) =>
+ returnm ((IK_mem_write (Write_RISCV_conditional_strong_release)) : instruction_kind )
+ | (true, false) =>
+ (internal_error "STORECON type not implemented in initial_analysis")
+ : M (instruction_kind)
+ end) >>= fun w__24 : instruction_kind =>
+ let ik : instruction_kind := w__24 in
+ returnm (Nias, aR, iR, ik, oR)
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs2)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs2)))) :: iR in
+ let iR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then iR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: iR in
+ let aR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rs1)) 0)) then aR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rs1)))) :: aR in
+ let oR : list regfp :=
+ if sumbool_of_bool ((Z.eqb (projT1 (regidx_to_regno rd)) 0)) then oR
+ else (RFull (vec_access_dec GPRstr (projT1 (regidx_to_regno rd)))) :: oR in
+ let ik : instruction_kind :=
+ match (aq, rl) with
+ | (false, false) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional))
+ | (false, true) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional_release))
+ | (true, false) => IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional))
+ | (true, true) =>
+ IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional_release))
+ end in
+ returnm (Nias, aR, iR, ik, oR)
+ | _ => returnm (Nias, aR, iR, ik, oR)
+ end) >>= fun '((Nias, aR, iR, ik, oR)
+ : (list niafp * list regfp * list regfp * instruction_kind * list regfp)) =>
+ returnm (iR, oR, aR, Nias, Dia, ik).
+
+
+End Content.
diff --git a/prover_snapshots/coq/RV64/riscv_extras.v b/prover_snapshots/coq/RV64/riscv_extras.v
new file mode 100644
index 0000000..84f6761
--- /dev/null
+++ b/prover_snapshots/coq/RV64/riscv_extras.v
@@ -0,0 +1,155 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import String.
+Require Import List.
+Import List.ListNotations.
+
+Axiom real : Type.
+
+Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_rw tt).
+Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_rw tt).
+Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_r tt).
+Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_w tt).
+Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_w tt).
+Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_rw tt).
+Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_r tt).
+Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_w tt).
+Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_r tt).
+Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_tso tt).
+Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_i tt).
+(*
+val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+*)
+Definition MEMea {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addrsize addr size.
+Definition MEMea_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addrsize addr size.
+Definition MEMea_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addrsize addr size.
+Definition MEMea_conditional {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addrsize addr size.
+Definition MEMea_conditional_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addrsize addr size.
+Definition MEMea_conditional_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e
+ := write_mem_ea Write_RISCV_conditional_strong_release addrsize addr size.
+
+(*
+val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+*)
+
+Definition MEMr {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_plain addrsize addr size.
+Definition MEMr_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_acquire addrsize addr size.
+Definition MEMr_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_strong_acquire addrsize addr size.
+Definition MEMr_reserved {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved addrsize addr size.
+Definition MEMr_reserved_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_acquire addrsize addr size.
+Definition MEMr_reserved_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_strong_acquire addrsize addr size.
+
+(*
+val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+*)
+
+Definition MEMw {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_plain addrsize addr size v.
+Definition MEMw_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_release addrsize addr size v.
+Definition MEMw_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_strong_release addrsize addr size v.
+Definition MEMw_conditional {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional addrsize addr size v.
+Definition MEMw_conditional_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_release addrsize addr size v.
+Definition MEMw_conditional_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_strong_release addrsize addr size v.
+
+Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftl v (int_of_mword false n).
+
+Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftr v (int_of_mword false n).
+
+Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a :=
+ arith_shiftr v (int_of_mword false n).
+
+(* Use constants for undefined values for now *)
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) : Z := 0.
+(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*)
+
+Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)).
+
+(*val get_time_ns : unit -> integer*)
+Definition get_time_ns (_:unit) : Z := 0.
+(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*)
+
+Definition eq_bit (x : bitU) (y : bitU) : bool :=
+ match x, y with
+ | B0, B0 => true
+ | B1, B1 => true
+ | BU, BU => true
+ | _,_ => false
+ end.
+
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+apply existT with (x := ZEuclid.modulo m n).
+constructor.
+destruct H.
+assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
+(* Override the more general version *)
+
+Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
+Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
+
+Axiom sys_enable_writable_misa : unit -> bool.
+Axiom sys_enable_rvc : unit -> bool.
+
+(* The constraint solver can do this itself, but a Coq bug puts
+ anonymous_subproof into the term instead of an actual subproof. *)
+Lemma n_leading_spaces_fact {w__0} :
+ w__0 >= 0 -> exists ex17629_ : Z, 1 + w__0 = 1 + ex17629_ /\ 0 <= ex17629_.
+intro.
+exists w__0.
+omega.
+Qed.
+Hint Resolve n_leading_spaces_fact : sail.
diff --git a/prover_snapshots/coq/RV64/riscv_types.v b/prover_snapshots/coq/RV64/riscv_types.v
new file mode 100644
index 0000000..98f6666
--- /dev/null
+++ b/prover_snapshots/coq/RV64/riscv_types.v
@@ -0,0 +1,14318 @@
+(*Generated by Sail from riscv.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Import ListNotations.
+Definition bits (n : Z) : Type := mword n.
+
+Inductive regfp :=
+ | RFull : string -> regfp
+ | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RField : (string * string) -> regfp.
+Arguments regfp : clear implicits.
+
+Definition regfps : Type := list regfp.
+
+Inductive niafp :=
+ | NIAFP_successor : unit -> niafp
+ | NIAFP_concrete_address : bits 64 -> niafp
+ | NIAFP_indirect_address : unit -> niafp.
+Arguments niafp : clear implicits.
+
+Definition niafps : Type := list niafp.
+
+Inductive diafp :=
+ | DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp.
+Arguments diafp : clear implicits.
+
+Inductive a64_barrier_domain := A64_FullShare | A64_InnerShare | A64_OuterShare | A64_NonShare.
+Scheme Equality for a64_barrier_domain.
+Instance Decidable_eq_a64_barrier_domain :
+forall (x y : a64_barrier_domain), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_domain_eq_dec.
+
+Inductive a64_barrier_type := A64_barrier_all | A64_barrier_LD | A64_barrier_ST.
+Scheme Equality for a64_barrier_type.
+Instance Decidable_eq_a64_barrier_type :
+forall (x y : a64_barrier_type), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_type_eq_dec.
+
+Inductive cache_op_kind :=
+ Cache_op_D_IVAC
+ | Cache_op_D_ISW
+ | Cache_op_D_CSW
+ | Cache_op_D_CISW
+ | Cache_op_D_ZVA
+ | Cache_op_D_CVAC
+ | Cache_op_D_CVAU
+ | Cache_op_D_CIVAC
+ | Cache_op_I_IALLUIS
+ | Cache_op_I_IALLU
+ | Cache_op_I_IVAU.
+Scheme Equality for cache_op_kind.
+Instance Decidable_eq_cache_op_kind :
+forall (x y : cache_op_kind), Decidable (x = y) :=
+Decidable_eq_from_dec cache_op_kind_eq_dec.
+
+Definition xlen : Z := 64.
+Hint Unfold xlen : sail.
+
+Definition xlen_bytes : Z := 8.
+Hint Unfold xlen_bytes : sail.
+
+Definition xlenbits : Type := bits 64.
+
+Definition mem_meta : Type := unit.
+
+Definition max_mem_access : Z := 16.
+Hint Unfold max_mem_access : sail.
+
+Definition half : Type := bits 16.
+
+Definition word : Type := bits 32.
+
+Definition regidx : Type := bits 5.
+
+Definition cregidx : Type := bits 3.
+
+Definition csreg : Type := bits 12.
+
+Definition regno (n : Z)`{ArithFact (0 <= n /\ n < 32)} : Type := Z.
+
+Definition opcode : Type := bits 7.
+
+Definition imm12 : Type := bits 12.
+
+Definition imm20 : Type := bits 20.
+
+Definition amo : Type := bits 1.
+
+Inductive Architecture := RV32 | RV64 | RV128.
+Scheme Equality for Architecture.
+Instance Decidable_eq_Architecture :
+forall (x y : Architecture), Decidable (x = y) :=
+Decidable_eq_from_dec Architecture_eq_dec.
+
+Definition arch_xlen : Type := bits 2.
+
+Definition priv_level : Type := bits 2.
+
+Inductive Privilege := User | Supervisor | Machine.
+Scheme Equality for Privilege.
+Instance Decidable_eq_Privilege :
+forall (x y : Privilege), Decidable (x = y) :=
+Decidable_eq_from_dec Privilege_eq_dec.
+
+Inductive amoop := AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU.
+Scheme Equality for amoop.
+Instance Decidable_eq_amoop :
+forall (x y : amoop), Decidable (x = y) :=
+Decidable_eq_from_dec amoop_eq_dec.
+
+Inductive bop := RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU.
+Scheme Equality for bop.
+Instance Decidable_eq_bop :
+forall (x y : bop), Decidable (x = y) :=
+Decidable_eq_from_dec bop_eq_dec.
+
+Inductive csrop := CSRRW | CSRRS | CSRRC.
+Scheme Equality for csrop.
+Instance Decidable_eq_csrop :
+forall (x y : csrop), Decidable (x = y) :=
+Decidable_eq_from_dec csrop_eq_dec.
+
+Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI.
+Scheme Equality for iop.
+Instance Decidable_eq_iop :
+forall (x y : iop), Decidable (x = y) :=
+Decidable_eq_from_dec iop_eq_dec.
+
+Inductive rop :=
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND.
+Scheme Equality for rop.
+Instance Decidable_eq_rop :
+forall (x y : rop), Decidable (x = y) :=
+Decidable_eq_from_dec rop_eq_dec.
+
+Inductive ropw := RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW.
+Scheme Equality for ropw.
+Instance Decidable_eq_ropw :
+forall (x y : ropw), Decidable (x = y) :=
+Decidable_eq_from_dec ropw_eq_dec.
+
+Inductive sop := RISCV_SLLI | RISCV_SRLI | RISCV_SRAI.
+Scheme Equality for sop.
+Instance Decidable_eq_sop :
+forall (x y : sop), Decidable (x = y) :=
+Decidable_eq_from_dec sop_eq_dec.
+
+Inductive sopw := RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW.
+Scheme Equality for sopw.
+Instance Decidable_eq_sopw :
+forall (x y : sopw), Decidable (x = y) :=
+Decidable_eq_from_dec sopw_eq_dec.
+
+Inductive uop := RISCV_LUI | RISCV_AUIPC.
+Scheme Equality for uop.
+Instance Decidable_eq_uop :
+forall (x y : uop), Decidable (x = y) :=
+Decidable_eq_from_dec uop_eq_dec.
+
+Inductive word_width := BYTE | HALF | WORD | DOUBLE.
+Scheme Equality for word_width.
+Instance Decidable_eq_word_width :
+forall (x y : word_width), Decidable (x = y) :=
+Decidable_eq_from_dec word_width_eq_dec.
+
+Inductive ast :=
+ | UTYPE : (bits 20 * regidx * uop) -> ast
+ | RISCV_JAL : (bits 21 * regidx) -> ast
+ | RISCV_JALR : (bits 12 * regidx * regidx) -> ast
+ | BTYPE : (bits 13 * regidx * regidx * bop) -> ast
+ | ITYPE : (bits 12 * regidx * regidx * iop) -> ast
+ | SHIFTIOP : (bits 6 * regidx * regidx * sop) -> ast
+ | RTYPE : (regidx * regidx * regidx * rop) -> ast
+ | LOAD : (bits 12 * regidx * regidx * bool * word_width * bool * bool) -> ast
+ | STORE : (bits 12 * regidx * regidx * word_width * bool * bool) -> ast
+ | ADDIW : (bits 12 * regidx * regidx) -> ast
+ | SHIFTW : (bits 5 * regidx * regidx * sop) -> ast
+ | RTYPEW : (regidx * regidx * regidx * ropw) -> ast
+ | SHIFTIWOP : (bits 5 * regidx * regidx * sopw) -> ast
+ | FENCE : (bits 4 * bits 4) -> ast
+ | FENCE_TSO : (bits 4 * bits 4) -> ast
+ | FENCEI : unit -> ast
+ | ECALL : unit -> ast
+ | MRET : unit -> ast
+ | SRET : unit -> ast
+ | EBREAK : unit -> ast
+ | WFI : unit -> ast
+ | SFENCE_VMA : (regidx * regidx) -> ast
+ | LOADRES : (bool * bool * regidx * word_width * regidx) -> ast
+ | STORECON : (bool * bool * regidx * regidx * word_width * regidx) -> ast
+ | AMO : (amoop * bool * bool * regidx * regidx * word_width * regidx) -> ast
+ | C_NOP : unit -> ast
+ | C_ADDI4SPN : (cregidx * bits 8) -> ast
+ | C_LW : (bits 5 * cregidx * cregidx) -> ast
+ | C_LD : (bits 5 * cregidx * cregidx) -> ast
+ | C_SW : (bits 5 * cregidx * cregidx) -> ast
+ | C_SD : (bits 5 * cregidx * cregidx) -> ast
+ | C_ADDI : (bits 6 * regidx) -> ast
+ | C_JAL : bits 11 -> ast
+ | C_ADDIW : (bits 6 * regidx) -> ast
+ | C_LI : (bits 6 * regidx) -> ast
+ | C_ADDI16SP : bits 6 -> ast
+ | C_LUI : (bits 6 * regidx) -> ast
+ | C_SRLI : (bits 6 * cregidx) -> ast
+ | C_SRAI : (bits 6 * cregidx) -> ast
+ | C_ANDI : (bits 6 * cregidx) -> ast
+ | C_SUB : (cregidx * cregidx) -> ast
+ | C_XOR : (cregidx * cregidx) -> ast
+ | C_OR : (cregidx * cregidx) -> ast
+ | C_AND : (cregidx * cregidx) -> ast
+ | C_SUBW : (cregidx * cregidx) -> ast
+ | C_ADDW : (cregidx * cregidx) -> ast
+ | C_J : bits 11 -> ast
+ | C_BEQZ : (bits 8 * cregidx) -> ast
+ | C_BNEZ : (bits 8 * cregidx) -> ast
+ | C_SLLI : (bits 6 * regidx) -> ast
+ | C_LWSP : (bits 6 * regidx) -> ast
+ | C_LDSP : (bits 6 * regidx) -> ast
+ | C_SWSP : (bits 6 * regidx) -> ast
+ | C_SDSP : (bits 6 * regidx) -> ast
+ | C_JR : regidx -> ast
+ | C_JALR : regidx -> ast
+ | C_MV : (regidx * regidx) -> ast
+ | C_EBREAK : unit -> ast
+ | C_ADD : (regidx * regidx) -> ast
+ | MUL : (regidx * regidx * regidx * bool * bool * bool) -> ast
+ | DIV : (regidx * regidx * regidx * bool) -> ast
+ | REM : (regidx * regidx * regidx * bool) -> ast
+ | MULW : (regidx * regidx * regidx) -> ast
+ | DIVW : (regidx * regidx * regidx * bool) -> ast
+ | REMW : (regidx * regidx * regidx * bool) -> ast
+ | CSR : (bits 12 * regidx * regidx * bool * csrop) -> ast
+ | URET : unit -> ast
+ | ILLEGAL : word -> ast
+ | C_ILLEGAL : half -> ast.
+Arguments ast : clear implicits.
+
+Inductive Retired := RETIRE_SUCCESS | RETIRE_FAIL.
+Scheme Equality for Retired.
+Instance Decidable_eq_Retired :
+forall (x y : Retired), Decidable (x = y) :=
+Decidable_eq_from_dec Retired_eq_dec.
+
+Inductive AccessType := Read | Write | ReadWrite | Execute.
+Scheme Equality for AccessType.
+Instance Decidable_eq_AccessType :
+forall (x y : AccessType), Decidable (x = y) :=
+Decidable_eq_from_dec AccessType_eq_dec.
+
+Definition exc_code : Type := bits 8.
+
+Inductive InterruptType :=
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External.
+Scheme Equality for InterruptType.
+Instance Decidable_eq_InterruptType :
+forall (x y : InterruptType), Decidable (x = y) :=
+Decidable_eq_from_dec InterruptType_eq_dec.
+
+Inductive ExceptionType :=
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI.
+Scheme Equality for ExceptionType.
+Instance Decidable_eq_ExceptionType :
+forall (x y : ExceptionType), Decidable (x = y) :=
+Decidable_eq_from_dec ExceptionType_eq_dec.
+
+Inductive exception :=
+ | Error_not_implemented : string -> exception | Error_internal_error : unit -> exception.
+Arguments exception : clear implicits.
+
+Definition tv_mode : Type := bits 2.
+
+Inductive TrapVectorMode := TV_Direct | TV_Vector | TV_Reserved.
+Scheme Equality for TrapVectorMode.
+Instance Decidable_eq_TrapVectorMode :
+forall (x y : TrapVectorMode), Decidable (x = y) :=
+Decidable_eq_from_dec TrapVectorMode_eq_dec.
+
+Definition ext_status : Type := bits 2.
+
+Inductive ExtStatus := Off | Initial | Clean | Dirty.
+Scheme Equality for ExtStatus.
+Instance Decidable_eq_ExtStatus :
+forall (x y : ExtStatus), Decidable (x = y) :=
+Decidable_eq_from_dec ExtStatus_eq_dec.
+
+Definition satp_mode : Type := bits 4.
+
+Inductive SATPMode := Sbare | Sv32 | Sv39 | Sv48.
+Scheme Equality for SATPMode.
+Instance Decidable_eq_SATPMode :
+forall (x y : SATPMode), Decidable (x = y) :=
+Decidable_eq_from_dec SATPMode_eq_dec.
+
+Definition csrRW : Type := bits 2.
+
+Definition regtype : Type := xlenbits.
+
+Record Misa := { Misa_Misa_chunk_0 : mword 64; }.
+Arguments Misa : clear implicits.
+Notation "{[ r 'with' 'Misa_Misa_chunk_0' := e ]}" := {| Misa_Misa_chunk_0 := e |} (only parsing).
+
+Record SV48_PTE := { SV48_PTE_SV48_PTE_chunk_0 : mword 64; }.
+Arguments SV48_PTE : clear implicits.
+Notation "{[ r 'with' 'SV48_PTE_SV48_PTE_chunk_0' := e ]}" :=
+ {| SV48_PTE_SV48_PTE_chunk_0 := e |} (only parsing).
+
+Record PTE_Bits := { PTE_Bits_PTE_Bits_chunk_0 : mword 8; }.
+Arguments PTE_Bits : clear implicits.
+Notation "{[ r 'with' 'PTE_Bits_PTE_Bits_chunk_0' := e ]}" :=
+ {| PTE_Bits_PTE_Bits_chunk_0 := e |} (only parsing).
+
+Record Pmpcfg_ent := { Pmpcfg_ent_Pmpcfg_ent_chunk_0 : mword 8; }.
+Arguments Pmpcfg_ent : clear implicits.
+Notation "{[ r 'with' 'Pmpcfg_ent_Pmpcfg_ent_chunk_0' := e ]}" :=
+ {| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := e |} (only parsing).
+
+Record Mstatus := { Mstatus_Mstatus_chunk_0 : mword 64; }.
+Arguments Mstatus : clear implicits.
+Notation "{[ r 'with' 'Mstatus_Mstatus_chunk_0' := e ]}" :=
+ {| Mstatus_Mstatus_chunk_0 := e |} (only parsing).
+
+Record Sstatus := { Sstatus_Sstatus_chunk_0 : mword 64; }.
+Arguments Sstatus : clear implicits.
+Notation "{[ r 'with' 'Sstatus_Sstatus_chunk_0' := e ]}" :=
+ {| Sstatus_Sstatus_chunk_0 := e |} (only parsing).
+
+Record Ustatus := { Ustatus_Ustatus_chunk_0 : mword 64; }.
+Arguments Ustatus : clear implicits.
+Notation "{[ r 'with' 'Ustatus_Ustatus_chunk_0' := e ]}" :=
+ {| Ustatus_Ustatus_chunk_0 := e |} (only parsing).
+
+Record Minterrupts := { Minterrupts_Minterrupts_chunk_0 : mword 64; }.
+Arguments Minterrupts : clear implicits.
+Notation "{[ r 'with' 'Minterrupts_Minterrupts_chunk_0' := e ]}" :=
+ {| Minterrupts_Minterrupts_chunk_0 := e |} (only parsing).
+
+Record Sinterrupts := { Sinterrupts_Sinterrupts_chunk_0 : mword 64; }.
+Arguments Sinterrupts : clear implicits.
+Notation "{[ r 'with' 'Sinterrupts_Sinterrupts_chunk_0' := e ]}" :=
+ {| Sinterrupts_Sinterrupts_chunk_0 := e |} (only parsing).
+
+Record Uinterrupts := { Uinterrupts_Uinterrupts_chunk_0 : mword 64; }.
+Arguments Uinterrupts : clear implicits.
+Notation "{[ r 'with' 'Uinterrupts_Uinterrupts_chunk_0' := e ]}" :=
+ {| Uinterrupts_Uinterrupts_chunk_0 := e |} (only parsing).
+
+Record Medeleg := { Medeleg_Medeleg_chunk_0 : mword 64; }.
+Arguments Medeleg : clear implicits.
+Notation "{[ r 'with' 'Medeleg_Medeleg_chunk_0' := e ]}" :=
+ {| Medeleg_Medeleg_chunk_0 := e |} (only parsing).
+
+Record Sedeleg := { Sedeleg_Sedeleg_chunk_0 : mword 64; }.
+Arguments Sedeleg : clear implicits.
+Notation "{[ r 'with' 'Sedeleg_Sedeleg_chunk_0' := e ]}" :=
+ {| Sedeleg_Sedeleg_chunk_0 := e |} (only parsing).
+
+Record Mtvec := { Mtvec_Mtvec_chunk_0 : mword 64; }.
+Arguments Mtvec : clear implicits.
+Notation "{[ r 'with' 'Mtvec_Mtvec_chunk_0' := e ]}" :=
+ {| Mtvec_Mtvec_chunk_0 := e |} (only parsing).
+
+Record Satp32 := { Satp32_Satp32_chunk_0 : mword 32; }.
+Arguments Satp32 : clear implicits.
+Notation "{[ r 'with' 'Satp32_Satp32_chunk_0' := e ]}" :=
+ {| Satp32_Satp32_chunk_0 := e |} (only parsing).
+
+Record Mcause := { Mcause_Mcause_chunk_0 : mword 64; }.
+Arguments Mcause : clear implicits.
+Notation "{[ r 'with' 'Mcause_Mcause_chunk_0' := e ]}" :=
+ {| Mcause_Mcause_chunk_0 := e |} (only parsing).
+
+Record Counteren := { Counteren_Counteren_chunk_0 : mword 32; }.
+Arguments Counteren : clear implicits.
+Notation "{[ r 'with' 'Counteren_Counteren_chunk_0' := e ]}" :=
+ {| Counteren_Counteren_chunk_0 := e |} (only parsing).
+
+Record Satp64 := { Satp64_Satp64_chunk_0 : mword 64; }.
+Arguments Satp64 : clear implicits.
+Notation "{[ r 'with' 'Satp64_Satp64_chunk_0' := e ]}" :=
+ {| Satp64_Satp64_chunk_0 := e |} (only parsing).
+
+Inductive PmpAddrMatchType := OFF | TOR | NA4 | NAPOT.
+Scheme Equality for PmpAddrMatchType.
+Instance Decidable_eq_PmpAddrMatchType :
+forall (x y : PmpAddrMatchType), Decidable (x = y) :=
+Decidable_eq_from_dec PmpAddrMatchType_eq_dec.
+
+Definition pmp_addr_range : Type := option ((xlenbits * xlenbits)).
+
+Inductive pmpAddrMatch := PMP_NoMatch | PMP_PartialMatch | PMP_Match.
+Scheme Equality for pmpAddrMatch.
+Instance Decidable_eq_pmpAddrMatch :
+forall (x y : pmpAddrMatch), Decidable (x = y) :=
+Decidable_eq_from_dec pmpAddrMatch_eq_dec.
+
+Inductive pmpMatch := PMP_Success | PMP_Continue | PMP_Fail.
+Scheme Equality for pmpMatch.
+Instance Decidable_eq_pmpMatch :
+forall (x y : pmpMatch), Decidable (x = y) :=
+Decidable_eq_from_dec pmpMatch_eq_dec.
+
+Inductive Ext_FetchAddr_Check {a : Type} :=
+ | Ext_FetchAddr_OK : xlenbits -> Ext_FetchAddr_Check
+ | Ext_FetchAddr_Error : a -> Ext_FetchAddr_Check.
+Arguments Ext_FetchAddr_Check : clear implicits.
+
+Inductive Ext_ControlAddr_Check {a : Type} :=
+ | Ext_ControlAddr_OK : xlenbits -> Ext_ControlAddr_Check
+ | Ext_ControlAddr_Error : a -> Ext_ControlAddr_Check.
+Arguments Ext_ControlAddr_Check : clear implicits.
+
+Inductive Ext_DataAddr_Check {a : Type} :=
+ | Ext_DataAddr_OK : xlenbits -> Ext_DataAddr_Check | Ext_DataAddr_Error : a -> Ext_DataAddr_Check.
+Arguments Ext_DataAddr_Check : clear implicits.
+
+Definition ext_fetch_addr_error : Type := unit.
+
+Definition ext_control_addr_error : Type := unit.
+
+Definition ext_data_addr_error : Type := unit.
+
+Definition ext_exception : Type := unit.
+
+Record sync_exception :=
+ { sync_exception_trap : ExceptionType;
+ sync_exception_excinfo : option xlenbits;
+ sync_exception_ext : option ext_exception; }.
+Arguments sync_exception : clear implicits.
+Notation "{[ r 'with' 'sync_exception_trap' := e ]}" := {|
+ sync_exception_trap := e;
+ sync_exception_excinfo := sync_exception_excinfo r;
+ sync_exception_ext := sync_exception_ext r
+ |}.
+Notation "{[ r 'with' 'sync_exception_excinfo' := e ]}" := {|
+ sync_exception_excinfo := e;
+ sync_exception_trap := sync_exception_trap r;
+ sync_exception_ext := sync_exception_ext r
+ |}.
+Notation "{[ r 'with' 'sync_exception_ext' := e ]}" := {|
+ sync_exception_ext := e;
+ sync_exception_trap := sync_exception_trap r;
+ sync_exception_excinfo := sync_exception_excinfo r
+ |}.
+
+Inductive interrupt_set :=
+ | Ints_Pending : xlenbits -> interrupt_set
+ | Ints_Delegated : xlenbits -> interrupt_set
+ | Ints_Empty : unit -> interrupt_set.
+Arguments interrupt_set : clear implicits.
+
+Inductive ctl_result :=
+ | CTL_TRAP : sync_exception -> ctl_result
+ | CTL_SRET : unit -> ctl_result
+ | CTL_MRET : unit -> ctl_result
+ | CTL_URET : unit -> ctl_result.
+Arguments ctl_result : clear implicits.
+
+Inductive MemoryOpResult {a : Type} :=
+ | MemValue : a -> MemoryOpResult | MemException : ExceptionType -> MemoryOpResult.
+Arguments MemoryOpResult : clear implicits.
+
+Record htif_cmd := { htif_cmd_htif_cmd_chunk_0 : mword 64; }.
+Arguments htif_cmd : clear implicits.
+Notation "{[ r 'with' 'htif_cmd_htif_cmd_chunk_0' := e ]}" :=
+ {| htif_cmd_htif_cmd_chunk_0 := e |} (only parsing).
+
+Definition pteAttribs : Type := bits 8.
+
+Inductive PTW_Error :=
+ PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update.
+Scheme Equality for PTW_Error.
+Instance Decidable_eq_PTW_Error :
+forall (x y : PTW_Error), Decidable (x = y) :=
+Decidable_eq_from_dec PTW_Error_eq_dec.
+
+Definition vaddr32 : Type := bits 32.
+
+Definition paddr32 : Type := bits 34.
+
+Definition pte32 : Type := bits 32.
+
+Definition asid32 : Type := bits 9.
+
+Record SV32_Vaddr := { SV32_Vaddr_SV32_Vaddr_chunk_0 : mword 32; }.
+Arguments SV32_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV32_Vaddr_SV32_Vaddr_chunk_0' := e ]}" :=
+ {| SV32_Vaddr_SV32_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV48_Vaddr := { SV48_Vaddr_SV48_Vaddr_chunk_0 : mword 48; }.
+Arguments SV48_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV48_Vaddr_SV48_Vaddr_chunk_0' := e ]}" :=
+ {| SV48_Vaddr_SV48_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV48_Paddr := { SV48_Paddr_SV48_Paddr_chunk_0 : mword 56; }.
+Arguments SV48_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV48_Paddr_SV48_Paddr_chunk_0' := e ]}" :=
+ {| SV48_Paddr_SV48_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV32_Paddr := { SV32_Paddr_SV32_Paddr_chunk_0 : mword 34; }.
+Arguments SV32_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV32_Paddr_SV32_Paddr_chunk_0' := e ]}" :=
+ {| SV32_Paddr_SV32_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV32_PTE := { SV32_PTE_SV32_PTE_chunk_0 : mword 32; }.
+Arguments SV32_PTE : clear implicits.
+Notation "{[ r 'with' 'SV32_PTE_SV32_PTE_chunk_0' := e ]}" :=
+ {| SV32_PTE_SV32_PTE_chunk_0 := e |} (only parsing).
+
+Definition paddr64 : Type := bits 56.
+
+Definition pte64 : Type := bits 64.
+
+Definition asid64 : Type := bits 16.
+
+Definition vaddr39 : Type := bits 39.
+
+Record SV39_Vaddr := { SV39_Vaddr_SV39_Vaddr_chunk_0 : mword 39; }.
+Arguments SV39_Vaddr : clear implicits.
+Notation "{[ r 'with' 'SV39_Vaddr_SV39_Vaddr_chunk_0' := e ]}" :=
+ {| SV39_Vaddr_SV39_Vaddr_chunk_0 := e |} (only parsing).
+
+Record SV39_Paddr := { SV39_Paddr_SV39_Paddr_chunk_0 : mword 56; }.
+Arguments SV39_Paddr : clear implicits.
+Notation "{[ r 'with' 'SV39_Paddr_SV39_Paddr_chunk_0' := e ]}" :=
+ {| SV39_Paddr_SV39_Paddr_chunk_0 := e |} (only parsing).
+
+Record SV39_PTE := { SV39_PTE_SV39_PTE_chunk_0 : mword 64; }.
+Arguments SV39_PTE : clear implicits.
+Notation "{[ r 'with' 'SV39_PTE_SV39_PTE_chunk_0' := e ]}" :=
+ {| SV39_PTE_SV39_PTE_chunk_0 := e |} (only parsing).
+
+Definition vaddr48 : Type := bits 48.
+
+Definition pte48 : Type := bits 64.
+
+Inductive PTW_Result {paddr : Type} {pte : Type} :=
+ | PTW_Success : (paddr * pte * paddr * {n : Z & ArithFact (n >= 0)} * bool) -> PTW_Result
+ | PTW_Failure : PTW_Error -> PTW_Result.
+Arguments PTW_Result : clear implicits.
+
+Inductive TR_Result {paddr : Type} {failure : Type} :=
+ | TR_Address : paddr -> TR_Result | TR_Failure : failure -> TR_Result.
+Arguments TR_Result : clear implicits.
+
+Record TLB_Entry {asidlen : Z} {valen : Z} {palen : Z} {ptelen : Z} :=
+ { TLB_Entry_asid : bits asidlen;
+ TLB_Entry_global : bool;
+ TLB_Entry_vAddr : bits valen;
+ TLB_Entry_pAddr : bits palen;
+ TLB_Entry_vMatchMask : bits valen;
+ TLB_Entry_vAddrMask : bits valen;
+ TLB_Entry_pte : bits ptelen;
+ TLB_Entry_pteAddr : bits palen;
+ TLB_Entry_age : bits 64; }.
+Arguments TLB_Entry : clear implicits.
+Notation "{[ r 'with' 'TLB_Entry_asid' := e ]}" := {|
+ TLB_Entry_asid := e;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_global' := e ]}" := {|
+ TLB_Entry_global := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vAddr' := e ]}" := {|
+ TLB_Entry_vAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pAddr' := e ]}" := {|
+ TLB_Entry_pAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vMatchMask' := e ]}" := {|
+ TLB_Entry_vMatchMask := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_vAddrMask' := e ]}" := {|
+ TLB_Entry_vAddrMask := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pte' := e ]}" := {|
+ TLB_Entry_pte := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_pteAddr' := e ]}" := {|
+ TLB_Entry_pteAddr := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_age := TLB_Entry_age r
+ |}.
+Notation "{[ r 'with' 'TLB_Entry_age' := e ]}" := {|
+ TLB_Entry_age := e;
+ TLB_Entry_asid := TLB_Entry_asid r;
+ TLB_Entry_global := TLB_Entry_global r;
+ TLB_Entry_vAddr := TLB_Entry_vAddr r;
+ TLB_Entry_pAddr := TLB_Entry_pAddr r;
+ TLB_Entry_vMatchMask := TLB_Entry_vMatchMask r;
+ TLB_Entry_vAddrMask := TLB_Entry_vAddrMask r;
+ TLB_Entry_pte := TLB_Entry_pte r;
+ TLB_Entry_pteAddr := TLB_Entry_pteAddr r
+ |}.
+
+Definition TLB39_Entry : Type := TLB_Entry 16 39 56 64.
+
+Definition TLB48_Entry : Type := TLB_Entry 16 48 56 64.
+
+Inductive register_value :=
+ | Regval_vector : (Z * bool * list register_value) -> register_value
+ | Regval_list : list register_value -> register_value
+ | Regval_option : option register_value -> register_value
+ | Regval_Counteren : Counteren -> register_value
+ | Regval_Mcause : Mcause -> register_value
+ | Regval_Medeleg : Medeleg -> register_value
+ | Regval_Minterrupts : Minterrupts -> register_value
+ | Regval_Misa : Misa -> register_value
+ | Regval_Mstatus : Mstatus -> register_value
+ | Regval_Mtvec : Mtvec -> register_value
+ | Regval_Pmpcfg_ent : Pmpcfg_ent -> register_value
+ | Regval_Privilege : Privilege -> register_value
+ | Regval_Sedeleg : Sedeleg -> register_value
+ | Regval_Sinterrupts : Sinterrupts -> register_value
+ | Regval_TLB_Entry_16_39_56_64 : TLB_Entry 16 39 56 64 -> register_value
+ | Regval_TLB_Entry_16_48_56_64 : TLB_Entry 16 48 56 64 -> register_value
+ | Regval_bit : bitU -> register_value
+ | Regval_bitvector_32_dec : mword 32 -> register_value
+ | Regval_bitvector_64_dec : mword 64 -> register_value
+ | Regval_bool : bool -> register_value.
+Arguments register_value : clear implicits.
+
+Record regstate :=
+ { satp : mword 64;
+ tlb48 : option (TLB_Entry 16 48 56 64);
+ tlb39 : option (TLB_Entry 16 39 56 64);
+ htif_exit_code : mword 64;
+ htif_done : bool;
+ htif_tohost : mword 64;
+ mtimecmp : mword 64;
+ utval : mword 64;
+ ucause : Mcause;
+ uepc : mword 64;
+ uscratch : mword 64;
+ utvec : Mtvec;
+ pmpaddr15 : mword 64;
+ pmpaddr14 : mword 64;
+ pmpaddr13 : mword 64;
+ pmpaddr12 : mword 64;
+ pmpaddr11 : mword 64;
+ pmpaddr10 : mword 64;
+ pmpaddr9 : mword 64;
+ pmpaddr8 : mword 64;
+ pmpaddr7 : mword 64;
+ pmpaddr6 : mword 64;
+ pmpaddr5 : mword 64;
+ pmpaddr4 : mword 64;
+ pmpaddr3 : mword 64;
+ pmpaddr2 : mword 64;
+ pmpaddr1 : mword 64;
+ pmpaddr0 : mword 64;
+ pmp15cfg : Pmpcfg_ent;
+ pmp14cfg : Pmpcfg_ent;
+ pmp13cfg : Pmpcfg_ent;
+ pmp12cfg : Pmpcfg_ent;
+ pmp11cfg : Pmpcfg_ent;
+ pmp10cfg : Pmpcfg_ent;
+ pmp9cfg : Pmpcfg_ent;
+ pmp8cfg : Pmpcfg_ent;
+ pmp7cfg : Pmpcfg_ent;
+ pmp6cfg : Pmpcfg_ent;
+ pmp5cfg : Pmpcfg_ent;
+ pmp4cfg : Pmpcfg_ent;
+ pmp3cfg : Pmpcfg_ent;
+ pmp2cfg : Pmpcfg_ent;
+ pmp1cfg : Pmpcfg_ent;
+ pmp0cfg : Pmpcfg_ent;
+ tselect : mword 64;
+ stval : mword 64;
+ scause : Mcause;
+ sepc : mword 64;
+ sscratch : mword 64;
+ stvec : Mtvec;
+ sideleg : Sinterrupts;
+ sedeleg : Sedeleg;
+ mhartid : mword 64;
+ marchid : mword 64;
+ mimpid : mword 64;
+ mvendorid : mword 32;
+ minstret_written : bool;
+ minstret : mword 64;
+ mtime : mword 64;
+ mcycle : mword 64;
+ scounteren : Counteren;
+ mcounteren : Counteren;
+ mscratch : mword 64;
+ mtval : mword 64;
+ mepc : mword 64;
+ mcause : Mcause;
+ mtvec : Mtvec;
+ medeleg : Medeleg;
+ mideleg : Minterrupts;
+ mie : Minterrupts;
+ mip : Minterrupts;
+ mstatus : Mstatus;
+ misa : Misa;
+ cur_inst : mword 64;
+ cur_privilege : Privilege;
+ x31 : mword 64;
+ x30 : mword 64;
+ x29 : mword 64;
+ x28 : mword 64;
+ x27 : mword 64;
+ x26 : mword 64;
+ x25 : mword 64;
+ x24 : mword 64;
+ x23 : mword 64;
+ x22 : mword 64;
+ x21 : mword 64;
+ x20 : mword 64;
+ x19 : mword 64;
+ x18 : mword 64;
+ x17 : mword 64;
+ x16 : mword 64;
+ x15 : mword 64;
+ x14 : mword 64;
+ x13 : mword 64;
+ x12 : mword 64;
+ x11 : mword 64;
+ x10 : mword 64;
+ x9 : mword 64;
+ x8 : mword 64;
+ x7 : mword 64;
+ x6 : mword 64;
+ x5 : mword 64;
+ x4 : mword 64;
+ x3 : mword 64;
+ x2 : mword 64;
+ x1 : mword 64;
+ Xs : vec (mword 64) 32;
+ instbits : mword 64;
+ nextPC : mword 64;
+ PC : mword 64; }.
+Arguments regstate : clear implicits.
+Notation "{[ r 'with' 'satp' := e ]}" := {|
+ satp := e;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'tlb48' := e ]}" := {|
+ tlb48 := e;
+ satp := satp r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'tlb39' := e ]}" := {|
+ tlb39 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_exit_code' := e ]}" := {|
+ htif_exit_code := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_done' := e ]}" := {|
+ htif_done := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'htif_tohost' := e ]}" := {|
+ htif_tohost := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtimecmp' := e ]}" := {|
+ mtimecmp := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'utval' := e ]}" := {|
+ utval := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'ucause' := e ]}" := {|
+ ucause := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'uepc' := e ]}" := {|
+ uepc := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'uscratch' := e ]}" := {|
+ uscratch := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'utvec' := e ]}" := {|
+ utvec := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr15' := e ]}" := {|
+ pmpaddr15 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr14' := e ]}" := {|
+ pmpaddr14 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr13' := e ]}" := {|
+ pmpaddr13 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr12' := e ]}" := {|
+ pmpaddr12 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr11' := e ]}" := {|
+ pmpaddr11 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr10' := e ]}" := {|
+ pmpaddr10 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr9' := e ]}" := {|
+ pmpaddr9 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr8' := e ]}" := {|
+ pmpaddr8 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr7' := e ]}" := {|
+ pmpaddr7 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr6' := e ]}" := {|
+ pmpaddr6 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr5' := e ]}" := {|
+ pmpaddr5 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr4' := e ]}" := {|
+ pmpaddr4 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr3' := e ]}" := {|
+ pmpaddr3 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr2' := e ]}" := {|
+ pmpaddr2 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr1' := e ]}" := {|
+ pmpaddr1 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmpaddr0' := e ]}" := {|
+ pmpaddr0 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp15cfg' := e ]}" := {|
+ pmp15cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp14cfg' := e ]}" := {|
+ pmp14cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp13cfg' := e ]}" := {|
+ pmp13cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp12cfg' := e ]}" := {|
+ pmp12cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp11cfg' := e ]}" := {|
+ pmp11cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp10cfg' := e ]}" := {|
+ pmp10cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp9cfg' := e ]}" := {|
+ pmp9cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp8cfg' := e ]}" := {|
+ pmp8cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp7cfg' := e ]}" := {|
+ pmp7cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp6cfg' := e ]}" := {|
+ pmp6cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp5cfg' := e ]}" := {|
+ pmp5cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp4cfg' := e ]}" := {|
+ pmp4cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp3cfg' := e ]}" := {|
+ pmp3cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp2cfg' := e ]}" := {|
+ pmp2cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp1cfg' := e ]}" := {|
+ pmp1cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'pmp0cfg' := e ]}" := {|
+ pmp0cfg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'tselect' := e ]}" := {|
+ tselect := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'stval' := e ]}" := {|
+ stval := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'scause' := e ]}" := {|
+ scause := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sepc' := e ]}" := {|
+ sepc := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sscratch' := e ]}" := {|
+ sscratch := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'stvec' := e ]}" := {|
+ stvec := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sideleg' := e ]}" := {|
+ sideleg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'sedeleg' := e ]}" := {|
+ sedeleg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mhartid' := e ]}" := {|
+ mhartid := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'marchid' := e ]}" := {|
+ marchid := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mimpid' := e ]}" := {|
+ mimpid := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mvendorid' := e ]}" := {|
+ mvendorid := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'minstret_written' := e ]}" := {|
+ minstret_written := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'minstret' := e ]}" := {|
+ minstret := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtime' := e ]}" := {|
+ mtime := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcycle' := e ]}" := {|
+ mcycle := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'scounteren' := e ]}" := {|
+ scounteren := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcounteren' := e ]}" := {|
+ mcounteren := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mscratch' := e ]}" := {|
+ mscratch := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtval' := e ]}" := {|
+ mtval := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mepc' := e ]}" := {|
+ mepc := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mcause' := e ]}" := {|
+ mcause := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mtvec' := e ]}" := {|
+ mtvec := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'medeleg' := e ]}" := {|
+ medeleg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mideleg' := e ]}" := {|
+ mideleg := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mie' := e ]}" := {|
+ mie := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mip' := e ]}" := {|
+ mip := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'mstatus' := e ]}" := {|
+ mstatus := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'misa' := e ]}" := {|
+ misa := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'cur_inst' := e ]}" := {|
+ cur_inst := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'cur_privilege' := e ]}" := {|
+ cur_privilege := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x31' := e ]}" := {|
+ x31 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x30' := e ]}" := {|
+ x30 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x29' := e ]}" := {|
+ x29 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x28' := e ]}" := {|
+ x28 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x27' := e ]}" := {|
+ x27 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x26' := e ]}" := {|
+ x26 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x25' := e ]}" := {|
+ x25 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x24' := e ]}" := {|
+ x24 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x23' := e ]}" := {|
+ x23 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x22' := e ]}" := {|
+ x22 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x21' := e ]}" := {|
+ x21 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x20' := e ]}" := {|
+ x20 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x19' := e ]}" := {|
+ x19 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x18' := e ]}" := {|
+ x18 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x17' := e ]}" := {|
+ x17 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x16' := e ]}" := {|
+ x16 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x15' := e ]}" := {|
+ x15 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x14' := e ]}" := {|
+ x14 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x13' := e ]}" := {|
+ x13 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x12' := e ]}" := {|
+ x12 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x11' := e ]}" := {|
+ x11 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x10' := e ]}" := {|
+ x10 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x9' := e ]}" := {|
+ x9 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x8' := e ]}" := {|
+ x8 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x7' := e ]}" := {|
+ x7 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x6' := e ]}" := {|
+ x6 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x5' := e ]}" := {|
+ x5 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x4' := e ]}" := {|
+ x4 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x3' := e ]}" := {|
+ x3 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x2' := e ]}" := {|
+ x2 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'x1' := e ]}" := {|
+ x1 := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'Xs' := e ]}" := {|
+ Xs := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ instbits := instbits r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'instbits' := e ]}" := {|
+ instbits := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ nextPC := nextPC r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'nextPC' := e ]}" := {|
+ nextPC := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ PC := PC r
+ |}.
+Notation "{[ r 'with' 'PC' := e ]}" := {|
+ PC := e;
+ satp := satp r;
+ tlb48 := tlb48 r;
+ tlb39 := tlb39 r;
+ htif_exit_code := htif_exit_code r;
+ htif_done := htif_done r;
+ htif_tohost := htif_tohost r;
+ mtimecmp := mtimecmp r;
+ utval := utval r;
+ ucause := ucause r;
+ uepc := uepc r;
+ uscratch := uscratch r;
+ utvec := utvec r;
+ pmpaddr15 := pmpaddr15 r;
+ pmpaddr14 := pmpaddr14 r;
+ pmpaddr13 := pmpaddr13 r;
+ pmpaddr12 := pmpaddr12 r;
+ pmpaddr11 := pmpaddr11 r;
+ pmpaddr10 := pmpaddr10 r;
+ pmpaddr9 := pmpaddr9 r;
+ pmpaddr8 := pmpaddr8 r;
+ pmpaddr7 := pmpaddr7 r;
+ pmpaddr6 := pmpaddr6 r;
+ pmpaddr5 := pmpaddr5 r;
+ pmpaddr4 := pmpaddr4 r;
+ pmpaddr3 := pmpaddr3 r;
+ pmpaddr2 := pmpaddr2 r;
+ pmpaddr1 := pmpaddr1 r;
+ pmpaddr0 := pmpaddr0 r;
+ pmp15cfg := pmp15cfg r;
+ pmp14cfg := pmp14cfg r;
+ pmp13cfg := pmp13cfg r;
+ pmp12cfg := pmp12cfg r;
+ pmp11cfg := pmp11cfg r;
+ pmp10cfg := pmp10cfg r;
+ pmp9cfg := pmp9cfg r;
+ pmp8cfg := pmp8cfg r;
+ pmp7cfg := pmp7cfg r;
+ pmp6cfg := pmp6cfg r;
+ pmp5cfg := pmp5cfg r;
+ pmp4cfg := pmp4cfg r;
+ pmp3cfg := pmp3cfg r;
+ pmp2cfg := pmp2cfg r;
+ pmp1cfg := pmp1cfg r;
+ pmp0cfg := pmp0cfg r;
+ tselect := tselect r;
+ stval := stval r;
+ scause := scause r;
+ sepc := sepc r;
+ sscratch := sscratch r;
+ stvec := stvec r;
+ sideleg := sideleg r;
+ sedeleg := sedeleg r;
+ mhartid := mhartid r;
+ marchid := marchid r;
+ mimpid := mimpid r;
+ mvendorid := mvendorid r;
+ minstret_written := minstret_written r;
+ minstret := minstret r;
+ mtime := mtime r;
+ mcycle := mcycle r;
+ scounteren := scounteren r;
+ mcounteren := mcounteren r;
+ mscratch := mscratch r;
+ mtval := mtval r;
+ mepc := mepc r;
+ mcause := mcause r;
+ mtvec := mtvec r;
+ medeleg := medeleg r;
+ mideleg := mideleg r;
+ mie := mie r;
+ mip := mip r;
+ mstatus := mstatus r;
+ misa := misa r;
+ cur_inst := cur_inst r;
+ cur_privilege := cur_privilege r;
+ x31 := x31 r;
+ x30 := x30 r;
+ x29 := x29 r;
+ x28 := x28 r;
+ x27 := x27 r;
+ x26 := x26 r;
+ x25 := x25 r;
+ x24 := x24 r;
+ x23 := x23 r;
+ x22 := x22 r;
+ x21 := x21 r;
+ x20 := x20 r;
+ x19 := x19 r;
+ x18 := x18 r;
+ x17 := x17 r;
+ x16 := x16 r;
+ x15 := x15 r;
+ x14 := x14 r;
+ x13 := x13 r;
+ x12 := x12 r;
+ x11 := x11 r;
+ x10 := x10 r;
+ x9 := x9 r;
+ x8 := x8 r;
+ x7 := x7 r;
+ x6 := x6 r;
+ x5 := x5 r;
+ x4 := x4 r;
+ x3 := x3 r;
+ x2 := x2 r;
+ x1 := x1 r;
+ Xs := Xs r;
+ instbits := instbits r;
+ nextPC := nextPC r
+ |}.
+
+
+
+Definition Counteren_of_regval (merge_var : register_value)
+: option Counteren :=
+
+ match merge_var with | Regval_Counteren (v) => Some (v) | _ => None end.
+
+Definition regval_of_Counteren (v : Counteren) : register_value := Regval_Counteren (v).
+
+Definition Mcause_of_regval (merge_var : register_value)
+: option Mcause :=
+
+ match merge_var with | Regval_Mcause (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mcause (v : Mcause) : register_value := Regval_Mcause (v).
+
+Definition Medeleg_of_regval (merge_var : register_value)
+: option Medeleg :=
+
+ match merge_var with | Regval_Medeleg (v) => Some (v) | _ => None end.
+
+Definition regval_of_Medeleg (v : Medeleg) : register_value := Regval_Medeleg (v).
+
+Definition Minterrupts_of_regval (merge_var : register_value)
+: option Minterrupts :=
+
+ match merge_var with | Regval_Minterrupts (v) => Some (v) | _ => None end.
+
+Definition regval_of_Minterrupts (v : Minterrupts) : register_value := Regval_Minterrupts (v).
+
+Definition Misa_of_regval (merge_var : register_value)
+: option Misa :=
+
+ match merge_var with | Regval_Misa (v) => Some (v) | _ => None end.
+
+Definition regval_of_Misa (v : Misa) : register_value := Regval_Misa (v).
+
+Definition Mstatus_of_regval (merge_var : register_value)
+: option Mstatus :=
+
+ match merge_var with | Regval_Mstatus (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mstatus (v : Mstatus) : register_value := Regval_Mstatus (v).
+
+Definition Mtvec_of_regval (merge_var : register_value)
+: option Mtvec :=
+
+ match merge_var with | Regval_Mtvec (v) => Some (v) | _ => None end.
+
+Definition regval_of_Mtvec (v : Mtvec) : register_value := Regval_Mtvec (v).
+
+Definition Pmpcfg_ent_of_regval (merge_var : register_value)
+: option Pmpcfg_ent :=
+
+ match merge_var with | Regval_Pmpcfg_ent (v) => Some (v) | _ => None end.
+
+Definition regval_of_Pmpcfg_ent (v : Pmpcfg_ent) : register_value := Regval_Pmpcfg_ent (v).
+
+Definition Privilege_of_regval (merge_var : register_value)
+: option Privilege :=
+
+ match merge_var with | Regval_Privilege (v) => Some (v) | _ => None end.
+
+Definition regval_of_Privilege (v : Privilege) : register_value := Regval_Privilege (v).
+
+Definition Sedeleg_of_regval (merge_var : register_value)
+: option Sedeleg :=
+
+ match merge_var with | Regval_Sedeleg (v) => Some (v) | _ => None end.
+
+Definition regval_of_Sedeleg (v : Sedeleg) : register_value := Regval_Sedeleg (v).
+
+Definition Sinterrupts_of_regval (merge_var : register_value)
+: option Sinterrupts :=
+
+ match merge_var with | Regval_Sinterrupts (v) => Some (v) | _ => None end.
+
+Definition regval_of_Sinterrupts (v : Sinterrupts) : register_value := Regval_Sinterrupts (v).
+
+Definition TLB_Entry_16_39_56_64_of_regval (merge_var : register_value)
+: option (TLB_Entry 16 39 56 64) :=
+
+ match merge_var with | Regval_TLB_Entry_16_39_56_64 (v) => Some (v) | _ => None end.
+
+Definition regval_of_TLB_Entry_16_39_56_64 (v : TLB_Entry 16 39 56 64)
+: register_value :=
+
+ Regval_TLB_Entry_16_39_56_64
+ (v).
+
+Definition TLB_Entry_16_48_56_64_of_regval (merge_var : register_value)
+: option (TLB_Entry 16 48 56 64) :=
+
+ match merge_var with | Regval_TLB_Entry_16_48_56_64 (v) => Some (v) | _ => None end.
+
+Definition regval_of_TLB_Entry_16_48_56_64 (v : TLB_Entry 16 48 56 64)
+: register_value :=
+
+ Regval_TLB_Entry_16_48_56_64
+ (v).
+
+Definition bit_of_regval (merge_var : register_value)
+: option bitU :=
+
+ match merge_var with | Regval_bit (v) => Some (v) | _ => None end.
+
+Definition regval_of_bit (v : bitU) : register_value := Regval_bit (v).
+
+Definition bitvector_32_dec_of_regval (merge_var : register_value)
+: option (mword 32) :=
+
+ match merge_var with | Regval_bitvector_32_dec (v) => Some (v) | _ => None end.
+
+Definition regval_of_bitvector_32_dec (v : mword 32)
+: register_value :=
+
+ Regval_bitvector_32_dec
+ (v).
+
+Definition bitvector_64_dec_of_regval (merge_var : register_value)
+: option (mword 64) :=
+
+ match merge_var with | Regval_bitvector_64_dec (v) => Some (v) | _ => None end.
+
+Definition regval_of_bitvector_64_dec (v : mword 64)
+: register_value :=
+
+ Regval_bitvector_64_dec
+ (v).
+
+Definition bool_of_regval (merge_var : register_value)
+: option bool :=
+
+ match merge_var with | Regval_bool (v) => Some (v) | _ => None end.
+
+Definition regval_of_bool (v : bool) : register_value := Regval_bool (v).
+
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with
+ | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None
+ | _ => None
+end.
+
+Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with
+ | Regval_list v => just_list (List.map of_regval v)
+ | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with
+ | Regval_option v => option_map of_regval v
+ | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition satp_ref := {|
+ name := "satp";
+ read_from := (fun s => s.(satp));
+ write_to := (fun v s => ({[ s with satp := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition tlb48_ref := {|
+ name := "tlb48";
+ read_from := (fun s => s.(tlb48));
+ write_to := (fun v s => ({[ s with tlb48 := v ]}));
+ of_regval := (fun v => option_of_regval (fun v => TLB_Entry_16_48_56_64_of_regval v) v);
+ regval_of := (fun v => regval_of_option (fun v => regval_of_TLB_Entry_16_48_56_64 v) v) |}.
+
+Definition tlb39_ref := {|
+ name := "tlb39";
+ read_from := (fun s => s.(tlb39));
+ write_to := (fun v s => ({[ s with tlb39 := v ]}));
+ of_regval := (fun v => option_of_regval (fun v => TLB_Entry_16_39_56_64_of_regval v) v);
+ regval_of := (fun v => regval_of_option (fun v => regval_of_TLB_Entry_16_39_56_64 v) v) |}.
+
+Definition htif_exit_code_ref := {|
+ name := "htif_exit_code";
+ read_from := (fun s => s.(htif_exit_code));
+ write_to := (fun v s => ({[ s with htif_exit_code := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition htif_done_ref := {|
+ name := "htif_done";
+ read_from := (fun s => s.(htif_done));
+ write_to := (fun v s => ({[ s with htif_done := v ]}));
+ of_regval := (fun v => bool_of_regval v);
+ regval_of := (fun v => regval_of_bool v) |}.
+
+Definition htif_tohost_ref := {|
+ name := "htif_tohost";
+ read_from := (fun s => s.(htif_tohost));
+ write_to := (fun v s => ({[ s with htif_tohost := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mtimecmp_ref := {|
+ name := "mtimecmp";
+ read_from := (fun s => s.(mtimecmp));
+ write_to := (fun v s => ({[ s with mtimecmp := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition utval_ref := {|
+ name := "utval";
+ read_from := (fun s => s.(utval));
+ write_to := (fun v s => ({[ s with utval := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition ucause_ref := {|
+ name := "ucause";
+ read_from := (fun s => s.(ucause));
+ write_to := (fun v s => ({[ s with ucause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition uepc_ref := {|
+ name := "uepc";
+ read_from := (fun s => s.(uepc));
+ write_to := (fun v s => ({[ s with uepc := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition uscratch_ref := {|
+ name := "uscratch";
+ read_from := (fun s => s.(uscratch));
+ write_to := (fun v s => ({[ s with uscratch := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition utvec_ref := {|
+ name := "utvec";
+ read_from := (fun s => s.(utvec));
+ write_to := (fun v s => ({[ s with utvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition pmpaddr15_ref := {|
+ name := "pmpaddr15";
+ read_from := (fun s => s.(pmpaddr15));
+ write_to := (fun v s => ({[ s with pmpaddr15 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr14_ref := {|
+ name := "pmpaddr14";
+ read_from := (fun s => s.(pmpaddr14));
+ write_to := (fun v s => ({[ s with pmpaddr14 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr13_ref := {|
+ name := "pmpaddr13";
+ read_from := (fun s => s.(pmpaddr13));
+ write_to := (fun v s => ({[ s with pmpaddr13 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr12_ref := {|
+ name := "pmpaddr12";
+ read_from := (fun s => s.(pmpaddr12));
+ write_to := (fun v s => ({[ s with pmpaddr12 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr11_ref := {|
+ name := "pmpaddr11";
+ read_from := (fun s => s.(pmpaddr11));
+ write_to := (fun v s => ({[ s with pmpaddr11 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr10_ref := {|
+ name := "pmpaddr10";
+ read_from := (fun s => s.(pmpaddr10));
+ write_to := (fun v s => ({[ s with pmpaddr10 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr9_ref := {|
+ name := "pmpaddr9";
+ read_from := (fun s => s.(pmpaddr9));
+ write_to := (fun v s => ({[ s with pmpaddr9 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr8_ref := {|
+ name := "pmpaddr8";
+ read_from := (fun s => s.(pmpaddr8));
+ write_to := (fun v s => ({[ s with pmpaddr8 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr7_ref := {|
+ name := "pmpaddr7";
+ read_from := (fun s => s.(pmpaddr7));
+ write_to := (fun v s => ({[ s with pmpaddr7 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr6_ref := {|
+ name := "pmpaddr6";
+ read_from := (fun s => s.(pmpaddr6));
+ write_to := (fun v s => ({[ s with pmpaddr6 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr5_ref := {|
+ name := "pmpaddr5";
+ read_from := (fun s => s.(pmpaddr5));
+ write_to := (fun v s => ({[ s with pmpaddr5 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr4_ref := {|
+ name := "pmpaddr4";
+ read_from := (fun s => s.(pmpaddr4));
+ write_to := (fun v s => ({[ s with pmpaddr4 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr3_ref := {|
+ name := "pmpaddr3";
+ read_from := (fun s => s.(pmpaddr3));
+ write_to := (fun v s => ({[ s with pmpaddr3 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr2_ref := {|
+ name := "pmpaddr2";
+ read_from := (fun s => s.(pmpaddr2));
+ write_to := (fun v s => ({[ s with pmpaddr2 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr1_ref := {|
+ name := "pmpaddr1";
+ read_from := (fun s => s.(pmpaddr1));
+ write_to := (fun v s => ({[ s with pmpaddr1 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmpaddr0_ref := {|
+ name := "pmpaddr0";
+ read_from := (fun s => s.(pmpaddr0));
+ write_to := (fun v s => ({[ s with pmpaddr0 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition pmp15cfg_ref := {|
+ name := "pmp15cfg";
+ read_from := (fun s => s.(pmp15cfg));
+ write_to := (fun v s => ({[ s with pmp15cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp14cfg_ref := {|
+ name := "pmp14cfg";
+ read_from := (fun s => s.(pmp14cfg));
+ write_to := (fun v s => ({[ s with pmp14cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp13cfg_ref := {|
+ name := "pmp13cfg";
+ read_from := (fun s => s.(pmp13cfg));
+ write_to := (fun v s => ({[ s with pmp13cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp12cfg_ref := {|
+ name := "pmp12cfg";
+ read_from := (fun s => s.(pmp12cfg));
+ write_to := (fun v s => ({[ s with pmp12cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp11cfg_ref := {|
+ name := "pmp11cfg";
+ read_from := (fun s => s.(pmp11cfg));
+ write_to := (fun v s => ({[ s with pmp11cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp10cfg_ref := {|
+ name := "pmp10cfg";
+ read_from := (fun s => s.(pmp10cfg));
+ write_to := (fun v s => ({[ s with pmp10cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp9cfg_ref := {|
+ name := "pmp9cfg";
+ read_from := (fun s => s.(pmp9cfg));
+ write_to := (fun v s => ({[ s with pmp9cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp8cfg_ref := {|
+ name := "pmp8cfg";
+ read_from := (fun s => s.(pmp8cfg));
+ write_to := (fun v s => ({[ s with pmp8cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp7cfg_ref := {|
+ name := "pmp7cfg";
+ read_from := (fun s => s.(pmp7cfg));
+ write_to := (fun v s => ({[ s with pmp7cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp6cfg_ref := {|
+ name := "pmp6cfg";
+ read_from := (fun s => s.(pmp6cfg));
+ write_to := (fun v s => ({[ s with pmp6cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp5cfg_ref := {|
+ name := "pmp5cfg";
+ read_from := (fun s => s.(pmp5cfg));
+ write_to := (fun v s => ({[ s with pmp5cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp4cfg_ref := {|
+ name := "pmp4cfg";
+ read_from := (fun s => s.(pmp4cfg));
+ write_to := (fun v s => ({[ s with pmp4cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp3cfg_ref := {|
+ name := "pmp3cfg";
+ read_from := (fun s => s.(pmp3cfg));
+ write_to := (fun v s => ({[ s with pmp3cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp2cfg_ref := {|
+ name := "pmp2cfg";
+ read_from := (fun s => s.(pmp2cfg));
+ write_to := (fun v s => ({[ s with pmp2cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp1cfg_ref := {|
+ name := "pmp1cfg";
+ read_from := (fun s => s.(pmp1cfg));
+ write_to := (fun v s => ({[ s with pmp1cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition pmp0cfg_ref := {|
+ name := "pmp0cfg";
+ read_from := (fun s => s.(pmp0cfg));
+ write_to := (fun v s => ({[ s with pmp0cfg := v ]}));
+ of_regval := (fun v => Pmpcfg_ent_of_regval v);
+ regval_of := (fun v => regval_of_Pmpcfg_ent v) |}.
+
+Definition tselect_ref := {|
+ name := "tselect";
+ read_from := (fun s => s.(tselect));
+ write_to := (fun v s => ({[ s with tselect := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition stval_ref := {|
+ name := "stval";
+ read_from := (fun s => s.(stval));
+ write_to := (fun v s => ({[ s with stval := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition scause_ref := {|
+ name := "scause";
+ read_from := (fun s => s.(scause));
+ write_to := (fun v s => ({[ s with scause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition sepc_ref := {|
+ name := "sepc";
+ read_from := (fun s => s.(sepc));
+ write_to := (fun v s => ({[ s with sepc := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition sscratch_ref := {|
+ name := "sscratch";
+ read_from := (fun s => s.(sscratch));
+ write_to := (fun v s => ({[ s with sscratch := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition stvec_ref := {|
+ name := "stvec";
+ read_from := (fun s => s.(stvec));
+ write_to := (fun v s => ({[ s with stvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition sideleg_ref := {|
+ name := "sideleg";
+ read_from := (fun s => s.(sideleg));
+ write_to := (fun v s => ({[ s with sideleg := v ]}));
+ of_regval := (fun v => Sinterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Sinterrupts v) |}.
+
+Definition sedeleg_ref := {|
+ name := "sedeleg";
+ read_from := (fun s => s.(sedeleg));
+ write_to := (fun v s => ({[ s with sedeleg := v ]}));
+ of_regval := (fun v => Sedeleg_of_regval v);
+ regval_of := (fun v => regval_of_Sedeleg v) |}.
+
+Definition mhartid_ref := {|
+ name := "mhartid";
+ read_from := (fun s => s.(mhartid));
+ write_to := (fun v s => ({[ s with mhartid := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition marchid_ref := {|
+ name := "marchid";
+ read_from := (fun s => s.(marchid));
+ write_to := (fun v s => ({[ s with marchid := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mimpid_ref := {|
+ name := "mimpid";
+ read_from := (fun s => s.(mimpid));
+ write_to := (fun v s => ({[ s with mimpid := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mvendorid_ref := {|
+ name := "mvendorid";
+ read_from := (fun s => s.(mvendorid));
+ write_to := (fun v s => ({[ s with mvendorid := v ]}));
+ of_regval := (fun v => bitvector_32_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_32_dec v) |}.
+
+Definition minstret_written_ref := {|
+ name := "minstret_written";
+ read_from := (fun s => s.(minstret_written));
+ write_to := (fun v s => ({[ s with minstret_written := v ]}));
+ of_regval := (fun v => bool_of_regval v);
+ regval_of := (fun v => regval_of_bool v) |}.
+
+Definition minstret_ref := {|
+ name := "minstret";
+ read_from := (fun s => s.(minstret));
+ write_to := (fun v s => ({[ s with minstret := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mtime_ref := {|
+ name := "mtime";
+ read_from := (fun s => s.(mtime));
+ write_to := (fun v s => ({[ s with mtime := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mcycle_ref := {|
+ name := "mcycle";
+ read_from := (fun s => s.(mcycle));
+ write_to := (fun v s => ({[ s with mcycle := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition scounteren_ref := {|
+ name := "scounteren";
+ read_from := (fun s => s.(scounteren));
+ write_to := (fun v s => ({[ s with scounteren := v ]}));
+ of_regval := (fun v => Counteren_of_regval v);
+ regval_of := (fun v => regval_of_Counteren v) |}.
+
+Definition mcounteren_ref := {|
+ name := "mcounteren";
+ read_from := (fun s => s.(mcounteren));
+ write_to := (fun v s => ({[ s with mcounteren := v ]}));
+ of_regval := (fun v => Counteren_of_regval v);
+ regval_of := (fun v => regval_of_Counteren v) |}.
+
+Definition mscratch_ref := {|
+ name := "mscratch";
+ read_from := (fun s => s.(mscratch));
+ write_to := (fun v s => ({[ s with mscratch := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mtval_ref := {|
+ name := "mtval";
+ read_from := (fun s => s.(mtval));
+ write_to := (fun v s => ({[ s with mtval := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mepc_ref := {|
+ name := "mepc";
+ read_from := (fun s => s.(mepc));
+ write_to := (fun v s => ({[ s with mepc := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition mcause_ref := {|
+ name := "mcause";
+ read_from := (fun s => s.(mcause));
+ write_to := (fun v s => ({[ s with mcause := v ]}));
+ of_regval := (fun v => Mcause_of_regval v);
+ regval_of := (fun v => regval_of_Mcause v) |}.
+
+Definition mtvec_ref := {|
+ name := "mtvec";
+ read_from := (fun s => s.(mtvec));
+ write_to := (fun v s => ({[ s with mtvec := v ]}));
+ of_regval := (fun v => Mtvec_of_regval v);
+ regval_of := (fun v => regval_of_Mtvec v) |}.
+
+Definition medeleg_ref := {|
+ name := "medeleg";
+ read_from := (fun s => s.(medeleg));
+ write_to := (fun v s => ({[ s with medeleg := v ]}));
+ of_regval := (fun v => Medeleg_of_regval v);
+ regval_of := (fun v => regval_of_Medeleg v) |}.
+
+Definition mideleg_ref := {|
+ name := "mideleg";
+ read_from := (fun s => s.(mideleg));
+ write_to := (fun v s => ({[ s with mideleg := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mie_ref := {|
+ name := "mie";
+ read_from := (fun s => s.(mie));
+ write_to := (fun v s => ({[ s with mie := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mip_ref := {|
+ name := "mip";
+ read_from := (fun s => s.(mip));
+ write_to := (fun v s => ({[ s with mip := v ]}));
+ of_regval := (fun v => Minterrupts_of_regval v);
+ regval_of := (fun v => regval_of_Minterrupts v) |}.
+
+Definition mstatus_ref := {|
+ name := "mstatus";
+ read_from := (fun s => s.(mstatus));
+ write_to := (fun v s => ({[ s with mstatus := v ]}));
+ of_regval := (fun v => Mstatus_of_regval v);
+ regval_of := (fun v => regval_of_Mstatus v) |}.
+
+Definition misa_ref := {|
+ name := "misa";
+ read_from := (fun s => s.(misa));
+ write_to := (fun v s => ({[ s with misa := v ]}));
+ of_regval := (fun v => Misa_of_regval v);
+ regval_of := (fun v => regval_of_Misa v) |}.
+
+Definition cur_inst_ref := {|
+ name := "cur_inst";
+ read_from := (fun s => s.(cur_inst));
+ write_to := (fun v s => ({[ s with cur_inst := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition cur_privilege_ref := {|
+ name := "cur_privilege";
+ read_from := (fun s => s.(cur_privilege));
+ write_to := (fun v s => ({[ s with cur_privilege := v ]}));
+ of_regval := (fun v => Privilege_of_regval v);
+ regval_of := (fun v => regval_of_Privilege v) |}.
+
+Definition x31_ref := {|
+ name := "x31";
+ read_from := (fun s => s.(x31));
+ write_to := (fun v s => ({[ s with x31 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x30_ref := {|
+ name := "x30";
+ read_from := (fun s => s.(x30));
+ write_to := (fun v s => ({[ s with x30 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x29_ref := {|
+ name := "x29";
+ read_from := (fun s => s.(x29));
+ write_to := (fun v s => ({[ s with x29 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x28_ref := {|
+ name := "x28";
+ read_from := (fun s => s.(x28));
+ write_to := (fun v s => ({[ s with x28 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x27_ref := {|
+ name := "x27";
+ read_from := (fun s => s.(x27));
+ write_to := (fun v s => ({[ s with x27 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x26_ref := {|
+ name := "x26";
+ read_from := (fun s => s.(x26));
+ write_to := (fun v s => ({[ s with x26 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x25_ref := {|
+ name := "x25";
+ read_from := (fun s => s.(x25));
+ write_to := (fun v s => ({[ s with x25 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x24_ref := {|
+ name := "x24";
+ read_from := (fun s => s.(x24));
+ write_to := (fun v s => ({[ s with x24 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x23_ref := {|
+ name := "x23";
+ read_from := (fun s => s.(x23));
+ write_to := (fun v s => ({[ s with x23 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x22_ref := {|
+ name := "x22";
+ read_from := (fun s => s.(x22));
+ write_to := (fun v s => ({[ s with x22 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x21_ref := {|
+ name := "x21";
+ read_from := (fun s => s.(x21));
+ write_to := (fun v s => ({[ s with x21 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x20_ref := {|
+ name := "x20";
+ read_from := (fun s => s.(x20));
+ write_to := (fun v s => ({[ s with x20 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x19_ref := {|
+ name := "x19";
+ read_from := (fun s => s.(x19));
+ write_to := (fun v s => ({[ s with x19 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x18_ref := {|
+ name := "x18";
+ read_from := (fun s => s.(x18));
+ write_to := (fun v s => ({[ s with x18 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x17_ref := {|
+ name := "x17";
+ read_from := (fun s => s.(x17));
+ write_to := (fun v s => ({[ s with x17 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x16_ref := {|
+ name := "x16";
+ read_from := (fun s => s.(x16));
+ write_to := (fun v s => ({[ s with x16 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x15_ref := {|
+ name := "x15";
+ read_from := (fun s => s.(x15));
+ write_to := (fun v s => ({[ s with x15 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x14_ref := {|
+ name := "x14";
+ read_from := (fun s => s.(x14));
+ write_to := (fun v s => ({[ s with x14 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x13_ref := {|
+ name := "x13";
+ read_from := (fun s => s.(x13));
+ write_to := (fun v s => ({[ s with x13 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x12_ref := {|
+ name := "x12";
+ read_from := (fun s => s.(x12));
+ write_to := (fun v s => ({[ s with x12 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x11_ref := {|
+ name := "x11";
+ read_from := (fun s => s.(x11));
+ write_to := (fun v s => ({[ s with x11 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x10_ref := {|
+ name := "x10";
+ read_from := (fun s => s.(x10));
+ write_to := (fun v s => ({[ s with x10 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x9_ref := {|
+ name := "x9";
+ read_from := (fun s => s.(x9));
+ write_to := (fun v s => ({[ s with x9 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x8_ref := {|
+ name := "x8";
+ read_from := (fun s => s.(x8));
+ write_to := (fun v s => ({[ s with x8 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x7_ref := {|
+ name := "x7";
+ read_from := (fun s => s.(x7));
+ write_to := (fun v s => ({[ s with x7 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x6_ref := {|
+ name := "x6";
+ read_from := (fun s => s.(x6));
+ write_to := (fun v s => ({[ s with x6 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x5_ref := {|
+ name := "x5";
+ read_from := (fun s => s.(x5));
+ write_to := (fun v s => ({[ s with x5 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x4_ref := {|
+ name := "x4";
+ read_from := (fun s => s.(x4));
+ write_to := (fun v s => ({[ s with x4 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x3_ref := {|
+ name := "x3";
+ read_from := (fun s => s.(x3));
+ write_to := (fun v s => ({[ s with x3 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x2_ref := {|
+ name := "x2";
+ read_from := (fun s => s.(x2));
+ write_to := (fun v s => ({[ s with x2 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition x1_ref := {|
+ name := "x1";
+ read_from := (fun s => s.(x1));
+ write_to := (fun v s => ({[ s with x1 := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition Xs_ref := {|
+ name := "Xs";
+ read_from := (fun s => s.(Xs));
+ write_to := (fun v s => ({[ s with Xs := v ]}));
+ of_regval := (fun v => vector_of_regval 32 (fun v => bitvector_64_dec_of_regval v) v);
+ regval_of := (fun v => regval_of_vector (fun v => regval_of_bitvector_64_dec v) 32 false v) |}.
+
+Definition instbits_ref := {|
+ name := "instbits";
+ read_from := (fun s => s.(instbits));
+ write_to := (fun v s => ({[ s with instbits := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition nextPC_ref := {|
+ name := "nextPC";
+ read_from := (fun s => s.(nextPC));
+ write_to := (fun v s => ({[ s with nextPC := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition PC_ref := {|
+ name := "PC";
+ read_from := (fun s => s.(PC));
+ write_to := (fun v s => ({[ s with PC := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+ if string_dec reg_name "satp" then Some (satp_ref.(regval_of) (satp_ref.(read_from) s)) else
+ if string_dec reg_name "tlb48" then Some (tlb48_ref.(regval_of) (tlb48_ref.(read_from) s)) else
+ if string_dec reg_name "tlb39" then Some (tlb39_ref.(regval_of) (tlb39_ref.(read_from) s)) else
+ if string_dec reg_name "htif_exit_code" then Some (htif_exit_code_ref.(regval_of) (htif_exit_code_ref.(read_from) s)) else
+ if string_dec reg_name "htif_done" then Some (htif_done_ref.(regval_of) (htif_done_ref.(read_from) s)) else
+ if string_dec reg_name "htif_tohost" then Some (htif_tohost_ref.(regval_of) (htif_tohost_ref.(read_from) s)) else
+ if string_dec reg_name "mtimecmp" then Some (mtimecmp_ref.(regval_of) (mtimecmp_ref.(read_from) s)) else
+ if string_dec reg_name "utval" then Some (utval_ref.(regval_of) (utval_ref.(read_from) s)) else
+ if string_dec reg_name "ucause" then Some (ucause_ref.(regval_of) (ucause_ref.(read_from) s)) else
+ if string_dec reg_name "uepc" then Some (uepc_ref.(regval_of) (uepc_ref.(read_from) s)) else
+ if string_dec reg_name "uscratch" then Some (uscratch_ref.(regval_of) (uscratch_ref.(read_from) s)) else
+ if string_dec reg_name "utvec" then Some (utvec_ref.(regval_of) (utvec_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr15" then Some (pmpaddr15_ref.(regval_of) (pmpaddr15_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr14" then Some (pmpaddr14_ref.(regval_of) (pmpaddr14_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr13" then Some (pmpaddr13_ref.(regval_of) (pmpaddr13_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr12" then Some (pmpaddr12_ref.(regval_of) (pmpaddr12_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr11" then Some (pmpaddr11_ref.(regval_of) (pmpaddr11_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr10" then Some (pmpaddr10_ref.(regval_of) (pmpaddr10_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr9" then Some (pmpaddr9_ref.(regval_of) (pmpaddr9_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr8" then Some (pmpaddr8_ref.(regval_of) (pmpaddr8_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr7" then Some (pmpaddr7_ref.(regval_of) (pmpaddr7_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr6" then Some (pmpaddr6_ref.(regval_of) (pmpaddr6_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr5" then Some (pmpaddr5_ref.(regval_of) (pmpaddr5_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr4" then Some (pmpaddr4_ref.(regval_of) (pmpaddr4_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr3" then Some (pmpaddr3_ref.(regval_of) (pmpaddr3_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr2" then Some (pmpaddr2_ref.(regval_of) (pmpaddr2_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr1" then Some (pmpaddr1_ref.(regval_of) (pmpaddr1_ref.(read_from) s)) else
+ if string_dec reg_name "pmpaddr0" then Some (pmpaddr0_ref.(regval_of) (pmpaddr0_ref.(read_from) s)) else
+ if string_dec reg_name "pmp15cfg" then Some (pmp15cfg_ref.(regval_of) (pmp15cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp14cfg" then Some (pmp14cfg_ref.(regval_of) (pmp14cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp13cfg" then Some (pmp13cfg_ref.(regval_of) (pmp13cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp12cfg" then Some (pmp12cfg_ref.(regval_of) (pmp12cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp11cfg" then Some (pmp11cfg_ref.(regval_of) (pmp11cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp10cfg" then Some (pmp10cfg_ref.(regval_of) (pmp10cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp9cfg" then Some (pmp9cfg_ref.(regval_of) (pmp9cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp8cfg" then Some (pmp8cfg_ref.(regval_of) (pmp8cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp7cfg" then Some (pmp7cfg_ref.(regval_of) (pmp7cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp6cfg" then Some (pmp6cfg_ref.(regval_of) (pmp6cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp5cfg" then Some (pmp5cfg_ref.(regval_of) (pmp5cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp4cfg" then Some (pmp4cfg_ref.(regval_of) (pmp4cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp3cfg" then Some (pmp3cfg_ref.(regval_of) (pmp3cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp2cfg" then Some (pmp2cfg_ref.(regval_of) (pmp2cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp1cfg" then Some (pmp1cfg_ref.(regval_of) (pmp1cfg_ref.(read_from) s)) else
+ if string_dec reg_name "pmp0cfg" then Some (pmp0cfg_ref.(regval_of) (pmp0cfg_ref.(read_from) s)) else
+ if string_dec reg_name "tselect" then Some (tselect_ref.(regval_of) (tselect_ref.(read_from) s)) else
+ if string_dec reg_name "stval" then Some (stval_ref.(regval_of) (stval_ref.(read_from) s)) else
+ if string_dec reg_name "scause" then Some (scause_ref.(regval_of) (scause_ref.(read_from) s)) else
+ if string_dec reg_name "sepc" then Some (sepc_ref.(regval_of) (sepc_ref.(read_from) s)) else
+ if string_dec reg_name "sscratch" then Some (sscratch_ref.(regval_of) (sscratch_ref.(read_from) s)) else
+ if string_dec reg_name "stvec" then Some (stvec_ref.(regval_of) (stvec_ref.(read_from) s)) else
+ if string_dec reg_name "sideleg" then Some (sideleg_ref.(regval_of) (sideleg_ref.(read_from) s)) else
+ if string_dec reg_name "sedeleg" then Some (sedeleg_ref.(regval_of) (sedeleg_ref.(read_from) s)) else
+ if string_dec reg_name "mhartid" then Some (mhartid_ref.(regval_of) (mhartid_ref.(read_from) s)) else
+ if string_dec reg_name "marchid" then Some (marchid_ref.(regval_of) (marchid_ref.(read_from) s)) else
+ if string_dec reg_name "mimpid" then Some (mimpid_ref.(regval_of) (mimpid_ref.(read_from) s)) else
+ if string_dec reg_name "mvendorid" then Some (mvendorid_ref.(regval_of) (mvendorid_ref.(read_from) s)) else
+ if string_dec reg_name "minstret_written" then Some (minstret_written_ref.(regval_of) (minstret_written_ref.(read_from) s)) else
+ if string_dec reg_name "minstret" then Some (minstret_ref.(regval_of) (minstret_ref.(read_from) s)) else
+ if string_dec reg_name "mtime" then Some (mtime_ref.(regval_of) (mtime_ref.(read_from) s)) else
+ if string_dec reg_name "mcycle" then Some (mcycle_ref.(regval_of) (mcycle_ref.(read_from) s)) else
+ if string_dec reg_name "scounteren" then Some (scounteren_ref.(regval_of) (scounteren_ref.(read_from) s)) else
+ if string_dec reg_name "mcounteren" then Some (mcounteren_ref.(regval_of) (mcounteren_ref.(read_from) s)) else
+ if string_dec reg_name "mscratch" then Some (mscratch_ref.(regval_of) (mscratch_ref.(read_from) s)) else
+ if string_dec reg_name "mtval" then Some (mtval_ref.(regval_of) (mtval_ref.(read_from) s)) else
+ if string_dec reg_name "mepc" then Some (mepc_ref.(regval_of) (mepc_ref.(read_from) s)) else
+ if string_dec reg_name "mcause" then Some (mcause_ref.(regval_of) (mcause_ref.(read_from) s)) else
+ if string_dec reg_name "mtvec" then Some (mtvec_ref.(regval_of) (mtvec_ref.(read_from) s)) else
+ if string_dec reg_name "medeleg" then Some (medeleg_ref.(regval_of) (medeleg_ref.(read_from) s)) else
+ if string_dec reg_name "mideleg" then Some (mideleg_ref.(regval_of) (mideleg_ref.(read_from) s)) else
+ if string_dec reg_name "mie" then Some (mie_ref.(regval_of) (mie_ref.(read_from) s)) else
+ if string_dec reg_name "mip" then Some (mip_ref.(regval_of) (mip_ref.(read_from) s)) else
+ if string_dec reg_name "mstatus" then Some (mstatus_ref.(regval_of) (mstatus_ref.(read_from) s)) else
+ if string_dec reg_name "misa" then Some (misa_ref.(regval_of) (misa_ref.(read_from) s)) else
+ if string_dec reg_name "cur_inst" then Some (cur_inst_ref.(regval_of) (cur_inst_ref.(read_from) s)) else
+ if string_dec reg_name "cur_privilege" then Some (cur_privilege_ref.(regval_of) (cur_privilege_ref.(read_from) s)) else
+ if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else
+ if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else
+ if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else
+ if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else
+ if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else
+ if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else
+ if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else
+ if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else
+ if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else
+ if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else
+ if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else
+ if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else
+ if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else
+ if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else
+ if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else
+ if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else
+ if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else
+ if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else
+ if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else
+ if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else
+ if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else
+ if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else
+ if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else
+ if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else
+ if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else
+ if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else
+ if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else
+ if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else
+ if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else
+ if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else
+ if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else
+ if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else
+ if string_dec reg_name "instbits" then Some (instbits_ref.(regval_of) (instbits_ref.(read_from) s)) else
+ if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+ if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+ None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+ if string_dec reg_name "satp" then option_map (fun v => satp_ref.(write_to) v s) (satp_ref.(of_regval) v) else
+ if string_dec reg_name "tlb48" then option_map (fun v => tlb48_ref.(write_to) v s) (tlb48_ref.(of_regval) v) else
+ if string_dec reg_name "tlb39" then option_map (fun v => tlb39_ref.(write_to) v s) (tlb39_ref.(of_regval) v) else
+ if string_dec reg_name "htif_exit_code" then option_map (fun v => htif_exit_code_ref.(write_to) v s) (htif_exit_code_ref.(of_regval) v) else
+ if string_dec reg_name "htif_done" then option_map (fun v => htif_done_ref.(write_to) v s) (htif_done_ref.(of_regval) v) else
+ if string_dec reg_name "htif_tohost" then option_map (fun v => htif_tohost_ref.(write_to) v s) (htif_tohost_ref.(of_regval) v) else
+ if string_dec reg_name "mtimecmp" then option_map (fun v => mtimecmp_ref.(write_to) v s) (mtimecmp_ref.(of_regval) v) else
+ if string_dec reg_name "utval" then option_map (fun v => utval_ref.(write_to) v s) (utval_ref.(of_regval) v) else
+ if string_dec reg_name "ucause" then option_map (fun v => ucause_ref.(write_to) v s) (ucause_ref.(of_regval) v) else
+ if string_dec reg_name "uepc" then option_map (fun v => uepc_ref.(write_to) v s) (uepc_ref.(of_regval) v) else
+ if string_dec reg_name "uscratch" then option_map (fun v => uscratch_ref.(write_to) v s) (uscratch_ref.(of_regval) v) else
+ if string_dec reg_name "utvec" then option_map (fun v => utvec_ref.(write_to) v s) (utvec_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr15" then option_map (fun v => pmpaddr15_ref.(write_to) v s) (pmpaddr15_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr14" then option_map (fun v => pmpaddr14_ref.(write_to) v s) (pmpaddr14_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr13" then option_map (fun v => pmpaddr13_ref.(write_to) v s) (pmpaddr13_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr12" then option_map (fun v => pmpaddr12_ref.(write_to) v s) (pmpaddr12_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr11" then option_map (fun v => pmpaddr11_ref.(write_to) v s) (pmpaddr11_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr10" then option_map (fun v => pmpaddr10_ref.(write_to) v s) (pmpaddr10_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr9" then option_map (fun v => pmpaddr9_ref.(write_to) v s) (pmpaddr9_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr8" then option_map (fun v => pmpaddr8_ref.(write_to) v s) (pmpaddr8_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr7" then option_map (fun v => pmpaddr7_ref.(write_to) v s) (pmpaddr7_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr6" then option_map (fun v => pmpaddr6_ref.(write_to) v s) (pmpaddr6_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr5" then option_map (fun v => pmpaddr5_ref.(write_to) v s) (pmpaddr5_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr4" then option_map (fun v => pmpaddr4_ref.(write_to) v s) (pmpaddr4_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr3" then option_map (fun v => pmpaddr3_ref.(write_to) v s) (pmpaddr3_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr2" then option_map (fun v => pmpaddr2_ref.(write_to) v s) (pmpaddr2_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr1" then option_map (fun v => pmpaddr1_ref.(write_to) v s) (pmpaddr1_ref.(of_regval) v) else
+ if string_dec reg_name "pmpaddr0" then option_map (fun v => pmpaddr0_ref.(write_to) v s) (pmpaddr0_ref.(of_regval) v) else
+ if string_dec reg_name "pmp15cfg" then option_map (fun v => pmp15cfg_ref.(write_to) v s) (pmp15cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp14cfg" then option_map (fun v => pmp14cfg_ref.(write_to) v s) (pmp14cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp13cfg" then option_map (fun v => pmp13cfg_ref.(write_to) v s) (pmp13cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp12cfg" then option_map (fun v => pmp12cfg_ref.(write_to) v s) (pmp12cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp11cfg" then option_map (fun v => pmp11cfg_ref.(write_to) v s) (pmp11cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp10cfg" then option_map (fun v => pmp10cfg_ref.(write_to) v s) (pmp10cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp9cfg" then option_map (fun v => pmp9cfg_ref.(write_to) v s) (pmp9cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp8cfg" then option_map (fun v => pmp8cfg_ref.(write_to) v s) (pmp8cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp7cfg" then option_map (fun v => pmp7cfg_ref.(write_to) v s) (pmp7cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp6cfg" then option_map (fun v => pmp6cfg_ref.(write_to) v s) (pmp6cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp5cfg" then option_map (fun v => pmp5cfg_ref.(write_to) v s) (pmp5cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp4cfg" then option_map (fun v => pmp4cfg_ref.(write_to) v s) (pmp4cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp3cfg" then option_map (fun v => pmp3cfg_ref.(write_to) v s) (pmp3cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp2cfg" then option_map (fun v => pmp2cfg_ref.(write_to) v s) (pmp2cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp1cfg" then option_map (fun v => pmp1cfg_ref.(write_to) v s) (pmp1cfg_ref.(of_regval) v) else
+ if string_dec reg_name "pmp0cfg" then option_map (fun v => pmp0cfg_ref.(write_to) v s) (pmp0cfg_ref.(of_regval) v) else
+ if string_dec reg_name "tselect" then option_map (fun v => tselect_ref.(write_to) v s) (tselect_ref.(of_regval) v) else
+ if string_dec reg_name "stval" then option_map (fun v => stval_ref.(write_to) v s) (stval_ref.(of_regval) v) else
+ if string_dec reg_name "scause" then option_map (fun v => scause_ref.(write_to) v s) (scause_ref.(of_regval) v) else
+ if string_dec reg_name "sepc" then option_map (fun v => sepc_ref.(write_to) v s) (sepc_ref.(of_regval) v) else
+ if string_dec reg_name "sscratch" then option_map (fun v => sscratch_ref.(write_to) v s) (sscratch_ref.(of_regval) v) else
+ if string_dec reg_name "stvec" then option_map (fun v => stvec_ref.(write_to) v s) (stvec_ref.(of_regval) v) else
+ if string_dec reg_name "sideleg" then option_map (fun v => sideleg_ref.(write_to) v s) (sideleg_ref.(of_regval) v) else
+ if string_dec reg_name "sedeleg" then option_map (fun v => sedeleg_ref.(write_to) v s) (sedeleg_ref.(of_regval) v) else
+ if string_dec reg_name "mhartid" then option_map (fun v => mhartid_ref.(write_to) v s) (mhartid_ref.(of_regval) v) else
+ if string_dec reg_name "marchid" then option_map (fun v => marchid_ref.(write_to) v s) (marchid_ref.(of_regval) v) else
+ if string_dec reg_name "mimpid" then option_map (fun v => mimpid_ref.(write_to) v s) (mimpid_ref.(of_regval) v) else
+ if string_dec reg_name "mvendorid" then option_map (fun v => mvendorid_ref.(write_to) v s) (mvendorid_ref.(of_regval) v) else
+ if string_dec reg_name "minstret_written" then option_map (fun v => minstret_written_ref.(write_to) v s) (minstret_written_ref.(of_regval) v) else
+ if string_dec reg_name "minstret" then option_map (fun v => minstret_ref.(write_to) v s) (minstret_ref.(of_regval) v) else
+ if string_dec reg_name "mtime" then option_map (fun v => mtime_ref.(write_to) v s) (mtime_ref.(of_regval) v) else
+ if string_dec reg_name "mcycle" then option_map (fun v => mcycle_ref.(write_to) v s) (mcycle_ref.(of_regval) v) else
+ if string_dec reg_name "scounteren" then option_map (fun v => scounteren_ref.(write_to) v s) (scounteren_ref.(of_regval) v) else
+ if string_dec reg_name "mcounteren" then option_map (fun v => mcounteren_ref.(write_to) v s) (mcounteren_ref.(of_regval) v) else
+ if string_dec reg_name "mscratch" then option_map (fun v => mscratch_ref.(write_to) v s) (mscratch_ref.(of_regval) v) else
+ if string_dec reg_name "mtval" then option_map (fun v => mtval_ref.(write_to) v s) (mtval_ref.(of_regval) v) else
+ if string_dec reg_name "mepc" then option_map (fun v => mepc_ref.(write_to) v s) (mepc_ref.(of_regval) v) else
+ if string_dec reg_name "mcause" then option_map (fun v => mcause_ref.(write_to) v s) (mcause_ref.(of_regval) v) else
+ if string_dec reg_name "mtvec" then option_map (fun v => mtvec_ref.(write_to) v s) (mtvec_ref.(of_regval) v) else
+ if string_dec reg_name "medeleg" then option_map (fun v => medeleg_ref.(write_to) v s) (medeleg_ref.(of_regval) v) else
+ if string_dec reg_name "mideleg" then option_map (fun v => mideleg_ref.(write_to) v s) (mideleg_ref.(of_regval) v) else
+ if string_dec reg_name "mie" then option_map (fun v => mie_ref.(write_to) v s) (mie_ref.(of_regval) v) else
+ if string_dec reg_name "mip" then option_map (fun v => mip_ref.(write_to) v s) (mip_ref.(of_regval) v) else
+ if string_dec reg_name "mstatus" then option_map (fun v => mstatus_ref.(write_to) v s) (mstatus_ref.(of_regval) v) else
+ if string_dec reg_name "misa" then option_map (fun v => misa_ref.(write_to) v s) (misa_ref.(of_regval) v) else
+ if string_dec reg_name "cur_inst" then option_map (fun v => cur_inst_ref.(write_to) v s) (cur_inst_ref.(of_regval) v) else
+ if string_dec reg_name "cur_privilege" then option_map (fun v => cur_privilege_ref.(write_to) v s) (cur_privilege_ref.(of_regval) v) else
+ if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else
+ if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else
+ if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else
+ if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else
+ if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else
+ if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else
+ if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else
+ if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else
+ if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else
+ if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else
+ if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else
+ if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else
+ if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else
+ if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else
+ if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else
+ if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else
+ if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else
+ if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else
+ if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else
+ if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else
+ if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else
+ if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else
+ if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else
+ if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else
+ if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else
+ if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else
+ if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else
+ if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else
+ if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else
+ if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else
+ if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else
+ if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else
+ if string_dec reg_name "instbits" then option_map (fun v => instbits_ref.(write_to) v s) (instbits_ref.(of_regval) v) else
+ if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+ if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+ None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r exception.
+Definition M a := monad register_value a exception.
diff --git a/prover_snapshots/coq/build b/prover_snapshots/coq/build
new file mode 100755
index 0000000..f8a1c2f
--- /dev/null
+++ b/prover_snapshots/coq/build
@@ -0,0 +1,27 @@
+#!/bin/bash
+
+if [ ! -d RV64 ]; then
+ echo Run build from the coq directory
+ exit 1
+fi
+
+if [ ! -d ../bbv ]; then
+ echo 'Check out a copy of https://github.com/mit-plv/bbv in the parent directory and build it.'
+ exit 1
+fi
+
+set -ex
+cd lib/sail
+make
+cd ../../RV32
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_extras.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_types.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv.v
+cd ../RV64
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_extras.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_types.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv.v
+cd ../duopod
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_extras.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_duopod_types.v
+coqc -R ../../bbv/theories bbv -R ../lib/sail Sail riscv_duopod.v
diff --git a/prover_snapshots/coq/clean b/prover_snapshots/coq/clean
new file mode 100755
index 0000000..6bab8e6
--- /dev/null
+++ b/prover_snapshots/coq/clean
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+if [ ! -d RV64 ]; then
+ echo Run clean from the coq directory
+ exit 1
+fi
+
+set -ex
+rm -f RV32/*.{vo,glob} RV32/.*.aux
+rm -f RV64/*.{vo,glob} RV64/.*.aux
+rm -f duopod/*.{vo,glob} RV64/.*.aux
+cd lib/sail
+make clean
diff --git a/prover_snapshots/coq/duopod/riscv_duopod.v b/prover_snapshots/coq/duopod/riscv_duopod.v
new file mode 100644
index 0000000..714bfcf
--- /dev/null
+++ b/prover_snapshots/coq/duopod/riscv_duopod.v
@@ -0,0 +1,1792 @@
+(*Generated by Sail from riscv_duopod.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Require Import riscv_duopod_types.
+Require Import riscv_extras.
+Import ListNotations.
+Open Scope string.
+Open Scope bool.
+Section Content.
+
+Definition is_none {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a)
+: bool :=
+
+ match opt with | Some (_) => true | None => false end.
+
+Definition eq_unit (_ : unit) (_ : unit)
+: {_bool : bool & ArithFact (_bool = true)} :=
+
+ build_ex(true).
+
+Definition neq_int (x : Z) (y : Z)
+: {_bool : bool & ArithFact (iff (_bool = true) (x <> y))} :=
+
+ build_ex(negb (Z.eqb x y)).
+
+Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y).
+
+Definition __id (x : Z) : {_retval : Z & ArithFact (_retval = x)} := build_ex(x).
+
+Definition concat_str_bits {n : Z} (str : string) (x : mword n)
+: string :=
+
+ String.append str (string_of_bits x).
+
+Definition concat_str_dec (str : string) (x : Z) : string := String.append str (dec_str x).
+
+
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)}
+: mword len :=
+
+ if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len
+ else zero_extend v len.
+
+Definition sail_ones (n : Z) `{ArithFact (n >= 0)} : mword n := not_vec (zeros n).
+
+Definition slice_mask (n : Z) (i : Z) (l : Z) `{ArithFact (n >= 0)}
+: mword n :=
+
+ if sumbool_of_bool ((Z.geb l n)) then shiftl (sail_ones n) i
+ else
+ let one : bits n := sail_mask n ((vec_of_bits [B1] : mword 1) : bits 1) in
+ shiftl (sub_vec (shiftl one l) one) i.
+
+Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)}
+: read_kind :=
+
+ let l__34 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__34 0)) then Read_plain
+ else if sumbool_of_bool ((Z.eqb l__34 1)) then Read_reserve
+ else if sumbool_of_bool ((Z.eqb l__34 2)) then Read_acquire
+ else if sumbool_of_bool ((Z.eqb l__34 3)) then Read_exclusive
+ else if sumbool_of_bool ((Z.eqb l__34 4)) then Read_exclusive_acquire
+ else if sumbool_of_bool ((Z.eqb l__34 5)) then Read_stream
+ else if sumbool_of_bool ((Z.eqb l__34 6)) then Read_RISCV_acquire
+ else if sumbool_of_bool ((Z.eqb l__34 7)) then Read_RISCV_strong_acquire
+ else if sumbool_of_bool ((Z.eqb l__34 8)) then Read_RISCV_reserved
+ else if sumbool_of_bool ((Z.eqb l__34 9)) then Read_RISCV_reserved_acquire
+ else if sumbool_of_bool ((Z.eqb l__34 10)) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked.
+
+Definition num_of_read_kind (arg_ : read_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 11)} :=
+
+ build_ex(match arg_ with
+ | Read_plain => 0
+ | Read_reserve => 1
+ | Read_acquire => 2
+ | Read_exclusive => 3
+ | Read_exclusive_acquire => 4
+ | Read_stream => 5
+ | Read_RISCV_acquire => 6
+ | Read_RISCV_strong_acquire => 7
+ | Read_RISCV_reserved => 8
+ | Read_RISCV_reserved_acquire => 9
+ | Read_RISCV_reserved_strong_acquire => 10
+ | Read_X86_locked => 11
+ end).
+
+Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: write_kind :=
+
+ let l__24 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__24 0)) then Write_plain
+ else if sumbool_of_bool ((Z.eqb l__24 1)) then Write_conditional
+ else if sumbool_of_bool ((Z.eqb l__24 2)) then Write_release
+ else if sumbool_of_bool ((Z.eqb l__24 3)) then Write_exclusive
+ else if sumbool_of_bool ((Z.eqb l__24 4)) then Write_exclusive_release
+ else if sumbool_of_bool ((Z.eqb l__24 5)) then Write_RISCV_release
+ else if sumbool_of_bool ((Z.eqb l__24 6)) then Write_RISCV_strong_release
+ else if sumbool_of_bool ((Z.eqb l__24 7)) then Write_RISCV_conditional
+ else if sumbool_of_bool ((Z.eqb l__24 8)) then Write_RISCV_conditional_release
+ else if sumbool_of_bool ((Z.eqb l__24 9)) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked.
+
+Definition num_of_write_kind (arg_ : write_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Write_plain => 0
+ | Write_conditional => 1
+ | Write_release => 2
+ | Write_exclusive => 3
+ | Write_exclusive_release => 4
+ | Write_RISCV_release => 5
+ | Write_RISCV_strong_release => 6
+ | Write_RISCV_conditional => 7
+ | Write_RISCV_conditional_release => 8
+ | Write_RISCV_conditional_strong_release => 9
+ | Write_X86_locked => 10
+ end).
+
+Definition a64_barrier_domain_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)}
+: a64_barrier_domain :=
+
+ let l__21 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__21 0)) then A64_FullShare
+ else if sumbool_of_bool ((Z.eqb l__21 1)) then A64_InnerShare
+ else if sumbool_of_bool ((Z.eqb l__21 2)) then A64_OuterShare
+ else A64_NonShare.
+
+Definition num_of_a64_barrier_domain (arg_ : a64_barrier_domain)
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+
+ build_ex(match arg_ with
+ | A64_FullShare => 0
+ | A64_InnerShare => 1
+ | A64_OuterShare => 2
+ | A64_NonShare => 3
+ end).
+
+Definition a64_barrier_type_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: a64_barrier_type :=
+
+ let l__19 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__19 0)) then A64_barrier_all
+ else if sumbool_of_bool ((Z.eqb l__19 1)) then A64_barrier_LD
+ else A64_barrier_ST.
+
+Definition num_of_a64_barrier_type (arg_ : a64_barrier_type)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with | A64_barrier_all => 0 | A64_barrier_LD => 1 | A64_barrier_ST => 2 end).
+
+Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)}
+: trans_kind :=
+
+ let l__17 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__17 0)) then Transaction_start
+ else if sumbool_of_bool ((Z.eqb l__17 1)) then Transaction_commit
+ else Transaction_abort.
+
+Definition num_of_trans_kind (arg_ : trans_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+
+ build_ex(match arg_ with
+ | Transaction_start => 0
+ | Transaction_commit => 1
+ | Transaction_abort => 2
+ end).
+
+Definition cache_op_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)}
+: cache_op_kind :=
+
+ let l__7 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__7 0)) then Cache_op_D_IVAC
+ else if sumbool_of_bool ((Z.eqb l__7 1)) then Cache_op_D_ISW
+ else if sumbool_of_bool ((Z.eqb l__7 2)) then Cache_op_D_CSW
+ else if sumbool_of_bool ((Z.eqb l__7 3)) then Cache_op_D_CISW
+ else if sumbool_of_bool ((Z.eqb l__7 4)) then Cache_op_D_ZVA
+ else if sumbool_of_bool ((Z.eqb l__7 5)) then Cache_op_D_CVAC
+ else if sumbool_of_bool ((Z.eqb l__7 6)) then Cache_op_D_CVAU
+ else if sumbool_of_bool ((Z.eqb l__7 7)) then Cache_op_D_CIVAC
+ else if sumbool_of_bool ((Z.eqb l__7 8)) then Cache_op_I_IALLUIS
+ else if sumbool_of_bool ((Z.eqb l__7 9)) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU.
+
+Definition num_of_cache_op_kind (arg_ : cache_op_kind)
+: {e : Z & ArithFact (0 <= e /\ e <= 10)} :=
+
+ build_ex(match arg_ with
+ | Cache_op_D_IVAC => 0
+ | Cache_op_D_ISW => 1
+ | Cache_op_D_CSW => 2
+ | Cache_op_D_CISW => 3
+ | Cache_op_D_ZVA => 4
+ | Cache_op_D_CVAC => 5
+ | Cache_op_D_CVAU => 6
+ | Cache_op_D_CIVAC => 7
+ | Cache_op_I_IALLUIS => 8
+ | Cache_op_I_IALLU => 9
+ | Cache_op_I_IVAU => 10
+ end).
+
+Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+
+
+
+Definition cast_unit_vec (b : bitU)
+: M (mword 1) :=
+
+ (match b with
+ | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1)
+ | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1)
+ | _ => exit tt : M (mword 1)
+ end)
+ : M (mword 1).
+
+Definition get_config_print_instr '(tt : unit) : bool := false.
+
+Definition get_config_print_reg '(tt : unit) : bool := false.
+
+Definition get_config_print_mem '(tt : unit) : bool := false.
+
+Definition get_config_print_platform '(tt : unit) : bool := false.
+
+Definition EXTS {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := sign_extend v m.
+
+Definition EXTZ {n : Z} (m : Z) (v : mword n) `{ArithFact (m >= n)} : mword m := zero_extend v m.
+
+Definition zeros_implicit (n : Z) `{ArithFact (n >= 0)} : mword n := zeros n.
+
+Definition zeros (n : Z) `{ArithFact (n >= 0)}
+: mword n :=
+
+ autocast (replicate_bits (vec_of_bits [B0] : mword 1) n).
+
+Definition ones (n : Z) `{ArithFact (n >= 0)} : mword n := sail_ones n.
+
+Definition bool_to_bits (x : bool)
+: mword 1 :=
+
+ if sumbool_of_bool (x) then (vec_of_bits [B1] : mword 1)
+ else (vec_of_bits [B0] : mword 1).
+
+Definition bit_to_bool (b : bitU)
+: M (bool) :=
+
+ (match b with
+ | B1 => returnm (projT1 (build_ex true : {_bool : bool & ArithFact (_bool = true)}))
+ | B0 => returnm (projT1 (build_ex false : {_bool : bool & ArithFact (not (_bool = true))}))
+ | _ => exit tt : M (bool)
+ end)
+ : M (bool).
+
+Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0.
+
+Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.ltb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n > 0)}
+: bool :=
+
+ Z.geb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.ltb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.geb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n)
+: bool :=
+
+ Z.leb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition shift_right_arith64 (v : mword 64) (shift : mword 6)
+: mword 64 :=
+
+ let v128 : bits 128 := EXTS 128 v in
+ subrange_vec_dec (shift_bits_right v128 shift) 63 0.
+
+Definition shift_right_arith32 (v : mword 32) (shift : mword 5)
+: mword 32 :=
+
+ let v64 : bits 64 := EXTS 64 v in
+ subrange_vec_dec (shift_bits_right v64 shift) 31 0.
+
+Fixpoint _rec_n_leading_spaces (s : string) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit)
+{struct _acc} : M ({n : Z & ArithFact (n >= 0)}) :=
+
+ assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ =>
+ let p0_ := s in
+ (if ((generic_eq p0_ "")) then returnm (build_ex (0 : Z))
+ else
+ let p0_ := string_take s 1 in
+ (if ((generic_eq p0_ " ")) then
+ (_rec_n_leading_spaces (string_drop s 1) (Z.sub _reclimit 1) (_limit_reduces _acc)) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >=
+ 0)}) =>
+ returnm (build_ex
+ (projT1
+ (build_ex
+ (Z.add 1 w__0)
+ : {_atom : Z & ArithFact (exists ex4231_ , _atom = (1 + ex4231_) /\ 0 <= ex4231_)})))
+ else returnm (build_ex (0 : Z)))
+ : M ({n : Z & ArithFact (n >= 0)}))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition n_leading_spaces (s : string)
+: M ({n : Z & ArithFact (n >= 0)}) :=
+
+ (_rec_n_leading_spaces s ((projT1 (string_length s)) : Z) (Zwf_guarded _))
+ : M ({n : Z & ArithFact (n >= 0)}).
+
+Definition spc_forwards '(tt : unit) : string := " ".
+
+Definition spc_backwards (s : string) : unit := tt.
+
+Definition spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ n _) =>
+ let l__6 := n in
+ returnm ((if sumbool_of_bool ((Z.eqb l__6 0)) then None
+ else Some ((tt, build_ex n)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition opt_spc_forwards '(tt : unit) : string := "".
+
+Definition opt_spc_backwards (s : string) : unit := tt.
+
+Definition opt_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (n_leading_spaces s) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= 0)}) =>
+ returnm ((Some
+ ((tt, build_ex
+ w__0)))
+ : option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition def_spc_forwards '(tt : unit) : string := " ".
+
+Definition def_spc_backwards (s : string) : unit := tt.
+
+Definition def_spc_matches_prefix (s : string)
+: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) :=
+
+ (opt_spc_matches_prefix s)
+ : M (option ((unit * {n : Z & ArithFact (n >= 0)}))).
+
+Definition hex_bits_1_forwards_matches (bv : mword 1) : bool := true.
+
+Definition hex_bits_1_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_1_matches_prefix s) with
+ | Some ((g__79, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_1_backwards (s : string)
+: M (mword 1) :=
+
+ (match (hex_bits_1_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 1)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt)
+ : M (mword 1)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 1).
+
+Definition hex_bits_2_forwards_matches (bv : mword 2) : bool := true.
+
+Definition hex_bits_2_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_2_matches_prefix s) with
+ | Some ((g__78, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_2_backwards (s : string)
+: M (mword 2) :=
+
+ (match (hex_bits_2_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 2)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt)
+ : M (mword 2)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 2).
+
+Definition hex_bits_3_forwards_matches (bv : mword 3) : bool := true.
+
+Definition hex_bits_3_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_3_matches_prefix s) with
+ | Some ((g__77, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_3_backwards (s : string)
+: M (mword 3) :=
+
+ (match (hex_bits_3_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 3)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt)
+ : M (mword 3)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 3).
+
+Definition hex_bits_4_forwards_matches (bv : mword 4) : bool := true.
+
+Definition hex_bits_4_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_4_matches_prefix s) with
+ | Some ((g__76, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_4_backwards (s : string)
+: M (mword 4) :=
+
+ (match (hex_bits_4_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 4)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt)
+ : M (mword 4)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 4).
+
+Definition hex_bits_5_forwards_matches (bv : mword 5) : bool := true.
+
+Definition hex_bits_5_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_5_matches_prefix s) with
+ | Some ((g__75, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_5_backwards (s : string)
+: M (mword 5) :=
+
+ (match (hex_bits_5_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 5)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt)
+ : M (mword 5)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 5).
+
+Definition hex_bits_6_forwards_matches (bv : mword 6) : bool := true.
+
+Definition hex_bits_6_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_6_matches_prefix s) with
+ | Some ((g__74, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_6_backwards (s : string)
+: M (mword 6) :=
+
+ (match (hex_bits_6_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 6)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt)
+ : M (mword 6)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 6).
+
+Definition hex_bits_7_forwards_matches (bv : mword 7) : bool := true.
+
+Definition hex_bits_7_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_7_matches_prefix s) with
+ | Some ((g__73, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_7_backwards (s : string)
+: M (mword 7) :=
+
+ (match (hex_bits_7_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 7)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt)
+ : M (mword 7)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 7).
+
+Definition hex_bits_8_forwards_matches (bv : mword 8) : bool := true.
+
+Definition hex_bits_8_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_8_matches_prefix s) with
+ | Some ((g__72, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_8_backwards (s : string)
+: M (mword 8) :=
+
+ (match (hex_bits_8_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 8)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt)
+ : M (mword 8)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 8).
+
+Definition hex_bits_9_forwards_matches (bv : mword 9) : bool := true.
+
+Definition hex_bits_9_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_9_matches_prefix s) with
+ | Some ((g__71, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_9_backwards (s : string)
+: M (mword 9) :=
+
+ (match (hex_bits_9_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 9)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt)
+ : M (mword 9)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 9).
+
+Definition hex_bits_10_forwards_matches (bv : mword 10) : bool := true.
+
+Definition hex_bits_10_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_10_matches_prefix s) with
+ | Some ((g__70, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_10_backwards (s : string)
+: M (mword 10) :=
+
+ (match (hex_bits_10_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 10)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt)
+ : M (mword 10)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 10).
+
+Definition hex_bits_11_forwards_matches (bv : mword 11) : bool := true.
+
+Definition hex_bits_11_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_11_matches_prefix s) with
+ | Some ((g__69, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_11_backwards (s : string)
+: M (mword 11) :=
+
+ (match (hex_bits_11_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 11)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt)
+ : M (mword 11)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 11).
+
+Definition hex_bits_12_forwards_matches (bv : mword 12) : bool := true.
+
+Definition hex_bits_12_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_12_matches_prefix s) with
+ | Some ((g__68, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_12_backwards (s : string)
+: M (mword 12) :=
+
+ (match (hex_bits_12_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 12)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt)
+ : M (mword 12)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 12).
+
+Definition hex_bits_13_forwards_matches (bv : mword 13) : bool := true.
+
+Definition hex_bits_13_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_13_matches_prefix s) with
+ | Some ((g__67, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_13_backwards (s : string)
+: M (mword 13) :=
+
+ (match (hex_bits_13_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 13)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt)
+ : M (mword 13)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 13).
+
+Definition hex_bits_14_forwards_matches (bv : mword 14) : bool := true.
+
+Definition hex_bits_14_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_14_matches_prefix s) with
+ | Some ((g__66, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_14_backwards (s : string)
+: M (mword 14) :=
+
+ (match (hex_bits_14_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 14)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt)
+ : M (mword 14)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 14).
+
+Definition hex_bits_15_forwards_matches (bv : mword 15) : bool := true.
+
+Definition hex_bits_15_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_15_matches_prefix s) with
+ | Some ((g__65, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_15_backwards (s : string)
+: M (mword 15) :=
+
+ (match (hex_bits_15_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 15)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt)
+ : M (mword 15)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 15).
+
+Definition hex_bits_16_forwards_matches (bv : mword 16) : bool := true.
+
+Definition hex_bits_16_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_16_matches_prefix s) with
+ | Some ((g__64, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_16_backwards (s : string)
+: M (mword 16) :=
+
+ (match (hex_bits_16_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 16)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt)
+ : M (mword 16)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 16).
+
+Definition hex_bits_17_forwards_matches (bv : mword 17) : bool := true.
+
+Definition hex_bits_17_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_17_matches_prefix s) with
+ | Some ((g__63, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_17_backwards (s : string)
+: M (mword 17) :=
+
+ (match (hex_bits_17_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 17)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt)
+ : M (mword 17)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 17).
+
+Definition hex_bits_18_forwards_matches (bv : mword 18) : bool := true.
+
+Definition hex_bits_18_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_18_matches_prefix s) with
+ | Some ((g__62, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_18_backwards (s : string)
+: M (mword 18) :=
+
+ (match (hex_bits_18_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 18)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt)
+ : M (mword 18)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 18).
+
+Definition hex_bits_19_forwards_matches (bv : mword 19) : bool := true.
+
+Definition hex_bits_19_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_19_matches_prefix s) with
+ | Some ((g__61, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_19_backwards (s : string)
+: M (mword 19) :=
+
+ (match (hex_bits_19_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 19)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt)
+ : M (mword 19)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 19).
+
+Definition hex_bits_20_forwards_matches (bv : mword 20) : bool := true.
+
+Definition hex_bits_20_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_20_matches_prefix s) with
+ | Some ((g__60, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_20_backwards (s : string)
+: M (mword 20) :=
+
+ (match (hex_bits_20_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 20)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt)
+ : M (mword 20)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 20).
+
+Definition hex_bits_21_forwards_matches (bv : mword 21) : bool := true.
+
+Definition hex_bits_21_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_21_matches_prefix s) with
+ | Some ((g__59, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_21_backwards (s : string)
+: M (mword 21) :=
+
+ (match (hex_bits_21_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 21)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt)
+ : M (mword 21)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 21).
+
+Definition hex_bits_22_forwards_matches (bv : mword 22) : bool := true.
+
+Definition hex_bits_22_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_22_matches_prefix s) with
+ | Some ((g__58, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_22_backwards (s : string)
+: M (mword 22) :=
+
+ (match (hex_bits_22_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 22)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt)
+ : M (mword 22)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 22).
+
+Definition hex_bits_23_forwards_matches (bv : mword 23) : bool := true.
+
+Definition hex_bits_23_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_23_matches_prefix s) with
+ | Some ((g__57, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_23_backwards (s : string)
+: M (mword 23) :=
+
+ (match (hex_bits_23_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 23)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt)
+ : M (mword 23)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 23).
+
+Definition hex_bits_24_forwards_matches (bv : mword 24) : bool := true.
+
+Definition hex_bits_24_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_24_matches_prefix s) with
+ | Some ((g__56, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_24_backwards (s : string)
+: M (mword 24) :=
+
+ (match (hex_bits_24_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 24)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt)
+ : M (mword 24)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 24).
+
+Definition hex_bits_25_forwards_matches (bv : mword 25) : bool := true.
+
+Definition hex_bits_25_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_25_matches_prefix s) with
+ | Some ((g__55, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_25_backwards (s : string)
+: M (mword 25) :=
+
+ (match (hex_bits_25_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 25)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt)
+ : M (mword 25)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 25).
+
+Definition hex_bits_26_forwards_matches (bv : mword 26) : bool := true.
+
+Definition hex_bits_26_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_26_matches_prefix s) with
+ | Some ((g__54, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_26_backwards (s : string)
+: M (mword 26) :=
+
+ (match (hex_bits_26_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 26)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt)
+ : M (mword 26)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 26).
+
+Definition hex_bits_27_forwards_matches (bv : mword 27) : bool := true.
+
+Definition hex_bits_27_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_27_matches_prefix s) with
+ | Some ((g__53, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_27_backwards (s : string)
+: M (mword 27) :=
+
+ (match (hex_bits_27_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 27)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt)
+ : M (mword 27)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 27).
+
+Definition hex_bits_28_forwards_matches (bv : mword 28) : bool := true.
+
+Definition hex_bits_28_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_28_matches_prefix s) with
+ | Some ((g__52, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_28_backwards (s : string)
+: M (mword 28) :=
+
+ (match (hex_bits_28_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 28)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt)
+ : M (mword 28)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 28).
+
+Definition hex_bits_29_forwards_matches (bv : mword 29) : bool := true.
+
+Definition hex_bits_29_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_29_matches_prefix s) with
+ | Some ((g__51, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_29_backwards (s : string)
+: M (mword 29) :=
+
+ (match (hex_bits_29_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 29)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt)
+ : M (mword 29)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 29).
+
+Definition hex_bits_30_forwards_matches (bv : mword 30) : bool := true.
+
+Definition hex_bits_30_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_30_matches_prefix s) with
+ | Some ((g__50, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_30_backwards (s : string)
+: M (mword 30) :=
+
+ (match (hex_bits_30_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 30)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt)
+ : M (mword 30)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 30).
+
+Definition hex_bits_31_forwards_matches (bv : mword 31) : bool := true.
+
+Definition hex_bits_31_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_31_matches_prefix s) with
+ | Some ((g__49, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_31_backwards (s : string)
+: M (mword 31) :=
+
+ (match (hex_bits_31_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 31)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt)
+ : M (mword 31)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 31).
+
+Definition hex_bits_32_forwards_matches (bv : mword 32) : bool := true.
+
+Definition hex_bits_32_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_32_matches_prefix s) with
+ | Some ((g__48, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_32_backwards (s : string)
+: M (mword 32) :=
+
+ (match (hex_bits_32_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 32)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt)
+ : M (mword 32)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 32).
+
+Definition hex_bits_33_forwards_matches (bv : mword 33) : bool := true.
+
+Definition hex_bits_33_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_33_matches_prefix s) with
+ | Some ((g__47, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_33_backwards (s : string)
+: M (mword 33) :=
+
+ (match (hex_bits_33_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 33)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt)
+ : M (mword 33)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 33).
+
+Definition hex_bits_48_forwards_matches (bv : mword 48) : bool := true.
+
+Definition hex_bits_48_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_48_matches_prefix s) with
+ | Some ((g__46, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_48_backwards (s : string)
+: M (mword 48) :=
+
+ (match (hex_bits_48_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 48)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt)
+ : M (mword 48)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 48).
+
+Definition hex_bits_64_forwards_matches (bv : mword 64) : bool := true.
+
+Definition hex_bits_64_backwards_matches (s : string)
+: bool :=
+
+ match s with
+ | s =>
+ if ((match (hex_bits_64_matches_prefix s) with
+ | Some ((g__45, existT _ n _)) =>
+ if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true else false
+ | _ => false
+ end)) then
+ true
+ else false
+ end.
+
+Definition hex_bits_64_backwards (s : string)
+: M (mword 64) :=
+
+ (match (hex_bits_64_matches_prefix s) with
+ | Some ((bv, existT _ n _)) =>
+ (if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then returnm (bv : mword 64)
+ else
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt)
+ : M (mword 64)
+ | _ =>
+ assert_exp' false "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3" >>= fun _ =>
+ exit tt
+ end)
+ : M (mword 64).
+
+Definition default_meta : mem_meta := tt.
+Hint Unfold default_meta : sail.
+Definition __WriteRAM_Meta (addr : mword 64) (width : Z) (meta : unit)
+: M (unit) :=
+
+ returnm (tt
+ : unit).
+
+Definition __ReadRAM_Meta (addr : mword 64) (width : Z) : M (unit) := returnm (tt : unit).
+
+Definition write_ram
+(wk : write_kind) (addr : mword 64) (width : Z) (data : mword (8 * width)) (meta : unit)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (bool) :=
+
+ (write_mem wk 64 addr width data) >>= fun ret : bool =>
+ (if sumbool_of_bool (ret) then (__WriteRAM_Meta addr width meta) : M (unit)
+ else returnm (tt : unit)) >>
+ returnm (ret
+ : bool).
+
+Definition write_ram_ea (wk : write_kind) (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (unit) :=
+
+ (write_mem_ea wk 64 addr width)
+ : M (unit).
+
+Definition read_ram (rk : read_kind) (addr : mword 64) (width : Z)
+`{ArithFact (0 < width /\ width <= 16)}
+: M (mword (8 * width)) :=
+
+ (read_mem rk 64 addr width)
+ : M (mword (8 * width)).
+
+Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit.
+
+Definition regbits_to_regno (b : mword 5)
+: {n : Z & ArithFact (0 <= n /\ n < 32)} :=
+
+ build_ex(let 'r := projT1 (uint b) in
+ r).
+
+Definition rX (l__5 : Z) `{ArithFact (0 <= l__5 /\ l__5 < 32)}
+: M (mword 64) :=
+
+ (if sumbool_of_bool ((Z.eqb l__5 0)) then
+ returnm ((EXTZ 64 (vec_of_bits [B0;B0;B0;B0] : mword 4))
+ : mword 64)
+ else if sumbool_of_bool ((Z.gtb l__5 0)) then
+ read_reg Xs_ref >>= fun w__0 : vec (mword 64) 32 =>
+ returnm ((vec_access_dec w__0 l__5)
+ : mword 64)
+ else
+ assert_exp' false "Pattern match failure at model/riscv_duopod.sail 22:0 - 23:27" >>= fun _ =>
+ exit tt)
+ : M (mword 64).
+
+Definition wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ r < 32)}
+: M (unit) :=
+
+ (if sumbool_of_bool ((projT1 (neq_int r 0))) then
+ read_reg Xs_ref >>= fun w__0 : vec (mword 64) 32 =>
+ write_reg Xs_ref (vec_update_dec w__0 r v)
+ : M (unit)
+ else returnm (tt : unit))
+ : M (unit).
+
+Definition read_mem (addr : mword 64) (width : Z) `{ArithFact (width >= 0)}
+: M (mword (8 * width)) :=
+
+ (MEMr 64 width (EXTZ 64 (vec_of_bits [B0;B0;B0;B0] : mword 4)) addr)
+ : M (mword (8 * width)).
+
+Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)}
+: iop :=
+
+ let l__0 := arg_ in
+ if sumbool_of_bool ((Z.eqb l__0 0)) then RISCV_ADDI
+ else if sumbool_of_bool ((Z.eqb l__0 1)) then RISCV_SLTI
+ else if sumbool_of_bool ((Z.eqb l__0 2)) then RISCV_SLTIU
+ else if sumbool_of_bool ((Z.eqb l__0 3)) then RISCV_XORI
+ else if sumbool_of_bool ((Z.eqb l__0 4)) then RISCV_ORI
+ else RISCV_ANDI.
+
+Definition num_of_iop (arg_ : iop)
+: {e : Z & ArithFact (0 <= e /\ e <= 5)} :=
+
+ build_ex(match arg_ with
+ | RISCV_ADDI => 0
+ | RISCV_SLTI => 1
+ | RISCV_SLTIU => 2
+ | RISCV_XORI => 3
+ | RISCV_ORI => 4
+ | RISCV_ANDI => 5
+ end).
+
+Definition execute_LOAD (imm : mword 12) (rs1 : mword 5) (rd : mword 5)
+: M (unit) :=
+
+ (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 =>
+ let addr : xlenbits := add_vec w__0 (EXTS 64 imm) in
+ (read_mem addr 8) >>= fun result : xlenbits =>
+ (wX (projT1 (regbits_to_regno rd)) result)
+ : M (unit).
+
+Definition execute_ITYPE (arg0 : mword 12) (arg1 : mword 5) (arg2 : mword 5) (arg3 : iop)
+: M (unit) :=
+
+ let merge_var := (arg0, arg1, arg2, arg3) in
+ (match merge_var with
+ | (imm, rs1, rd, RISCV_ADDI) =>
+ (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val =>
+ let imm_ext : xlenbits := EXTS 64 imm in
+ let result := add_vec rs1_val imm_ext in
+ (wX (projT1 (regbits_to_regno rd)) result)
+ : M (unit)
+ | _ => exit tt : M (unit)
+ end)
+ : M (unit).
+
+Definition execute (merge_var : ast)
+: M (unit) :=
+
+ (match merge_var with
+ | ITYPE ((imm, rs1, rd, arg3)) => (execute_ITYPE imm rs1 rd arg3) : M (unit)
+ | LOAD ((imm, rs1, rd)) => (execute_LOAD imm rs1 rd) : M (unit)
+ end)
+ : M (unit).
+
+Definition decode (v__0 : mword 32)
+: option ast :=
+
+ if ((andb (eq_vec (subrange_vec_dec v__0 14 12) (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__0 6 0)
+ (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then
+ let imm : bits 12 := subrange_vec_dec v__0 31 20 in
+ let rs1 : regbits := subrange_vec_dec v__0 19 15 in
+ let rd : regbits := subrange_vec_dec v__0 11 7 in
+ let imm : bits 12 := subrange_vec_dec v__0 31 20 in
+ Some
+ (ITYPE
+ ((imm, rs1, rd, RISCV_ADDI)))
+ else if ((andb
+ (eq_vec (subrange_vec_dec v__0 14 12) (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1)))
+ (eq_vec (subrange_vec_dec v__0 6 0)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then
+ let imm : bits 12 := subrange_vec_dec v__0 31 20 in
+ let rs1 : regbits := subrange_vec_dec v__0 19 15 in
+ let rd : regbits := subrange_vec_dec v__0 11 7 in
+ let imm : bits 12 := subrange_vec_dec v__0 31 20 in
+ Some
+ (LOAD
+ ((imm, rs1, rd)))
+ else None.
+
+Definition initial_regstate : regstate :=
+{| Xs :=
+ (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64)]);
+ nextPC :=
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64);
+ PC :=
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0]
+ : mword 64) |}.
+Hint Unfold initial_regstate : sail.
+
+End Content.
diff --git a/prover_snapshots/coq/duopod/riscv_duopod_types.v b/prover_snapshots/coq/duopod/riscv_duopod_types.v
new file mode 100644
index 0000000..b408f5c
--- /dev/null
+++ b/prover_snapshots/coq/duopod/riscv_duopod_types.v
@@ -0,0 +1,186 @@
+(*Generated by Sail from riscv_duopod.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_string.
+Require Import Sail2_real.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Import ListNotations.
+Definition bits (n : Z) : Type := mword n.
+
+Inductive regfp :=
+ | RFull : string -> regfp
+ | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp
+ | RField : (string * string) -> regfp.
+Arguments regfp : clear implicits.
+
+Definition regfps : Type := list regfp.
+
+Inductive niafp :=
+ | NIAFP_successor : unit -> niafp
+ | NIAFP_concrete_address : bits 64 -> niafp
+ | NIAFP_indirect_address : unit -> niafp.
+Arguments niafp : clear implicits.
+
+Definition niafps : Type := list niafp.
+
+Inductive diafp :=
+ | DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp.
+Arguments diafp : clear implicits.
+
+Inductive a64_barrier_domain := A64_FullShare | A64_InnerShare | A64_OuterShare | A64_NonShare.
+Scheme Equality for a64_barrier_domain.
+Instance Decidable_eq_a64_barrier_domain :
+forall (x y : a64_barrier_domain), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_domain_eq_dec.
+
+Inductive a64_barrier_type := A64_barrier_all | A64_barrier_LD | A64_barrier_ST.
+Scheme Equality for a64_barrier_type.
+Instance Decidable_eq_a64_barrier_type :
+forall (x y : a64_barrier_type), Decidable (x = y) :=
+Decidable_eq_from_dec a64_barrier_type_eq_dec.
+
+Inductive cache_op_kind :=
+ Cache_op_D_IVAC
+ | Cache_op_D_ISW
+ | Cache_op_D_CSW
+ | Cache_op_D_CISW
+ | Cache_op_D_ZVA
+ | Cache_op_D_CVAC
+ | Cache_op_D_CVAU
+ | Cache_op_D_CIVAC
+ | Cache_op_I_IALLUIS
+ | Cache_op_I_IALLU
+ | Cache_op_I_IVAU.
+Scheme Equality for cache_op_kind.
+Instance Decidable_eq_cache_op_kind :
+forall (x y : cache_op_kind), Decidable (x = y) :=
+Decidable_eq_from_dec cache_op_kind_eq_dec.
+
+Definition xlen : Z := 64.
+Hint Unfold xlen : sail.
+
+Definition xlen_bytes : Z := 8.
+Hint Unfold xlen_bytes : sail.
+
+Definition xlenbits : Type := bits 64.
+
+Definition mem_meta : Type := unit.
+
+Definition max_mem_access : Z := 16.
+Hint Unfold max_mem_access : sail.
+
+Definition regno (n : Z)`{ArithFact (0 <= n /\ n < 32)} : Type := Z.
+
+Definition regbits : Type := bits 5.
+
+Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI.
+Scheme Equality for iop.
+Instance Decidable_eq_iop :
+forall (x y : iop), Decidable (x = y) :=
+Decidable_eq_from_dec iop_eq_dec.
+
+Inductive ast :=
+ | ITYPE : (bits 12 * regbits * regbits * iop) -> ast | LOAD : (bits 12 * regbits * regbits) -> ast.
+Arguments ast : clear implicits.
+
+Inductive register_value :=
+ | Regval_vector : (Z * bool * list register_value) -> register_value
+ | Regval_list : list register_value -> register_value
+ | Regval_option : option register_value -> register_value
+ | Regval_bit : bitU -> register_value
+ | Regval_bitvector_64_dec : mword 64 -> register_value.
+Arguments register_value : clear implicits.
+
+Record regstate := { Xs : vec (mword 64) 32; nextPC : mword 64; PC : mword 64; }.
+Arguments regstate : clear implicits.
+Notation "{[ r 'with' 'Xs' := e ]}" := {| Xs := e; nextPC := nextPC r; PC := PC r |}.
+Notation "{[ r 'with' 'nextPC' := e ]}" := {| nextPC := e; Xs := Xs r; PC := PC r |}.
+Notation "{[ r 'with' 'PC' := e ]}" := {| PC := e; Xs := Xs r; nextPC := nextPC r |}.
+
+
+
+Definition bit_of_regval (merge_var : register_value)
+: option bitU :=
+
+ match merge_var with | Regval_bit (v) => Some (v) | _ => None end.
+
+Definition regval_of_bit (v : bitU) : register_value := Regval_bit (v).
+
+Definition bitvector_64_dec_of_regval (merge_var : register_value)
+: option (mword 64) :=
+
+ match merge_var with | Regval_bitvector_64_dec (v) => Some (v) | _ => None end.
+
+Definition regval_of_bitvector_64_dec (v : mword 64)
+: register_value :=
+
+ Regval_bitvector_64_dec
+ (v).
+
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with
+ | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None
+ | _ => None
+end.
+
+Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with
+ | Regval_list v => just_list (List.map of_regval v)
+ | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with
+ | Regval_option v => option_map of_regval v
+ | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition Xs_ref := {|
+ name := "Xs";
+ read_from := (fun s => s.(Xs));
+ write_to := (fun v s => ({[ s with Xs := v ]}));
+ of_regval := (fun v => vector_of_regval 32 (fun v => bitvector_64_dec_of_regval v) v);
+ regval_of := (fun v => regval_of_vector (fun v => regval_of_bitvector_64_dec v) 32 false v) |}.
+
+Definition nextPC_ref := {|
+ name := "nextPC";
+ read_from := (fun s => s.(nextPC));
+ write_to := (fun v s => ({[ s with nextPC := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Definition PC_ref := {|
+ name := "PC";
+ read_from := (fun s => s.(PC));
+ write_to := (fun v s => ({[ s with PC := v ]}));
+ of_regval := (fun v => bitvector_64_dec_of_regval v);
+ regval_of := (fun v => regval_of_bitvector_64_dec v) |}.
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+ if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else
+ if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+ if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+ None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+ if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else
+ if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+ if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+ None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r unit.
+Definition M a := monad register_value a unit.
diff --git a/prover_snapshots/coq/duopod/riscv_extras.v b/prover_snapshots/coq/duopod/riscv_extras.v
new file mode 100644
index 0000000..84f6761
--- /dev/null
+++ b/prover_snapshots/coq/duopod/riscv_extras.v
@@ -0,0 +1,155 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import String.
+Require Import List.
+Import List.ListNotations.
+
+Axiom real : Type.
+
+Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_rw tt).
+Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_rw tt).
+Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_r tt).
+Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_w tt).
+Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_w tt).
+Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_rw tt).
+Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_rw_r tt).
+Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_r_w tt).
+Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_w_r tt).
+Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_tso tt).
+Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier (Barrier_RISCV_i tt).
+(*
+val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e
+*)
+Definition MEMea {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addrsize addr size.
+Definition MEMea_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addrsize addr size.
+Definition MEMea_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addrsize addr size.
+Definition MEMea_conditional {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addrsize addr size.
+Definition MEMea_conditional_release {rv a e} addrsize (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addrsize addr size.
+Definition MEMea_conditional_strong_release {rv a e} addrsize (addr : mword a) size : monad rv unit e
+ := write_mem_ea Write_RISCV_conditional_strong_release addrsize addr size.
+
+(*
+val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e
+*)
+
+Definition MEMr {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_plain addrsize addr size.
+Definition MEMr_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_acquire addrsize addr size.
+Definition MEMr_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_strong_acquire addrsize addr size.
+Definition MEMr_reserved {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved addrsize addr size.
+Definition MEMr_reserved_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_acquire addrsize addr size.
+Definition MEMr_reserved_strong_acquire {rv e} addrsize size (hexRAM addr : mword addrsize) `{ArithFact (size >= 0)} : monad rv (mword (8 * size)) e := read_mem Read_RISCV_reserved_strong_acquire addrsize addr size.
+
+(*
+val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e
+*)
+
+Definition MEMw {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_plain addrsize addr size v.
+Definition MEMw_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_release addrsize addr size v.
+Definition MEMw_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_strong_release addrsize addr size v.
+Definition MEMw_conditional {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional addrsize addr size v.
+Definition MEMw_conditional_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_release addrsize addr size v.
+Definition MEMw_conditional_strong_release {rv e} addrsize size (hexRAM addr : mword addrsize) (v : mword (8 * size)) : monad rv bool e := write_mem Write_RISCV_conditional_strong_release addrsize addr size v.
+
+Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftl v (int_of_mword false n).
+
+Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a :=
+ shiftr v (int_of_mword false n).
+
+Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a :=
+ arith_shiftr v (int_of_mword false n).
+
+(* Use constants for undefined values for now *)
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) : Z := 0.
+(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*)
+
+Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)).
+
+(*val get_time_ns : unit -> integer*)
+Definition get_time_ns (_:unit) : Z := 0.
+(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*)
+
+Definition eq_bit (x : bitU) (y : bitU) : bool :=
+ match x, y with
+ | B0, B0 => true
+ | B1, B1 => true
+ | BU, BU => true
+ | _,_ => false
+ end.
+
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+apply existT with (x := ZEuclid.modulo m n).
+constructor.
+destruct H.
+assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
+(* Override the more general version *)
+
+Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
+Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
+
+Axiom sys_enable_writable_misa : unit -> bool.
+Axiom sys_enable_rvc : unit -> bool.
+
+(* The constraint solver can do this itself, but a Coq bug puts
+ anonymous_subproof into the term instead of an actual subproof. *)
+Lemma n_leading_spaces_fact {w__0} :
+ w__0 >= 0 -> exists ex17629_ : Z, 1 + w__0 = 1 + ex17629_ /\ 0 <= ex17629_.
+intro.
+exists w__0.
+omega.
+Qed.
+Hint Resolve n_leading_spaces_fact : sail.
diff --git a/prover_snapshots/coq/lib/sail/Hoare.v b/prover_snapshots/coq/lib/sail/Hoare.v
new file mode 100644
index 0000000..d23ff32
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Hoare.v
@@ -0,0 +1,810 @@
+Require Import String ZArith.
+Require Import Sail2_state_monad Sail2_prompt Sail2_state Sail2_state_monad_lemmas.
+Require Import Sail2_state_lemmas.
+
+(*adhoc_overloading
+ Monad_Syntax.bind State_monad.bindS*)
+
+(*section \<open>Hoare logic for the state, exception and nondeterminism monad\<close>
+
+subsection \<open>Hoare triples\<close>
+*)
+Definition predS regs := sequential_state regs -> Prop.
+
+Definition PrePost {Regs A E} (P : predS Regs) (f : monadS Regs A E) (Q : result A E -> predS Regs) : Prop :=
+ (*"\<lbrace>_\<rbrace> _ \<lbrace>_\<rbrace>"*)
+ forall s, P s -> (forall r s', List.In (r, s') (f s) -> Q r s').
+
+Notation "{{ P }} m {{ Q }}" := (PrePost P m Q).
+
+(*
+lemma PrePostI:
+ assumes "\<And>s r s'. P s \<Longrightarrow> (r, s') \<in> f s \<Longrightarrow> Q r s'"
+ shows "PrePost P f Q"
+ using assms unfolding PrePost_def by auto
+
+lemma PrePost_elim:
+ assumes "PrePost P f Q" and "P s" and "(r, s') \<in> f s"
+ obtains "Q r s'"
+ using assms by (fastforce simp: PrePost_def)
+*)
+Lemma PrePost_consequence Regs X E (A P : predS Regs) (f : monadS Regs X E) (B Q : result X E -> predS Regs) :
+ PrePost A f B ->
+ (forall s, P s -> A s) ->
+ (forall v s, B v s -> Q v s) ->
+ PrePost P f Q.
+intros Triple PA BQ.
+intros s Pre r s' IN.
+specialize (Triple s).
+auto.
+Qed.
+
+Lemma PrePost_strengthen_pre Regs X E (A B : predS Regs) (f : monadS Regs X E) (C : result X E -> predS Regs) :
+ PrePost A f C ->
+ (forall s, B s -> A s) ->
+ PrePost B f C.
+eauto using PrePost_consequence.
+Qed.
+
+Lemma PrePost_weaken_post Regs X E (A : predS Regs) (f : monadS Regs X E) (B C : result X E -> predS Regs) :
+ PrePost A f B ->
+ (forall v s, B v s -> C v s) ->
+ PrePost A f C.
+eauto using PrePost_consequence.
+Qed.
+
+Lemma PrePost_True_post (*[PrePost_atomI, intro, simp]:*) Regs A E (P : predS Regs) (m : monadS Regs A E) :
+ PrePost P m (fun _ _ => True).
+unfold PrePost. auto.
+Qed.
+
+Lemma PrePost_any Regs A E (m : monadS Regs A E) (Q : result A E -> predS Regs) :
+ PrePost (fun s => forall r s', List.In (r, s') (m s) -> Q r s') m Q.
+unfold PrePost. auto.
+Qed.
+
+Lemma PrePost_returnS (*[intro, PrePost_atomI]:*) Regs A E (P : result A E -> predS Regs) (x : A) :
+ PrePost (P (Value x)) (returnS x) P.
+unfold PrePost, returnS.
+intros s p r s' IN.
+simpl in IN.
+destruct IN as [[=] | []].
+subst; auto.
+Qed.
+
+Lemma PrePost_bindS (*[intro, PrePost_compositeI]:*) Regs A B E (m : monadS Regs A E) (f : A -> monadS Regs B E) (P : predS Regs) (Q : result B E -> predS Regs) (R : A -> predS Regs) :
+ (forall s a s', List.In (Value a, s') (m s) -> PrePost (R a) (f a) Q) ->
+ (PrePost P m (fun r => match r with Value a => R a | Ex e => Q (Ex e) end)) ->
+ PrePost P (bindS m f) Q.
+intros F M s Pre r s' IN.
+destruct (bindS_cases IN) as [(a & a' & s'' & [= ->] & IN' & IN'') | [(e & [= ->] & IN') | (e & a & s'' & [= ->] & IN' & IN'')]].
+* eapply F. apply IN'. specialize (M s Pre (Value a') s'' IN'). apply M. assumption.
+* specialize (M _ Pre _ _ IN'). apply M.
+* specialize (M _ Pre _ _ IN'). simpl in M. eapply F; eauto.
+Qed.
+
+Lemma PrePost_bindS_ignore Regs A B E (m : monadS Regs A E) (f : monadS Regs B E) (P : predS Regs) (Q : result B E -> predS Regs) (R : predS Regs) :
+ PrePost R f Q ->
+ PrePost P m (fun r => match r with Value a => R | Ex e => Q (Ex e) end) ->
+ PrePost P (bindS m (fun _ => f)) Q.
+intros F M.
+eapply PrePost_bindS; eauto.
+* intros. apply F.
+* apply M.
+Qed.
+
+Lemma PrePost_bindS_unit Regs B E (m : monadS Regs unit E) (f : unit -> monadS Regs B E) P Q R :
+ PrePost R (f tt) Q ->
+ PrePost P m (fun r => match r with Value a => R | Ex e => Q (Ex e) end) ->
+ PrePost P (bindS m f) Q.
+intros F M.
+eapply PrePost_bindS with (R := fun _ => R).
+* intros. destruct a. apply F.
+* apply M.
+Qed.
+
+Lemma PrePost_readS (*[intro, PrePost_atomI]:*) Regs A E (P : result A E -> predS Regs) f :
+ PrePost (fun s => P (Value (f s)) s) (readS f) P.
+unfold PrePost, readS, returnS.
+intros s Pre r s' [H | []].
+inversion H; subst.
+assumption.
+Qed.
+
+Lemma PrePost_updateS (*[intro, PrePost_atomI]:*) Regs E (P : result unit E -> predS Regs) f :
+ PrePost (fun s => P (Value tt) (f s)) (updateS f) P.
+unfold PrePost, readS, returnS.
+intros s Pre r s' [H | []].
+inversion H; subst.
+assumption.
+Qed.
+
+Lemma PrePost_if Regs A E b (f g : monadS Regs A E) P Q :
+ (b = true -> PrePost P f Q) ->
+ (b = false -> PrePost P g Q) ->
+ PrePost P (if b then f else g) Q.
+intros T F.
+destruct b; auto.
+Qed.
+
+Lemma PrePost_if_branch (*[PrePost_compositeI]:*) Regs A E b (f g : monadS Regs A E) Pf Pg Q :
+ (b = true -> PrePost Pf f Q) ->
+ (b = false -> PrePost Pg g Q) ->
+ PrePost (if b then Pf else Pg) (if b then f else g) Q.
+destruct b; auto.
+Qed.
+
+Lemma PrePost_if_then Regs A E b (f g : monadS Regs A E) P Q :
+ b = true ->
+ PrePost P f Q ->
+ PrePost P (if b then f else g) Q.
+intros; subst; auto.
+Qed.
+
+Lemma PrePost_if_else Regs A E b (f g : monadS Regs A E) P Q :
+ b = false ->
+ PrePost P g Q ->
+ PrePost P (if b then f else g) Q.
+intros; subst; auto.
+Qed.
+
+Lemma PrePost_prod_cases (*[PrePost_compositeI]:*) Regs A B E (f : A -> B -> monadS Regs A E) P Q x :
+ PrePost P (f (fst x) (snd x)) Q ->
+ PrePost P (match x with (a, b) => f a b end) Q.
+destruct x; auto.
+Qed.
+
+Lemma PrePost_option_cases (*[PrePost_compositeI]:*) Regs A B E x (s : A -> monadS Regs B E) n PS PN Q :
+ (forall a, PrePost (PS a) (s a) Q) ->
+ PrePost PN n Q ->
+ PrePost (match x with Some a => PS a | None => PN end) (match x with Some a => s a | None => n end) Q.
+destruct x; auto.
+Qed.
+
+Lemma PrePost_let (*[intro, PrePost_compositeI]:*) Regs A B E y (m : A -> monadS Regs B E) P Q :
+ PrePost P (m y) Q ->
+ PrePost P (let x := y in m x) Q.
+auto.
+Qed.
+
+Lemma PrePost_and_boolS (*[PrePost_compositeI]:*) Regs E (l r : monadS Regs bool E) P Q R :
+ PrePost R r Q ->
+ PrePost P l (fun r => match r with Value true => R | _ => Q r end) ->
+ PrePost P (and_boolS l r) Q.
+intros Hr Hl.
+unfold and_boolS.
+eapply PrePost_bindS.
+2: { instantiate (1 := fun a => if a then R else Q (Value false)).
+ eapply PrePost_weaken_post.
+ apply Hl.
+ intros [[|] | ] s H; auto. }
+* intros. destruct a; eauto.
+ apply PrePost_returnS.
+Qed.
+
+Lemma PrePost_or_boolS (*[PrePost_compositeI]:*) Regs E (l r : monadS Regs bool E) P Q R :
+ PrePost R r Q ->
+ PrePost P l (fun r => match r with Value false => R | _ => Q r end) ->
+ PrePost P (or_boolS l r) Q.
+intros Hr Hl.
+unfold or_boolS.
+eapply PrePost_bindS.
+* intros.
+ instantiate (1 := fun a => if a then Q (Value true) else R).
+ destruct a; eauto.
+ apply PrePost_returnS.
+* eapply PrePost_weaken_post.
+ apply Hl.
+ intros [[|] | ] s H; auto.
+Qed.
+
+Lemma PrePost_failS (*[intro, PrePost_atomI]:*) Regs A E msg (Q : result A E -> predS Regs) :
+ PrePost (Q (Ex (Failure msg))) (failS msg) Q.
+intros s Pre r s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePost_assert_expS (*[intro, PrePost_atomI]:*) Regs E (c : bool) m (P : result unit E -> predS Regs) :
+ PrePost (if c then P (Value tt) else P (Ex (Failure m))) (assert_expS c m) P.
+destruct c; simpl.
+* apply PrePost_returnS.
+* apply PrePost_failS.
+Qed.
+
+Lemma PrePost_chooseS (*[intro, PrePost_atomI]:*) Regs A E xs (Q : result A E -> predS Regs) :
+ PrePost (fun s => forall x, List.In x xs -> Q (Value x) s) (chooseS xs) Q.
+unfold PrePost, chooseS.
+intros s IN r s' IN'.
+apply List.in_map_iff in IN'.
+destruct IN' as (x & [= <- <-] & IN').
+auto.
+Qed.
+
+Lemma case_result_combine (*[simp]:*) A E X r (Q : result A E -> X) :
+ (match r with Value a => Q (Value a) | Ex e => Q (Ex e) end) = Q r.
+destruct r; auto.
+Qed.
+
+Lemma PrePost_foreachS_Nil (*[intro, simp, PrePost_atomI]:*) Regs A Vars E vars body (Q : result Vars E -> predS Regs) :
+ PrePost (Q (Value vars)) (foreachS (A := A) nil vars body) Q.
+simpl. apply PrePost_returnS.
+Qed.
+
+Lemma PrePost_foreachS_Cons Regs A Vars E (x : A) xs vars body (Q : result Vars E -> predS Regs) :
+ (forall s vars' s', List.In (Value vars', s') (body x vars s) -> PrePost (Q (Value vars')) (foreachS xs vars' body) Q) ->
+ PrePost (Q (Value vars)) (body x vars) Q ->
+ PrePost (Q (Value vars)) (foreachS (x :: xs) vars body) Q.
+intros XS X.
+simpl.
+eapply PrePost_bindS.
+* apply XS.
+* apply PrePost_weaken_post with (B := Q).
+ assumption.
+ intros; rewrite case_result_combine.
+ assumption.
+Qed.
+
+Lemma PrePost_foreachS_invariant Regs A Vars E (xs : list A) vars body (Q : result Vars E -> predS Regs) :
+ (forall x vars, List.In x xs -> PrePost (Q (Value vars)) (body x vars) Q) ->
+ PrePost (Q (Value vars)) (foreachS xs vars body) Q.
+revert vars.
+induction xs.
+* intros. apply PrePost_foreachS_Nil.
+* intros. apply PrePost_foreachS_Cons.
+ + auto with datatypes.
+ + apply H. auto with datatypes.
+Qed.
+
+(*subsection \<open>Hoare quadruples\<close>
+
+text \<open>It is often convenient to treat the exception case separately. For this purpose, we use
+a Hoare logic similar to the one used in [1]. It features not only Hoare triples, but also quadruples
+with two postconditions: one for the case where the computation succeeds, and one for the case where
+there is an exception.
+
+[1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’,
+in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close>
+*)
+Definition PrePostE {Regs A Ety} (P : predS Regs) (f : monadS Regs A Ety) (Q : A -> predS Regs) (E : ex Ety -> predS Regs) : Prop :=
+(* ("\<lbrace>_\<rbrace> _ \<lbrace>_ \<bar> _\<rbrace>")*)
+ PrePost P f (fun v => match v with Value a => Q a | Ex e => E e end).
+
+Notation "{{ P }} m {{ Q | X }}" := (PrePostE P m Q X).
+
+(*lemmas PrePost_defs = PrePost_def PrePostE_def*)
+
+Lemma PrePostE_I (*[case_names Val Err]:*) Regs A Ety (P : predS Regs) f (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ (forall s a s', P s -> List.In (Value a, s') (f s) -> Q a s') ->
+ (forall s e s', P s -> List.In (Ex e, s') (f s) -> E e s') ->
+ PrePostE P f Q E.
+intros. unfold PrePostE.
+unfold PrePost.
+intros s Pre [a | e] s' IN; eauto.
+Qed.
+
+Lemma PrePostE_PrePost Regs A Ety P m (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePost P m (fun v => match v with Value a => Q a | Ex e => E e end) ->
+ PrePostE P m Q E.
+auto.
+Qed.
+
+Lemma PrePostE_elim Regs A Ety P f r s s' (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE P f Q E ->
+ P s ->
+ List.In (r, s') (f s) ->
+ (exists v, r = Value v /\ Q v s') \/
+ (exists e, r = Ex e /\ E e s').
+intros PP Pre IN.
+specialize (PP _ Pre _ _ IN).
+destruct r; eauto.
+Qed.
+
+Lemma PrePostE_consequence Regs Aty Ety (P : predS Regs) f A B C (Q : Aty -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE A f B C ->
+ (forall s, P s -> A s) ->
+ (forall v s, B v s -> Q v s) ->
+ (forall e s, C e s -> E e s) ->
+ PrePostE P f Q E.
+intros PP PA BQ CE.
+intros s Pre [a | e] s' IN.
+* apply BQ. specialize (PP _ (PA _ Pre) _ _ IN).
+ apply PP.
+* apply CE. specialize (PP _ (PA _ Pre) _ _ IN).
+ apply PP.
+Qed.
+
+Lemma PrePostE_strengthen_pre Regs Aty Ety (P : predS Regs) f R (Q : Aty -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE R f Q E ->
+ (forall s, P s -> R s) ->
+ PrePostE P f Q E.
+intros PP PR.
+eapply PrePostE_consequence; eauto.
+Qed.
+
+Lemma PrePostE_weaken_post Regs Aty Ety (A : predS Regs) f (B C : Aty -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE A f B E ->
+ (forall v s, B v s -> C v s) ->
+ PrePostE A f C E.
+intros PP BC.
+eauto using PrePostE_consequence.
+Qed.
+
+Lemma PrePostE_weaken_Epost Regs Aty Ety (A : predS Regs) f (B : Aty -> predS Regs) (E F : ex Ety -> predS Regs) :
+ PrePostE A f B E ->
+ (forall v s, E v s -> F v s) ->
+ PrePostE A f B F.
+intros PP EF.
+eauto using PrePostE_consequence.
+Qed.
+(*named_theorems PrePostE_compositeI
+named_theorems PrePostE_atomI*)
+
+Lemma PrePostE_conj_conds Regs Aty Ety (P1 P2 : predS Regs) m (Q1 Q2 : Aty -> predS Regs) (E1 E2 : ex Ety -> predS Regs) :
+ PrePostE P1 m Q1 E1 ->
+ PrePostE P2 m Q2 E2 ->
+ PrePostE (fun s => P1 s /\ P2 s) m (fun r s => Q1 r s /\ Q2 r s) (fun e s => E1 e s /\ E2 e s).
+intros H1 H2.
+apply PrePostE_I.
+* intros s a s' [p1 p2] IN.
+ specialize (H1 _ p1 _ _ IN).
+ specialize (H2 _ p2 _ _ IN).
+ simpl in *.
+ auto.
+* intros s a s' [p1 p2] IN.
+ specialize (H1 _ p1 _ _ IN).
+ specialize (H2 _ p2 _ _ IN).
+ simpl in *.
+ auto.
+Qed.
+
+(*lemmas PrePostE_conj_conds_consequence = PrePostE_conj_conds[THEN PrePostE_consequence]*)
+
+Lemma PrePostE_post_mp Regs Aty Ety (P : predS Regs) m (Q Q' : Aty -> predS Regs) (E: ex Ety -> predS Regs) :
+ PrePostE P m Q' E ->
+ PrePostE P m (fun r s => Q' r s -> Q r s) E ->
+ PrePostE P m Q E.
+intros H1 H2.
+eapply PrePostE_conj_conds in H1. 2: apply H2.
+eapply PrePostE_consequence. apply H1. all: simpl; intuition.
+Qed.
+
+Lemma PrePostE_cong Regs Aty Ety (P1 P2 : predS Regs) m1 m2 (Q1 Q2 : Aty -> predS Regs) (E1 E2 : ex Ety -> predS Regs) :
+ (forall s, P1 s <-> P2 s) ->
+ (forall s, P1 s -> m1 s = m2 s) ->
+ (forall r s, Q1 r s <-> Q2 r s) ->
+ (forall e s, E1 e s <-> E2 e s) ->
+ PrePostE P1 m1 Q1 E1 <-> PrePostE P2 m2 Q2 E2.
+intros P12 m12 Q12 E12.
+unfold PrePostE, PrePost.
+split.
+* intros. apply P12 in H0. rewrite <- m12 in H1; auto. specialize (H _ H0 _ _ H1).
+ destruct r; [ apply Q12 | apply E12]; auto.
+* intros. rewrite m12 in H1; auto. apply P12 in H0. specialize (H _ H0 _ _ H1).
+ destruct r; [ apply Q12 | apply E12]; auto.
+Qed.
+
+Lemma PrePostE_True_post (*[PrePostE_atomI, intro, simp]:*) Regs A E P (m : monadS Regs A E) :
+ PrePostE P m (fun _ _ => True) (fun _ _ => True).
+intros s Pre [a | e]; auto.
+Qed.
+
+Lemma PrePostE_any Regs A Ety m (Q : result A Ety -> predS Regs) E :
+ PrePostE (Ety := Ety) (fun s => forall r s', List.In (r, s') (m s) -> match r with Value a => Q a s' | Ex e => E e s' end) m Q E.
+apply PrePostE_I.
+intros. apply (H (Value a)); auto.
+intros. apply (H (Ex e)); auto.
+Qed.
+
+Lemma PrePostE_returnS (*[PrePostE_atomI, intro, simp]:*) Regs A E P (x : A) (Q : ex E -> predS Regs) :
+ PrePostE (P x) (returnS x) P Q.
+unfold PrePostE, PrePost.
+intros s Pre r s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePostE_bindS (*[intro, PrePostE_compositeI]:*) Regs A B Ety P m (f : A -> monadS Regs B Ety) Q R E :
+ (forall s a s', List.In (Value a, s') (m s) -> PrePostE (R a) (f a) Q E) ->
+ PrePostE P m R E ->
+ PrePostE P (bindS m f) Q E.
+intros.
+unfold PrePostE in *.
+eauto using PrePost_bindS.
+Qed.
+
+Lemma PrePostE_bindS_ignore Regs A B Ety (P : predS Regs) (m : monadS Regs A Ety) (f : monadS Regs B Ety) R Q E :
+ PrePostE R f Q E ->
+ PrePostE P m (fun _ => R) E ->
+ PrePostE P (bindS m (fun _ => f)) Q E.
+apply PrePost_bindS_ignore.
+Qed.
+
+Lemma PrePostE_bindS_unit Regs A Ety (P : predS Regs) (m : monadS Regs unit Ety) (f : unit -> monadS Regs A Ety) Q R E :
+ PrePostE R (f tt) Q E ->
+ PrePostE P m (fun _ => R) E ->
+ PrePostE P (bindS m f) Q E.
+apply PrePost_bindS_unit.
+Qed.
+
+Lemma PrePostE_readS (*[PrePostE_atomI, intro]:*) Regs A Ety (P : predS Regs) f (Q : result A Ety -> predS Regs) E :
+ PrePostE (Ety := Ety) (fun s => Q (f s) s) (readS f) Q E.
+unfold PrePostE, PrePost, readS.
+intros s Pre [a | e] s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePostE_updateS (*[PrePostE_atomI, intro]:*) Regs Ety f (Q : unit -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => Q tt (f s)) (updateS f) Q E.
+intros s Pre [a | e] s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePostE_if_branch (*[PrePostE_compositeI]:*) Regs A Ety (b : bool) (f g : monadS Regs A Ety) Pf Pg Q E :
+ (b = true -> PrePostE Pf f Q E) ->
+ (b = false -> PrePostE Pg g Q E) ->
+ PrePostE (if b then Pf else Pg) (if b then f else g) Q E.
+destruct b; auto.
+Qed.
+
+Lemma PrePostE_if Regs A Ety (b : bool) (f g : monadS Regs A Ety) P Q E :
+ (b = true -> PrePostE P f Q E) ->
+ (b = false -> PrePostE P g Q E) ->
+ PrePostE P (if b then f else g) Q E.
+destruct b; auto.
+Qed.
+
+Lemma PrePostE_if_then Regs A Ety (b : bool) (f g : monadS Regs A Ety) P Q E :
+ b = true ->
+ PrePostE P f Q E ->
+ PrePostE P (if b then f else g) Q E.
+intros; subst; auto.
+Qed.
+
+Lemma PrePostE_if_else Regs A Ety (b : bool) (f g : monadS Regs A Ety) P Q E :
+ b = false ->
+ PrePostE P g Q E ->
+ PrePostE P (if b then f else g) Q E.
+intros; subst; auto.
+Qed.
+
+Lemma PrePostE_prod_cases (*[PrePostE_compositeI]:*) Regs A B C Ety x (f : A -> B -> monadS Regs C Ety) P Q E :
+ PrePostE P (f (fst x) (snd x)) Q E ->
+ PrePostE P (match x with (a, b) => f a b end) Q E.
+destruct x; auto.
+Qed.
+
+Lemma PrePostE_option_cases (*[PrePostE_compositeI]:*) Regs A B Ety x (s : option A -> monadS Regs B Ety) n PS PN Q E :
+ (forall a, PrePostE (PS a) (s a) Q E) ->
+ PrePostE PN n Q E ->
+ PrePostE (match x with Some a => PS a | None => PN end) (match x with Some a => s a | None => n end) Q E.
+apply PrePost_option_cases.
+Qed.
+
+Lemma PrePostE_sum_cases (*[PrePostE_compositeI]:*) Regs A B C Ety x (l : A -> monadS Regs C Ety) (r : B -> monadS Regs C Ety) Pl Pr Q E :
+ (forall a, PrePostE (Pl a) (l a) Q E) ->
+ (forall b, PrePostE (Pr b) (r b) Q E) ->
+ PrePostE (match x with inl a => Pl a | inr b => Pr b end) (match x with inl a => l a | inr b => r b end) Q E.
+intros; destruct x; auto.
+Qed.
+
+Lemma PrePostE_let (*[PrePostE_compositeI]:*) Regs A B Ety y (m : A -> monadS Regs B Ety) P Q E :
+ PrePostE P (m y) Q E ->
+ PrePostE P (let x := y in m x) Q E.
+auto.
+Qed.
+
+Lemma PrePostE_and_boolS (*[PrePostE_compositeI]:*) Regs Ety (l r : monadS Regs bool Ety) P Q R E :
+ PrePostE R r Q E ->
+ PrePostE P l (fun r => if r then R else Q false) E ->
+ PrePostE P (and_boolS l r) Q E.
+intros Hr Hl.
+unfold and_boolS.
+eapply PrePostE_bindS.
+* intros.
+ instantiate (1 := fun a => if a then R else Q false).
+ destruct a; eauto.
+ apply PrePostE_returnS.
+* assumption.
+Qed.
+
+Lemma PrePostE_or_boolS (*[PrePostE_compositeI]:*) Regs Ety (l r : monadS Regs bool Ety) P Q R E :
+ PrePostE R r Q E ->
+ PrePostE P l (fun r => if r then Q true else R) E ->
+ PrePostE P (or_boolS l r) Q E.
+intros Hr Hl.
+unfold or_boolS.
+eapply PrePostE_bindS.
+* intros.
+ instantiate (1 := fun a => if a then Q true else R).
+ destruct a; eauto.
+ apply PrePostE_returnS.
+* assumption.
+Qed.
+
+Lemma PrePostE_failS (*[PrePostE_atomI, intro]:*) Regs A Ety msg (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (E (Failure msg)) (failS msg) Q E.
+unfold PrePostE, PrePost, failS.
+intros s Pre r s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePostE_assert_expS (*[PrePostE_atomI, intro]:*) Regs Ety (c : bool) m P (Q : ex Ety -> predS Regs) :
+ PrePostE (if c then P tt else Q (Failure m)) (assert_expS c m) P Q.
+unfold assert_expS.
+destruct c; auto using PrePostE_returnS, PrePostE_failS.
+Qed.
+
+Lemma PrePostE_maybe_failS (*[PrePostE_atomI]:*) Regs A Ety msg v (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => match v with Some v => Q v s | None => E (Failure msg) s end) (maybe_failS msg v) Q E.
+unfold maybe_failS.
+destruct v; auto using PrePostE_returnS, PrePostE_failS.
+Qed.
+
+Lemma PrePostE_exitS (*[PrePostE_atomI, intro]:*) Regs A Ety msg (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (E (Failure "exit")) (exitS msg) Q E.
+unfold exitS.
+apply PrePostE_failS.
+Qed.
+
+Lemma PrePostE_chooseS (*[intro, PrePostE_atomI]:*) Regs A Ety (xs : list A) (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => forall x, List.In x xs -> Q x s) (chooseS xs) Q E.
+unfold chooseS.
+intros s IN r s' IN'.
+apply List.in_map_iff in IN'.
+destruct IN' as (x & [= <- <-] & IN').
+auto.
+Qed.
+
+Lemma PrePostE_throwS (*[PrePostE_atomI]:*) Regs A Ety e (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (E (Throw e)) (throwS e) Q E.
+unfold throwS.
+intros s Pre r s' [[= <- <-] | []].
+assumption.
+Qed.
+
+Lemma PrePostE_try_catchS (*[PrePostE_compositeI]:*) Regs A E1 E2 m h P (Ph : E1 -> predS Regs) (Q : A -> predS Regs) (E : ex E2 -> predS Regs) :
+ (forall s e s', List.In (Ex (Throw e), s') (m s) -> PrePostE (Ph e) (h e) Q E) ->
+ PrePostE P m Q (fun ex => match ex with Throw e => Ph e | Failure msg => E (Failure msg) end) ->
+ PrePostE P (try_catchS m h) Q E.
+intros.
+intros s Pre r s' IN.
+destruct (try_catchS_cases IN) as [(a' & [= ->] & IN') | [(msg & [= ->] & IN') | (e & s'' & IN1 & IN2)]].
+* specialize (H0 _ Pre _ _ IN'). apply H0.
+* specialize (H0 _ Pre _ _ IN'). apply H0.
+* specialize (H _ _ _ IN1). specialize (H0 _ Pre _ _ IN1). simpl in *.
+ specialize (H _ H0 _ _ IN2). apply H.
+Qed.
+
+Lemma PrePostE_catch_early_returnS (*[PrePostE_compositeI]:*) Regs A Ety m P (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE P m Q (fun ex => match ex with Throw (inl a) => Q a | Throw (inr e) => E (Throw e) | Failure msg => E (Failure msg) end) ->
+ PrePostE P (catch_early_returnS m) Q E.
+unfold catch_early_returnS.
+intro H.
+apply PrePostE_try_catchS with (Ph := fun e => match e with inl a => Q a | inr e => E (Throw e) end).
+* intros. destruct e.
+ + apply PrePostE_returnS.
+ + apply PrePostE_throwS.
+* apply H.
+Qed.
+
+Lemma PrePostE_early_returnS (*[PrePostE_atomI]:*) Regs A E1 E2 r (Q : A -> predS Regs) (E : ex (E1 + E2) -> predS Regs) :
+ PrePostE (E (Throw (inl r))) (early_returnS r) Q E.
+unfold early_returnS.
+apply PrePostE_throwS.
+Qed.
+
+Lemma PrePostE_liftRS (*[PrePostE_compositeI]:*) Regs A E1 E2 m P (Q : A -> predS Regs) (E : ex (E1 + E2) -> predS Regs) :
+ PrePostE P m Q (fun ex => match ex with Throw e => E (Throw (inr e)) | Failure msg => E (Failure msg) end) ->
+ PrePostE P (liftRS m) Q E.
+unfold liftRS.
+apply PrePostE_try_catchS.
+auto using PrePostE_throwS.
+Qed.
+
+Lemma PrePostE_foreachS_Cons Regs A Vars Ety (x : A) xs vars body (Q : Vars -> predS Regs) (E : ex Ety -> predS Regs) :
+ (forall s vars' s', List.In (Value vars', s') (body x vars s) -> PrePostE (Q vars') (foreachS xs vars' body) Q E) ->
+ PrePostE (Q vars) (body x vars) Q E ->
+ PrePostE (Q vars) (foreachS (x :: xs) vars body) Q E.
+intros.
+simpl.
+apply PrePostE_bindS with (R := Q); auto.
+Qed.
+
+Lemma PrePostE_foreachS_invariant Regs A Vars Ety (xs : list A) vars body (Q : Vars -> predS Regs) (E : ex Ety -> predS Regs) :
+ (forall x vars, List.In x xs -> PrePostE (Q vars) (body x vars) Q E) ->
+ PrePostE (Q vars) (foreachS xs vars body) Q E.
+unfold PrePostE.
+intros H.
+apply PrePost_foreachS_invariant with (Q := fun v => match v with Value a => Q a | Ex e => E e end).
+auto.
+Qed.
+
+
+Lemma PrePostE_use_pre Regs A Ety m (P : predS Regs) (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ (forall s, P s -> PrePostE P m Q E) ->
+ PrePostE P m Q E.
+unfold PrePostE, PrePost.
+intros H s p r s' IN.
+eapply H; eauto.
+Qed.
+
+Local Open Scope Z.
+Local Opaque _limit_reduces.
+Ltac gen_reduces :=
+ match goal with |- context[@_limit_reduces ?a ?b ?c] => generalize (@_limit_reduces a b c) end.
+
+
+Lemma PrePostE_untilST Regs Vars Ety vars measure cond (body : Vars -> monadS Regs Vars Ety) Inv Inv' (Q : Vars -> predS Regs) E :
+ (forall vars, PrePostE (Inv' Q vars) (cond vars) (fun c s' => Inv Q vars s' /\ (c = true -> Q vars s')) E) ->
+ (forall vars, PrePostE (Inv Q vars) (body vars) (fun vars' s' => Inv' Q vars' s' /\ measure vars' < measure vars) E) ->
+ (forall vars s, Inv Q vars s -> measure vars >= 0) ->
+ PrePostE (Inv Q vars) (untilST vars measure cond body) Q E.
+
+intros Hcond Hbody Hmeasure.
+unfold untilST.
+apply PrePostE_use_pre. intros s0 Pre0.
+assert (measure vars >= 0) as Hlimit_0 by eauto. clear s0 Pre0.
+remember (measure vars) as limit eqn: Heqlimit in Hlimit_0 |- *.
+assert (measure vars <= limit) as Hlimit by omega. clear Heqlimit.
+generalize (Sail2_prompt.Zwf_guarded limit).
+revert vars Hlimit.
+apply Wf_Z.natlike_ind with (x := limit).
+* intros vars Hmeasure_limit [acc]. simpl.
+ eapply PrePostE_bindS; [ | apply Hbody ].
+ intros s vars' s' IN.
+ eapply PrePostE_bindS with (R := (fun c s' => (Inv Q vars' s' /\ (c = true -> Q vars' s')) /\ measure vars' < measure vars)).
+ 2: {
+ apply PrePostE_weaken_Epost with (E := (fun e s' => E e s' /\ measure vars' < measure vars)). 2: tauto.
+ eapply PrePostE_conj_conds.
+ apply Hcond.
+ apply PrePostE_I; tauto.
+ }
+ intros.
+ destruct a.
+ - eapply PrePostE_strengthen_pre; try apply PrePostE_returnS.
+ intros ? [[? ?] ?]; auto.
+ - apply PrePostE_I;
+ intros ? ? ? [[Pre ?] ?] ?; exfalso;
+ specialize (Hmeasure _ _ Pre); omega.
+* intros limit' Hlimit' IH vars Hmeasure_limit [acc].
+ simpl.
+ destruct (Z_ge_dec _ _); try omega.
+ eapply PrePostE_bindS; [ | apply Hbody].
+ intros s vars' s' IN.
+ eapply PrePostE_bindS with (R := (fun c s' => (Inv Q vars' s' /\ (c = true -> Q vars' s')) /\ measure vars' < measure vars)).
+ 2: {
+ apply PrePostE_weaken_Epost with (E := (fun e s' => E e s' /\ measure vars' < measure vars)). 2: tauto.
+ eapply PrePostE_conj_conds.
+ apply Hcond.
+ apply PrePostE_I; tauto.
+ }
+ intros.
+ destruct a.
+ - eapply PrePostE_strengthen_pre; try apply PrePostE_returnS.
+ intros ? [[? ?] ?]; auto.
+ - gen_reduces.
+ replace (Z.succ limit' - 1) with limit'; [ | omega].
+ intro acc'.
+ apply PrePostE_use_pre. intros sx [[Pre _] Hreduces].
+ apply Hmeasure in Pre.
+ eapply PrePostE_strengthen_pre; [apply IH | ].
+ + omega.
+ + tauto.
+* omega.
+Qed.
+
+
+Lemma PrePostE_untilST_pure_cond Regs Vars Ety vars measure cond (body : Vars -> monadS Regs Vars Ety) Inv (Q : Vars -> predS Regs) E :
+ (forall vars, PrePostE (Inv Q vars) (body vars) (fun vars' s' => Inv Q vars' s' /\ measure vars' < measure vars /\ (cond vars' = true -> Q vars' s')) E) ->
+ (forall vars s, Inv Q vars s -> measure vars >= 0) ->
+ (PrePostE (Inv Q vars) (untilST vars measure (fun vars => returnS (cond vars)) body) Q E).
+intros Hbody Hmeasure.
+apply PrePostE_untilST with (Inv' := fun Q vars s => Inv Q vars s /\ (cond vars = true -> Q vars s)).
+* intro.
+ apply PrePostE_returnS with (P := fun c s' => Inv Q vars0 s' /\ (c = true -> Q vars0 s')).
+* intro.
+ eapply PrePost_weaken_post; [ apply Hbody | ].
+ simpl. intros [a |e]; eauto. tauto.
+* apply Hmeasure.
+Qed.
+
+Local Close Scope Z.
+
+(*
+lemma PrePostE_liftState_untilM:
+ assumes dom: (forall s, Inv Q vars s -> untilM_dom (vars, cond, body))
+ and cond: (forall vars, PrePostE (Inv' Q vars) (liftState r (cond vars)) (fun c s' => Inv Q vars s' /\ (c \<longrightarrow> Q vars s')) E)
+ and body: (forall vars, PrePostE (Inv Q vars) (liftState r (body vars)) (Inv' Q) E)
+ shows "PrePostE (Inv Q vars) (liftState r (untilM vars cond body)) Q E"
+proof -
+ have domS: "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" if "Inv Q vars s" for s
+ using dom that by (intro untilM_dom_untilS_dom)
+ then have "PrePostE (Inv Q vars) (untilS vars (liftState r \<circ> cond) (liftState r \<circ> body)) Q E"
+ using cond body by (auto intro: PrePostE_untilS simp: comp_def)
+ moreover have "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+ if "Inv Q vars s" for s
+ unfolding liftState_untilM[OF domS[OF that] dom[OF that]] ..
+ ultimately show ?thesis by (auto cong: PrePostE_cong)
+qed
+
+lemma PrePostE_liftState_untilM_pure_cond:
+ assumes dom: (forall s, Inv Q vars s -> untilM_dom (vars, return \<circ> cond, body)"
+ and body: (forall vars, PrePostE (Inv Q vars) (liftState r (body vars)) (fun vars' s' => Inv Q vars' s' /\ (cond vars' \<longrightarrow> Q vars' s')) E"
+ shows "PrePostE (Inv Q vars) (liftState r (untilM vars (return \<circ> cond) body)) Q E"
+ using assms by (intro PrePostE_liftState_untilM) (auto simp: comp_def liftState_simp)
+*)
+Lemma PrePostE_choose_boolS_any (*[PrePostE_atomI]:*) Regs Ety unit_val (Q : bool -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => forall b, Q b s) (choose_boolS unit_val) Q E.
+unfold choose_boolS, seqS.
+eapply PrePostE_strengthen_pre.
+apply PrePostE_chooseS.
+simpl. intros. destruct x; auto.
+Qed.
+
+Lemma PrePostE_bool_of_bitU_nondetS_any Regs Ety b (Q : bool -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => forall b, Q b s) (bool_of_bitU_nondetS b) Q E.
+unfold bool_of_bitU_nondetS, undefined_boolS.
+destruct b.
+* intros s Pre r s' [[= <- <-] | []]. auto.
+* intros s Pre r s' [[= <- <-] | []]. auto.
+* apply PrePostE_choose_boolS_any.
+Qed.
+(*
+Lemma PrePostE_bools_of_bits_nondetS_any:
+ PrePostE (fun s => forall bs, Q bs s) (bools_of_bits_nondetS bs) Q E.
+ unfolding bools_of_bits_nondetS_def
+ by (rule PrePostE_weaken_post[where B = "fun _ s => forall bs, Q bs s"], rule PrePostE_strengthen_pre,
+ (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS
+ PrePostE_bool_of_bitU_nondetS_any)+)
+ auto
+*)
+Lemma PrePostE_choose_boolsS_any Regs Ety n (Q : list bool -> predS Regs) (E : ex Ety -> predS Regs) :
+ PrePostE (fun s => forall bs, Q bs s) (choose_boolsS n) Q E.
+unfold choose_boolsS, genlistS.
+apply PrePostE_weaken_post with (B := fun _ s => forall bs, Q bs s).
+* apply PrePostE_foreachS_invariant with (Q := fun _ s => forall bs, Q bs s).
+ intros. apply PrePostE_bindS with (R := fun _ s => forall bs, Q bs s).
+ + intros. apply PrePostE_returnS with (P := fun _ s => forall bs, Q bs s).
+ + eapply PrePostE_strengthen_pre.
+ apply PrePostE_choose_boolS_any.
+ intuition.
+* intuition.
+Qed.
+
+Lemma nth_error_exists {A} {l : list A} {n} :
+ n < Datatypes.length l -> exists x, List.In x l /\ List.nth_error l n = Some x.
+revert n. induction l.
+* simpl. intros. apply PeanoNat.Nat.nlt_0_r in H. destruct H.
+* intros. destruct n.
+ + exists a. auto with datatypes.
+ + simpl in H. apply Lt.lt_S_n in H.
+ destruct (IHl n H) as [x H1].
+ intuition eauto with datatypes.
+Qed.
+
+Lemma nth_error_modulo {A} {xs : list A} n :
+ xs <> nil ->
+ exists x, List.In x xs /\ List.nth_error xs (PeanoNat.Nat.modulo n (Datatypes.length xs)) = Some x.
+intro notnil.
+assert (Datatypes.length xs <> 0) by (rewrite List.length_zero_iff_nil; auto).
+assert (PeanoNat.Nat.modulo n (Datatypes.length xs) < Datatypes.length xs) by auto using PeanoNat.Nat.mod_upper_bound.
+destruct (nth_error_exists H0) as [x [H1 H2]].
+exists x.
+auto.
+Qed.
+
+Lemma PrePostE_internal_pick Regs A Ety (xs : list A) (Q : A -> predS Regs) (E : ex Ety -> predS Regs) :
+ xs <> nil ->
+ PrePostE (fun s => forall x, List.In x xs -> Q x s) (internal_pickS xs) Q E.
+unfold internal_pickS.
+intro notnil.
+eapply PrePostE_bindS with (R := fun _ s => forall x, List.In x xs -> Q x s).
+* intros.
+ destruct (nth_error_modulo (Sail2_values.nat_of_bools a) notnil) as (x & IN & nth).
+ rewrite nth.
+ eapply PrePostE_strengthen_pre.
+ apply PrePostE_returnS.
+ intuition.
+* eapply PrePostE_strengthen_pre.
+ apply PrePostE_choose_boolsS_any.
+ intuition.
+Qed.
diff --git a/prover_snapshots/coq/lib/sail/Makefile b/prover_snapshots/coq/lib/sail/Makefile
new file mode 100644
index 0000000..fa453d9
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Makefile
@@ -0,0 +1,26 @@
+BBV_DIR?=../../../bbv
+
+CORESRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v Sail2_state_lifting.v Sail2_string.v Sail2_real.v
+PROOFSRC=Sail2_state_monad_lemmas.v Sail2_state_lemmas.v Hoare.v
+SRC=$(CORESRC) $(PROOFSRC)
+
+COQ_LIBS = -R . Sail -R "$(BBV_DIR)/theories" bbv
+
+TARGETS=$(SRC:.v=.vo)
+
+.PHONY: all clean *.ide
+
+all: $(TARGETS)
+clean:
+ rm -f -- $(TARGETS) $(TARGETS:.vo=.glob) $(TARGETS:%.vo=.%.aux) deps
+
+%.vo: %.v
+ coqc $(COQ_LIBS) $<
+
+%.ide: %.v
+ coqide $(COQ_LIBS) $<
+
+deps: $(SRC)
+ coqdep $(COQ_LIBS) $(SRC) > deps
+
+-include deps
diff --git a/prover_snapshots/coq/lib/sail/Sail2_impl_base.v b/prover_snapshots/coq/lib/sail/Sail2_impl_base.v
new file mode 100644
index 0000000..464c290
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_impl_base.v
@@ -0,0 +1,1103 @@
+(*========================================================================*)
+(* Sail *)
+(* *)
+(* Copyright (c) 2013-2017 *)
+(* Kathyrn Gray *)
+(* Shaked Flur *)
+(* Stephen Kell *)
+(* Gabriel Kerneis *)
+(* Robert Norton-Wright *)
+(* Christopher Pulte *)
+(* Peter Sewell *)
+(* Alasdair Armstrong *)
+(* Brian Campbell *)
+(* Thomas Bauereiss *)
+(* Anthony Fox *)
+(* Jon French *)
+(* Dominic Mulligan *)
+(* Stephen Kell *)
+(* Mark Wassell *)
+(* *)
+(* All rights reserved. *)
+(* *)
+(* This software was developed by the University of Cambridge Computer *)
+(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *)
+(* (REMS) project, funded by EPSRC grant EP/K008528/1. *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in *)
+(* the documentation and/or other materials provided with the *)
+(* distribution. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *)
+(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *)
+(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *)
+(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *)
+(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *)
+(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *)
+(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *)
+(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *)
+(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *)
+(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *)
+(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *)
+(* SUCH DAMAGE. *)
+(*========================================================================*)
+
+Require Import Sail2_instr_kinds.
+
+(*
+class ( EnumerationType 'a )
+ val toNat : 'a -> nat
+end
+
+
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 =
+ compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare = defaultCompare
+
+
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+ let compare = enumeration_typeCompare
+ let (<) r1 r2 = (enumeration_typeCompare r1 r2) = LT
+ let (<=) r1 r2 = (enumeration_typeCompare r1 r2) <> GT
+ let (>) r1 r2 = (enumeration_typeCompare r1 r2) = GT
+ let (>=) r1 r2 = (enumeration_typeCompare r1 r2) <> LT
+end
+
+
+
+(* maybe isn't a member of type Ord - this should be in the Lem standard library*)
+instance forall 'a. Ord 'a => (Ord (maybe 'a))
+ let compare = maybeCompare compare
+ let (<) r1 r2 = (maybeCompare compare r1 r2) = LT
+ let (<=) r1 r2 = (maybeCompare compare r1 r2) <> GT
+ let (>) r1 r2 = (maybeCompare compare r1 r2) = GT
+ let (>=) r1 r2 = (maybeCompare compare r1 r2) <> LT
+end
+
+type word8 = nat (* bounded at a byte, for when lem supports it*)
+
+type end_flag =
+ | E_big_endian
+ | E_little_endian
+
+type bit =
+ | Bitc_zero
+ | Bitc_one
+
+type bit_lifted =
+ | Bitl_zero
+ | Bitl_one
+ | Bitl_undef (* used for modelling h/w arch unspecified bits *)
+ | Bitl_unknown (* used for interpreter analysis exhaustive execution *)
+
+type direction =
+ | D_increasing
+ | D_decreasing
+
+let dir_of_bool is_inc = if is_inc then D_increasing else D_decreasing
+let bool_of_dir = function
+ | D_increasing -> true
+ | D_decreasing -> false
+ end
+
+(* at some point this should probably not mention bit_lifted anymore *)
+type register_value = <|
+ rv_bits: list bit_lifted (* MSB first, smallest index number *);
+ rv_dir: direction;
+ rv_start: nat ;
+ rv_start_internal: nat;
+ (*when dir is increasing, rv_start = rv_start_internal.
+ Otherwise, tells interpreter how to reconstruct a proper decreasing value*)
+ |>
+
+type byte_lifted = Byte_lifted of list bit_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type instruction_field_value = list bit
+
+type byte = Byte of list bit (* of length 8 *) (*MSB first everywhere*)
+
+type address_lifted = Address_lifted of list byte_lifted (* of length 8 for 64bit machines*) * maybe integer
+(* for both values of end_flag, MSBy first *)
+
+type memory_byte = byte_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type memory_value = list memory_byte
+(* the list is of length >=1 *)
+(* the head of the list is the byte stored at the lowest address;
+when calling a Sail function with a wmv effect, the least significant 8
+bits of the bit vector passed to the function will be interpreted as
+the lowest address byte; similarly, when calling a Sail function with
+rmem effect, the lowest address byte will be placed in the least
+significant 8 bits of the bit vector returned by the function; this
+behaviour is consistent with little-endian. *)
+
+
+(* not sure which of these is more handy yet *)
+type address = Address of list byte (* of length 8 *) * integer
+(* type address = Address of integer *)
+
+type opcode = Opcode of list byte (* of length 4 *)
+
+(** typeclass instantiations *)
+
+instance (EnumerationType bit)
+ let toNat = function
+ | Bitc_zero -> 0
+ | Bitc_one -> 1
+ end
+end
+
+instance (EnumerationType bit_lifted)
+ let toNat = function
+ | Bitl_zero -> 0
+ | Bitl_one -> 1
+ | Bitl_undef -> 2
+ | Bitl_unknown -> 3
+ end
+end
+
+let ~{ocaml} byte_liftedCompare (Byte_lifted b1) (Byte_lifted b2) = compare b1 b2
+let inline {ocaml} byte_liftedCompare = defaultCompare
+
+let ~{ocaml} byte_liftedLess b1 b2 = byte_liftedCompare b1 b2 = LT
+let ~{ocaml} byte_liftedLessEq b1 b2 = byte_liftedCompare b1 b2 <> GT
+let ~{ocaml} byte_liftedGreater b1 b2 = byte_liftedCompare b1 b2 = GT
+let ~{ocaml} byte_liftedGreaterEq b1 b2 = byte_liftedCompare b1 b2 <> LT
+
+let inline {ocaml} byte_liftedLess = defaultLess
+let inline {ocaml} byte_liftedLessEq = defaultLessEq
+let inline {ocaml} byte_liftedGreater = defaultGreater
+let inline {ocaml} byte_liftedGreaterEq = defaultGreaterEq
+
+instance (Ord byte_lifted)
+ let compare = byte_liftedCompare
+ let (<) = byte_liftedLess
+ let (<=) = byte_liftedLessEq
+ let (>) = byte_liftedGreater
+ let (>=) = byte_liftedGreaterEq
+end
+
+let ~{ocaml} byteCompare (Byte b1) (Byte b2) = compare b1 b2
+let inline {ocaml} byteCompare = defaultCompare
+
+let ~{ocaml} byteLess b1 b2 = byteCompare b1 b2 = LT
+let ~{ocaml} byteLessEq b1 b2 = byteCompare b1 b2 <> GT
+let ~{ocaml} byteGreater b1 b2 = byteCompare b1 b2 = GT
+let ~{ocaml} byteGreaterEq b1 b2 = byteCompare b1 b2 <> LT
+
+let inline {ocaml} byteLess = defaultLess
+let inline {ocaml} byteLessEq = defaultLessEq
+let inline {ocaml} byteGreater = defaultGreater
+let inline {ocaml} byteGreaterEq = defaultGreaterEq
+
+instance (Ord byte)
+ let compare = byteCompare
+ let (<) = byteLess
+ let (<=) = byteLessEq
+ let (>) = byteGreater
+ let (>=) = byteGreaterEq
+end
+
+
+
+
+
+let ~{ocaml} opcodeCompare (Opcode o1) (Opcode o2) =
+ compare o1 o2
+let {ocaml} opcodeCompare = defaultCompare
+
+let ~{ocaml} opcodeLess b1 b2 = opcodeCompare b1 b2 = LT
+let ~{ocaml} opcodeLessEq b1 b2 = opcodeCompare b1 b2 <> GT
+let ~{ocaml} opcodeGreater b1 b2 = opcodeCompare b1 b2 = GT
+let ~{ocaml} opcodeGreaterEq b1 b2 = opcodeCompare b1 b2 <> LT
+
+let inline {ocaml} opcodeLess = defaultLess
+let inline {ocaml} opcodeLessEq = defaultLessEq
+let inline {ocaml} opcodeGreater = defaultGreater
+let inline {ocaml} opcodeGreaterEq = defaultGreaterEq
+
+instance (Ord opcode)
+ let compare = opcodeCompare
+ let (<) = opcodeLess
+ let (<=) = opcodeLessEq
+ let (>) = opcodeGreater
+ let (>=) = opcodeGreaterEq
+end
+
+let addressCompare (Address b1 i1) (Address b2 i2) = compare i1 i2
+(* this cannot be defaultCompare for OCaml because addresses contain big ints *)
+
+let addressLess b1 b2 = addressCompare b1 b2 = LT
+let addressLessEq b1 b2 = addressCompare b1 b2 <> GT
+let addressGreater b1 b2 = addressCompare b1 b2 = GT
+let addressGreaterEq b1 b2 = addressCompare b1 b2 <> LT
+
+instance (SetType address)
+ let setElemCompare = addressCompare
+end
+
+instance (Ord address)
+ let compare = addressCompare
+ let (<) = addressLess
+ let (<=) = addressLessEq
+ let (>) = addressGreater
+ let (>=) = addressGreaterEq
+end
+
+let {coq; ocaml} addressEqual a1 a2 = (addressCompare a1 a2) = EQ
+let inline {hol; isabelle} addressEqual = unsafe_structural_equality
+
+let {coq; ocaml} addressInequal a1 a2 = not (addressEqual a1 a2)
+let inline {hol; isabelle} addressInequal = unsafe_structural_inequality
+
+instance (Eq address)
+ let (=) = addressEqual
+ let (<>) = addressInequal
+end
+
+let ~{ocaml} directionCompare d1 d2 =
+ match (d1, d2) with
+ | (D_decreasing, D_increasing) -> GT
+ | (D_increasing, D_decreasing) -> LT
+ | _ -> EQ
+ end
+let inline {ocaml} directionCompare = defaultCompare
+
+let ~{ocaml} directionLess b1 b2 = directionCompare b1 b2 = LT
+let ~{ocaml} directionLessEq b1 b2 = directionCompare b1 b2 <> GT
+let ~{ocaml} directionGreater b1 b2 = directionCompare b1 b2 = GT
+let ~{ocaml} directionGreaterEq b1 b2 = directionCompare b1 b2 <> LT
+
+let inline {ocaml} directionLess = defaultLess
+let inline {ocaml} directionLessEq = defaultLessEq
+let inline {ocaml} directionGreater = defaultGreater
+let inline {ocaml} directionGreaterEq = defaultGreaterEq
+
+instance (Ord direction)
+ let compare = directionCompare
+ let (<) = directionLess
+ let (<=) = directionLessEq
+ let (>) = directionGreater
+ let (>=) = directionGreaterEq
+end
+
+instance (Show direction)
+ let show = function D_increasing -> "D_increasing" | D_decreasing -> "D_decreasing" end
+end
+
+let ~{ocaml} register_valueCompare rv1 rv2 =
+ compare (rv1.rv_bits, rv1.rv_dir, rv1.rv_start, rv1.rv_start_internal)
+ (rv2.rv_bits, rv2.rv_dir, rv2.rv_start, rv2.rv_start_internal)
+let inline {ocaml} register_valueCompare = defaultCompare
+
+let ~{ocaml} register_valueLess b1 b2 = register_valueCompare b1 b2 = LT
+let ~{ocaml} register_valueLessEq b1 b2 = register_valueCompare b1 b2 <> GT
+let ~{ocaml} register_valueGreater b1 b2 = register_valueCompare b1 b2 = GT
+let ~{ocaml} register_valueGreaterEq b1 b2 = register_valueCompare b1 b2 <> LT
+
+let inline {ocaml} register_valueLess = defaultLess
+let inline {ocaml} register_valueLessEq = defaultLessEq
+let inline {ocaml} register_valueGreater = defaultGreater
+let inline {ocaml} register_valueGreaterEq = defaultGreaterEq
+
+instance (Ord register_value)
+ let compare = register_valueCompare
+ let (<) = register_valueLess
+ let (<=) = register_valueLessEq
+ let (>) = register_valueGreater
+ let (>=) = register_valueGreaterEq
+end
+
+let address_liftedCompare (Address_lifted b1 i1) (Address_lifted b2 i2) =
+ compare (i1,b1) (i2,b2)
+(* this cannot be defaultCompare for OCaml because address_lifteds contain big
+ ints *)
+
+let address_liftedLess b1 b2 = address_liftedCompare b1 b2 = LT
+let address_liftedLessEq b1 b2 = address_liftedCompare b1 b2 <> GT
+let address_liftedGreater b1 b2 = address_liftedCompare b1 b2 = GT
+let address_liftedGreaterEq b1 b2 = address_liftedCompare b1 b2 <> LT
+
+instance (Ord address_lifted)
+ let compare = address_liftedCompare
+ let (<) = address_liftedLess
+ let (<=) = address_liftedLessEq
+ let (>) = address_liftedGreater
+ let (>=) = address_liftedGreaterEq
+end
+
+(* Registers *)
+type slice = (nat * nat)
+
+type reg_name =
+ (* do we really need this here if ppcmem already has this information by itself? *)
+| Reg of string * nat * nat * direction
+(*Name of the register, accessing the entire register, the start and size of this register, and its direction *)
+
+| Reg_slice of string * nat * direction * slice
+(* Name of the register, accessing from the bit indexed by the first
+to the bit indexed by the second integer of the slice, inclusive. For
+machineDef* the first is a smaller number or equal to the second, adjusted
+to reflect the correct span direction in the interpreter side. *)
+
+| Reg_field of string * nat * direction * string * slice
+(*Name of the register, start and direction, and name of the field of the register
+accessed. The slice specifies where this field is in the register*)
+
+| Reg_f_slice of string * nat * direction * string * slice * slice
+(* The first four components are as in Reg_field; the final slice
+specifies a part of the field, indexed w.r.t. the register as a whole *)
+
+let register_base_name : reg_name -> string = function
+ | Reg s _ _ _ -> s
+ | Reg_slice s _ _ _ -> s
+ | Reg_field s _ _ _ _ -> s
+ | Reg_f_slice s _ _ _ _ _ -> s
+ end
+
+let slice_of_reg_name : reg_name -> slice = function
+ | Reg _ start width D_increasing -> (start, start + width -1)
+ | Reg _ start width D_decreasing -> (start - width - 1, start)
+ | Reg_slice _ _ _ sl -> sl
+ | Reg_field _ _ _ _ sl -> sl
+ | Reg_f_slice _ _ _ _ _ sl -> sl
+ end
+
+let width_of_reg_name (r: reg_name) : nat =
+ let width_of_slice (i, j) = (* j - i + 1 in *)
+
+ (integerFromNat j) - (integerFromNat i) + 1
+ $> abs $> natFromInteger
+ in
+ match r with
+ | Reg _ _ width _ -> width
+ | Reg_slice _ _ _ sl -> width_of_slice sl
+ | Reg_field _ _ _ _ sl -> width_of_slice sl
+ | Reg_f_slice _ _ _ _ _ sl -> width_of_slice sl
+ end
+
+let reg_name_non_empty_intersection (r: reg_name) (r': reg_name) : bool =
+ register_base_name r = register_base_name r' &&
+ let (i1, i2) = slice_of_reg_name r in
+ let (i1', i2') = slice_of_reg_name r' in
+ i1' <= i2 && i2' >= i1
+
+let reg_nameCompare r1 r2 =
+ compare (register_base_name r1,slice_of_reg_name r1)
+ (register_base_name r2,slice_of_reg_name r2)
+
+let reg_nameLess b1 b2 = reg_nameCompare b1 b2 = LT
+let reg_nameLessEq b1 b2 = reg_nameCompare b1 b2 <> GT
+let reg_nameGreater b1 b2 = reg_nameCompare b1 b2 = GT
+let reg_nameGreaterEq b1 b2 = reg_nameCompare b1 b2 <> LT
+
+instance (Ord reg_name)
+ let compare = reg_nameCompare
+ let (<) = reg_nameLess
+ let (<=) = reg_nameLessEq
+ let (>) = reg_nameGreater
+ let (>=) = reg_nameGreaterEq
+end
+
+let {coq;ocaml} reg_nameEqual a1 a2 = (reg_nameCompare a1 a2) = EQ
+let {hol;isabelle} reg_nameEqual = unsafe_structural_equality
+let {coq;ocaml} reg_nameInequal a1 a2 = not (reg_nameEqual a1 a2)
+let {hol;isabelle} reg_nameInequal = unsafe_structural_inequality
+
+instance (Eq reg_name)
+ let (=) = reg_nameEqual
+ let (<>) = reg_nameInequal
+end
+
+instance (SetType reg_name)
+ let setElemCompare = reg_nameCompare
+end
+
+let direction_of_reg_name r = match r with
+ | Reg _ _ _ d -> d
+ | Reg_slice _ _ d _ -> d
+ | Reg_field _ _ d _ _ -> d
+ | Reg_f_slice _ _ d _ _ _ -> d
+ end
+
+let start_of_reg_name r = match r with
+ | Reg _ start _ _ -> start
+ | Reg_slice _ start _ _ -> start
+ | Reg_field _ start _ _ _ -> start
+ | Reg_f_slice _ start _ _ _ _ -> start
+end
+
+(* Data structures for building up instructions *)
+
+(* read_kind, write_kind, barrier_kind, trans_kind and instruction_kind have
+ been moved to sail_instr_kinds.lem. This removes the dependency of the
+ shallow embedding on the rest of sail_impl_base.lem, and helps avoid name
+ clashes between the different monad types. *)
+
+type event =
+ | E_read_mem of read_kind * address_lifted * nat * maybe (list reg_name)
+ | E_read_memt of read_kind * address_lifted * nat * maybe (list reg_name)
+ | E_write_mem of write_kind * address_lifted * nat * maybe (list reg_name) * memory_value * maybe (list reg_name)
+ | E_write_ea of write_kind * address_lifted * nat * maybe (list reg_name)
+ | E_excl_res
+ | E_write_memv of maybe address_lifted * memory_value * maybe (list reg_name)
+ | E_write_memvt of maybe address_lifted * (bit_lifted * memory_value) * maybe (list reg_name)
+ | E_barrier of barrier_kind
+ | E_footprint
+ | E_read_reg of reg_name
+ | E_write_reg of reg_name * register_value
+ | E_escape
+ | E_error of string
+
+
+let eventCompare e1 e2 =
+ match (e1,e2) with
+ | (E_read_mem rk1 v1 i1 tr1, E_read_mem rk2 v2 i2 tr2) ->
+ compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2))
+ | (E_read_memt rk1 v1 i1 tr1, E_read_memt rk2 v2 i2 tr2) ->
+ compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2))
+ | (E_write_mem wk1 v1 i1 tr1 v1' tr1', E_write_mem wk2 v2 i2 tr2 v2' tr2') ->
+ compare ((wk1,v1,i1),(tr1,v1',tr1')) ((wk2,v2,i2),(tr2,v2',tr2'))
+ | (E_write_ea wk1 a1 i1 tr1, E_write_ea wk2 a2 i2 tr2) ->
+ compare (wk1, (a1, i1, tr1)) (wk2, (a2, i2, tr2))
+ | (E_excl_res, E_excl_res) -> EQ
+ | (E_write_memv _ mv1 tr1, E_write_memv _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+ | (E_write_memvt _ mv1 tr1, E_write_memvt _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+ | (E_barrier bk1, E_barrier bk2) -> compare bk1 bk2
+ | (E_read_reg r1, E_read_reg r2) -> compare r1 r2
+ | (E_write_reg r1 v1, E_write_reg r2 v2) -> compare (r1,v1) (r2,v2)
+ | (E_error s1, E_error s2) -> compare s1 s2
+ | (E_escape,E_escape) -> EQ
+ | (E_read_mem _ _ _ _, _) -> LT
+ | (E_write_mem _ _ _ _ _ _, _) -> LT
+ | (E_write_ea _ _ _ _, _) -> LT
+ | (E_excl_res, _) -> LT
+ | (E_write_memv _ _ _, _) -> LT
+ | (E_barrier _, _) -> LT
+ | (E_read_reg _, _) -> LT
+ | (E_write_reg _ _, _) -> LT
+ | _ -> GT
+ end
+
+let eventLess b1 b2 = eventCompare b1 b2 = LT
+let eventLessEq b1 b2 = eventCompare b1 b2 <> GT
+let eventGreater b1 b2 = eventCompare b1 b2 = GT
+let eventGreaterEq b1 b2 = eventCompare b1 b2 <> LT
+
+instance (Ord event)
+ let compare = eventCompare
+ let (<) = eventLess
+ let (<=) = eventLessEq
+ let (>) = eventGreater
+ let (>=) = eventGreaterEq
+end
+
+instance (SetType event)
+ let setElemCompare = compare
+end
+
+
+(* the address_lifted types should go away here and be replaced by address *)
+type with_aux 'o = 'o * maybe ((unit -> (string * string)) * ((list (reg_name * register_value)) -> list event))
+type outcome 'a 'e =
+ (* Request to read memory, value is location to read, integer is size to read,
+ followed by registers that were used in computing that size *)
+ | Read_mem of (read_kind * address_lifted * nat) * (memory_value -> with_aux (outcome 'a 'e))
+ (* Tell the system a write is imminent, at address lifted, of size nat *)
+ | Write_ea of (write_kind * address_lifted * nat) * (with_aux (outcome 'a 'e))
+ (* Request the result of store-exclusive *)
+ | Excl_res of (bool -> with_aux (outcome 'a 'e))
+ (* Request to write memory at last signalled address. Memory value should be 8
+ times the size given in ea signal *)
+ | Write_memv of memory_value * (bool -> with_aux (outcome 'a 'e))
+ (* Request a memory barrier *)
+ | Barrier of barrier_kind * with_aux (outcome 'a 'e)
+ (* Tell the system to dynamically recalculate dependency footprint *)
+ | Footprint of with_aux (outcome 'a 'e)
+ (* Request to read register, will track dependency when mode.track_values *)
+ | Read_reg of reg_name * (register_value -> with_aux (outcome 'a 'e))
+ (* Request to write register *)
+ | Write_reg of (reg_name * register_value) * with_aux (outcome 'a 'e)
+ | Escape of maybe string
+ (*Result of a failed assert with possible error message to report*)
+ | Fail of maybe string
+ (* Exception of type 'e *)
+ | Exception of 'e
+ | Internal of (maybe string * maybe (unit -> string)) * with_aux (outcome 'a 'e)
+ | Done of 'a
+ | Error of string
+
+type outcome_s 'a 'e = with_aux (outcome 'a 'e)
+(* first string : output of instruction_stack_to_string
+ second string: output of local_variables_to_string *)
+
+(** operations and coercions on basic values *)
+
+val word8_to_bitls : word8 -> list bit_lifted
+val bitls_to_word8 : list bit_lifted -> word8
+
+val integer_of_word8_list : list word8 -> integer
+val word8_list_of_integer : integer -> integer -> list word8
+
+val concretizable_bitl : bit_lifted -> bool
+val concretizable_bytl : byte_lifted -> bool
+val concretizable_bytls : list byte_lifted -> bool
+
+let concretizable_bitl = function
+ | Bitl_zero -> true
+ | Bitl_one -> true
+ | Bitl_undef -> false
+ | Bitl_unknown -> false
+end
+
+let concretizable_bytl (Byte_lifted bs) = List.all concretizable_bitl bs
+let concretizable_bytls = List.all concretizable_bytl
+
+(* constructing values *)
+
+val build_register_value : list bit_lifted -> direction -> nat -> nat -> register_value
+let build_register_value bs dir width start_index =
+ <| rv_bits = bs;
+ rv_dir = dir; (* D_increasing for Power, D_decreasing for ARM *)
+ rv_start_internal = start_index;
+ rv_start = if dir = D_increasing
+ then start_index
+ else (start_index+1) - width; (* Smaller index, as in Power, for external interaction *)
+ |>
+
+val register_value : bit_lifted -> direction -> nat -> nat -> register_value
+let register_value b dir width start_index =
+ build_register_value (List.replicate width b) dir width start_index
+
+val register_value_zeros : direction -> nat -> nat -> register_value
+let register_value_zeros dir width start_index =
+ register_value Bitl_zero dir width start_index
+
+val register_value_ones : direction -> nat -> nat -> register_value
+let register_value_ones dir width start_index =
+ register_value Bitl_one dir width start_index
+
+val register_value_for_reg : reg_name -> list bit_lifted -> register_value
+let register_value_for_reg r bs : register_value =
+ let () = ensure (width_of_reg_name r = List.length bs)
+ ("register_value_for_reg (\"" ^ show (register_base_name r) ^ "\") length mismatch: "
+ ^ show (width_of_reg_name r) ^ " vs " ^ show (List.length bs))
+ in
+ let (j1, j2) = slice_of_reg_name r in
+ let d = direction_of_reg_name r in
+ <| rv_bits = bs;
+ rv_dir = d;
+ rv_start_internal = if d = D_increasing then j1 else (start_of_reg_name r) - j1;
+ rv_start = j1;
+ |>
+
+val byte_lifted_undef : byte_lifted
+let byte_lifted_undef = Byte_lifted (List.replicate 8 Bitl_undef)
+
+val byte_lifted_unknown : byte_lifted
+let byte_lifted_unknown = Byte_lifted (List.replicate 8 Bitl_unknown)
+
+val memory_value_unknown : nat (*the number of bytes*) -> memory_value
+let memory_value_unknown (width:nat) : memory_value =
+ List.replicate width byte_lifted_unknown
+
+val memory_value_undef : nat (*the number of bytes*) -> memory_value
+let memory_value_undef (width:nat) : memory_value =
+ List.replicate width byte_lifted_undef
+
+val match_endianness : forall 'a. end_flag -> list 'a -> list 'a
+let match_endianness endian l =
+ match endian with
+ | E_little_endian -> List.reverse l
+ | E_big_endian -> l
+ end
+
+(* lengths *)
+
+val memory_value_length : memory_value -> nat
+let memory_value_length (mv:memory_value) = List.length mv
+
+
+(* aux fns *)
+
+val maybe_all : forall 'a. list (maybe 'a) -> maybe (list 'a)
+let rec maybe_all' xs acc =
+ match xs with
+ | [] -> Just (List.reverse acc)
+ | Nothing :: _ -> Nothing
+ | (Just y)::xs' -> maybe_all' xs' (y::acc)
+ end
+let maybe_all xs = maybe_all' xs []
+
+(** coercions *)
+
+(* bits and bytes *)
+
+let bit_to_bool = function (* TODO: rename bool_of_bit *)
+ | Bitc_zero -> false
+ | Bitc_one -> true
+end
+
+
+val bit_lifted_of_bit : bit -> bit_lifted
+let bit_lifted_of_bit b =
+ match b with
+ | Bitc_zero -> Bitl_zero
+ | Bitc_one -> Bitl_one
+ end
+
+val bit_of_bit_lifted : bit_lifted -> maybe bit
+let bit_of_bit_lifted bl =
+ match bl with
+ | Bitl_zero -> Just Bitc_zero
+ | Bitl_one -> Just Bitc_one
+ | Bitl_undef -> Nothing
+ | Bitl_unknown -> Nothing
+ end
+
+
+val byte_lifted_of_byte : byte -> byte_lifted
+let byte_lifted_of_byte (Byte bs) : byte_lifted = Byte_lifted (List.map bit_lifted_of_bit bs)
+
+val byte_of_byte_lifted : byte_lifted -> maybe byte
+let byte_of_byte_lifted bl =
+ match bl with
+ | Byte_lifted bls ->
+ match maybe_all (List.map bit_of_bit_lifted bls) with
+ | Nothing -> Nothing
+ | Just bs -> Just (Byte bs)
+ end
+ end
+
+
+val bytes_of_bits : list bit -> list byte (*assumes (length bits) mod 8 = 0*)
+let rec bytes_of_bits bits = match bits with
+ | [] -> []
+ | b0::b1::b2::b3::b4::b5::b6::b7::bits ->
+ (Byte [b0;b1;b2;b3;b4;b5;b6;b7])::(bytes_of_bits bits)
+ | _ -> failwith "bytes_of_bits not given bits divisible by 8"
+end
+
+val byte_lifteds_of_bit_lifteds : list bit_lifted -> list byte_lifted (*assumes (length bits) mod 8 = 0*)
+let rec byte_lifteds_of_bit_lifteds bits = match bits with
+ | [] -> []
+ | b0::b1::b2::b3::b4::b5::b6::b7::bits ->
+ (Byte_lifted [b0;b1;b2;b3;b4;b5;b6;b7])::(byte_lifteds_of_bit_lifteds bits)
+ | _ -> failwith "byte_lifteds of bit_lifteds not given bits divisible by 8"
+end
+
+
+val byte_of_memory_byte : memory_byte -> maybe byte
+let byte_of_memory_byte = byte_of_byte_lifted
+
+val memory_byte_of_byte : byte -> memory_byte
+let memory_byte_of_byte = byte_lifted_of_byte
+
+
+(* to and from nat *)
+
+(* this natFromBoolList could move to the Lem word.lem library *)
+val natFromBoolList : list bool -> nat
+let rec natFromBoolListAux (acc : nat) (bl : list bool) =
+ match bl with
+ | [] -> acc
+ | (true :: bl') -> natFromBoolListAux ((acc * 2) + 1) bl'
+ | (false :: bl') -> natFromBoolListAux (acc * 2) bl'
+ end
+let natFromBoolList bl =
+ natFromBoolListAux 0 (List.reverse bl)
+
+
+val nat_of_bit_list : list bit -> nat
+let nat_of_bit_list b =
+ natFromBoolList (List.reverse (List.map bit_to_bool b))
+ (* natFromBoolList takes a list with LSB first, for consistency with rest of Lem word library, so we reverse it. twice. *)
+
+
+(* to and from integer *)
+
+val integer_of_bit_list : list bit -> integer
+let integer_of_bit_list b =
+ integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+ (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+
+val bit_list_of_integer : nat -> integer -> list bit
+let bit_list_of_integer len b =
+ List.map (fun b -> if b then Bitc_one else Bitc_zero)
+ (reverse (boolListFrombitSeq len (bitSeqFromInteger Nothing b)))
+
+val integer_of_byte_list : list byte -> integer
+let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes)
+
+val byte_list_of_integer : nat -> integer -> list byte
+let byte_list_of_integer (len:nat) (a:integer):list byte =
+ let bits = bit_list_of_integer (len * 8) a in bytes_of_bits bits
+
+
+val integer_of_address : address -> integer
+let integer_of_address (a:address):integer =
+ match a with
+ | Address bs i -> i
+ end
+
+val address_of_integer : integer -> address
+let address_of_integer (i:integer):address =
+ Address (byte_list_of_integer 8 i) i
+
+(* to and from signed-integer *)
+
+val signed_integer_of_bit_list : list bit -> integer
+let signed_integer_of_bit_list b =
+ match b with
+ | [] -> failwith "empty bit list"
+ | Bitc_zero :: b' ->
+ integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+ | Bitc_one :: b' ->
+ let b'_val = integerFromBoolList (false,(List.reverse (List.map bit_to_bool b'))) in
+ (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+ let msb_val = integerPow 2 ((List.length b) - 1) in
+ b'_val - msb_val
+ end
+
+
+(* regarding a list of int as a list of bytes in memory, MSB lowest-address first, convert to an integer *)
+val integer_address_of_int_list : list int -> integer
+let rec integerFromIntListAux (acc: integer) (is: list int) =
+ match is with
+ | [] -> acc
+ | (i :: is') -> integerFromIntListAux ((acc * 256) + integerFromInt i) is'
+ end
+let integer_address_of_int_list (is: list int) =
+ integerFromIntListAux 0 is
+
+val address_of_byte_list : list byte -> address
+let address_of_byte_list bs =
+ if List.length bs <> 8 then failwith "address_of_byte_list given list not of length 8" else
+ Address bs (integer_of_byte_list bs)
+
+let address_of_byte_lifted_list bls =
+ match maybe_all (List.map byte_of_byte_lifted bls) with
+ | Nothing -> Nothing
+ | Just bs -> Just (address_of_byte_list bs)
+ end
+
+(* operations on addresses *)
+
+val add_address_nat : address -> nat -> address
+let add_address_nat (a:address) (i:nat) : address =
+ address_of_integer ((integer_of_address a) + (integerFromNat i))
+
+val clear_low_order_bits_of_address : address -> address
+let clear_low_order_bits_of_address a =
+ match a with
+ | Address [b0;b1;b2;b3;b4;b5;b6;b7] i ->
+ match b7 with
+ | Byte [bt0;bt1;bt2;bt3;bt4;bt5;bt6;bt7] ->
+ let b7' = Byte [bt0;bt1;bt2;bt3;bt4;bt5;Bitc_zero;Bitc_zero] in
+ let bytes = [b0;b1;b2;b3;b4;b5;b6;b7'] in
+ Address bytes (integer_of_byte_list bytes)
+ | _ -> failwith "Byte does not contain 8 bits"
+ end
+ | _ -> failwith "Address does not contain 8 bytes"
+ end
+
+
+
+val byte_list_of_memory_value : end_flag -> memory_value -> maybe (list byte)
+let byte_list_of_memory_value endian mv =
+ match_endianness endian mv
+ $> List.map byte_of_memory_byte
+ $> maybe_all
+
+
+val integer_of_memory_value : end_flag -> memory_value -> maybe integer
+let integer_of_memory_value endian (mv:memory_value):maybe integer =
+ match byte_list_of_memory_value endian mv with
+ | Just bs -> Just (integer_of_byte_list bs)
+ | Nothing -> Nothing
+ end
+
+val memory_value_of_integer : end_flag -> nat -> integer -> memory_value
+let memory_value_of_integer endian (len:nat) (i:integer):memory_value =
+ List.map byte_lifted_of_byte (byte_list_of_integer len i)
+ $> match_endianness endian
+
+
+val integer_of_register_value : register_value -> maybe integer
+let integer_of_register_value (rv:register_value):maybe integer =
+ match maybe_all (List.map bit_of_bit_lifted rv.rv_bits) with
+ | Nothing -> Nothing
+ | Just bs -> Just (integer_of_bit_list bs)
+ end
+
+(* NOTE: register_value_for_reg_of_integer might be easier to use *)
+val register_value_of_integer : nat -> nat -> direction -> integer -> register_value
+let register_value_of_integer (len:nat) (start:nat) (dir:direction) (i:integer):register_value =
+ let bs = bit_list_of_integer len i in
+ build_register_value (List.map bit_lifted_of_bit bs) dir len start
+
+val register_value_for_reg_of_integer : reg_name -> integer -> register_value
+let register_value_for_reg_of_integer (r: reg_name) (i:integer) : register_value =
+ register_value_of_integer (width_of_reg_name r) (start_of_reg_name r) (direction_of_reg_name r) i
+
+(* *)
+
+val opcode_of_bytes : byte -> byte -> byte -> byte -> opcode
+let opcode_of_bytes b0 b1 b2 b3 : opcode = Opcode [b0;b1;b2;b3]
+
+val register_value_of_address : address -> direction -> register_value
+let register_value_of_address (Address bytes _) dir : register_value =
+ let bits = List.concatMap (fun (Byte bs) -> List.map bit_lifted_of_bit bs) bytes in
+ <| rv_bits = bits;
+ rv_dir = dir;
+ rv_start = 0;
+ rv_start_internal = if dir = D_increasing then 0 else (List.length bits) - 1
+ |>
+
+val register_value_of_memory_value : memory_value -> direction -> register_value
+let register_value_of_memory_value bytes dir : register_value =
+ let bitls = List.concatMap (fun (Byte_lifted bs) -> bs) bytes in
+ <| rv_bits = bitls;
+ rv_dir = dir;
+ rv_start = 0;
+ rv_start_internal = if dir = D_increasing then 0 else (List.length bitls) - 1
+ |>
+
+val memory_value_of_register_value: register_value -> memory_value
+let memory_value_of_register_value r =
+ (byte_lifteds_of_bit_lifteds r.rv_bits)
+
+val address_lifted_of_register_value : register_value -> maybe address_lifted
+(* returning Nothing iff the register value is not 64 bits wide, but
+allowing Bitl_undef and Bitl_unknown *)
+let address_lifted_of_register_value (rv:register_value) : maybe address_lifted =
+ if List.length rv.rv_bits <> 64 then Nothing
+ else
+ Just (Address_lifted (byte_lifteds_of_bit_lifteds rv.rv_bits)
+ (if List.all concretizable_bitl rv.rv_bits
+ then match (maybe_all (List.map bit_of_bit_lifted rv.rv_bits)) with
+ | (Just(bits)) -> Just (integer_of_bit_list bits)
+ | Nothing -> Nothing end
+ else Nothing))
+
+val address_of_address_lifted : address_lifted -> maybe address
+(* returning Nothing iff the address contains any Bitl_undef or Bitl_unknown *)
+let address_of_address_lifted (al:address_lifted): maybe address =
+ match al with
+ | Address_lifted bls (Just i)->
+ match maybe_all ((List.map byte_of_byte_lifted) bls) with
+ | Nothing -> Nothing
+ | Just bs -> Just (Address bs i)
+ end
+ | _ -> Nothing
+end
+
+val address_of_register_value : register_value -> maybe address
+(* returning Nothing iff the register value is not 64 bits wide, or contains Bitl_undef or Bitl_unknown *)
+let address_of_register_value (rv:register_value) : maybe address =
+ match address_lifted_of_register_value rv with
+ | Nothing -> Nothing
+ | Just al ->
+ match address_of_address_lifted al with
+ | Nothing -> Nothing
+ | Just a -> Just a
+ end
+ end
+
+let address_of_memory_value (endian: end_flag) (mv:memory_value) : maybe address =
+ match byte_list_of_memory_value endian mv with
+ | Nothing -> Nothing
+ | Just bs ->
+ if List.length bs <> 8 then Nothing else
+ Just (address_of_byte_list bs)
+ end
+
+val byte_of_int : int -> byte
+let byte_of_int (i:int) : byte =
+ Byte (bit_list_of_integer 8 (integerFromInt i))
+
+val memory_byte_of_int : int -> memory_byte
+let memory_byte_of_int (i:int) : memory_byte =
+ memory_byte_of_byte (byte_of_int i)
+
+(*
+val int_of_memory_byte : int -> maybe memory_byte
+let int_of_memory_byte (mb:memory_byte) : int =
+ failwith "TODO"
+*)
+
+
+
+val memory_value_of_address_lifted : end_flag -> address_lifted -> memory_value
+let memory_value_of_address_lifted endian (Address_lifted bs _ :address_lifted) =
+ match_endianness endian bs
+
+val byte_list_of_address : address -> list byte
+let byte_list_of_address (Address bs _) : list byte = bs
+
+val memory_value_of_address : end_flag -> address -> memory_value
+let memory_value_of_address endian (Address bs _) =
+ match_endianness endian bs
+ $> List.map byte_lifted_of_byte
+
+val byte_list_of_opcode : opcode -> list byte
+let byte_list_of_opcode (Opcode bs) : list byte = bs
+
+(** ****************************************** *)
+(** show type class instantiations *)
+(** ****************************************** *)
+
+(* matching printing_functions.ml *)
+val stringFromReg_name : reg_name -> string
+let stringFromReg_name r =
+ let norm_sl start dir (first,second) = (first,second)
+ (* match dir with
+ | D_increasing -> (first,second)
+ | D_decreasing -> (start - first, start - second)
+ end *)
+ in
+ match r with
+ | Reg s start size dir -> s
+ | Reg_slice s start dir sl ->
+ let (first,second) = norm_sl start dir sl in
+ s ^ "[" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+ | Reg_field s start dir f sl ->
+ let (first,second) = norm_sl start dir sl in
+ s ^ "." ^ f ^ " (" ^ (show start) ^ ", " ^ (show dir) ^ ", " ^ (show first) ^ ", " ^ (show second) ^ ")"
+ | Reg_f_slice s start dir f (first1,second1) (first,second) ->
+ let (first,second) =
+ match dir with
+ | D_increasing -> (first,second)
+ | D_decreasing -> (start - first, start - second)
+ end in
+ s ^ "." ^ f ^ "]" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+ end
+
+instance (Show reg_name)
+ let show = stringFromReg_name
+end
+
+
+(* hex pp of integers, adapting the Lem string_extra.lem code *)
+val stringFromNaturalHexHelper : natural -> list char -> list char
+let rec stringFromNaturalHexHelper n acc =
+ if n = 0 then
+ acc
+ else
+ stringFromNaturalHexHelper (n / 16) (String_extra.chr (natFromNatural (let nd = n mod 16 in if nd <=9 then nd + 48 else nd - 10 + 97)) :: acc)
+
+val stringFromNaturalHex : natural -> string
+let (*~{ocaml;hol}*) stringFromNaturalHex n =
+ if n = 0 then "0" else toString (stringFromNaturalHexHelper n [])
+
+val stringFromIntegerHex : integer -> string
+let (*~{ocaml}*) stringFromIntegerHex i =
+ if i < 0 then
+ "-" ^ stringFromNaturalHex (naturalFromInteger i)
+ else
+ stringFromNaturalHex (naturalFromInteger i)
+
+
+let stringFromAddress (Address bs i) =
+ let i' = integer_of_byte_list bs in
+ if i=i' then
+(*TODO: ideally this should be made to match the src/pp.ml pp_address; the following very roughly matches what's used in the ppcmem UI, enough to make exceptions readable *)
+ if i < 65535 then
+ show i
+ else
+ stringFromIntegerHex i
+ else
+ "stringFromAddress bytes and integer mismatch"
+
+instance (Show address)
+ let show = stringFromAddress
+end
+
+let stringFromByte_lifted bl =
+ match byte_of_byte_lifted bl with
+ | Nothing -> "u?"
+ | Just (Byte bits) ->
+ let i = integer_of_bit_list bits in
+ show i
+ end
+
+instance (Show byte_lifted)
+ let show = stringFromByte_lifted
+end
+
+(* possible next instruction address options *)
+type nia =
+ | NIA_successor
+ | NIA_concrete_address of address
+ | NIA_indirect_address
+
+let niaCompare n1 n2 = match (n1,n2) with
+ | (NIA_successor, NIA_successor) -> EQ
+ | (NIA_successor, _) -> LT
+ | (_, NIA_successor) -> GT
+ | (NIA_concrete_address a1, NIA_concrete_address a2) -> compare a1 a2
+ | (NIA_concrete_address _, _) -> LT
+ | (_, NIA_concrete_address _) -> GT
+ | (NIA_indirect_address, NIA_indirect_address) -> EQ
+ (* | (NIA_indirect_address, _) -> LT
+ | (_, NIA_indirect_address) -> GT *)
+ end
+
+instance (Ord nia)
+ let compare = niaCompare
+ let (<) n1 n2 = (niaCompare n1 n2) = LT
+ let (<=) n1 n2 = (niaCompare n1 n2) <> GT
+ let (>) n1 n2 = (niaCompare n1 n2) = GT
+ let (>=) n1 n2 = (niaCompare n1 n2) <> LT
+end
+
+let stringFromNia = function
+ | NIA_successor -> "NIA_successor"
+ | NIA_concrete_address a -> "NIA_concrete_address " ^ show a
+ | NIA_indirect_address -> "NIA_indirect_address"
+end
+
+instance (Show nia)
+ let show = stringFromNia
+end
+
+type dia =
+ | DIA_none
+ | DIA_concrete_address of address
+ | DIA_register of reg_name
+
+let diaCompare d1 d2 = match (d1, d2) with
+ | (DIA_none, DIA_none) -> EQ
+ | (DIA_none, _) -> LT
+ | (DIA_concrete_address a1, DIA_none) -> GT
+ | (DIA_concrete_address a1, DIA_concrete_address a2) -> compare a1 a2
+ | (DIA_concrete_address a1, _) -> LT
+ | (DIA_register r1, DIA_register r2) -> compare r1 r2
+ | (DIA_register _, _) -> GT
+end
+
+instance (Ord dia)
+ let compare = diaCompare
+ let (<) n1 n2 = (diaCompare n1 n2) = LT
+ let (<=) n1 n2 = (diaCompare n1 n2) <> GT
+ let (>) n1 n2 = (diaCompare n1 n2) = GT
+ let (>=) n1 n2 = (diaCompare n1 n2) <> LT
+end
+
+let stringFromDia = function
+ | DIA_none -> "DIA_none"
+ | DIA_concrete_address a -> "DIA_concrete_address " ^ show a
+ | DIA_register r -> "DIA_delayed_register " ^ show r
+end
+
+instance (Show dia)
+ let show = stringFromDia
+end
+*)
diff --git a/prover_snapshots/coq/lib/sail/Sail2_instr_kinds.v b/prover_snapshots/coq/lib/sail/Sail2_instr_kinds.v
new file mode 100644
index 0000000..d03d5e6
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_instr_kinds.v
@@ -0,0 +1,332 @@
+(*========================================================================*)
+(* Sail *)
+(* *)
+(* Copyright (c) 2013-2017 *)
+(* Kathyrn Gray *)
+(* Shaked Flur *)
+(* Stephen Kell *)
+(* Gabriel Kerneis *)
+(* Robert Norton-Wright *)
+(* Christopher Pulte *)
+(* Peter Sewell *)
+(* Alasdair Armstrong *)
+(* Brian Campbell *)
+(* Thomas Bauereiss *)
+(* Anthony Fox *)
+(* Jon French *)
+(* Dominic Mulligan *)
+(* Stephen Kell *)
+(* Mark Wassell *)
+(* *)
+(* All rights reserved. *)
+(* *)
+(* This software was developed by the University of Cambridge Computer *)
+(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *)
+(* (REMS) project, funded by EPSRC grant EP/K008528/1. *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in *)
+(* the documentation and/or other materials provided with the *)
+(* distribution. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *)
+(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *)
+(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *)
+(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *)
+(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *)
+(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *)
+(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *)
+(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *)
+(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *)
+(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *)
+(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *)
+(* SUCH DAMAGE. *)
+(*========================================================================*)
+
+Require Import DecidableClass.
+
+Class EnumerationType (A : Type) := {
+ toNat : A -> nat
+}.
+
+(*
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 :=
+ compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare := defaultCompare
+
+
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+ let compare := enumeration_typeCompare
+ let (<) r1 r2 := (enumeration_typeCompare r1 r2) = LT
+ let (<=) r1 r2 := (enumeration_typeCompare r1 r2) <> GT
+ let (>) r1 r2 := (enumeration_typeCompare r1 r2) = GT
+ let (>=) r1 r2 := (enumeration_typeCompare r1 r2) <> LT
+end
+*)
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+ reflected in deep_shallow_convert *)
+Inductive read_kind :=
+ (* common reads *)
+ | Read_plain
+ (* Power reads *)
+ | Read_reserve
+ (* AArch64 reads *)
+ | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+ (* RISC-V reads *)
+ | Read_RISCV_acquire | Read_RISCV_strong_acquire
+ | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+ | Read_RISCV_reserved_strong_acquire
+ (* x86 reads *)
+ | Read_X86_locked (* the read part of a lock'd instruction (rmw) *)
+.
+Scheme Equality for read_kind.
+(*
+instance (Show read_kind)
+ let show := function
+ | Read_plain -> "Read_plain"
+ | Read_reserve -> "Read_reserve"
+ | Read_acquire -> "Read_acquire"
+ | Read_exclusive -> "Read_exclusive"
+ | Read_exclusive_acquire -> "Read_exclusive_acquire"
+ | Read_stream -> "Read_stream"
+ | Read_RISCV_acquire -> "Read_RISCV_acquire"
+ | Read_RISCV_strong_acquire -> "Read_RISCV_strong_acquire"
+ | Read_RISCV_reserved -> "Read_RISCV_reserved"
+ | Read_RISCV_reserved_acquire -> "Read_RISCV_reserved_acquire"
+ | Read_RISCV_reserved_strong_acquire -> "Read_RISCV_reserved_strong_acquire"
+ | Read_X86_locked -> "Read_X86_locked"
+ end
+end
+*)
+Inductive write_kind :=
+ (* common writes *)
+ | Write_plain
+ (* Power writes *)
+ | Write_conditional
+ (* AArch64 writes *)
+ | Write_release | Write_exclusive | Write_exclusive_release
+ (* RISC-V *)
+ | Write_RISCV_release | Write_RISCV_strong_release
+ | Write_RISCV_conditional | Write_RISCV_conditional_release
+ | Write_RISCV_conditional_strong_release
+ (* x86 writes *)
+ | Write_X86_locked (* the write part of a lock'd instruction (rmw) *)
+.
+Scheme Equality for write_kind.
+(*
+instance (Show write_kind)
+ let show := function
+ | Write_plain -> "Write_plain"
+ | Write_conditional -> "Write_conditional"
+ | Write_release -> "Write_release"
+ | Write_exclusive -> "Write_exclusive"
+ | Write_exclusive_release -> "Write_exclusive_release"
+ | Write_RISCV_release -> "Write_RISCV_release"
+ | Write_RISCV_strong_release -> "Write_RISCV_strong_release"
+ | Write_RISCV_conditional -> "Write_RISCV_conditional"
+ | Write_RISCV_conditional_release -> "Write_RISCV_conditional_release"
+ | Write_RISCV_conditional_strong_release -> "Write_RISCV_conditional_strong_release"
+ | Write_X86_locked -> "Write_X86_locked"
+ end
+end
+*)
+
+Inductive a64_barrier_domain :=
+ A64_FullShare
+ | A64_InnerShare
+ | A64_OuterShare
+ | A64_NonShare.
+
+Inductive a64_barrier_type :=
+ A64_barrier_all
+ | A64_barrier_LD
+ | A64_barrier_ST.
+
+Inductive barrier_kind :=
+ (* Power barriers *)
+ | Barrier_Sync : unit -> barrier_kind
+ | Barrier_LwSync : unit -> barrier_kind
+ | Barrier_Eieio : unit -> barrier_kind
+ | Barrier_Isync : unit -> barrier_kind
+ (* AArch64 barriers *)
+ | Barrier_DMB : a64_barrier_domain -> a64_barrier_type -> barrier_kind
+ | Barrier_DSB : a64_barrier_domain -> a64_barrier_type -> barrier_kind
+ | Barrier_ISB : unit -> barrier_kind
+ (* | Barrier_TM_COMMIT*)
+ (* MIPS barriers *)
+ | Barrier_MIPS_SYNC : unit -> barrier_kind
+ (* RISC-V barriers *)
+ | Barrier_RISCV_rw_rw : unit -> barrier_kind
+ | Barrier_RISCV_r_rw : unit -> barrier_kind
+ | Barrier_RISCV_r_r : unit -> barrier_kind
+ | Barrier_RISCV_rw_w : unit -> barrier_kind
+ | Barrier_RISCV_w_w : unit -> barrier_kind
+ | Barrier_RISCV_w_rw : unit -> barrier_kind
+ | Barrier_RISCV_rw_r : unit -> barrier_kind
+ | Barrier_RISCV_r_w : unit -> barrier_kind
+ | Barrier_RISCV_w_r : unit -> barrier_kind
+ | Barrier_RISCV_tso : unit -> barrier_kind
+ | Barrier_RISCV_i : unit -> barrier_kind
+ (* X86 *)
+ | Barrier_x86_MFENCE : unit -> barrier_kind.
+Scheme Equality for barrier_kind.
+
+(*
+instance (Show barrier_kind)
+ let show := function
+ | Barrier_Sync -> "Barrier_Sync"
+ | Barrier_LwSync -> "Barrier_LwSync"
+ | Barrier_Eieio -> "Barrier_Eieio"
+ | Barrier_Isync -> "Barrier_Isync"
+ | Barrier_DMB -> "Barrier_DMB"
+ | Barrier_DMB_ST -> "Barrier_DMB_ST"
+ | Barrier_DMB_LD -> "Barrier_DMB_LD"
+ | Barrier_DSB -> "Barrier_DSB"
+ | Barrier_DSB_ST -> "Barrier_DSB_ST"
+ | Barrier_DSB_LD -> "Barrier_DSB_LD"
+ | Barrier_ISB -> "Barrier_ISB"
+ | Barrier_TM_COMMIT -> "Barrier_TM_COMMIT"
+ | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC"
+ | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw"
+ | Barrier_RISCV_r_rw -> "Barrier_RISCV_r_rw"
+ | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r"
+ | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w"
+ | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w"
+ | Barrier_RISCV_w_rw -> "Barrier_RISCV_w_rw"
+ | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r"
+ | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w"
+ | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r"
+ | Barrier_RISCV_tso -> "Barrier_RISCV_tso"
+ | Barrier_RISCV_i -> "Barrier_RISCV_i"
+ | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE"
+ end
+end*)
+
+Inductive trans_kind :=
+ (* AArch64 *)
+ | Transaction_start | Transaction_commit | Transaction_abort.
+Scheme Equality for trans_kind.
+(*
+instance (Show trans_kind)
+ let show := function
+ | Transaction_start -> "Transaction_start"
+ | Transaction_commit -> "Transaction_commit"
+ | Transaction_abort -> "Transaction_abort"
+ end
+end*)
+
+Inductive instruction_kind :=
+ | IK_barrier : barrier_kind -> instruction_kind
+ | IK_mem_read : read_kind -> instruction_kind
+ | IK_mem_write : write_kind -> instruction_kind
+ | IK_mem_rmw : (read_kind * write_kind) -> instruction_kind
+ | IK_branch : unit -> instruction_kind (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+ indirect/computed-branch (single nia of kind NIA_indirect_address)
+ and branch/jump (single nia of kind NIA_concrete_address) *)
+ | IK_trans : trans_kind -> instruction_kind
+ | IK_simple : unit -> instruction_kind.
+
+(*
+instance (Show instruction_kind)
+ let show := function
+ | IK_barrier barrier_kind -> "IK_barrier " ^ (show barrier_kind)
+ | IK_mem_read read_kind -> "IK_mem_read " ^ (show read_kind)
+ | IK_mem_write write_kind -> "IK_mem_write " ^ (show write_kind)
+ | IK_mem_rmw (r, w) -> "IK_mem_rmw " ^ (show r) ^ " " ^ (show w)
+ | IK_branch -> "IK_branch"
+ | IK_trans trans_kind -> "IK_trans " ^ (show trans_kind)
+ | IK_simple -> "IK_simple"
+ end
+end
+*)
+
+Definition read_is_exclusive r :=
+match r with
+ | Read_plain => false
+ | Read_reserve => true
+ | Read_acquire => false
+ | Read_exclusive => true
+ | Read_exclusive_acquire => true
+ | Read_stream => false
+ | Read_RISCV_acquire => false
+ | Read_RISCV_strong_acquire => false
+ | Read_RISCV_reserved => true
+ | Read_RISCV_reserved_acquire => true
+ | Read_RISCV_reserved_strong_acquire => true
+ | Read_X86_locked => true
+end.
+
+
+(*
+instance (EnumerationType read_kind)
+ let toNat := function
+ | Read_plain -> 0
+ | Read_reserve -> 1
+ | Read_acquire -> 2
+ | Read_exclusive -> 3
+ | Read_exclusive_acquire -> 4
+ | Read_stream -> 5
+ | Read_RISCV_acquire -> 6
+ | Read_RISCV_strong_acquire -> 7
+ | Read_RISCV_reserved -> 8
+ | Read_RISCV_reserved_acquire -> 9
+ | Read_RISCV_reserved_strong_acquire -> 10
+ | Read_X86_locked -> 11
+ end
+end
+
+instance (EnumerationType write_kind)
+ let toNat := function
+ | Write_plain -> 0
+ | Write_conditional -> 1
+ | Write_release -> 2
+ | Write_exclusive -> 3
+ | Write_exclusive_release -> 4
+ | Write_RISCV_release -> 5
+ | Write_RISCV_strong_release -> 6
+ | Write_RISCV_conditional -> 7
+ | Write_RISCV_conditional_release -> 8
+ | Write_RISCV_conditional_strong_release -> 9
+ | Write_X86_locked -> 10
+ end
+end
+
+instance (EnumerationType barrier_kind)
+ let toNat := function
+ | Barrier_Sync -> 0
+ | Barrier_LwSync -> 1
+ | Barrier_Eieio ->2
+ | Barrier_Isync -> 3
+ | Barrier_DMB -> 4
+ | Barrier_DMB_ST -> 5
+ | Barrier_DMB_LD -> 6
+ | Barrier_DSB -> 7
+ | Barrier_DSB_ST -> 8
+ | Barrier_DSB_LD -> 9
+ | Barrier_ISB -> 10
+ | Barrier_TM_COMMIT -> 11
+ | Barrier_MIPS_SYNC -> 12
+ | Barrier_RISCV_rw_rw -> 13
+ | Barrier_RISCV_r_rw -> 14
+ | Barrier_RISCV_r_r -> 15
+ | Barrier_RISCV_rw_w -> 16
+ | Barrier_RISCV_w_w -> 17
+ | Barrier_RISCV_w_rw -> 18
+ | Barrier_RISCV_rw_r -> 19
+ | Barrier_RISCV_r_w -> 20
+ | Barrier_RISCV_w_r -> 21
+ | Barrier_RISCV_tso -> 22
+ | Barrier_RISCV_i -> 23
+ | Barrier_x86_MFENCE -> 24
+ end
+end
+*)
diff --git a/prover_snapshots/coq/lib/sail/Sail2_operators.v b/prover_snapshots/coq/lib/sail/Sail2_operators.v
new file mode 100644
index 0000000..ab02c4a
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_operators.v
@@ -0,0 +1,232 @@
+Require Import Sail2_values.
+Require List.
+Import List.ListNotations.
+
+(*** Bit vector operations *)
+
+Section Bitvectors.
+Context {a b c} `{Bitvector a} `{Bitvector b} `{Bitvector c}.
+
+(*val concat_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c*)
+Definition concat_bv (l : a) (r : b) : list bitU := bits_of l ++ bits_of r.
+
+(*val cons_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b*)
+Definition cons_bv b' (v : a) : list bitU := b' :: bits_of v.
+
+Definition cast_unit_bv b : list bitU := [b].
+Definition bv_of_bit len b : list bitU := extz_bits len [b].
+
+(*Definition most_significant v := match bits_of v with
+ | cons b _ => b
+ | _ => failwith "most_significant applied to empty vector"
+ end.
+
+Definition get_max_representable_in sign (n : integer) : integer :=
+ if (n = 64) then match sign with | true -> max_64 | false -> max_64u end
+ else if (n=32) then match sign with | true -> max_32 | false -> max_32u end
+ else if (n=8) then max_8
+ else if (n=5) then max_5
+ else match sign with | true -> integerPow 2 ((natFromInteger n) -1)
+ | false -> integerPow 2 (natFromInteger n)
+ end
+
+Definition get_min_representable_in _ (n : integer) : integer :=
+ if n = 64 then min_64
+ else if n = 32 then min_32
+ else if n = 8 then min_8
+ else if n = 5 then min_5
+ else 0 - (integerPow 2 (natFromInteger n))
+
+val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+Definition arith_op_bv_int {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : a) (r : Z) : a :=
+ let r' := of_int (length l) r in
+ arith_op_bv op sign l r'.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+Definition arith_op_int_bv {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : Z) (r : a) : a :=
+ let l' := of_int (length r) l in
+ arith_op_bv op sign l' r.
+(*
+Definition add_bv_int := arith_op_bv_int Zplus false 1.
+Definition sadd_bv_int := arith_op_bv_int Zplus true 1.
+Definition sub_bv_int := arith_op_bv_int Zminus false 1.
+Definition mult_bv_int := arith_op_bv_int Zmult false 2.
+Definition smult_bv_int := arith_op_bv_int Zmult true 2.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> integer -> 'a -> 'b
+Definition arith_op_int_bv op sign size l r :=
+ let r' = int_of_bv sign r in
+ let n = op l r' in
+ of_int (size * length r) n
+
+Definition add_int_bv = arith_op_int_bv integerAdd false 1
+Definition sadd_int_bv = arith_op_int_bv integerAdd true 1
+Definition sub_int_bv = arith_op_int_bv integerMinus false 1
+Definition mult_int_bv = arith_op_int_bv integerMult false 2
+Definition smult_int_bv = arith_op_int_bv integerMult true 2
+
+Definition arith_op_bv_bit op sign (size : integer) l r :=
+ let l' = int_of_bv sign l in
+ let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in
+ of_int (size * length l) n
+
+Definition add_bv_bit := arith_op_bv_bit integerAdd false 1
+Definition sadd_bv_bit := arith_op_bv_bit integerAdd true 1
+Definition sub_bv_bit := arith_op_bv_bit integerMinus true 1
+
+val arith_op_overflow_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv op sign size l r :=
+ let len := length l in
+ let act_size := len * size in
+ let (l_sign,r_sign) := (int_of_bv sign l,int_of_bv sign r) in
+ let (l_unsign,r_unsign) := (int_of_bv false l,int_of_bv false r) in
+ let n := op l_sign r_sign in
+ let n_unsign := op l_unsign r_unsign in
+ let correct_size := of_int act_size n in
+ let one_more_size_u := bits_of_int (act_size + 1) n_unsign in
+ let overflow :=
+ if n <= get_max_representable_in sign len &&
+ n >= get_min_representable_in sign len
+ then B0 else B1 in
+ let c_out := most_significant one_more_size_u in
+ (correct_size,overflow,c_out)
+
+Definition add_overflow_bv := arith_op_overflow_bv integerAdd false 1
+Definition add_overflow_bv_signed := arith_op_overflow_bv integerAdd true 1
+Definition sub_overflow_bv := arith_op_overflow_bv integerMinus false 1
+Definition sub_overflow_bv_signed := arith_op_overflow_bv integerMinus true 1
+Definition mult_overflow_bv := arith_op_overflow_bv integerMult false 2
+Definition mult_overflow_bv_signed := arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv_bit op sign size l r_bit :=
+ let act_size := length l * size in
+ let l' := int_of_bv sign l in
+ let l_u := int_of_bv false l in
+ let (n,nu,changed) := match r_bit with
+ | B1 -> (op l' 1, op l_u 1, true)
+ | B0 -> (l',l_u,false)
+ | BU -> failwith "arith_op_overflow_bv_bit applied to undefined bit"
+ end in
+ let correct_size := of_int act_size n in
+ let one_larger := bits_of_int (act_size + 1) nu in
+ let overflow :=
+ if changed
+ then
+ if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+ then B0 else B1
+ else B0 in
+ (correct_size,overflow,most_significant one_larger)
+
+Definition add_overflow_bv_bit := arith_op_overflow_bv_bit integerAdd false 1
+Definition add_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerAdd true 1
+Definition sub_overflow_bv_bit := arith_op_overflow_bv_bit integerMinus false 1
+Definition sub_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerMinus true 1
+
+type shift := LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
+
+val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a
+Definition shift_op_bv op v n :=
+ match op with
+ | LL_shift ->
+ of_bits (get_bits true v n (length v - 1) ++ repeat [B0] n)
+ | RR_shift ->
+ of_bits (repeat [B0] n ++ get_bits true v 0 (length v - n - 1))
+ | RR_shift_arith ->
+ of_bits (repeat [most_significant v] n ++ get_bits true v 0 (length v - n - 1))
+ | LL_rot ->
+ of_bits (get_bits true v n (length v - 1) ++ get_bits true v 0 (n - 1))
+ | RR_rot ->
+ of_bits (get_bits false v 0 (n - 1) ++ get_bits false v n (length v - 1))
+ end
+
+Definition shiftl_bv := shift_op_bv LL_shift (*"<<"*)
+Definition shiftr_bv := shift_op_bv RR_shift (*">>"*)
+Definition arith_shiftr_bv := shift_op_bv RR_shift_arith
+Definition rotl_bv := shift_op_bv LL_rot (*"<<<"*)
+Definition rotr_bv := shift_op_bv LL_rot (*">>>"*)
+
+Definition shiftl_mword w n := Machine_word.shiftLeft w (natFromInteger n)
+Definition shiftr_mword w n := Machine_word.shiftRight w (natFromInteger n)
+Definition rotl_mword w n := Machine_word.rotateLeft (natFromInteger n) w
+Definition rotr_mword w n := Machine_word.rotateRight (natFromInteger n) w
+
+Definition rec arith_op_no0 (op : integer -> integer -> integer) l r :=
+ if r = 0
+ then Nothing
+ else Just (op l r)
+
+val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b
+Definition arith_op_bv_no0 op sign size l r :=
+ let act_size := length l * size in
+ let (l',r') := (int_of_bv sign l,int_of_bv sign r) in
+ let n := arith_op_no0 op l' r' in
+ let (representable,n') :=
+ match n with
+ | Just n' ->
+ (n' <= get_max_representable_in sign act_size &&
+ n' >= get_min_representable_in sign act_size, n')
+ | _ -> (false,0)
+ end in
+ if representable then (of_int act_size n') else (of_bits (repeat [BU] act_size))
+
+Definition mod_bv := arith_op_bv_no0 hardware_mod false 1
+Definition quot_bv := arith_op_bv_no0 hardware_quot false 1
+Definition quot_bv_signed := arith_op_bv_no0 hardware_quot true 1
+
+Definition mod_mword := Machine_word.modulo
+Definition quot_mword := Machine_word.unsignedDivide
+Definition quot_mword_signed := Machine_word.signedDivide
+
+Definition arith_op_bv_int_no0 op sign size l r :=
+ arith_op_bv_no0 op sign size l (of_int (length l) r)
+
+Definition quot_bv_int := arith_op_bv_int_no0 hardware_quot false 1
+Definition mod_bv_int := arith_op_bv_int_no0 hardware_mod false 1
+*)
+Definition replicate_bits_bv {a b} `{Bitvector a} `{Bitvector b} (v : a) count : b := of_bits (repeat (bits_of v) count).
+Import List.
+Import ListNotations.
+Definition duplicate_bit_bv {a} `{Bitvector a} bit len : a := replicate_bits_bv [bit] len.
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition eq_bv {A} `{Bitvector A} (l : A) r := (unsigned l =? unsigned r).
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition neq_bv (l : a) (r :a) : bool := (negb (unsigned l =? unsigned r)).
+(*
+val ucmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition ucmp_bv cmp l r := cmp (unsigned l) (unsigned r)
+
+val scmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition scmp_bv cmp l r := cmp (signed l) (signed r)
+
+Definition ult_bv := ucmp_bv (<)
+Definition slt_bv := scmp_bv (<)
+Definition ugt_bv := ucmp_bv (>)
+Definition sgt_bv := scmp_bv (>)
+Definition ulteq_bv := ucmp_bv (<=)
+Definition slteq_bv := scmp_bv (<=)
+Definition ugteq_bv := ucmp_bv (>=)
+Definition sgteq_bv := scmp_bv (>=)
+*)
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)*)
+Definition get_slice_int_bv {a} `{Bitvector a} len n lo : a :=
+ let hi := lo + len - 1 in
+ let bs := bools_of_int (hi + 1) n in
+ of_bools (subrange_list false bs hi lo).
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer
+Definition set_slice_int_bv {a} `{Bitvector a} len n lo (v : a) :=
+ let hi := lo + len - 1 in
+ let bs := bits_of_int (hi + 1) n in
+ maybe_failwith (signed_of_bits (update_subrange_list false bs hi lo (bits_of v))).*)
+
+End Bitvectors.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_operators_bitlists.v b/prover_snapshots/coq/lib/sail/Sail2_operators_bitlists.v
new file mode 100644
index 0000000..dbd8215
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_operators_bitlists.v
@@ -0,0 +1,182 @@
+Require Import Sail2_values.
+Require Import Sail2_operators.
+
+(*
+
+(* Specialisation of operators to bit lists *)
+
+val access_vec_inc : list bitU -> integer -> bitU
+let access_vec_inc = access_bv_inc
+
+val access_vec_dec : list bitU -> integer -> bitU
+let access_vec_dec = access_bv_dec
+
+val update_vec_inc : list bitU -> integer -> bitU -> list bitU
+let update_vec_inc = update_bv_inc
+
+val update_vec_dec : list bitU -> integer -> bitU -> list bitU
+let update_vec_dec = update_bv_dec
+
+val subrange_vec_inc : list bitU -> integer -> integer -> list bitU
+let subrange_vec_inc = subrange_bv_inc
+
+val subrange_vec_dec : list bitU -> integer -> integer -> list bitU
+let subrange_vec_dec = subrange_bv_dec
+
+val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_inc = update_subrange_bv_inc
+
+val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_dec = update_subrange_bv_dec
+
+val extz_vec : integer -> list bitU -> list bitU
+let extz_vec = extz_bv
+
+val exts_vec : integer -> list bitU -> list bitU
+let exts_vec = exts_bv
+
+val concat_vec : list bitU -> list bitU -> list bitU
+let concat_vec = concat_bv
+
+val cons_vec : bitU -> list bitU -> list bitU
+let cons_vec = cons_bv
+
+val bool_of_vec : mword ty1 -> bitU
+let bool_of_vec = bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+let cast_unit_vec = cast_unit_bv
+
+val vec_of_bit : integer -> bitU -> list bitU
+let vec_of_bit = bv_of_bit
+
+val msb : list bitU -> bitU
+let msb = most_significant
+
+val int_of_vec : bool -> list bitU -> integer
+let int_of_vec = int_of_bv
+
+val string_of_vec : list bitU -> string
+let string_of_vec = string_of_bv
+
+val and_vec : list bitU -> list bitU -> list bitU
+val or_vec : list bitU -> list bitU -> list bitU
+val xor_vec : list bitU -> list bitU -> list bitU
+val not_vec : list bitU -> list bitU
+let and_vec = and_bv
+let or_vec = or_bv
+let xor_vec = xor_bv
+let not_vec = not_bv
+
+val add_vec : list bitU -> list bitU -> list bitU
+val sadd_vec : list bitU -> list bitU -> list bitU
+val sub_vec : list bitU -> list bitU -> list bitU
+val mult_vec : list bitU -> list bitU -> list bitU
+val smult_vec : list bitU -> list bitU -> list bitU
+let add_vec = add_bv
+let sadd_vec = sadd_bv
+let sub_vec = sub_bv
+let mult_vec = mult_bv
+let smult_vec = smult_bv
+
+val add_vec_int : list bitU -> integer -> list bitU
+val sadd_vec_int : list bitU -> integer -> list bitU
+val sub_vec_int : list bitU -> integer -> list bitU
+val mult_vec_int : list bitU -> integer -> list bitU
+val smult_vec_int : list bitU -> integer -> list bitU
+let add_vec_int = add_bv_int
+let sadd_vec_int = sadd_bv_int
+let sub_vec_int = sub_bv_int
+let mult_vec_int = mult_bv_int
+let smult_vec_int = smult_bv_int
+
+val add_int_vec : integer -> list bitU -> list bitU
+val sadd_int_vec : integer -> list bitU -> list bitU
+val sub_int_vec : integer -> list bitU -> list bitU
+val mult_int_vec : integer -> list bitU -> list bitU
+val smult_int_vec : integer -> list bitU -> list bitU
+let add_int_vec = add_int_bv
+let sadd_int_vec = sadd_int_bv
+let sub_int_vec = sub_int_bv
+let mult_int_vec = mult_int_bv
+let smult_int_vec = smult_int_bv
+
+val add_vec_bit : list bitU -> bitU -> list bitU
+val sadd_vec_bit : list bitU -> bitU -> list bitU
+val sub_vec_bit : list bitU -> bitU -> list bitU
+let add_vec_bit = add_bv_bit
+let sadd_vec_bit = sadd_bv_bit
+let sub_vec_bit = sub_bv_bit
+
+val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec = add_overflow_bv
+let add_overflow_vec_signed = add_overflow_bv_signed
+let sub_overflow_vec = sub_overflow_bv
+let sub_overflow_vec_signed = sub_overflow_bv_signed
+let mult_overflow_vec = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit = add_overflow_bv_bit
+let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed
+
+val shiftl : list bitU -> integer -> list bitU
+val shiftr : list bitU -> integer -> list bitU
+val arith_shiftr : list bitU -> integer -> list bitU
+val rotl : list bitU -> integer -> list bitU
+val rotr : list bitU -> integer -> list bitU
+let shiftl = shiftl_bv
+let shiftr = shiftr_bv
+let arith_shiftr = arith_shiftr_bv
+let rotl = rotl_bv
+let rotr = rotr_bv
+
+val mod_vec : list bitU -> list bitU -> list bitU
+val quot_vec : list bitU -> list bitU -> list bitU
+val quot_vec_signed : list bitU -> list bitU -> list bitU
+let mod_vec = mod_bv
+let quot_vec = quot_bv
+let quot_vec_signed = quot_bv_signed
+
+val mod_vec_int : list bitU -> integer -> list bitU
+val quot_vec_int : list bitU -> integer -> list bitU
+let mod_vec_int = mod_bv_int
+let quot_vec_int = quot_bv_int
+
+val replicate_bits : list bitU -> integer -> list bitU
+let replicate_bits = replicate_bits_bv
+
+val duplicate : bitU -> integer -> list bitU
+let duplicate = duplicate_bit_bv
+
+val eq_vec : list bitU -> list bitU -> bool
+val neq_vec : list bitU -> list bitU -> bool
+val ult_vec : list bitU -> list bitU -> bool
+val slt_vec : list bitU -> list bitU -> bool
+val ugt_vec : list bitU -> list bitU -> bool
+val sgt_vec : list bitU -> list bitU -> bool
+val ulteq_vec : list bitU -> list bitU -> bool
+val slteq_vec : list bitU -> list bitU -> bool
+val ugteq_vec : list bitU -> list bitU -> bool
+val sgteq_vec : list bitU -> list bitU -> bool
+let eq_vec = eq_bv
+let neq_vec = neq_bv
+let ult_vec = ult_bv
+let slt_vec = slt_bv
+let ugt_vec = ugt_bv
+let sgt_vec = sgt_bv
+let ulteq_vec = ulteq_bv
+let slteq_vec = slteq_bv
+let ugteq_vec = ugteq_bv
+let sgteq_vec = sgteq_bv
+*)
diff --git a/prover_snapshots/coq/lib/sail/Sail2_operators_mwords.v b/prover_snapshots/coq/lib/sail/Sail2_operators_mwords.v
new file mode 100644
index 0000000..697bc4a
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_operators_mwords.v
@@ -0,0 +1,544 @@
+Require Import Sail2_values.
+Require Import Sail2_operators.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import bbv.Word.
+Require bbv.BinNotation.
+Require Import Arith.
+Require Import ZArith.
+Require Import Omega.
+Require Import Eqdep_dec.
+
+Fixpoint cast_positive (T : positive -> Type) (p q : positive) : T p -> p = q -> T q.
+refine (
+match p, q with
+| xH, xH => fun x _ => x
+| xO p', xO q' => fun x e => cast_positive (fun x => T (xO x)) p' q' x _
+| xI p', xI q' => fun x e => cast_positive (fun x => T (xI x)) p' q' x _
+| _, _ => _
+end); congruence.
+Defined.
+
+Definition cast_T {T : Z -> Type} {m n} : forall (x : T m) (eq : m = n), T n.
+refine (match m,n with
+| Z0, Z0 => fun x _ => x
+| Zneg p1, Zneg p2 => fun x e => cast_positive (fun p => T (Zneg p)) p1 p2 x _
+| Zpos p1, Zpos p2 => fun x e => cast_positive (fun p => T (Zpos p)) p1 p2 x _
+| _,_ => _
+end); congruence.
+Defined.
+
+Lemma cast_positive_refl : forall p T x (e : p = p),
+ cast_positive T p p x e = x.
+induction p.
+* intros. simpl. rewrite IHp; auto.
+* intros. simpl. rewrite IHp; auto.
+* reflexivity.
+Qed.
+
+Lemma cast_T_refl {T : Z -> Type} {m} {H:m = m} (x : T m) : cast_T x H = x.
+destruct m.
+* reflexivity.
+* simpl. rewrite cast_positive_refl. reflexivity.
+* simpl. rewrite cast_positive_refl. reflexivity.
+Qed.
+
+Definition autocast {T : Z -> Type} {m n} (x : T m) `{H:ArithFact (m = n)} : T n :=
+ cast_T x (use_ArithFact H).
+
+Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e :=
+ x >>= fun x => returnm (cast_T x (use_ArithFact H)).
+
+Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n :=
+ DepEqNat.nat_cast _ eq x.
+
+Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x.
+rewrite (UIP_refl_nat _ H).
+apply nat_cast_same.
+Qed.
+
+Definition mword_of_nat {m} : Word.word m -> mword (Z.of_nat m).
+refine (match m return word m -> mword (Z.of_nat m) with
+| O => fun x => x
+| S m' => fun x => nat_cast _ _ x
+end).
+rewrite SuccNat2Pos.id_succ.
+reflexivity.
+Defined.
+
+Definition cast_to_mword {m n} (x : Word.word m) : Z.of_nat m = n -> mword n.
+refine (match n return Z.of_nat m = n -> mword n with
+| Z0 => fun _ => WO
+| Zpos p => fun eq => cast_T (mword_of_nat x) eq
+| Zneg p => _
+end).
+intro eq.
+exfalso. destruct m; simpl in *; congruence.
+Defined.
+
+(*
+(* Specialisation of operators to machine words *)
+
+val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_inc {a} : mword a -> Z -> bitU := access_mword_inc.
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_dec {a} : mword a -> Z -> bitU := access_mword_dec.
+
+(*val update_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+(* TODO: probably ought to use a monadic version instead, but using bad default for
+ type compatibility just now *)
+Definition update_vec_inc {a} (w : mword a) i b : mword a :=
+ opt_def w (update_mword_inc w i b).
+
+(*val update_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+Definition update_vec_dec {a} (w : mword a) i b : mword a := opt_def w (update_mword_dec w i b).
+
+Lemma subrange_lemma0 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : (Z.to_nat o <= Z.to_nat m < Z.to_nat n)%nat.
+intros.
+unwrap_ArithFacts.
+split.
++ apply Z2Nat.inj_le; omega.
++ apply Z2Nat.inj_lt; omega.
+Qed.
+Lemma subrange_lemma1 {n m o} : (o <= m < n -> n = m + 1 + (n - (m + 1)))%nat.
+intros. omega.
+Qed.
+Lemma subrange_lemma2 {n m o} : (o <= m < n -> m+1 = o+(m-o+1))%nat.
+omega.
+Qed.
+Lemma subrange_lemma3 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} :
+ Z.of_nat (Z.to_nat m - Z.to_nat o + 1)%nat = m - o + 1.
+unwrap_ArithFacts.
+rewrite Nat2Z.inj_add.
+rewrite Nat2Z.inj_sub.
+repeat rewrite Z2Nat.id; try omega.
+reflexivity.
+apply Z2Nat.inj_le; omega.
+Qed.
+
+Definition subrange_vec_dec {n} (v : mword n) m o `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : mword (m - o + 1) :=
+ let n := Z.to_nat n in
+ let m := Z.to_nat m in
+ let o := Z.to_nat o in
+ let prf : (o <= m < n)%nat := subrange_lemma0 in
+ let w := get_word v in
+ cast_to_mword (split2 o (m-o+1)
+ (cast_word (split1 (m+1) (n-(m+1)) (cast_word w (subrange_lemma1 prf)))
+ (subrange_lemma2 prf))) subrange_lemma3.
+
+Definition subrange_vec_inc {n} (v : mword n) m o `{ArithFact (0 <= m)} `{ArithFact (m <= o < n)} : mword (o - m + 1) := autocast (subrange_vec_dec v (n-1-m) (n-1-o)).
+
+(* TODO: get rid of bogus default *)
+Parameter dummy_vector : forall {n} `{ArithFact (n >= 0)}, mword n.
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_inc {a b} (v : mword a) i j (w : mword b) : mword a :=
+ opt_def dummy_vector (of_bits (update_subrange_bv_inc v i j w)).
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_dec {a b} (v : mword a) i j (w : mword b) : mword a :=
+ opt_def dummy_vector (of_bits (update_subrange_bv_dec v i j w)).
+
+Lemma mword_nonneg {a} : mword a -> a >= 0.
+destruct a;
+auto using Z.le_ge, Zle_0_pos with zarith.
+destruct 1.
+Qed.
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition extz_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.zext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition exts_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.sext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := extz_vec n v.
+
+Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v.
+
+Definition zeros (n : Z) `{ArithFact (n >= 0)} : mword n.
+refine (cast_to_mword (Word.wzero (Z.to_nat n)) _).
+unwrap_ArithFacts.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat.
+intros.
+assert ((Z.to_nat m <= Z.to_nat n)%nat).
+{ apply Z2Nat.inj_le; omega. }
+omega.
+Qed.
+Lemma truncateLSB_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat.
+intros.
+assert ((Z.to_nat m <= Z.to_nat n)%nat).
+{ apply Z2Nat.inj_le; omega. }
+omega.
+Qed.
+
+Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m :=
+ cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m).
+
+Definition vector_truncateLSB {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m :=
+ cast_to_mword (Word.split2 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncateLSB_eq; auto) : Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m).
+
+Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b.
+intros.
+rewrite Nat2Z.inj_add.
+rewrite Z2Nat.id; auto with zarith.
+rewrite Z2Nat.id; auto with zarith.
+Qed.
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+Definition concat_vec {a b} (v : mword a) (w : mword b) : mword (a + b) :=
+ cast_to_mword (Word.combine (get_word w) (get_word v)) (ltac:(solve [auto using concat_eq, mword_nonneg with zarith]) : Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b).
+
+(*val cons_vec : forall 'a 'b 'c. Size 'a, Size 'b => bitU -> mword 'a -> mword 'b*)
+(*Definition cons_vec {a b} : bitU -> mword a -> mword b := cons_bv.*)
+
+(*val bool_of_vec : mword ty1 -> bitU
+Definition bool_of_vec := bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+Definition cast_unit_vec := cast_unit_bv
+
+val vec_of_bit : forall 'a. Size 'a => integer -> bitU -> mword 'a
+Definition vec_of_bit := bv_of_bit*)
+
+Require Import bbv.NatLib.
+
+Lemma Npow2_pow {n} : (2 ^ (N.of_nat n) = Npow2 n)%N.
+induction n.
+* reflexivity.
+* rewrite Nnat.Nat2N.inj_succ.
+ rewrite N.pow_succ_r'.
+ rewrite IHn.
+ rewrite Npow2_S.
+ rewrite Word.Nmul_two.
+ reflexivity.
+Qed.
+
+Program Definition uint {a} (x : mword a) : {z : Z & ArithFact (0 <= z /\ z <= 2 ^ a - 1)} :=
+ existT _ (Z.of_N (Word.wordToN (get_word x))) _.
+Next Obligation.
+constructor.
+constructor.
+* apply N2Z.is_nonneg.
+* assert (2 ^ a - 1 = Z.of_N (2 ^ (Z.to_N a) - 1)). {
+ rewrite N2Z.inj_sub.
+ * rewrite N2Z.inj_pow.
+ rewrite Z2N.id; auto.
+ destruct a; auto with zarith. destruct x.
+ * apply N.le_trans with (m := (2^0)%N); auto using N.le_refl.
+ apply N.pow_le_mono_r.
+ inversion 1.
+ apply N.le_0_l.
+ }
+ rewrite H.
+ apply N2Z.inj_le.
+ rewrite N.sub_1_r.
+ apply N.lt_le_pred.
+ rewrite <- Z_nat_N.
+ rewrite Npow2_pow.
+ apply Word.wordToN_bound.
+Defined.
+
+Lemma Zpow_pow2 {n} : 2 ^ Z.of_nat n = Z.of_nat (pow2 n).
+induction n.
+* reflexivity.
+* rewrite pow2_S_z.
+ rewrite Nat2Z.inj_succ.
+ rewrite Z.pow_succ_r; auto with zarith.
+Qed.
+
+Program Definition sint {a} `{ArithFact (a > 0)} (x : mword a) : {z : Z & ArithFact (-(2^(a-1)) <= z /\ z <= 2 ^ (a-1) - 1)} :=
+ existT _ (Word.wordToZ (get_word x)) _.
+Next Obligation.
+destruct H.
+destruct a; try inversion fact.
+constructor.
+generalize (get_word x).
+rewrite <- positive_nat_Z.
+destruct (Pos2Nat.is_succ p) as [n eq].
+rewrite eq.
+rewrite Nat2Z.id.
+intro w.
+destruct (Word.wordToZ_size' w) as [LO HI].
+replace 1 with (Z.of_nat 1); auto.
+rewrite <- Nat2Z.inj_sub; auto with arith.
+simpl.
+rewrite <- minus_n_O.
+rewrite Zpow_pow2.
+rewrite Z.sub_1_r.
+rewrite <- Z.lt_le_pred.
+auto.
+Defined.
+
+Definition sint0 {a} `{ArithFact (a >= 0)} (x : mword a) : Z :=
+ if sumbool_of_bool (Z.eqb a 0) then 0 else projT1 (sint x).
+
+Lemma length_list_pos : forall {A} {l:list A}, length_list l >= 0.
+unfold length_list.
+auto with zarith.
+Qed.
+Hint Resolve length_list_pos : sail.
+
+Definition vec_of_bits (l:list bitU) : mword (length_list l) := opt_def dummy_vector (of_bits l).
+(*
+
+val msb : forall 'a. Size 'a => mword 'a -> bitU
+Definition msb := most_significant
+
+val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer
+Definition int_of_vec := int_of_bv
+
+val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
+Definition string_of_bits {n} (w : mword n) : string := string_of_bv w.
+Definition with_word' {n} (P : Type -> Type) : (forall n, Word.word n -> P (Word.word n)) -> mword n -> P (mword n) := fun f w => @with_word n _ (f (Z.to_nat n)) w.
+Definition word_binop {n} (f : forall n, Word.word n -> Word.word n -> Word.word n) : mword n -> mword n -> mword n := with_word' (fun x => x -> x) f.
+Definition word_unop {n} (f : forall n, Word.word n -> Word.word n) : mword n -> mword n := with_word' (fun x => x) f.
+
+
+(*
+val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+Definition and_vec {n} : mword n -> mword n -> mword n := word_binop Word.wand.
+Definition or_vec {n} : mword n -> mword n -> mword n := word_binop Word.wor.
+Definition xor_vec {n} : mword n -> mword n -> mword n := word_binop Word.wxor.
+Definition not_vec {n} : mword n -> mword n := word_unop Word.wnot.
+
+(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sadd_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b
+val smult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+Definition add_vec {n} : mword n -> mword n -> mword n := word_binop Word.wplus.
+(*Definition sadd_vec {n} : mword n -> mword n -> mword n := sadd_bv w.*)
+Definition sub_vec {n} : mword n -> mword n -> mword n := word_binop Word.wminus.
+Definition mult_vec {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+ word_binop Word.wmult (zero_extend l _) (zero_extend r _).
+Definition mults_vec {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+ word_binop Word.wmult (sign_extend l _) (sign_extend r _).
+
+(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sadd_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
+val smult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Definition add_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add false l r.
+Definition sadd_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add true l r.
+Definition sub_vec_int {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.sub false l r.
+(*Definition mult_vec_int {a b} : mword a -> Z -> mword b := mult_bv_int.
+Definition smult_vec_int {a b} : mword a -> Z -> mword b := smult_bv_int.*)
+
+(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sadd_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+val smult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+Definition add_int_vec := add_int_bv
+Definition sadd_int_vec := sadd_int_bv
+Definition sub_int_vec := sub_int_bv
+Definition mult_int_vec := mult_int_bv
+Definition smult_int_vec := smult_int_bv
+
+val add_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sadd_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sub_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+Definition add_vec_bit := add_bv_bit
+Definition sadd_vec_bit := sadd_bv_bit
+Definition sub_vec_bit := sub_bv_bit
+
+val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val add_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec := add_overflow_bv
+Definition add_overflow_vec_signed := add_overflow_bv_signed
+Definition sub_overflow_vec := sub_overflow_bv
+Definition sub_overflow_vec_signed := sub_overflow_bv_signed
+Definition mult_overflow_vec := mult_overflow_bv
+Definition mult_overflow_vec_signed := mult_overflow_bv_signed
+
+val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec_bit := add_overflow_bv_bit
+Definition add_overflow_vec_bit_signed := add_overflow_bv_bit_signed
+Definition sub_overflow_vec_bit := sub_overflow_bv_bit
+Definition sub_overflow_vec_bit_signed := sub_overflow_bv_bit_signed
+
+val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(* TODO: check/redefine behaviour on out-of-range n *)
+Definition shiftl {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wlshift' w (Z.to_nat n)) v.
+Definition shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshift' w (Z.to_nat n)) v.
+Definition arith_shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshifta' w (Z.to_nat n)) v.
+(*
+Definition rotl := rotl_bv
+Definition rotr := rotr_bv
+
+val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+Definition mod_vec := mod_bv
+Definition quot_vec := quot_bv
+Definition quot_vec_signed := quot_bv_signed
+
+val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+Definition mod_vec_int := mod_bv_int
+Definition quot_vec_int := quot_bv_int
+
+val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Fixpoint replicate_bits_aux {a} (w : Word.word a) (n : nat) : Word.word (n * a) :=
+match n with
+| O => Word.WO
+| S m => Word.combine w (replicate_bits_aux w m)
+end.
+Lemma replicate_ok {n a} `{ArithFact (n >= 0)} `{ArithFact (a >= 0)} :
+ Z.of_nat (Z.to_nat n * Z.to_nat a) = a * n.
+destruct H. destruct H0.
+rewrite <- Z2Nat.id; auto with zarith.
+rewrite Z2Nat.inj_mul; auto with zarith.
+rewrite Nat.mul_comm. reflexivity.
+Qed.
+Definition replicate_bits {a} (w : mword a) (n : Z) `{ArithFact (n >= 0)} : mword (a * n) :=
+ cast_to_mword (replicate_bits_aux (get_word w) (Z.to_nat n)) replicate_ok.
+
+(*val duplicate : forall 'a. Size 'a => bitU -> integer -> mword 'a
+Definition duplicate := duplicate_bit_bv
+
+val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ult_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+Definition eq_vec {n} (x : mword n) (y : mword n) : bool := Word.weqb (get_word x) (get_word y).
+Definition neq_vec {n} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+(*Definition ult_vec := ult_bv.
+Definition slt_vec := slt_bv.
+Definition ugt_vec := ugt_bv.
+Definition sgt_vec := sgt_bv.
+Definition ulteq_vec := ulteq_bv.
+Definition slteq_vec := slteq_bv.
+Definition ugteq_vec := ugteq_bv.
+Definition sgteq_vec := sgteq_bv.
+
+*)
+
+Definition eq_vec_dec {n} : forall (x y : mword n), {x = y} + {x <> y}.
+refine (match n with
+| Z0 => _
+| Zpos m => _
+| Zneg m => _
+end).
+* simpl. apply Word.weq.
+* simpl. apply Word.weq.
+* simpl. destruct x.
+Defined.
+
+Instance Decidable_eq_mword {n} : forall (x y : mword n), Decidable (x = y) :=
+ Decidable_eq_from_dec eq_vec_dec.
+
+Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n :=
+ match n with
+ | S (S (S (S (S (S (S (S m))))))) =>
+ combine
+ (reverse_endianness_word (split2 8 m bits))
+ (split1 8 m bits)
+ | _ => bits
+ end.
+Next Obligation.
+omega.
+Qed.
+
+Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits.
+
+Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv.
+
+Definition set_slice n m (v : mword n) x (w : mword m) : mword n :=
+ update_subrange_vec_dec v (x + m - 1) x w.
+
+Definition set_slice_int len n lo (v : mword len) : Z :=
+ let hi := lo + len - 1 in
+ (* We don't currently have a constraint on lo in the sail prelude, so let's
+ avoid one here. *)
+ if sumbool_of_bool (Z.gtb hi 0) then
+ let bs : mword (hi + 1) := mword_of_int n in
+ (int_of_mword true (update_subrange_vec_dec bs hi lo v))
+ else n.
+
+(* Variant of bitvector slicing for the ARM model with few constraints *)
+Definition slice {m} (v : mword m) lo len `{ArithFact (0 <= len)} : mword len :=
+ if sumbool_of_bool (orb (len =? 0) (lo <? 0))
+ then zeros len
+ else
+ if sumbool_of_bool (lo + len - 1 >=? m)
+ then if sumbool_of_bool (lo <? m)
+ then zero_extend (subrange_vec_dec v (m - 1) lo) len
+ else zeros len
+ else autocast (subrange_vec_dec v (lo + len - 1) lo).
+
+(*
+Lemma slice_is_ok m (v : mword m) lo len
+ (H1 : 0 <= lo) (H2 : 0 < len) (H3: lo + len < m) :
+ slice v lo len = autocast (subrange_vec_dec v (lo + len - 1) lo).
+unfold slice.
+destruct (sumbool_of_bool _).
+* exfalso.
+ unbool_comparisons.
+ omega.
+* destruct (sumbool_of_bool _).
+ + exfalso.
+ unbool_comparisons.
+ omega.
+ + f_equal.
+ f_equal.
+*)
+
+Import ListNotations.
+Definition count_leading_zeros {N : Z} (x : mword N) `{ArithFact (N >= 1)}
+: {n : Z & ArithFact (0 <= n /\ n <= N)} :=
+ let r : {n : Z & ArithFact (0 <= n /\ n <= N)} := build_ex N in
+ foreach_Z_up 0 (N - 1) 1 r
+ (fun i _ r =>
+ (if ((eq_vec (vec_of_bits [access_vec_dec x i] : mword 1) (vec_of_bits [B1] : mword 1)))
+ then build_ex
+ (Z.sub (Z.sub (length_mword x) i) 1)
+ : {n : Z & ArithFact (0 <= n /\ n <= N)}
+ else r))
+ .
+
+Definition prerr_bits {a} (s : string) (bs : mword a) : unit := tt.
+Definition print_bits {a} (s : string) (bs : mword a) : unit := tt.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_prompt.v b/prover_snapshots/coq/lib/sail/Sail2_prompt.v
new file mode 100644
index 0000000..79bf87e
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_prompt.v
@@ -0,0 +1,229 @@
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+Require Export ZArith.Zwf.
+Require Import List.
+Import ListNotations.
+(*
+
+val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let rec iter_aux i f xs = match xs with
+ | x :: xs -> f i x >> iter_aux (i + 1) f xs
+ | [] -> return ()
+ end
+
+declare {isabelle} termination_argument iter_aux = automatic
+
+val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iteri f xs = iter_aux 0 f xs
+
+val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iter f xs = iteri (fun _ x -> f x) xs
+
+val foreachM : forall 'a 'rv 'vars 'e.
+ list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint foreachM {a rv Vars e} (l : list a) (vars : Vars) (body : a -> Vars -> monad rv Vars e) : monad rv Vars e :=
+match l with
+| [] => returnm vars
+| (x :: xs) =>
+ body x vars >>= fun vars =>
+ foreachM xs vars body
+end.
+
+Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+ if sumbool_of_bool (from + off <=? to) then
+ match n with
+ | O => returnm vars
+ | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_up' from to step (off + step) n vars body
+ end
+ else returnm vars.
+
+Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+ if sumbool_of_bool (to <=? from + off) then
+ match n with
+ | O => returnm vars
+ | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_down' from to step (off - step) n vars body
+ end
+ else returnm vars.
+
+Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (0 < step)} :=
+ foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (0 < step)} :=
+ foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*declare {isabelle} termination_argument foreachM = automatic*)
+
+Definition genlistM {A RV E} (f : nat -> monad RV A E) (n : nat) : monad RV (list A) E :=
+ let indices := List.seq 0 n in
+ foreachM indices [] (fun n xs => (f n >>= (fun x => returnm (xs ++ [x])))).
+
+(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition and_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then r else returnm false).
+
+Definition and_boolMP {rv E} {P Q R:bool->Prop} (x : monad rv {b:bool & ArithFact (P b)} E) (y : monad rv {b:bool & ArithFact (Q b)} E)
+ `{H:ArithFact (forall l r, P l -> (l = true -> Q r) -> R (andb l r))}
+ : monad rv {b:bool & ArithFact (R b)} E.
+refine (
+ x >>= fun '(existT _ x (Build_ArithFact _ p)) => (if x return P x -> _ then
+ fun p => y >>= fun '(existT _ y _) => returnm (existT _ y _)
+ else fun p => returnm (existT _ false _)) p
+).
+* constructor. destruct H. destruct a0. change y with (andb true y). auto.
+* constructor. destruct H. change false with (andb false false). apply fact.
+ assumption.
+ congruence.
+Defined.
+
+(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition or_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then returnm true else r).
+Definition or_boolMP {rv E} {P Q R:bool -> Prop} (l : monad rv {b : bool & ArithFact (P b)} E) (r : monad rv {b : bool & ArithFact (Q b)} E)
+ `{ArithFact (forall l r, P l -> (l = false -> Q r) -> R (orb l r))}
+ : monad rv {b : bool & ArithFact (R b)} E.
+refine (
+ l >>= fun '(existT _ l (Build_ArithFact _ p)) =>
+ (if l return P l -> _ then fun p => returnm (existT _ true _)
+ else fun p => r >>= fun '(existT _ r _) => returnm (existT _ r _)) p
+).
+* constructor. destruct H. change true with (orb true true). apply fact. assumption. congruence.
+* constructor. destruct H. destruct a0. change r with (orb false r). auto.
+Defined.
+
+Definition build_trivial_ex {rv E} {T:Type} (x:monad rv T E) : monad rv {x : T & ArithFact True} E :=
+ x >>= fun x => returnm (existT _ x (Build_ArithFact _ I)).
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_fail {rv E} (b : bitU) : monad rv bool E :=
+match b with
+ | B0 => returnm false
+ | B1 => returnm true
+ | BU => Fail "bool_of_bitU"
+end.
+
+(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_oracle {rv E} (b : bitU) : monad rv bool E :=
+match b with
+ | B0 => returnm false
+ | B1 => returnm true
+ | BU => undefined_bool tt
+end.
+
+(* For termination of recursive functions. We don't name assertions, so use
+ the type class mechanism to find it. *)
+Definition _limit_reduces {_limit} (_acc:Acc (Zwf 0) _limit) `{ArithFact (_limit >= 0)} : Acc (Zwf 0) (_limit - 1).
+refine (Acc_inv _acc _).
+destruct H.
+red.
+omega.
+Defined.
+
+(* A version of well-foundedness of measures with a guard to ensure that
+ definitions can be reduced without inspecting proofs, based on a coq-club
+ thread featuring Barras, Gonthier and Gregoire, see
+ https://sympa.inria.fr/sympa/arc/coq-club/2007-07/msg00014.html *)
+
+Fixpoint pos_guard_wf {A:Type} {R:A -> A -> Prop} (p:positive) : well_founded R -> well_founded R :=
+ match p with
+ | xH => fun wfR x => Acc_intro x (fun y _ => wfR y)
+ | xO p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F
+wfR) y)
+ | xI p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F
+wfR) y)
+ end.
+
+Definition Zwf_guarded (z:Z) : Acc (Zwf 0) z :=
+ Acc_intro _ (fun y H => match z with
+ | Zpos p => pos_guard_wf p (Zwf_well_founded _) _
+ | Zneg p => pos_guard_wf p (Zwf_well_founded _) _
+ | Z0 => Zwf_well_founded _ _
+ end).
+
+(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+ ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint whileMT' {RV Vars E} limit (vars : Vars) (cond : Vars -> monad RV bool E) (body : Vars -> monad RV Vars E) (acc : Acc (Zwf 0) limit) : monad RV Vars E :=
+ if Z_ge_dec limit 0 then
+ cond vars >>= fun cond_val =>
+ if cond_val then
+ body vars >>= fun vars => whileMT' (limit - 1) vars cond body (_limit_reduces acc)
+ else returnm vars
+ else Fail "Termination limit reached".
+
+Definition whileMT {RV Vars E} (vars : Vars) (measure : Vars -> Z) (cond : Vars -> monad RV bool E) (body : Vars -> monad RV Vars E) : monad RV Vars E :=
+ let limit := measure vars in
+ whileMT' limit vars cond body (Zwf_guarded limit).
+
+(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+ ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint untilMT' {RV Vars E} limit (vars : Vars) (cond : Vars -> monad RV bool E) (body : Vars -> monad RV Vars E) (acc : Acc (Zwf 0) limit) : monad RV Vars E :=
+ if Z_ge_dec limit 0 then
+ body vars >>= fun vars =>
+ cond vars >>= fun cond_val =>
+ if cond_val then returnm vars else untilMT' (limit - 1) vars cond body (_limit_reduces acc)
+ else Fail "Termination limit reached".
+
+Definition untilMT {RV Vars E} (vars : Vars) (measure : Vars -> Z) (cond : Vars -> monad RV bool E) (body : Vars -> monad RV Vars E) : monad RV Vars E :=
+ let limit := measure vars in
+ untilMT' limit vars cond body (Zwf_guarded limit).
+
+(*let write_two_regs r1 r2 vec =
+ let is_inc =
+ let is_inc_r1 = is_inc_of_reg r1 in
+ let is_inc_r2 = is_inc_of_reg r2 in
+ let () = ensure (is_inc_r1 = is_inc_r2)
+ "write_two_regs called with vectors of different direction" in
+ is_inc_r1 in
+
+ let (size_r1 : integer) = size_of_reg r1 in
+ let (start_vec : integer) = get_start vec in
+ let size_vec = length vec in
+ let r1_v =
+ if is_inc
+ then slice vec start_vec (size_r1 - start_vec - 1)
+ else slice vec start_vec (start_vec - size_r1 - 1) in
+ let r2_v =
+ if is_inc
+ then slice vec (size_r1 - start_vec) (size_vec - start_vec)
+ else slice vec (start_vec - size_r1) (start_vec - size_vec) in
+ write_reg r1 r1_v >> write_reg r2 r2_v*)
+
+Definition choose_bools {RV E} (descr : string) (n : nat) : monad RV (list bool) E :=
+ genlistM (fun _ => choose_bool descr) n.
+
+Definition choose {RV A E} (descr : string) (xs : list A) : monad RV A E :=
+ (* Use sufficiently many nondeterministically chosen bits and convert into an
+ index into the list *)
+ choose_bools descr (List.length xs) >>= fun bs =>
+ let idx := ((nat_of_bools bs) mod List.length xs)%nat in
+ match List.nth_error xs idx with
+ | Some x => returnm x
+ | None => Fail ("choose " ++ descr)
+ end.
+
+Definition internal_pick {rv a e} (xs : list a) : monad rv a e :=
+ choose "internal_pick" xs.
+
+Fixpoint undefined_word_nat {rv e} n : monad rv (Word.word n) e :=
+ match n with
+ | O => returnm Word.WO
+ | S m =>
+ choose_bool "undefined_word_nat" >>= fun b =>
+ undefined_word_nat m >>= fun t =>
+ returnm (Word.WS b t)
+ end.
+
+Definition undefined_bitvector {rv e} n `{ArithFact (n >= 0)} : monad rv (mword n) e :=
+ undefined_word_nat (Z.to_nat n) >>= fun w =>
+ returnm (word_to_mword w).
+
+(* If we need to build an existential after a monadic operation, assume that
+ we can do it entirely from the type. *)
+
+Definition build_ex_m {rv e} {T:Type} (x:monad rv T e) {P:T -> Prop} `{H:forall x, ArithFact (P x)} : monad rv {x : T & ArithFact (P x)} e :=
+ x >>= fun y => returnm (existT _ y (H y)).
+
+Definition projT1_m {rv e} {T:Type} {P:T -> Prop} (x: monad rv {x : T & P x} e) : monad rv T e :=
+ x >>= fun y => returnm (projT1 y).
+
+Definition derive_m {rv e} {T:Type} {P Q:T -> Prop} (x : monad rv {x : T & P x} e) `{forall x, ArithFact (P x) -> ArithFact (Q x)} : monad rv {x : T & (ArithFact (Q x))} e :=
+ x >>= fun y => returnm (build_ex (projT1 y)).
diff --git a/prover_snapshots/coq/lib/sail/Sail2_prompt_monad.v b/prover_snapshots/coq/lib/sail/Sail2_prompt_monad.v
new file mode 100644
index 0000000..b26a2ff
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_prompt_monad.v
@@ -0,0 +1,367 @@
+Require Import String.
+(*Require Import Sail_impl_base*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require bbv.Word.
+Import ListNotations.
+
+Definition register_name := string.
+Definition address := list bitU.
+
+Inductive monad regval a e :=
+ | Done : a -> monad regval a e
+ (* Read a number of bytes from memory, returned in little endian order,
+ with or without a tag. The first nat specifies the address, the second
+ the number of bytes. *)
+ | Read_mem : read_kind -> nat -> nat -> (list memory_byte -> monad regval a e) -> monad regval a e
+ | Read_memt : read_kind -> nat -> nat -> ((list memory_byte * bitU) -> monad regval a e) -> monad regval a e
+ (* Tell the system a write is imminent, at the given address and with the
+ given size. *)
+ | Write_ea : write_kind -> nat -> nat -> monad regval a e -> monad regval a e
+ (* Request the result : store-exclusive *)
+ | Excl_res : (bool -> monad regval a e) -> monad regval a e
+ (* Request to write a memory value of the given size at the given address,
+ with or without a tag. *)
+ | Write_mem : write_kind -> nat -> nat -> list memory_byte -> (bool -> monad regval a e) -> monad regval a e
+ | Write_memt : write_kind -> nat -> nat -> list memory_byte -> bitU -> (bool -> monad regval a e) -> monad regval a e
+ (* Tell the system to dynamically recalculate dependency footprint *)
+ | Footprint : monad regval a e -> monad regval a e
+ (* Request a memory barrier *)
+ | Barrier : barrier_kind -> monad regval a e -> monad regval a e
+ (* Request to read register, will track dependency when mode.track_values *)
+ | Read_reg : register_name -> (regval -> monad regval a e) -> monad regval a e
+ (* Request to write register *)
+ | Write_reg : register_name -> regval -> monad regval a e -> monad regval a e
+ (* Request to choose a Boolean, e.g. to resolve an undefined bit. The string
+ argument may be used to provide information to the system about what the
+ Boolean is going to be used for. *)
+ | Choose : string -> (bool -> monad regval a e) -> monad regval a e
+ (* Print debugging or tracing information *)
+ | Print : string -> monad regval a e -> monad regval a e
+ (*Result of a failed assert with possible error message to report*)
+ | Fail : string -> monad regval a e
+ (* Exception of type e *)
+ | Exception : e -> monad regval a e.
+
+Arguments Done [_ _ _].
+Arguments Read_mem [_ _ _].
+Arguments Read_memt [_ _ _].
+Arguments Write_ea [_ _ _].
+Arguments Excl_res [_ _ _].
+Arguments Write_mem [_ _ _].
+Arguments Write_memt [_ _ _].
+Arguments Footprint [_ _ _].
+Arguments Barrier [_ _ _].
+Arguments Read_reg [_ _ _].
+Arguments Write_reg [_ _ _].
+Arguments Choose [_ _ _].
+Arguments Print [_ _ _].
+Arguments Fail [_ _ _].
+Arguments Exception [_ _ _].
+
+Inductive event {regval} :=
+ | E_read_mem : read_kind -> nat -> nat -> list memory_byte -> event
+ | E_read_memt : read_kind -> nat -> nat -> (list memory_byte * bitU) -> event
+ | E_write_mem : write_kind -> nat -> nat -> list memory_byte -> bool -> event
+ | E_write_memt : write_kind -> nat -> nat -> list memory_byte -> bitU -> bool -> event
+ | E_write_ea : write_kind -> nat -> nat -> event
+ | E_excl_res : bool -> event
+ | E_barrier : barrier_kind -> event
+ | E_footprint : event
+ | E_read_reg : register_name -> regval -> event
+ | E_write_reg : register_name -> regval -> event
+ | E_choose : string -> bool -> event
+ | E_print : string -> event.
+Arguments event : clear implicits.
+
+Definition trace regval := list (event regval).
+
+(*val return : forall rv a e. a -> monad rv a e*)
+Definition returnm {rv A E} (a : A) : monad rv A E := Done a.
+
+(*val bind : forall rv a b e. monad rv a e -> (a -> monad rv b e) -> monad rv b e*)
+Fixpoint bind {rv A B E} (m : monad rv A E) (f : A -> monad rv B E) := match m with
+ | Done a => f a
+ | Read_mem rk a sz k => Read_mem rk a sz (fun v => bind (k v) f)
+ | Read_memt rk a sz k => Read_memt rk a sz (fun v => bind (k v) f)
+ | Write_mem wk a sz v k => Write_mem wk a sz v (fun v => bind (k v) f)
+ | Write_memt wk a sz v t k => Write_memt wk a sz v t (fun v => bind (k v) f)
+ | Read_reg descr k => Read_reg descr (fun v => bind (k v) f)
+ | Excl_res k => Excl_res (fun v => bind (k v) f)
+ | Choose descr k => Choose descr (fun v => bind (k v) f)
+ | Write_ea wk a sz k => Write_ea wk a sz (bind k f)
+ | Footprint k => Footprint (bind k f)
+ | Barrier bk k => Barrier bk (bind k f)
+ | Write_reg r v k => Write_reg r v (bind k f)
+ | Print msg k => Print msg (bind k f)
+ | Fail descr => Fail descr
+ | Exception e => Exception e
+end.
+
+Notation "m >>= f" := (bind m f) (at level 50, left associativity).
+(*val (>>) : forall rv b e. monad rv unit e -> monad rv b e -> monad rv b e*)
+Definition bind0 {rv A E} (m : monad rv unit E) (n : monad rv A E) :=
+ m >>= fun (_ : unit) => n.
+Notation "m >> n" := (bind0 m n) (at level 50, left associativity).
+
+(*val exit : forall rv a e. unit -> monad rv a e*)
+Definition exit {rv A E} (_ : unit) : monad rv A E := Fail "exit".
+
+(*val choose_bool : forall 'rv 'e. string -> monad 'rv bool 'e*)
+Definition choose_bool {rv E} descr : monad rv bool E := Choose descr returnm.
+
+(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*)
+Definition undefined_bool {rv e} (_:unit) : monad rv bool e := choose_bool "undefined_bool".
+
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val assert_exp : forall rv e. bool -> string -> monad rv unit e*)
+Definition assert_exp {rv E} (exp :bool) msg : monad rv unit E :=
+ if exp then Done tt else Fail msg.
+
+Definition assert_exp' {rv E} (exp :bool) msg : monad rv (exp = true) E :=
+ if exp return monad rv (exp = true) E then Done eq_refl else Fail msg.
+Definition bindH {rv A P E} (m : monad rv P E) (n : monad rv A E) :=
+ m >>= fun (H : P) => n.
+Notation "m >>> n" := (bindH m n) (at level 50, left associativity).
+
+(*val throw : forall rv a e. e -> monad rv a e*)
+Definition throw {rv A E} e : monad rv A E := Exception e.
+
+(*val try_catch : forall rv a e1 e2. monad rv a e1 -> (e1 -> monad rv a e2) -> monad rv a e2*)
+Fixpoint try_catch {rv A E1 E2} (m : monad rv A E1) (h : E1 -> monad rv A E2) := match m with
+ | Done a => Done a
+ | Read_mem rk a sz k => Read_mem rk a sz (fun v => try_catch (k v) h)
+ | Read_memt rk a sz k => Read_memt rk a sz (fun v => try_catch (k v) h)
+ | Write_mem wk a sz v k => Write_mem wk a sz v (fun v => try_catch (k v) h)
+ | Write_memt wk a sz v t k => Write_memt wk a sz v t (fun v => try_catch (k v) h)
+ | Read_reg descr k => Read_reg descr (fun v => try_catch (k v) h)
+ | Excl_res k => Excl_res (fun v => try_catch (k v) h)
+ | Choose descr k => Choose descr (fun v => try_catch (k v) h)
+ | Write_ea wk a sz k => Write_ea wk a sz (try_catch k h)
+ | Footprint k => Footprint (try_catch k h)
+ | Barrier bk k => Barrier bk (try_catch k h)
+ | Write_reg r v k => Write_reg r v (try_catch k h)
+ | Print msg k => Print msg (try_catch k h)
+ | Fail descr => Fail descr
+ | Exception e => h e
+end.
+
+(* For early return, we abuse exceptions by throwing and catching
+ the return value. The exception type is "either r e", where "inr e"
+ represents a proper exception and "inl r" an early return : value "r". *)
+Definition monadR rv a r e := monad rv a (sum r e).
+
+(*val early_return : forall rv a r e. r -> monadR rv a r e*)
+Definition early_return {rv A R E} (r : R) : monadR rv A R E := throw (inl r).
+
+(*val catch_early_return : forall rv a e. monadR rv a a e -> monad rv a e*)
+Definition catch_early_return {rv A E} (m : monadR rv A A E) :=
+ try_catch m
+ (fun r => match r with
+ | inl a => returnm a
+ | inr e => throw e
+ end).
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftR : forall rv a r e. monad rv a e -> monadR rv a r e*)
+Definition liftR {rv A R E} (m : monad rv A E) : monadR rv A R E :=
+ try_catch m (fun e => throw (inr e)).
+
+(* Catch exceptions in the presence : early returns *)
+(*val try_catchR : forall rv a r e1 e2. monadR rv a r e1 -> (e1 -> monadR rv a r e2) -> monadR rv a r e2*)
+Definition try_catchR {rv A R E1 E2} (m : monadR rv A R E1) (h : E1 -> monadR rv A R E2) :=
+ try_catch m
+ (fun r => match r with
+ | inl r => throw (inl r)
+ | inr e => h e
+ end).
+
+(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*)
+Definition maybe_fail {rv A E} msg (x : option A) : monad rv A E :=
+match x with
+ | Some a => returnm a
+ | None => Fail msg
+end.
+
+(*val read_memt_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte * bitU) 'e*)
+Definition read_memt_bytes {rv A E} rk (addr : mword A) sz : monad rv (list memory_byte * bitU) E :=
+ Read_memt rk (Word.wordToNat (get_word addr)) (Z.to_nat sz) returnm.
+
+(*val read_memt : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv ('b * bitU) 'e*)
+Definition read_memt {rv A B E} `{ArithFact (B >= 0)} rk (addr : mword A) sz : monad rv (mword B * bitU) E :=
+ bind
+ (read_memt_bytes rk addr sz)
+ (fun '(bytes, tag) =>
+ match of_bits (bits_of_mem_bytes bytes) with
+ | Some v => returnm (v, tag)
+ | None => Fail "bits_of_mem_bytes"
+ end).
+
+(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*)
+Definition read_mem_bytes {rv A E} rk (addr : mword A) sz : monad rv (list memory_byte) E :=
+ Read_mem rk (Word.wordToNat (get_word addr)) (Z.to_nat sz) returnm.
+
+(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*)
+Definition read_mem {rv A B E} `{ArithFact (B >= 0)} rk (addrsz : Z) (addr : mword A) sz : monad rv (mword B) E :=
+ bind
+ (read_mem_bytes rk addr sz)
+ (fun bytes =>
+ maybe_fail "bits_of_mem_bytes" (of_bits (bits_of_mem_bytes bytes))).
+
+(*val excl_result : forall rv e. unit -> monad rv bool e*)
+Definition excl_result {rv e} (_:unit) : monad rv bool e :=
+ let k successful := (returnm successful) in
+ Excl_res k.
+
+Definition write_mem_ea {rv a E} wk (addrsz : Z) (addr: mword a) sz : monad rv unit E :=
+ Write_ea wk (Word.wordToNat (get_word addr)) (Z.to_nat sz) (Done tt).
+
+(*val write_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b =>
+ write_kind -> integer -> 'a -> integer -> 'b -> monad 'rv bool 'e*)
+Definition write_mem {rv a b E} wk (addrsz : Z) (addr : mword a) sz (v : mword b) : monad rv bool E :=
+ match (mem_bytes_of_bits v, Word.wordToNat (get_word addr)) with
+ | (Some v, addr) =>
+ Write_mem wk addr (Z.to_nat sz) v returnm
+ | _ => Fail "write_mem"
+ end.
+
+(*val write_memt : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> bitU -> monad 'rv bool 'e*)
+Definition write_memt {rv a b E} wk (addr : mword a) sz (v : mword b) tag : monad rv bool E :=
+ match (mem_bytes_of_bits v, Word.wordToNat (get_word addr)) with
+ | (Some v, addr) =>
+ Write_memt wk addr (Z.to_nat sz) v tag returnm
+ | _ => Fail "write_mem"
+ end.
+
+Definition read_reg {s rv a e} (reg : register_ref s rv a) : monad rv a e :=
+ let k v :=
+ match reg.(of_regval) v with
+ | Some v => Done v
+ | None => Fail "read_reg: unrecognised value"
+ end
+ in
+ Read_reg reg.(name) k.
+
+(* TODO
+val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e
+let read_reg_range reg i j =
+ read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j))
+
+let read_reg_bit reg i =
+ read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v ->
+ return (extract_only_element v)
+
+let read_reg_field reg regfield =
+ read_reg_aux (external_reg_field_whole reg regfield)
+
+let read_reg_bitfield reg regfield =
+ read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
+ return (extract_only_element v)*)
+
+Definition reg_deref {s rv a e} := @read_reg s rv a e.
+
+(*Parameter write_reg : forall {s rv a e}, register_ref s rv a -> a -> monad rv unit e.*)
+Definition write_reg {s rv a e} (reg : register_ref s rv a) (v : a) : monad rv unit e :=
+ Write_reg reg.(name) (reg.(regval_of) v) (Done tt).
+
+(* TODO
+let write_reg reg v =
+ write_reg_aux (external_reg_whole reg) v
+let write_reg_range reg i j v =
+ write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v
+let write_reg_pos reg i v =
+ let iN = nat_of_int i in
+ write_reg_aux (external_reg_slice reg (iN,iN)) [v]
+let write_reg_bit = write_reg_pos
+let write_reg_field reg regfield v =
+ write_reg_aux (external_reg_field_whole reg regfield.field_name) v
+let write_reg_field_bit reg regfield bit =
+ write_reg_aux (external_reg_field_whole reg regfield.field_name)
+ (Vector [bit] 0 (is_inc_of_reg reg))
+let write_reg_field_range reg regfield i j v =
+ write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v
+let write_reg_field_pos reg regfield i v =
+ write_reg_field_range reg regfield i i [v]
+let write_reg_field_bit = write_reg_field_pos*)
+
+(*val barrier : forall rv e. barrier_kind -> monad rv unit e*)
+Definition barrier {rv e} bk : monad rv unit e := Barrier bk (Done tt).
+
+(*val footprint : forall rv e. unit -> monad rv unit e*)
+Definition footprint {rv e} (_ : unit) : monad rv unit e := Footprint (Done tt).
+
+(* Event traces *)
+
+Local Open Scope bool_scope.
+
+(*val emitEvent : forall 'regval 'a 'e. Eq 'regval => monad 'regval 'a 'e -> event 'regval -> maybe (monad 'regval 'a 'e)*)
+Definition emitEvent {Regval A E} `{forall (x y : Regval), Decidable (x = y)} (m : monad Regval A E) (e : event Regval) : option (monad Regval A E) :=
+ match (e, m) with
+ | (E_read_mem rk a sz v, Read_mem rk' a' sz' k) =>
+ if read_kind_beq rk' rk && Nat.eqb a' a && Nat.eqb sz' sz then Some (k v) else None
+ | (E_read_memt rk a sz vt, Read_memt rk' a' sz' k) =>
+ if read_kind_beq rk' rk && Nat.eqb a' a && Nat.eqb sz' sz then Some (k vt) else None
+ | (E_write_mem wk a sz v r, Write_mem wk' a' sz' v' k) =>
+ if write_kind_beq wk' wk && Nat.eqb a' a && Nat.eqb sz' sz && generic_eq v' v then Some (k r) else None
+ | (E_write_memt wk a sz v tag r, Write_memt wk' a' sz' v' tag' k) =>
+ if write_kind_beq wk' wk && Nat.eqb a' a && Nat.eqb sz' sz && generic_eq v' v && generic_eq tag' tag then Some (k r) else None
+ | (E_read_reg r v, Read_reg r' k) =>
+ if generic_eq r' r then Some (k v) else None
+ | (E_write_reg r v, Write_reg r' v' k) =>
+ if generic_eq r' r && generic_eq v' v then Some k else None
+ | (E_write_ea wk a sz, Write_ea wk' a' sz' k) =>
+ if write_kind_beq wk' wk && Nat.eqb a' a && Nat.eqb sz' sz then Some k else None
+ | (E_barrier bk, Barrier bk' k) =>
+ if barrier_kind_beq bk' bk then Some k else None
+ | (E_print m, Print m' k) =>
+ if generic_eq m' m then Some k else None
+ | (E_excl_res v, Excl_res k) => Some (k v)
+ | (E_choose descr v, Choose descr' k) => if generic_eq descr' descr then Some (k v) else None
+ | (E_footprint, Footprint k) => Some k
+ | _ => None
+end.
+
+Definition option_bind {A B : Type} (a : option A) (f : A -> option B) : option B :=
+match a with
+| Some x => f x
+| None => None
+end.
+
+(*val runTrace : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> maybe (monad 'regval 'a 'e)*)
+Fixpoint runTrace {Regval A E} `{forall (x y : Regval), Decidable (x = y)} (t : trace Regval) (m : monad Regval A E) : option (monad Regval A E) :=
+match t with
+ | [] => Some m
+ | e :: t' => option_bind (emitEvent m e) (runTrace t')
+end.
+
+(*val final : forall 'regval 'a 'e. monad 'regval 'a 'e -> bool*)
+Definition final {Regval A E} (m : monad Regval A E) : bool :=
+match m with
+ | Done _ => true
+ | Fail _ => true
+ | Exception _ => true
+ | _ => false
+end.
+
+(*val hasTrace : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool*)
+Definition hasTrace {Regval A E} `{forall (x y : Regval), Decidable (x = y)} (t : trace Regval) (m : monad Regval A E) : bool :=
+match runTrace t m with
+ | Some m => final m
+ | None => false
+end.
+
+(*val hasException : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool*)
+Definition hasException {Regval A E} `{forall (x y : Regval), Decidable (x = y)} (t : trace Regval) (m : monad Regval A E) :=
+match runTrace t m with
+ | Some (Exception _) => true
+ | _ => false
+end.
+
+(*val hasFailure : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool*)
+Definition hasFailure {Regval A E} `{forall (x y : Regval), Decidable (x = y)} (t : trace Regval) (m : monad Regval A E) :=
+match runTrace t m with
+ | Some (Fail _) => true
+ | _ => false
+end.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_real.v b/prover_snapshots/coq/lib/sail/Sail2_real.v
new file mode 100644
index 0000000..494e36d
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_real.v
@@ -0,0 +1,36 @@
+Require Export Rbase.
+Require Import Reals.
+Require Export ROrderedType.
+Require Import Sail2_values.
+
+(* "Decidable" in a classical sense... *)
+Instance Decidable_eq_real : forall (x y : R), Decidable (x = y) :=
+ Decidable_eq_from_dec Req_dec.
+
+Definition realFromFrac (num denom : Z) : R := Rdiv (IZR num) (IZR denom).
+
+Definition neg_real := Ropp.
+Definition mult_real := Rmult.
+Definition sub_real := Rminus.
+Definition add_real := Rplus.
+Definition div_real := Rdiv.
+Definition sqrt_real := sqrt.
+Definition abs_real := Rabs.
+
+(* Use flocq definitions, but without making the whole library a dependency. *)
+Definition round_down (x : R) := (up x - 1)%Z.
+Definition round_up (x : R) := (- round_down (- x))%Z.
+
+Definition to_real := IZR.
+
+Definition eq_real := Reqb.
+Definition gteq_real (x y : R) : bool := if Rge_dec x y then true else false.
+Definition lteq_real (x y : R) : bool := if Rle_dec x y then true else false.
+Definition gt_real (x y : R) : bool := if Rgt_dec x y then true else false.
+Definition lt_real (x y : R) : bool := if Rlt_dec x y then true else false.
+
+(* Export select definitions from outside of Rbase *)
+Definition pow_real := powerRZ.
+
+Definition print_real (_ : string) (_ : R) : unit := tt.
+Definition prerr_real (_ : string) (_ : R) : unit := tt.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_state.v b/prover_snapshots/coq/lib/sail/Sail2_state.v
new file mode 100644
index 0000000..dc635cb
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_state.v
@@ -0,0 +1,167 @@
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state_monad.
+Import ListNotations.
+
+(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+Fixpoint iterS_aux {RV A E} i (f : Z -> A -> monadS RV unit E) (xs : list A) :=
+ match xs with
+ | x :: xs => f i x >>$ iterS_aux (i + 1) f xs
+ | [] => returnS tt
+ end.
+
+(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+Definition iteriS {RV A E} (f : Z -> A -> monadS RV unit E) (xs : list A) : monadS RV unit E :=
+ iterS_aux 0 f xs.
+
+(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+Definition iterS {RV A E} (f : A -> monadS RV unit E) (xs : list A) : monadS RV unit E :=
+ iteriS (fun _ x => f x) xs.
+
+(*val foreachS : forall 'a 'rv 'vars 'e.
+ list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+Fixpoint foreachS {A RV Vars E} (xs : list A) (vars : Vars) (body : A -> Vars -> monadS RV Vars E) : monadS RV Vars E :=
+ match xs with
+ | [] => returnS vars
+ | x :: xs =>
+ body x vars >>$= fun vars =>
+ foreachS xs vars body
+end.
+
+(*val genlistS : forall 'a 'rv 'e. (nat -> monadS 'rv 'a 'e) -> nat -> monadS 'rv (list 'a) 'e*)
+Definition genlistS {A RV E} (f : nat -> monadS RV A E) n : monadS RV (list A) E :=
+ let indices := List.seq 0 n in
+ foreachS indices [] (fun n xs => (f n >>$= (fun x => returnS (xs ++ [x])))).
+
+(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+Definition and_boolS {RV E} (l r : monadS RV bool E) : monadS RV bool E :=
+ l >>$= (fun l => if l then r else returnS false).
+
+(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+Definition or_boolS {RV E} (l r : monadS RV bool E) : monadS RV bool E :=
+ l >>$= (fun l => if l then returnS true else r).
+
+Definition and_boolSP {rv E} {P Q R:bool->Prop} (x : monadS rv {b:bool & ArithFact (P b)} E) (y : monadS rv {b:bool & ArithFact (Q b)} E)
+ `{H:ArithFact (forall l r, P l -> (l = true -> Q r) -> R (andb l r))}
+ : monadS rv {b:bool & ArithFact (R b)} E.
+refine (
+ x >>$= fun '(existT _ x (Build_ArithFact _ p)) => (if x return P x -> _ then
+ fun p => y >>$= fun '(existT _ y _) => returnS (existT _ y _)
+ else fun p => returnS (existT _ false _)) p
+).
+* constructor. destruct H. destruct a0. change y with (andb true y). auto.
+* constructor. destruct H. change false with (andb false false). apply fact.
+ assumption.
+ congruence.
+Defined.
+Definition or_boolSP {rv E} {P Q R:bool -> Prop} (l : monadS rv {b : bool & ArithFact (P b)} E) (r : monadS rv {b : bool & ArithFact (Q b)} E)
+ `{ArithFact (forall l r, P l -> (l = false -> Q r) -> R (orb l r))}
+ : monadS rv {b : bool & ArithFact (R b)} E.
+refine (
+ l >>$= fun '(existT _ l (Build_ArithFact _ p)) =>
+ (if l return P l -> _ then fun p => returnS (existT _ true _)
+ else fun p => r >>$= fun '(existT _ r _) => returnS (existT _ r _)) p
+).
+* constructor. destruct H. change true with (orb true true). apply fact. assumption. congruence.
+* constructor. destruct H. destruct a0. change r with (orb false r). auto.
+Defined.
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+Definition bool_of_bitU_fail {RV E} (b : bitU) : monadS RV bool E :=
+match b with
+ | B0 => returnS false
+ | B1 => returnS true
+ | BU => failS "bool_of_bitU"
+end.
+
+(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+Definition bool_of_bitU_nondetS {RV E} (b : bitU) : monadS RV bool E :=
+match b with
+ | B0 => returnS false
+ | B1 => returnS true
+ | BU => undefined_boolS tt
+end.
+
+(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*)
+Definition bools_of_bits_nondetS {RV E} bits : monadS RV (list bool) E :=
+ foreachS bits []
+ (fun b bools =>
+ bool_of_bitU_nondetS b >>$= (fun b =>
+ returnS (bools ++ [b]))).
+
+(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+Definition of_bits_nondetS {RV A E} bits `{ArithFact (A >= 0)} : monadS RV (mword A) E :=
+ bools_of_bits_nondetS bits >>$= (fun bs =>
+ returnS (of_bools bs)).
+
+(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+Definition of_bits_failS {RV A E} bits `{ArithFact (A >= 0)} : monadS RV (mword A) E :=
+ maybe_failS "of_bits" (of_bits bits).
+
+(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e
+let mword_nondetS () =
+ bools_of_bits_nondetS (repeat [BU] (integerFromNat size)) >>$= (fun bs ->
+ returnS (wordFromBitlist bs))
+
+
+val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec whileS vars cond body s =
+ (cond vars >>$= (fun cond_val s' ->
+ if cond_val then
+ (body vars >>$= (fun vars s'' -> whileS vars cond body s'')) s'
+ else returnS vars s')) s
+
+val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec untilS vars cond body s =
+ (body vars >>$= (fun vars s' ->
+ (cond vars >>$= (fun cond_val s'' ->
+ if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s
+*)
+
+Fixpoint whileST' {RV Vars E} limit (vars : Vars) (cond : Vars -> monadS RV bool E) (body : Vars -> monadS RV Vars E) (acc : Acc (Zwf 0) limit) : monadS RV Vars E :=
+ if Z_ge_dec limit 0 then
+ cond vars >>$= fun cond_val =>
+ if cond_val then
+ body vars >>$= fun vars => whileST' (limit - 1) vars cond body (_limit_reduces acc)
+ else returnS vars
+ else failS "Termination limit reached".
+
+Definition whileST {RV Vars E} (vars : Vars) measure (cond : Vars -> monadS RV bool E) (body : Vars -> monadS RV Vars E) : monadS RV Vars E :=
+ let limit := measure vars in
+ whileST' limit vars cond body (Zwf_guarded limit).
+
+(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+ ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint untilST' {RV Vars E} limit (vars : Vars) (cond : Vars -> monadS RV bool E) (body : Vars -> monadS RV Vars E) (acc : Acc (Zwf 0) limit) : monadS RV Vars E :=
+ if Z_ge_dec limit 0 then
+ body vars >>$= fun vars =>
+ cond vars >>$= fun cond_val =>
+ if cond_val then returnS vars else untilST' (limit - 1) vars cond body (_limit_reduces acc)
+ else failS "Termination limit reached".
+
+Definition untilST {RV Vars E} (vars : Vars) measure (cond : Vars -> monadS RV bool E) (body : Vars -> monadS RV Vars E) : monadS RV Vars E :=
+ let limit := measure vars in
+ untilST' limit vars cond body (Zwf_guarded limit).
+
+
+(*val choose_boolsS : forall 'rv 'e. nat -> monadS 'rv (list bool) 'e*)
+Definition choose_boolsS {RV E} n : monadS RV (list bool) E :=
+ genlistS (fun _ => choose_boolS tt) n.
+
+(* TODO: Replace by chooseS and prove equivalence to prompt monad version *)
+(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*)
+Definition internal_pickS {RV A E} (xs : list A) : monadS RV A E :=
+ (* Use sufficiently many nondeterministically chosen bits and convert into an
+ index into the list *)
+ choose_boolsS (List.length xs) >>$= fun bs =>
+ let idx := ((nat_of_bools bs) mod List.length xs)%nat in
+ match List.nth_error xs idx with
+ | Some x => returnS x
+ | None => failS "choose internal_pick"
+ end.
+
+
diff --git a/prover_snapshots/coq/lib/sail/Sail2_state_lemmas.v b/prover_snapshots/coq/lib/sail/Sail2_state_lemmas.v
new file mode 100644
index 0000000..c07016d
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_state_lemmas.v
@@ -0,0 +1,819 @@
+Require Import Sail2_values Sail2_prompt_monad Sail2_prompt Sail2_state_monad Sail2_state Sail2_state Sail2_state_lifting.
+Require Import Sail2_state_monad_lemmas.
+
+Local Open Scope equiv_scope.
+
+(* Monad lifting *)
+
+Lemma liftState_bind Regval Regs A B E {r : Sail2_values.register_accessors Regs Regval} {m : monad Regval A E} {f : A -> monad Regval B E} :
+ liftState r (bind m f) === bindS (liftState r m) (fun x => liftState r (f x)).
+induction m; simpl; autorewrite with state; auto using bindS_cong.
+Qed.
+Hint Rewrite liftState_bind : liftState.
+
+(* TODO: I want a general tactic for this, but abstracting the hint db out
+ appears to break.
+ This does beta reduction when no rules apply to try and allow more rules to apply
+ (e.g., the application of f to x in the above lemma may introduce a beta redex). *)
+Ltac rewrite_liftState := rewrite_strat topdown (choice (progress try hints liftState) progress eval cbn beta).
+
+Lemma liftState_return Regval Regs A E {r : Sail2_values.register_accessors Regs Regval} {a :A} :
+ liftState (E:=E) r (returnm a) = returnS a.
+reflexivity.
+Qed.
+Hint Rewrite liftState_return : liftState.
+
+(*
+Lemma Value_liftState_Run:
+ List.In (Value a, s') (liftState r m s)
+ exists t, Run m t a.
+ by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>;
+ simp add: failS_def throwS_def returnS_def del: read_regvalS.simps;
+ blast elim: Value_bindS_elim)
+
+lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra]
+*)
+Lemma liftState_if_distrib Regs Regval A E {r x y} {c : bool} :
+ @liftState Regs Regval A E r (if c then x else y) = if c then liftState r x else liftState r y.
+destruct c; reflexivity.
+Qed.
+Lemma liftState_if_distrib_sumbool {Regs Regval A E P Q r x y} {c : sumbool P Q} :
+ @liftState Regs Regval A E r (if c then x else y) = if c then liftState r x else liftState r y.
+destruct c; reflexivity.
+Qed.
+
+Lemma Value_bindS_iff {Regs A B E} {f : A -> monadS Regs B E} {b m s s''} :
+ List.In (Value b, s'') (bindS m f s) <-> (exists a s', List.In (Value a, s') (m s) /\ List.In (Value b, s'') (f a s')).
+split.
+* intro H.
+ apply bindS_cases in H.
+ destruct H as [(? & ? & ? & [= <-] & ? & ?) | [(? & [= <-] & ?) | (? & ? & ? & [= <-] & ? & ?)]];
+ eauto.
+* intros (? & ? & ? & ?).
+ eauto with bindS_intros.
+Qed.
+
+Lemma Ex_bindS_iff {Regs A B E} {f : A -> monadS Regs B E} {m e s s''} :
+ List.In (Ex e, s'') (bindS m f s) <-> List.In (Ex e, s'') (m s) \/ (exists a s', List.In (Value a, s') (m s) /\ List.In (Ex e, s'') (f a s')).
+split.
+* intro H.
+ apply bindS_cases in H.
+ destruct H as [(? & ? & ? & [= <-] & ? & ?) | [(? & [= <-] & ?) | (? & ? & ? & [= <-] & ? & ?)]];
+ eauto.
+* intros [H | (? & ? & H1 & H2)];
+ eauto with bindS_intros.
+Qed.
+
+Lemma liftState_throw Regs Regval A E {r} {e : E} :
+ @liftState Regval Regs A E r (throw e) = throwS e.
+reflexivity.
+Qed.
+Lemma liftState_assert Regs Regval E {r c msg} :
+ @liftState Regval Regs _ E r (assert_exp c msg) = assert_expS c msg.
+destruct c; reflexivity.
+Qed.
+Lemma liftState_exit Regs Regval A E r :
+ @liftState Regval Regs A E r (exit tt) = exitS tt.
+reflexivity.
+Qed.
+Lemma liftState_exclResult Regs Regval E r :
+ @liftState Regs Regval _ E r (excl_result tt) = excl_resultS tt.
+reflexivity.
+Qed.
+Lemma liftState_barrier Regs Regval E r bk :
+ @liftState Regs Regval _ E r (barrier bk) = returnS tt.
+reflexivity.
+Qed.
+Lemma liftState_footprint Regs Regval E r :
+ @liftState Regs Regval _ E r (footprint tt) = returnS tt.
+reflexivity.
+Qed.
+Lemma liftState_choose_bool Regs Regval E r descr :
+ @liftState Regs Regval _ E r (choose_bool descr) = choose_boolS tt.
+reflexivity.
+Qed.
+(*declare undefined_boolS_def[simp]*)
+Lemma liftState_undefined Regs Regval E r :
+ @liftState Regs Regval _ E r (undefined_bool tt) = undefined_boolS tt.
+reflexivity.
+Qed.
+Lemma liftState_maybe_fail Regs Regval A E r msg x :
+ @liftState Regs Regval A E r (maybe_fail msg x) = maybe_failS msg x.
+destruct x; reflexivity.
+Qed.
+Lemma liftState_and_boolM Regs Regval E r x y :
+ @liftState Regs Regval _ E r (and_boolM x y) === and_boolS (liftState r x) (liftState r y).
+unfold and_boolM, and_boolS.
+rewrite liftState_bind.
+apply bindS_cong; auto.
+intros. rewrite liftState_if_distrib.
+reflexivity.
+Qed.
+Lemma liftState_and_boolMP Regs Regval E P Q R r x y H :
+ @liftState Regs Regval _ E r (@and_boolMP _ _ P Q R x y H) === and_boolSP (liftState r x) (liftState r y).
+unfold and_boolMP, and_boolSP.
+rewrite liftState_bind.
+apply bindS_cong; auto.
+intros [[|] [A]].
+* rewrite liftState_bind;
+ simpl;
+ apply bindS_cong; auto;
+ intros [a' A'];
+ rewrite liftState_return;
+ reflexivity.
+* rewrite liftState_return.
+ reflexivity.
+Qed.
+
+Lemma liftState_or_boolM Regs Regval E r x y :
+ @liftState Regs Regval _ E r (or_boolM x y) === or_boolS (liftState r x) (liftState r y).
+unfold or_boolM, or_boolS.
+rewrite liftState_bind.
+apply bindS_cong; auto.
+intros. rewrite liftState_if_distrib.
+reflexivity.
+Qed.
+Lemma liftState_or_boolMP Regs Regval E P Q R r x y H :
+ @liftState Regs Regval _ E r (@or_boolMP _ _ P Q R x y H) === or_boolSP (liftState r x) (liftState r y).
+unfold or_boolMP, or_boolSP.
+rewrite liftState_bind.
+simpl.
+apply bindS_cong; auto.
+intros [[|] [A]].
+* rewrite liftState_return.
+ reflexivity.
+* rewrite liftState_bind;
+ simpl;
+ apply bindS_cong; auto;
+ intros [a' A'];
+ rewrite liftState_return;
+ reflexivity.
+Qed.
+Hint Rewrite liftState_throw liftState_assert liftState_exit liftState_exclResult
+ liftState_barrier liftState_footprint liftState_choose_bool
+ liftState_undefined liftState_maybe_fail
+ liftState_and_boolM liftState_and_boolMP
+ liftState_or_boolM liftState_or_boolMP
+ : liftState.
+
+Lemma liftState_try_catch Regs Regval A E1 E2 r m h :
+ @liftState Regs Regval A E2 r (try_catch (E1 := E1) m h) === try_catchS (liftState r m) (fun e => liftState r (h e)).
+induction m; intros; simpl; autorewrite with state;
+solve
+[ auto
+| erewrite try_catchS_bindS_no_throw; intros;
+ only 2,3: (autorewrite with ignore_throw; reflexivity);
+ apply bindS_cong; auto
+].
+Qed.
+Hint Rewrite liftState_try_catch : liftState.
+
+Lemma liftState_early_return Regs Regval A R E r x :
+ liftState (Regs := Regs) r (@early_return Regval A R E x) = early_returnS x.
+reflexivity.
+Qed.
+Hint Rewrite liftState_early_return : liftState.
+
+Lemma liftState_catch_early_return (*[liftState_simp]:*) Regs Regval A E r m :
+ liftState (Regs := Regs) r (@catch_early_return Regval A E m) === catch_early_returnS (liftState r m).
+unfold catch_early_return, catch_early_returnS.
+rewrite_liftState.
+apply try_catchS_cong; auto.
+intros [a | e] s'; auto.
+Qed.
+Hint Rewrite liftState_catch_early_return : liftState.
+
+Lemma liftState_liftR Regs Regval A R E r m :
+ liftState (Regs := Regs) r (@liftR Regval A R E m) === liftRS (liftState r m).
+unfold liftR, liftRS.
+rewrite_liftState.
+reflexivity.
+Qed.
+Hint Rewrite liftState_liftR : liftState.
+
+Lemma liftState_try_catchR Regs Regval A R E1 E2 r m h :
+ liftState (Regs := Regs) r (@try_catchR Regval A R E1 E2 m h) === try_catchRS (liftState r m) (fun x => liftState r (h x)).
+unfold try_catchR, try_catchRS. rewrite_liftState.
+apply try_catchS_cong; auto.
+intros [r' | e] s'; auto.
+Qed.
+Hint Rewrite liftState_try_catchR : liftState.
+(*
+Lemma liftState_bool_of_bitU_nondet Regs Regval :
+ "liftState r (bool_of_bitU_nondet b) = bool_of_bitU_nondetS b"
+ by (cases b; auto simp: bool_of_bitU_nondet_def bool_of_bitU_nondetS_def liftState_simp)
+Hint Rewrite liftState_bool_of_bitU_nondet : liftState.
+*)
+Lemma liftState_read_memt Regs Regval A B E H rk a sz r :
+ liftState (Regs := Regs) r (@read_memt Regval A B E H rk a sz) === read_memtS rk a sz.
+unfold read_memt, read_memt_bytes, read_memtS, maybe_failS. simpl.
+apply bindS_cong; auto.
+intros [byte bit].
+destruct (option_map _); auto.
+Qed.
+Hint Rewrite liftState_read_memt : liftState.
+
+Lemma liftState_read_mem Regs Regval A B E H rk asz a sz r :
+ liftState (Regs := Regs) r (@read_mem Regval A B E H rk asz a sz) === read_memS rk a sz.
+unfold read_mem, read_memS, read_memtS. simpl.
+unfold read_mem_bytesS, read_memt_bytesS.
+repeat rewrite bindS_assoc.
+apply bindS_cong; auto.
+intros [ bytes | ]; auto. simpl.
+apply bindS_cong; auto.
+intros [byte bit].
+rewrite bindS_returnS_left. rewrite_liftState.
+destruct (option_map _); auto.
+Qed.
+Hint Rewrite liftState_read_mem : liftState.
+
+Lemma liftState_write_mem_ea Regs Regval A E rk asz a sz r :
+ liftState (Regs := Regs) r (@write_mem_ea Regval A E rk asz a sz) = returnS tt.
+reflexivity.
+Qed.
+Hint Rewrite liftState_write_mem_ea : liftState.
+
+Lemma liftState_write_memt Regs Regval A B E wk addr sz v t r :
+ liftState (Regs := Regs) r (@write_memt Regval A B E wk addr sz v t) = write_memtS wk addr sz v t.
+unfold write_memt, write_memtS.
+destruct (Sail2_values.mem_bytes_of_bits v); auto.
+Qed.
+Hint Rewrite liftState_write_memt : liftState.
+
+Lemma liftState_write_mem Regs Regval A B E wk addrsize addr sz v r :
+ liftState (Regs := Regs) r (@write_mem Regval A B E wk addrsize addr sz v) = write_memS wk addr sz v.
+unfold write_mem, write_memS, write_memtS.
+destruct (Sail2_values.mem_bytes_of_bits v); simpl; auto.
+Qed.
+Hint Rewrite liftState_write_mem : liftState.
+
+Lemma bindS_rw_left Regs A B E m1 m2 (f : A -> monadS Regs B E) s :
+ m1 s = m2 s ->
+ bindS m1 f s = bindS m2 f s.
+intro H. unfold bindS. rewrite H. reflexivity.
+Qed.
+
+Lemma liftState_read_reg_readS Regs Regval A E reg get_regval' set_regval' :
+ (forall s, map_bind reg.(of_regval) (get_regval' reg.(name) s) = Some (reg.(read_from) s)) ->
+ liftState (Regs := Regs) (get_regval', set_regval') (@read_reg _ Regval A E reg) === readS (fun x => reg.(read_from) (ss_regstate x)).
+intros.
+unfold read_reg. simpl. unfold readS. intro s.
+erewrite bindS_rw_left. 2: {
+ apply bindS_returnS_left.
+}
+specialize (H (ss_regstate s)).
+destruct (get_regval' _ _) as [v | ]; only 2: discriminate H.
+rewrite bindS_returnS_left.
+simpl in *.
+rewrite H.
+reflexivity.
+Qed.
+
+Lemma liftState_write_reg_updateS Regs Regval A E get_regval' set_regval' reg (v : A) :
+ (forall s, set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)) ->
+ liftState (Regs := Regs) (Regval := Regval) (E := E) (get_regval', set_regval') (write_reg reg v) === updateS (fun s => {| ss_regstate := (write_to reg v s.(ss_regstate)); ss_memstate := s.(ss_memstate); ss_tagstate := s.(ss_tagstate) |}).
+intros. intro s.
+unfold write_reg. simpl. unfold readS, seqS.
+erewrite bindS_rw_left. 2: {
+ apply bindS_returnS_left.
+}
+specialize (H (ss_regstate s)).
+destruct (set_regval' _ _) as [v' | ]; only 2: discriminate H.
+injection H as H1.
+unfold updateS.
+rewrite <- H1.
+reflexivity.
+Qed.
+(*
+Lemma liftState_iter_aux Regs Regval A E :
+ liftState r (iter_aux i f xs) = iterS_aux i (fun i x => liftState r (f i x)) xs.
+ by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct)
+ (auto simp: liftState_simp cong: bindS_cong)
+Hint Rewrite liftState_iter_aux : liftState.
+
+lemma liftState_iteri[liftState_simp]:
+ "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs"
+ by (auto simp: iteri_def iteriS_def liftState_simp)
+
+lemma liftState_iter[liftState_simp]:
+ "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs"
+ by (auto simp: iter_def iterS_def liftState_simp)
+*)
+Lemma liftState_foreachM Regs Regval A Vars E (xs : list A) (vars : Vars) (body : A -> Vars -> monad Regval Vars E) r :
+ liftState (Regs := Regs) r (foreachM xs vars body) === foreachS xs vars (fun x vars => liftState r (body x vars)).
+revert vars.
+induction xs as [ | h t].
+* reflexivity.
+* intros vars. simpl.
+ rewrite_liftState.
+ apply bindS_cong; auto.
+Qed.
+Hint Rewrite liftState_foreachM : liftState.
+
+Lemma foreachS_cong {A RV Vars E} xs vars f f' :
+ (forall a vars, f a vars === f' a vars) ->
+ @foreachS A RV Vars E xs vars f === foreachS xs vars f'.
+intro H.
+revert vars.
+induction xs.
+* reflexivity.
+* intros. simpl.
+ rewrite H.
+ apply bindS_cong; auto.
+Qed.
+
+Add Parametric Morphism {Regs A Vars E : Type} : (@foreachS A Regs Vars E)
+ with signature eq ==> eq ==> equiv ==> equiv as foreachS_morphism.
+apply foreachS_cong.
+Qed.
+
+(*Tactic Notation "sail_rewrite" ident(hintdb) := rewrite_strat topdown (choice (hints hintdb) progress eval cbn beta).
+Ltac sail_rewrite hintdb := rewrite_strat topdown (choice (hints hintdb) progress eval cbn beta).*)
+
+Lemma liftState_genlistM Regs Regval A E r f n :
+ liftState (Regs := Regs) r (@genlistM A Regval E f n) === genlistS (fun x => liftState r (f x)) n.
+unfold genlistM, genlistS.
+rewrite_liftState.
+reflexivity.
+Qed.
+Hint Rewrite liftState_genlistM : liftState.
+
+Add Parametric Morphism {A RV E : Type} : (@genlistS A RV E)
+ with signature equiv ==> eq ==> equiv as genlistS_morphism.
+intros f g EQ n.
+unfold genlistS.
+apply foreachS_cong.
+intros m vars.
+rewrite EQ.
+reflexivity.
+Qed.
+
+Lemma liftState_choose_bools Regs Regval E descr n r :
+ liftState (Regs := Regs) r (@choose_bools Regval E descr n) === choose_boolsS n.
+unfold choose_bools, choose_boolsS.
+rewrite_liftState.
+reflexivity.
+Qed.
+Hint Rewrite liftState_choose_bools : liftState.
+
+(*
+Lemma liftState_bools_of_bits_nondet[liftState_simp]:
+ "liftState r (bools_of_bits_nondet bs) = bools_of_bits_nondetS bs"
+ unfolding bools_of_bits_nondet_def bools_of_bits_nondetS_def
+ by (auto simp: liftState_simp comp_def)
+Hint Rewrite liftState_choose_bools : liftState.
+*)
+
+Lemma liftState_internal_pick Regs Regval A E r (xs : list A) :
+ liftState (Regs := Regs) (Regval := Regval) (E := E) r (internal_pick xs) === internal_pickS xs.
+unfold internal_pick, internal_pickS.
+unfold choose.
+rewrite_liftState.
+apply bindS_cong; auto.
+intros.
+destruct (nth_error _ _); auto.
+Qed.
+Hint Rewrite liftState_internal_pick : liftState.
+
+Lemma liftRS_returnS (*[simp]:*) A R Regs E x :
+ @liftRS A R Regs E (returnS x) = returnS x.
+reflexivity.
+Qed.
+
+Lemma concat_singleton A (xs : list A) :
+ concat (xs::nil) = xs.
+simpl.
+rewrite app_nil_r.
+reflexivity.
+Qed.
+
+Lemma liftRS_bindS Regs A B R E (m : monadS Regs A E) (f : A -> monadS Regs B E) :
+ @liftRS B R Regs E (bindS m f) === bindS (liftRS m) (fun x => liftRS (f x)).
+intro s.
+unfold liftRS, try_catchS, bindS, throwS, returnS.
+induction (m s) as [ | [[a | [msg | e]] t]].
+* reflexivity.
+* simpl. rewrite flat_map_app. rewrite IHl. reflexivity.
+* simpl. rewrite IHl. reflexivity.
+* simpl. rewrite IHl. reflexivity.
+Qed.
+
+Lemma liftRS_assert_expS_True (*[simp]:*) Regs R E msg :
+ @liftRS _ R Regs E (assert_expS true msg) = returnS tt.
+reflexivity.
+Qed.
+
+(*
+lemma untilM_domI:
+ fixes V :: "'vars \<Rightarrow> nat"
+ assumes "Inv vars"
+ and "\<And>vars t vars' t'. \<lbrakk>Inv vars; Run (body vars) t vars'; Run (cond vars') t' False\<rbrakk> \<Longrightarrow> V vars' < V vars \<and> Inv vars'"
+ shows "untilM_dom (vars, cond, body)"
+ using assms
+ by (induction vars rule: measure_induct_rule[where f = V])
+ (auto intro: untilM.domintros)
+
+lemma untilM_dom_untilS_dom:
+ assumes "untilM_dom (vars, cond, body)"
+ shows "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ using assms
+ by (induction vars cond body arbitrary: s rule: untilM.pinduct)
+ (rule untilS.domintros, auto elim!: Value_liftState_Run)
+
+lemma measure2_induct:
+ fixes f :: "'a \<Rightarrow> 'b \<Rightarrow> nat"
+ assumes "\<And>x1 y1. (\<And>x2 y2. f x2 y2 < f x1 y1 \<Longrightarrow> P x2 y2) \<Longrightarrow> P x1 y1"
+ shows "P x y"
+proof -
+ have "P (fst x) (snd x)" for x
+ by (induction x rule: measure_induct_rule[where f = "\<lambda>x. f (fst x) (snd x)"]) (auto intro: assms)
+ then show ?thesis by auto
+qed
+
+lemma untilS_domI:
+ fixes V :: "'vars \<Rightarrow> 'regs sequential_state \<Rightarrow> nat"
+ assumes "Inv vars s"
+ and "\<And>vars s vars' s' s''.
+ \<lbrakk>Inv vars s; (Value vars', s') \<in> body vars s; (Value False, s'') \<in> cond vars' s'\<rbrakk>
+ \<Longrightarrow> V vars' s'' < V vars s \<and> Inv vars' s''"
+ shows "untilS_dom (vars, cond, body, s)"
+ using assms
+ by (induction vars s rule: measure2_induct[where f = V])
+ (auto intro: untilS.domintros)
+
+lemma whileS_dom_step:
+ assumes "whileS_dom (vars, cond, body, s)"
+ and "(Value True, s') \<in> cond vars s"
+ and "(Value vars', s'') \<in> body vars s'"
+ shows "whileS_dom (vars', cond, body, s'')"
+ by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>)
+ (auto intro: whileS.domintros)
+
+lemma whileM_dom_step:
+ assumes "whileM_dom (vars, cond, body)"
+ and "Run (cond vars) t True"
+ and "Run (body vars) t' vars'"
+ shows "whileM_dom (vars', cond, body)"
+ by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>)
+ (auto intro: whileM.domintros)
+
+lemma whileM_dom_ex_step:
+ assumes "whileM_dom (vars, cond, body)"
+ and "\<exists>t. Run (cond vars) t True"
+ and "\<exists>t'. Run (body vars) t' vars'"
+ shows "whileM_dom (vars', cond, body)"
+ using assms by (blast intro: whileM_dom_step)
+
+lemmas whileS_pinduct = whileS.pinduct[case_names Step]
+
+lemma liftState_whileM:
+ assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ and "whileM_dom (vars, cond, body)"
+ shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>)
+ case Step: (1 vars s)
+ note domS = Step(1) and IH = Step(2) and domM = Step(3)
+ show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind
+ proof (intro bindS_ext_cong, goal_cases cond while)
+ case (while a s')
+ have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' =
+ bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'"
+ if "a"
+ proof (intro bindS_ext_cong, goal_cases body while')
+ case (while' vars' s'')
+ have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM])
+ show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run)
+ show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run)
+ qed
+ then show ?case using while while' that IH by auto
+ qed auto
+ then show ?case by (auto simp: liftState_simp)
+ qed auto
+qed
+*)
+
+Local Opaque _limit_reduces.
+Ltac gen_reduces :=
+ match goal with |- context[@_limit_reduces ?a ?b ?c] => generalize (@_limit_reduces a b c) end.
+
+(* TODO: rewrite_liftState is performing really badly here. We could add liftState_if_distrib
+ to the hint db, but then it starts failing in a way that causes the whole rewriting to fail. *)
+
+Lemma liftState_whileM RV Vars E r measure vars cond (body : Vars -> monad RV Vars E) :
+ liftState (Regs := RV) r (whileMT vars measure cond body) === whileST vars measure (fun vars => liftState r (cond vars)) (fun vars => liftState r (body vars)).
+unfold whileMT, whileST.
+generalize (measure vars) as limit. intro.
+revert vars.
+destruct (Z.le_decidable 0 limit).
+* generalize (Zwf_guarded limit) as acc.
+ apply Wf_Z.natlike_ind with (x := limit).
+ + intros [acc] *; simpl.
+ match goal with |- context [Build_ArithFact _ ?prf] => generalize prf; intros ?Proof end.
+ rewrite_liftState.
+ setoid_rewrite liftState_if_distrib.
+ apply bindS_cong; auto.
+ destruct a; rewrite_liftState; auto.
+ apply bindS_cong; auto.
+ intros. destruct (_limit_reduces _). simpl.
+ reflexivity.
+ + clear limit H.
+ intros limit H IH [acc] vars s. simpl.
+ destruct (Z_ge_dec _ _); try omega.
+ autorewrite with liftState.
+ apply bindS_ext_cong; auto.
+ intros. rewrite liftState_if_distrib.
+ destruct a; autorewrite with liftState; auto.
+ apply bindS_ext_cong; auto.
+ intros.
+ gen_reduces.
+ replace (Z.succ limit - 1) with limit; try omega. intro acc'.
+ apply IH.
+ + assumption.
+* intros. simpl.
+ destruct (Z_ge_dec _ _); try omega.
+ reflexivity.
+Qed.
+
+(*
+lemma untilM_dom_step:
+ assumes "untilM_dom (vars, cond, body)"
+ and "Run (body vars) t vars'"
+ and "Run (cond vars') t' False"
+ shows "untilM_dom (vars', cond, body)"
+ by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>)
+ (auto intro: untilM.domintros)
+
+lemma untilM_dom_ex_step:
+ assumes "untilM_dom (vars, cond, body)"
+ and "\<exists>t. Run (body vars) t vars'"
+ and "\<exists>t'. Run (cond vars') t' False"
+ shows "untilM_dom (vars', cond, body)"
+ using assms by (blast intro: untilM_dom_step)
+
+lemma liftState_untilM:
+ assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ and "untilM_dom (vars, cond, body)"
+ shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>)
+ case Step: (1 vars s)
+ note domS = Step(1) and IH = Step(2) and domM = Step(3)
+ show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind
+ proof (intro bindS_ext_cong, goal_cases body k)
+ case (k vars' s')
+ show ?case unfolding comp_def liftState_bind
+ proof (intro bindS_ext_cong, goal_cases cond until)
+ case (until a s'')
+ have "untilM_dom (vars', cond, body)" if "\<not>a"
+ proof (rule untilM_dom_ex_step[OF domM])
+ show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run)
+ show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run)
+ qed
+ then show ?case using k until IH by (auto simp: comp_def liftState_simp)
+ qed auto
+ qed auto
+qed*)
+
+Lemma liftState_untilM RV Vars E r measure vars cond (body : Vars -> monad RV Vars E) :
+ liftState (Regs := RV) r (untilMT vars measure cond body) === untilST vars measure (fun vars => liftState r (cond vars)) (fun vars => liftState r (body vars)).
+unfold untilMT, untilST.
+generalize (measure vars) as limit. intro.
+revert vars.
+destruct (Z.le_decidable 0 limit).
+* generalize (Zwf_guarded limit) as acc.
+ apply Wf_Z.natlike_ind with (x := limit).
+ + intros [acc] * s; simpl.
+(* TODO rewrite_liftState.*)
+autorewrite with liftState.
+ apply bindS_ext_cong; auto.
+ intros. autorewrite with liftState.
+ apply bindS_ext_cong; auto.
+ intros. rewrite liftState_if_distrib.
+ destruct a0; auto.
+ destruct (_limit_reduces _). simpl.
+ reflexivity.
+ + clear limit H.
+ intros limit H IH [acc] vars s. simpl.
+ destruct (Z_ge_dec _ _); try omega.
+ autorewrite with liftState.
+ apply bindS_ext_cong; auto.
+ intros. autorewrite with liftState; auto.
+ apply bindS_ext_cong; auto.
+ intros. rewrite liftState_if_distrib.
+ destruct a0; autorewrite with liftState; auto.
+ gen_reduces.
+ replace (Z.succ limit - 1) with limit; try omega. intro acc'.
+ apply IH.
+ + assumption.
+* intros. simpl.
+ destruct (Z_ge_dec _ _); try omega.
+ reflexivity.
+Qed.
+
+(*
+
+text \<open>Simplification rules for monadic Boolean connectives\<close>
+
+lemma if_return_return[simp]: "(if a then return True else return False) = return a" by auto
+
+lemma and_boolM_simps[simp]:
+ "and_boolM (return b) (return c) = return (b \<and> c)"
+ "and_boolM x (return True) = x"
+ "and_boolM x (return False) = x \<bind> (\<lambda>_. return False)"
+ "\<And>x y z. and_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. and_boolM (y r) z))"
+ by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_if:
+ "and_boolM (return b) y = (if b then y else return False)"
+ by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_return_and[simp]: "and_boolM (return l) (return r) = return (l \<and> r)"
+ by (auto simp: and_boolM_def)
+
+lemmas and_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolM x y" for y]
+
+lemma or_boolM_simps[simp]:
+ "or_boolM (return b) (return c) = return (b \<or> c)"
+ "or_boolM x (return True) = x \<bind> (\<lambda>_. return True)"
+ "or_boolM x (return False) = x"
+ "\<And>x y z. or_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. or_boolM (y r) z))"
+ by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_if:
+ "or_boolM (return b) y = (if b then return True else y)"
+ by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_return_or[simp]: "or_boolM (return l) (return r) = return (l \<or> r)"
+ by (auto simp: or_boolM_def)
+
+lemmas or_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolM x y" for y]
+
+lemma if_returnS_returnS[simp]: "(if a then returnS True else returnS False) = returnS a" by auto
+
+lemma and_boolS_simps[simp]:
+ "and_boolS (returnS b) (returnS c) = returnS (b \<and> c)"
+ "and_boolS x (returnS True) = x"
+ "and_boolS x (returnS False) = bindS x (\<lambda>_. returnS False)"
+ "\<And>x y z. and_boolS (bindS x y) z = (bindS x (\<lambda>r. and_boolS (y r) z))"
+ by (auto simp: and_boolS_def)
+
+lemma and_boolS_returnS_if:
+ "and_boolS (returnS b) y = (if b then y else returnS False)"
+ by (auto simp: and_boolS_def)
+
+lemmas and_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolS x y" for y]
+
+lemma and_boolS_returnS_True[simp]: "and_boolS (returnS True) c = c"
+ by (auto simp: and_boolS_def)
+
+lemma or_boolS_simps[simp]:
+ "or_boolS (returnS b) (returnS c) = returnS (b \<or> c)"
+ "or_boolS (returnS False) m = m"
+ "or_boolS x (returnS True) = bindS x (\<lambda>_. returnS True)"
+ "or_boolS x (returnS False) = x"
+ "\<And>x y z. or_boolS (bindS x y) z = (bindS x (\<lambda>r. or_boolS (y r) z))"
+ by (auto simp: or_boolS_def)
+
+lemma or_boolS_returnS_if:
+ "or_boolS (returnS b) y = (if b then returnS True else y)"
+ by (auto simp: or_boolS_def)
+
+lemmas or_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolS x y" for y]
+
+lemma Run_or_boolM_E:
+ assumes "Run (or_boolM l r) t a"
+ obtains "Run l t True" and "a"
+ | tl tr where "Run l tl False" and "Run r tr a" and "t = tl @ tr"
+ using assms by (auto simp: or_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma Run_and_boolM_E:
+ assumes "Run (and_boolM l r) t a"
+ obtains "Run l t False" and "\<not>a"
+ | tl tr where "Run l tl True" and "Run r tr a" and "t = tl @ tr"
+ using assms by (auto simp: and_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma maybe_failS_Some[simp]: "maybe_failS msg (Some v) = returnS v"
+ by (auto simp: maybe_failS_def)
+
+text \<open>Event traces\<close>
+
+lemma Some_eq_bind_conv: "Some x = Option.bind f g \<longleftrightarrow> (\<exists>y. f = Some y \<and> g y = Some x)"
+ unfolding bind_eq_Some_conv[symmetric] by auto
+
+lemma if_then_Some_eq_Some_iff: "((if b then Some x else None) = Some y) \<longleftrightarrow> (b \<and> y = x)"
+ by auto
+
+lemma Some_eq_if_then_Some_iff: "(Some y = (if b then Some x else None)) \<longleftrightarrow> (b \<and> y = x)"
+ by auto
+
+lemma emitEventS_update_cases:
+ assumes "emitEventS ra e s = Some s'"
+ obtains
+ (Write_mem) wk addr sz v tag r
+ where "e = E_write_memt wk addr sz v tag r \<or> (e = E_write_mem wk addr sz v r \<and> tag = B0)"
+ and "s' = put_mem_bytes addr sz v tag s"
+ | (Write_reg) r v rs'
+ where "e = E_write_reg r v" and "(snd ra) r v (regstate s) = Some rs'"
+ and "s' = s\<lparr>regstate := rs'\<rparr>"
+ | (Read) "s' = s"
+ using assms
+ by (elim emitEventS.elims)
+ (auto simp: Some_eq_bind_conv bind_eq_Some_conv if_then_Some_eq_Some_iff Some_eq_if_then_Some_iff)
+
+lemma runTraceS_singleton[simp]: "runTraceS ra [e] s = emitEventS ra e s"
+ by (cases "emitEventS ra e s"; auto)
+
+lemma runTraceS_ConsE:
+ assumes "runTraceS ra (e # t) s = Some s'"
+ obtains s'' where "emitEventS ra e s = Some s''" and "runTraceS ra t s'' = Some s'"
+ using assms by (auto simp: bind_eq_Some_conv)
+
+lemma runTraceS_ConsI:
+ assumes "emitEventS ra e s = Some s'" and "runTraceS ra t s' = Some s''"
+ shows "runTraceS ra (e # t) s = Some s''"
+ using assms by auto
+
+lemma runTraceS_Cons_tl:
+ assumes "emitEventS ra e s = Some s'"
+ shows "runTraceS ra (e # t) s = runTraceS ra t s'"
+ using assms by (elim emitEventS.elims) (auto simp: Some_eq_bind_conv bind_eq_Some_conv)
+
+lemma runTraceS_appendE:
+ assumes "runTraceS ra (t @ t') s = Some s'"
+ obtains s'' where "runTraceS ra t s = Some s''" and "runTraceS ra t' s'' = Some s'"
+proof -
+ have "\<exists>s''. runTraceS ra t s = Some s'' \<and> runTraceS ra t' s'' = Some s'"
+ proof (use assms in \<open>induction t arbitrary: s\<close>)
+ case (Cons e t)
+ from Cons.prems
+ obtain s_e where "emitEventS ra e s = Some s_e" and "runTraceS ra (t @ t') s_e = Some s'"
+ by (auto elim: runTraceS_ConsE simp: bind_eq_Some_conv)
+ with Cons.IH[of s_e] show ?case by (auto intro: runTraceS_ConsI)
+ qed auto
+ then show ?thesis using that by blast
+qed
+
+lemma runTraceS_nth_split:
+ assumes "runTraceS ra t s = Some s'" and n: "n < length t"
+ obtains s1 s2 where "runTraceS ra (take n t) s = Some s1"
+ and "emitEventS ra (t ! n) s1 = Some s2"
+ and "runTraceS ra (drop (Suc n) t) s2 = Some s'"
+proof -
+ have "runTraceS ra (take n t @ t ! n # drop (Suc n) t) s = Some s'"
+ using assms
+ by (auto simp: id_take_nth_drop[OF n, symmetric])
+ then show thesis by (blast elim: runTraceS_appendE runTraceS_ConsE intro: that)
+qed
+
+text \<open>Memory accesses\<close>
+
+lemma get_mem_bytes_put_mem_bytes_same_addr:
+ assumes "length v = sz"
+ shows "get_mem_bytes addr sz (put_mem_bytes addr sz v tag s) = Some (v, if sz > 0 then tag else B1)"
+proof (unfold assms[symmetric], induction v rule: rev_induct)
+ case Nil
+ then show ?case by (auto simp: get_mem_bytes_def)
+next
+ case (snoc x xs)
+ then show ?case
+ by (cases tag)
+ (auto simp: get_mem_bytes_def put_mem_bytes_def Let_def and_bit_eq_iff foldl_and_bit_eq_iff
+ cong: option.case_cong split: if_splits option.splits)
+qed
+
+lemma memstate_put_mem_bytes:
+ assumes "length v = sz"
+ shows "memstate (put_mem_bytes addr sz v tag s) addr' =
+ (if addr' \<in> {addr..<addr+sz} then Some (v ! (addr' - addr)) else memstate s addr')"
+ unfolding assms[symmetric]
+ by (induction v rule: rev_induct) (auto simp: put_mem_bytes_def nth_Cons nth_append Let_def)
+
+lemma tagstate_put_mem_bytes:
+ assumes "length v = sz"
+ shows "tagstate (put_mem_bytes addr sz v tag s) addr' =
+ (if addr' \<in> {addr..<addr+sz} then Some tag else tagstate s addr')"
+ unfolding assms[symmetric]
+ by (induction v rule: rev_induct) (auto simp: put_mem_bytes_def nth_Cons nth_append Let_def)
+
+lemma get_mem_bytes_cong:
+ assumes "\<forall>addr'. addr \<le> addr' \<and> addr' < addr + sz \<longrightarrow>
+ (memstate s' addr' = memstate s addr' \<and> tagstate s' addr' = tagstate s addr')"
+ shows "get_mem_bytes addr sz s' = get_mem_bytes addr sz s"
+proof (use assms in \<open>induction sz\<close>)
+ case 0
+ then show ?case by (auto simp: get_mem_bytes_def)
+next
+ case (Suc sz)
+ then show ?case
+ by (auto simp: get_mem_bytes_def Let_def
+ intro!: map_option_cong map_cong foldl_cong
+ arg_cong[where f = just_list] arg_cong2[where f = and_bit])
+qed
+
+lemma get_mem_bytes_tagged_tagstate:
+ assumes "get_mem_bytes addr sz s = Some (v, B1)"
+ shows "\<forall>addr' \<in> {addr..<addr + sz}. tagstate s addr' = Some B1"
+ using assms
+ by (auto simp: get_mem_bytes_def foldl_and_bit_eq_iff Let_def split: option.splits)
+
+end
+*) \ No newline at end of file
diff --git a/prover_snapshots/coq/lib/sail/Sail2_state_lifting.v b/prover_snapshots/coq/lib/sail/Sail2_state_lifting.v
new file mode 100644
index 0000000..1544c3c
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_state_lifting.v
@@ -0,0 +1,61 @@
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state_monad.
+Import ListNotations.
+
+(* Lifting from prompt monad to state monad *)
+(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*)
+Fixpoint liftState {Regval Regs A E} (ra : register_accessors Regs Regval) (m : monad Regval A E) : monadS Regs A E :=
+ match m with
+ | (Done a) => returnS a
+ | (Read_mem rk a sz k) => bindS (read_mem_bytesS rk a sz) (fun v => liftState ra (k v))
+ | (Read_memt rk a sz k) => bindS (read_memt_bytesS rk a sz) (fun v => liftState ra (k v))
+ | (Write_mem wk a sz v k) => bindS (write_mem_bytesS wk a sz v) (fun v => liftState ra (k v))
+ | (Write_memt wk a sz v t k) => bindS (write_memt_bytesS wk a sz v t) (fun v => liftState ra (k v))
+ | (Read_reg r k) => bindS (read_regvalS ra r) (fun v => liftState ra (k v))
+ | (Excl_res k) => bindS (excl_resultS tt) (fun v => liftState ra (k v))
+ | (Choose _ k) => bindS (choose_boolS tt) (fun v => liftState ra (k v))
+ | (Write_reg r v k) => seqS (write_regvalS ra r v) (liftState ra k)
+ | (Write_ea _ _ _ k) => liftState ra k
+ | (Footprint k) => liftState ra k
+ | (Barrier _ k) => liftState ra k
+ | (Print _ k) => liftState ra k (* TODO *)
+ | (Fail descr) => failS descr
+ | (Exception e) => throwS e
+end.
+
+Local Open Scope bool_scope.
+
+(*val emitEventS : forall 'regval 'regs 'a 'e. Eq 'regval => register_accessors 'regs 'regval -> event 'regval -> sequential_state 'regs -> maybe (sequential_state 'regs)*)
+Definition emitEventS {Regval Regs} `{forall (x y : Regval), Decidable (x = y)} (ra : register_accessors Regs Regval) (e : event Regval) (s : sequential_state Regs) : option (sequential_state Regs) :=
+match e with
+ | E_read_mem _ addr sz v =>
+ option_bind (get_mem_bytes addr sz s) (fun '(v', _) =>
+ if generic_eq v' v then Some s else None)
+ | E_read_memt _ addr sz (v, tag) =>
+ option_bind (get_mem_bytes addr sz s) (fun '(v', tag') =>
+ if generic_eq v' v && generic_eq tag' tag then Some s else None)
+ | E_write_mem _ addr sz v success =>
+ if success then Some (put_mem_bytes addr sz v B0 s) else None
+ | E_write_memt _ addr sz v tag success =>
+ if success then Some (put_mem_bytes addr sz v tag s) else None
+ | E_read_reg r v =>
+ let (read_reg, _) := ra in
+ option_bind (read_reg r s.(ss_regstate)) (fun v' =>
+ if generic_eq v' v then Some s else None)
+ | E_write_reg r v =>
+ let (_, write_reg) := ra in
+ option_bind (write_reg r v s.(ss_regstate)) (fun rs' =>
+ Some {| ss_regstate := rs'; ss_memstate := s.(ss_memstate); ss_tagstate := s.(ss_tagstate) |})
+ | _ => Some s
+end.
+
+Local Close Scope bool_scope.
+
+(*val runTraceS : forall 'regval 'regs 'a 'e. Eq 'regval => register_accessors 'regs 'regval -> trace 'regval -> sequential_state 'regs -> maybe (sequential_state 'regs)*)
+Fixpoint runTraceS {Regval Regs} `{forall (x y : Regval), Decidable (x = y)} (ra : register_accessors Regs Regval) (t : trace Regval) (s : sequential_state Regs) : option (sequential_state Regs) :=
+match t with
+ | [] => Some s
+ | e :: t' => option_bind (emitEventS ra e s) (runTraceS ra t')
+end.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_state_monad.v b/prover_snapshots/coq/lib/sail/Sail2_state_monad.v
new file mode 100644
index 0000000..552fa68
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_state_monad.v
@@ -0,0 +1,323 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require FMapList.
+Require Import OrderedType.
+Require OrderedTypeEx.
+Require Import List.
+Require bbv.Word.
+Import ListNotations.
+
+(* TODO: revisit choice of FMapList *)
+Module NatMap := FMapList.Make(OrderedTypeEx.Nat_as_OT).
+
+Definition Memstate : Type := NatMap.t memory_byte.
+Definition Tagstate : Type := NatMap.t bitU.
+(* type regstate = map string (vector bitU) *)
+
+(* We deviate from the Lem library and prefix the fields with ss_ to avoid
+ name clashes. *)
+Record sequential_state {Regs} :=
+ { ss_regstate : Regs;
+ ss_memstate : Memstate;
+ ss_tagstate : Tagstate }.
+Arguments sequential_state : clear implicits.
+
+(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*)
+Definition init_state {Regs} regs : sequential_state Regs :=
+ {| ss_regstate := regs;
+ ss_memstate := NatMap.empty _;
+ ss_tagstate := NatMap.empty _ |}.
+
+Inductive ex E :=
+ | Failure : string -> ex E
+ | Throw : E -> ex E.
+Arguments Failure {E} _.
+Arguments Throw {E} _.
+
+Inductive result A E :=
+ | Value : A -> result A E
+ | Ex : ex E -> result A E.
+Arguments Value {A} {E} _.
+Arguments Ex {A} {E} _.
+
+(* State, nondeterminism and exception monad with result value type 'a
+ and exception type 'e. *)
+(* TODO: the list was originally a set, can we reasonably go back to a set? *)
+Definition monadS Regs a e : Type :=
+ sequential_state Regs -> list (result a e * sequential_state Regs).
+
+(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
+Definition returnS {Regs A E} (a:A) : monadS Regs A E := fun s => [(Value a,s)].
+
+(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
+Definition bindS {Regs A B E} (m : monadS Regs A E) (f : A -> monadS Regs B E) : monadS Regs B E :=
+ fun (s : sequential_state Regs) =>
+ List.flat_map (fun v => match v with
+ | (Value a, s') => f a s'
+ | (Ex e, s') => [(Ex e, s')]
+ end) (m s).
+
+(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
+Definition seqS {Regs B E} (m : monadS Regs unit E) (n : monadS Regs B E) : monadS Regs B E :=
+ bindS m (fun (_ : unit) => n).
+(*
+let inline (>>$=) = bindS
+let inline (>>$) = seqS
+*)
+Notation "m >>$= f" := (bindS m f) (at level 50, left associativity).
+Notation "m >>$ n" := (seqS m n) (at level 50, left associativity).
+
+(*val chooseS : forall 'regs 'a 'e. SetType 'a => list 'a -> monadS 'regs 'a 'e*)
+Definition chooseS {Regs A E} (xs : list A) : monadS Regs A E :=
+ fun s => (List.map (fun x => (Value x, s)) xs).
+
+(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
+Definition readS {Regs A E} (f : sequential_state Regs -> A) : monadS Regs A E :=
+ (fun s => returnS (f s) s).
+
+(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
+Definition updateS {Regs E} (f : sequential_state Regs -> sequential_state Regs) : monadS Regs unit E :=
+ (fun s => returnS tt (f s)).
+
+(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
+Definition failS {Regs A E} msg : monadS Regs A E :=
+ fun s => [(Ex (Failure msg), s)].
+
+(*val choose_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
+Definition choose_boolS {Regs E} (_:unit) : monadS Regs bool E :=
+ chooseS [false; true].
+Definition undefined_boolS {Regs E} := @choose_boolS Regs E.
+
+(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
+Definition exitS {Regs A E} (_:unit) : monadS Regs A E := failS "exit".
+
+(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
+Definition throwS {Regs A E} (e : E) :monadS Regs A E :=
+ fun s => [(Ex (Throw e), s)].
+
+(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*)
+Definition try_catchS {Regs A E1 E2} (m : monadS Regs A E1) (h : E1 -> monadS Regs A E2) : monadS Regs A E2 :=
+fun s =>
+ List.flat_map (fun v => match v with
+ | (Value a, s') => returnS a s'
+ | (Ex (Throw e), s') => h e s'
+ | (Ex (Failure msg), s') => [(Ex (Failure msg), s')]
+ end) (m s).
+
+(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
+Definition assert_expS {Regs E} (exp : bool) (msg : string) : monadS Regs unit E :=
+ if exp then returnS tt else failS msg.
+
+(* For early return, we abuse exceptions by throwing and catching
+ the return value. The exception type is "either 'r 'e", where "Right e"
+ represents a proper exception and "Left r" an early return of value "r". *)
+Definition monadRS Regs A R E := monadS Regs A (sum R E).
+
+(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*)
+Definition early_returnS {Regs A R E} (r : R) : monadRS Regs A R E := throwS (inl r).
+
+(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
+Definition catch_early_returnS {Regs A E} (m : monadRS Regs A A E) : monadS Regs A E :=
+ try_catchS m
+ (fun v => match v with
+ | inl a => returnS a
+ | inr e => throwS e
+ end).
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*)
+Definition liftRS {A R Regs E} (m : monadS Regs A E) : monadRS Regs A R E :=
+ try_catchS m (fun e => throwS (inr e)).
+
+(* Catch exceptions in the presence of early returns *)
+(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2*)
+Definition try_catchRS {Regs A R E1 E2} (m : monadRS Regs A R E1) (h : E1 -> monadRS Regs A R E2) : monadRS Regs A R E2 :=
+ try_catchS m
+ (fun v => match v with
+ | inl r => throwS (inl r)
+ | inr e => h e
+ end).
+
+(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
+Definition maybe_failS {Regs A E} msg (v : option A) : monadS Regs A E :=
+match v with
+ | Some a => returnS a
+ | None => failS msg
+end.
+
+(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
+Definition read_tagS {Regs A E} (addr : mword A) : monadS Regs bitU E :=
+ let addr := Word.wordToNat (get_word addr) in
+ readS (fun s => opt_def B0 (NatMap.find addr s.(ss_tagstate))).
+
+Fixpoint genlist_acc {A:Type} (f : nat -> A) n acc : list A :=
+ match n with
+ | O => acc
+ | S n' => genlist_acc f n' (f n' :: acc)
+ end.
+Definition genlist {A} f n := @genlist_acc A f n [].
+
+
+(* Read bytes from memory and return in little endian order *)
+(*val get_mem_bytes : forall 'regs. nat -> nat -> sequential_state 'regs -> maybe (list memory_byte * bitU)*)
+Definition get_mem_bytes {Regs} addr sz (s : sequential_state Regs) : option (list memory_byte * bitU) :=
+ let addrs := genlist (fun n => addr + n)%nat sz in
+ let read_byte s addr := NatMap.find addr s.(ss_memstate) in
+ let read_tag s addr := opt_def B0 (NatMap.find addr s.(ss_tagstate)) in
+ option_map
+ (fun mem_val => (mem_val, List.fold_left and_bit (List.map (read_tag s) addrs) B1))
+ (just_list (List.map (read_byte s) addrs)).
+
+(*val read_memt_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte * bitU) 'e*)
+Definition read_memt_bytesS {Regs E} (_ : read_kind) addr sz : monadS Regs (list memory_byte * bitU) E :=
+ readS (get_mem_bytes addr sz) >>$=
+ maybe_failS "read_memS".
+
+(*val read_mem_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte) 'e*)
+Definition read_mem_bytesS {Regs E} (rk : read_kind) addr sz : monadS Regs (list memory_byte) E :=
+ read_memt_bytesS rk addr sz >>$= (fun '(bytes, _) =>
+ returnS bytes).
+
+(*val read_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs ('b * bitU) 'e*)
+Definition read_memtS {Regs E A B} (rk : read_kind) (a : mword A) sz `{ArithFact (B >= 0)} : monadS Regs (mword B * bitU) E :=
+ let a := Word.wordToNat (get_word a) in
+ read_memt_bytesS rk a (Z.to_nat sz) >>$= (fun '(bytes, tag) =>
+ maybe_failS "bits_of_mem_bytes" (of_bits (bits_of_mem_bytes bytes)) >>$= (fun mem_val =>
+ returnS (mem_val, tag))).
+
+(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*)
+Definition read_memS {Regs E A B} rk (a : mword A) sz `{ArithFact (B >= 0)} : monadS Regs (mword B) E :=
+ read_memtS rk a sz >>$= (fun '(bytes, _) =>
+ returnS bytes).
+
+(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
+Definition excl_resultS {Regs E} : unit -> monadS Regs bool E :=
+ (* TODO: This used to be more deterministic, checking a flag in the state
+ whether an exclusive load has occurred before. However, this does not
+ seem very precise; it might be safer to overapproximate the possible
+ behaviours by always making a nondeterministic choice. *)
+ @undefined_boolS Regs E.
+
+(* Write little-endian list of bytes to given address *)
+(*val put_mem_bytes : forall 'regs. nat -> nat -> list memory_byte -> bitU -> sequential_state 'regs -> sequential_state 'regs*)
+Definition put_mem_bytes {Regs} addr sz (v : list memory_byte) (tag : bitU) (s : sequential_state Regs) : sequential_state Regs :=
+ let addrs := genlist (fun n => addr + n)%nat sz in
+ let a_v := List.combine addrs v in
+ let write_byte mem '(addr, v) := NatMap.add addr v mem in
+ let write_tag mem addr := NatMap.add addr tag mem in
+ {| ss_regstate := s.(ss_regstate);
+ ss_memstate := List.fold_left write_byte a_v s.(ss_memstate);
+ ss_tagstate := List.fold_left write_tag addrs s.(ss_tagstate) |}.
+
+(*val write_memt_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> bitU -> monadS 'regs bool 'e*)
+Definition write_memt_bytesS {Regs E} (_ : write_kind) addr sz (v : list memory_byte) (t : bitU) : monadS Regs bool E :=
+ updateS (put_mem_bytes addr sz v t) >>$
+ returnS true.
+
+(*val write_mem_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> monadS 'regs bool 'e*)
+Definition write_mem_bytesS {Regs E} wk addr sz (v : list memory_byte) : monadS Regs bool E :=
+ write_memt_bytesS wk addr sz v B0.
+
+(*val write_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> bitU -> monadS 'regs bool 'e*)
+Definition write_memtS {Regs E A B} wk (addr : mword A) sz (v : mword B) (t : bitU) : monadS Regs bool E :=
+ match (Word.wordToNat (get_word addr), mem_bytes_of_bits v) with
+ | (addr, Some v) => write_memt_bytesS wk addr (Z.to_nat sz) v t
+ | _ => failS "write_mem"
+ end.
+
+(*val write_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> monadS 'regs bool 'e*)
+Definition write_memS {Regs E A B} wk (addr : mword A) sz (v : mword B) : monadS Regs bool E :=
+ write_memtS wk addr sz v B0.
+
+(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
+Definition read_regS {Regs RV A E} (reg : register_ref Regs RV A) : monadS Regs A E :=
+ readS (fun s => reg.(read_from) s.(ss_regstate)).
+
+(* TODO
+let read_reg_range reg i j state =
+ let v = slice (get_reg state (name_of_reg reg)) i j in
+ [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+ let v = access (get_reg state (name_of_reg reg)) i in
+ [(Value v,state)]
+let read_reg_field reg regfield =
+ let (i,j) = register_field_indices reg regfield in
+ read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+ let (i,_) = register_field_indices reg regfield in
+ read_reg_bit reg i *)
+
+(*val read_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
+Definition read_regvalS {Regs RV E} (acc : register_accessors Regs RV) reg : monadS Regs RV E :=
+ let '(read, _) := acc in
+ readS (fun s => read reg s.(ss_regstate)) >>$= (fun v => match v with
+ | Some v => returnS v
+ | None => failS ("read_regvalS " ++ reg)
+ end).
+
+(*val write_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
+Definition write_regvalS {Regs RV E} (acc : register_accessors Regs RV) reg (v : RV) : monadS Regs unit E :=
+ let '(_, write) := acc in
+ readS (fun s => write reg v s.(ss_regstate)) >>$= (fun x => match x with
+ | Some rs' => updateS (fun s => {| ss_regstate := rs'; ss_memstate := s.(ss_memstate); ss_tagstate := s.(ss_tagstate) |})
+ | None => failS ("write_regvalS " ++ reg)
+ end).
+
+(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
+Definition write_regS {Regs RV A E} (reg : register_ref Regs RV A) (v:A) : monadS Regs unit E :=
+ updateS (fun s => {| ss_regstate := reg.(write_to) v s.(ss_regstate); ss_memstate := s.(ss_memstate); ss_tagstate := s.(ss_tagstate) |}).
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+ let current_value = get_reg state reg in
+ let new_value = f current_value v in
+ [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+
+(* TODO Add Show typeclass for value and exception type *)
+(*val show_result : forall 'a 'e. result 'a 'e -> string*)
+Definition show_result {A E} (x : result A E) : string := match x with
+ | Value _ => "Value ()"
+ | Ex (Failure msg) => "Failure " ++ msg
+ | Ex (Throw _) => "Throw"
+end.
+
+(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
+Definition prerr_results {A E S} (rs : list (result A E * S)) : unit := tt.
+(* let _ = Set.map (fun (r, _) -> let _ = prerr_endline (show_result r) in ()) rs in
+ ()*)
+
diff --git a/prover_snapshots/coq/lib/sail/Sail2_state_monad_lemmas.v b/prover_snapshots/coq/lib/sail/Sail2_state_monad_lemmas.v
new file mode 100644
index 0000000..99fef32
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_state_monad_lemmas.v
@@ -0,0 +1,542 @@
+Require Import Sail2_state_monad.
+(*Require Import Sail2_values_lemmas.*)
+Require Export Setoid.
+Require Export Morphisms Equivalence.
+
+(* Ensure that pointwise equality on states is the preferred notion of
+ equivalence for the state monad. *)
+Local Open Scope equiv_scope.
+Instance monadS_equivalence {Regs A E} :
+ Equivalence (pointwise_relation (sequential_state Regs) (@eq (list (result A E * sequential_state Regs)))) | 9.
+split; apply _.
+Qed.
+
+Global Instance refl_eq_subrelation {A : Type} {R : A -> A -> Prop} `{Reflexive A R} : subrelation eq R.
+intros x y EQ. subst. reflexivity.
+Qed.
+
+Hint Extern 4 (_ === _) => reflexivity.
+Hint Extern 4 (_ === _) => symmetry.
+
+Lemma bindS_ext_cong (*[fundef_cong]:*) {Regs A B E}
+ {m1 m2 : monadS Regs A E} {f1 f2 : A -> monadS Regs B E} s :
+ m1 s = m2 s ->
+ (forall a s', List.In (Value a, s') (m2 s) -> f1 a s' = f2 a s') ->
+ bindS m1 f1 s = bindS m2 f2 s.
+intros.
+unfold bindS.
+rewrite H.
+rewrite !List.flat_map_concat_map.
+f_equal.
+apply List.map_ext_in.
+intros [[a|a] s'] H_in; auto.
+Qed.
+
+(* Weaker than the Isabelle version, but avoids talking about individual states *)
+Lemma bindS_cong (*[fundef_cong]:*) Regs A B E m1 m2 (f1 f2 : A -> monadS Regs B E) :
+ m1 === m2 ->
+ (forall a, f1 a === f2 a) ->
+ bindS m1 f1 === bindS m2 f2.
+intros M F s.
+apply bindS_ext_cong; intros; auto.
+apply F.
+Qed.
+
+Add Parametric Morphism {Regs A B E : Type} : (@bindS Regs A B E)
+ with signature equiv ==> equiv ==> equiv as bindS_morphism.
+auto using bindS_cong.
+Qed.
+
+Lemma bindS_returnS_left Regs A B E {x : A} {f : A -> monadS Regs B E} :
+ bindS (returnS x) f === f x.
+intro s.
+unfold returnS, bindS.
+simpl.
+auto using List.app_nil_r.
+Qed.
+Hint Rewrite bindS_returnS_left : state.
+
+Lemma bindS_returnS_right Regs A E {m : monadS Regs A E} :
+ bindS m returnS === m.
+intro s.
+unfold returnS, bindS.
+induction (m s) as [|[[a|a] s'] t]; auto;
+simpl;
+rewrite IHt;
+reflexivity.
+Qed.
+Hint Rewrite bindS_returnS_right : state.
+
+Lemma bindS_readS {Regs A E} {f} {m : A -> monadS Regs A E} {s} :
+ bindS (readS f) m s = m (f s) s.
+unfold readS, bindS.
+simpl.
+rewrite List.app_nil_r.
+reflexivity.
+Qed.
+
+Lemma bindS_updateS {Regs A E} {f : sequential_state Regs -> sequential_state Regs} {m : unit -> monadS Regs A E} {s} :
+ bindS (updateS f) m s = m tt (f s).
+unfold updateS, bindS.
+simpl.
+auto using List.app_nil_r.
+Qed.
+
+Lemma bindS_assertS_true Regs A E msg {f : unit -> monadS Regs A E} :
+ bindS (assert_expS true msg) f === f tt.
+intro s.
+unfold assert_expS, bindS.
+simpl.
+auto using List.app_nil_r.
+Qed.
+Hint Rewrite bindS_assertS_true : state.
+
+Lemma bindS_chooseS_returnS (*[simp]:*) Regs A B E {xs : list A} {f : A -> B} :
+ bindS (Regs := Regs) (E := E) (chooseS xs) (fun x => returnS (f x)) === chooseS (List.map f xs).
+intro s.
+unfold chooseS, bindS, returnS.
+induction xs; auto.
+simpl. rewrite IHxs.
+reflexivity.
+Qed.
+Hint Rewrite bindS_chooseS_returnS : state.
+
+Lemma result_cases : forall (A E : Type) (P : result A E -> Prop),
+ (forall a, P (Value a)) ->
+ (forall e, P (Ex (Throw e))) ->
+ (forall msg, P (Ex (Failure msg))) ->
+ forall r, P r.
+intros.
+destruct r; auto.
+destruct e; auto.
+Qed.
+
+Lemma result_state_cases {A E S} {P : result A E * S -> Prop} :
+ (forall a s, P (Value a, s)) ->
+ (forall e s, P (Ex (Throw e), s)) ->
+ (forall msg s, P (Ex (Failure msg), s)) ->
+ forall rs, P rs.
+intros.
+destruct rs as [[a|[e|msg]] s]; auto.
+Qed.
+
+(* TODO: needs sets, not lists
+Lemma monadS_ext_eqI {Regs A E} {m m' : monadS Regs A E} s :
+ (forall a s', List.In (Value a, s') (m s) <-> List.In (Value a, s') (m' s)) ->
+ (forall e s', List.In (Ex (Throw e), s') (m s) <-> List.In (Ex (Throw e), s') (m' s)) ->
+ (forall msg s', List.In (Ex (Failure msg), s') (m s) <-> List.In (Ex (Failure msg), s') (m' s)) ->
+ m s = m' s.
+proof (intro set_eqI)
+ fix x
+ show "x \<in> m s \<longleftrightarrow> x \<in> m' s" using assms by (cases x rule: result_state_cases) auto
+qed
+
+lemma monadS_eqI:
+ fixes m m' :: "('regs, 'a, 'e) monadS"
+ assumes "\<And>s a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
+ and "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
+ and "\<And>s msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
+ shows "m = m'"
+ using assms by (intro ext monadS_ext_eqI)
+*)
+
+Lemma bindS_cases {Regs A B E} {m} {f : A -> monadS Regs B E} {r s s'} :
+ List.In (r, s') (bindS m f s) ->
+ (exists a a' s'', r = Value a /\ List.In (Value a', s'') (m s) /\ List.In (Value a, s') (f a' s'')) \/
+ (exists e, r = Ex e /\ List.In (Ex e, s') (m s)) \/
+ (exists e a s'', r = Ex e /\ List.In (Value a, s'') (m s) /\ List.In (Ex e, s') (f a s'')).
+unfold bindS.
+intro IN.
+apply List.in_flat_map in IN.
+destruct IN as [[r' s''] [INr' INr]].
+destruct r' as [a'|e'].
+* destruct r as [a|e].
+ + left. eauto 10.
+ + right; right. eauto 10.
+* right; left. simpl in INr. destruct INr as [|[]]. inversion H. subst. eauto 10.
+Qed.
+
+Lemma bindS_intro_Value {Regs A B E} {m} {f : A -> monadS Regs B E} {s a s' a' s''} :
+ List.In (Value a', s'') (m s) -> List.In (Value a, s') (f a' s'') -> List.In (Value a, s') (bindS m f s).
+intros; unfold bindS.
+apply List.in_flat_map.
+eauto.
+Qed.
+Lemma bindS_intro_Ex_left {Regs A B E} {m} {f : A -> monadS Regs B E} {s e s'} :
+ List.In (Ex e, s') (m s) -> List.In (Ex e, s') (bindS m f s).
+intros; unfold bindS.
+apply List.in_flat_map.
+exists (Ex e, s').
+auto with datatypes.
+Qed.
+Lemma bindS_intro_Ex_right {Regs A B E} {m} {f : A -> monadS Regs B E} {s e s' a s''} :
+ List.In (Ex e, s') (f a s'') -> List.In (Value a, s'') (m s) -> List.In (Ex e, s') (bindS m f s).
+intros; unfold bindS.
+apply List.in_flat_map.
+eauto.
+Qed.
+Hint Resolve bindS_intro_Value bindS_intro_Ex_left bindS_intro_Ex_right : bindS_intros.
+
+Lemma bindS_assoc Regs A B C E {m} {f : A -> monadS Regs B E} {g : B -> monadS Regs C E} :
+ bindS (bindS m f) g === bindS m (fun x => bindS (f x) g).
+intro s.
+unfold bindS.
+induction (m s) as [ | [[a | e] t]].
+* reflexivity.
+* simpl. rewrite <- IHl.
+ rewrite !List.flat_map_concat_map.
+ rewrite List.map_app.
+ rewrite List.concat_app.
+ reflexivity.
+* simpl. rewrite IHl. reflexivity.
+Qed.
+Hint Rewrite bindS_assoc : state.
+
+Lemma bindS_failS Regs A B E {msg} {f : A -> monadS Regs B E} :
+ bindS (failS msg) f = failS msg.
+reflexivity.
+Qed.
+Hint Rewrite bindS_failS : state.
+
+Lemma bindS_throwS Regs A B E {e} {f : A -> monadS Regs B E} :
+ bindS (throwS e) f = throwS e.
+reflexivity.
+Qed.
+Hint Rewrite bindS_throwS : state.
+
+(*declare seqS_def[simp]*)
+Lemma seqS_def Regs A E m (m' : monadS Regs A E) :
+ m >>$ m' = m >>$= (fun _ => m').
+reflexivity.
+Qed.
+Hint Rewrite seqS_def : state.
+
+Lemma Value_bindS_elim {Regs A B E} {a m} {f : A -> monadS Regs B E} {s s'} :
+ List.In (Value a, s') (bindS m f s) ->
+ exists s'' a', List.In (Value a', s'') (m s) /\ List.In (Value a, s') (f a' s'').
+intro H.
+apply bindS_cases in H.
+destruct H as [(a0 & a' & s'' & [= <-] & [*]) | [(e & [= ] & _) | (_ & _ & _ & [= ] & _)]].
+eauto.
+Qed.
+
+Lemma Ex_bindS_elim {Regs A B E} {e m s s'} {f : A -> monadS Regs B E} :
+ List.In (Ex e, s') (bindS m f s) ->
+ List.In (Ex e, s') (m s) \/
+ exists s'' a', List.In (Value a', s'') (m s) /\ List.In (Ex e, s') (f a' s'').
+intro H.
+apply bindS_cases in H.
+destruct H as [(? & ? & ? & [= ] & _) | [(? & [= <-] & X) | (? & ? & ? & [= <-] & X)]];
+eauto.
+Qed.
+
+Lemma try_catchS_returnS Regs A E1 E2 {a} {h : E1 -> monadS Regs A E2}:
+ try_catchS (returnS a) h = returnS a.
+reflexivity.
+Qed.
+Hint Rewrite try_catchS_returnS : state.
+Lemma try_catchS_failS Regs A E1 E2 {msg} {h : E1 -> monadS Regs A E2}:
+ try_catchS (failS msg) h = failS msg.
+reflexivity.
+Qed.
+Hint Rewrite try_catchS_failS : state.
+Lemma try_catchS_throwS Regs A E1 E2 {e} {h : E1 -> monadS Regs A E2}:
+ try_catchS (throwS e) h === h e.
+intro s.
+unfold try_catchS, throwS.
+simpl.
+auto using List.app_nil_r.
+Qed.
+Hint Rewrite try_catchS_throwS : state.
+
+Lemma try_catchS_cong (*[cong]:*) {Regs A E1 E2 m1 m2} {h1 h2 : E1 -> monadS Regs A E2} :
+ m1 === m2 ->
+ (forall e, h1 e === h2 e) ->
+ try_catchS m1 h1 === try_catchS m2 h2.
+intros H1 H2 s.
+unfold try_catchS.
+rewrite H1.
+rewrite !List.flat_map_concat_map.
+f_equal.
+apply List.map_ext_in.
+intros [[a|[e|msg]] s'] H_in; auto. apply H2.
+Qed.
+
+Add Parametric Morphism {Regs A E1 E2 : Type} : (@try_catchS Regs A E1 E2)
+ with signature equiv ==> equiv ==> equiv as try_catchS_morphism.
+intros. auto using try_catchS_cong.
+Qed.
+
+Add Parametric Morphism {Regs A E : Type} : (@catch_early_returnS Regs A E)
+ with signature equiv ==> equiv as catch_early_returnS_morphism.
+intros.
+unfold catch_early_returnS.
+rewrite H.
+reflexivity.
+Qed.
+
+Lemma try_catchS_cases {Regs A E1 E2 m} {h : E1 -> monadS Regs A E2} {r s s'} :
+ List.In (r, s') (try_catchS m h s) ->
+ (exists a, r = Value a /\ List.In (Value a, s') (m s)) \/
+ (exists msg, r = Ex (Failure msg) /\ List.In (Ex (Failure msg), s') (m s)) \/
+ (exists e s'', List.In (Ex (Throw e), s'') (m s) /\ List.In (r, s') (h e s'')).
+unfold try_catchS.
+intro IN.
+apply List.in_flat_map in IN.
+destruct IN as [[r' s''] [INr' INr]].
+destruct r' as [a'|[e'|msg]].
+* left. simpl in INr. destruct INr as [[= <- <-] | []]. eauto 10.
+* simpl in INr. destruct INr as [[= <- <-] | []]. eauto 10.
+* eauto 10.
+Qed.
+
+Lemma try_catchS_intros {Regs A E1 E2} {m} {h : E1 -> monadS Regs A E2} :
+ (forall s a s', List.In (Value a, s') (m s) -> List.In (Value a, s') (try_catchS m h s)) /\
+ (forall s msg s', List.In (Ex (Failure msg), s') (m s) -> List.In (Ex (Failure msg), s') (try_catchS m h s)) /\
+ (forall s e s'' r s', List.In (Ex (Throw e), s'') (m s) -> List.In (r, s') (h e s'') -> List.In (r, s') (try_catchS m h s)).
+repeat split; unfold try_catchS; intros;
+apply List.in_flat_map.
+* eexists; split; [ apply H | ]. simpl. auto.
+* eexists; split; [ apply H | ]. simpl. auto.
+* eexists; split; [ apply H | ]. simpl. auto.
+Qed.
+
+Lemma no_Ex_basic_builtins (*[simp]:*) {Regs E} {s s' : sequential_state Regs} {e : ex E} :
+ (forall A (a:A), ~ List.In (Ex e, s') (returnS a s)) /\
+ (forall A (f : _ -> A), ~ List.In (Ex e, s') (readS f s)) /\
+ (forall f, ~ List.In (Ex e, s') (updateS f s)) /\
+ (forall A (xs : list A), ~ List.In (Ex e, s') (chooseS xs s)).
+repeat split; intros;
+unfold returnS, readS, updateS, chooseS; simpl;
+try intuition congruence.
+* intro H.
+ apply List.in_map_iff in H.
+ destruct H as [x [X _]].
+ congruence.
+Qed.
+
+Import List.ListNotations.
+Definition ignore_throw_aux {A E1 E2 S} (rs : result A E1 * S) : list (result A E2 * S) :=
+match rs with
+| (Value a, s') => [(Value a, s')]
+| (Ex (Throw e), s') => []
+| (Ex (Failure msg), s') => [(Ex (Failure msg), s')]
+end.
+Definition ignore_throw {A E1 E2 S} (m : S -> list (result A E1 * S)) s : list (result A E2 * S) :=
+ List.flat_map ignore_throw_aux (m s).
+
+Lemma ignore_throw_cong {Regs A E1 E2} {m1 m2 : monadS Regs A E1} :
+ m1 === m2 ->
+ ignore_throw (E2 := E2) m1 === ignore_throw m2.
+intros H s.
+unfold ignore_throw.
+rewrite H.
+reflexivity.
+Qed.
+
+Lemma ignore_throw_aux_member_simps (*[simp]:*) {A E1 E2 S} {s' : S} {ms} :
+ (forall a:A, List.In (Value a, s') (ignore_throw_aux (E1 := E1) (E2 := E2) ms) <-> ms = (Value a, s')) /\
+ (forall e, ~ List.In (Ex (E := E2) (Throw e), s') (ignore_throw_aux ms)) /\
+ (forall msg, List.In (Ex (E := E2) (Failure msg), s') (ignore_throw_aux ms) <-> ms = (Ex (Failure msg), s')).
+destruct ms as [[a' | [e' | msg']] s]; simpl;
+intuition congruence.
+Qed.
+
+Lemma ignore_throw_member_simps (*[simp]:*) {A E1 E2 S} {s s' : S} {m} :
+ (forall {a:A}, List.In (Value (E := E2) a, s') (ignore_throw m s) <-> List.In (Value (E := E1) a, s') (m s)) /\
+ (forall {a:A}, List.In (Value (E := E2) a, s') (ignore_throw m s) <-> List.In (Value a, s') (m s)) /\
+ (forall e, ~ List.In (Ex (E := E2) (Throw e), s') (ignore_throw m s)) /\
+ (forall {msg}, List.In (Ex (E := E2) (Failure msg), s') (ignore_throw m s) <-> List.In (Ex (Failure msg), s') (m s)).
+unfold ignore_throw.
+repeat apply conj; intros; try apply conj;
+rewrite ?List.in_flat_map;
+solve
+[ intros [x [H1 H2]]; apply ignore_throw_aux_member_simps in H2; congruence
+| intro H; eexists; split; [ apply H | apply ignore_throw_aux_member_simps; reflexivity] ].
+Qed.
+
+Lemma ignore_throw_cases {A E S} {m : S -> list (result A E * S)} {r s s'} :
+ ignore_throw m s = m s ->
+ List.In (r, s') (m s) ->
+ (exists a, r = Value a) \/
+ (exists msg, r = Ex (Failure msg)).
+destruct r as [a | [e | msg]]; eauto.
+* intros H1 H2. rewrite <- H1 in H2.
+ apply ignore_throw_member_simps in H2.
+ destruct H2.
+Qed.
+
+(* *** *)
+Lemma flat_map_app {A B} {f : A -> list B} {l1 l2} :
+ List.flat_map f (l1 ++ l2) = (List.flat_map f l1 ++ List.flat_map f l2)%list.
+rewrite !List.flat_map_concat_map.
+rewrite List.map_app, List.concat_app.
+reflexivity.
+Qed.
+
+Lemma ignore_throw_bindS (*[simp]:*) Regs A B E E2 {m} {f : A -> monadS Regs B E} :
+ ignore_throw (E2 := E2) (bindS m f) === bindS (ignore_throw m) (fun s => ignore_throw (f s)).
+intro s.
+unfold bindS, ignore_throw.
+induction (m s) as [ | [[a | [e | msg]] t]].
+* reflexivity.
+* simpl. rewrite <- IHl. rewrite flat_map_app. reflexivity.
+* simpl. rewrite <- IHl. reflexivity.
+* simpl. apply IHl.
+Qed.
+Hint Rewrite ignore_throw_bindS : ignore_throw.
+
+Lemma try_catchS_bindS_no_throw {Regs A B E1 E2} {m1 : monadS Regs A E1} {m2 : monadS Regs A E2} {f : A -> monadS Regs B _} {h} :
+ ignore_throw m1 === m1 ->
+ ignore_throw m1 === m2 ->
+ try_catchS (bindS m1 f) h === bindS m2 (fun a => try_catchS (f a) h).
+intros Ignore1 Ignore2.
+transitivity ((ignore_throw m1 >>$= (fun a => try_catchS (f a) h))).
+* intro s.
+ unfold bindS, try_catchS, ignore_throw.
+ specialize (Ignore1 s). revert Ignore1. unfold ignore_throw.
+ induction (m1 s) as [ | [[a | [e | msg]] t]]; auto.
+ + intro Ig. simpl. rewrite flat_map_app. rewrite IHl. auto. injection Ig. auto.
+ + intro Ig. simpl. rewrite IHl. reflexivity. injection Ig. auto.
+ + intro Ig. exfalso. clear -Ig.
+ assert (List.In (Ex (Throw msg), t) (List.flat_map ignore_throw_aux l)).
+ simpl in Ig. rewrite Ig. simpl. auto.
+ apply List.in_flat_map in H.
+ destruct H as [x [H1 H2]].
+ apply ignore_throw_aux_member_simps in H2.
+ assumption.
+* apply bindS_cong; auto.
+Qed.
+
+Lemma concat_map_singleton {A B} {f : A -> B} {a : list A} :
+ List.concat (List.map (fun x => [f x]%list) a) = List.map f a.
+induction a; simpl; try rewrite IHa; auto with datatypes.
+Qed.
+
+(*lemma no_throw_basic_builtins[simp]:*)
+Lemma no_throw_basic_builtins_1 Regs A E E2 {a : A} :
+ ignore_throw (E1 := E2) (returnS a) = @returnS Regs A E a.
+reflexivity. Qed.
+Lemma no_throw_basic_builtins_2 Regs A E E2 {f : sequential_state Regs -> A} :
+ ignore_throw (E1 := E) (E2 := E2) (readS f) = readS f.
+reflexivity. Qed.
+Lemma no_throw_basic_builtins_3 Regs E E2 {f : sequential_state Regs -> sequential_state Regs} :
+ ignore_throw (E1 := E) (E2 := E2) (updateS f) = updateS f.
+reflexivity. Qed.
+Lemma no_throw_basic_builtins_4 Regs A E1 E2 {xs : list A} :
+ ignore_throw (E1 := E1) (chooseS xs) === @chooseS Regs A E2 xs.
+intro s.
+unfold ignore_throw, chooseS.
+rewrite List.flat_map_concat_map, List.map_map. simpl.
+rewrite concat_map_singleton.
+reflexivity.
+Qed.
+Lemma no_throw_basic_builtins_5 Regs E1 E2 :
+ ignore_throw (E1 := E1) (choose_boolS tt) = @choose_boolS Regs E2 tt.
+reflexivity. Qed.
+Lemma no_throw_basic_builtins_6 Regs A E1 E2 msg :
+ ignore_throw (E1 := E1) (failS msg) = @failS Regs A E2 msg.
+reflexivity. Qed.
+Lemma no_throw_basic_builtins_7 Regs A E1 E2 msg x :
+ ignore_throw (E1 := E1) (maybe_failS msg x) = @maybe_failS Regs A E2 msg x.
+destruct x; reflexivity. Qed.
+
+Hint Rewrite no_throw_basic_builtins_1 no_throw_basic_builtins_2
+ no_throw_basic_builtins_3 no_throw_basic_builtins_4
+ no_throw_basic_builtins_5 no_throw_basic_builtins_6
+ no_throw_basic_builtins_7 : ignore_throw.
+
+Lemma ignore_throw_option_case_distrib_1 Regs B C E1 E2 (c : sequential_state Regs -> option B) s (n : monadS Regs C E1) (f : B -> monadS Regs C E1) :
+ ignore_throw (E2 := E2) (match c s with None => n | Some b => f b end) s =
+ match c s with None => ignore_throw n s | Some b => ignore_throw (f b) s end.
+destruct (c s); auto.
+Qed.
+Lemma ignore_throw_option_case_distrib_2 Regs B C E1 E2 (c : option B) (n : monadS Regs C E1) (f : B -> monadS Regs C E1) :
+ ignore_throw (E2 := E2) (match c with None => n | Some b => f b end) =
+ match c with None => ignore_throw n | Some b => ignore_throw (f b) end.
+destruct c; auto.
+Qed.
+
+Lemma ignore_throw_let_distrib Regs A B E1 E2 (y : A) (f : A -> monadS Regs B E1) :
+ ignore_throw (E2 := E2) (let x := y in f x) = (let x := y in ignore_throw (f x)).
+reflexivity.
+Qed.
+
+Lemma no_throw_mem_builtins_1 Regs E1 E2 rk a sz :
+ ignore_throw (E2 := E2) (@read_memt_bytesS Regs E1 rk a sz) === read_memt_bytesS rk a sz.
+unfold read_memt_bytesS. autorewrite with ignore_throw.
+apply bindS_cong; auto. intros. autorewrite with ignore_throw. reflexivity.
+Qed.
+Hint Rewrite no_throw_mem_builtins_1 : ignore_throw.
+Lemma no_throw_mem_builtins_2 Regs E1 E2 rk a sz :
+ ignore_throw (E2 := E2) (@read_mem_bytesS Regs E1 rk a sz) === read_mem_bytesS rk a sz.
+unfold read_mem_bytesS. autorewrite with ignore_throw.
+apply bindS_cong; intros; autorewrite with ignore_throw; auto.
+destruct a0; reflexivity.
+Qed.
+Hint Rewrite no_throw_mem_builtins_2 : ignore_throw.
+Lemma no_throw_mem_builtins_3 Regs A E1 E2 a :
+ ignore_throw (E2 := E2) (@read_tagS Regs A E1 a) === read_tagS a.
+reflexivity. Qed.
+Hint Rewrite no_throw_mem_builtins_3 : ignore_throw.
+Lemma no_throw_mem_builtins_4 Regs A V E1 E2 rk a sz H :
+ ignore_throw (E2 := E2) (@read_memtS Regs E1 A V rk a sz H) === read_memtS rk a sz.
+unfold read_memtS. autorewrite with ignore_throw.
+apply bindS_cong; intros; autorewrite with ignore_throw.
+reflexivity. destruct a0; simpl. autorewrite with ignore_throw.
+reflexivity.
+Qed.
+Hint Rewrite no_throw_mem_builtins_4 : ignore_throw.
+Lemma no_throw_mem_builtins_5 Regs A V E1 E2 rk a sz H :
+ ignore_throw (E2 := E2) (@read_memS Regs E1 A V rk a sz H) === read_memS rk a sz.
+unfold read_memS. autorewrite with ignore_throw.
+apply bindS_cong; intros; autorewrite with ignore_throw; auto.
+destruct a0; auto.
+Qed.
+Hint Rewrite no_throw_mem_builtins_5 : ignore_throw.
+Lemma no_throw_mem_builtins_6 Regs E1 E2 wk addr sz v t :
+ ignore_throw (E2 := E2) (@write_memt_bytesS Regs E1 wk addr sz v t) === write_memt_bytesS wk addr sz v t.
+unfold write_memt_bytesS. unfold seqS. autorewrite with ignore_throw.
+reflexivity.
+Qed.
+Hint Rewrite no_throw_mem_builtins_6 : ignore_throw.
+Lemma no_throw_mem_builtins_7 Regs E1 E2 wk addr sz v :
+ ignore_throw (E2 := E2) (@write_mem_bytesS Regs E1 wk addr sz v) === write_mem_bytesS wk addr sz v.
+unfold write_mem_bytesS. autorewrite with ignore_throw. reflexivity.
+Qed.
+Hint Rewrite no_throw_mem_builtins_7 : ignore_throw.
+Lemma no_throw_mem_builtins_8 Regs E1 E2 A B wk addr sz v t :
+ ignore_throw (E2 := E2) (@write_memtS Regs E1 A B wk addr sz v t) === write_memtS wk addr sz v t.
+unfold write_memtS. rewrite ignore_throw_option_case_distrib_2.
+destruct (Sail2_values.mem_bytes_of_bits v); autorewrite with ignore_throw; auto.
+Qed.
+Hint Rewrite no_throw_mem_builtins_8 : ignore_throw.
+Lemma no_throw_mem_builtins_9 Regs E1 E2 A B wk addr sz v :
+ ignore_throw (E2 := E2) (@write_memS Regs E1 A B wk addr sz v) === write_memS wk addr sz v.
+unfold write_memS. autorewrite with ignore_throw; auto.
+Qed.
+Hint Rewrite no_throw_mem_builtins_9 : ignore_throw.
+Lemma no_throw_mem_builtins_10 Regs E1 E2 :
+ ignore_throw (E2 := E2) (@excl_resultS Regs E1 tt) === excl_resultS tt.
+reflexivity. Qed.
+Hint Rewrite no_throw_mem_builtins_10 : ignore_throw.
+Lemma no_throw_mem_builtins_11 Regs E1 E2 :
+ ignore_throw (E2 := E2) (@undefined_boolS Regs E1 tt) === undefined_boolS tt.
+reflexivity. Qed.
+Hint Rewrite no_throw_mem_builtins_11 : ignore_throw.
+
+Lemma no_throw_read_regvalS Regs RV E1 E2 r reg_name :
+ ignore_throw (E2 := E2) (@read_regvalS Regs RV E1 r reg_name) === read_regvalS r reg_name.
+destruct r; simpl. autorewrite with ignore_throw.
+apply bindS_cong; intros; auto. rewrite ignore_throw_option_case_distrib_2.
+autorewrite with ignore_throw. reflexivity.
+Qed.
+Hint Rewrite no_throw_read_regvalS : ignore_throw.
+
+Lemma no_throw_write_regvalS Regs RV E1 E2 r reg_name v :
+ ignore_throw (E2 := E2) (@write_regvalS Regs RV E1 r reg_name v) === write_regvalS r reg_name v.
+destruct r; simpl. autorewrite with ignore_throw.
+apply bindS_cong; intros; auto. rewrite ignore_throw_option_case_distrib_2.
+autorewrite with ignore_throw. reflexivity.
+Qed.
+Hint Rewrite no_throw_write_regvalS : ignore_throw.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_string.v b/prover_snapshots/coq/lib/sail/Sail2_string.v
new file mode 100644
index 0000000..a0a2393
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_string.v
@@ -0,0 +1,194 @@
+Require Import Sail2_values.
+Require Import Coq.Strings.Ascii.
+
+Definition string_sub (s : string) (start : Z) (len : Z) : string :=
+ String.substring (Z.to_nat start) (Z.to_nat len) s.
+
+Definition string_startswith s expected :=
+ let prefix := String.substring 0 (String.length expected) s in
+ generic_eq prefix expected.
+
+Definition string_drop s (n : Z) `{ArithFact (n >= 0)} :=
+ let n := Z.to_nat n in
+ String.substring n (String.length s - n) s.
+
+Definition string_take s (n : Z) `{ArithFact (n >= 0)} :=
+ let n := Z.to_nat n in
+ String.substring 0 n s.
+
+Definition string_length s : {n : Z & ArithFact (n >= 0)} :=
+ build_ex (Z.of_nat (String.length s)).
+
+Definition string_append := String.append.
+
+Local Open Scope char_scope.
+Local Definition hex_char (c : Ascii.ascii) : option Z :=
+match c with
+| "0" => Some 0
+| "1" => Some 1
+| "2" => Some 2
+| "3" => Some 3
+| "4" => Some 4
+| "5" => Some 5
+| "6" => Some 6
+| "7" => Some 7
+| "8" => Some 8
+| "9" => Some 9
+| "a" => Some 10
+| "b" => Some 11
+| "c" => Some 12
+| "d" => Some 13
+| "e" => Some 14
+| "f" => Some 15
+| _ => None
+end.
+Local Close Scope char_scope.
+Local Fixpoint more_digits (s : string) (base : Z) (acc : Z) (len : nat) : Z * nat :=
+match s with
+| EmptyString => (acc, len)
+| String "_" t => more_digits t base acc (S len)
+| String h t =>
+ match hex_char h with
+ | None => (acc, len)
+ | Some i =>
+ if i <? base
+ then more_digits t base (base * acc + i) (S len)
+ else (acc, len)
+ end
+end.
+Local Definition int_of (s : string) (base : Z) (len : nat) : option (Z * {n : Z & ArithFact (n >= 0)}) :=
+match s with
+| EmptyString => None
+| String h t =>
+ match hex_char h with
+ | None => None
+ | Some i =>
+ if i <? base
+ then
+ let (i, len') := more_digits t base i (S len) in
+ Some (i, build_ex (Z.of_nat len'))
+ else None
+ end
+end.
+
+(* I've stuck closely to OCaml's int_of_string, because that's what's currently
+ used elsewhere. *)
+
+Definition maybe_int_of_prefix (s : string) : option (Z * {n : Z & ArithFact (n >= 0)}) :=
+match s with
+| EmptyString => None
+| String "0" (String ("x"|"X") t) => int_of t 16 2
+| String "0" (String ("o"|"O") t) => int_of t 8 2
+| String "0" (String ("b"|"B") t) => int_of t 2 2
+| String "0" (String "u" t) => int_of t 10 2
+| String "-" t =>
+ match int_of t 10 1 with
+ | None => None
+ | Some (i,len) => Some (-i,len)
+ end
+| _ => int_of s 10 0
+end.
+
+Definition maybe_int_of_string (s : string) : option Z :=
+match maybe_int_of_prefix s with
+| None => None
+| Some (i,len) =>
+ if projT1 len =? projT1 (string_length s)
+ then Some i
+ else None
+end.
+
+Fixpoint n_leading_spaces (s:string) : nat :=
+ match s with
+ | EmptyString => 0
+ | String " " t => S (n_leading_spaces t)
+ | _ => 0
+ end.
+
+Definition opt_spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) :=
+ Some (tt, build_ex (Z.of_nat (n_leading_spaces s))).
+
+Definition spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) :=
+ match n_leading_spaces s with
+ | O => None
+ | S n => Some (tt, build_ex (Z.of_nat (S n)))
+ end.
+
+Definition hex_bits_n_matches_prefix sz `{ArithFact (sz >= 0)} s : option (mword sz * {n : Z & ArithFact (n >= 0)}) :=
+ match maybe_int_of_prefix s with
+ | None => None
+ | Some (n, len) =>
+ if andb (0 <=? n) (n <? pow 2 sz)
+ then Some (of_int sz n, len)
+ else None
+ end.
+
+Definition hex_bits_1_matches_prefix s := hex_bits_n_matches_prefix 1 s.
+Definition hex_bits_2_matches_prefix s := hex_bits_n_matches_prefix 2 s.
+Definition hex_bits_3_matches_prefix s := hex_bits_n_matches_prefix 3 s.
+Definition hex_bits_4_matches_prefix s := hex_bits_n_matches_prefix 4 s.
+Definition hex_bits_5_matches_prefix s := hex_bits_n_matches_prefix 5 s.
+Definition hex_bits_6_matches_prefix s := hex_bits_n_matches_prefix 6 s.
+Definition hex_bits_7_matches_prefix s := hex_bits_n_matches_prefix 7 s.
+Definition hex_bits_8_matches_prefix s := hex_bits_n_matches_prefix 8 s.
+Definition hex_bits_9_matches_prefix s := hex_bits_n_matches_prefix 9 s.
+Definition hex_bits_10_matches_prefix s := hex_bits_n_matches_prefix 10 s.
+Definition hex_bits_11_matches_prefix s := hex_bits_n_matches_prefix 11 s.
+Definition hex_bits_12_matches_prefix s := hex_bits_n_matches_prefix 12 s.
+Definition hex_bits_13_matches_prefix s := hex_bits_n_matches_prefix 13 s.
+Definition hex_bits_14_matches_prefix s := hex_bits_n_matches_prefix 14 s.
+Definition hex_bits_15_matches_prefix s := hex_bits_n_matches_prefix 15 s.
+Definition hex_bits_16_matches_prefix s := hex_bits_n_matches_prefix 16 s.
+Definition hex_bits_17_matches_prefix s := hex_bits_n_matches_prefix 17 s.
+Definition hex_bits_18_matches_prefix s := hex_bits_n_matches_prefix 18 s.
+Definition hex_bits_19_matches_prefix s := hex_bits_n_matches_prefix 19 s.
+Definition hex_bits_20_matches_prefix s := hex_bits_n_matches_prefix 20 s.
+Definition hex_bits_21_matches_prefix s := hex_bits_n_matches_prefix 21 s.
+Definition hex_bits_22_matches_prefix s := hex_bits_n_matches_prefix 22 s.
+Definition hex_bits_23_matches_prefix s := hex_bits_n_matches_prefix 23 s.
+Definition hex_bits_24_matches_prefix s := hex_bits_n_matches_prefix 24 s.
+Definition hex_bits_25_matches_prefix s := hex_bits_n_matches_prefix 25 s.
+Definition hex_bits_26_matches_prefix s := hex_bits_n_matches_prefix 26 s.
+Definition hex_bits_27_matches_prefix s := hex_bits_n_matches_prefix 27 s.
+Definition hex_bits_28_matches_prefix s := hex_bits_n_matches_prefix 28 s.
+Definition hex_bits_29_matches_prefix s := hex_bits_n_matches_prefix 29 s.
+Definition hex_bits_30_matches_prefix s := hex_bits_n_matches_prefix 30 s.
+Definition hex_bits_31_matches_prefix s := hex_bits_n_matches_prefix 31 s.
+Definition hex_bits_32_matches_prefix s := hex_bits_n_matches_prefix 32 s.
+Definition hex_bits_33_matches_prefix s := hex_bits_n_matches_prefix 33 s.
+Definition hex_bits_48_matches_prefix s := hex_bits_n_matches_prefix 48 s.
+Definition hex_bits_64_matches_prefix s := hex_bits_n_matches_prefix 64 s.
+
+Local Definition zero : N := Ascii.N_of_ascii "0".
+Local Fixpoint string_of_N (limit : nat) (n : N) (acc : string) : string :=
+match limit with
+| O => acc
+| S limit' =>
+ let (d,m) := N.div_eucl n 10 in
+ let acc := String (Ascii.ascii_of_N (m + zero)) acc in
+ if N.ltb 0 d then string_of_N limit' d acc else acc
+end.
+Local Fixpoint pos_limit p :=
+match p with
+| xH => S O
+| xI p | xO p => S (pos_limit p)
+end.
+Definition string_of_int (z : Z) : string :=
+match z with
+| Z0 => "0"
+| Zpos p => string_of_N (pos_limit p) (Npos p) ""
+| Zneg p => String "-" (string_of_N (pos_limit p) (Npos p) "")
+end.
+
+Definition decimal_string_of_bv {a} `{Bitvector a} (bv : a) : string :=
+ match unsigned bv with
+ | None => "?"
+ | Some i => string_of_int i
+ end.
+
+Definition decimal_string_of_bits {n} (bv : mword n) : string := decimal_string_of_bv bv.
+
+
+(* Some aliases for compatibility. *)
+Definition dec_str := string_of_int.
+Definition concat_str := String.append.
diff --git a/prover_snapshots/coq/lib/sail/Sail2_values.v b/prover_snapshots/coq/lib/sail/Sail2_values.v
new file mode 100644
index 0000000..208f5c8
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/Sail2_values.v
@@ -0,0 +1,2490 @@
+(* Version of sail_values.lem that uses Lems machine words library *)
+
+(*Require Import Sail_impl_base*)
+Require Export ZArith.
+Require Import Ascii.
+Require Export String.
+Require Import bbv.Word.
+Require Export List.
+Require Export Sumbool.
+Require Export DecidableClass.
+Require Import Eqdep_dec.
+Require Export Zeuclid.
+Require Import Psatz.
+Import ListNotations.
+
+Open Scope Z.
+
+Module Z_eq_dec.
+Definition U := Z.
+Definition eq_dec := Z.eq_dec.
+End Z_eq_dec.
+Module ZEqdep := DecidableEqDep (Z_eq_dec).
+
+
+(* Constraint solving basics. A HintDb which unfolding hints and lemmata
+ can be added to, and a typeclass to wrap constraint arguments in to
+ trigger automatic solving. *)
+Create HintDb sail.
+Class ArithFact (P : Prop) := { fact : P }.
+Lemma use_ArithFact {P} `(ArithFact P) : P.
+apply fact.
+Defined.
+
+(* Allow setoid rewriting through ArithFact *)
+Require Import Coq.Classes.Morphisms.
+Require Import Coq.Program.Basics.
+Require Import Coq.Program.Tactics.
+Section Morphism.
+Local Obligation Tactic := try solve [simpl_relation | firstorder auto].
+
+Global Program Instance ArithFact_iff_morphism :
+ Proper (iff ==> iff) ArithFact.
+End Morphism.
+
+
+Definition build_ex {T:Type} (n:T) {P:T -> Prop} `{H:ArithFact (P n)} : {x : T & ArithFact (P x)} :=
+ existT _ n H.
+
+
+Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness.
+Definition generic_neq {T:Type} (x y:T) `{Decidable (x = y)} := negb Decidable_witness.
+Lemma generic_eq_true {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = true -> x = y.
+apply Decidable_spec.
+Qed.
+Lemma generic_eq_false {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = false -> x <> y.
+unfold generic_eq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+congruence.
+Qed.
+Lemma generic_neq_true {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = true -> x <> y.
+unfold generic_neq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+destruct Decidable_witness; simpl in *;
+congruence.
+Qed.
+Lemma generic_neq_false {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = false -> x = y.
+unfold generic_neq.
+intro H1.
+rewrite <- Decidable_spec.
+destruct Decidable_witness; simpl in *;
+congruence.
+Qed.
+Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> y}) :
+ forall (x y : T), Decidable (eq x y) := {
+ Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y))
+}.
+destruct (eqdec x y); simpl; split; congruence.
+Defined.
+
+Instance Decidable_eq_string : forall (x y : string), Decidable (x = y) :=
+ Decidable_eq_from_dec String.string_dec.
+
+Instance Decidable_eq_pair {A B : Type} `(DA : forall x y : A, Decidable (x = y), DB : forall x y : B, Decidable (x = y)) : forall x y : A*B, Decidable (x = y) :=
+{ Decidable_witness := andb (@Decidable_witness _ (DA (fst x) (fst y)))
+(@Decidable_witness _ (DB (snd x) (snd y))) }.
+destruct x as [x1 x2].
+destruct y as [y1 y2].
+simpl.
+destruct (DA x1 y1) as [b1 H1];
+destruct (DB x2 y2) as [b2 H2];
+simpl.
+split.
+* intro H.
+ apply Bool.andb_true_iff in H.
+ destruct H as [H1b H2b].
+ apply H1 in H1b.
+ apply H2 in H2b.
+ congruence.
+* intro. inversion H.
+ subst.
+ apply Bool.andb_true_iff.
+ tauto.
+Qed.
+
+Definition generic_dec {T:Type} (x y:T) `{Decidable (x = y)} : {x = y} + {x <> y}.
+refine ((if Decidable_witness as b return (b = true <-> x = y -> _) then fun H' => _ else fun H' => _) Decidable_spec).
+* left. tauto.
+* right. intuition.
+Defined.
+
+Instance Decidable_eq_list {A : Type} `(D : forall x y : A, Decidable (x = y)) : forall (x y : list A), Decidable (x = y) :=
+ Decidable_eq_from_dec (list_eq_dec (fun x y => generic_dec x y)).
+
+(* Used by generated code that builds Decidable equality instances for records. *)
+Ltac cmp_record_field x y :=
+ let H := fresh "H" in
+ case (generic_dec x y);
+ intro H; [ |
+ refine (Build_Decidable _ false _);
+ split; [congruence | intros Z; destruct H; injection Z; auto]
+ ].
+
+
+
+(* Project away range constraints in comparisons *)
+Definition ltb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.ltb (projT1 l) r.
+Definition leb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.leb (projT1 l) r.
+Definition gtb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.gtb (projT1 l) r.
+Definition geb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.geb (projT1 l) r.
+Definition ltb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.ltb l (projT1 r).
+Definition leb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.leb l (projT1 r).
+Definition gtb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.gtb l (projT1 r).
+Definition geb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.geb l (projT1 r).
+
+Definition ii := Z.
+Definition nn := nat.
+
+(*val pow : Z -> Z -> Z*)
+Definition pow m n := m ^ n.
+
+Program Definition pow2 n : {z : Z & ArithFact (2 ^ n <= z <= 2 ^ n)} := existT _ (pow 2 n) _.
+Next Obligation.
+constructor.
+unfold pow.
+auto using Z.le_refl.
+Qed.
+
+Lemma ZEuclid_div_pos : forall x y, y > 0 -> x >= 0 -> ZEuclid.div x y >= 0.
+intros.
+unfold ZEuclid.div.
+change 0 with (0 * 0).
+apply Zmult_ge_compat; auto with zarith.
+* apply Z.le_ge. apply Z.sgn_nonneg. apply Z.ge_le. auto with zarith.
+* apply Z_div_ge0; auto. apply Z.lt_gt. apply Z.abs_pos. auto with zarith.
+Qed.
+
+Lemma ZEuclid_pos_div : forall x y, y > 0 -> ZEuclid.div x y >= 0 -> x >= 0.
+intros x y GT.
+ specialize (ZEuclid.div_mod x y);
+ specialize (ZEuclid.mod_always_pos x y);
+ generalize (ZEuclid.modulo x y);
+ generalize (ZEuclid.div x y);
+ intros.
+nia.
+Qed.
+
+Lemma ZEuclid_div_ge : forall x y, y > 0 -> x >= 0 -> x - ZEuclid.div x y >= 0.
+intros.
+unfold ZEuclid.div.
+rewrite Z.sgn_pos; auto with zarith.
+rewrite Z.mul_1_l.
+apply Z.le_ge.
+apply Zle_minus_le_0.
+apply Z.div_le_upper_bound.
+* apply Z.abs_pos. auto with zarith.
+* rewrite Z.mul_comm.
+ assert (0 < Z.abs y). {
+ apply Z.abs_pos.
+ omega.
+ }
+ revert H1.
+ generalize (Z.abs y). intros. nia.
+Qed.
+
+Lemma ZEuclid_div_mod0 : forall x y, y <> 0 ->
+ ZEuclid.modulo x y = 0 ->
+ y * ZEuclid.div x y = x.
+intros x y H1 H2.
+rewrite Zplus_0_r_reverse at 1.
+rewrite <- H2.
+symmetry.
+apply ZEuclid.div_mod.
+assumption.
+Qed.
+
+Hint Resolve ZEuclid_div_pos ZEuclid_pos_div ZEuclid_div_ge ZEuclid_div_mod0 : sail.
+
+
+(*
+Definition inline lt := (<)
+Definition inline gt := (>)
+Definition inline lteq := (<=)
+Definition inline gteq := (>=)
+
+val eq : forall a. Eq a => a -> a -> bool
+Definition inline eq l r := (l = r)
+
+val neq : forall a. Eq a => a -> a -> bool*)
+Definition neq l r := (negb (l =? r)). (* Z only *)
+
+(*let add_int l r := integerAdd l r
+Definition add_signed l r := integerAdd l r
+Definition sub_int l r := integerMinus l r
+Definition mult_int l r := integerMult l r
+Definition div_int l r := integerDiv l r
+Definition div_nat l r := natDiv l r
+Definition power_int_nat l r := integerPow l r
+Definition power_int_int l r := integerPow l (Z.to_nat r)
+Definition negate_int i := integerNegate i
+Definition min_int l r := integerMin l r
+Definition max_int l r := integerMax l r
+
+Definition add_real l r := realAdd l r
+Definition sub_real l r := realMinus l r
+Definition mult_real l r := realMult l r
+Definition div_real l r := realDiv l r
+Definition negate_real r := realNegate r
+Definition abs_real r := realAbs r
+Definition power_real b e := realPowInteger b e*)
+
+Definition print_endline (_ : string) : unit := tt.
+Definition prerr_endline (_ : string) : unit := tt.
+Definition prerr (_ : string) : unit := tt.
+Definition print_int (_ : string) (_ : Z) : unit := tt.
+Definition prerr_int (_ : string) (_ : Z) : unit := tt.
+Definition putchar (_ : Z) : unit := tt.
+
+Definition shl_int := Z.shiftl.
+Definition shr_int := Z.shiftr.
+
+(*
+Definition or_bool l r := (l || r)
+Definition and_bool l r := (l && r)
+Definition xor_bool l r := xor l r
+*)
+Definition append_list {A:Type} (l : list A) r := l ++ r.
+Definition length_list {A:Type} (xs : list A) := Z.of_nat (List.length xs).
+Definition take_list {A:Type} n (xs : list A) := firstn (Z.to_nat n) xs.
+Definition drop_list {A:Type} n (xs : list A) := skipn (Z.to_nat n) xs.
+(*
+val repeat : forall a. list a -> Z -> list a*)
+Fixpoint repeat' {a} (xs : list a) n :=
+ match n with
+ | O => []
+ | S n => xs ++ repeat' xs n
+ end.
+Lemma repeat'_length {a} {xs : list a} {n : nat} : List.length (repeat' xs n) = (n * List.length xs)%nat.
+induction n.
+* reflexivity.
+* simpl.
+ rewrite app_length.
+ auto with arith.
+Qed.
+Definition repeat {a} (xs : list a) (n : Z) :=
+ if n <=? 0 then []
+ else repeat' xs (Z.to_nat n).
+Lemma repeat_length {a} {xs : list a} {n : Z} (H : n >= 0) : length_list (repeat xs n) = n * length_list xs.
+unfold length_list, repeat.
+destruct n.
++ reflexivity.
++ simpl (List.length _).
+ rewrite repeat'_length.
+ rewrite Nat2Z.inj_mul.
+ rewrite positive_nat_Z.
+ reflexivity.
++ exfalso.
+ auto with zarith.
+Qed.
+
+(*declare {isabelle} termination_argument repeat = automatic
+
+Definition duplicate_to_list bit length := repeat [bit] length
+
+Fixpoint replace bs (n : Z) b' := match bs with
+ | [] => []
+ | b :: bs =>
+ if n = 0 then b' :: bs
+ else b :: replace bs (n - 1) b'
+ end
+declare {isabelle} termination_argument replace = automatic
+
+Definition upper n := n
+
+(* Modulus operation corresponding to quot below -- result
+ has sign of dividend. *)
+Definition hardware_mod (a: Z) (b:Z) : Z :=
+ let m := (abs a) mod (abs b) in
+ if a < 0 then ~m else m
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+Definition hardware_quot (a:Z) (b:Z) : Z :=
+ let q := (abs a) / (abs b) in
+ if ((a<0) = (b<0)) then
+ q (* same sign -- result positive *)
+ else
+ ~q (* different sign -- result negative *)
+
+Definition max_64u := (integerPow 2 64) - 1
+Definition max_64 := (integerPow 2 63) - 1
+Definition min_64 := 0 - (integerPow 2 63)
+Definition max_32u := (4294967295 : Z)
+Definition max_32 := (2147483647 : Z)
+Definition min_32 := (0 - 2147483648 : Z)
+Definition max_8 := (127 : Z)
+Definition min_8 := (0 - 128 : Z)
+Definition max_5 := (31 : Z)
+Definition min_5 := (0 - 32 : Z)
+*)
+
+(* just_list takes a list of maybes and returns Some xs if all elements have
+ a value, and None if one of the elements is None. *)
+(*val just_list : forall a. list (option a) -> option (list a)*)
+Fixpoint just_list {A} (l : list (option A)) := match l with
+ | [] => Some []
+ | (x :: xs) =>
+ match (x, just_list xs) with
+ | (Some x, Some xs) => Some (x :: xs)
+ | (_, _) => None
+ end
+ end.
+(*declare {isabelle} termination_argument just_list = automatic
+
+lemma just_list_spec:
+ ((forall xs. (just_list xs = None) <-> List.elem None xs) &&
+ (forall xs es. (just_list xs = Some es) <-> (xs = List.map Some es)))*)
+
+Lemma just_list_length {A} : forall (l : list (option A)) (l' : list A),
+ Some l' = just_list l -> List.length l = List.length l'.
+induction l.
+* intros.
+ simpl in H.
+ inversion H.
+ reflexivity.
+* intros.
+ destruct a; simplify_eq H.
+ simpl in *.
+ destruct (just_list l); simplify_eq H.
+ intros.
+ subst.
+ simpl.
+ f_equal.
+ apply IHl.
+ reflexivity.
+Qed.
+
+Lemma just_list_length_Z {A} : forall (l : list (option A)) l', Some l' = just_list l -> length_list l = length_list l'.
+unfold length_list.
+intros.
+f_equal.
+auto using just_list_length.
+Qed.
+
+Fixpoint member_Z_list (x : Z) (l : list Z) : bool :=
+match l with
+| [] => false
+| h::t => if x =? h then true else member_Z_list x t
+end.
+
+Lemma member_Z_list_In {x l} : member_Z_list x l = true <-> In x l.
+induction l.
+* simpl. split. congruence. tauto.
+* simpl. destruct (x =? a) eqn:H.
+ + rewrite Z.eqb_eq in H. subst. tauto.
+ + rewrite Z.eqb_neq in H. split.
+ - intro Heq. right. apply IHl. assumption.
+ - intros [bad | good]. congruence. apply IHl. assumption.
+Qed.
+
+(*** Bits *)
+Inductive bitU := B0 | B1 | BU.
+
+Scheme Equality for bitU.
+Definition eq_bit := bitU_beq.
+Instance Decidable_eq_bit : forall (x y : bitU), Decidable (x = y) :=
+ Decidable_eq_from_dec bitU_eq_dec.
+
+Definition showBitU b :=
+match b with
+ | B0 => "O"
+ | B1 => "I"
+ | BU => "U"
+end%string.
+
+Definition bitU_char b :=
+match b with
+| B0 => "0"
+| B1 => "1"
+| BU => "?"
+end%char.
+
+(*instance (Show bitU)
+ let show := showBitU
+end*)
+
+Class BitU (a : Type) : Type := {
+ to_bitU : a -> bitU;
+ of_bitU : bitU -> a
+}.
+
+Instance bitU_BitU : (BitU bitU) := {
+ to_bitU b := b;
+ of_bitU b := b
+}.
+
+Definition bool_of_bitU bu := match bu with
+ | B0 => Some false
+ | B1 => Some true
+ | BU => None
+ end.
+
+Definition bitU_of_bool (b : bool) := if b then B1 else B0.
+
+(*Instance bool_BitU : (BitU bool) := {
+ to_bitU := bitU_of_bool;
+ of_bitU := bool_of_bitU
+}.*)
+
+Definition cast_bit_bool := bool_of_bitU.
+(*
+Definition bit_lifted_of_bitU bu := match bu with
+ | B0 => Bitl_zero
+ | B1 => Bitl_one
+ | BU => Bitl_undef
+ end.
+
+Definition bitU_of_bit := function
+ | Bitc_zero => B0
+ | Bitc_one => B1
+ end.
+
+Definition bit_of_bitU := function
+ | B0 => Bitc_zero
+ | B1 => Bitc_one
+ | BU => failwith "bit_of_bitU: BU"
+ end.
+
+Definition bitU_of_bit_lifted := function
+ | Bitl_zero => B0
+ | Bitl_one => B1
+ | Bitl_undef => BU
+ | Bitl_unknown => failwith "bitU_of_bit_lifted Bitl_unknown"
+ end.
+*)
+Definition not_bit b :=
+match b with
+ | B1 => B0
+ | B0 => B1
+ | BU => BU
+ end.
+
+(*val is_one : Z -> bitU*)
+Definition is_one (i : Z) :=
+ if i =? 1 then B1 else B0.
+
+Definition binop_bit op x y :=
+ match (x, y) with
+ | (BU,_) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+ | (_,BU) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+(* | (x,y) => bitU_of_bool (op (bool_of_bitU x) (bool_of_bitU y))*)
+ | (B0,B0) => bitU_of_bool (op false false)
+ | (B0,B1) => bitU_of_bool (op false true)
+ | (B1,B0) => bitU_of_bool (op true false)
+ | (B1,B1) => bitU_of_bool (op true true)
+ end.
+
+(*val and_bit : bitU -> bitU -> bitU*)
+Definition and_bit := binop_bit andb.
+
+(*val or_bit : bitU -> bitU -> bitU*)
+Definition or_bit := binop_bit orb.
+
+(*val xor_bit : bitU -> bitU -> bitU*)
+Definition xor_bit := binop_bit xorb.
+
+(*val (&.) : bitU -> bitU -> bitU
+Definition inline (&.) x y := and_bit x y
+
+val (|.) : bitU -> bitU -> bitU
+Definition inline (|.) x y := or_bit x y
+
+val (+.) : bitU -> bitU -> bitU
+Definition inline (+.) x y := xor_bit x y
+*)
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+Fixpoint bools_of_nat_aux len (x : nat) (acc : list bool) : list bool :=
+ match len with
+ | O => acc
+ | S len' => bools_of_nat_aux len' (x / 2) ((if x mod 2 =? 1 then true else false) :: acc)
+ end %nat.
+ (*else (if x mod 2 = 1 then true else false) :: bools_of_nat_aux (x / 2)*)
+(*declare {isabelle} termination_argument bools_of_nat_aux = automatic*)
+Definition bools_of_nat len n := bools_of_nat_aux (Z.to_nat len) n [] (*List.reverse (bools_of_nat_aux n)*).
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+Fixpoint nat_of_bools_aux (acc : nat) (bs : list bool) : nat :=
+ match bs with
+ | [] => acc
+ | true :: bs => nat_of_bools_aux ((2 * acc) + 1) bs
+ | false :: bs => nat_of_bools_aux (2 * acc) bs
+end.
+(*declare {isabelle; hol} termination_argument nat_of_bools_aux = automatic*)
+Definition nat_of_bools bs := nat_of_bools_aux 0 bs.
+
+(*val unsigned_of_bools : list bool -> integer*)
+Definition unsigned_of_bools bs := Z.of_nat (nat_of_bools bs).
+
+(*val signed_of_bools : list bool -> integer*)
+Definition signed_of_bools bs :=
+ match bs with
+ | true :: _ => 0 - (1 + (unsigned_of_bools (List.map negb bs)))
+ | false :: _ => unsigned_of_bools bs
+ | [] => 0 (* Treat empty list as all zeros *)
+ end.
+
+(*val int_of_bools : bool -> list bool -> integer*)
+Definition int_of_bools (sign : bool) bs := if sign then signed_of_bools bs else unsigned_of_bools bs.
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+Fixpoint pad_list_nat {a} (x : a) (xs : list a) n :=
+ match n with
+ | O => xs
+ | S n' => pad_list_nat x (x :: xs) n'
+ end.
+(*declare {isabelle} termination_argument pad_list = automatic*)
+Definition pad_list {a} x xs n := @pad_list_nat a x xs (Z.to_nat n).
+
+Definition ext_list {a} pad len (xs : list a) :=
+ let longer := len - (Z.of_nat (List.length xs)) in
+ if longer <? 0 then skipn (Z.abs_nat (longer)) xs
+ else pad_list pad xs longer.
+
+(*let extz_bools len bs = ext_list false len bs*)
+Definition exts_bools len bs :=
+ match bs with
+ | true :: _ => ext_list true len bs
+ | _ => ext_list false len bs
+ end.
+
+Fixpoint add_one_bool_ignore_overflow_aux bits := match bits with
+ | [] => []
+ | false :: bits => true :: bits
+ | true :: bits => false :: add_one_bool_ignore_overflow_aux bits
+end.
+(*declare {isabelle; hol} termination_argument add_one_bool_ignore_overflow_aux = automatic*)
+
+Definition add_one_bool_ignore_overflow bits :=
+ List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)).
+
+(* Ported from Lem, bad for large n.
+Definition bools_of_int len n :=
+ let bs_abs := bools_of_nat len (Z.abs_nat n) in
+ if n >=? 0 then bs_abs
+ else add_one_bool_ignore_overflow (List.map negb bs_abs).
+*)
+Fixpoint bitlistFromWord_rev {n} w :=
+match w with
+| WO => []
+| WS b w => b :: bitlistFromWord_rev w
+end.
+Definition bitlistFromWord {n} w :=
+ List.rev (@bitlistFromWord_rev n w).
+
+Definition bools_of_int len n :=
+ let w := Word.ZToWord (Z.to_nat len) n in
+ bitlistFromWord w.
+
+(*** Bit lists ***)
+
+(*val bits_of_nat_aux : natural -> list bitU*)
+Fixpoint bits_of_nat_aux n x :=
+ match n,x with
+ | O,_ => []
+ | _,O => []
+ | S n, S _ => (if x mod 2 =? 1 then B1 else B0) :: bits_of_nat_aux n (x / 2)
+ end%nat.
+(**declare {isabelle} termination_argument bits_of_nat_aux = automatic*)
+Definition bits_of_nat n := List.rev (bits_of_nat_aux n n).
+
+(*val nat_of_bits_aux : natural -> list bitU -> natural*)
+Fixpoint nat_of_bits_aux acc bs := match bs with
+ | [] => Some acc
+ | B1 :: bs => nat_of_bits_aux ((2 * acc) + 1) bs
+ | B0 :: bs => nat_of_bits_aux (2 * acc) bs
+ | BU :: bs => None
+end%nat.
+(*declare {isabelle} termination_argument nat_of_bits_aux = automatic*)
+Definition nat_of_bits bits := nat_of_bits_aux 0 bits.
+
+Definition not_bits := List.map not_bit.
+
+Definition binop_bits op bsl bsr :=
+ List.fold_right (fun '(bl, br) acc => binop_bit op bl br :: acc) [] (List.combine bsl bsr).
+(*
+Definition and_bits := binop_bits (&&)
+Definition or_bits := binop_bits (||)
+Definition xor_bits := binop_bits xor
+
+val unsigned_of_bits : list bitU -> Z*)
+Definition unsigned_of_bits bits :=
+match just_list (List.map bool_of_bitU bits) with
+| Some bs => Some (unsigned_of_bools bs)
+| None => None
+end.
+
+(*val signed_of_bits : list bitU -> Z*)
+Definition signed_of_bits bits :=
+ match just_list (List.map bool_of_bitU bits) with
+ | Some bs => Some (signed_of_bools bs)
+ | None => None
+ end.
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+Definition int_of_bits (sign : bool) bs :=
+ if sign then signed_of_bits bs else unsigned_of_bits bs.
+
+(*val pad_bitlist : bitU -> list bitU -> Z -> list bitU*)
+Fixpoint pad_bitlist_nat (b : bitU) bits n :=
+match n with
+| O => bits
+| S n' => pad_bitlist_nat b (b :: bits) n'
+end.
+Definition pad_bitlist b bits n := pad_bitlist_nat b bits (Z.to_nat n). (* Negative n will come out as 0 *)
+(* if n <= 0 then bits else pad_bitlist b (b :: bits) (n - 1).
+declare {isabelle} termination_argument pad_bitlist = automatic*)
+
+Definition ext_bits pad len bits :=
+ let longer := len - (Z.of_nat (List.length bits)) in
+ if longer <? 0 then skipn (Z.abs_nat longer) bits
+ else pad_bitlist pad bits longer.
+
+Definition extz_bits len bits := ext_bits B0 len bits.
+Parameter undefined_list_bitU : list bitU.
+Definition exts_bits len bits :=
+ match bits with
+ | BU :: _ => undefined_list_bitU (*failwith "exts_bits: undefined bit"*)
+ | B1 :: _ => ext_bits B1 len bits
+ | _ => ext_bits B0 len bits
+ end.
+
+Fixpoint add_one_bit_ignore_overflow_aux bits := match bits with
+ | [] => []
+ | B0 :: bits => B1 :: bits
+ | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
+ | BU :: _ => undefined_list_bitU (*failwith "add_one_bit_ignore_overflow: undefined bit"*)
+end.
+(*declare {isabelle} termination_argument add_one_bit_ignore_overflow_aux = automatic*)
+
+Definition add_one_bit_ignore_overflow bits :=
+ rev (add_one_bit_ignore_overflow_aux (rev bits)).
+
+Definition bitlist_of_int n :=
+ let bits_abs := B0 :: bits_of_nat (Z.abs_nat n) in
+ if n >=? 0 then bits_abs
+ else add_one_bit_ignore_overflow (not_bits bits_abs).
+
+Definition bits_of_int len n := exts_bits len (bitlist_of_int n).
+
+(*val arith_op_bits :
+ (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+Definition arith_op_bits (op : Z -> Z -> Z) (sign : bool) l r :=
+ match (int_of_bits sign l, int_of_bits sign r) with
+ | (Some li, Some ri) => bits_of_int (length_list l) (op li ri)
+ | (_, _) => repeat [BU] (length_list l)
+ end.
+
+
+Definition char_of_nibble x :=
+ match x with
+ | (B0, B0, B0, B0) => Some "0"%char
+ | (B0, B0, B0, B1) => Some "1"%char
+ | (B0, B0, B1, B0) => Some "2"%char
+ | (B0, B0, B1, B1) => Some "3"%char
+ | (B0, B1, B0, B0) => Some "4"%char
+ | (B0, B1, B0, B1) => Some "5"%char
+ | (B0, B1, B1, B0) => Some "6"%char
+ | (B0, B1, B1, B1) => Some "7"%char
+ | (B1, B0, B0, B0) => Some "8"%char
+ | (B1, B0, B0, B1) => Some "9"%char
+ | (B1, B0, B1, B0) => Some "A"%char
+ | (B1, B0, B1, B1) => Some "B"%char
+ | (B1, B1, B0, B0) => Some "C"%char
+ | (B1, B1, B0, B1) => Some "D"%char
+ | (B1, B1, B1, B0) => Some "E"%char
+ | (B1, B1, B1, B1) => Some "F"%char
+ | _ => None
+ end.
+
+Fixpoint hexstring_of_bits bs := match bs with
+ | b1 :: b2 :: b3 :: b4 :: bs =>
+ let n := char_of_nibble (b1, b2, b3, b4) in
+ let s := hexstring_of_bits bs in
+ match (n, s) with
+ | (Some n, Some s) => Some (String n s)
+ | _ => None
+ end
+ | [] => Some EmptyString
+ | _ => None
+ end%string.
+
+Fixpoint binstring_of_bits bs := match bs with
+ | b :: bs => String (bitU_char b) (binstring_of_bits bs)
+ | [] => EmptyString
+ end.
+
+Definition show_bitlist bs :=
+ match hexstring_of_bits bs with
+ | Some s => String "0" (String "x" s)
+ | None => String "0" (String "b" (binstring_of_bits bs))
+ end.
+
+(*** List operations *)
+(*
+Definition inline (^^) := append_list
+
+val subrange_list_inc : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_inc {A} (xs : list A) i j :=
+ let toJ := firstn (Z.to_nat j + 1) xs in
+ let fromItoJ := skipn (Z.to_nat i) toJ in
+ fromItoJ.
+
+(*val subrange_list_dec : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_dec {A} (xs : list A) i j :=
+ let top := (length_list xs) - 1 in
+ subrange_list_inc xs (top - i) (top - j).
+
+(*val subrange_list : forall a. bool -> list a -> Z -> Z -> list a*)
+Definition subrange_list {A} (is_inc : bool) (xs : list A) i j :=
+ if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j.
+
+Definition splitAt {A} n (l : list A) := (firstn n l, skipn n l).
+
+(*val update_subrange_list_inc : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_inc {A} (xs : list A) i j xs' :=
+ let (toJ,suffix) := splitAt (Z.to_nat j + 1) xs in
+ let (prefix,_fromItoJ) := splitAt (Z.to_nat i) toJ in
+ prefix ++ xs' ++ suffix.
+
+(*val update_subrange_list_dec : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_dec {A} (xs : list A) i j xs' :=
+ let top := (length_list xs) - 1 in
+ update_subrange_list_inc xs (top - i) (top - j) xs'.
+
+(*val update_subrange_list : forall a. bool -> list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list {A} (is_inc : bool) (xs : list A) i j xs' :=
+ if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'.
+
+Open Scope nat.
+Fixpoint nth_in_range {A} (n:nat) (l:list A) : n < length l -> A.
+refine
+ (match n, l with
+ | O, h::_ => fun _ => h
+ | S m, _::t => fun H => nth_in_range A m t _
+ | _,_ => fun H => _
+ end).
+exfalso. inversion H.
+exfalso. inversion H.
+simpl in H. omega.
+Defined.
+
+Lemma nth_in_range_is_nth : forall A n (l : list A) d (H : n < length l),
+ nth_in_range n l H = nth n l d.
+intros until d. revert n.
+induction l; intros n H.
+* inversion H.
+* destruct n.
+ + reflexivity.
+ + apply IHl.
+Qed.
+
+Lemma nth_Z_nat {A} {n} {xs : list A} :
+ (0 <= n)%Z -> (n < length_list xs)%Z -> Z.to_nat n < length xs.
+unfold length_list.
+intros nonneg bounded.
+rewrite Z2Nat.inj_lt in bounded; auto using Zle_0_nat.
+rewrite Nat2Z.id in bounded.
+assumption.
+Qed.
+
+(*
+Lemma nth_top_aux {A} {n} {xs : list A} : Z.to_nat n < length xs -> let top := ((length_list xs) - 1)%Z in Z.to_nat (top - n)%Z < length xs.
+unfold length_list.
+generalize (length xs).
+intro n0.
+rewrite <- (Nat2Z.id n0).
+intro H.
+apply Z2Nat.inj_lt.
+* omega.
+*)
+
+Close Scope nat.
+
+(*val access_list_inc : forall a. list a -> Z -> a*)
+Definition access_list_inc {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} := nth_in_range (Z.to_nat n) xs (nth_Z_nat (use_ArithFact _) (use_ArithFact _)).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_dec {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} : A.
+refine (
+ let top := (length_list xs) - 1 in
+ @access_list_inc A xs (top - n) _ _).
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+Defined.
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list {A} (is_inc : bool) (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} :=
+ if is_inc then access_list_inc xs n else access_list_dec xs n.
+
+Definition access_list_opt_inc {A} (xs : list A) n := nth_error xs (Z.to_nat n).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_opt_dec {A} (xs : list A) n :=
+ let top := (length_list xs) - 1 in
+ access_list_opt_inc xs (top - n).
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list_opt {A} (is_inc : bool) (xs : list A) n :=
+ if is_inc then access_list_opt_inc xs n else access_list_opt_dec xs n.
+
+Definition list_update {A} (xs : list A) n x := firstn n xs ++ x :: skipn (S n) xs.
+
+(*val update_list_inc : forall a. list a -> Z -> a -> list a*)
+Definition update_list_inc {A} (xs : list A) n x := list_update xs (Z.to_nat n) x.
+
+(*val update_list_dec : forall a. list a -> Z -> a -> list a*)
+Definition update_list_dec {A} (xs : list A) n x :=
+ let top := (length_list xs) - 1 in
+ update_list_inc xs (top - n) x.
+
+(*val update_list : forall a. bool -> list a -> Z -> a -> list a*)
+Definition update_list {A} (is_inc : bool) (xs : list A) n x :=
+ if is_inc then update_list_inc xs n x else update_list_dec xs n x.
+
+(*Definition extract_only_element := function
+ | [] => failwith "extract_only_element called for empty list"
+ | [e] => e
+ | _ => failwith "extract_only_element called for list with more elements"
+end*)
+
+(*** Machine words *)
+
+Definition mword (n : Z) :=
+ match n with
+ | Zneg _ => False
+ | Z0 => word 0
+ | Zpos p => word (Pos.to_nat p)
+ end.
+
+Definition get_word {n} : mword n -> word (Z.to_nat n) :=
+ match n with
+ | Zneg _ => fun x => match x with end
+ | Z0 => fun x => x
+ | Zpos p => fun x => x
+ end.
+
+Definition with_word {n} {P : Type -> Type} : (word (Z.to_nat n) -> P (word (Z.to_nat n))) -> mword n -> P (mword n) :=
+match n with
+| Zneg _ => fun f w => match w with end
+| Z0 => fun f w => f w
+| Zpos _ => fun f w => f w
+end.
+
+Program Definition to_word {n} : n >= 0 -> word (Z.to_nat n) -> mword n :=
+ match n with
+ | Zneg _ => fun H _ => _
+ | Z0 => fun _ w => w
+ | Zpos _ => fun _ w => w
+ end.
+
+Definition word_to_mword {n} (w : word (Z.to_nat n)) `{H:ArithFact (n >= 0)} : mword n :=
+ to_word (match H with Build_ArithFact _ H' => H' end) w.
+
+(*val length_mword : forall a. mword a -> Z*)
+Definition length_mword {n} (w : mword n) := n.
+
+(*val slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b*)
+(*Definition slice_mword_dec w i j := word_extract (Z.to_nat i) (Z.to_nat j) w.
+
+val slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b
+Definition slice_mword_inc w i j :=
+ let top := (length_mword w) - 1 in
+ slice_mword_dec w (top - i) (top - j)
+
+val slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b
+Definition slice_mword is_inc w i j := if is_inc then slice_mword_inc w i j else slice_mword_dec w i j
+
+val update_slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_dec w i j w' := word_update w (Z.to_nat i) (Z.to_nat j) w'
+
+val update_slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_inc w i j w' :=
+ let top := (length_mword w) - 1 in
+ update_slice_mword_dec w (top - i) (top - j) w'
+
+val update_slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword is_inc w i j w' :=
+ if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'
+
+val access_mword_dec : forall a. mword a -> Z -> bitU*)
+Parameter undefined_bit : bool.
+Definition getBit {n} :=
+match n with
+| O => fun (w : word O) i => undefined_bit
+| S n => fun (w : word (S n)) i => wlsb (wrshift' w i)
+end.
+
+Definition access_mword_dec {m} (w : mword m) n := bitU_of_bool (getBit (get_word w) (Z.to_nat n)).
+
+(*val access_mword_inc : forall a. mword a -> Z -> bitU*)
+Definition access_mword_inc {m} (w : mword m) n :=
+ let top := (length_mword w) - 1 in
+ access_mword_dec w (top - n).
+
+(*Parameter access_mword : forall {a}, bool -> mword a -> Z -> bitU.*)
+Definition access_mword {a} (is_inc : bool) (w : mword a) n :=
+ if is_inc then access_mword_inc w n else access_mword_dec w n.
+
+Definition setBit {n} :=
+match n with
+| O => fun (w : word O) i b => w
+| S n => fun (w : word (S n)) i (b : bool) =>
+ let bit : word (S n) := wlshift' (natToWord _ 1) i in
+ let mask : word (S n) := wnot bit in
+ let masked := wand mask w in
+ if b then masked else wor masked bit
+end.
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+Definition update_mword_bool_dec {a} (w : mword a) n b : mword a :=
+ with_word (P := id) (fun w => setBit w (Z.to_nat n) b) w.
+Definition update_mword_dec {a} (w : mword a) n b :=
+ match bool_of_bitU b with
+ | Some bl => Some (update_mword_bool_dec w n bl)
+ | None => None
+ end.
+
+(*val update_mword_inc : forall a. mword a -> Z -> bitU -> mword a*)
+Definition update_mword_inc {a} (w : mword a) n b :=
+ let top := (length_mword w) - 1 in
+ update_mword_dec w (top - n) b.
+
+(*Parameter update_mword : forall {a}, bool -> mword a -> Z -> bitU -> mword a.*)
+Definition update_mword {a} (is_inc : bool) (w : mword a) n b :=
+ if is_inc then update_mword_inc w n b else update_mword_dec w n b.
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+Definition int_of_mword {a} `{ArithFact (a >= 0)} (sign : bool) (w : mword a) :=
+ if sign then wordToZ (get_word w) else Z.of_N (wordToN (get_word w)).
+
+
+(*val mword_of_int : forall a. Size a => Z -> Z -> mword a
+Definition mword_of_int len n :=
+ let w := wordFromInteger n in
+ if (length_mword w = len) then w else failwith "unexpected word length"
+*)
+Program Definition mword_of_int {len} `{H:ArithFact (len >= 0)} n : mword len :=
+match len with
+| Zneg _ => _
+| Z0 => ZToWord 0 n
+| Zpos p => ZToWord (Pos.to_nat p) n
+end.
+Next Obligation.
+destruct H.
+auto.
+Defined.
+(*
+(* Translating between a type level number (itself n) and an integer *)
+
+Definition size_itself_int x := Z.of_nat (size_itself x)
+
+(* NB: the corresponding sail type is forall n. atom(n) -> itself(n),
+ the actual integer is ignored. *)
+
+val make_the_value : forall n. Z -> itself n
+Definition inline make_the_value x := the_value
+*)
+
+Fixpoint wordFromBitlist_rev l : word (length l) :=
+match l with
+| [] => WO
+| b::t => WS b (wordFromBitlist_rev t)
+end.
+Definition wordFromBitlist l : word (length l) :=
+ nat_cast _ (List.rev_length l) (wordFromBitlist_rev (List.rev l)).
+
+Local Open Scope nat.
+
+Fixpoint nat_diff {T : nat -> Type} n m {struct n} :
+forall
+ (lt : forall p, T n -> T (n + p))
+ (eq : T m -> T m)
+ (gt : forall p, T (m + p) -> T m), T n -> T m :=
+(match n, m return (forall p, T n -> T (n + p)) -> (T m -> T m) -> (forall p, T (m + p) -> T m) -> T n -> T m with
+| O, O => fun lt eq gt => eq
+| S n', O => fun lt eq gt => gt _
+| O, S m' => fun lt eq gt => lt _
+| S n', S m' => @nat_diff (fun x => T (S x)) n' m'
+end).
+
+Definition fit_bbv_word {n m} : word n -> word m :=
+nat_diff n m
+ (fun p w => nat_cast _ (Nat.add_comm _ _) (extz w p))
+ (fun w => w)
+ (fun p w => split2 _ _ (nat_cast _ (Nat.add_comm _ _) w)).
+
+Local Close Scope nat.
+
+(*** Bitvectors *)
+
+Class Bitvector (a:Type) : Type := {
+ bits_of : a -> list bitU;
+ of_bits : list bitU -> option a;
+ of_bools : list bool -> a;
+ (* The first parameter specifies the desired length of the bitvector *)
+ of_int : Z -> Z -> a;
+ length : a -> Z;
+ unsigned : a -> option Z;
+ signed : a -> option Z;
+ arith_op_bv : (Z -> Z -> Z) -> bool -> a -> a -> a
+}.
+
+Instance bitlist_Bitvector {a : Type} `{BitU a} : (Bitvector (list a)) := {
+ bits_of v := List.map to_bitU v;
+ of_bits v := Some (List.map of_bitU v);
+ of_bools v := List.map of_bitU (List.map bitU_of_bool v);
+ of_int len n := List.map of_bitU (bits_of_int len n);
+ length := length_list;
+ unsigned v := unsigned_of_bits (List.map to_bitU v);
+ signed v := signed_of_bits (List.map to_bitU v);
+ arith_op_bv op sign l r := List.map of_bitU (arith_op_bits op sign (List.map to_bitU l) (List.map to_bitU r))
+}.
+
+Class ReasonableSize (a : Z) : Prop := {
+ isPositive : a >= 0
+}.
+
+(* Omega doesn't know about In, but can handle disjunctions. *)
+Ltac unfold_In :=
+repeat match goal with
+| H:context [member_Z_list _ _ = true] |- _ => rewrite member_Z_list_In in H
+| H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H
+| H:context [In ?x []] |- _ => change (In x []) with False in H
+| |- context [member_Z_list _ _ = true] => rewrite member_Z_list_In
+| |- context [In ?x (?y :: ?t)] => change (In x (y :: t)) with (y = x \/ In x t)
+| |- context [In ?x []] => change (In x []) with False
+end.
+
+(* Definitions in the context that involve proof for other constraints can
+ break some of the constraint solving tactics, so prune definition bodies
+ down to integer types. *)
+Ltac not_Z_bool ty := match ty with Z => fail 1 | bool => fail 1 | _ => idtac end.
+Ltac clear_non_Z_bool_defns :=
+ repeat match goal with H := _ : ?X |- _ => not_Z_bool X; clearbody H end.
+Ltac clear_irrelevant_defns :=
+repeat match goal with X := _ |- _ =>
+ match goal with |- context[X] => idtac end ||
+ match goal with _ : context[X] |- _ => idtac end || clear X
+end.
+
+Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0).
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+Ltac unwrap_ArithFacts :=
+ repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H']; clear H end.
+Ltac unbool_comparisons :=
+ repeat match goal with
+ | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H
+ | H:context [Z.gtb _ _] |- _ => rewrite Z.gtb_ltb in H
+ | H:context [Z.leb _ _ = true] |- _ => rewrite Z.leb_le in H
+ | H:context [Z.ltb _ _ = true] |- _ => rewrite Z.ltb_lt in H
+ | H:context [Z.eqb _ _ = true] |- _ => rewrite Z.eqb_eq in H
+ | H:context [Z.leb _ _ = false] |- _ => rewrite Z.leb_gt in H
+ | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H
+ | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H
+ | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H
+ | H:context [orb _ _ = false] |- _ => rewrite Bool.orb_false_iff in H
+ | H:context [andb _ _ = true] |- _ => rewrite Bool.andb_true_iff in H
+ | H:context [andb _ _ = false] |- _ => rewrite Bool.andb_false_iff in H
+ | H:context [negb _ = true] |- _ => rewrite Bool.negb_true_iff in H
+ | H:context [negb _ = false] |- _ => rewrite Bool.negb_false_iff in H
+ | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H
+ | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H
+ | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H
+ | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H
+ | H:context [_ <> true] |- _ => rewrite Bool.not_true_iff_false in H
+ | H:context [_ <> false] |- _ => rewrite Bool.not_false_iff_true in H
+ end.
+Ltac unbool_comparisons_goal :=
+ repeat match goal with
+ | |- context [Z.geb _ _] => setoid_rewrite Z.geb_leb
+ | |- context [Z.gtb _ _] => setoid_rewrite Z.gtb_ltb
+ | |- context [Z.leb _ _ = true] => setoid_rewrite Z.leb_le
+ | |- context [Z.ltb _ _ = true] => setoid_rewrite Z.ltb_lt
+ | |- context [Z.eqb _ _ = true] => setoid_rewrite Z.eqb_eq
+ | |- context [Z.leb _ _ = false] => setoid_rewrite Z.leb_gt
+ | |- context [Z.ltb _ _ = false] => setoid_rewrite Z.ltb_ge
+ | |- context [Z.eqb _ _ = false] => setoid_rewrite Z.eqb_neq
+ | |- context [orb _ _ = true] => setoid_rewrite Bool.orb_true_iff
+ | |- context [orb _ _ = false] => setoid_rewrite Bool.orb_false_iff
+ | |- context [andb _ _ = true] => setoid_rewrite Bool.andb_true_iff
+ | |- context [andb _ _ = false] => setoid_rewrite Bool.andb_false_iff
+ | |- context [negb _ = true] => setoid_rewrite Bool.negb_true_iff
+ | |- context [negb _ = false] => setoid_rewrite Bool.negb_false_iff
+ | |- context [generic_eq _ _ = true] => apply generic_eq_true
+ | |- context [generic_eq _ _ = false] => apply generic_eq_false
+ | |- context [generic_neq _ _ = true] => apply generic_neq_true
+ | |- context [generic_neq _ _ = false] => apply generic_neq_false
+ | |- context [_ <> true] => setoid_rewrite Bool.not_true_iff_false
+ | |- context [_ <> false] => setoid_rewrite Bool.not_false_iff_true
+ end.
+
+(* Split up dependent pairs to get at proofs of properties *)
+Ltac extract_properties :=
+ (* Properties of local definitions *)
+ repeat match goal with H := context[projT1 ?X] |- _ =>
+ let x := fresh "x" in
+ let Hx := fresh "Hx" in
+ destruct X as [x Hx] in *;
+ change (projT1 (existT _ x Hx)) with x in * end;
+ (* Properties in the goal *)
+ repeat match goal with |- context [projT1 ?X] =>
+ let x := fresh "x" in
+ let Hx := fresh "Hx" in
+ destruct X as [x Hx] in *;
+ change (projT1 (existT _ x Hx)) with x in * end;
+ (* Properties with proofs embedded by build_ex; uses revert/generalize
+ rather than destruct because it seemed to be more efficient, but
+ some experimentation would be needed to be sure.
+ repeat (
+ match goal with H:context [@build_ex ?T ?n ?P ?prf] |- _ =>
+ let x := fresh "x" in
+ let zz := constr:(@build_ex T n P prf) in
+ revert dependent H(*; generalize zz; intros*)
+ end;
+ match goal with |- context [@build_ex ?T ?n ?P ?prf] =>
+ let x := fresh "x" in
+ let zz := constr:(@build_ex T n P prf) in
+ generalize zz as x
+ end;
+ intros).*)
+ repeat match goal with _:context [projT1 ?X] |- _ =>
+ let x := fresh "x" in
+ let Hx := fresh "Hx" in
+ destruct X as [x Hx] in *;
+ change (projT1 (existT _ x Hx)) with x in * end.
+(* TODO: hyps, too? *)
+Ltac reduce_list_lengths :=
+ repeat match goal with |- context [length_list ?X] =>
+ let r := (eval cbn in (length_list X)) in
+ change (length_list X) with r
+ end.
+(* TODO: can we restrict this to concrete terms? *)
+Ltac reduce_pow :=
+ repeat match goal with H:context [Z.pow ?X ?Y] |- _ =>
+ let r := (eval cbn in (Z.pow X Y)) in
+ change (Z.pow X Y) with r in H
+ end;
+ repeat match goal with |- context [Z.pow ?X ?Y] =>
+ let r := (eval cbn in (Z.pow X Y)) in
+ change (Z.pow X Y) with r
+ end.
+Ltac dump_context :=
+ repeat match goal with
+ | H:=?X |- _ => idtac H ":=" X; fail
+ | H:?X |- _ => idtac H ":" X; fail end;
+ match goal with |- ?X => idtac "Goal:" X end.
+Ltac split_cases :=
+ repeat match goal with
+ |- context [match ?X with _ => _ end] => destruct X
+ end.
+Lemma True_left {P:Prop} : (True /\ P) <-> P.
+tauto.
+Qed.
+Lemma True_right {P:Prop} : (P /\ True) <-> P.
+tauto.
+Qed.
+
+(* Turn exists into metavariables like eexists, except put in dummy values when
+ the variable is unused. This is used so that we can use eauto with a low
+ search bound that doesn't include the exists. (Not terribly happy with
+ how this works...) *)
+Ltac drop_Z_exists :=
+repeat
+ match goal with |- @ex Z ?p =>
+ let a := eval hnf in (p 0) in
+ let b := eval hnf in (p 1) in
+ match a with b => exists 0 | _ => eexists end
+ end.
+(*
+ match goal with |- @ex Z (fun x => @?p x) =>
+ let xx := fresh "x" in
+ evar (xx : Z);
+ let a := eval hnf in (p xx) in
+ match a with context [xx] => eexists | _ => exists 0 end;
+ instantiate (xx := 0);
+ clear xx
+ end.
+*)
+(* For boolean solving we just use plain metavariables *)
+Ltac drop_bool_exists :=
+repeat match goal with |- @ex bool _ => eexists end.
+
+(* The linear solver doesn't like existentials. *)
+Ltac destruct_exists :=
+ repeat match goal with H:@ex Z _ |- _ => destruct H end;
+ repeat match goal with H:@ex bool _ |- _ => destruct H end.
+
+(* The ASL to Sail translator sometimes puts constraints of the form
+ p | not(q) into function signatures, then the body case splits on q.
+ The filter_disjunctions tactic simplifies hypotheses by obtaining p. *)
+
+Lemma truefalse : true = false <-> False.
+intuition.
+Qed.
+Lemma falsetrue : false = true <-> False.
+intuition.
+Qed.
+Lemma or_False_l P : False \/ P <-> P.
+intuition.
+Qed.
+Lemma or_False_r P : P \/ False <-> P.
+intuition.
+Qed.
+
+Ltac filter_disjunctions :=
+ repeat match goal with
+ | H1:?P \/ ?t1 = ?t2, H2: ?t3 = ?t4 |- _ =>
+ (* I used to use non-linear matching above, but Coq is happy to match up
+ to conversion, including more unfolding than we normally do. *)
+ constr_eq t1 t3; constr_eq t2 t4; clear H1
+ | H1:context [?P \/ ?t = true], H2: ?t = false |- _ => is_var t; rewrite H2 in H1
+ | H1:context [?P \/ ?t = false], H2: ?t = true |- _ => is_var t; rewrite H2 in H1
+ | H1:context [?t = true \/ ?P], H2: ?t = false |- _ => is_var t; rewrite H2 in H1
+ | H1:context [?t = false \/ ?P], H2: ?t = true |- _ => is_var t; rewrite H2 in H1
+ end;
+ rewrite ?truefalse, ?falsetrue, ?or_False_l, ?or_False_r in *;
+ (* We may have uncovered more conjunctions *)
+ repeat match goal with H:and _ _ |- _ => destruct H end.
+
+(* Turn x := if _ then ... into x = ... \/ x = ... *)
+
+Ltac Z_if_to_or :=
+ repeat match goal with x := ?t : Z |- _ =>
+ let rec build_goal t :=
+ match t with
+ | if _ then ?y else ?z =>
+ let Hy := build_goal y in
+ let Hz := build_goal z in
+ constr:(Hy \/ Hz)
+ | ?y => constr:(x = y)
+ end
+ in
+ let rec split_hyp t :=
+ match t with
+ | if ?b then ?y else ?z =>
+ destruct b in x; [split_hyp y| split_hyp z]
+ | _ => idtac
+ end
+ in
+ let g := build_goal t in
+ assert g by (clear -x; split_hyp t; auto);
+ clearbody x
+ end.
+
+(* Once we've done everything else, get rid of irrelevant bool and Z bindings
+ to help the brute force solver *)
+Ltac clear_irrelevant_bindings :=
+ repeat
+ match goal with
+ | b : bool |- _ =>
+ lazymatch goal with
+ | _ : context [b] |- _ => fail
+ | |- context [b] => fail
+ | _ => clear b
+ end
+ | x : Z |- _ =>
+ lazymatch goal with
+ | _ : context [x] |- _ => fail
+ | |- context [x] => fail
+ | _ => clear x
+ end
+ | H:?x |- _ =>
+ let s := type of x in
+ lazymatch s with
+ | Prop =>
+ match x with
+ | context [?v] => is_var v; fail 1
+ | _ => clear H
+ end
+ | _ => fail
+ end
+ end.
+
+(* Currently, the ASL to Sail translation produces some constraints of the form
+ P \/ x = true, P \/ x = false, which are simplified by the tactic below. In
+ future the translation is likely to be cleverer, and this won't be
+ necessary. *)
+(* TODO: remove duplication with filter_disjunctions *)
+Lemma remove_unnecessary_casesplit {P:Prop} {x} :
+ P \/ x = true -> P \/ x = false -> P.
+ intuition congruence.
+Qed.
+Lemma remove_eq_false_true {P:Prop} {x} :
+ x = true -> P \/ x = false -> P.
+intros H1 [H|H]; congruence.
+Qed.
+Lemma remove_eq_true_false {P:Prop} {x} :
+ x = false -> P \/ x = true -> P.
+intros H1 [H|H]; congruence.
+Qed.
+Ltac remove_unnecessary_casesplit :=
+repeat match goal with
+| H1 : ?P \/ ?v = true, H2 : ?v = true |- _ => clear H1
+| H1 : ?P \/ ?v = true, H2 : ?v = false |- _ => apply (remove_eq_true_false H2) in H1
+| H1 : ?P \/ ?v = false, H2 : ?v = false |- _ => clear H1
+| H1 : ?P \/ ?v = false, H2 : ?v = true |- _ => apply (remove_eq_false_true H2) in H1
+| H1 : ?P \/ ?v1 = true, H2 : ?P \/ ?v2 = false |- _ =>
+ constr_eq v1 v2;
+ is_var v1;
+ apply (remove_unnecessary_casesplit H1) in H2;
+ clear H1
+ (* There are worse cases where the hypotheses are different, so we actually
+ do the casesplit *)
+| H1 : _ \/ ?v = true, H2 : _ \/ ?v = false |- _ =>
+ is_var v;
+ destruct v;
+ [ clear H1; destruct H2; [ | congruence ]
+ | clear H2; destruct H1; [ | congruence ]
+ ]
+end;
+(* We may have uncovered more conjunctions *)
+repeat match goal with H:and _ _ |- _ => destruct H end.
+
+Ltac generalize_embedded_proofs :=
+ repeat match goal with H:context [?X] |- _ =>
+ match type of X with ArithFact _ =>
+ generalize dependent X
+ end
+ end;
+ intros.
+
+Lemma iff_equal_l {T:Type} {P:Prop} {x:T} : (x = x <-> P) -> P.
+tauto.
+Qed.
+Lemma iff_equal_r {T:Type} {P:Prop} {x:T} : (P <-> x = x) -> P.
+tauto.
+Qed.
+
+Lemma iff_known_l {P Q : Prop} : P -> P <-> Q -> Q.
+tauto.
+Qed.
+Lemma iff_known_r {P Q : Prop} : P -> Q <-> P -> Q.
+tauto.
+Qed.
+
+Ltac clean_up_props :=
+ repeat match goal with
+ (* I did try phrasing these as rewrites, but Coq was oddly reluctant to use them *)
+ | H:?x = ?x <-> _ |- _ => apply iff_equal_l in H
+ | H:_ <-> ?x = ?x |- _ => apply iff_equal_r in H
+ | H:context[true = false] |- _ => rewrite truefalse in H
+ | H:context[false = true] |- _ => rewrite falsetrue in H
+ | H1:?P <-> False, H2:context[?Q] |- _ => constr_eq P Q; rewrite -> H1 in H2
+ | H1:False <-> ?P, H2:context[?Q] |- _ => constr_eq P Q; rewrite <- H1 in H2
+ | H1:?P, H2:?Q <-> ?R |- _ => constr_eq P Q; apply (iff_known_l H1) in H2
+ | H1:?P, H2:?R <-> ?Q |- _ => constr_eq P Q; apply (iff_known_r H1) in H2
+ | H:context[_ \/ False] |- _ => rewrite or_False_r in H
+ | H:context[False \/ _] |- _ => rewrite or_False_l in H
+ (* omega doesn't cope well with extra "True"s in the goal.
+ Check that they actually appear because setoid_rewrite can fill in evars. *)
+ | |- context[True /\ _] => setoid_rewrite True_left
+ | |- context[_ /\ True] => setoid_rewrite True_right
+ end;
+ remove_unnecessary_casesplit.
+
+Ltac prepare_for_solver :=
+(*dump_context;*)
+ generalize_embedded_proofs;
+ clear_irrelevant_defns;
+ clear_non_Z_bool_defns;
+ autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *)
+ split_cases;
+ extract_properties;
+ repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end;
+ unwrap_ArithFacts;
+ destruct_exists;
+ unbool_comparisons;
+ unbool_comparisons_goal;
+ repeat match goal with H:and _ _ |- _ => destruct H end;
+ remove_unnecessary_casesplit;
+ unfold_In; (* after unbool_comparisons to deal with && and || *)
+ reduce_list_lengths;
+ reduce_pow;
+ filter_disjunctions;
+ Z_if_to_or;
+ clear_irrelevant_bindings;
+ subst;
+ clean_up_props.
+
+Lemma trivial_range {x : Z} : ArithFact (x <= x /\ x <= x).
+constructor.
+auto with zarith.
+Qed.
+
+Lemma ArithFact_self_proof {P} : forall x : {y : Z & ArithFact (P y)}, ArithFact (P (projT1 x)).
+intros [x H].
+exact H.
+Qed.
+
+Ltac fill_in_evar_eq :=
+ match goal with |- ArithFact (?x = ?y) =>
+ (is_evar x || is_evar y);
+ (* compute to allow projections to remove proofs that might not be allowed in the evar *)
+(* Disabled because cbn may reduce definitions, even after clearbody
+ let x := eval cbn in x in
+ let y := eval cbn in y in*)
+ idtac "Warning: unknown equality constraint"; constructor; exact (eq_refl _ : x = y) end.
+
+Ltac bruteforce_bool_exists :=
+match goal with
+| |- exists _ : bool,_ => solve [ exists true; bruteforce_bool_exists
+ | exists false; bruteforce_bool_exists ]
+| _ => tauto
+end.
+
+Lemma or_iff_cong : forall A B C D, A <-> B -> C <-> D -> A \/ C <-> B \/ D.
+intros.
+tauto.
+Qed.
+
+Lemma and_iff_cong : forall A B C D, A <-> B -> C <-> D -> A /\ C <-> B /\ D.
+intros.
+tauto.
+Qed.
+
+Ltac solve_euclid :=
+repeat match goal with
+| |- context [ZEuclid.modulo ?x ?y] =>
+ specialize (ZEuclid.div_mod x y);
+ specialize (ZEuclid.mod_always_pos x y);
+ generalize (ZEuclid.modulo x y);
+ generalize (ZEuclid.div x y);
+ intros
+| |- context [ZEuclid.div ?x ?y] =>
+ specialize (ZEuclid.div_mod x y);
+ specialize (ZEuclid.mod_always_pos x y);
+ generalize (ZEuclid.modulo x y);
+ generalize (ZEuclid.div x y);
+ intros
+end;
+nia.
+
+(* A more ambitious brute force existential solver. *)
+
+Ltac guess_ex_solver :=
+ match goal with
+ | |- @ex bool ?t =>
+ match t with
+ | context [@eq bool ?b _] =>
+ solve [ exists b; guess_ex_solver
+ | exists (negb b); rewrite ?Bool.negb_true_iff, ?Bool.negb_false_iff;
+ guess_ex_solver ]
+ end
+(* | b : bool |- @ex bool _ => exists b; guess_ex_solver
+ | b : bool |- @ex bool _ =>
+ exists (negb b); rewrite ?Bool.negb_true_iff, ?Bool.negb_false_iff;
+ guess_ex_solver*)
+ | |- @ex bool _ => exists true; guess_ex_solver
+ | |- @ex bool _ => exists false; guess_ex_solver
+ | x : Z |- @ex Z _ => exists x; guess_ex_solver
+ | _ => solve [tauto | eauto 3 with zarith sail | omega | intuition]
+ end.
+
+(* A straightforward solver for simple problems like
+
+ exists ..., _ = true \/ _ = false /\ _ = true <-> _ = true \/ _ = true
+*)
+
+Ltac form_iff_true :=
+repeat match goal with
+| |- ?l <-> _ = true =>
+ let rec aux t :=
+ match t with
+ | _ = true \/ _ = true => rewrite <- Bool.orb_true_iff
+ | _ = true /\ _ = true => rewrite <- Bool.andb_true_iff
+ | _ = false => rewrite <- Bool.negb_true_iff
+ | ?l \/ ?r => aux l || aux r
+ | ?l /\ ?r => aux l || aux r
+ end
+ in aux l
+ end.
+Ltac simple_split_iff :=
+ repeat
+ match goal with
+ | |- _ /\ _ <-> _ /\ _ => apply and_iff_cong
+ | |- _ \/ _ <-> _ \/ _ => apply or_iff_cong
+ end.
+Ltac simple_ex_iff :=
+ match goal with
+ | |- @ex _ _ => eexists; simple_ex_iff
+ | |- _ <-> _ =>
+ simple_split_iff;
+ form_iff_true;
+ solve [apply iff_refl | eassumption]
+ end.
+
+(* Another attempt at similar goals, this time allowing for conjuncts to move
+ around, and filling in integer existentials and redundant boolean ones.
+ TODO: generalise / combine with simple_ex_iff. *)
+
+Ltac ex_iff_construct_bool_witness :=
+let rec search x y :=
+ lazymatch y with
+ | x => constr:(true)
+ | ?y1 /\ ?y2 =>
+ let b1 := search x y1 in
+ let b2 := search x y2 in
+ constr:(orb b1 b2)
+ | _ => constr:(false)
+ end
+in
+let rec make_clause x :=
+ lazymatch x with
+ | ?l = true => l
+ | ?l = false => constr:(negb l)
+ | @eq Z ?l ?n => constr:(Z.eqb l n)
+ | ?p \/ ?q =>
+ let p' := make_clause p in
+ let q' := make_clause q in
+ constr:(orb p' q')
+ | _ => fail
+ end in
+let add_clause x xs :=
+ let l := make_clause x in
+ match xs with
+ | true => l
+ | _ => constr:(andb l xs)
+ end
+in
+let rec construct_ex l r x :=
+ lazymatch l with
+ | ?l1 /\ ?l2 =>
+ let y := construct_ex l1 r x in
+ construct_ex l2 r y
+ | _ =>
+ let present := search l r in
+ lazymatch eval compute in present with true => x | _ => add_clause l x end
+ end
+in
+let witness := match goal with
+| |- ?l <-> ?r => construct_ex l r constr:(true)
+end in
+instantiate (1 := witness).
+
+Ltac ex_iff_fill_in_ints :=
+ let rec search l r y :=
+ match y with
+ | l = r => idtac
+ | ?v = r => is_evar v; unify v l
+ | ?y1 /\ ?y2 => first [search l r y1 | search l r y2]
+ | _ => fail
+ end
+ in
+ match goal with
+ | |- ?l <-> ?r =>
+ let rec traverse l :=
+ lazymatch l with
+ | ?l1 /\ ?l2 =>
+ traverse l1; traverse l2
+ | @eq Z ?x ?y => search x y r
+ | _ => idtac
+ end
+ in traverse l
+ end.
+
+Ltac ex_iff_fill_in_bools :=
+ let rec traverse t :=
+ lazymatch t with
+ | ?v = ?t => try (is_evar v; unify v t)
+ | ?p /\ ?q => traverse p; traverse q
+ | _ => idtac
+ end
+ in match goal with
+ | |- _ <-> ?r => traverse r
+ end.
+
+Ltac conjuncts_iff_solve :=
+ ex_iff_fill_in_ints;
+ ex_iff_construct_bool_witness;
+ ex_iff_fill_in_bools;
+ unbool_comparisons_goal;
+ clear;
+ intuition.
+
+Ltac ex_iff_solve :=
+ match goal with
+ | |- @ex _ _ => eexists; ex_iff_solve
+ (* Range constraints are attached to the right *)
+ | |- _ /\ _ => split; [ex_iff_solve | omega]
+ | |- _ <-> _ => conjuncts_iff_solve
+ end.
+
+
+Lemma iff_false_left {P Q R : Prop} : (false = true) <-> Q -> (false = true) /\ P <-> Q /\ R.
+intuition.
+Qed.
+
+(* Very simple proofs for trivial arithmetic. Preferable to running omega/lia because
+ they can get bogged down if they see large definitions; should also guarantee small
+ proof terms. *)
+Lemma Z_compare_lt_eq : Lt = Eq -> False. congruence. Qed.
+Lemma Z_compare_lt_gt : Lt = Gt -> False. congruence. Qed.
+Lemma Z_compare_eq_lt : Eq = Lt -> False. congruence. Qed.
+Lemma Z_compare_eq_gt : Eq = Gt -> False. congruence. Qed.
+Lemma Z_compare_gt_lt : Gt = Lt -> False. congruence. Qed.
+Lemma Z_compare_gt_eq : Gt = Eq -> False. congruence. Qed.
+Ltac z_comparisons :=
+ (* Don't try terms with variables - reduction may be expensive *)
+ match goal with |- context[?x] => is_var x; fail 1 | |- _ => idtac end;
+ solve [
+ exact eq_refl
+ | exact Z_compare_lt_eq
+ | exact Z_compare_lt_gt
+ | exact Z_compare_eq_lt
+ | exact Z_compare_eq_gt
+ | exact Z_compare_gt_lt
+ | exact Z_compare_gt_eq
+ ].
+
+(* Try to get the linear arithmetic solver to do booleans. *)
+
+Lemma b2z_true x : x = true <-> Z.b2z x = 1.
+destruct x; compute; split; congruence.
+Qed.
+
+Lemma b2z_false x : x = false <-> Z.b2z x = 0.
+destruct x; compute; split; congruence.
+Qed.
+
+Lemma b2z_tf x : 0 <= Z.b2z x <= 1.
+destruct x; simpl; omega.
+Qed.
+
+Ltac solve_bool_with_Z :=
+ subst;
+ rewrite ?truefalse, ?falsetrue, ?or_False_l, ?or_False_r in *;
+ (* I did try phrasing these as rewrites, but Coq was oddly reluctant to use them *)
+ repeat match goal with
+ | H:?x = ?x <-> _ |- _ => apply iff_equal_l in H
+ | H:_ <-> ?x = ?x |- _ => apply iff_equal_r in H
+ end;
+ repeat match goal with
+ | H:context [?v = true] |- _ => is_var v; rewrite (b2z_true v) in *
+ | |- context [?v = true] => is_var v; rewrite (b2z_true v) in *
+ | H:context [?v = false] |- _ => is_var v; rewrite (b2z_false v) in *
+ | |- context [?v = false] => is_var v; rewrite (b2z_false v) in *
+ end;
+ repeat match goal with
+ | _:context [Z.b2z ?v] |- _ => generalize (b2z_tf v); generalize dependent (Z.b2z v)
+ | |- context [Z.b2z ?v] => generalize (b2z_tf v); generalize dependent (Z.b2z v)
+ end;
+ intros;
+ lia.
+
+
+(* Redefine this to add extra solver tactics *)
+Ltac sail_extra_tactic := fail.
+
+Ltac main_solver :=
+ solve
+ [ apply ArithFact_mword; assumption
+ | z_comparisons
+ | omega with Z
+ (* Try sail hints before dropping the existential *)
+ | subst; eauto 3 with zarith sail
+ (* The datatypes hints give us some list handling, esp In *)
+ | subst; drop_Z_exists;
+ repeat match goal with |- and _ _ => split end;
+ eauto 3 with datatypes zarith sail
+ | subst; match goal with |- context [ZEuclid.div] => solve_euclid
+ | |- context [ZEuclid.modulo] => solve_euclid
+ end
+ | match goal with |- context [Z.mul] => nia end
+ (* If we have a disjunction from a set constraint on a variable we can often
+ solve a goal by trying them (admittedly this is quite heavy handed...) *)
+ | subst; drop_Z_exists;
+ let aux x :=
+ is_var x;
+ intuition (subst;auto with datatypes)
+ in
+ match goal with
+ | _:(@eq Z _ ?x) \/ (@eq Z _ ?x) \/ _ |- context[?x] => aux x
+ | _:(@eq Z ?x _) \/ (@eq Z ?x _) \/ _ |- context[?x] => aux x
+ | _:(@eq Z _ ?x) \/ (@eq Z _ ?x) \/ _, _:@eq Z ?y (ZEuclid.div ?x _) |- context[?y] => is_var x; aux y
+ | _:(@eq Z ?x _) \/ (@eq Z ?x _) \/ _, _:@eq Z ?y (ZEuclid.div ?x _) |- context[?y] => is_var x; aux y
+ end
+ (* Booleans - and_boolMP *)
+ | solve_bool_with_Z
+ | simple_ex_iff
+ | ex_iff_solve
+ | drop_bool_exists; solve [eauto using iff_refl, or_iff_cong, and_iff_cong | intuition]
+ | match goal with |- (forall l r:bool, _ -> _ -> exists _ : bool, _) =>
+ let r := fresh "r" in
+ let H1 := fresh "H" in
+ let H2 := fresh "H" in
+ intros [|] r H1 H2;
+ let t2 := type of H2 in
+ match t2 with
+ | ?b = ?b -> _ =>
+ destruct (H2 eq_refl);
+ repeat match goal with H:@ex _ _ |- _ => destruct H end;
+ simple_ex_iff
+ | ?b = _ -> _ =>
+ repeat match goal with H:@ex _ _ |- _ => destruct H end;
+ clear H2;
+ repeat match goal with
+ | |- @ex bool _ => exists b
+ | |- @ex Z _ => exists 0
+ end;
+ intuition
+ end
+ end
+ | match goal with |- (forall l r:bool, _ -> _ -> @ex _ _) =>
+ let H1 := fresh "H" in
+ let H2 := fresh "H" in
+ intros [|] [|] H1 H2;
+ repeat match goal with H:?X = ?X -> _ |- _ => specialize (H eq_refl) end;
+ repeat match goal with H:@ex _ _ |- _ => destruct H end;
+ guess_ex_solver
+ end
+ | match goal with |- @ex _ _ => guess_ex_solver end
+(* While firstorder was quite effective at dealing with existentially quantified
+ goals from boolean expressions, it attempts lazy normalization of terms,
+ which blows up on integer comparisons with large constants.
+ | match goal with |- context [@eq bool _ _] =>
+ (* Don't use auto for the fallback to keep runtime down *)
+ firstorder fail
+ end*)
+ | sail_extra_tactic
+ | idtac "Unable to solve constraint"; dump_context; fail
+ ].
+
+(* Omega can get upset by local definitions that are projections from value/proof pairs.
+ Complex goals can use prepare_for_solver to extract facts; this tactic can be used
+ for simpler proofs without using prepare_for_solver. *)
+Ltac simple_omega :=
+ repeat match goal with
+ H := projT1 _ |- _ => clearbody H
+ end; omega.
+
+Ltac solve_unknown :=
+ match goal with |- (ArithFact (?x ?y)) =>
+ is_evar x;
+ idtac "Warning: unknown constraint";
+ let t := type of y in
+ unify x (fun (_ : t) => True);
+ exact (Build_ArithFact _ I)
+ end.
+
+Ltac solve_arithfact :=
+(* Attempt a simple proof first to avoid lengthy preparation steps (especially
+ as the large proof terms can upset subsequent proofs). *)
+intros; (* To solve implications for derive_m *)
+try solve_unknown;
+match goal with |- ArithFact (?x <= ?x <= ?x) => try (exact trivial_range) | _ => idtac end;
+try fill_in_evar_eq;
+try match goal with |- context [projT1 ?X] => apply (ArithFact_self_proof X) end;
+(* Trying reflexivity will fill in more complex metavariable examples than
+ fill_in_evar_eq above, e.g., 8 * n = 8 * ?Goal3 *)
+try (constructor; reflexivity);
+try (constructor; repeat match goal with |- and _ _ => split end; z_comparisons);
+try (constructor; simple_omega);
+prepare_for_solver;
+(*dump_context;*)
+constructor;
+repeat match goal with |- and _ _ => split end;
+main_solver.
+
+(* Add an indirection so that you can redefine run_solver to fail to get
+ slow running constraints into proof mode. *)
+Ltac run_solver := solve_arithfact.
+Hint Extern 0 (ArithFact _) => run_solver : typeclass_instances.
+
+Hint Unfold length_mword : sail.
+
+Lemma unit_comparison_lemma : true = true <-> True.
+intuition.
+Qed.
+Hint Resolve unit_comparison_lemma : sail.
+
+Definition neq_atom (x : Z) (y : Z) : bool := negb (Z.eqb x y).
+Hint Unfold neq_atom : sail.
+
+Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a.
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+
+Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances.
+
+Definition to_range (x : Z) : {y : Z & ArithFact (x <= y <= x)} := build_ex x.
+
+
+
+Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := {
+ bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v));
+ of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v));
+ of_bools v := to_word isPositive (fit_bbv_word (wordFromBitlist v));
+ of_int len z := mword_of_int z; (* cheat a little *)
+ length v := a;
+ unsigned v := Some (Z.of_N (wordToN (get_word v)));
+ signed v := Some (wordToZ (get_word v));
+ arith_op_bv op sign l r := mword_of_int (op (int_of_mword sign l) (int_of_mword sign r))
+}.
+
+Section Bitvector_defs.
+Context {a b} `{Bitvector a} `{Bitvector b}.
+
+Definition opt_def {a} (def:a) (v:option a) :=
+match v with
+| Some x => x
+| None => def
+end.
+
+(* The Lem version is partial, but lets go with BU here to avoid constraints for now *)
+Definition access_bv_inc (v : a) n := opt_def BU (access_list_opt_inc (bits_of v) n).
+Definition access_bv_dec (v : a) n := opt_def BU (access_list_opt_dec (bits_of v) n).
+
+Definition update_bv_inc (v : a) n b := update_list true (bits_of v) n b.
+Definition update_bv_dec (v : a) n b := update_list false (bits_of v) n b.
+
+Definition subrange_bv_inc (v : a) i j := subrange_list true (bits_of v) i j.
+Definition subrange_bv_dec (v : a) i j := subrange_list true (bits_of v) i j.
+
+Definition update_subrange_bv_inc (v : a) i j (v' : b) := update_subrange_list true (bits_of v) i j (bits_of v').
+Definition update_subrange_bv_dec (v : a) i j (v' : b) := update_subrange_list false (bits_of v) i j (bits_of v').
+
+(*val extz_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition extz_bv n (v : a) : option b := of_bits (extz_bits n (bits_of v)).
+
+(*val exts_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition exts_bv n (v : a) : option b := of_bits (exts_bits n (bits_of v)).
+
+(*val string_of_bv : forall a. Bitvector a => a -> string *)
+Definition string_of_bv v := show_bitlist (bits_of v).
+
+End Bitvector_defs.
+
+(*** Bytes and addresses *)
+
+Definition memory_byte := list bitU.
+
+(*val byte_chunks : forall a. list a -> option (list (list a))*)
+Fixpoint byte_chunks {a} (bs : list a) := match bs with
+ | [] => Some []
+ | a::b::c::d::e::f::g::h::rest =>
+ match byte_chunks rest with
+ | None => None
+ | Some rest => Some ([a;b;c;d;e;f;g;h] :: rest)
+ end
+ | _ => None
+end.
+(*declare {isabelle} termination_argument byte_chunks = automatic*)
+
+Section BytesBits.
+Context {a} `{Bitvector a}.
+
+(*val bytes_of_bits : forall a. Bitvector a => a -> option (list memory_byte)*)
+Definition bytes_of_bits (bs : a) := byte_chunks (bits_of bs).
+
+(*val bits_of_bytes : forall a. Bitvector a => list memory_byte -> a*)
+Definition bits_of_bytes (bs : list memory_byte) : list bitU := List.concat (List.map bits_of bs).
+
+Definition mem_bytes_of_bits (bs : a) := option_map (@rev (list bitU)) (bytes_of_bits bs).
+Definition bits_of_mem_bytes (bs : list memory_byte) := bits_of_bytes (List.rev bs).
+
+End BytesBits.
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+Definition bitv_of_byte_lifteds v :=
+ foldl (fun x (Byte_lifted y) => x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+Definition bitv_of_bytes v :=
+ foldl (fun x (Byte y) => x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+Definition byte_lifteds_of_bitv bits :=
+ let bits := List.map bit_lifted_of_bitU bits in
+ byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+Definition bytes_of_bitv bits :=
+ let bits := List.map bit_of_bitU bits in
+ bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitUs bits := List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitv v := bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+Definition address_lifted_of_bitv v :=
+ let byte_lifteds := byte_lifteds_of_bitv v in
+ let maybe_address_integer :=
+ match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+ | Some bs => Some (integer_of_byte_list bs)
+ | _ => None
+ end in
+ Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+Definition bitv_of_address_lifted (Address_lifted bs _) := bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+Definition address_of_bitv v :=
+ let bytes := bytes_of_bitv v in
+ address_of_byte_list bytes*)
+
+Fixpoint reverse_endianness_list (bits : list bitU) :=
+ match bits with
+ | _ :: _ :: _ :: _ :: _ :: _ :: _ :: _ :: t =>
+ reverse_endianness_list t ++ firstn 8 bits
+ | _ => bits
+ end.
+
+(*** Registers *)
+
+Definition register_field := string.
+Definition register_field_index : Type := string * (Z * Z). (* name, start and end *)
+
+Inductive register :=
+ | Register : string * (* name *)
+ Z * (* length *)
+ Z * (* start index *)
+ bool * (* is increasing *)
+ list register_field_index
+ -> register
+ | UndefinedRegister : Z -> register (* length *)
+ | RegisterPair : register * register -> register.
+
+Record register_ref regstate regval a :=
+ { name : string;
+ (*is_inc : bool;*)
+ read_from : regstate -> a;
+ write_to : a -> regstate -> regstate;
+ of_regval : regval -> option a;
+ regval_of : a -> regval }.
+Notation "{[ r 'with' 'name' := e ]}" := ({| name := e; read_from := read_from r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'read_from' := e ]}" := ({| read_from := e; name := name r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'write_to' := e ]}" := ({| write_to := e; name := name r; read_from := read_from r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'of_regval' := e ]}" := ({| of_regval := e; name := name r; read_from := read_from r; write_to := write_to r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'regval_of' := e ]}" := ({| regval_of := e; name := name r; read_from := read_from r; write_to := write_to r; of_regval := of_regval r |}).
+Arguments name [_ _ _].
+Arguments read_from [_ _ _].
+Arguments write_to [_ _ _].
+Arguments of_regval [_ _ _].
+Arguments regval_of [_ _ _].
+
+(* Register accessors: pair of functions for reading and writing register values *)
+Definition register_accessors regstate regval : Type :=
+ ((string -> regstate -> option regval) *
+ (string -> regval -> regstate -> option regstate)).
+
+Record field_ref regtype a :=
+ { field_name : string;
+ field_start : Z;
+ field_is_inc : bool;
+ get_field : regtype -> a;
+ set_field : regtype -> a -> regtype }.
+Arguments field_name [_ _].
+Arguments field_start [_ _].
+Arguments field_is_inc [_ _].
+Arguments get_field [_ _].
+Arguments set_field [_ _].
+
+(*
+(*let name_of_reg := function
+ | Register name _ _ _ _ => name
+ | UndefinedRegister _ => failwith "name_of_reg UndefinedRegister"
+ | RegisterPair _ _ => failwith "name_of_reg RegisterPair"
+end
+
+Definition size_of_reg := function
+ | Register _ size _ _ _ => size
+ | UndefinedRegister size => size
+ | RegisterPair _ _ => failwith "size_of_reg RegisterPair"
+end
+
+Definition start_of_reg := function
+ | Register _ _ start _ _ => start
+ | UndefinedRegister _ => failwith "start_of_reg UndefinedRegister"
+ | RegisterPair _ _ => failwith "start_of_reg RegisterPair"
+end
+
+Definition is_inc_of_reg := function
+ | Register _ _ _ is_inc _ => is_inc
+ | UndefinedRegister _ => failwith "is_inc_of_reg UndefinedRegister"
+ | RegisterPair _ _ => failwith "in_inc_of_reg RegisterPair"
+end
+
+Definition dir_of_reg := function
+ | Register _ _ _ is_inc _ => dir_of_bool is_inc
+ | UndefinedRegister _ => failwith "dir_of_reg UndefinedRegister"
+ | RegisterPair _ _ => failwith "dir_of_reg RegisterPair"
+end
+
+Definition size_of_reg_nat reg := Z.to_nat (size_of_reg reg)
+Definition start_of_reg_nat reg := Z.to_nat (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> option (Z * Z)
+Fixpoint register_field_indices_aux register rfield :=
+ match register with
+ | Register _ _ _ _ rfields => List.lookup rfield rfields
+ | RegisterPair r1 r2 =>
+ let m_indices := register_field_indices_aux r1 rfield in
+ if isSome m_indices then m_indices else register_field_indices_aux r2 rfield
+ | UndefinedRegister _ => None
+ end
+
+val register_field_indices : register -> register_field -> Z * Z
+Definition register_field_indices register rfield :=
+ match register_field_indices_aux register rfield with
+ | Some indices => indices
+ | None => failwith "Invalid register/register-field combination"
+ end
+
+Definition register_field_indices_nat reg regfield=
+ let (i,j) := register_field_indices reg regfield in
+ (Z.to_nat i,Z.to_nat j)*)
+
+(*let rec external_reg_value reg_name v :=
+ let (internal_start, external_start, direction) :=
+ match reg_name with
+ | Reg _ start size dir =>
+ (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+ | Reg_slice _ reg_start dir (slice_start, _) =>
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_field _ reg_start dir _ (slice_start, _) =>
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_f_slice _ reg_start dir _ _ (slice_start, _) =>
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ end in
+ let bits := bit_lifteds_of_bitv v in
+ <| rv_bits := bits;
+ rv_dir := direction;
+ rv_start := external_start;
+ rv_start_internal := internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+Definition internal_reg_value v :=
+ List.map bitU_of_bit_lifted v.rv_bits
+ (*(Z.of_nat v.rv_start_internal)
+ (v.rv_dir = D_increasing)*)
+
+
+Definition external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) :=
+ match d with
+ (*This is the case the thread/concurrecny model expects, so no change needed*)
+ | D_increasing => (i,j)
+ | D_decreasing => let slice_i = start - i in
+ let slice_j = (i - j) + slice_i in
+ (slice_i,slice_j)
+ end *)
+
+(* TODO
+Definition external_reg_whole r :=
+ Reg (r.name) (Z.to_nat r.start) (Z.to_nat r.size) (dir_of_bool r.is_inc)
+
+Definition external_reg_slice r (i,j) :=
+ let start := Z.to_nat r.start in
+ let dir := dir_of_bool r.is_inc in
+ Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+Definition external_reg_field_whole reg rfield :=
+ let (m,n) := register_field_indices_nat reg rfield in
+ let start := start_of_reg_nat reg in
+ let dir := dir_of_reg reg in
+ Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+Definition external_reg_field_slice reg rfield (i,j) :=
+ let (m,n) := register_field_indices_nat reg rfield in
+ let start := start_of_reg_nat reg in
+ let dir := dir_of_reg reg in
+ Reg_f_slice (name_of_reg reg) start dir rfield
+ (external_slice dir start (m,n))
+ (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+Definition external_mem_value v :=
+ byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+Definition internal_mem_value bytes :=
+ List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+val foreach : forall a vars.
+ (list a) -> vars -> (a -> vars -> vars) -> vars*)
+Fixpoint foreach {a Vars} (l : list a) (vars : Vars) (body : a -> Vars -> Vars) : Vars :=
+match l with
+| [] => vars
+| (x :: xs) => foreach xs (body x vars) body
+end.
+
+(*declare {isabelle} termination_argument foreach = automatic
+
+val index_list : Z -> Z -> Z -> list Z*)
+Fixpoint index_list' from to step n :=
+ if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+ match n with
+ | O => []
+ | S n => from :: index_list' (from + step) to step n
+ end
+ else [].
+
+Definition index_list from to step :=
+ if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+ index_list' from to step (S (Z.abs_nat (from - to)))
+ else [].
+
+Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Vars) : Vars :=
+ if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+ match n with
+ | O => vars
+ | S n => let vars := body from vars in foreach_Z' (from + step) to step n vars body
+ end
+ else vars.
+
+Definition foreach_Z {Vars} from to step vars body :=
+ foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body.
+
+Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
+ if sumbool_of_bool (from + off <=? to) then
+ match n with
+ | O => vars
+ | S n => let vars := body (from + off) _ vars in foreach_Z_up' from to step (off + step) n vars body
+ end
+ else vars.
+
+Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
+ if sumbool_of_bool (to <=? from + off) then
+ match n with
+ | O => vars
+ | S n => let vars := body (from + off) _ vars in foreach_Z_down' from to step (off - step) n vars body
+ end
+ else vars.
+
+Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (0 < step)} :=
+ foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (0 < step)} :=
+ foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint while vars cond body :=
+ if cond vars then while (body vars) cond body else vars
+
+val until : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint until vars cond body :=
+ let vars := body vars in
+ if cond vars then vars else until (body vars) cond body
+
+
+Definition assert' b msg_opt :=
+ let msg := match msg_opt with
+ | Some msg => msg
+ | None => "unspecified error"
+ end in
+ if b then () else failwith msg
+
+(* convert numbers unsafely to naturals *)
+
+class (ToNatural a) val toNatural : a -> natural end
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+instance (ToNatural Z) let toNatural := (fun n => naturalFromInteger n) end
+instance (ToNatural int) let toNatural := (fun n => naturalFromInt n) end
+instance (ToNatural nat) let toNatural := (fun n => naturalFromNat n) end
+instance (ToNatural natural) let toNatural := (fun n => n) end
+
+Definition toNaturalFiveTup (n1,n2,n3,n4,n5) :=
+ (toNatural n1,
+ toNatural n2,
+ toNatural n3,
+ toNatural n4,
+ toNatural n5)
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+ or machine words as bitvector representation *)
+(*type regfp :=
+ | RFull of (string)
+ | RSlice of (string * Z * Z)
+ | RSliceBit of (string * Z)
+ | RField of (string * string)
+
+type niafp :=
+ | NIAFP_successor
+ | NIAFP_concrete_address of vector bitU
+ | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp :=
+ | DIAFP_none
+ | DIAFP_concrete of vector bitU
+ | DIAFP_reg of regfp
+
+Definition regfp_to_reg (reg_info : string -> option string -> (nat * nat * direction * (nat * nat))) := function
+ | RFull name =>
+ let (start,length,direction,_) := reg_info name None in
+ Reg name start length direction
+ | RSlice (name,i,j) =>
+ let i = Z.to_nat i in
+ let j = Z.to_nat j in
+ let (start,length,direction,_) = reg_info name None in
+ let slice = external_slice direction start (i,j) in
+ Reg_slice name start direction slice
+ | RSliceBit (name,i) =>
+ let i = Z.to_nat i in
+ let (start,length,direction,_) = reg_info name None in
+ let slice = external_slice direction start (i,i) in
+ Reg_slice name start direction slice
+ | RField (name,field_name) =>
+ let (start,length,direction,span) = reg_info name (Some field_name) in
+ let slice = external_slice direction start span in
+ Reg_field name start direction field_name slice
+end
+
+Definition niafp_to_nia reginfo = function
+ | NIAFP_successor => NIA_successor
+ | NIAFP_concrete_address v => NIA_concrete_address (address_of_bitv v)
+ | NIAFP_indirect_address => NIA_indirect_address
+end
+
+Definition diafp_to_dia reginfo = function
+ | DIAFP_none => DIA_none
+ | DIAFP_concrete v => DIA_concrete_address (address_of_bitv v)
+ | DIAFP_reg r => DIA_register (regfp_to_reg reginfo r)
+end
+*)
+*)
+
+(* Arithmetic functions which return proofs that match the expected Sail
+ types in smt.sail. *)
+
+Definition ediv_with_eq n m : {o : Z & ArithFact (o = ZEuclid.div n m)} := build_ex (ZEuclid.div n m).
+Definition emod_with_eq n m : {o : Z & ArithFact (o = ZEuclid.modulo n m)} := build_ex (ZEuclid.modulo n m).
+Definition abs_with_eq n : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n).
+
+(* Similarly, for ranges (currently in MIPS) *)
+
+Definition eq_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) : bool :=
+ (projT1 l) =? (projT1 r).
+Definition add_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+ : {x & ArithFact (n+o <= x <= m+p)} :=
+ build_ex ((projT1 l) + (projT1 r)).
+Definition sub_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+ : {x & ArithFact (n-p <= x <= m-o)} :=
+ build_ex ((projT1 l) - (projT1 r)).
+Definition negate_range {n m} (l : {l : Z & ArithFact (n <= l <= m)})
+ : {x : Z & ArithFact ((- m) <= x <= (- n))} :=
+ build_ex (- (projT1 l)).
+
+Definition min_atom (a : Z) (b : Z) : {c : Z & ArithFact ((c = a \/ c = b) /\ c <= a /\ c <= b)} :=
+ build_ex (Z.min a b).
+Definition max_atom (a : Z) (b : Z) : {c : Z & ArithFact ((c = a \/ c = b) /\ c >= a /\ c >= b)} :=
+ build_ex (Z.max a b).
+
+
+(*** Generic vectors *)
+
+Definition vec (T:Type) (n:Z) := { l : list T & length_list l = n }.
+Definition vec_length {T n} (v : vec T n) := n.
+Definition vec_access_dec {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+ access_list_dec (projT1 v) m.
+Definition vec_access_inc {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+ access_list_inc (projT1 v) m.
+
+Program Definition vec_init {T} (t : T) (n : Z) `{ArithFact (n >= 0)} : vec T n :=
+ existT _ (repeat [t] n) _.
+Next Obligation.
+rewrite repeat_length; auto using fact.
+unfold length_list.
+simpl.
+auto with zarith.
+Qed.
+
+Definition vec_concat {T m n} (v : vec T m) (w : vec T n) : vec T (m + n).
+refine (existT _ (projT1 v ++ projT1 w) _).
+destruct v.
+destruct w.
+simpl.
+unfold length_list in *.
+rewrite <- e, <- e0.
+rewrite app_length.
+rewrite Nat2Z.inj_add.
+reflexivity.
+Defined.
+
+Lemma skipn_length {A n} {l: list A} : (n <= List.length l -> List.length (skipn n l) = List.length l - n)%nat.
+revert l.
+induction n.
+* simpl. auto with arith.
+* intros l H.
+ destruct l.
+ + inversion H.
+ + simpl in H.
+ simpl.
+ rewrite IHn; auto with arith.
+Qed.
+Lemma update_list_inc_length {T} {l:list T} {m x} : 0 <= m < length_list l -> length_list (update_list_inc l m x) = length_list l.
+unfold update_list_inc, list_update, length_list.
+intro H.
+f_equal.
+assert ((0 <= Z.to_nat m < Datatypes.length l)%nat).
+{ destruct H as [H1 H2].
+ split.
+ + change 0%nat with (Z.to_nat 0).
+ apply Z2Nat.inj_le; auto with zarith.
+ + rewrite <- Nat2Z.id.
+ apply Z2Nat.inj_lt; auto with zarith.
+}
+rewrite app_length.
+rewrite firstn_length_le; only 2:omega.
+cbn -[skipn].
+rewrite skipn_length;
+omega.
+Qed.
+
+Program Definition vec_update_dec {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_dec (projT1 v) m t) _.
+Next Obligation.
+unfold update_list_dec.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+ destruct v. simpl (projT1 _). rewrite e.
+ omega.
+Qed.
+
+Program Definition vec_update_inc {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_inc (projT1 v) m t) _.
+Next Obligation.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+ destruct v. simpl (projT1 _). rewrite e.
+ omega.
+Qed.
+
+Program Definition vec_map {S T} (f : S -> T) {n} (v : vec S n) : vec T n := existT _ (List.map f (projT1 v)) _.
+Next Obligation.
+destruct v as [l H].
+cbn.
+unfold length_list.
+rewrite map_length.
+apply H.
+Qed.
+
+Program Definition just_vec {A n} (v : vec (option A) n) : option (vec A n) :=
+ match just_list (projT1 v) with
+ | None => None
+ | Some v' => Some (existT _ v' _)
+ end.
+Next Obligation.
+rewrite <- (just_list_length_Z _ _ Heq_anonymous).
+destruct v.
+assumption.
+Qed.
+
+Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v.
+
+Definition vec_eq_dec {T n} (D : forall x y : T, {x = y} + {x <> y}) (x y : vec T n) :
+ {x = y} + {x <> y}.
+refine (if List.list_eq_dec D (projT1 x) (projT1 y) then left _ else right _).
+* apply eq_sigT_hprop; auto using ZEqdep.UIP.
+* contradict n0. rewrite n0. reflexivity.
+Defined.
+
+Instance Decidable_eq_vec {T : Type} {n} `(DT : forall x y : T, Decidable (x = y)) :
+ forall x y : vec T n, Decidable (x = y) := {
+ Decidable_witness := proj1_sig (bool_of_sumbool (vec_eq_dec (fun x y => generic_dec x y) x y))
+}.
+destruct (vec_eq_dec _ x y); simpl; split; congruence.
+Defined.
+
+Program Definition vec_of_list {A} n (l : list A) : option (vec A n) :=
+ if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None.
+Next Obligation.
+symmetry.
+apply Z.eqb_eq.
+assumption.
+Qed.
+
+Definition vec_of_list_len {A} (l : list A) : vec A (length_list l) := existT _ l (eq_refl _).
+
+Definition map_bind {A B} (f : A -> option B) (a : option A) : option B :=
+match a with
+| Some a' => f a'
+| None => None
+end.
+
+Definition sub_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} :
+ {z : Z & ArithFact (z >= 0)} :=
+ let z := x - y in
+ if sumbool_of_bool (z >=? 0) then build_ex z else build_ex 0.
+
+Definition min_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} :
+ {z : Z & ArithFact (z >= 0)} :=
+ build_ex (Z.min x y).
+
+Definition max_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} :
+ {z : Z & ArithFact (z >= 0)} :=
+ build_ex (Z.max x y).
+
+Definition shl_int_8 (x y : Z) `{HE:ArithFact (x = 8)} `{HR:ArithFact (0 <= y <= 3)}: {z : Z & ArithFact (In z [8;16;32;64])}.
+refine (existT _ (shl_int x y) _).
+destruct HE as [HE].
+destruct HR as [HR].
+assert (H : y = 0 \/ y = 1 \/ y = 2 \/ y = 3) by omega.
+constructor.
+intuition (subst; compute; auto).
+Defined.
+
+Definition shl_int_32 (x y : Z) `{HE:ArithFact (x = 32)} `{HR:ArithFact (In y [0;1])}: {z : Z & ArithFact (In z [32;64])}.
+refine (existT _ (shl_int x y) _).
+destruct HE as [HE].
+destruct HR as [[HR1 | [HR2 | []]]];
+subst; compute;
+auto using Build_ArithFact.
+Defined.
+
+Definition shr_int_32 (x y : Z) `{HE:ArithFact (0 <= x <= 31)} `{HR:ArithFact (y = 1)}: {z : Z & ArithFact (0 <= z <= 15)}.
+refine (existT _ (shr_int x y) _).
+destruct HE as [HE].
+destruct HR as [HR];
+subst.
+unfold shr_int.
+rewrite <- Z.div2_spec.
+constructor.
+rewrite Z.div2_div.
+specialize (Z.div_mod x 2).
+specialize (Z.mod_pos_bound x 2).
+generalize (Z.div x 2).
+generalize (x mod 2).
+intros.
+nia.
+Defined.
+
+Lemma shl_8_ge_0 {n} : shl_int 8 n >= 0.
+unfold shl_int.
+apply Z.le_ge.
+apply <- Z.shiftl_nonneg.
+omega.
+Qed.
+Hint Resolve shl_8_ge_0 : sail.
+
+(* This is needed because Sail's internal constraint language doesn't have
+ < and could disappear if we add it... *)
+
+Lemma sail_lt_ge (x y : Z) :
+ x < y <-> y >= x +1.
+omega.
+Qed.
+Hint Resolve sail_lt_ge : sail.
diff --git a/prover_snapshots/coq/lib/sail/_CoqProject b/prover_snapshots/coq/lib/sail/_CoqProject
new file mode 100644
index 0000000..9f5d26b
--- /dev/null
+++ b/prover_snapshots/coq/lib/sail/_CoqProject
@@ -0,0 +1,2 @@
+-R . Sail
+-R ../../../bbv/theories bbv
diff --git a/prover_snapshots/hol4/.gitignore b/prover_snapshots/hol4/.gitignore
new file mode 100644
index 0000000..b8721d9
--- /dev/null
+++ b/prover_snapshots/hol4/.gitignore
@@ -0,0 +1,9 @@
+*.ui
+*.uo
+*Theory.sml
+*Theory.dat
+*Theory.sig
+.hollogs
+.HOLMK
+lib/lem/lemheap
+lib/sail/sail-heap
diff --git a/prover_snapshots/hol4/README.md b/prover_snapshots/hol4/README.md
new file mode 100644
index 0000000..6a16b91
--- /dev/null
+++ b/prover_snapshots/hol4/README.md
@@ -0,0 +1,11 @@
+# Snapshot of HOL4 output for Sail RISC-V model
+
+These theories are a snapshot of the generated files for the Sail RISC-V models
+translated to HOL4 via Lem. They only require HOL4; the necessary Lem library
+files are included.
+
+A recent checkout of HOL4 from the repository at
+<https://github.com/HOL-Theorem-Prover/HOL/> is required. This snapshot was
+successfully built with commit `86a5bc67f`, for example. Some older versions
+will fail with a Holdep error due to a lexer bug in HOL that has now been
+fixed.
diff --git a/prover_snapshots/hol4/RV32/Holmakefile b/prover_snapshots/hol4/RV32/Holmakefile
new file mode 100644
index 0000000..d90fcbe
--- /dev/null
+++ b/prover_snapshots/hol4/RV32/Holmakefile
@@ -0,0 +1,13 @@
+INCLUDES = ../lib/lem ../lib/sail
+
+SCRIPTS = riscv_extrasScript.sml riscv_typesScript.sml riscvScript.sml
+
+THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
+
+all: $(THYS)
+.PHONY: all
+
+ifdef POLY
+BASE_HEAP = ../lib/sail/sail-heap
+
+endif
diff --git a/prover_snapshots/hol4/RV32/riscvAuxiliaryScript.sml b/prover_snapshots/hol4/RV32/riscvAuxiliaryScript.sml
new file mode 100644
index 0000000..8de7133
--- /dev/null
+++ b/prover_snapshots/hol4/RV32/riscvAuxiliaryScript.sml
@@ -0,0 +1,50 @@
+(*Generated by Lem from generated_definitions/lem/RV32/riscv.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory riscvTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "riscvAuxiliary"
+
+
+(****************************************************)
+(* *)
+(* Termination Proofs *)
+(* *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (n_leading_spaces0_def, n_leading_spaces0_ind) *)
+val (n_leading_spaces0_rw, n_leading_spaces0_ind_rw) =
+ Defn.tprove_no_defn ((n_leading_spaces0_def, n_leading_spaces0_ind),
+ cheat (* the termination proof *)
+ )
+val n_leading_spaces0_rw = save_thm ("n_leading_spaces0_rw", n_leading_spaces0_rw);
+val n_leading_spaces0_ind_rw = save_thm ("n_leading_spaces0_ind_rw", n_leading_spaces0_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (walk32_def, walk32_ind) *)
+val (walk32_rw, walk32_ind_rw) =
+ Defn.tprove_no_defn ((walk32_def, walk32_ind),
+ cheat (* the termination proof *)
+ )
+val walk32_rw = save_thm ("walk32_rw", walk32_rw);
+val walk32_ind_rw = save_thm ("walk32_ind_rw", walk32_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (execute_def, execute_ind) *)
+val (execute_rw, execute_ind_rw) =
+ Defn.tprove_no_defn ((execute_def, execute_ind),
+ cheat (* the termination proof *)
+ )
+val execute_rw = save_thm ("execute_rw", execute_rw);
+val execute_ind_rw = save_thm ("execute_ind_rw", execute_ind_rw);
+
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV32/riscvScript.sml b/prover_snapshots/hol4/RV32/riscvScript.sml
new file mode 100644
index 0000000..52b43e6
--- /dev/null
+++ b/prover_snapshots/hol4/RV32/riscvScript.sml
@@ -0,0 +1,34910 @@
+(*Generated by Lem from generated_definitions/lem/RV32/riscv.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv"
+
+(*Generated by Sail from riscv.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+(*open import Riscv_types*)
+(*open import Riscv_extras*)
+
+(*val is_none : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_none:'a option -> bool) opt= ((case opt of SOME (_) => F | NONE => T )))`;
+
+
+(*val is_some : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_some:'a option -> bool) opt= ((case opt of SOME (_) => T | NONE => F )))`;
+
+
+(*val eq_unit : unit -> unit -> bool*)
+
+val _ = Define `
+ ((eq_unit:unit -> unit -> bool) _ _= T)`;
+
+
+
+
+(*val neq_bool : bool -> bool -> bool*)
+
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`;
+
+
+(*val __id : integer -> integer*)
+
+val _ = Define `
+ ((id:int -> int) x= x)`;
+
+
+(*val concat_str_bits : forall 'n. Size 'n => string -> mword 'n -> string*)
+
+val _ = Define `
+ ((concat_str_bits:string -> 'n words$word -> string) str x= (STRCAT str ((string_of_bits x))))`;
+
+
+(*val concat_str_dec : string -> ii -> string*)
+
+val _ = Define `
+ ((concat_str_dec:string -> int -> string) str x= (STRCAT str ((dec_str x))))`;
+
+
+
+
+(*val sail_mask : forall 'len 'v. Size 'len, Size 'v => integer -> mword 'v -> mword 'len*)
+
+val _ = Define `
+ ((sail_mask:int -> 'v words$word -> 'len words$word) len v=
+ (if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len : 'len words$word)
+ else (zero_extend v len : 'len words$word)))`;
+
+
+(*val sail_ones : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((sail_ones:int -> 'n words$word) n= ((not_vec ((zeros n : 'n words$word)) : 'n words$word)))`;
+
+
+(*val slice_mask : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*)
+
+val _ = Define `
+ ((slice_mask:int -> int -> int -> 'n words$word) n i l=
+ (if ((l >= n)) then (shiftl ((sail_ones n : 'n words$word)) i : 'n words$word)
+ else
+ let one1 = ((sail_mask n (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in
+ (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`;
+
+
+(*val read_kind_of_num : integer -> read_kind*)
+
+val _ = Define `
+ ((read_kind_of_num:int -> read_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Read_plain
+ else if (((p0_ = (( 1 : int):ii)))) then Read_reserve
+ else if (((p0_ = (( 2 : int):ii)))) then Read_acquire
+ else if (((p0_ = (( 3 : int):ii)))) then Read_exclusive
+ else if (((p0_ = (( 4 : int):ii)))) then Read_exclusive_acquire
+ else if (((p0_ = (( 5 : int):ii)))) then Read_stream
+ else if (((p0_ = (( 6 : int):ii)))) then Read_RISCV_acquire
+ else if (((p0_ = (( 7 : int):ii)))) then Read_RISCV_strong_acquire
+ else if (((p0_ = (( 8 : int):ii)))) then Read_RISCV_reserved
+ else if (((p0_ = (( 9 : int):ii)))) then Read_RISCV_reserved_acquire
+ else if (((p0_ = (( 10 : int):ii)))) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked))`;
+
+
+(*val num_of_read_kind : read_kind -> integer*)
+
+val _ = Define `
+ ((num_of_read_kind:read_kind -> int) arg_=
+ ((case arg_ of
+ Read_plain => (( 0 : int):ii)
+ | Read_reserve => (( 1 : int):ii)
+ | Read_acquire => (( 2 : int):ii)
+ | Read_exclusive => (( 3 : int):ii)
+ | Read_exclusive_acquire => (( 4 : int):ii)
+ | Read_stream => (( 5 : int):ii)
+ | Read_RISCV_acquire => (( 6 : int):ii)
+ | Read_RISCV_strong_acquire => (( 7 : int):ii)
+ | Read_RISCV_reserved => (( 8 : int):ii)
+ | Read_RISCV_reserved_acquire => (( 9 : int):ii)
+ | Read_RISCV_reserved_strong_acquire => (( 10 : int):ii)
+ | Read_X86_locked => (( 11 : int):ii)
+ )))`;
+
+
+(*val write_kind_of_num : integer -> write_kind*)
+
+val _ = Define `
+ ((write_kind_of_num:int -> write_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Write_plain
+ else if (((p0_ = (( 1 : int):ii)))) then Write_conditional
+ else if (((p0_ = (( 2 : int):ii)))) then Write_release
+ else if (((p0_ = (( 3 : int):ii)))) then Write_exclusive
+ else if (((p0_ = (( 4 : int):ii)))) then Write_exclusive_release
+ else if (((p0_ = (( 5 : int):ii)))) then Write_RISCV_release
+ else if (((p0_ = (( 6 : int):ii)))) then Write_RISCV_strong_release
+ else if (((p0_ = (( 7 : int):ii)))) then Write_RISCV_conditional
+ else if (((p0_ = (( 8 : int):ii)))) then Write_RISCV_conditional_release
+ else if (((p0_ = (( 9 : int):ii)))) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked))`;
+
+
+(*val num_of_write_kind : write_kind -> integer*)
+
+val _ = Define `
+ ((num_of_write_kind:write_kind -> int) arg_=
+ ((case arg_ of
+ Write_plain => (( 0 : int):ii)
+ | Write_conditional => (( 1 : int):ii)
+ | Write_release => (( 2 : int):ii)
+ | Write_exclusive => (( 3 : int):ii)
+ | Write_exclusive_release => (( 4 : int):ii)
+ | Write_RISCV_release => (( 5 : int):ii)
+ | Write_RISCV_strong_release => (( 6 : int):ii)
+ | Write_RISCV_conditional => (( 7 : int):ii)
+ | Write_RISCV_conditional_release => (( 8 : int):ii)
+ | Write_RISCV_conditional_strong_release => (( 9 : int):ii)
+ | Write_X86_locked => (( 10 : int):ii)
+ )))`;
+
+
+(*val barrier_kind_of_num : integer -> barrier_kind*)
+
+val _ = Define `
+ ((barrier_kind_of_num:int -> barrier_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Barrier_Sync
+ else if (((p0_ = (( 1 : int):ii)))) then Barrier_LwSync
+ else if (((p0_ = (( 2 : int):ii)))) then Barrier_Eieio
+ else if (((p0_ = (( 3 : int):ii)))) then Barrier_Isync
+ else if (((p0_ = (( 4 : int):ii)))) then Barrier_DMB
+ else if (((p0_ = (( 5 : int):ii)))) then Barrier_DMB_ST
+ else if (((p0_ = (( 6 : int):ii)))) then Barrier_DMB_LD
+ else if (((p0_ = (( 7 : int):ii)))) then Barrier_DSB
+ else if (((p0_ = (( 8 : int):ii)))) then Barrier_DSB_ST
+ else if (((p0_ = (( 9 : int):ii)))) then Barrier_DSB_LD
+ else if (((p0_ = (( 10 : int):ii)))) then Barrier_ISB
+ else if (((p0_ = (( 11 : int):ii)))) then Barrier_MIPS_SYNC
+ else if (((p0_ = (( 12 : int):ii)))) then Barrier_RISCV_rw_rw
+ else if (((p0_ = (( 13 : int):ii)))) then Barrier_RISCV_r_rw
+ else if (((p0_ = (( 14 : int):ii)))) then Barrier_RISCV_r_r
+ else if (((p0_ = (( 15 : int):ii)))) then Barrier_RISCV_rw_w
+ else if (((p0_ = (( 16 : int):ii)))) then Barrier_RISCV_w_w
+ else if (((p0_ = (( 17 : int):ii)))) then Barrier_RISCV_w_rw
+ else if (((p0_ = (( 18 : int):ii)))) then Barrier_RISCV_rw_r
+ else if (((p0_ = (( 19 : int):ii)))) then Barrier_RISCV_r_w
+ else if (((p0_ = (( 20 : int):ii)))) then Barrier_RISCV_w_r
+ else if (((p0_ = (( 21 : int):ii)))) then Barrier_RISCV_tso
+ else if (((p0_ = (( 22 : int):ii)))) then Barrier_RISCV_i
+ else Barrier_x86_MFENCE))`;
+
+
+(*val num_of_barrier_kind : barrier_kind -> integer*)
+
+val _ = Define `
+ ((num_of_barrier_kind:barrier_kind -> int) arg_=
+ ((case arg_ of
+ Barrier_Sync => (( 0 : int):ii)
+ | Barrier_LwSync => (( 1 : int):ii)
+ | Barrier_Eieio => (( 2 : int):ii)
+ | Barrier_Isync => (( 3 : int):ii)
+ | Barrier_DMB => (( 4 : int):ii)
+ | Barrier_DMB_ST => (( 5 : int):ii)
+ | Barrier_DMB_LD => (( 6 : int):ii)
+ | Barrier_DSB => (( 7 : int):ii)
+ | Barrier_DSB_ST => (( 8 : int):ii)
+ | Barrier_DSB_LD => (( 9 : int):ii)
+ | Barrier_ISB => (( 10 : int):ii)
+ | Barrier_MIPS_SYNC => (( 11 : int):ii)
+ | Barrier_RISCV_rw_rw => (( 12 : int):ii)
+ | Barrier_RISCV_r_rw => (( 13 : int):ii)
+ | Barrier_RISCV_r_r => (( 14 : int):ii)
+ | Barrier_RISCV_rw_w => (( 15 : int):ii)
+ | Barrier_RISCV_w_w => (( 16 : int):ii)
+ | Barrier_RISCV_w_rw => (( 17 : int):ii)
+ | Barrier_RISCV_rw_r => (( 18 : int):ii)
+ | Barrier_RISCV_r_w => (( 19 : int):ii)
+ | Barrier_RISCV_w_r => (( 20 : int):ii)
+ | Barrier_RISCV_tso => (( 21 : int):ii)
+ | Barrier_RISCV_i => (( 22 : int):ii)
+ | Barrier_x86_MFENCE => (( 23 : int):ii)
+ )))`;
+
+
+(*val trans_kind_of_num : integer -> trans_kind*)
+
+val _ = Define `
+ ((trans_kind_of_num:int -> trans_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Transaction_start
+ else if (((p0_ = (( 1 : int):ii)))) then Transaction_commit
+ else Transaction_abort))`;
+
+
+(*val num_of_trans_kind : trans_kind -> integer*)
+
+val _ = Define `
+ ((num_of_trans_kind:trans_kind -> int) arg_=
+ ((case arg_ of
+ Transaction_start => (( 0 : int):ii)
+ | Transaction_commit => (( 1 : int):ii)
+ | Transaction_abort => (( 2 : int):ii)
+ )))`;
+
+
+(*val cache_op_kind_of_num : integer -> cache_op_kind*)
+
+val _ = Define `
+ ((cache_op_kind_of_num:int -> cache_op_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Cache_op_D_IVAC
+ else if (((p0_ = (( 1 : int):ii)))) then Cache_op_D_ISW
+ else if (((p0_ = (( 2 : int):ii)))) then Cache_op_D_CSW
+ else if (((p0_ = (( 3 : int):ii)))) then Cache_op_D_CISW
+ else if (((p0_ = (( 4 : int):ii)))) then Cache_op_D_ZVA
+ else if (((p0_ = (( 5 : int):ii)))) then Cache_op_D_CVAC
+ else if (((p0_ = (( 6 : int):ii)))) then Cache_op_D_CVAU
+ else if (((p0_ = (( 7 : int):ii)))) then Cache_op_D_CIVAC
+ else if (((p0_ = (( 8 : int):ii)))) then Cache_op_I_IALLUIS
+ else if (((p0_ = (( 9 : int):ii)))) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU))`;
+
+
+(*val num_of_cache_op_kind : cache_op_kind -> integer*)
+
+val _ = Define `
+ ((num_of_cache_op_kind:cache_op_kind -> int) arg_=
+ ((case arg_ of
+ Cache_op_D_IVAC => (( 0 : int):ii)
+ | Cache_op_D_ISW => (( 1 : int):ii)
+ | Cache_op_D_CSW => (( 2 : int):ii)
+ | Cache_op_D_CISW => (( 3 : int):ii)
+ | Cache_op_D_ZVA => (( 4 : int):ii)
+ | Cache_op_D_CVAC => (( 5 : int):ii)
+ | Cache_op_D_CVAU => (( 6 : int):ii)
+ | Cache_op_D_CIVAC => (( 7 : int):ii)
+ | Cache_op_I_IALLUIS => (( 8 : int):ii)
+ | Cache_op_I_IALLU => (( 9 : int):ii)
+ | Cache_op_I_IVAU => (( 10 : int):ii)
+ )))`;
+
+
+
+
+
+
+(*val cast_unit_vec : bitU -> mword ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(1)words$word) b=
+ ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`;
+
+
+(*val get_config_print_instr : unit -> bool*)
+
+(*val get_config_print_reg : unit -> bool*)
+
+(*val get_config_print_mem : unit -> bool*)
+
+(*val get_config_print_platform : unit -> bool*)
+
+val _ = Define `
+ ((get_config_print_instr:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_reg:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_mem:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_platform:unit -> bool) () = F)`;
+
+
+(*val EXTS : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+(*val EXTZ : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((EXTS:int -> 'n words$word -> 'm words$word) m v= ((sign_extend v m : 'm words$word)))`;
+
+
+val _ = Define `
+ ((EXTZ:int -> 'n words$word -> 'm words$word) m v= ((zero_extend v m : 'm words$word)))`;
+
+
+(*val zeros_implicit : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((zeros_implicit:int -> 'n words$word) n= ((zeros n : 'n words$word)))`;
+
+
+(*val ones : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((ones:int -> 'n words$word) n= ((sail_ones n : 'n words$word)))`;
+
+
+(*val bool_to_bits : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`;
+
+
+(*val bit_to_bool : bitU -> bool*)
+
+val _ = Define `
+ ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | B0 => F )))`;
+
+
+(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*)
+
+val _ = Define `
+ ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int l n (( 0 : int):ii) : 'l words$word)))`;
+
+
+(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+val _ = Define `
+ ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) >= ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) < ((lem$w2ui y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) >= ((lem$w2ui y))))`;
+
+
+val _ = Define `
+ ((zopz0zIzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) <= ((lem$w2ui y))))`;
+
+
+(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*)
+
+val _ = Define `
+ ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 bits) (shift : 6 bits)=
+ (let (v128 : 128 bits) = ((EXTS (( 128 : int):ii) v : 128 words$word)) in
+ (subrange_vec_dec ((shift_bits_right v128 shift : 128 words$word)) (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*)
+
+val _ = Define `
+ ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 bits) (shift : 5 bits)=
+ (let (v64 : 64 bits) = ((EXTS (( 64 : int):ii) v : 64 words$word)) in
+ (subrange_vec_dec ((shift_bits_right v64 shift : 64 words$word)) (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val n_leading_spaces : string -> ii*)
+
+ val n_leading_spaces0_defn = Hol_defn "n_leading_spaces0" `
+ ((n_leading_spaces0:string -> int) s=
+ (let p0_ = s in
+ if (((p0_ = ""))) then (( 0 : int):ii)
+ else
+ let p0_ = (string_take s (( 1 : int):ii)) in
+ if (((p0_ = " "))) then (( 1 : int):ii) + ((n_leading_spaces0 ((string_drop s (( 1 : int):ii)))))
+ else (( 0 : int):ii)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn n_leading_spaces0_defn;
+
+(*val spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((spc_forwards:unit -> string) () = " ")`;
+
+
+(*val spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((spc_backwards:string -> unit) s= () )`;
+
+
+(*val spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((spc_matches_prefix0:string ->(unit#int)option) s=
+ (let n = (n_leading_spaces0 s) in
+ let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then NONE
+ else SOME (() , n)))`;
+
+
+(*val opt_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((opt_spc_forwards:unit -> string) () = "")`;
+
+
+(*val opt_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((opt_spc_backwards:string -> unit) s= () )`;
+
+
+(*val opt_spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((opt_spc_matches_prefix0:string ->(unit#int)option) s= (SOME (() , n_leading_spaces0 s)))`;
+
+
+(*val def_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((def_spc_forwards:unit -> string) () = " ")`;
+
+
+(*val def_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((def_spc_backwards:string -> unit) s= () )`;
+
+
+(*val def_spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((def_spc_matches_prefix:string ->(unit#ii)option) s= (opt_spc_matches_prefix0 s))`;
+
+
+(*val hex_bits_1_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((hex_bits_1_forwards_matches:(1)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_1_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_1_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 1 words$word # ii)) option)) of
+ SOME ((g__39, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_1_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((hex_bits_1_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 1 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_2_forwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((hex_bits_2_forwards_matches:(2)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_2_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_2_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 2 words$word # ii)) option)) of
+ SOME ((g__38, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_2_backwards : string -> M (mword ty2)*)
+
+val _ = Define `
+ ((hex_bits_2_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 2 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_3_forwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((hex_bits_3_forwards_matches:(3)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_3_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_3_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 3 words$word # ii)) option)) of
+ SOME ((g__37, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_3_backwards : string -> M (mword ty3)*)
+
+val _ = Define `
+ ((hex_bits_3_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((3)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 3 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_4_forwards_matches : mword ty4 -> bool*)
+
+val _ = Define `
+ ((hex_bits_4_forwards_matches:(4)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_4_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_4_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 4 words$word # ii)) option)) of
+ SOME ((g__36, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_4_backwards : string -> M (mword ty4)*)
+
+val _ = Define `
+ ((hex_bits_4_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 4 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_5_forwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((hex_bits_5_forwards_matches:(5)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_5_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_5_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 5 words$word # ii)) option)) of
+ SOME ((g__35, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_5_backwards : string -> M (mword ty5)*)
+
+val _ = Define `
+ ((hex_bits_5_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 5 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_6_forwards_matches : mword ty6 -> bool*)
+
+val _ = Define `
+ ((hex_bits_6_forwards_matches:(6)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_6_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_6_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 6 words$word # ii)) option)) of
+ SOME ((g__34, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_6_backwards : string -> M (mword ty6)*)
+
+val _ = Define `
+ ((hex_bits_6_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((6)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 6 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_7_forwards_matches : mword ty7 -> bool*)
+
+val _ = Define `
+ ((hex_bits_7_forwards_matches:(7)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_7_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_7_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 7 words$word # ii)) option)) of
+ SOME ((g__33, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_7_backwards : string -> M (mword ty7)*)
+
+val _ = Define `
+ ((hex_bits_7_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((7)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 7 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_8_forwards_matches : mword ty8 -> bool*)
+
+val _ = Define `
+ ((hex_bits_8_forwards_matches:(8)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_8_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_8_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 8 words$word # ii)) option)) of
+ SOME ((g__32, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_8_backwards : string -> M (mword ty8)*)
+
+val _ = Define `
+ ((hex_bits_8_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((8)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 8 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_9_forwards_matches : mword ty9 -> bool*)
+
+val _ = Define `
+ ((hex_bits_9_forwards_matches:(9)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_9_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_9_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 9 words$word # ii)) option)) of
+ SOME ((g__31, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_9_backwards : string -> M (mword ty9)*)
+
+val _ = Define `
+ ((hex_bits_9_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((9)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 9 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_10_forwards_matches : mword ty10 -> bool*)
+
+val _ = Define `
+ ((hex_bits_10_forwards_matches:(10)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_10_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_10_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 10 words$word # ii)) option)) of
+ SOME ((g__30, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_10_backwards : string -> M (mword ty10)*)
+
+val _ = Define `
+ ((hex_bits_10_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((10)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 10 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_11_forwards_matches : mword ty11 -> bool*)
+
+val _ = Define `
+ ((hex_bits_11_forwards_matches:(11)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_11_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_11_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 11 words$word # ii)) option)) of
+ SOME ((g__29, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_11_backwards : string -> M (mword ty11)*)
+
+val _ = Define `
+ ((hex_bits_11_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((11)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 11 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_12_forwards_matches : mword ty12 -> bool*)
+
+val _ = Define `
+ ((hex_bits_12_forwards_matches:(12)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_12_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_12_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 12 words$word # ii)) option)) of
+ SOME ((g__28, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_12_backwards : string -> M (mword ty12)*)
+
+val _ = Define `
+ ((hex_bits_12_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((12)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 12 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_13_forwards_matches : mword ty13 -> bool*)
+
+val _ = Define `
+ ((hex_bits_13_forwards_matches:(13)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_13_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_13_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 13 words$word # ii)) option)) of
+ SOME ((g__27, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_13_backwards : string -> M (mword ty13)*)
+
+val _ = Define `
+ ((hex_bits_13_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((13)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 13 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_14_forwards_matches : mword ty14 -> bool*)
+
+val _ = Define `
+ ((hex_bits_14_forwards_matches:(14)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_14_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_14_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 14 words$word # ii)) option)) of
+ SOME ((g__26, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_14_backwards : string -> M (mword ty14)*)
+
+val _ = Define `
+ ((hex_bits_14_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((14)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 14 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_15_forwards_matches : mword ty15 -> bool*)
+
+val _ = Define `
+ ((hex_bits_15_forwards_matches:(15)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_15_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_15_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 15 words$word # ii)) option)) of
+ SOME ((g__25, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_15_backwards : string -> M (mword ty15)*)
+
+val _ = Define `
+ ((hex_bits_15_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((15)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 15 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_16_forwards_matches : mword ty16 -> bool*)
+
+val _ = Define `
+ ((hex_bits_16_forwards_matches:(16)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_16_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_16_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 16 words$word # ii)) option)) of
+ SOME ((g__24, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_16_backwards : string -> M (mword ty16)*)
+
+val _ = Define `
+ ((hex_bits_16_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 16 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_17_forwards_matches : mword ty17 -> bool*)
+
+val _ = Define `
+ ((hex_bits_17_forwards_matches:(17)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_17_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_17_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 17 words$word # ii)) option)) of
+ SOME ((g__23, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_17_backwards : string -> M (mword ty17)*)
+
+val _ = Define `
+ ((hex_bits_17_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((17)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 17 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_18_forwards_matches : mword ty18 -> bool*)
+
+val _ = Define `
+ ((hex_bits_18_forwards_matches:(18)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_18_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_18_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 18 words$word # ii)) option)) of
+ SOME ((g__22, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_18_backwards : string -> M (mword ty18)*)
+
+val _ = Define `
+ ((hex_bits_18_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((18)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 18 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_19_forwards_matches : mword ty19 -> bool*)
+
+val _ = Define `
+ ((hex_bits_19_forwards_matches:(19)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_19_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_19_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 19 words$word # ii)) option)) of
+ SOME ((g__21, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_19_backwards : string -> M (mword ty19)*)
+
+val _ = Define `
+ ((hex_bits_19_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((19)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 19 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_20_forwards_matches : mword ty20 -> bool*)
+
+val _ = Define `
+ ((hex_bits_20_forwards_matches:(20)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_20_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_20_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 20 words$word # ii)) option)) of
+ SOME ((g__20, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_20_backwards : string -> M (mword ty20)*)
+
+val _ = Define `
+ ((hex_bits_20_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((20)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 20 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_21_forwards_matches : mword ty21 -> bool*)
+
+val _ = Define `
+ ((hex_bits_21_forwards_matches:(21)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_21_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_21_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 21 words$word # ii)) option)) of
+ SOME ((g__19, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_21_backwards : string -> M (mword ty21)*)
+
+val _ = Define `
+ ((hex_bits_21_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((21)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 21 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_22_forwards_matches : mword ty22 -> bool*)
+
+val _ = Define `
+ ((hex_bits_22_forwards_matches:(22)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_22_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_22_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 22 words$word # ii)) option)) of
+ SOME ((g__18, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_22_backwards : string -> M (mword ty22)*)
+
+val _ = Define `
+ ((hex_bits_22_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((22)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 22 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_23_forwards_matches : mword ty23 -> bool*)
+
+val _ = Define `
+ ((hex_bits_23_forwards_matches:(23)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_23_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_23_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 23 words$word # ii)) option)) of
+ SOME ((g__17, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_23_backwards : string -> M (mword ty23)*)
+
+val _ = Define `
+ ((hex_bits_23_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((23)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 23 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_24_forwards_matches : mword ty24 -> bool*)
+
+val _ = Define `
+ ((hex_bits_24_forwards_matches:(24)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_24_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_24_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 24 words$word # ii)) option)) of
+ SOME ((g__16, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_24_backwards : string -> M (mword ty24)*)
+
+val _ = Define `
+ ((hex_bits_24_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((24)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 24 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_25_forwards_matches : mword ty25 -> bool*)
+
+val _ = Define `
+ ((hex_bits_25_forwards_matches:(25)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_25_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_25_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 25 words$word # ii)) option)) of
+ SOME ((g__15, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_25_backwards : string -> M (mword ty25)*)
+
+val _ = Define `
+ ((hex_bits_25_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 25 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_26_forwards_matches : mword ty26 -> bool*)
+
+val _ = Define `
+ ((hex_bits_26_forwards_matches:(26)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_26_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_26_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 26 words$word # ii)) option)) of
+ SOME ((g__14, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_26_backwards : string -> M (mword ty26)*)
+
+val _ = Define `
+ ((hex_bits_26_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((26)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 26 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_27_forwards_matches : mword ty27 -> bool*)
+
+val _ = Define `
+ ((hex_bits_27_forwards_matches:(27)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_27_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_27_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 27 words$word # ii)) option)) of
+ SOME ((g__13, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_27_backwards : string -> M (mword ty27)*)
+
+val _ = Define `
+ ((hex_bits_27_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((27)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 27 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_28_forwards_matches : mword ty28 -> bool*)
+
+val _ = Define `
+ ((hex_bits_28_forwards_matches:(28)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_28_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_28_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 28 words$word # ii)) option)) of
+ SOME ((g__12, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_28_backwards : string -> M (mword ty28)*)
+
+val _ = Define `
+ ((hex_bits_28_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((28)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 28 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_29_forwards_matches : mword ty29 -> bool*)
+
+val _ = Define `
+ ((hex_bits_29_forwards_matches:(29)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_29_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_29_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 29 words$word # ii)) option)) of
+ SOME ((g__11, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_29_backwards : string -> M (mword ty29)*)
+
+val _ = Define `
+ ((hex_bits_29_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((29)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 29 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_30_forwards_matches : mword ty30 -> bool*)
+
+val _ = Define `
+ ((hex_bits_30_forwards_matches:(30)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_30_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_30_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 30 words$word # ii)) option)) of
+ SOME ((g__10, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_30_backwards : string -> M (mword ty30)*)
+
+val _ = Define `
+ ((hex_bits_30_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((30)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 30 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_31_forwards_matches : mword ty31 -> bool*)
+
+val _ = Define `
+ ((hex_bits_31_forwards_matches:(31)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_31_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_31_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 31 words$word # ii)) option)) of
+ SOME ((g__9, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_31_backwards : string -> M (mword ty31)*)
+
+val _ = Define `
+ ((hex_bits_31_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((31)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 31 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_32_forwards_matches : mword ty32 -> bool*)
+
+val _ = Define `
+ ((hex_bits_32_forwards_matches:(32)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_32_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_32_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 32 words$word # ii)) option)) of
+ SOME ((g__8, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_32_backwards : string -> M (mword ty32)*)
+
+val _ = Define `
+ ((hex_bits_32_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 32 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_33_forwards_matches : mword ty33 -> bool*)
+
+val _ = Define `
+ ((hex_bits_33_forwards_matches:(33)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_33_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_33_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 33 words$word # ii)) option)) of
+ SOME ((g__7, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_33_backwards : string -> M (mword ty33)*)
+
+val _ = Define `
+ ((hex_bits_33_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((33)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 33 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_48_forwards_matches : mword ty48 -> bool*)
+
+val _ = Define `
+ ((hex_bits_48_forwards_matches:(48)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_48_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_48_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 48 words$word # ii)) option)) of
+ SOME ((g__6, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_48_backwards : string -> M (mword ty48)*)
+
+val _ = Define `
+ ((hex_bits_48_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((48)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 48 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_64_forwards_matches : mword ty64 -> bool*)
+
+val _ = Define `
+ ((hex_bits_64_forwards_matches:(64)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_64_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_64_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 64 words$word # ii)) option)) of
+ SOME ((g__5, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_64_backwards : string -> M (mword ty64)*)
+
+val _ = Define `
+ ((hex_bits_64_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 64 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+val _ = Define `
+((default_meta:unit)= () )`;
+
+
+(*val __WriteRAM_Meta : mword ty32 -> integer -> unit -> M unit*)
+
+val _ = Define `
+ ((WriteRAM_Meta:(32)words$word -> int -> unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width meta= (sail2_state_monad$returnS () ))`;
+
+
+(*val __ReadRAM_Meta : mword ty32 -> integer -> M unit*)
+
+val _ = Define `
+ ((ReadRAM_Meta:(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= (sail2_state_monad$returnS () ))`;
+
+
+(*val write_ram : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M bool*)
+
+val _ = Define `
+ ((write_ram:write_kind ->(32)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) wk addr width data meta= (sail2_state_monad$bindS
+ (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 32 : int):ii) addr width data) (\ (ret : bool) . sail2_state_monad$seqS
+ (if ret then WriteRAM_Meta addr width meta else sail2_state_monad$returnS () ) (sail2_state_monad$returnS ret))))`;
+
+
+(*val write_ram_ea : write_kind -> mword ty32 -> integer -> M unit*)
+
+val _ = Define `
+ ((write_ram_ea:write_kind ->(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) wk addr width= (sail2_state_monad$returnS () ))`;
+
+
+(*val read_ram : forall 'int8_times_n. Size 'int8_times_n => read_kind -> mword ty32 -> integer -> M (mword 'int8_times_n)*)
+
+val _ = Define `
+ ((read_ram:read_kind ->(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('int8_times_n words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rk addr width= ((sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rk (( 32 : int):ii) addr width : ( 'int8_times_n words$word) M)))`;
+
+
+(*val __TraceMemoryWrite : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit*)
+
+(*val __TraceMemoryRead : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit*)
+
+val _ = Define `
+ ((xlen_val:int)= ((( 32 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_unsigned:int)= (((pow2 (( 32 : int):ii))) - (( 1 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_signed:int)= (((pow2 (((( 32 : int):ii) - (( 1 : int):ii))))) - (( 1 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_min_signed:int)= ((( 0 : int):ii) - ((pow2 (((( 32 : int):ii) - (( 1 : int):ii)))))))`;
+
+
+(*val regidx_to_regno : mword ty5 -> integer*)
+
+val _ = Define `
+ ((regidx_to_regno:(5)words$word -> int) b=
+ (let r = (lem$w2ui b) in
+ r))`;
+
+
+(*val creg2reg_idx : mword ty3 -> mword ty5*)
+
+val _ = Define `
+ ((creg2reg_idx:(3)words$word ->(5)words$word) creg= ((concat_vec (vec_of_bits [B0;B1] : 2 words$word) creg : 5 words$word)))`;
+
+
+val _ = Define `
+((zreg:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`;
+
+
+val _ = Define `
+((ra:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))`;
+
+
+val _ = Define `
+((sp:(5)words$word)= ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))`;
+
+
+(*val Architecture_of_num : integer -> Architecture*)
+
+val _ = Define `
+ ((Architecture_of_num:int -> Architecture) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RV32
+ else if (((p0_ = (( 1 : int):ii)))) then RV64
+ else RV128))`;
+
+
+(*val num_of_Architecture : Architecture -> integer*)
+
+val _ = Define `
+ ((num_of_Architecture:Architecture -> int) arg_=
+ ((case arg_ of RV32 => (( 0 : int):ii) | RV64 => (( 1 : int):ii) | RV128 => (( 2 : int):ii) )))`;
+
+
+(*val architecture : mword ty2 -> maybe Architecture*)
+
+val _ = Define `
+ ((architecture:(2)words$word ->(Architecture)option) a=
+ (let b__0 = a in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then SOME RV32
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then SOME RV64
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then SOME RV128
+ else NONE))`;
+
+
+(*val arch_to_bits : Architecture -> mword ty2*)
+
+val _ = Define `
+ ((arch_to_bits:Architecture ->(2)words$word) a=
+ ((case a of
+ RV32 => (vec_of_bits [B0;B1] : 2 words$word)
+ | RV64 => (vec_of_bits [B1;B0] : 2 words$word)
+ | RV128 => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val Privilege_of_num : integer -> Privilege*)
+
+val _ = Define `
+ ((Privilege_of_num:int -> Privilege) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then User
+ else if (((p0_ = (( 1 : int):ii)))) then Supervisor
+ else Machine))`;
+
+
+(*val num_of_Privilege : Privilege -> integer*)
+
+val _ = Define `
+ ((num_of_Privilege:Privilege -> int) arg_=
+ ((case arg_ of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Machine => (( 2 : int):ii) )))`;
+
+
+(*val privLevel_to_bits : Privilege -> mword ty2*)
+
+val _ = Define `
+ ((privLevel_to_bits:Privilege ->(2)words$word) p=
+ ((case p of
+ User => (vec_of_bits [B0;B0] : 2 words$word)
+ | Supervisor => (vec_of_bits [B0;B1] : 2 words$word)
+ | Machine => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val privLevel_of_bits : mword ty2 -> M Privilege*)
+
+val _ = Define `
+ ((privLevel_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p=
+ (let b__0 = p in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS User
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS Supervisor
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS Machine
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_types.sail 78:2 - 82:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val privLevel_to_str : Privilege -> string*)
+
+val _ = Define `
+ ((privLevel_to_str:Privilege -> string) p= ((case p of User => "U" | Supervisor => "S" | Machine => "M" )))`;
+
+
+(*val print_insn : ast -> M string*)
+
+(*val Retired_of_num : integer -> Retired*)
+
+val _ = Define `
+ ((Retired_of_num:int -> Retired) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RETIRE_SUCCESS
+ else RETIRE_FAIL))`;
+
+
+(*val num_of_Retired : Retired -> integer*)
+
+val _ = Define `
+ ((num_of_Retired:Retired -> int) arg_= ((case arg_ of RETIRE_SUCCESS => (( 0 : int):ii) | RETIRE_FAIL => (( 1 : int):ii) )))`;
+
+
+(*val AccessType_of_num : integer -> AccessType*)
+
+val _ = Define `
+ ((AccessType_of_num:int -> AccessType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Read
+ else if (((p0_ = (( 1 : int):ii)))) then Write
+ else if (((p0_ = (( 2 : int):ii)))) then ReadWrite
+ else Execute))`;
+
+
+(*val num_of_AccessType : AccessType -> integer*)
+
+val _ = Define `
+ ((num_of_AccessType:AccessType -> int) arg_=
+ ((case arg_ of Read => (( 0 : int):ii) | Write => (( 1 : int):ii) | ReadWrite => (( 2 : int):ii) | Execute => (( 3 : int):ii) )))`;
+
+
+(*val accessType_to_str : AccessType -> string*)
+
+val _ = Define `
+ ((accessType_to_str:AccessType -> string) a=
+ ((case a of Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" )))`;
+
+
+(*val word_width_of_num : integer -> word_width*)
+
+val _ = Define `
+ ((word_width_of_num:int -> word_width) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then BYTE
+ else if (((p0_ = (( 1 : int):ii)))) then HALF
+ else if (((p0_ = (( 2 : int):ii)))) then WORD
+ else DOUBLE))`;
+
+
+(*val num_of_word_width : word_width -> integer*)
+
+val _ = Define `
+ ((num_of_word_width:word_width -> int) arg_=
+ ((case arg_ of BYTE => (( 0 : int):ii) | HALF => (( 1 : int):ii) | WORD => (( 2 : int):ii) | DOUBLE => (( 3 : int):ii) )))`;
+
+
+(*val InterruptType_of_num : integer -> InterruptType*)
+
+val _ = Define `
+ ((InterruptType_of_num:int -> InterruptType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then I_U_Software
+ else if (((p0_ = (( 1 : int):ii)))) then I_S_Software
+ else if (((p0_ = (( 2 : int):ii)))) then I_M_Software
+ else if (((p0_ = (( 3 : int):ii)))) then I_U_Timer
+ else if (((p0_ = (( 4 : int):ii)))) then I_S_Timer
+ else if (((p0_ = (( 5 : int):ii)))) then I_M_Timer
+ else if (((p0_ = (( 6 : int):ii)))) then I_U_External
+ else if (((p0_ = (( 7 : int):ii)))) then I_S_External
+ else I_M_External))`;
+
+
+(*val num_of_InterruptType : InterruptType -> integer*)
+
+val _ = Define `
+ ((num_of_InterruptType:InterruptType -> int) arg_=
+ ((case arg_ of
+ I_U_Software => (( 0 : int):ii)
+ | I_S_Software => (( 1 : int):ii)
+ | I_M_Software => (( 2 : int):ii)
+ | I_U_Timer => (( 3 : int):ii)
+ | I_S_Timer => (( 4 : int):ii)
+ | I_M_Timer => (( 5 : int):ii)
+ | I_U_External => (( 6 : int):ii)
+ | I_S_External => (( 7 : int):ii)
+ | I_M_External => (( 8 : int):ii)
+ )))`;
+
+
+(*val interruptType_to_bits : InterruptType -> mword ty8*)
+
+val _ = Define `
+ ((interruptType_to_bits:InterruptType ->(8)words$word) i=
+ ((case i of
+ I_U_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)
+ | I_S_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)
+ | I_M_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word)
+ | I_U_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word)
+ | I_S_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word)
+ | I_M_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word)
+ | I_U_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word)
+ | I_S_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word)
+ | I_M_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word)
+ )))`;
+
+
+(*val ExceptionType_of_num : integer -> ExceptionType*)
+
+val _ = Define `
+ ((ExceptionType_of_num:int -> ExceptionType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then E_Fetch_Addr_Align
+ else if (((p0_ = (( 1 : int):ii)))) then E_Fetch_Access_Fault
+ else if (((p0_ = (( 2 : int):ii)))) then E_Illegal_Instr
+ else if (((p0_ = (( 3 : int):ii)))) then E_Breakpoint
+ else if (((p0_ = (( 4 : int):ii)))) then E_Load_Addr_Align
+ else if (((p0_ = (( 5 : int):ii)))) then E_Load_Access_Fault
+ else if (((p0_ = (( 6 : int):ii)))) then E_SAMO_Addr_Align
+ else if (((p0_ = (( 7 : int):ii)))) then E_SAMO_Access_Fault
+ else if (((p0_ = (( 8 : int):ii)))) then E_U_EnvCall
+ else if (((p0_ = (( 9 : int):ii)))) then E_S_EnvCall
+ else if (((p0_ = (( 10 : int):ii)))) then E_Reserved_10
+ else if (((p0_ = (( 11 : int):ii)))) then E_M_EnvCall
+ else if (((p0_ = (( 12 : int):ii)))) then E_Fetch_Page_Fault
+ else if (((p0_ = (( 13 : int):ii)))) then E_Load_Page_Fault
+ else if (((p0_ = (( 14 : int):ii)))) then E_Reserved_14
+ else if (((p0_ = (( 15 : int):ii)))) then E_SAMO_Page_Fault
+ else E_CHERI))`;
+
+
+(*val num_of_ExceptionType : ExceptionType -> integer*)
+
+val _ = Define `
+ ((num_of_ExceptionType:ExceptionType -> int) arg_=
+ ((case arg_ of
+ E_Fetch_Addr_Align => (( 0 : int):ii)
+ | E_Fetch_Access_Fault => (( 1 : int):ii)
+ | E_Illegal_Instr => (( 2 : int):ii)
+ | E_Breakpoint => (( 3 : int):ii)
+ | E_Load_Addr_Align => (( 4 : int):ii)
+ | E_Load_Access_Fault => (( 5 : int):ii)
+ | E_SAMO_Addr_Align => (( 6 : int):ii)
+ | E_SAMO_Access_Fault => (( 7 : int):ii)
+ | E_U_EnvCall => (( 8 : int):ii)
+ | E_S_EnvCall => (( 9 : int):ii)
+ | E_Reserved_10 => (( 10 : int):ii)
+ | E_M_EnvCall => (( 11 : int):ii)
+ | E_Fetch_Page_Fault => (( 12 : int):ii)
+ | E_Load_Page_Fault => (( 13 : int):ii)
+ | E_Reserved_14 => (( 14 : int):ii)
+ | E_SAMO_Page_Fault => (( 15 : int):ii)
+ | E_CHERI => (( 16 : int):ii)
+ )))`;
+
+
+(*val exceptionType_to_bits : ExceptionType -> mword ty8*)
+
+val _ = Define `
+ ((exceptionType_to_bits:ExceptionType ->(8)words$word) e=
+ ((case e of
+ E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)
+ | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)
+ | E_Illegal_Instr => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word)
+ | E_Breakpoint => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word)
+ | E_Load_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word)
+ | E_Load_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word)
+ | E_SAMO_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : 8 words$word)
+ | E_SAMO_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word)
+ | E_U_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word)
+ | E_S_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word)
+ | E_Reserved_10 => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word)
+ | E_M_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word)
+ | E_Fetch_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word)
+ | E_Load_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word)
+ | E_Reserved_14 => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B0] : 8 words$word)
+ | E_SAMO_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1] : 8 words$word)
+ | E_CHERI => (vec_of_bits [B0;B0;B1;B0;B0;B0;B0;B0] : 8 words$word)
+ )))`;
+
+
+(*val exceptionType_to_str : ExceptionType -> string*)
+
+val _ = Define `
+ ((exceptionType_to_str:ExceptionType -> string) e=
+ ((case e of
+ E_Fetch_Addr_Align => "misaligned-fetch"
+ | E_Fetch_Access_Fault => "fetch-access-fault"
+ | E_Illegal_Instr => "illegal-instruction"
+ | E_Breakpoint => "breakpoint"
+ | E_Load_Addr_Align => "misaligned-load"
+ | E_Load_Access_Fault => "load-access-fault"
+ | E_SAMO_Addr_Align => "misaliged-store/amo"
+ | E_SAMO_Access_Fault => "store/amo-access-fault"
+ | E_U_EnvCall => "u-call"
+ | E_S_EnvCall => "s-call"
+ | E_Reserved_10 => "reserved-0"
+ | E_M_EnvCall => "m-call"
+ | E_Fetch_Page_Fault => "fetch-page-fault"
+ | E_Load_Page_Fault => "load-page-fault"
+ | E_Reserved_14 => "reserved-1"
+ | E_SAMO_Page_Fault => "store/amo-page-fault"
+ | E_CHERI => "CHERI"
+ )))`;
+
+
+(*val not_implemented : forall 'a. string -> M 'a*)
+
+val _ = Define `
+ ((not_implemented:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) message= (sail2_state_monad$throwS (Error_not_implemented message)))`;
+
+
+(*val internal_error : forall 'a. string -> M 'a*)
+
+val _ = Define `
+ ((internal_error:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (sail2_state_monad$assert_expS F s) (sail2_state_monad$exitS () )))`;
+
+
+(*val TrapVectorMode_of_num : integer -> TrapVectorMode*)
+
+val _ = Define `
+ ((TrapVectorMode_of_num:int -> TrapVectorMode) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then TV_Direct
+ else if (((p0_ = (( 1 : int):ii)))) then TV_Vector
+ else TV_Reserved))`;
+
+
+(*val num_of_TrapVectorMode : TrapVectorMode -> integer*)
+
+val _ = Define `
+ ((num_of_TrapVectorMode:TrapVectorMode -> int) arg_=
+ ((case arg_ of TV_Direct => (( 0 : int):ii) | TV_Vector => (( 1 : int):ii) | TV_Reserved => (( 2 : int):ii) )))`;
+
+
+(*val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode*)
+
+val _ = Define `
+ ((trapVectorMode_of_bits:(2)words$word -> TrapVectorMode) m=
+ (let b__0 = m in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then TV_Direct
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then TV_Vector
+ else TV_Reserved))`;
+
+
+(*val ExtStatus_of_num : integer -> ExtStatus*)
+
+val _ = Define `
+ ((ExtStatus_of_num:int -> ExtStatus) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Off
+ else if (((p0_ = (( 1 : int):ii)))) then Initial
+ else if (((p0_ = (( 2 : int):ii)))) then Clean
+ else Dirty))`;
+
+
+(*val num_of_ExtStatus : ExtStatus -> integer*)
+
+val _ = Define `
+ ((num_of_ExtStatus:ExtStatus -> int) arg_=
+ ((case arg_ of Off => (( 0 : int):ii) | Initial => (( 1 : int):ii) | Clean => (( 2 : int):ii) | Dirty => (( 3 : int):ii) )))`;
+
+
+(*val extStatus_to_bits : ExtStatus -> mword ty2*)
+
+val _ = Define `
+ ((extStatus_to_bits:ExtStatus ->(2)words$word) e=
+ ((case e of
+ Off => (vec_of_bits [B0;B0] : 2 words$word)
+ | Initial => (vec_of_bits [B0;B1] : 2 words$word)
+ | Clean => (vec_of_bits [B1;B0] : 2 words$word)
+ | Dirty => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val extStatus_of_bits : mword ty2 -> M ExtStatus*)
+
+val _ = Define `
+ ((extStatus_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ExtStatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) e=
+ (let b__0 = e in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS Off
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS Initial
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS Clean
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS Dirty
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_types.sail 264:2 - 269:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val SATPMode_of_num : integer -> SATPMode*)
+
+val _ = Define `
+ ((SATPMode_of_num:int -> SATPMode) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Sbare
+ else if (((p0_ = (( 1 : int):ii)))) then Sv32
+ else if (((p0_ = (( 2 : int):ii)))) then Sv39
+ else Sv48))`;
+
+
+(*val num_of_SATPMode : SATPMode -> integer*)
+
+val _ = Define `
+ ((num_of_SATPMode:SATPMode -> int) arg_=
+ ((case arg_ of Sbare => (( 0 : int):ii) | Sv32 => (( 1 : int):ii) | Sv39 => (( 2 : int):ii) | Sv48 => (( 3 : int):ii) )))`;
+
+
+(*val satp64Mode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*)
+
+val _ = Define `
+ ((satp64Mode_of_bits:Architecture ->(4)words$word ->(SATPMode)option) (a : Architecture) (m : satp_mode)=
+ ((case (a, m) of
+ (g__4, b__0) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then SOME Sbare
+ else
+ (case (g__4, b__0) of
+ (RV32, b__0) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then SOME Sv32
+ else (case (RV32, b__0) of (_, _) => NONE )
+ | (RV64, b__0) =>
+ if (((b__0 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then SOME Sv39
+ else if (((b__0 = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) then SOME Sv48
+ else (case (RV64, b__0) of (_, _) => NONE )
+ | (_, _) => NONE
+ )
+ )))`;
+
+
+(*val uop_of_num : integer -> uop*)
+
+val _ = Define `
+ ((uop_of_num:int -> uop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_LUI
+ else RISCV_AUIPC))`;
+
+
+(*val num_of_uop : uop -> integer*)
+
+val _ = Define `
+ ((num_of_uop:uop -> int) arg_= ((case arg_ of RISCV_LUI => (( 0 : int):ii) | RISCV_AUIPC => (( 1 : int):ii) )))`;
+
+
+(*val bop_of_num : integer -> bop*)
+
+val _ = Define `
+ ((bop_of_num:int -> bop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_BEQ
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_BNE
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_BLT
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_BGE
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_BLTU
+ else RISCV_BGEU))`;
+
+
+(*val num_of_bop : bop -> integer*)
+
+val _ = Define `
+ ((num_of_bop:bop -> int) arg_=
+ ((case arg_ of
+ RISCV_BEQ => (( 0 : int):ii)
+ | RISCV_BNE => (( 1 : int):ii)
+ | RISCV_BLT => (( 2 : int):ii)
+ | RISCV_BGE => (( 3 : int):ii)
+ | RISCV_BLTU => (( 4 : int):ii)
+ | RISCV_BGEU => (( 5 : int):ii)
+ )))`;
+
+
+(*val iop_of_num : integer -> iop*)
+
+val _ = Define `
+ ((iop_of_num:int -> iop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDI
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SLTI
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLTIU
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_XORI
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_ORI
+ else RISCV_ANDI))`;
+
+
+(*val num_of_iop : iop -> integer*)
+
+val _ = Define `
+ ((num_of_iop:iop -> int) arg_=
+ ((case arg_ of
+ RISCV_ADDI => (( 0 : int):ii)
+ | RISCV_SLTI => (( 1 : int):ii)
+ | RISCV_SLTIU => (( 2 : int):ii)
+ | RISCV_XORI => (( 3 : int):ii)
+ | RISCV_ORI => (( 4 : int):ii)
+ | RISCV_ANDI => (( 5 : int):ii)
+ )))`;
+
+
+(*val sop_of_num : integer -> sop*)
+
+val _ = Define `
+ ((sop_of_num:int -> sop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLI
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLI
+ else RISCV_SRAI))`;
+
+
+(*val num_of_sop : sop -> integer*)
+
+val _ = Define `
+ ((num_of_sop:sop -> int) arg_=
+ ((case arg_ of RISCV_SLLI => (( 0 : int):ii) | RISCV_SRLI => (( 1 : int):ii) | RISCV_SRAI => (( 2 : int):ii) )))`;
+
+
+(*val rop_of_num : integer -> rop*)
+
+val _ = Define `
+ ((rop_of_num:int -> rop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADD
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUB
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLL
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_SLT
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_SLTU
+ else if (((p0_ = (( 5 : int):ii)))) then RISCV_XOR
+ else if (((p0_ = (( 6 : int):ii)))) then RISCV_SRL
+ else if (((p0_ = (( 7 : int):ii)))) then RISCV_SRA
+ else if (((p0_ = (( 8 : int):ii)))) then RISCV_OR
+ else RISCV_AND))`;
+
+
+(*val num_of_rop : rop -> integer*)
+
+val _ = Define `
+ ((num_of_rop:rop -> int) arg_=
+ ((case arg_ of
+ RISCV_ADD => (( 0 : int):ii)
+ | RISCV_SUB => (( 1 : int):ii)
+ | RISCV_SLL => (( 2 : int):ii)
+ | RISCV_SLT => (( 3 : int):ii)
+ | RISCV_SLTU => (( 4 : int):ii)
+ | RISCV_XOR => (( 5 : int):ii)
+ | RISCV_SRL => (( 6 : int):ii)
+ | RISCV_SRA => (( 7 : int):ii)
+ | RISCV_OR => (( 8 : int):ii)
+ | RISCV_AND => (( 9 : int):ii)
+ )))`;
+
+
+(*val ropw_of_num : integer -> ropw*)
+
+val _ = Define `
+ ((ropw_of_num:int -> ropw) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDW
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUBW
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLLW
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_SRLW
+ else RISCV_SRAW))`;
+
+
+(*val num_of_ropw : ropw -> integer*)
+
+val _ = Define `
+ ((num_of_ropw:ropw -> int) arg_=
+ ((case arg_ of
+ RISCV_ADDW => (( 0 : int):ii)
+ | RISCV_SUBW => (( 1 : int):ii)
+ | RISCV_SLLW => (( 2 : int):ii)
+ | RISCV_SRLW => (( 3 : int):ii)
+ | RISCV_SRAW => (( 4 : int):ii)
+ )))`;
+
+
+(*val sopw_of_num : integer -> sopw*)
+
+val _ = Define `
+ ((sopw_of_num:int -> sopw) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLIW
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLIW
+ else RISCV_SRAIW))`;
+
+
+(*val num_of_sopw : sopw -> integer*)
+
+val _ = Define `
+ ((num_of_sopw:sopw -> int) arg_=
+ ((case arg_ of RISCV_SLLIW => (( 0 : int):ii) | RISCV_SRLIW => (( 1 : int):ii) | RISCV_SRAIW => (( 2 : int):ii) )))`;
+
+
+(*val amoop_of_num : integer -> amoop*)
+
+val _ = Define `
+ ((amoop_of_num:int -> amoop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then AMOSWAP
+ else if (((p0_ = (( 1 : int):ii)))) then AMOADD
+ else if (((p0_ = (( 2 : int):ii)))) then AMOXOR
+ else if (((p0_ = (( 3 : int):ii)))) then AMOAND
+ else if (((p0_ = (( 4 : int):ii)))) then AMOOR
+ else if (((p0_ = (( 5 : int):ii)))) then AMOMIN
+ else if (((p0_ = (( 6 : int):ii)))) then AMOMAX
+ else if (((p0_ = (( 7 : int):ii)))) then AMOMINU
+ else AMOMAXU))`;
+
+
+(*val num_of_amoop : amoop -> integer*)
+
+val _ = Define `
+ ((num_of_amoop:amoop -> int) arg_=
+ ((case arg_ of
+ AMOSWAP => (( 0 : int):ii)
+ | AMOADD => (( 1 : int):ii)
+ | AMOXOR => (( 2 : int):ii)
+ | AMOAND => (( 3 : int):ii)
+ | AMOOR => (( 4 : int):ii)
+ | AMOMIN => (( 5 : int):ii)
+ | AMOMAX => (( 6 : int):ii)
+ | AMOMINU => (( 7 : int):ii)
+ | AMOMAXU => (( 8 : int):ii)
+ )))`;
+
+
+(*val csrop_of_num : integer -> csrop*)
+
+val _ = Define `
+ ((csrop_of_num:int -> csrop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then CSRRW
+ else if (((p0_ = (( 1 : int):ii)))) then CSRRS
+ else CSRRC))`;
+
+
+(*val num_of_csrop : csrop -> integer*)
+
+val _ = Define `
+ ((num_of_csrop:csrop -> int) arg_= ((case arg_ of CSRRW => (( 0 : int):ii) | CSRRS => (( 1 : int):ii) | CSRRC => (( 2 : int):ii) )))`;
+
+
+(*val sep_forwards : unit -> string*)
+
+val _ = Define `
+ ((sep_forwards:unit -> string) arg_=
+ ((case arg_ of
+ () =>
+ string_append ((opt_spc_forwards () ))
+ ((string_append "," ((string_append ((def_spc_forwards () )) ""))))
+ )))`;
+
+
+(*val sep_backwards : string -> M unit*)
+
+(*val _s0_ : string -> maybe unit*)
+
+val _ = Define `
+ ((s0_:string ->(unit)option) s1_0=
+ ((case s1_0 of
+ s2_0 =>
+ (case ((opt_spc_matches_prefix0 s2_0)) of
+ SOME ((() , s3_0)) =>
+ let s4_0 = (string_drop s2_0 s3_0) in
+ if ((string_startswith s4_0 ",")) then
+ (case ((string_drop s4_0 ((string_length ",")))) of
+ s5_0 =>
+ (case ((def_spc_matches_prefix s5_0)) of
+ SOME ((() , s6_0)) =>
+ let p0_ = (string_drop s5_0 s6_0) in
+ if (((p0_ = ""))) then SOME () else NONE
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s7_0 = arg_ in
+ if ((case ((s0_ s7_0)) of SOME (() ) => T | _ => F )) then
+ (case s0_ s7_0 of (SOME (() )) => sail2_state_monad$returnS () )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val sep_forwards_matches : unit -> bool*)
+
+val _ = Define `
+ ((sep_forwards_matches:unit -> bool) arg_=
+ ((case arg_ of () => T )))`;
+
+
+(*val sep_backwards_matches : string -> bool*)
+
+(*val _s8_ : string -> maybe unit*)
+
+val _ = Define `
+ ((s8_:string ->(unit)option) s9_0=
+ ((case s9_0 of
+ s10_0 =>
+ (case ((opt_spc_matches_prefix0 s10_0)) of
+ SOME ((() , s11_0)) =>
+ let s12_0 = (string_drop s10_0 s11_0) in
+ if ((string_startswith s12_0 ",")) then
+ (case ((string_drop s12_0 ((string_length ",")))) of
+ s13_0 =>
+ (case ((def_spc_matches_prefix s13_0)) of
+ SOME ((() , s14_0)) =>
+ let p0_ = (string_drop s13_0 s14_0) in
+ if (((p0_ = ""))) then SOME () else NONE
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_backwards_matches:string -> bool) arg_=
+ (let s15_0 = arg_ in
+ if ((case ((s8_ s15_0)) of SOME (() ) => T | _ => F )) then
+ (case s8_ s15_0 of (SOME (() )) => T )
+ else F))`;
+
+
+(*val sep_matches_prefix : string -> maybe ((unit * ii))*)
+
+(*val _s16_ : string -> maybe string*)
+
+val _ = Define `
+ ((s16_:string ->(string)option) s17_0=
+ ((case s17_0 of
+ s18_0 =>
+ (case ((opt_spc_matches_prefix0 s18_0)) of
+ SOME ((() , s19_0)) =>
+ let s20_0 = (string_drop s18_0 s19_0) in
+ if ((string_startswith s20_0 ",")) then
+ (case ((string_drop s20_0 ((string_length ",")))) of
+ s21_0 =>
+ (case ((def_spc_matches_prefix s21_0)) of
+ SOME ((() , s22_0)) =>
+ (case ((string_drop s21_0 s22_0)) of s_ => SOME s_ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_matches_prefix:string ->(unit#int)option) arg_=
+ (let s23_0 = arg_ in
+ if ((case ((s16_ s23_0)) of SOME (s_) => T | _ => F )) then
+ (case s16_ s23_0 of
+ (SOME (s_)) =>
+ SOME (() , ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bool_bits_forwards : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_bits_forwards:bool ->(1)words$word) arg_=
+ ((case arg_ of
+ T => (vec_of_bits [B1] : 1 words$word)
+ | F => (vec_of_bits [B0] : 1 words$word)
+ )))`;
+
+
+(*val bool_bits_backwards : mword ty1 -> M bool*)
+
+val _ = Define `
+ ((bool_bits_backwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bool_bits_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((bool_bits_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val bool_bits_backwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bool_bits_backwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bool_not_bits_forwards : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_not_bits_forwards:bool ->(1)words$word) arg_=
+ ((case arg_ of
+ T => (vec_of_bits [B0] : 1 words$word)
+ | F => (vec_of_bits [B1] : 1 words$word)
+ )))`;
+
+
+(*val bool_not_bits_backwards : mword ty1 -> M bool*)
+
+val _ = Define `
+ ((bool_not_bits_backwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS T
+ else if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bool_not_bits_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((bool_not_bits_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val bool_not_bits_backwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bool_not_bits_backwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val size_bits_forwards : word_width -> mword ty2*)
+
+val _ = Define `
+ ((size_bits_forwards:word_width ->(2)words$word) arg_=
+ ((case arg_ of
+ BYTE => (vec_of_bits [B0;B0] : 2 words$word)
+ | HALF => (vec_of_bits [B0;B1] : 2 words$word)
+ | WORD => (vec_of_bits [B1;B0] : 2 words$word)
+ | DOUBLE => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val size_bits_backwards : mword ty2 -> M word_width*)
+
+val _ = Define `
+ ((size_bits_backwards:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((word_width),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS BYTE
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS HALF
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS WORD
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS DOUBLE
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val size_bits_forwards_matches : word_width -> bool*)
+
+val _ = Define `
+ ((size_bits_forwards_matches:word_width -> bool) arg_=
+ ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
+
+
+(*val size_bits_backwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((size_bits_backwards_matches:(2)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then T
+ else F))`;
+
+
+(*val size_mnemonic_forwards : word_width -> string*)
+
+val _ = Define `
+ ((size_mnemonic_forwards:word_width -> string) arg_=
+ ((case arg_ of BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" )))`;
+
+
+(*val size_mnemonic_backwards : string -> M word_width*)
+
+val _ = Define `
+ ((size_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((word_width),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "b"))) then sail2_state_monad$returnS BYTE
+ else if (((p0_ = "h"))) then sail2_state_monad$returnS HALF
+ else if (((p0_ = "w"))) then sail2_state_monad$returnS WORD
+ else if (((p0_ = "d"))) then sail2_state_monad$returnS DOUBLE
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val size_mnemonic_forwards_matches : word_width -> bool*)
+
+val _ = Define `
+ ((size_mnemonic_forwards_matches:word_width -> bool) arg_=
+ ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
+
+
+(*val size_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((size_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "b"))) then T
+ else if (((p0_ = "h"))) then T
+ else if (((p0_ = "w"))) then T
+ else if (((p0_ = "d"))) then T
+ else F))`;
+
+
+(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*)
+
+(*val _s36_ : string -> maybe string*)
+
+val _ = Define `
+ ((s36_:string ->(string)option) s37_0=
+ (let s38_0 = s37_0 in
+ if ((string_startswith s38_0 "d")) then
+ (case ((string_drop s38_0 ((string_length "d")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s32_ : string -> maybe string*)
+
+val _ = Define `
+ ((s32_:string ->(string)option) s33_0=
+ (let s34_0 = s33_0 in
+ if ((string_startswith s34_0 "w")) then
+ (case ((string_drop s34_0 ((string_length "w")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s28_ : string -> maybe string*)
+
+val _ = Define `
+ ((s28_:string ->(string)option) s29_0=
+ (let s30_0 = s29_0 in
+ if ((string_startswith s30_0 "h")) then
+ (case ((string_drop s30_0 ((string_length "h")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s24_ : string -> maybe string*)
+
+val _ = Define `
+ ((s24_:string ->(string)option) s25_0=
+ (let s26_0 = s25_0 in
+ if ((string_startswith s26_0 "b")) then
+ (case ((string_drop s26_0 ((string_length "b")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((size_mnemonic_matches_prefix:string ->(word_width#int)option) arg_=
+ (let s27_0 = arg_ in
+ if ((case ((s24_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s24_ s27_0 of
+ (SOME (s_)) =>
+ SOME (BYTE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s28_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s28_ s27_0 of
+ (SOME (s_)) =>
+ SOME (HALF, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s32_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s32_ s27_0 of
+ (SOME (s_)) =>
+ SOME (WORD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s36_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s36_ s27_0 of
+ (SOME (s_)) =>
+ SOME (DOUBLE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val word_width_bytes : word_width -> integer*)
+
+val _ = Define `
+ ((word_width_bytes:word_width -> int) width=
+ ((case width of BYTE => (( 1 : int):ii) | HALF => (( 2 : int):ii) | WORD => (( 4 : int):ii) | DOUBLE => (( 8 : int):ii) )))`;
+
+
+val _ = Define `
+((zero_reg:(32)words$word)= ((EXTZ (( 32 : int):ii) (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 32 words$word)))`;
+
+
+(*val RegStr : mword ty32 -> string*)
+
+val _ = Define `
+ ((RegStr:(32)words$word -> string) r= (string_of_bits r))`;
+
+
+(*val regval_from_reg : mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((regval_from_reg:(32)words$word ->(32)words$word) r= r)`;
+
+
+(*val regval_into_reg : mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((regval_into_reg:(32)words$word ->(32)words$word) v= v)`;
+
+
+(*val rX : integer -> M (mword ty32)*)
+
+val _ = Define `
+ ((rX:int ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+ (let p0_ = r in sail2_state_monad$bindS
+ (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS zero_reg
+ else if (((p0_ = (( 1 : int):ii)))) then (sail2_state_monad$read_regS x1_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 2 : int):ii)))) then (sail2_state_monad$read_regS x2_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 3 : int):ii)))) then (sail2_state_monad$read_regS x3_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 4 : int):ii)))) then (sail2_state_monad$read_regS x4_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 5 : int):ii)))) then (sail2_state_monad$read_regS x5_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 6 : int):ii)))) then (sail2_state_monad$read_regS x6_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 7 : int):ii)))) then (sail2_state_monad$read_regS x7_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 8 : int):ii)))) then (sail2_state_monad$read_regS x8_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 9 : int):ii)))) then (sail2_state_monad$read_regS x9_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 10 : int):ii)))) then (sail2_state_monad$read_regS x10_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 11 : int):ii)))) then (sail2_state_monad$read_regS x11_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 12 : int):ii)))) then (sail2_state_monad$read_regS x12_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 13 : int):ii)))) then (sail2_state_monad$read_regS x13_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 14 : int):ii)))) then (sail2_state_monad$read_regS x14_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 15 : int):ii)))) then (sail2_state_monad$read_regS x15_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 16 : int):ii)))) then (sail2_state_monad$read_regS x16_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 17 : int):ii)))) then (sail2_state_monad$read_regS x17_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 18 : int):ii)))) then (sail2_state_monad$read_regS x18_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 19 : int):ii)))) then (sail2_state_monad$read_regS x19_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 20 : int):ii)))) then (sail2_state_monad$read_regS x20_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 21 : int):ii)))) then (sail2_state_monad$read_regS x21_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 22 : int):ii)))) then (sail2_state_monad$read_regS x22_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 23 : int):ii)))) then (sail2_state_monad$read_regS x23_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 24 : int):ii)))) then (sail2_state_monad$read_regS x24_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 25 : int):ii)))) then (sail2_state_monad$read_regS x25_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 26 : int):ii)))) then (sail2_state_monad$read_regS x26_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 27 : int):ii)))) then (sail2_state_monad$read_regS x27_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 28 : int):ii)))) then (sail2_state_monad$read_regS x28_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 29 : int):ii)))) then (sail2_state_monad$read_regS x29_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 30 : int):ii)))) then (sail2_state_monad$read_regS x30_ref : ( 32 words$word) M)
+ else if (((p0_ = (( 31 : int):ii)))) then (sail2_state_monad$read_regS x31_ref : ( 32 words$word) M)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "invalid register number") (sail2_state_monad$exitS () )) (\ (v : regtype) .
+ sail2_state_monad$returnS ((regval_from_reg v : 32 words$word)))))`;
+
+
+(*val rvfi_wX : integer -> mword ty32 -> unit*)
+
+val _ = Define `
+ ((rvfi_wX:int ->(32)words$word -> unit) r v= () )`;
+
+
+(*val wX : integer -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((wX:int ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r in_v=
+ (let v = ((regval_into_reg in_v : 32 words$word)) in
+ let p0_ = r in sail2_state_monad$seqS
+ (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS ()
+ else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$write_regS x1_ref v
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$write_regS x2_ref v
+ else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$write_regS x3_ref v
+ else if (((p0_ = (( 4 : int):ii)))) then sail2_state_monad$write_regS x4_ref v
+ else if (((p0_ = (( 5 : int):ii)))) then sail2_state_monad$write_regS x5_ref v
+ else if (((p0_ = (( 6 : int):ii)))) then sail2_state_monad$write_regS x6_ref v
+ else if (((p0_ = (( 7 : int):ii)))) then sail2_state_monad$write_regS x7_ref v
+ else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$write_regS x8_ref v
+ else if (((p0_ = (( 9 : int):ii)))) then sail2_state_monad$write_regS x9_ref v
+ else if (((p0_ = (( 10 : int):ii)))) then sail2_state_monad$write_regS x10_ref v
+ else if (((p0_ = (( 11 : int):ii)))) then sail2_state_monad$write_regS x11_ref v
+ else if (((p0_ = (( 12 : int):ii)))) then sail2_state_monad$write_regS x12_ref v
+ else if (((p0_ = (( 13 : int):ii)))) then sail2_state_monad$write_regS x13_ref v
+ else if (((p0_ = (( 14 : int):ii)))) then sail2_state_monad$write_regS x14_ref v
+ else if (((p0_ = (( 15 : int):ii)))) then sail2_state_monad$write_regS x15_ref v
+ else if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$write_regS x16_ref v
+ else if (((p0_ = (( 17 : int):ii)))) then sail2_state_monad$write_regS x17_ref v
+ else if (((p0_ = (( 18 : int):ii)))) then sail2_state_monad$write_regS x18_ref v
+ else if (((p0_ = (( 19 : int):ii)))) then sail2_state_monad$write_regS x19_ref v
+ else if (((p0_ = (( 20 : int):ii)))) then sail2_state_monad$write_regS x20_ref v
+ else if (((p0_ = (( 21 : int):ii)))) then sail2_state_monad$write_regS x21_ref v
+ else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$write_regS x22_ref v
+ else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$write_regS x23_ref v
+ else if (((p0_ = (( 24 : int):ii)))) then sail2_state_monad$write_regS x24_ref v
+ else if (((p0_ = (( 25 : int):ii)))) then sail2_state_monad$write_regS x25_ref v
+ else if (((p0_ = (( 26 : int):ii)))) then sail2_state_monad$write_regS x26_ref v
+ else if (((p0_ = (( 27 : int):ii)))) then sail2_state_monad$write_regS x27_ref v
+ else if (((p0_ = (( 28 : int):ii)))) then sail2_state_monad$write_regS x28_ref v
+ else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$write_regS x29_ref v
+ else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$write_regS x30_ref v
+ else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$write_regS x31_ref v
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "invalid register number") (sail2_state_monad$exitS () ))
+ (sail2_state_monad$returnS (if (((r <> (( 0 : int):ii)))) then
+ let (_ : unit) = (rvfi_wX r in_v) in
+ if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "x"
+ ((STRCAT ((stringFromInteger r)) ((STRCAT " <- " ((RegStr v))))))))
+ else ()
+ else () ))))`;
+
+
+(*val reg_name_abi : mword ty5 -> M string*)
+
+val _ = Define `
+ ((reg_name_abi:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+ (let b__0 = r in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS "zero"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "ra"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "sp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "gp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "tp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "fp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s8"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s9"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s10"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s11"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t6"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_regs.sail 149:2 - 182:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_forwards : mword ty5 -> M string*)
+
+val _ = Define `
+ ((reg_name_forwards:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS "zero"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "ra"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "sp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "gp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "tp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "fp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s8"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s9"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s10"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s11"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t6"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_backwards : string -> M (mword ty5)*)
+
+val _ = Define `
+ ((reg_name_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "zero"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "ra"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "sp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "gp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "tp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "t0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "t1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "t2"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "fp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "s1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "a0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "a1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "a2"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "a3"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "a4"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "a5"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "a6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "a7"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "s2"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "s3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "s4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "s5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "s6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "s7"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "s8"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "s9"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "s10"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "s11"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "t3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "t4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "t5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "t6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_forwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((reg_name_forwards_matches:(5)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else F))`;
+
+
+(*val reg_name_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((reg_name_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "zero"))) then T
+ else if (((p0_ = "ra"))) then T
+ else if (((p0_ = "sp"))) then T
+ else if (((p0_ = "gp"))) then T
+ else if (((p0_ = "tp"))) then T
+ else if (((p0_ = "t0"))) then T
+ else if (((p0_ = "t1"))) then T
+ else if (((p0_ = "t2"))) then T
+ else if (((p0_ = "fp"))) then T
+ else if (((p0_ = "s1"))) then T
+ else if (((p0_ = "a0"))) then T
+ else if (((p0_ = "a1"))) then T
+ else if (((p0_ = "a2"))) then T
+ else if (((p0_ = "a3"))) then T
+ else if (((p0_ = "a4"))) then T
+ else if (((p0_ = "a5"))) then T
+ else if (((p0_ = "a6"))) then T
+ else if (((p0_ = "a7"))) then T
+ else if (((p0_ = "s2"))) then T
+ else if (((p0_ = "s3"))) then T
+ else if (((p0_ = "s4"))) then T
+ else if (((p0_ = "s5"))) then T
+ else if (((p0_ = "s6"))) then T
+ else if (((p0_ = "s7"))) then T
+ else if (((p0_ = "s8"))) then T
+ else if (((p0_ = "s9"))) then T
+ else if (((p0_ = "s10"))) then T
+ else if (((p0_ = "s11"))) then T
+ else if (((p0_ = "t3"))) then T
+ else if (((p0_ = "t4"))) then T
+ else if (((p0_ = "t5"))) then T
+ else if (((p0_ = "t6"))) then T
+ else F))`;
+
+
+(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*)
+
+(*val _s164_ : string -> maybe string*)
+
+val _ = Define `
+ ((s164_:string ->(string)option) s165_0=
+ (let s166_0 = s165_0 in
+ if ((string_startswith s166_0 "t6")) then
+ (case ((string_drop s166_0 ((string_length "t6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s160_ : string -> maybe string*)
+
+val _ = Define `
+ ((s160_:string ->(string)option) s161_0=
+ (let s162_0 = s161_0 in
+ if ((string_startswith s162_0 "t5")) then
+ (case ((string_drop s162_0 ((string_length "t5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s156_ : string -> maybe string*)
+
+val _ = Define `
+ ((s156_:string ->(string)option) s157_0=
+ (let s158_0 = s157_0 in
+ if ((string_startswith s158_0 "t4")) then
+ (case ((string_drop s158_0 ((string_length "t4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s152_ : string -> maybe string*)
+
+val _ = Define `
+ ((s152_:string ->(string)option) s153_0=
+ (let s154_0 = s153_0 in
+ if ((string_startswith s154_0 "t3")) then
+ (case ((string_drop s154_0 ((string_length "t3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s148_ : string -> maybe string*)
+
+val _ = Define `
+ ((s148_:string ->(string)option) s149_0=
+ (let s150_0 = s149_0 in
+ if ((string_startswith s150_0 "s11")) then
+ (case ((string_drop s150_0 ((string_length "s11")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s144_ : string -> maybe string*)
+
+val _ = Define `
+ ((s144_:string ->(string)option) s145_0=
+ (let s146_0 = s145_0 in
+ if ((string_startswith s146_0 "s10")) then
+ (case ((string_drop s146_0 ((string_length "s10")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s140_ : string -> maybe string*)
+
+val _ = Define `
+ ((s140_:string ->(string)option) s141_0=
+ (let s142_0 = s141_0 in
+ if ((string_startswith s142_0 "s9")) then
+ (case ((string_drop s142_0 ((string_length "s9")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s136_ : string -> maybe string*)
+
+val _ = Define `
+ ((s136_:string ->(string)option) s137_0=
+ (let s138_0 = s137_0 in
+ if ((string_startswith s138_0 "s8")) then
+ (case ((string_drop s138_0 ((string_length "s8")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s132_ : string -> maybe string*)
+
+val _ = Define `
+ ((s132_:string ->(string)option) s133_0=
+ (let s134_0 = s133_0 in
+ if ((string_startswith s134_0 "s7")) then
+ (case ((string_drop s134_0 ((string_length "s7")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s128_ : string -> maybe string*)
+
+val _ = Define `
+ ((s128_:string ->(string)option) s129_0=
+ (let s130_0 = s129_0 in
+ if ((string_startswith s130_0 "s6")) then
+ (case ((string_drop s130_0 ((string_length "s6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s124_ : string -> maybe string*)
+
+val _ = Define `
+ ((s124_:string ->(string)option) s125_0=
+ (let s126_0 = s125_0 in
+ if ((string_startswith s126_0 "s5")) then
+ (case ((string_drop s126_0 ((string_length "s5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s120_ : string -> maybe string*)
+
+val _ = Define `
+ ((s120_:string ->(string)option) s121_0=
+ (let s122_0 = s121_0 in
+ if ((string_startswith s122_0 "s4")) then
+ (case ((string_drop s122_0 ((string_length "s4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s116_ : string -> maybe string*)
+
+val _ = Define `
+ ((s116_:string ->(string)option) s117_0=
+ (let s118_0 = s117_0 in
+ if ((string_startswith s118_0 "s3")) then
+ (case ((string_drop s118_0 ((string_length "s3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s112_ : string -> maybe string*)
+
+val _ = Define `
+ ((s112_:string ->(string)option) s113_0=
+ (let s114_0 = s113_0 in
+ if ((string_startswith s114_0 "s2")) then
+ (case ((string_drop s114_0 ((string_length "s2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s108_ : string -> maybe string*)
+
+val _ = Define `
+ ((s108_:string ->(string)option) s109_0=
+ (let s110_0 = s109_0 in
+ if ((string_startswith s110_0 "a7")) then
+ (case ((string_drop s110_0 ((string_length "a7")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s104_ : string -> maybe string*)
+
+val _ = Define `
+ ((s104_:string ->(string)option) s105_0=
+ (let s106_0 = s105_0 in
+ if ((string_startswith s106_0 "a6")) then
+ (case ((string_drop s106_0 ((string_length "a6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s100_ : string -> maybe string*)
+
+val _ = Define `
+ ((s100_:string ->(string)option) s101_0=
+ (let s102_0 = s101_0 in
+ if ((string_startswith s102_0 "a5")) then
+ (case ((string_drop s102_0 ((string_length "a5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s96_ : string -> maybe string*)
+
+val _ = Define `
+ ((s96_:string ->(string)option) s97_0=
+ (let s98_0 = s97_0 in
+ if ((string_startswith s98_0 "a4")) then
+ (case ((string_drop s98_0 ((string_length "a4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s92_ : string -> maybe string*)
+
+val _ = Define `
+ ((s92_:string ->(string)option) s93_0=
+ (let s94_0 = s93_0 in
+ if ((string_startswith s94_0 "a3")) then
+ (case ((string_drop s94_0 ((string_length "a3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s88_ : string -> maybe string*)
+
+val _ = Define `
+ ((s88_:string ->(string)option) s89_0=
+ (let s90_0 = s89_0 in
+ if ((string_startswith s90_0 "a2")) then
+ (case ((string_drop s90_0 ((string_length "a2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s84_ : string -> maybe string*)
+
+val _ = Define `
+ ((s84_:string ->(string)option) s85_0=
+ (let s86_0 = s85_0 in
+ if ((string_startswith s86_0 "a1")) then
+ (case ((string_drop s86_0 ((string_length "a1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s80_ : string -> maybe string*)
+
+val _ = Define `
+ ((s80_:string ->(string)option) s81_0=
+ (let s82_0 = s81_0 in
+ if ((string_startswith s82_0 "a0")) then
+ (case ((string_drop s82_0 ((string_length "a0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s76_ : string -> maybe string*)
+
+val _ = Define `
+ ((s76_:string ->(string)option) s77_0=
+ (let s78_0 = s77_0 in
+ if ((string_startswith s78_0 "s1")) then
+ (case ((string_drop s78_0 ((string_length "s1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s72_ : string -> maybe string*)
+
+val _ = Define `
+ ((s72_:string ->(string)option) s73_0=
+ (let s74_0 = s73_0 in
+ if ((string_startswith s74_0 "fp")) then
+ (case ((string_drop s74_0 ((string_length "fp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s68_ : string -> maybe string*)
+
+val _ = Define `
+ ((s68_:string ->(string)option) s69_0=
+ (let s70_0 = s69_0 in
+ if ((string_startswith s70_0 "t2")) then
+ (case ((string_drop s70_0 ((string_length "t2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s64_ : string -> maybe string*)
+
+val _ = Define `
+ ((s64_:string ->(string)option) s65_0=
+ (let s66_0 = s65_0 in
+ if ((string_startswith s66_0 "t1")) then
+ (case ((string_drop s66_0 ((string_length "t1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s60_ : string -> maybe string*)
+
+val _ = Define `
+ ((s60_:string ->(string)option) s61_0=
+ (let s62_0 = s61_0 in
+ if ((string_startswith s62_0 "t0")) then
+ (case ((string_drop s62_0 ((string_length "t0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s56_ : string -> maybe string*)
+
+val _ = Define `
+ ((s56_:string ->(string)option) s57_0=
+ (let s58_0 = s57_0 in
+ if ((string_startswith s58_0 "tp")) then
+ (case ((string_drop s58_0 ((string_length "tp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s52_ : string -> maybe string*)
+
+val _ = Define `
+ ((s52_:string ->(string)option) s53_0=
+ (let s54_0 = s53_0 in
+ if ((string_startswith s54_0 "gp")) then
+ (case ((string_drop s54_0 ((string_length "gp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s48_ : string -> maybe string*)
+
+val _ = Define `
+ ((s48_:string ->(string)option) s49_0=
+ (let s50_0 = s49_0 in
+ if ((string_startswith s50_0 "sp")) then
+ (case ((string_drop s50_0 ((string_length "sp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s44_ : string -> maybe string*)
+
+val _ = Define `
+ ((s44_:string ->(string)option) s45_0=
+ (let s46_0 = s45_0 in
+ if ((string_startswith s46_0 "ra")) then
+ (case ((string_drop s46_0 ((string_length "ra")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s40_ : string -> maybe string*)
+
+val _ = Define `
+ ((s40_:string ->(string)option) s41_0=
+ (let s42_0 = s41_0 in
+ if ((string_startswith s42_0 "zero")) then
+ (case ((string_drop s42_0 ((string_length "zero")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((reg_name_matches_prefix:string ->((5)words$word#int)option) arg_=
+ (let s43_0 = arg_ in
+ if ((case ((s40_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s40_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s44_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s44_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s48_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s48_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s52_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s52_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s56_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s56_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s60_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s60_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s64_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s64_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s68_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s68_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s72_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s72_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s76_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s76_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s80_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s80_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s84_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s84_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s88_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s88_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s92_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s92_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s96_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s96_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s100_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s100_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s104_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s104_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s108_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s108_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s112_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s112_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s116_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s116_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s120_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s120_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s124_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s124_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s128_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s128_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s132_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s132_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s136_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s136_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s140_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s140_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s144_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s144_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s148_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s148_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s152_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s152_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s156_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s156_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s160_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s160_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s164_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s164_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val creg_name_forwards : mword ty3 -> M string*)
+
+val _ = Define `
+ ((creg_name_forwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS "s0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS "s1"
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS "a0"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS "a1"
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS "a2"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS "a3"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS "a4"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS "a5"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val creg_name_backwards : string -> M (mword ty3)*)
+
+val _ = Define `
+ ((creg_name_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((3)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "s0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0] : 3 words$word)
+ else if (((p0_ = "s1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1] : 3 words$word)
+ else if (((p0_ = "a0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0] : 3 words$word)
+ else if (((p0_ = "a1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1] : 3 words$word)
+ else if (((p0_ = "a2"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0] : 3 words$word)
+ else if (((p0_ = "a3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1] : 3 words$word)
+ else if (((p0_ = "a4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0] : 3 words$word)
+ else if (((p0_ = "a5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1] : 3 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val creg_name_forwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((creg_name_forwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val creg_name_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((creg_name_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "s0"))) then T
+ else if (((p0_ = "s1"))) then T
+ else if (((p0_ = "a0"))) then T
+ else if (((p0_ = "a1"))) then T
+ else if (((p0_ = "a2"))) then T
+ else if (((p0_ = "a3"))) then T
+ else if (((p0_ = "a4"))) then T
+ else if (((p0_ = "a5"))) then T
+ else F))`;
+
+
+(*val creg_name_matches_prefix : string -> maybe ((mword ty3 * ii))*)
+
+(*val _s196_ : string -> maybe string*)
+
+val _ = Define `
+ ((s196_:string ->(string)option) s197_0=
+ (let s198_0 = s197_0 in
+ if ((string_startswith s198_0 "a5")) then
+ (case ((string_drop s198_0 ((string_length "a5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s192_ : string -> maybe string*)
+
+val _ = Define `
+ ((s192_:string ->(string)option) s193_0=
+ (let s194_0 = s193_0 in
+ if ((string_startswith s194_0 "a4")) then
+ (case ((string_drop s194_0 ((string_length "a4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s188_ : string -> maybe string*)
+
+val _ = Define `
+ ((s188_:string ->(string)option) s189_0=
+ (let s190_0 = s189_0 in
+ if ((string_startswith s190_0 "a3")) then
+ (case ((string_drop s190_0 ((string_length "a3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s184_ : string -> maybe string*)
+
+val _ = Define `
+ ((s184_:string ->(string)option) s185_0=
+ (let s186_0 = s185_0 in
+ if ((string_startswith s186_0 "a2")) then
+ (case ((string_drop s186_0 ((string_length "a2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s180_ : string -> maybe string*)
+
+val _ = Define `
+ ((s180_:string ->(string)option) s181_0=
+ (let s182_0 = s181_0 in
+ if ((string_startswith s182_0 "a1")) then
+ (case ((string_drop s182_0 ((string_length "a1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s176_ : string -> maybe string*)
+
+val _ = Define `
+ ((s176_:string ->(string)option) s177_0=
+ (let s178_0 = s177_0 in
+ if ((string_startswith s178_0 "a0")) then
+ (case ((string_drop s178_0 ((string_length "a0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s172_ : string -> maybe string*)
+
+val _ = Define `
+ ((s172_:string ->(string)option) s173_0=
+ (let s174_0 = s173_0 in
+ if ((string_startswith s174_0 "s1")) then
+ (case ((string_drop s174_0 ((string_length "s1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s168_ : string -> maybe string*)
+
+val _ = Define `
+ ((s168_:string ->(string)option) s169_0=
+ (let s170_0 = s169_0 in
+ if ((string_startswith s170_0 "s0")) then
+ (case ((string_drop s170_0 ((string_length "s0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((creg_name_matches_prefix:string ->((3)words$word#int)option) arg_=
+ (let s171_0 = arg_ in
+ if ((case ((s168_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s168_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s172_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s172_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s176_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s176_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s180_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s180_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s184_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s184_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s188_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s188_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s192_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s192_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s196_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s196_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val init_base_regs : unit -> M unit*)
+
+val _ = Define `
+ ((init_base_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS x1_ref zero_reg)
+ (sail2_state_monad$write_regS x2_ref zero_reg))
+ (sail2_state_monad$write_regS x3_ref zero_reg))
+ (sail2_state_monad$write_regS x4_ref zero_reg))
+ (sail2_state_monad$write_regS x5_ref zero_reg))
+ (sail2_state_monad$write_regS x6_ref zero_reg))
+ (sail2_state_monad$write_regS x7_ref zero_reg))
+ (sail2_state_monad$write_regS x8_ref zero_reg))
+ (sail2_state_monad$write_regS x9_ref zero_reg))
+ (sail2_state_monad$write_regS x10_ref zero_reg))
+ (sail2_state_monad$write_regS x11_ref zero_reg))
+ (sail2_state_monad$write_regS x12_ref zero_reg))
+ (sail2_state_monad$write_regS x13_ref zero_reg))
+ (sail2_state_monad$write_regS x14_ref zero_reg))
+ (sail2_state_monad$write_regS x15_ref zero_reg))
+ (sail2_state_monad$write_regS x16_ref zero_reg))
+ (sail2_state_monad$write_regS x17_ref zero_reg))
+ (sail2_state_monad$write_regS x18_ref zero_reg))
+ (sail2_state_monad$write_regS x19_ref zero_reg))
+ (sail2_state_monad$write_regS x20_ref zero_reg))
+ (sail2_state_monad$write_regS x21_ref zero_reg))
+ (sail2_state_monad$write_regS x22_ref zero_reg))
+ (sail2_state_monad$write_regS x23_ref zero_reg))
+ (sail2_state_monad$write_regS x24_ref zero_reg))
+ (sail2_state_monad$write_regS x25_ref zero_reg))
+ (sail2_state_monad$write_regS x26_ref zero_reg))
+ (sail2_state_monad$write_regS x27_ref zero_reg))
+ (sail2_state_monad$write_regS x28_ref zero_reg))
+ (sail2_state_monad$write_regS x29_ref zero_reg)) (sail2_state_monad$write_regS x30_ref zero_reg)) (sail2_state_monad$write_regS x31_ref zero_reg)))`;
+
+
+(*
+ Retrieves the architectural PC value. This is not necessarily the value
+ found in the PC register as extensions may choose to override this function.
+ The value in the PC register is the absolute virtual address of the instruction
+ to fetch.
+ *)
+(*val get_arch_pc : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_arch_pc:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS PC_ref : ( 32 words$word) M)))`;
+
+
+(*val get_next_pc : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS nextPC_ref : ( 32 words$word) M)))`;
+
+
+(*val set_next_pc : mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_next_pc:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc= (sail2_state_monad$write_regS nextPC_ref pc))`;
+
+
+(*val tick_pc : unit -> M unit*)
+
+val _ = Define `
+ ((tick_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS nextPC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$write_regS PC_ref w__0)))`;
+
+
+(*val Mk_Misa : mword ty32 -> Misa*)
+
+val _ = Define `
+ ((Mk_Misa:(32)words$word -> Misa) v= (<| Misa_Misa_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Misa_bits : Misa -> mword ty32*)
+
+val _ = Define `
+ ((get_Misa_bits:Misa ->(32)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_bits:((regstate),(register_value),(Misa))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_bits : Misa -> mword ty32 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_bits:Misa ->(32)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_bits : SV48_PTE -> mword ty64 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_bits : SV48_PTE -> mword ty64*)
+
+(*val _set_SV48_PTE_bits : register_ref regstate register_value SV48_PTE -> mword ty64 -> M unit*)
+
+(*val _get_Misa_MXL : Misa -> mword ty2*)
+
+val _ = Define `
+ ((get_Misa_MXL:Misa ->(2)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 31 : int):ii) (( 30 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_MXL:Misa ->(2)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 31 : int):ii) (( 30 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_Z : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Z:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Z : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Z:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_Y : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Y:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Y : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Y:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_X : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_X:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_X : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_X:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_X : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_W : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_W:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_W : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_W:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_W : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_V : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_V:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_V : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_V:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_V : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_U : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_U:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_U : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_U:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_U : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_T : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_T:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_T : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_T:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_S : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_S:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_S : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_S:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_R : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_R:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_R : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_R:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_R : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_Q : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Q:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Q : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Q:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_P : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_P:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_P : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_P:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_O : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_O:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_O : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_O:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_N : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_N:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_N : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_N:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_M : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_M:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_M : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_M:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_L : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_L:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_L : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_L:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+(*val _get_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1*)
+
+(*val _set_Pmpcfg_ent_L : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+(*val _get_Misa_K : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_K:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_K : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_K:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_J : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_J:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_J : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_J:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_I : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_I:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_I : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_I:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_H : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_H:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_H : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_H:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_G : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_G:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_G : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_G:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_G : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_F : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_F:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_F : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_F:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_E : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_E:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_E : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_E:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_D : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_D:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_D : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_D:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_D : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_C : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_C:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_C : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_C:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_B : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_B:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_B : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_B:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Misa_A : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_A:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_A : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_A:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_A : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val legalize_misa : Misa -> mword ty32 -> M Misa*)
+
+val _ = Define `
+ ((legalize_misa:Misa ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Misa),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Misa) (v : xlenbits)=
+ (if ((sys_enable_writable_misa () )) then
+ let v = (Mk_Misa v) in sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((get_Misa_C v : 1 words$word)) = ((bool_to_bits F : 1 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS nextPC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ sail2_state_monad$returnS (((((bit_to_bool ((access_vec_dec w__0 (( 1 : int):ii))))) = T)))))) (\ (w__1 : bool) .
+ sail2_state_monad$returnS (if w__1 then m
+ else update_Misa_C m ((get_Misa_C v : 1 words$word))))
+ else sail2_state_monad$returnS m))`;
+
+
+(*val haveAtomics : unit -> M bool*)
+
+val _ = Define `
+ ((haveAtomics:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveRVC : unit -> M bool*)
+
+val _ = Define `
+ ((haveRVC:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveMulDiv : unit -> M bool*)
+
+val _ = Define `
+ ((haveMulDiv:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveSupMode : unit -> M bool*)
+
+val _ = Define `
+ ((haveSupMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_S w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveUsrMode : unit -> M bool*)
+
+val _ = Define `
+ ((haveUsrMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_U w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveNExt : unit -> M bool*)
+
+val _ = Define `
+ ((haveNExt:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_N w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val Mk_Mstatus : mword ty32 -> Mstatus*)
+
+val _ = Define `
+ ((Mk_Mstatus:(32)words$word -> Mstatus) v=
+ (<| Mstatus_Mstatus_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Mstatus_bits : Mstatus -> mword ty32*)
+
+val _ = Define `
+ ((get_Mstatus_bits:Mstatus ->(32)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_bits:((regstate),(register_value),(Mstatus))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_bits : Mstatus -> mword ty32 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_bits:Mstatus ->(32)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SD : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SD:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SD : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_TSR : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TSR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_TW : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TW:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_TVM : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TVM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_MXR : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MXR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_MXR : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_SUM : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SUM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SUM : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MPRV : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPRV:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_XS : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_XS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*)
+
+(*val _get_Sstatus_XS : Sstatus -> mword ty2*)
+
+(*val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*)
+
+(*val _get_Mstatus_FS : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_FS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*)
+
+(*val _get_Sstatus_FS : Sstatus -> mword ty2*)
+
+(*val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*)
+
+(*val _get_Mstatus_MPP : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_MPP:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SPP : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPP:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SPP : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SPIE : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_UPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Ustatus_UPIE : Ustatus -> mword ty1 -> Ustatus*)
+
+(*val _get_Ustatus_UPIE : Ustatus -> mword ty1*)
+
+(*val _set_Ustatus_UPIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SIE : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_UIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Ustatus_UIE : Ustatus -> mword ty1 -> Ustatus*)
+
+(*val _get_Ustatus_UIE : Ustatus -> mword ty1*)
+
+(*val _set_Ustatus_UIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit*)
+
+(*val effectivePrivilege : Mstatus -> Privilege -> M Privilege*)
+
+val _ = Define `
+ ((effectivePrivilege:Mstatus -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (priv : Privilege)=
+ (if (((((get_Mstatus_MPRV m : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__0 : 2 words$word)))
+ else sail2_state_monad$read_regS cur_privilege_ref))`;
+
+
+(*val get_mstatus_SXL : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_mstatus_SXL:Mstatus ->(2)words$word) m= ((arch_to_bits RV32 : 2 words$word)))`;
+
+
+(*val set_mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((set_mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) (m : Mstatus) (a : arch_xlen)= m)`;
+
+
+(*val get_mstatus_UXL : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_mstatus_UXL:Mstatus ->(2)words$word) m= ((arch_to_bits RV32 : 2 words$word)))`;
+
+
+(*val set_mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((set_mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) (m : Mstatus) (a : arch_xlen)= m)`;
+
+
+(*val legalize_mstatus : Mstatus -> mword ty32 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_mstatus:Mstatus ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Mstatus) (v : xlenbits)=
+ (let (m : Mstatus) = (Mk_Mstatus v) in
+ let m = (update_Mstatus_XS m ((extStatus_to_bits Off : 2 words$word))) in sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_FS m : 2 words$word))) (\ (w__0 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__0 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_XS m : 2 words$word))) (\ (w__1 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__1 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) (\ (w__2 : bool) .
+ let m = (update_Mstatus_SD m ((bool_to_bits w__2 : 1 words$word))) in
+ let m = (set_mstatus_SXL m ((get_mstatus_SXL o1 : 2 words$word))) in
+ let m = (set_mstatus_UXL m ((get_mstatus_UXL o1 : 2 words$word))) in
+ let m = (update_Mstatus_UPIE m ((bool_to_bits F : 1 words$word))) in
+ let m = (update_Mstatus_UIE m ((bool_to_bits F : 1 words$word))) in
+ sail2_state_monad$returnS m)))`;
+
+
+(*val cur_Architecture : unit -> M Architecture*)
+
+val _ = Define `
+ ((cur_Architecture:unit ->(regstate)sail2_state_monad$sequential_state ->(((Architecture),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (case w__0 of
+ Machine => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . sail2_state_monad$returnS ((get_Misa_MXL w__1 : 2 words$word)))
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . sail2_state_monad$returnS ((get_mstatus_SXL w__2 : 2 words$word)))
+ | User => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . sail2_state_monad$returnS ((get_mstatus_UXL w__3 : 2 words$word)))
+ ) (\ (a : arch_xlen) .
+ (case ((architecture a)) of
+ SOME (a) => sail2_state_monad$returnS a
+ | NONE => internal_error "Invalid current architecture"
+ )))))`;
+
+
+(*val in32BitMode : unit -> M bool*)
+
+val _ = Define `
+ ((in32BitMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) . sail2_state_monad$returnS (((w__0 = RV32))))))`;
+
+
+(*val Mk_Minterrupts : mword ty32 -> Minterrupts*)
+
+val _ = Define `
+ ((Mk_Minterrupts:(32)words$word -> Minterrupts) v=
+ (<| Minterrupts_Minterrupts_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Minterrupts_bits : Minterrupts -> mword ty32*)
+
+val _ = Define `
+ ((get_Minterrupts_bits:Minterrupts ->(32)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_bits:((regstate),(register_value),(Minterrupts))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_bits : Minterrupts -> mword ty32 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_bits:Minterrupts ->(32)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_UEI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_UEI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_UEI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_STI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_STI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_STI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_UTI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_UTI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_UTI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_USI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_USI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_USI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_USI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_USI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val legalize_mip : Minterrupts -> mword ty32 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_mip:Minterrupts ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (v : xlenbits)=
+ (let v = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v : 1 words$word))) in
+ let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in
+ let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))) in sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v : 1 words$word))) in
+ let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v : 1 words$word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v : 1 words$word))
+ else m))))`;
+
+
+(*val legalize_mie : Minterrupts -> mword ty32 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_mie:Minterrupts ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (v : xlenbits)=
+ (let v = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v : 1 words$word))) in
+ let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v : 1 words$word))) in
+ let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v : 1 words$word))) in
+ let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v : 1 words$word))) in
+ let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in
+ let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))) in sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v : 1 words$word))) in
+ let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v : 1 words$word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v : 1 words$word))
+ else m))))`;
+
+
+(*val legalize_mideleg : Minterrupts -> mword ty32 -> Minterrupts*)
+
+val _ = Define `
+ ((legalize_mideleg:Minterrupts ->(32)words$word -> Minterrupts) (o1 : Minterrupts) (v : xlenbits)=
+ (let m = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_MEI m ((bool_to_bits F : 1 words$word))) in
+ let m = (update_Minterrupts_MTI m ((bool_to_bits F : 1 words$word))) in
+ update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`;
+
+
+(*val Mk_Medeleg : mword ty32 -> Medeleg*)
+
+val _ = Define `
+ ((Mk_Medeleg:(32)words$word -> Medeleg) v=
+ (<| Medeleg_Medeleg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Medeleg_bits : Medeleg -> mword ty32*)
+
+val _ = Define `
+ ((get_Medeleg_bits:Medeleg ->(32)words$word) v= ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_bits:((regstate),(register_value),(Medeleg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_bits : Medeleg -> mword ty32 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_bits:Medeleg ->(32)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val legalize_medeleg : Medeleg -> mword ty32 -> Medeleg*)
+
+val _ = Define `
+ ((legalize_medeleg:Medeleg ->(32)words$word -> Medeleg) (o1 : Medeleg) (v : xlenbits)=
+ (let m = (Mk_Medeleg v) in
+ update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`;
+
+
+(*val Mk_Mtvec : mword ty32 -> Mtvec*)
+
+val _ = Define `
+ ((Mk_Mtvec:(32)words$word -> Mtvec) v= (<| Mtvec_Mtvec_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Mtvec_bits : Mtvec -> mword ty32*)
+
+val _ = Define `
+ ((get_Mtvec_bits:Mtvec ->(32)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_bits:((regstate),(register_value),(Mtvec))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_bits : Mtvec -> mword ty32 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_bits:Mtvec ->(32)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mtvec_Base : Mtvec -> mword ty30*)
+
+val _ = Define `
+ ((get_Mtvec_Base:Mtvec ->(30)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 2 : int):ii) : 30 words$word)))`;
+
+
+(*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty30 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(30)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 29 : int):ii) (( 0 : int):ii) : 30 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_Base : Mtvec -> mword ty30 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Base:Mtvec ->(30)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 31 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 29 : int):ii) (( 0 : int):ii) : 30 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mtvec_Mode : Mtvec -> mword ty2*)
+
+val _ = Define `
+ ((get_Mtvec_Mode:Mtvec ->(2)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_Satp32_Mode : Satp32 -> mword ty1 -> Satp32*)
+
+(*val _get_Satp32_Mode : Satp32 -> mword ty1*)
+
+(*val _set_Satp32_Mode : register_ref regstate register_value Satp32 -> mword ty1 -> M unit*)
+
+(*val legalize_tvec : Mtvec -> mword ty32 -> Mtvec*)
+
+val _ = Define `
+ ((legalize_tvec:Mtvec ->(32)words$word -> Mtvec) (o1 : Mtvec) (v : xlenbits)=
+ (let v = (Mk_Mtvec v) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v : 2 words$word)))) of
+ TV_Direct => v
+ | TV_Vector => v
+ | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 : 2 words$word))
+ )))`;
+
+
+(*val Mk_Mcause : mword ty32 -> Mcause*)
+
+val _ = Define `
+ ((Mk_Mcause:(32)words$word -> Mcause) v= (<| Mcause_Mcause_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Mcause_bits : Mcause -> mword ty32*)
+
+val _ = Define `
+ ((get_Mcause_bits:Mcause ->(32)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_bits:((regstate),(register_value),(Mcause))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_bits : Mcause -> mword ty32 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_bits:Mcause ->(32)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*)
+
+val _ = Define `
+ ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) v=
+ ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Mcause_Cause : Mcause -> mword ty31*)
+
+val _ = Define `
+ ((get_Mcause_Cause:Mcause ->(31)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)))`;
+
+
+(*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty31 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(31)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 30 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 30 : int):ii) (( 0 : int):ii) : 31 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_Cause : Mcause -> mword ty31 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_Cause:Mcause ->(31)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 30 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 30 : int):ii) (( 0 : int):ii) : 31 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((tvec_addr:Mtvec -> Mcause ->((32)words$word)option) (m : Mtvec) (c : Mcause)=
+ (let (base : xlenbits) =
+ ((concat_vec ((get_Mtvec_Base m : 30 words$word)) (vec_of_bits [B0;B0] : 2 words$word)
+ : 32 words$word)) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m : 2 words$word)))) of
+ TV_Direct => SOME base
+ | TV_Vector =>
+ if (((((get_Mcause_IsInterrupt c : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME ((add_vec base
+ ((shiftl ((EXTZ (( 32 : int):ii) ((get_Mcause_Cause c : 31 words$word)) : 32 words$word))
+ (( 2 : int):ii)
+ : 32 words$word))
+ : 32 words$word))
+ else SOME base
+ | TV_Reserved => NONE
+ )))`;
+
+
+(*val legalize_xepc : mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((legalize_xepc:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS
+ (sail2_state$or_boolS (sail2_state_monad$returnS ((sys_enable_writable_misa () )))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) (\ (w__1 :
+ bool) .
+ sail2_state_monad$returnS (if w__1 then (update_vec_dec v (( 0 : int):ii) B0 : 32 words$word)
+ else
+ (and_vec v ((EXTS (( 32 : int):ii) (vec_of_bits [B1;B0;B0] : 3 words$word) : 32 words$word))
+ : 32 words$word)))))`;
+
+
+(*val pc_alignment_mask : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((pc_alignment_mask:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS ((not_vec
+ ((EXTZ (( 32 : int):ii)
+ (if (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ (vec_of_bits [B0;B0] : 2 words$word)
+ else (vec_of_bits [B1;B0] : 2 words$word))
+ : 32 words$word))
+ : 32 words$word)))))`;
+
+
+(*val Mk_Counteren : mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((Mk_Counteren:(32)words$word -> Counteren) v=
+ (<| Counteren_Counteren_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Counteren_bits : Counteren -> mword ty32*)
+
+val _ = Define `
+ ((get_Counteren_bits:Counteren ->(32)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_bits:((regstate),(register_value),(Counteren))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_bits:Counteren ->(32)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_HPM : Counteren -> mword ty29*)
+
+val _ = Define `
+ ((get_Counteren_HPM:Counteren ->(29)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii) : 29 words$word)))`;
+
+
+(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_HPM:((regstate),(register_value),(Counteren))register_ref ->(29)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 28 : int):ii) (( 0 : int):ii) : 29 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_HPM:Counteren ->(29)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 28 : int):ii) (( 0 : int):ii) : 29 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_IR : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_IR:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_IR:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_IR:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_TM : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_TM:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_TM:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_TM:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_CY : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_CY:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_CY:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_CY:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val legalize_mcounteren : Counteren -> mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((legalize_mcounteren:Counteren ->(32)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in
+ let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`;
+
+
+(*val legalize_scounteren : Counteren -> mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((legalize_scounteren:Counteren ->(32)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in
+ let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`;
+
+
+(*val retire_instruction : unit -> M unit*)
+
+val _ = Define `
+ ((retire_instruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_written_ref) (\ (w__0 : bool) .
+ if (((w__0 = T))) then sail2_state_monad$write_regS minstret_written_ref F
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$write_regS minstret_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))))))`;
+
+
+(*val Mk_Sstatus : mword ty32 -> Sstatus*)
+
+val _ = Define `
+ ((Mk_Sstatus:(32)words$word -> Sstatus) v=
+ (<| Sstatus_Sstatus_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Sstatus_bits : Sstatus -> mword ty32*)
+
+val _ = Define `
+ ((get_Sstatus_bits:Sstatus ->(32)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_bits:((regstate),(register_value),(Sstatus))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_bits : Sstatus -> mword ty32 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_bits:Sstatus ->(32)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SD:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_MXR:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SUM:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_XS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_FS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPP:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Sstatus_UPIE : Sstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Sstatus_UPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Sstatus_UIE : Sstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Sstatus_UIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val get_sstatus_UXL : Sstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_sstatus_UXL:Sstatus ->(2)words$word) s=
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s : 32 words$word))) in
+ (get_mstatus_UXL m : 2 words$word)))`;
+
+
+(*val set_sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*)
+
+val _ = Define `
+ ((set_sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) (s : Sstatus) (a : arch_xlen)=
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s : 32 words$word))) in
+ let m = (set_mstatus_UXL m a) in
+ Mk_Sstatus ((get_Mstatus_bits m : 32 words$word))))`;
+
+
+(*val lower_mstatus : Mstatus -> Sstatus*)
+
+val _ = Define `
+ ((lower_mstatus:Mstatus -> Sstatus) m=
+ (let s = (Mk_Sstatus ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let s = (update_Sstatus_SD s ((get_Mstatus_SD m : 1 words$word))) in
+ let s = (set_sstatus_UXL s ((get_mstatus_UXL m : 2 words$word))) in
+ let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m : 1 words$word))) in
+ let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m : 1 words$word))) in
+ let s = (update_Sstatus_XS s ((get_Mstatus_XS m : 2 words$word))) in
+ let s = (update_Sstatus_FS s ((get_Mstatus_FS m : 2 words$word))) in
+ let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m : 1 words$word))) in
+ let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m : 1 words$word))) in
+ let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m : 1 words$word))) in
+ let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m : 1 words$word))) in
+ update_Sstatus_UIE s ((get_Mstatus_UIE m : 1 words$word))))`;
+
+
+(*val lift_sstatus : Mstatus -> Sstatus -> M Mstatus*)
+
+val _ = Define `
+ ((lift_sstatus:Mstatus -> Sstatus ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (s : Sstatus)=
+ (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in
+ let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in
+ let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in
+ let m = (update_Mstatus_FS m ((get_Sstatus_FS s : 2 words$word))) in sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_FS m : 2 words$word))) (\ (w__0 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__0 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_XS m : 2 words$word))) (\ (w__1 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__1 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) (\ (w__2 : bool) .
+ let m = (update_Mstatus_SD m ((bool_to_bits w__2 : 1 words$word))) in
+ let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s : 1 words$word))) in
+ let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s : 1 words$word))) in
+ let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s : 1 words$word))) in
+ let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s : 1 words$word))) in
+ let m = (update_Mstatus_UIE m ((get_Sstatus_UIE s : 1 words$word))) in
+ sail2_state_monad$returnS m)))`;
+
+
+(*val legalize_sstatus : Mstatus -> mword ty32 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_sstatus:Mstatus ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (v : xlenbits)= (lift_sstatus m ((Mk_Sstatus v))))`;
+
+
+(*val Mk_Sedeleg : mword ty32 -> Sedeleg*)
+
+val _ = Define `
+ ((Mk_Sedeleg:(32)words$word -> Sedeleg) v=
+ (<| Sedeleg_Sedeleg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Sedeleg_bits : Sedeleg -> mword ty32*)
+
+val _ = Define `
+ ((get_Sedeleg_bits:Sedeleg ->(32)words$word) v= ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Sedeleg_bits:((regstate),(register_value),(Sedeleg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sedeleg_bits : Sedeleg -> mword ty32 -> Sedeleg*)
+
+val _ = Define `
+ ((update_Sedeleg_bits:Sedeleg ->(32)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val legalize_sedeleg : Sedeleg -> mword ty32 -> Sedeleg*)
+
+val _ = Define `
+ ((legalize_sedeleg:Sedeleg ->(32)words$word -> Sedeleg) (s : Sedeleg) (v : xlenbits)=
+ (Mk_Sedeleg ((EXTZ (( 32 : int):ii) ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word)) : 32 words$word))))`;
+
+
+(*val Mk_Sinterrupts : mword ty32 -> Sinterrupts*)
+
+val _ = Define `
+ ((Mk_Sinterrupts:(32)words$word -> Sinterrupts) v=
+ (<| Sinterrupts_Sinterrupts_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty32*)
+
+val _ = Define `
+ ((get_Sinterrupts_bits:Sinterrupts ->(32)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_bits:((regstate),(register_value),(Sinterrupts))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty32 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_bits:Sinterrupts ->(32)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_USI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lower_mip:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)=
+ (let (s : Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lower_mie:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)=
+ (let (s : Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts*)
+
+val _ = Define `
+ ((lift_sip:Minterrupts -> Minterrupts -> Sinterrupts ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)=
+ (let (m : Minterrupts) = o1 in
+ let m =
+ (update_Minterrupts_SSI m
+ ((and_vec ((get_Sinterrupts_SSI s : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in sail2_state_monad$bindS
+ (haveNExt () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m =
+ (if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word))
+ else m) in
+ if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word))
+ else m
+ else m))))`;
+
+
+(*val legalize_sip : Minterrupts -> Minterrupts -> mword ty32 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_sip:Minterrupts -> Minterrupts ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
+ (lift_sip m d ((Mk_Sinterrupts v))))`;
+
+
+(*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts*)
+
+val _ = Define `
+ ((lift_sie:Minterrupts -> Minterrupts -> Sinterrupts ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)=
+ (let (m : Minterrupts) = o1 in
+ let m =
+ (if (((((get_Minterrupts_SEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_SEI m ((get_Sinterrupts_SEI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_STI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_STI m ((get_Sinterrupts_STI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_SSI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_SSI m ((get_Sinterrupts_SSI s : 1 words$word))
+ else m) in sail2_state_monad$bindS
+ (haveNExt () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m =
+ (if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UTI m ((get_Sinterrupts_UTI s : 1 words$word))
+ else m) in
+ if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word))
+ else m
+ else m))))`;
+
+
+(*val legalize_sie : Minterrupts -> Minterrupts -> mword ty32 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_sie:Minterrupts -> Minterrupts ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
+ (lift_sie m d ((Mk_Sinterrupts v))))`;
+
+
+(*val Mk_Satp64 : mword ty64 -> Satp64*)
+
+val _ = Define `
+ ((Mk_Satp64:(64)words$word -> Satp64) v= (<| Satp64_Satp64_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Satp64_bits : Satp64 -> mword ty64*)
+
+val _ = Define `
+ ((get_Satp64_bits:Satp64 ->(64)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_bits:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_bits:Satp64 ->(64)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Satp64_Mode : Satp64 -> mword ty4*)
+
+val _ = Define `
+ ((get_Satp64_Mode:Satp64 ->(4)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii) : 4 words$word)))`;
+
+
+(*val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+ ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii) : 4 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+ ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii) : 4 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Satp64_Asid : Satp64 -> mword ty16*)
+
+val _ = Define `
+ ((get_Satp64_Asid:Satp64 ->(16)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii) : 16 words$word)))`;
+
+
+(*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+ ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+ ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Satp32_Asid : Satp32 -> mword ty9 -> Satp32*)
+
+(*val _get_Satp32_Asid : Satp32 -> mword ty9*)
+
+(*val _set_Satp32_Asid : register_ref regstate register_value Satp32 -> mword ty9 -> M unit*)
+
+(*val _get_Satp64_PPN : Satp64 -> mword ty44*)
+
+val _ = Define `
+ ((get_Satp64_PPN:Satp64 ->(44)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Satp32_PPN : Satp32 -> mword ty22 -> Satp32*)
+
+(*val _get_Satp32_PPN : Satp32 -> mword ty22*)
+
+(*val _set_Satp32_PPN : register_ref regstate register_value Satp32 -> mword ty22 -> M unit*)
+
+(*val legalize_satp64 : Architecture -> mword ty64 -> mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((legalize_satp64:Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : Architecture) (o1 : 64 bits) (v : 64 bits)=
+ (let s = (Mk_Satp64 v) in
+ (case ((satp64Mode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of
+ NONE => o1
+ | SOME (Sv32) => o1
+ | SOME (_) => (get_Satp64_bits s : 64 words$word)
+ )))`;
+
+
+(*val Mk_Satp32 : mword ty32 -> Satp32*)
+
+val _ = Define `
+ ((Mk_Satp32:(32)words$word -> Satp32) v= (<| Satp32_Satp32_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Satp32_bits : Satp32 -> mword ty32*)
+
+val _ = Define `
+ ((get_Satp32_bits:Satp32 ->(32)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Satp32_bits : register_ref regstate register_value Satp32 -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Satp32_bits:((regstate),(register_value),(Satp32))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp32_bits : Satp32 -> mword ty32 -> Satp32*)
+
+val _ = Define `
+ ((update_Satp32_bits:Satp32 ->(32)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_Mode:Satp32 ->(1)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_Mode:((regstate),(register_value),(Satp32))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_Mode:Satp32 ->(1)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_Asid:Satp32 ->(9)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii) : 9 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_Asid:((regstate),(register_value),(Satp32))register_ref ->(9)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_Asid:Satp32 ->(9)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 8 : int):ii) (( 0 : int):ii) : 9 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_PPN:Satp32 ->(22)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii) : 22 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_PPN:((regstate),(register_value),(Satp32))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_PPN:Satp32 ->(22)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val legalize_satp32 : Architecture -> mword ty32 -> mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((legalize_satp32:Architecture ->(32)words$word ->(32)words$word ->(32)words$word) (a : Architecture) (o1 : 32 bits) (v : 32 bits)= v)`;
+
+
+(*val PmpAddrMatchType_of_num : integer -> PmpAddrMatchType*)
+
+val _ = Define `
+ ((PmpAddrMatchType_of_num:int -> PmpAddrMatchType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then OFF
+ else if (((p0_ = (( 1 : int):ii)))) then TOR
+ else if (((p0_ = (( 2 : int):ii)))) then NA4
+ else NAPOT))`;
+
+
+(*val num_of_PmpAddrMatchType : PmpAddrMatchType -> integer*)
+
+val _ = Define `
+ ((num_of_PmpAddrMatchType:PmpAddrMatchType -> int) arg_=
+ ((case arg_ of OFF => (( 0 : int):ii) | TOR => (( 1 : int):ii) | NA4 => (( 2 : int):ii) | NAPOT => (( 3 : int):ii) )))`;
+
+
+(*val pmpAddrMatchType_of_bits : mword ty2 -> M PmpAddrMatchType*)
+
+val _ = Define `
+ ((pmpAddrMatchType_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((PmpAddrMatchType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bs=
+ (let b__0 = bs in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS OFF
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS TOR
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS NA4
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS NAPOT
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpAddrMatchType_to_bits : PmpAddrMatchType -> mword ty2*)
+
+val _ = Define `
+ ((pmpAddrMatchType_to_bits:PmpAddrMatchType ->(2)words$word) bs=
+ ((case bs of
+ OFF => (vec_of_bits [B0;B0] : 2 words$word)
+ | TOR => (vec_of_bits [B0;B1] : 2 words$word)
+ | NA4 => (vec_of_bits [B1;B0] : 2 words$word)
+ | NAPOT => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val Mk_Pmpcfg_ent : mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((Mk_Pmpcfg_ent:(8)words$word -> Pmpcfg_ent) v=
+ (<| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) |>))`;
+
+
+(*val _get_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_bits:Pmpcfg_ent ->(8)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_bits : register_ref regstate register_value Pmpcfg_ent -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_bits:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_bits:Pmpcfg_ent ->(8)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Pmpcfg_ent_L:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Pmpcfg_ent_L:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Pmpcfg_ent_L:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_A:Pmpcfg_ent ->(2)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_A : register_ref regstate register_value Pmpcfg_ent -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_A:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_A:Pmpcfg_ent ->(2)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_X:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_X : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_X:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_X:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_W:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_W : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_W:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_W:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_R:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_R : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_R:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_R:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val pmpReadCfgReg : integer -> M (mword ty32)*)
+
+val _ = Define `
+ ((pmpReadCfgReg:int ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n=
+ (let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__3 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__0 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__1 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__2 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__3 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))))))
+ else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__7 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__4 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__5 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__6 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__7 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))))))
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__8 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__9 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__11 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__8 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__9 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__10 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__11 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))))))
+ else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__12 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__13 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__14 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__15 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))))))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpWriteCfg : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((pmpWriteCfg:Pmpcfg_ent ->(8)words$word -> Pmpcfg_ent) (cfg : Pmpcfg_ent) (v : 8 bits)=
+ (if (((((get_Pmpcfg_ent_L cfg : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then cfg
+ else Mk_Pmpcfg_ent v))`;
+
+
+(*val pmpWriteCfgReg : integer -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((pmpWriteCfgReg:int ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n v=
+ (let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp0cfg_ref ((pmpWriteCfg w__0 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp1cfg_ref)) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp1cfg_ref ((pmpWriteCfg w__1 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp2cfg_ref)) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp2cfg_ref ((pmpWriteCfg w__2 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp3cfg_ref)) (\ (w__3 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS pmp3cfg_ref ((pmpWriteCfg w__3 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word))))))))
+ else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp4cfg_ref ((pmpWriteCfg w__4 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp5cfg_ref)) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp5cfg_ref ((pmpWriteCfg w__5 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp6cfg_ref)) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp6cfg_ref ((pmpWriteCfg w__6 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp7cfg_ref)) (\ (w__7 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS pmp7cfg_ref ((pmpWriteCfg w__7 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word))))))))
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__8 : Pmpcfg_ent) .
+ let pmp8cfg8 = (pmpWriteCfg w__8 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__9 : Pmpcfg_ent) .
+ let pmp9cfg9 = (pmpWriteCfg w__9 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp10cfg_ref
+ ((pmpWriteCfg w__10 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp11cfg_ref)) (\ (w__11 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS
+ pmp11cfg_ref
+ ((pmpWriteCfg w__11 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word))))))))
+ else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp12cfg_ref ((pmpWriteCfg w__12 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp13cfg_ref)) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp13cfg_ref ((pmpWriteCfg w__13 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp14cfg_ref)) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp14cfg_ref
+ ((pmpWriteCfg w__14 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp15cfg_ref)) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS
+ pmp15cfg_ref
+ ((pmpWriteCfg w__15 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word))))))))
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpWriteAddr : Pmpcfg_ent -> mword ty32 -> mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((pmpWriteAddr:Pmpcfg_ent ->(32)words$word ->(32)words$word ->(32)words$word) (cfg : Pmpcfg_ent) (reg : xlenbits) (v : xlenbits)=
+ (if (((((get_Pmpcfg_ent_L cfg : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then reg
+ else v))`;
+
+
+(*val pmpAddrRange : Pmpcfg_ent -> mword ty32 -> mword ty32 -> M (maybe ((mword ty32 * mword ty32)))*)
+
+val _ = Define `
+ ((pmpAddrRange:Pmpcfg_ent ->(32)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((32)words$word#(32)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cfg : Pmpcfg_ent) (pmpaddr : xlenbits) (prev_pmpaddr : xlenbits)= (sail2_state_monad$bindS
+ (pmpAddrMatchType_of_bits ((get_Pmpcfg_ent_A cfg : 2 words$word))) (\ (w__0 : PmpAddrMatchType) .
+ sail2_state_monad$returnS ((case w__0 of
+ OFF => NONE
+ | TOR => SOME ((shiftl prev_pmpaddr (( 2 : int):ii) : 32 words$word), (shiftl pmpaddr (( 2 : int):ii) : 32 words$word))
+ | NA4 =>
+ let lo = ((shiftl pmpaddr (( 2 : int):ii) : 32 words$word)) in
+ SOME (lo, (add_vec_int lo (( 4 : int):ii) : 32 words$word))
+ | NAPOT =>
+ let mask = ((xor_vec pmpaddr ((add_vec_int pmpaddr (( 1 : int):ii) : 32 words$word)) : 32 words$word)) in
+ let lo = ((and_vec pmpaddr ((not_vec mask : 32 words$word)) : 32 words$word)) in
+ let len = ((add_vec_int mask (( 1 : int):ii) : 32 words$word)) in
+ SOME ((shiftl lo (( 2 : int):ii) : 32 words$word),
+ (shiftl ((add_vec lo len : 32 words$word)) (( 2 : int):ii) : 32 words$word))
+ )))))`;
+
+
+(*val pmpCheckRWX : Pmpcfg_ent -> AccessType -> bool*)
+
+val _ = Define `
+ ((pmpCheckRWX:Pmpcfg_ent -> AccessType -> bool) ent acc=
+ ((case acc of
+ Read => (((get_Pmpcfg_ent_R ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ | Write => (((get_Pmpcfg_ent_W ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ | ReadWrite =>
+ ((((((get_Pmpcfg_ent_R ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_Pmpcfg_ent_W ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ | Execute => (((get_Pmpcfg_ent_X ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ )))`;
+
+
+(*val pmpCheckPerms : Pmpcfg_ent -> AccessType -> Privilege -> bool*)
+
+val _ = Define `
+ ((pmpCheckPerms:Pmpcfg_ent -> AccessType -> Privilege -> bool) ent acc priv=
+ ((case priv of
+ Machine =>
+ if (((((get_Pmpcfg_ent_L ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ pmpCheckRWX ent acc
+ else T
+ | _ => pmpCheckRWX ent acc
+ )))`;
+
+
+(*val pmpAddrMatch_of_num : integer -> pmpAddrMatch*)
+
+val _ = Define `
+ ((pmpAddrMatch_of_num:int -> pmpAddrMatch) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PMP_NoMatch
+ else if (((p0_ = (( 1 : int):ii)))) then PMP_PartialMatch
+ else PMP_Match))`;
+
+
+(*val num_of_pmpAddrMatch : pmpAddrMatch -> integer*)
+
+val _ = Define `
+ ((num_of_pmpAddrMatch:pmpAddrMatch -> int) arg_=
+ ((case arg_ of PMP_NoMatch => (( 0 : int):ii) | PMP_PartialMatch => (( 1 : int):ii) | PMP_Match => (( 2 : int):ii) )))`;
+
+
+(*val pmpMatchAddr : mword ty32 -> mword ty32 -> maybe ((mword ty32 * mword ty32)) -> pmpAddrMatch*)
+
+val _ = Define `
+ ((pmpMatchAddr:(32)words$word ->(32)words$word ->(xlenbits#xlenbits)option -> pmpAddrMatch) (addr : xlenbits) (width : xlenbits) (rng : pmp_addr_range)=
+ ((case rng of
+ NONE => PMP_NoMatch
+ | SOME ((lo, hi)) =>
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if (((((zopz0zI_u ((add_vec addr width : 32 words$word)) lo)) \/ ((zopz0zI_u hi addr)))))
+ then
+ PMP_NoMatch
+ else if (((((zopz0zIzJ_u lo addr)) /\ ((zopz0zIzJ_u ((add_vec addr width : 32 words$word)) hi))))) then
+ PMP_Match
+ else PMP_PartialMatch
+ )))`;
+
+
+(*val pmpMatch_of_num : integer -> pmpMatch*)
+
+val _ = Define `
+ ((pmpMatch_of_num:int -> pmpMatch) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PMP_Success
+ else if (((p0_ = (( 1 : int):ii)))) then PMP_Continue
+ else PMP_Fail))`;
+
+
+(*val num_of_pmpMatch : pmpMatch -> integer*)
+
+val _ = Define `
+ ((num_of_pmpMatch:pmpMatch -> int) arg_=
+ ((case arg_ of PMP_Success => (( 0 : int):ii) | PMP_Continue => (( 1 : int):ii) | PMP_Fail => (( 2 : int):ii) )))`;
+
+
+(*val pmpMatchEntry : mword ty32 -> mword ty32 -> AccessType -> Privilege -> Pmpcfg_ent -> mword ty32 -> mword ty32 -> M pmpMatch*)
+
+val _ = Define `
+ ((pmpMatchEntry:(32)words$word ->(32)words$word -> AccessType -> Privilege -> Pmpcfg_ent ->(32)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((pmpMatch),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : xlenbits) (acc : AccessType) (priv : Privilege) (ent :
+ Pmpcfg_ent) (pmpaddr : xlenbits) (prev_pmpaddr : xlenbits)= (sail2_state_monad$bindS
+ (pmpAddrRange ent pmpaddr prev_pmpaddr : ( (( 32 words$word # 32 words$word))option) M) (\ rng .
+ sail2_state_monad$returnS ((case ((pmpMatchAddr addr width rng)) of
+ PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc priv)) then PMP_Success else PMP_Fail
+ )))))`;
+
+
+(*val pmpCheck : mword ty32 -> integer -> AccessType -> Privilege -> M (maybe ExceptionType)*)
+
+val _ = Define `
+ ((pmpCheck:(32)words$word -> int -> AccessType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->((((ExceptionType)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (acc : AccessType) (priv : Privilege)=
+ (let (width : xlenbits) = ((to_bits (( 32 : int):ii) width : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__0 w__1 ((zeros_implicit (( 32 : int):ii) : 32 words$word))) (\ (w__2 :
+ pmpMatch) . sail2_state_monad$bindS
+ (case w__2 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__3 w__4 w__5) (\ (w__6 : pmpMatch) .
+ (case w__6 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__7 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__7 w__8 w__9) (\ (w__10 : pmpMatch) .
+ (case w__10 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 32 words$word) M) (\ (w__13 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__11 w__12 w__13) (\ (w__14 : pmpMatch) .
+ (case w__14 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__15 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 32 words$word) M) (\ (w__16 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 32 words$word) M) (\ (w__17 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__15 w__16 w__17) (\ (w__18 : pmpMatch) .
+ (case w__18 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__19 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 32 words$word) M) (\ (w__20 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 32 words$word) M) (\ (w__21 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__19 w__20 w__21) (\ (w__22 : pmpMatch) .
+ (case w__22 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__23 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 32 words$word) M) (\ (w__24 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 32 words$word) M) (\ (w__25 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__23 w__24 w__25) (\ (w__26 : pmpMatch) .
+ (case w__26 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__27 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 32 words$word) M) (\ (w__28 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 32 words$word) M) (\ (w__29 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__27 w__28 w__29) (\ (w__30 :
+ pmpMatch) .
+ (case w__30 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__31 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 32 words$word) M) (\ (w__32 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 32 words$word) M) (\ (w__33 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__31 w__32 w__33) (\ (w__34 :
+ pmpMatch) .
+ (case w__34 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__35 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 32 words$word) M) (\ (w__36 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 32 words$word) M) (\ (w__37 : 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__35 w__36 w__37) (\ (w__38 :
+ pmpMatch) .
+ (case w__38 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__39 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 32 words$word) M) (\ (w__40 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 32 words$word) M) (\ (w__41 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__39 w__40 w__41) (\ (w__42 :
+ pmpMatch) .
+ (case w__42 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__43 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 32 words$word) M) (\ (w__44 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 32 words$word) M) (\ (w__45 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__43 w__44 w__45) (\ (w__46 :
+ pmpMatch) .
+ (case w__46 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__47 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 32 words$word) M) (\ (w__48 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 32 words$word) M) (\ (w__49 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__47 w__48 w__49) (\ (w__50 :
+ pmpMatch) .
+ (case w__50 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__51 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 32 words$word) M) (\ (w__52 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 32 words$word) M) (\ (w__53 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__51 w__52 w__53) (\ (w__54 :
+ pmpMatch) .
+ (case w__54 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__55 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 32 words$word) M) (\ (w__56 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 32 words$word) M) (\ (w__57 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__55 w__56 w__57) (\ (w__58 :
+ pmpMatch) .
+ (case w__58 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__59 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 32 words$word) M) (\ (w__60 :
+ 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 32 words$word) M) (\ (w__61 :
+ 32 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__59 w__60 w__61) (\ (w__62 :
+ pmpMatch) .
+ sail2_state_monad$returnS ((case w__62 of
+ PMP_Success => T
+ | PMP_Fail => F
+ | PMP_Continue =>
+ (case priv of
+ Machine => T
+ | _ => F
+ )
+ ))))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ ) (\ (check' : bool) .
+ sail2_state_monad$returnS (if check' then NONE
+ else
+ (case acc of
+ Read => SOME E_Load_Access_Fault
+ | Write => SOME E_SAMO_Access_Fault
+ | ReadWrite => SOME E_SAMO_Access_Fault
+ | Execute => SOME E_Fetch_Access_Fault
+ ))))))))`;
+
+
+(*val init_pmp : unit -> M unit*)
+
+val _ = Define `
+ ((init_pmp:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp0cfg_ref ((update_Pmpcfg_ent_A w__0 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp1cfg_ref)) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp1cfg_ref ((update_Pmpcfg_ent_A w__1 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp2cfg_ref)) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp2cfg_ref ((update_Pmpcfg_ent_A w__2 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp3cfg_ref)) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp3cfg_ref ((update_Pmpcfg_ent_A w__3 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp4cfg_ref)) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp4cfg_ref ((update_Pmpcfg_ent_A w__4 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp5cfg_ref)) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp5cfg_ref ((update_Pmpcfg_ent_A w__5 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp6cfg_ref)) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp6cfg_ref ((update_Pmpcfg_ent_A w__6 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp7cfg_ref)) (\ (w__7 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp7cfg_ref ((update_Pmpcfg_ent_A w__7 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp8cfg_ref)) (\ (w__8 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp8cfg_ref ((update_Pmpcfg_ent_A w__8 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp9cfg_ref)) (\ (w__9 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp9cfg_ref ((update_Pmpcfg_ent_A w__9 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp10cfg_ref)) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp10cfg_ref
+ ((update_Pmpcfg_ent_A w__10 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp11cfg_ref)) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp11cfg_ref
+ ((update_Pmpcfg_ent_A w__11 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp12cfg_ref)) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp12cfg_ref
+ ((update_Pmpcfg_ent_A w__12 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp13cfg_ref)) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp13cfg_ref
+ ((update_Pmpcfg_ent_A w__13 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp14cfg_ref)) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp14cfg_ref
+ ((update_Pmpcfg_ent_A w__14 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp15cfg_ref)) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS
+ pmp15cfg_ref
+ ((update_Pmpcfg_ent_A w__15 ((pmpAddrMatchType_to_bits OFF : 2 words$word))))))))))))))))))))))`;
+
+
+(*val ext_init_regs : unit -> M unit*)
+
+val _ = Define `
+ ((ext_init_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`;
+
+
+(*
+This function is called after above when running rvfi and allows the model
+to be initialised differently (e.g. CHERI cap regs are initialised
+to omnipotent instead of null).
+ *)
+(*val ext_rvfi_init : unit -> M unit*)
+
+val _ = Define `
+ ((ext_rvfi_init:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`;
+
+
+(*val ext_fetch_check_pc : mword ty32 -> mword ty32 -> Ext_FetchAddr_Check unit*)
+
+val _ = Define `
+ ((ext_fetch_check_pc:(32)words$word ->(32)words$word ->(unit)Ext_FetchAddr_Check) (start_pc : xlenbits) (pc : xlenbits)= (Ext_FetchAddr_OK pc))`;
+
+
+(*val ext_handle_fetch_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_fetch_check_error:unit -> unit) err= () )`;
+
+
+(*val ext_control_check_addr : mword ty32 -> Ext_ControlAddr_Check unit*)
+
+val _ = Define `
+ ((ext_control_check_addr:(32)words$word ->(unit)Ext_ControlAddr_Check) pc= (Ext_ControlAddr_OK pc))`;
+
+
+(*val ext_control_check_pc : mword ty32 -> Ext_ControlAddr_Check unit*)
+
+val _ = Define `
+ ((ext_control_check_pc:(32)words$word ->(unit)Ext_ControlAddr_Check) pc= (Ext_ControlAddr_OK pc))`;
+
+
+(*val ext_handle_control_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_control_check_error:unit -> unit) err= () )`;
+
+
+(*val ext_data_get_addr : mword ty5 -> mword ty32 -> AccessType -> word_width -> M (Ext_DataAddr_Check unit)*)
+
+val _ = Define `
+ ((ext_data_get_addr:(5)words$word ->(32)words$word -> AccessType -> word_width ->(regstate)sail2_state_monad$sequential_state ->((((unit)Ext_DataAddr_Check),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (base : regidx) (offset : xlenbits) (acc : AccessType) (width : word_width)= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno base)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let addr = ((add_vec w__0 offset : 32 words$word)) in
+ sail2_state_monad$returnS (Ext_DataAddr_OK addr))))`;
+
+
+(*val ext_handle_data_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_data_check_error:unit -> unit) err= () )`;
+
+
+(*val csr_name : mword ty12 -> string*)
+
+val _ = Define `
+ ((csr_name:(12)words$word -> string) csr=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "ustatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "uie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "utvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "uscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "uepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "ucause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "utval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "uip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "fflags"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "frm"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "fcsr"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "cycle"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "time"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "instret"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "cycleh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "timeh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "instreth"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "sstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "sedeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "sideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "sie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "stvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ "scounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "sscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "sepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "scause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "stval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "sip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "satp"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ "mvendorid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ "marchid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ "mimpid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ "mhartid"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "misa"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "medeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "mideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "mie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "mtvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ "mcounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "mepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "mcause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "mtval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "mip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "pmpcfg0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ "pmpaddr0"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mcycle"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "minstret"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mcycleh"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "minstreth"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "tselect"
+ else "UNKNOWN"))`;
+
+
+(*val csr_name_map_forwards : mword ty12 -> M string*)
+
+val _ = Define `
+ ((csr_name_map_forwards:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "ustatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "utvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "uepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "ucause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "utval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "fflags"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "frm"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "fcsr"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "cycle"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "time"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "instret"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "cycleh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "timeh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "instreth"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sedeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "sideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "stvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "scounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "sepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "scause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "stval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "satp"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mvendorid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "marchid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mimpid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mhartid"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "misa"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "medeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mtvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mtval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg1"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg2"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg3"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr1"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr2"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr3"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr4"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr5"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr6"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr7"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr8"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr9"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr10"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr11"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr12"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr13"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr14"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr15"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcycle"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "minstret"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcycleh"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "minstreth"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "tselect"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata1"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata2"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata3"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_name_map_backwards : string -> M (mword ty12)*)
+
+val _ = Define `
+ ((csr_name_map_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((12)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "ustatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "uie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "utvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "uscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "uepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "ucause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "utval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "uip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "fflags"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "frm"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "fcsr"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "cycle"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "time"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "instret"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "cycleh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "timeh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "instreth"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "sstatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "sedeleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "sideleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "sie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "stvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "scounteren"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "sscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "sepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "scause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "stval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "sip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "satp"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "mvendorid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "marchid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mimpid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mhartid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "mstatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "misa"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "medeleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mideleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "mtvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "mcounteren"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "mscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "mepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "mcause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mtval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg0"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpcfg2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr0"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr4"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr5"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr6"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr7"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr8"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr9"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr10"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr11"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr12"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr13"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr14"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr15"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)
+ else if (((p0_ = "mcycle"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "minstret"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mcycleh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "minstreth"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "tselect"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "tdata1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "tdata2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "tdata3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_name_map_forwards_matches : mword ty12 -> bool*)
+
+val _ = Define `
+ ((csr_name_map_forwards_matches:(12)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else F))`;
+
+
+(*val csr_name_map_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((csr_name_map_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "ustatus"))) then T
+ else if (((p0_ = "uie"))) then T
+ else if (((p0_ = "utvec"))) then T
+ else if (((p0_ = "uscratch"))) then T
+ else if (((p0_ = "uepc"))) then T
+ else if (((p0_ = "ucause"))) then T
+ else if (((p0_ = "utval"))) then T
+ else if (((p0_ = "uip"))) then T
+ else if (((p0_ = "fflags"))) then T
+ else if (((p0_ = "frm"))) then T
+ else if (((p0_ = "fcsr"))) then T
+ else if (((p0_ = "cycle"))) then T
+ else if (((p0_ = "time"))) then T
+ else if (((p0_ = "instret"))) then T
+ else if (((p0_ = "cycleh"))) then T
+ else if (((p0_ = "timeh"))) then T
+ else if (((p0_ = "instreth"))) then T
+ else if (((p0_ = "sstatus"))) then T
+ else if (((p0_ = "sedeleg"))) then T
+ else if (((p0_ = "sideleg"))) then T
+ else if (((p0_ = "sie"))) then T
+ else if (((p0_ = "stvec"))) then T
+ else if (((p0_ = "scounteren"))) then T
+ else if (((p0_ = "sscratch"))) then T
+ else if (((p0_ = "sepc"))) then T
+ else if (((p0_ = "scause"))) then T
+ else if (((p0_ = "stval"))) then T
+ else if (((p0_ = "sip"))) then T
+ else if (((p0_ = "satp"))) then T
+ else if (((p0_ = "mvendorid"))) then T
+ else if (((p0_ = "marchid"))) then T
+ else if (((p0_ = "mimpid"))) then T
+ else if (((p0_ = "mhartid"))) then T
+ else if (((p0_ = "mstatus"))) then T
+ else if (((p0_ = "misa"))) then T
+ else if (((p0_ = "medeleg"))) then T
+ else if (((p0_ = "mideleg"))) then T
+ else if (((p0_ = "mie"))) then T
+ else if (((p0_ = "mtvec"))) then T
+ else if (((p0_ = "mcounteren"))) then T
+ else if (((p0_ = "mscratch"))) then T
+ else if (((p0_ = "mepc"))) then T
+ else if (((p0_ = "mcause"))) then T
+ else if (((p0_ = "mtval"))) then T
+ else if (((p0_ = "mip"))) then T
+ else if (((p0_ = "pmpcfg0"))) then T
+ else if (((p0_ = "pmpcfg1"))) then T
+ else if (((p0_ = "pmpcfg2"))) then T
+ else if (((p0_ = "pmpcfg3"))) then T
+ else if (((p0_ = "pmpaddr0"))) then T
+ else if (((p0_ = "pmpaddr1"))) then T
+ else if (((p0_ = "pmpaddr2"))) then T
+ else if (((p0_ = "pmpaddr3"))) then T
+ else if (((p0_ = "pmpaddr4"))) then T
+ else if (((p0_ = "pmpaddr5"))) then T
+ else if (((p0_ = "pmpaddr6"))) then T
+ else if (((p0_ = "pmpaddr7"))) then T
+ else if (((p0_ = "pmpaddr8"))) then T
+ else if (((p0_ = "pmpaddr9"))) then T
+ else if (((p0_ = "pmpaddr10"))) then T
+ else if (((p0_ = "pmpaddr11"))) then T
+ else if (((p0_ = "pmpaddr12"))) then T
+ else if (((p0_ = "pmpaddr13"))) then T
+ else if (((p0_ = "pmpaddr14"))) then T
+ else if (((p0_ = "pmpaddr15"))) then T
+ else if (((p0_ = "mcycle"))) then T
+ else if (((p0_ = "minstret"))) then T
+ else if (((p0_ = "mcycleh"))) then T
+ else if (((p0_ = "minstreth"))) then T
+ else if (((p0_ = "tselect"))) then T
+ else if (((p0_ = "tdata1"))) then T
+ else if (((p0_ = "tdata2"))) then T
+ else if (((p0_ = "tdata3"))) then T
+ else F))`;
+
+
+(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*)
+
+(*val _s488_ : string -> maybe string*)
+
+val _ = Define `
+ ((s488_:string ->(string)option) s489_0=
+ (let s490_0 = s489_0 in
+ if ((string_startswith s490_0 "tdata3")) then
+ (case ((string_drop s490_0 ((string_length "tdata3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s484_ : string -> maybe string*)
+
+val _ = Define `
+ ((s484_:string ->(string)option) s485_0=
+ (let s486_0 = s485_0 in
+ if ((string_startswith s486_0 "tdata2")) then
+ (case ((string_drop s486_0 ((string_length "tdata2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s480_ : string -> maybe string*)
+
+val _ = Define `
+ ((s480_:string ->(string)option) s481_0=
+ (let s482_0 = s481_0 in
+ if ((string_startswith s482_0 "tdata1")) then
+ (case ((string_drop s482_0 ((string_length "tdata1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s476_ : string -> maybe string*)
+
+val _ = Define `
+ ((s476_:string ->(string)option) s477_0=
+ (let s478_0 = s477_0 in
+ if ((string_startswith s478_0 "tselect")) then
+ (case ((string_drop s478_0 ((string_length "tselect")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s472_ : string -> maybe string*)
+
+val _ = Define `
+ ((s472_:string ->(string)option) s473_0=
+ (let s474_0 = s473_0 in
+ if ((string_startswith s474_0 "minstreth")) then
+ (case ((string_drop s474_0 ((string_length "minstreth")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s468_ : string -> maybe string*)
+
+val _ = Define `
+ ((s468_:string ->(string)option) s469_0=
+ (let s470_0 = s469_0 in
+ if ((string_startswith s470_0 "mcycleh")) then
+ (case ((string_drop s470_0 ((string_length "mcycleh")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s464_ : string -> maybe string*)
+
+val _ = Define `
+ ((s464_:string ->(string)option) s465_0=
+ (let s466_0 = s465_0 in
+ if ((string_startswith s466_0 "minstret")) then
+ (case ((string_drop s466_0 ((string_length "minstret")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s460_ : string -> maybe string*)
+
+val _ = Define `
+ ((s460_:string ->(string)option) s461_0=
+ (let s462_0 = s461_0 in
+ if ((string_startswith s462_0 "mcycle")) then
+ (case ((string_drop s462_0 ((string_length "mcycle")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s456_ : string -> maybe string*)
+
+val _ = Define `
+ ((s456_:string ->(string)option) s457_0=
+ (let s458_0 = s457_0 in
+ if ((string_startswith s458_0 "pmpaddr15")) then
+ (case ((string_drop s458_0 ((string_length "pmpaddr15")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s452_ : string -> maybe string*)
+
+val _ = Define `
+ ((s452_:string ->(string)option) s453_0=
+ (let s454_0 = s453_0 in
+ if ((string_startswith s454_0 "pmpaddr14")) then
+ (case ((string_drop s454_0 ((string_length "pmpaddr14")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s448_ : string -> maybe string*)
+
+val _ = Define `
+ ((s448_:string ->(string)option) s449_0=
+ (let s450_0 = s449_0 in
+ if ((string_startswith s450_0 "pmpaddr13")) then
+ (case ((string_drop s450_0 ((string_length "pmpaddr13")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s444_ : string -> maybe string*)
+
+val _ = Define `
+ ((s444_:string ->(string)option) s445_0=
+ (let s446_0 = s445_0 in
+ if ((string_startswith s446_0 "pmpaddr12")) then
+ (case ((string_drop s446_0 ((string_length "pmpaddr12")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s440_ : string -> maybe string*)
+
+val _ = Define `
+ ((s440_:string ->(string)option) s441_0=
+ (let s442_0 = s441_0 in
+ if ((string_startswith s442_0 "pmpaddr11")) then
+ (case ((string_drop s442_0 ((string_length "pmpaddr11")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s436_ : string -> maybe string*)
+
+val _ = Define `
+ ((s436_:string ->(string)option) s437_0=
+ (let s438_0 = s437_0 in
+ if ((string_startswith s438_0 "pmpaddr10")) then
+ (case ((string_drop s438_0 ((string_length "pmpaddr10")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s432_ : string -> maybe string*)
+
+val _ = Define `
+ ((s432_:string ->(string)option) s433_0=
+ (let s434_0 = s433_0 in
+ if ((string_startswith s434_0 "pmpaddr9")) then
+ (case ((string_drop s434_0 ((string_length "pmpaddr9")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s428_ : string -> maybe string*)
+
+val _ = Define `
+ ((s428_:string ->(string)option) s429_0=
+ (let s430_0 = s429_0 in
+ if ((string_startswith s430_0 "pmpaddr8")) then
+ (case ((string_drop s430_0 ((string_length "pmpaddr8")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s424_ : string -> maybe string*)
+
+val _ = Define `
+ ((s424_:string ->(string)option) s425_0=
+ (let s426_0 = s425_0 in
+ if ((string_startswith s426_0 "pmpaddr7")) then
+ (case ((string_drop s426_0 ((string_length "pmpaddr7")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s420_ : string -> maybe string*)
+
+val _ = Define `
+ ((s420_:string ->(string)option) s421_0=
+ (let s422_0 = s421_0 in
+ if ((string_startswith s422_0 "pmpaddr6")) then
+ (case ((string_drop s422_0 ((string_length "pmpaddr6")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s416_ : string -> maybe string*)
+
+val _ = Define `
+ ((s416_:string ->(string)option) s417_0=
+ (let s418_0 = s417_0 in
+ if ((string_startswith s418_0 "pmpaddr5")) then
+ (case ((string_drop s418_0 ((string_length "pmpaddr5")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s412_ : string -> maybe string*)
+
+val _ = Define `
+ ((s412_:string ->(string)option) s413_0=
+ (let s414_0 = s413_0 in
+ if ((string_startswith s414_0 "pmpaddr4")) then
+ (case ((string_drop s414_0 ((string_length "pmpaddr4")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s408_ : string -> maybe string*)
+
+val _ = Define `
+ ((s408_:string ->(string)option) s409_0=
+ (let s410_0 = s409_0 in
+ if ((string_startswith s410_0 "pmpaddr3")) then
+ (case ((string_drop s410_0 ((string_length "pmpaddr3")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s404_ : string -> maybe string*)
+
+val _ = Define `
+ ((s404_:string ->(string)option) s405_0=
+ (let s406_0 = s405_0 in
+ if ((string_startswith s406_0 "pmpaddr2")) then
+ (case ((string_drop s406_0 ((string_length "pmpaddr2")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s400_ : string -> maybe string*)
+
+val _ = Define `
+ ((s400_:string ->(string)option) s401_0=
+ (let s402_0 = s401_0 in
+ if ((string_startswith s402_0 "pmpaddr1")) then
+ (case ((string_drop s402_0 ((string_length "pmpaddr1")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s396_ : string -> maybe string*)
+
+val _ = Define `
+ ((s396_:string ->(string)option) s397_0=
+ (let s398_0 = s397_0 in
+ if ((string_startswith s398_0 "pmpaddr0")) then
+ (case ((string_drop s398_0 ((string_length "pmpaddr0")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s392_ : string -> maybe string*)
+
+val _ = Define `
+ ((s392_:string ->(string)option) s393_0=
+ (let s394_0 = s393_0 in
+ if ((string_startswith s394_0 "pmpcfg3")) then
+ (case ((string_drop s394_0 ((string_length "pmpcfg3")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s388_ : string -> maybe string*)
+
+val _ = Define `
+ ((s388_:string ->(string)option) s389_0=
+ (let s390_0 = s389_0 in
+ if ((string_startswith s390_0 "pmpcfg2")) then
+ (case ((string_drop s390_0 ((string_length "pmpcfg2")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s384_ : string -> maybe string*)
+
+val _ = Define `
+ ((s384_:string ->(string)option) s385_0=
+ (let s386_0 = s385_0 in
+ if ((string_startswith s386_0 "pmpcfg1")) then
+ (case ((string_drop s386_0 ((string_length "pmpcfg1")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s380_ : string -> maybe string*)
+
+val _ = Define `
+ ((s380_:string ->(string)option) s381_0=
+ (let s382_0 = s381_0 in
+ if ((string_startswith s382_0 "pmpcfg0")) then
+ (case ((string_drop s382_0 ((string_length "pmpcfg0")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s376_ : string -> maybe string*)
+
+val _ = Define `
+ ((s376_:string ->(string)option) s377_0=
+ (let s378_0 = s377_0 in
+ if ((string_startswith s378_0 "mip")) then
+ (case ((string_drop s378_0 ((string_length "mip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s372_ : string -> maybe string*)
+
+val _ = Define `
+ ((s372_:string ->(string)option) s373_0=
+ (let s374_0 = s373_0 in
+ if ((string_startswith s374_0 "mtval")) then
+ (case ((string_drop s374_0 ((string_length "mtval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s368_ : string -> maybe string*)
+
+val _ = Define `
+ ((s368_:string ->(string)option) s369_0=
+ (let s370_0 = s369_0 in
+ if ((string_startswith s370_0 "mcause")) then
+ (case ((string_drop s370_0 ((string_length "mcause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s364_ : string -> maybe string*)
+
+val _ = Define `
+ ((s364_:string ->(string)option) s365_0=
+ (let s366_0 = s365_0 in
+ if ((string_startswith s366_0 "mepc")) then
+ (case ((string_drop s366_0 ((string_length "mepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s360_ : string -> maybe string*)
+
+val _ = Define `
+ ((s360_:string ->(string)option) s361_0=
+ (let s362_0 = s361_0 in
+ if ((string_startswith s362_0 "mscratch")) then
+ (case ((string_drop s362_0 ((string_length "mscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s356_ : string -> maybe string*)
+
+val _ = Define `
+ ((s356_:string ->(string)option) s357_0=
+ (let s358_0 = s357_0 in
+ if ((string_startswith s358_0 "mcounteren")) then
+ (case ((string_drop s358_0 ((string_length "mcounteren")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s352_ : string -> maybe string*)
+
+val _ = Define `
+ ((s352_:string ->(string)option) s353_0=
+ (let s354_0 = s353_0 in
+ if ((string_startswith s354_0 "mtvec")) then
+ (case ((string_drop s354_0 ((string_length "mtvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s348_ : string -> maybe string*)
+
+val _ = Define `
+ ((s348_:string ->(string)option) s349_0=
+ (let s350_0 = s349_0 in
+ if ((string_startswith s350_0 "mie")) then
+ (case ((string_drop s350_0 ((string_length "mie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s344_ : string -> maybe string*)
+
+val _ = Define `
+ ((s344_:string ->(string)option) s345_0=
+ (let s346_0 = s345_0 in
+ if ((string_startswith s346_0 "mideleg")) then
+ (case ((string_drop s346_0 ((string_length "mideleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s340_ : string -> maybe string*)
+
+val _ = Define `
+ ((s340_:string ->(string)option) s341_0=
+ (let s342_0 = s341_0 in
+ if ((string_startswith s342_0 "medeleg")) then
+ (case ((string_drop s342_0 ((string_length "medeleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s336_ : string -> maybe string*)
+
+val _ = Define `
+ ((s336_:string ->(string)option) s337_0=
+ (let s338_0 = s337_0 in
+ if ((string_startswith s338_0 "misa")) then
+ (case ((string_drop s338_0 ((string_length "misa")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s332_ : string -> maybe string*)
+
+val _ = Define `
+ ((s332_:string ->(string)option) s333_0=
+ (let s334_0 = s333_0 in
+ if ((string_startswith s334_0 "mstatus")) then
+ (case ((string_drop s334_0 ((string_length "mstatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s328_ : string -> maybe string*)
+
+val _ = Define `
+ ((s328_:string ->(string)option) s329_0=
+ (let s330_0 = s329_0 in
+ if ((string_startswith s330_0 "mhartid")) then
+ (case ((string_drop s330_0 ((string_length "mhartid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s324_ : string -> maybe string*)
+
+val _ = Define `
+ ((s324_:string ->(string)option) s325_0=
+ (let s326_0 = s325_0 in
+ if ((string_startswith s326_0 "mimpid")) then
+ (case ((string_drop s326_0 ((string_length "mimpid")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s320_ : string -> maybe string*)
+
+val _ = Define `
+ ((s320_:string ->(string)option) s321_0=
+ (let s322_0 = s321_0 in
+ if ((string_startswith s322_0 "marchid")) then
+ (case ((string_drop s322_0 ((string_length "marchid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s316_ : string -> maybe string*)
+
+val _ = Define `
+ ((s316_:string ->(string)option) s317_0=
+ (let s318_0 = s317_0 in
+ if ((string_startswith s318_0 "mvendorid")) then
+ (case ((string_drop s318_0 ((string_length "mvendorid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s312_ : string -> maybe string*)
+
+val _ = Define `
+ ((s312_:string ->(string)option) s313_0=
+ (let s314_0 = s313_0 in
+ if ((string_startswith s314_0 "satp")) then
+ (case ((string_drop s314_0 ((string_length "satp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s308_ : string -> maybe string*)
+
+val _ = Define `
+ ((s308_:string ->(string)option) s309_0=
+ (let s310_0 = s309_0 in
+ if ((string_startswith s310_0 "sip")) then
+ (case ((string_drop s310_0 ((string_length "sip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s304_ : string -> maybe string*)
+
+val _ = Define `
+ ((s304_:string ->(string)option) s305_0=
+ (let s306_0 = s305_0 in
+ if ((string_startswith s306_0 "stval")) then
+ (case ((string_drop s306_0 ((string_length "stval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s300_ : string -> maybe string*)
+
+val _ = Define `
+ ((s300_:string ->(string)option) s301_0=
+ (let s302_0 = s301_0 in
+ if ((string_startswith s302_0 "scause")) then
+ (case ((string_drop s302_0 ((string_length "scause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s296_ : string -> maybe string*)
+
+val _ = Define `
+ ((s296_:string ->(string)option) s297_0=
+ (let s298_0 = s297_0 in
+ if ((string_startswith s298_0 "sepc")) then
+ (case ((string_drop s298_0 ((string_length "sepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s292_ : string -> maybe string*)
+
+val _ = Define `
+ ((s292_:string ->(string)option) s293_0=
+ (let s294_0 = s293_0 in
+ if ((string_startswith s294_0 "sscratch")) then
+ (case ((string_drop s294_0 ((string_length "sscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s288_ : string -> maybe string*)
+
+val _ = Define `
+ ((s288_:string ->(string)option) s289_0=
+ (let s290_0 = s289_0 in
+ if ((string_startswith s290_0 "scounteren")) then
+ (case ((string_drop s290_0 ((string_length "scounteren")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s284_ : string -> maybe string*)
+
+val _ = Define `
+ ((s284_:string ->(string)option) s285_0=
+ (let s286_0 = s285_0 in
+ if ((string_startswith s286_0 "stvec")) then
+ (case ((string_drop s286_0 ((string_length "stvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s280_ : string -> maybe string*)
+
+val _ = Define `
+ ((s280_:string ->(string)option) s281_0=
+ (let s282_0 = s281_0 in
+ if ((string_startswith s282_0 "sie")) then
+ (case ((string_drop s282_0 ((string_length "sie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s276_ : string -> maybe string*)
+
+val _ = Define `
+ ((s276_:string ->(string)option) s277_0=
+ (let s278_0 = s277_0 in
+ if ((string_startswith s278_0 "sideleg")) then
+ (case ((string_drop s278_0 ((string_length "sideleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s272_ : string -> maybe string*)
+
+val _ = Define `
+ ((s272_:string ->(string)option) s273_0=
+ (let s274_0 = s273_0 in
+ if ((string_startswith s274_0 "sedeleg")) then
+ (case ((string_drop s274_0 ((string_length "sedeleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s268_ : string -> maybe string*)
+
+val _ = Define `
+ ((s268_:string ->(string)option) s269_0=
+ (let s270_0 = s269_0 in
+ if ((string_startswith s270_0 "sstatus")) then
+ (case ((string_drop s270_0 ((string_length "sstatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s264_ : string -> maybe string*)
+
+val _ = Define `
+ ((s264_:string ->(string)option) s265_0=
+ (let s266_0 = s265_0 in
+ if ((string_startswith s266_0 "instreth")) then
+ (case ((string_drop s266_0 ((string_length "instreth")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s260_ : string -> maybe string*)
+
+val _ = Define `
+ ((s260_:string ->(string)option) s261_0=
+ (let s262_0 = s261_0 in
+ if ((string_startswith s262_0 "timeh")) then
+ (case ((string_drop s262_0 ((string_length "timeh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s256_ : string -> maybe string*)
+
+val _ = Define `
+ ((s256_:string ->(string)option) s257_0=
+ (let s258_0 = s257_0 in
+ if ((string_startswith s258_0 "cycleh")) then
+ (case ((string_drop s258_0 ((string_length "cycleh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s252_ : string -> maybe string*)
+
+val _ = Define `
+ ((s252_:string ->(string)option) s253_0=
+ (let s254_0 = s253_0 in
+ if ((string_startswith s254_0 "instret")) then
+ (case ((string_drop s254_0 ((string_length "instret")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s248_ : string -> maybe string*)
+
+val _ = Define `
+ ((s248_:string ->(string)option) s249_0=
+ (let s250_0 = s249_0 in
+ if ((string_startswith s250_0 "time")) then
+ (case ((string_drop s250_0 ((string_length "time")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s244_ : string -> maybe string*)
+
+val _ = Define `
+ ((s244_:string ->(string)option) s245_0=
+ (let s246_0 = s245_0 in
+ if ((string_startswith s246_0 "cycle")) then
+ (case ((string_drop s246_0 ((string_length "cycle")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s240_ : string -> maybe string*)
+
+val _ = Define `
+ ((s240_:string ->(string)option) s241_0=
+ (let s242_0 = s241_0 in
+ if ((string_startswith s242_0 "fcsr")) then
+ (case ((string_drop s242_0 ((string_length "fcsr")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s236_ : string -> maybe string*)
+
+val _ = Define `
+ ((s236_:string ->(string)option) s237_0=
+ (let s238_0 = s237_0 in
+ if ((string_startswith s238_0 "frm")) then
+ (case ((string_drop s238_0 ((string_length "frm")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s232_ : string -> maybe string*)
+
+val _ = Define `
+ ((s232_:string ->(string)option) s233_0=
+ (let s234_0 = s233_0 in
+ if ((string_startswith s234_0 "fflags")) then
+ (case ((string_drop s234_0 ((string_length "fflags")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s228_ : string -> maybe string*)
+
+val _ = Define `
+ ((s228_:string ->(string)option) s229_0=
+ (let s230_0 = s229_0 in
+ if ((string_startswith s230_0 "uip")) then
+ (case ((string_drop s230_0 ((string_length "uip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s224_ : string -> maybe string*)
+
+val _ = Define `
+ ((s224_:string ->(string)option) s225_0=
+ (let s226_0 = s225_0 in
+ if ((string_startswith s226_0 "utval")) then
+ (case ((string_drop s226_0 ((string_length "utval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s220_ : string -> maybe string*)
+
+val _ = Define `
+ ((s220_:string ->(string)option) s221_0=
+ (let s222_0 = s221_0 in
+ if ((string_startswith s222_0 "ucause")) then
+ (case ((string_drop s222_0 ((string_length "ucause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s216_ : string -> maybe string*)
+
+val _ = Define `
+ ((s216_:string ->(string)option) s217_0=
+ (let s218_0 = s217_0 in
+ if ((string_startswith s218_0 "uepc")) then
+ (case ((string_drop s218_0 ((string_length "uepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s212_ : string -> maybe string*)
+
+val _ = Define `
+ ((s212_:string ->(string)option) s213_0=
+ (let s214_0 = s213_0 in
+ if ((string_startswith s214_0 "uscratch")) then
+ (case ((string_drop s214_0 ((string_length "uscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s208_ : string -> maybe string*)
+
+val _ = Define `
+ ((s208_:string ->(string)option) s209_0=
+ (let s210_0 = s209_0 in
+ if ((string_startswith s210_0 "utvec")) then
+ (case ((string_drop s210_0 ((string_length "utvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s204_ : string -> maybe string*)
+
+val _ = Define `
+ ((s204_:string ->(string)option) s205_0=
+ (let s206_0 = s205_0 in
+ if ((string_startswith s206_0 "uie")) then
+ (case ((string_drop s206_0 ((string_length "uie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s200_ : string -> maybe string*)
+
+val _ = Define `
+ ((s200_:string ->(string)option) s201_0=
+ (let s202_0 = s201_0 in
+ if ((string_startswith s202_0 "ustatus")) then
+ (case ((string_drop s202_0 ((string_length "ustatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((csr_name_map_matches_prefix:string ->((12)words$word#int)option) arg_=
+ (let s203_0 = arg_ in
+ if ((case ((s200_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s200_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s204_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s204_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s208_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s208_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s212_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s212_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s216_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s216_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s220_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s220_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s224_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s224_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s228_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s228_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s232_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s232_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s236_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s236_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s240_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s240_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s244_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s244_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s248_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s248_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s252_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s252_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s256_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s256_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s260_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s260_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s264_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s264_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s268_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s268_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s272_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s272_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s276_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s276_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s280_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s280_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s284_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s284_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s288_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s288_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s292_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s292_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s296_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s296_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s300_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s300_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s304_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s304_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s308_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s308_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s312_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s312_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s316_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s316_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s320_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s320_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s324_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s324_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s328_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s328_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s332_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s332_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s336_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s336_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s340_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s340_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s344_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s344_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s348_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s348_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s352_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s352_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s356_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s356_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s360_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s360_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s364_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s364_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s368_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s368_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s372_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s372_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s376_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s376_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s380_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s380_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s384_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s384_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s388_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s388_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s392_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s392_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s396_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s396_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s400_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s400_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s404_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s404_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s408_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s408_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s412_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s412_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s416_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s416_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s420_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s420_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s424_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s424_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s428_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s428_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s432_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s432_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s436_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s436_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s440_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s440_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s444_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s444_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s448_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s448_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s452_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s452_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s456_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s456_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s460_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s460_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s464_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s464_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s468_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s468_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s472_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s472_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s476_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s476_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s480_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s480_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s484_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s484_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s488_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s488_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val Mk_Ustatus : mword ty32 -> Ustatus*)
+
+val _ = Define `
+ ((Mk_Ustatus:(32)words$word -> Ustatus) v=
+ (<| Ustatus_Ustatus_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Ustatus_bits : Ustatus -> mword ty32*)
+
+val _ = Define `
+ ((get_Ustatus_bits:Ustatus ->(32)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Ustatus_bits : register_ref regstate register_value Ustatus -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Ustatus_bits:((regstate),(register_value),(Ustatus))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Ustatus_bits : Ustatus -> mword ty32 -> Ustatus*)
+
+val _ = Define `
+ ((update_Ustatus_bits:Ustatus ->(32)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Ustatus_UPIE:Ustatus ->(1)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Ustatus_UPIE:((regstate),(register_value),(Ustatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Ustatus_UPIE:Ustatus ->(1)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Ustatus_UIE:Ustatus ->(1)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Ustatus_UIE:((regstate),(register_value),(Ustatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Ustatus_UIE:Ustatus ->(1)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val lower_sstatus : Sstatus -> Ustatus*)
+
+val _ = Define `
+ ((lower_sstatus:Sstatus -> Ustatus) s=
+ (let u = (Mk_Ustatus ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let u = (update_Ustatus_UPIE u ((get_Sstatus_UPIE s : 1 words$word))) in
+ update_Ustatus_UIE u ((get_Sstatus_UIE s : 1 words$word))))`;
+
+
+(*val lift_ustatus : Sstatus -> Ustatus -> Sstatus*)
+
+val _ = Define `
+ ((lift_ustatus:Sstatus -> Ustatus -> Sstatus) (s : Sstatus) (u : Ustatus)=
+ (let s = (update_Sstatus_UPIE s ((get_Ustatus_UPIE u : 1 words$word))) in
+ update_Sstatus_UIE s ((get_Ustatus_UIE u : 1 words$word))))`;
+
+
+(*val legalize_ustatus : Mstatus -> mword ty32 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_ustatus:Mstatus ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (v : xlenbits)=
+ (let u = (Mk_Ustatus v) in
+ let s = (lower_mstatus m) in
+ let s = (lift_ustatus s u) in
+ lift_sstatus m s))`;
+
+
+(*val Mk_Uinterrupts : mword ty32 -> Uinterrupts*)
+
+val _ = Define `
+ ((Mk_Uinterrupts:(32)words$word -> Uinterrupts) v=
+ (<| Uinterrupts_Uinterrupts_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Uinterrupts_bits : Uinterrupts -> mword ty32*)
+
+val _ = Define `
+ ((get_Uinterrupts_bits:Uinterrupts ->(32)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Uinterrupts_bits : register_ref regstate register_value Uinterrupts -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Uinterrupts_bits:((regstate),(register_value),(Uinterrupts))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Uinterrupts_bits : Uinterrupts -> mword ty32 -> Uinterrupts*)
+
+val _ = Define `
+ ((update_Uinterrupts_bits:Uinterrupts ->(32)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_UEI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_UEI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_UEI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_UTI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_UTI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_UTI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_USI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_USI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_USI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val lower_sip : Sinterrupts -> Sinterrupts -> Uinterrupts*)
+
+val _ = Define `
+ ((lower_sip:Sinterrupts -> Sinterrupts -> Uinterrupts) (s : Sinterrupts) (d : Sinterrupts)=
+ (let (u : Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s : 1 words$word)) ((get_Sinterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s : 1 words$word)) ((get_Sinterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s : 1 words$word)) ((get_Sinterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lower_sie : Sinterrupts -> Sinterrupts -> Uinterrupts*)
+
+val _ = Define `
+ ((lower_sie:Sinterrupts -> Sinterrupts -> Uinterrupts) (s : Sinterrupts) (d : Sinterrupts)=
+ (let (u : Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) in
+ let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s : 1 words$word)) ((get_Sinterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s : 1 words$word)) ((get_Sinterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s : 1 words$word)) ((get_Sinterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lift_uip : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lift_uip:Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts) (o1 : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)=
+ (let (s : Sinterrupts) = o1 in
+ if (((((get_Sinterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u : 1 words$word))
+ else s))`;
+
+
+(*val legalize_uip : Sinterrupts -> Sinterrupts -> mword ty32 -> Sinterrupts*)
+
+val _ = Define `
+ ((legalize_uip:Sinterrupts -> Sinterrupts ->(32)words$word -> Sinterrupts) (s : Sinterrupts) (d : Sinterrupts) (v : xlenbits)=
+ (lift_uip s d ((Mk_Uinterrupts v))))`;
+
+
+(*val lift_uie : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lift_uie:Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts) (o1 : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)=
+ (let (s : Sinterrupts) = o1 in
+ let s =
+ (if (((((get_Sinterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_UEI s ((get_Uinterrupts_UEI u : 1 words$word))
+ else s) in
+ let s =
+ (if (((((get_Sinterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_UTI s ((get_Uinterrupts_UTI u : 1 words$word))
+ else s) in
+ if (((((get_Sinterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u : 1 words$word))
+ else s))`;
+
+
+(*val legalize_uie : Sinterrupts -> Sinterrupts -> mword ty32 -> Sinterrupts*)
+
+val _ = Define `
+ ((legalize_uie:Sinterrupts -> Sinterrupts ->(32)words$word -> Sinterrupts) (s : Sinterrupts) (d : Sinterrupts) (v : xlenbits)=
+ (lift_uie s d ((Mk_Uinterrupts v))))`;
+
+
+(*val handle_trap_extension : Privilege -> mword ty32 -> maybe unit -> unit*)
+
+val _ = Define `
+ ((handle_trap_extension:Privilege ->(32)words$word ->(unit)option -> unit) (p : Privilege) (pc : xlenbits) (u : unit option)= () )`;
+
+
+(*val prepare_trap_vector : Privilege -> Mcause -> M (mword ty32)*)
+
+val _ = Define `
+ ((prepare_trap_vector:Privilege -> Mcause ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p : Privilege) (cause : Mcause)= (sail2_state_monad$bindS
+ (case p of
+ Machine => sail2_state_monad$read_regS mtvec_ref
+ | Supervisor => sail2_state_monad$read_regS stvec_ref
+ | User => sail2_state_monad$read_regS utvec_ref
+ ) (\ (tvec : Mtvec) .
+ (case ((tvec_addr tvec cause : ( 32 words$word)option)) of
+ SOME (epc) => sail2_state_monad$returnS epc
+ | NONE => (internal_error "Invalid tvec mode" : ( 32 words$word) M)
+ ))))`;
+
+
+(*val get_xret_target : Privilege -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_xret_target:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p=
+ ((case p of
+ Machine => (sail2_state_monad$read_regS mepc_ref : ( 32 words$word) M)
+ | Supervisor => (sail2_state_monad$read_regS sepc_ref : ( 32 words$word) M)
+ | User => (sail2_state_monad$read_regS uepc_ref : ( 32 words$word) M)
+ )))`;
+
+
+(*val set_xret_target : Privilege -> mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((set_xret_target:Privilege ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p value= (sail2_state_monad$bindS
+ (legalize_xepc value : ( 32 words$word) M) (\ target . sail2_state_monad$seqS
+ (case p of
+ Machine => sail2_state_monad$write_regS mepc_ref target
+ | Supervisor => sail2_state_monad$write_regS sepc_ref target
+ | User => sail2_state_monad$write_regS uepc_ref target
+ )
+ (sail2_state_monad$returnS target))))`;
+
+
+(*val prepare_xret_target : Privilege -> M (mword ty32)*)
+
+val _ = Define `
+ ((prepare_xret_target:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p= ((get_xret_target p : ( 32 words$word) M)))`;
+
+
+(*val get_mtvec : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_mtvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 32 words$word)))))`;
+
+
+(*val get_stvec : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_stvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS stvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 32 words$word)))))`;
+
+
+(*val get_utvec : unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((get_utvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 32 words$word)))))`;
+
+
+(*val set_mtvec : mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((set_mtvec:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS mtvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 32 words$word))))))`;
+
+
+(*val set_stvec : mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((set_stvec:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS stvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS stvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS stvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 32 words$word))))))`;
+
+
+(*val set_utvec : mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((set_utvec:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS utvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS utvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 32 words$word))))))`;
+
+
+(*val is_NExt_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((is_NExt_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : 12 bits) (p : Privilege)=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else sail2_state_monad$returnS F))`;
+
+
+(*val read_NExt_CSR : mword ty12 -> M (maybe (mword ty32))*)
+
+val _ = Define `
+ ((read_NExt_CSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((32)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Ustatus_bits ((lower_sstatus ((lower_mstatus w__0)))) : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__1 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__2 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__3 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Uinterrupts_bits ((lower_sie ((lower_mie w__1 w__2)) w__3)) : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_utvec () : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$returnS (SOME w__4))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS uscratch_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) . sail2_state_monad$returnS (SOME w__5))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target User : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__7 : 32 words$word) .
+ sail2_state_monad$returnS (SOME ((and_vec w__6 w__7 : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS ucause_ref) (\ (w__8 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__8 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utval_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . sail2_state_monad$returnS (SOME w__9))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__10 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__11 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__12 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Uinterrupts_bits ((lower_sip ((lower_mip w__10 w__11)) w__12))
+ : 32 words$word))))))
+ else sail2_state_monad$returnS NONE))`;
+
+
+(*val write_NExt_CSR : mword ty12 -> mword ty32 -> M bool*)
+
+val _ = Define `
+ ((write_NExt_CSR:(12)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)=
+ (let b__0 = csr in sail2_state_monad$bindS
+ (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (legalize_ustatus w__0 value) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__1)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__2 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__3 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__4 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__5 : Sinterrupts) .
+ let sie = (legalize_uie ((lower_mie w__3 w__4)) w__5 value) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . sail2_state_monad$bindS
+ (lift_sie w__6 w__7 sie) (\ (w__8 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__8)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__9 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__9 : 32 words$word))))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_utvec value : ( 32 words$word) M) (\ (w__10 : 32 words$word) . sail2_state_monad$returnS (SOME w__10))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS uscratch_ref value)
+ (sail2_state_monad$read_regS uscratch_ref : ( 32 words$word) M)) (\ (w__11 : 32 words$word) . sail2_state_monad$returnS (SOME w__11))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target User value : ( 32 words$word) M) (\ (w__12 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__12))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits ucause_ref value)
+ (sail2_state_monad$read_regS ucause_ref)) (\ (w__13 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__13 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS utval_ref value)
+ (sail2_state_monad$read_regS utval_ref : ( 32 words$word) M)) (\ (w__14 : 32 words$word) . sail2_state_monad$returnS (SOME w__14))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__15 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__16 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) .
+ let sip = (legalize_uip ((lower_mip w__15 w__16)) w__17 value) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__18 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__19 : Minterrupts) . sail2_state_monad$bindS
+ (lift_sip w__18 w__19 sip) (\ (w__20 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__20)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__21 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__21 : 32 words$word))))))))))
+ else sail2_state_monad$returnS NONE) (\ (res : xlenbits option) .
+ sail2_state_monad$returnS ((case res of
+ SOME (v) =>
+ let (_ : unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr))
+ ((STRCAT " <- "
+ ((STRCAT ((string_of_bits v))
+ ((STRCAT " (input: " ((STRCAT ((string_of_bits value)) ")"))))))))))))
+ else () ) in
+ T
+ | NONE => F
+ )))))`;
+
+
+(*val ext_is_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((ext_is_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (is_NExt_CSR_defined csr p))`;
+
+
+(*val ext_read_CSR : mword ty12 -> M (maybe (mword ty32))*)
+
+val _ = Define `
+ ((ext_read_CSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((32)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr= ((read_NExt_CSR csr : ( ( 32 words$word)option) M)))`;
+
+
+(*val ext_write_CSR : mword ty12 -> mword ty32 -> M bool*)
+
+val _ = Define `
+ ((ext_write_CSR:(12)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= (write_NExt_CSR csr value))`;
+
+
+(*val csrAccess : mword ty12 -> mword ty2*)
+
+val _ = Define `
+ ((csrAccess:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)))`;
+
+
+(*val csrPriv : mword ty12 -> mword ty2*)
+
+val _ = Define `
+ ((csrPriv:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val is_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((is_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 32 : int):ii) = (( 32 : int):ii)))))))
+ else ext_is_CSR_defined csr p))`;
+
+
+(*val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool*)
+
+val _ = Define `
+ ((check_CSR_access:(2)words$word ->(2)words$word -> Privilege -> bool -> bool) csrrw csrpr p isWrite=
+ (((~ ((((((isWrite = T))) /\ (((csrrw = (vec_of_bits [B1;B1] : 2 words$word))))))))) /\ ((zopz0zKzJ_u ((privLevel_to_bits p : 2 words$word)) csrpr))))`;
+
+
+(*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ (w__2 :
+ bool) .
+ sail2_state_monad$returnS ((~ w__2)))))`;
+
+
+(*val check_Counteren : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((check_Counteren:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=
+ ((case (csr, p) of
+ (b__0, Supervisor) =>
+ if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__0 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__1 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__2 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else
+ sail2_state_monad$returnS ((case (b__0, Supervisor) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T
+ ))
+ | (b__3, User) =>
+ if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__6 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__7 : bool) . sail2_state_monad$returnS ((~ w__7))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__8 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__8 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__11 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__11 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__12 : bool) . sail2_state_monad$returnS ((~ w__12))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__13 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__13 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__16 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__16 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__17 : bool) . sail2_state_monad$returnS ((~ w__17))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__18 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__18 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else
+ sail2_state_monad$returnS ((case (b__3, User) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T
+ ))
+ | (_, _) =>
+ sail2_state_monad$returnS (if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T)
+ )))`;
+
+
+(*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*)
+
+val _ = Define `
+ ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)=
+ (sail2_state$and_boolS ((is_CSR_defined csr p))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p
+ isWrite))) (sail2_state$and_boolS ((check_TVM_SATP csr p)) ((check_Counteren csr p))))))`;
+
+
+(*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*)
+
+val _ = Define `
+ ((exception_delegatee:ExceptionType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)=
+ (let idx = (num_of_ExceptionType e) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) .
+ let super = (access_vec_dec ((get_Medeleg_bits w__0 : 32 words$word)) idx) in sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$bindS
+ (if w__1 then
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool super)))
+ (sail2_state$and_boolS ((haveNExt () ))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS sedeleg_ref) (\ (w__3 : Sedeleg) .
+ sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec ((get_Sedeleg_bits w__3 : 32 words$word)) idx)))))))
+ else sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool super))) ((haveNExt () ))) (\ user . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveUsrMode () )) (sail2_state_monad$returnS user)) (\ w__9 . sail2_state_monad$bindS
+ (if w__9 then sail2_state_monad$returnS User
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveSupMode () )) (sail2_state_monad$returnS ((bit_to_bool super)))) (\ (w__11 : bool) .
+ sail2_state_monad$returnS (if w__11 then Supervisor
+ else Machine))) (\ deleg .
+ sail2_state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg : 2 words$word))
+ ((privLevel_to_bits p : 2 words$word)))) then
+ p
+ else deleg))))))))`;
+
+
+(*val findPendingInterrupt : mword ty32 -> maybe InterruptType*)
+
+val _ = Define `
+ ((findPendingInterrupt:(32)words$word ->(InterruptType)option) ip=
+ (let ip = (Mk_Minterrupts ip) in
+ if (((((get_Minterrupts_MEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ SOME I_M_External
+ else if (((((get_Minterrupts_MSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_M_Software
+ else if (((((get_Minterrupts_MTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_M_Timer
+ else if (((((get_Minterrupts_SEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_External
+ else if (((((get_Minterrupts_SSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_Software
+ else if (((((get_Minterrupts_STI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_Timer
+ else if (((((get_Minterrupts_UEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_External
+ else if (((((get_Minterrupts_USI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_Software
+ else if (((((get_Minterrupts_UTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_Timer
+ else NONE))`;
+
+
+(*val processPending : Minterrupts -> Minterrupts -> mword ty32 -> bool -> interrupt_set*)
+
+val _ = Define `
+ ((processPending:Minterrupts -> Minterrupts ->(32)words$word -> bool -> interrupt_set) (xip : Minterrupts) (xie : Minterrupts) (xideleg : xlenbits) (priv_enabled : bool)=
+ (let effective_pend =
+ ((and_vec ((get_Minterrupts_bits xip : 32 words$word))
+ ((and_vec ((get_Minterrupts_bits xie : 32 words$word)) ((not_vec xideleg : 32 words$word))
+ : 32 words$word))
+ : 32 words$word)) in
+ let effective_delg = ((and_vec ((get_Minterrupts_bits xip : 32 words$word)) xideleg : 32 words$word)) in
+ if (((priv_enabled /\ (((effective_pend <> ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))))))
+ then
+ Ints_Pending effective_pend
+ else if (((effective_delg <> ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)))))
+ then
+ Ints_Delegated effective_delg
+ else Ints_Empty () ))`;
+
+
+(*val getPendingSet : Privilege -> M (maybe ((mword ty32 * Privilege)))*)
+
+val _ = Define `
+ ((getPendingSet:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((((32)words$word#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv= (sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__0 "no user mode: M/U or M/S/U system required")
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__1 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__2 : Minterrupts) .
+ let effective_pending =
+ ((and_vec ((get_Minterrupts_bits w__1 : 32 words$word))
+ ((get_Minterrupts_bits w__2 : 32 words$word))
+ : 32 words$word)) in
+ if (((effective_pending = ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)))))
+ then
+ sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) <> ((privLevel_to_bits Machine : 2 words$word))))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_MIE w__3 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ mIE . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_SIE w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))))) (\ sIE . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveNExt () ))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_UIE w__10 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ uIE . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__12 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__13 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__14 : Minterrupts) .
+ (case ((processPending w__12 w__13 ((get_Minterrupts_bits w__14 : 32 words$word)) mIE)) of
+ Ints_Empty (() ) => sail2_state_monad$returnS NONE
+ | Ints_Pending (p) =>
+ let r = (p, Machine) in
+ sail2_state_monad$returnS (SOME r)
+ | Ints_Delegated (d) => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__15 : bool) .
+ if ((~ w__15)) then
+ sail2_state_monad$returnS (if uIE then
+ let r = (d, User) in
+ SOME r
+ else NONE)
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__16 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) .
+ sail2_state_monad$returnS ((case ((processPending ((Mk_Minterrupts d)) w__16
+ ((get_Sinterrupts_bits w__17 : 32 words$word)) sIE)) of
+ Ints_Empty (() ) => NONE
+ | Ints_Pending (p) =>
+ let r = (p, Supervisor) in
+ SOME r
+ | Ints_Delegated (d) =>
+ if uIE then
+ let r = (d, User) in
+ SOME r
+ else NONE
+ )))))
+ ))))))))))))`;
+
+
+(*val dispatchInterrupt : Privilege -> M (maybe ((InterruptType * Privilege)))*)
+
+val _ = Define `
+ ((dispatchInterrupt:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv= (sail2_state_monad$bindS
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))
+ (sail2_state$and_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))
+ ( sail2_state_monad$bindS(haveNExt () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) .
+ if w__4 then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) "invalid current privilege")
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__5 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) .
+ let enabled_pending =
+ ((and_vec ((get_Minterrupts_bits w__5 : 32 words$word))
+ ((get_Minterrupts_bits w__6 : 32 words$word))
+ : 32 words$word)) in
+ sail2_state_monad$returnS ((case ((findPendingInterrupt enabled_pending)) of
+ SOME (i) =>
+ let r = (i, Machine) in
+ SOME r
+ | NONE => NONE
+ ))))
+ else sail2_state_monad$bindS
+ (getPendingSet priv : ( (( 32 words$word # Privilege))option) M) (\ (w__7 :
+ (( 32 words$word # Privilege))option) .
+ sail2_state_monad$returnS ((case w__7 of
+ NONE => NONE
+ | SOME ((ip, p)) =>
+ (case ((findPendingInterrupt ip)) of
+ NONE => NONE
+ | SOME (i) =>
+ let r = (i, p) in
+ SOME r
+ )
+ ))))))`;
+
+
+(*val tval : maybe (mword ty32) -> mword ty32*)
+
+val _ = Define `
+ ((tval:((32)words$word)option ->(32)words$word) excinfo=
+ ((case excinfo of
+ SOME (e) => e
+ | NONE => (EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)
+ )))`;
+
+
+(*val rvfi_trap : unit -> unit*)
+
+val _ = Define `
+ ((rvfi_trap:unit -> unit) () = () )`;
+
+
+(*val trap_handler : Privilege -> bool -> mword ty8 -> mword ty32 -> maybe (mword ty32) -> maybe unit -> M (mword ty32)*)
+
+val _ = Define `
+ ((trap_handler:Privilege -> bool ->(8)words$word ->(32)words$word ->(xlenbits)option ->(ext_exception)option ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info :
+ xlenbits option) (ext : ext_exception option)=
+ (let (_ : unit) = (rvfi_trap () ) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "handling "
+ ((STRCAT (if intr then "int#" else "exc#")
+ ((STRCAT ((string_of_bits c))
+ ((STRCAT " at priv "
+ ((STRCAT ((privLevel_to_str del_priv))
+ ((STRCAT " with tval "
+ ((string_of_bits ((tval info : 32 words$word))))))))))))))))
+ else () ) in
+ let (_ : unit) = (cancel_reservation () ) in
+ (case del_priv of
+ Machine => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word)))
+ (set_Mcause_Cause mcause_ref ((EXTZ (( 31 : int):ii) c : 31 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word)))
+ (set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word)))
+ (sail2_state_monad$write_regS mtval_ref ((tval info : 32 words$word))))
+ (sail2_state_monad$write_regS mepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__2 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mcause_ref)) (\ (w__3 : Mcause) .
+ (prepare_trap_vector del_priv w__3 : ( 32 words$word) M)))))
+ | Supervisor => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__5 "no supervisor mode present for delegation")
+ (set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))))
+ (set_Mcause_Cause scause_ref ((EXTZ (( 31 : int):ii) c : 31 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word)))
+ (set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . sail2_state_monad$bindS
+ (case w__7 of
+ User => sail2_state_monad$returnS ((bool_to_bits F : 1 words$word))
+ | Supervisor => sail2_state_monad$returnS ((bool_to_bits T : 1 words$word))
+ | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) M)
+ ) (\ (w__9 : 1 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SPP mstatus_ref w__9)
+ (sail2_state_monad$write_regS stval_ref ((tval info : 32 words$word))))
+ (sail2_state_monad$write_regS sepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__10 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS scause_ref)) (\ (w__11 : Mcause) .
+ (prepare_trap_vector del_priv w__11 : ( 32 words$word) M)))))))
+ | User => sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__13 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__13 "no user mode present for delegation")
+ (set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr : 1 words$word))))
+ (set_Mcause_Cause ucause_ref ((EXTZ (( 31 : int):ii) c : 31 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__14 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_UPIE mstatus_ref ((get_Mstatus_UIE w__14 : 1 words$word)))
+ (set_Mstatus_UIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$write_regS utval_ref ((tval info : 32 words$word))))
+ (sail2_state_monad$write_regS uepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__15 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS ucause_ref)) (\ (w__16 : Mcause) .
+ (prepare_trap_vector del_priv w__16 : ( 32 words$word) M)))))
+ )))`;
+
+
+(*val exception_handler : Privilege -> ctl_result -> mword ty32 -> M (mword ty32)*)
+
+val _ = Define `
+ ((exception_handler:Privilege -> ctl_result ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)=
+ ((case (cur_priv, ctl) of
+ (_, CTL_TRAP (e)) => sail2_state_monad$bindS
+ (exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv .
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "trapping from "
+ ((STRCAT ((privLevel_to_str cur_priv))
+ ((STRCAT " to "
+ ((STRCAT ((privLevel_to_str del_priv))
+ ((STRCAT " to handle "
+ ((exceptionType_to_str e.sync_exception_trap))))))))))))
+ else () ) in
+ (trap_handler del_priv F ((exceptionType_to_bits e.sync_exception_trap : 8 words$word)) pc
+ e.sync_exception_excinfo e.sync_exception_ext
+ : ( 32 words$word) M))
+ | (_, CTL_MRET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word)))
+ (set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS
+ (privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))) (\ (w__3 : Privilege) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS cur_privilege_ref w__3)
+ (haveUsrMode () )) (\ (w__4 : bool) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPP mstatus_ref
+ ((privLevel_to_bits (if w__4 then User else Machine) : 2 words$word)))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__5 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__6 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__6)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target Machine : ( 32 words$word) M) (\ (w__7 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__8 : 32 words$word) .
+ sail2_state_monad$returnS ((and_vec w__7 w__8 : 32 words$word))))))))))
+ | (_, CTL_SRET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__9 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__9 : 1 words$word)))
+ (set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__10 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ cur_privilege_ref
+ (if (((((get_Mstatus_SPP w__10 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ Supervisor
+ else User))
+ (set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__11 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__11 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__12 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__12)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target Supervisor : ( 32 words$word) M) (\ (w__13 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__14 : 32 words$word) .
+ sail2_state_monad$returnS ((and_vec w__13 w__14 : 32 words$word))))))))
+ | (_, CTL_URET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_UIE mstatus_ref ((get_Mstatus_UPIE w__15 : 1 words$word)))
+ (set_Mstatus_UPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$write_regS cur_privilege_ref User))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__16 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__16 : 32 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__17 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__17)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target User : ( 32 words$word) M) (\ (w__18 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__19 : 32 words$word) .
+ sail2_state_monad$returnS ((and_vec w__18 w__19 : 32 words$word)))))))
+ )))`;
+
+
+(*val handle_mem_exception : mword ty32 -> ExceptionType -> M unit*)
+
+val _ = Define `
+ ((handle_mem_exception:(32)words$word -> ExceptionType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)=
+ (let (t : sync_exception) =
+ (<| sync_exception_trap := e;
+ sync_exception_excinfo := (SOME addr);
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__0 (CTL_TRAP t) w__1 : ( 32 words$word) M) (\ (w__2 : 32 words$word) .
+ set_next_pc w__2)))))`;
+
+
+(*val handle_interrupt : InterruptType -> Privilege -> M unit*)
+
+val _ = Define `
+ ((handle_interrupt:InterruptType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS
+ (trap_handler del_priv T ((interruptType_to_bits i : 8 words$word)) w__0 NONE NONE
+ : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ set_next_pc w__1))))`;
+
+
+(*val init_sys : unit -> M unit*)
+
+val _ = Define `
+ ((init_sys:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS cur_privilege_ref Machine)
+ (sail2_state_monad$write_regS mhartid_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Misa_MXL misa_ref ((arch_to_bits RV32 : 2 words$word))))
+ (set_Misa_A misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_C misa_ref ((bool_to_bits ((sys_enable_rvc () )) : 1 words$word))))
+ (set_Misa_I misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_M misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_U misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_S misa_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref ((set_mstatus_SXL w__0 ((get_Misa_MXL w__1 : 2 words$word)))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__3 : Misa) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref ((set_mstatus_UXL w__2 ((get_Misa_MXL w__3 : 2 words$word)))))
+ (set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (set_Minterrupts_bits mip_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Minterrupts_bits mie_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Minterrupts_bits mideleg_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Medeleg_bits medeleg_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Mtvec_bits mtvec_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (set_Mcause_bits mcause_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS mepc_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS mtval_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS mscratch_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS mcycle_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mtime_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Counteren_bits mcounteren_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS minstret_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS minstret_written_ref F))
+ (init_pmp () ))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((STRCAT ((string_of_bits ((get_Mstatus_bits w__4 : 32 words$word))))
+ ((STRCAT " (input: "
+ ((STRCAT
+ ((string_of_bits
+ ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ ")")))))))))))
+ else sail2_state_monad$returnS () )))))))`;
+
+
+(*val elf_tohost : unit -> ii*)
+
+(*val elf_entry : unit -> ii*)
+
+
+
+(*val phys_mem_segments : unit -> list ((mword ty32 * mword ty32))*)
+
+val _ = Define `
+ ((phys_mem_segments:unit ->((32)words$word#(32)words$word)list) () =
+ (((plat_rom_base () : 32 words$word), (plat_rom_size () : 32 words$word)) ::
+ (((plat_ram_base () : 32 words$word), (plat_ram_size () : 32 words$word)) :: [])))`;
+
+
+(*val within_phys_mem : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_phys_mem:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (let addr_int = (lem$w2ui addr) in
+ let ram_base_int = (lem$w2ui ((plat_ram_base () : 32 words$word))) in
+ let rom_base_int = (lem$w2ui ((plat_rom_base () : 32 words$word))) in
+ let ram_size_int = (lem$w2ui ((plat_ram_size () : 32 words$word))) in
+ let rom_size_int = (lem$w2ui ((plat_rom_size () : 32 words$word))) in
+ if (((((ram_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <= ((ram_base_int + ram_size_int)))))))
+ then
+ T
+ else if (((((rom_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <=
+ ((rom_base_int + rom_size_int))))))) then
+ T
+ else
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT "within_phys_mem: "
+ ((STRCAT ((string_of_bits addr)) " not within phys-mem:"))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_rom_base: " ((string_of_bits ((plat_rom_base () : 32 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_rom_size: " ((string_of_bits ((plat_rom_size () : 32 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_ram_base: " ((string_of_bits ((plat_ram_base () : 32 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_ram_size: " ((string_of_bits ((plat_ram_size () : 32 words$word))))))) in
+ F))`;
+
+
+(*val within_clint : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_clint:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (let addr_int = (lem$w2ui addr) in
+ let clint_base_int = (lem$w2ui ((plat_clint_base () : 32 words$word))) in
+ let clint_size_int = (lem$w2ui ((plat_clint_size () : 32 words$word))) in
+ (((clint_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <= ((clint_base_int + clint_size_int)))))))`;
+
+
+(*val within_htif_writable : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_htif_writable:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ ((((((plat_htif_tohost () : 32 words$word)) = addr))) \/ ((((((((add_vec_int ((plat_htif_tohost () : 32 words$word)) (( 4 : int):ii) : 32 words$word)) = addr))) /\ (((width = (( 4 : int):ii)))))))))`;
+
+
+(*val within_htif_readable : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_htif_readable:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ ((((((plat_htif_tohost () : 32 words$word)) = addr))) \/ ((((((((add_vec_int ((plat_htif_tohost () : 32 words$word)) (( 4 : int):ii) : 32 words$word)) = addr))) /\ (((width = (( 4 : int):ii)))))))))`;
+
+
+val _ = Define `
+((MSIP_BASE:(32)words$word)=
+ ((EXTZ (( 32 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 20 words$word)
+ : 32 words$word)))`;
+
+
+val _ = Define `
+((MTIMECMP_BASE:(32)words$word)=
+ ((EXTZ (( 32 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 20 words$word)
+ : 32 words$word)))`;
+
+
+val _ = Define `
+((MTIMECMP_BASE_HI:(32)words$word)=
+ ((EXTZ (( 32 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 20 words$word)
+ : 32 words$word)))`;
+
+
+val _ = Define `
+((MTIME_BASE:(32)words$word)=
+ ((EXTZ (( 32 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0] : 20 words$word)
+ : 32 words$word)))`;
+
+
+val _ = Define `
+((MTIME_BASE_HI:(32)words$word)=
+ ((EXTZ (( 32 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0] : 20 words$word)
+ : 32 words$word)))`;
+
+
+(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((clint_load:(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+ (let addr = ((sub_vec addr ((plat_clint_base () : 32 words$word)) : 32 words$word)) in
+ if ((((((addr = MSIP_BASE))) /\ ((((((((id width)) = (( 8 : int):ii)))) \/ (((((id width)) = (( 4 : int):ii)))))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits ((get_Minterrupts_MSI w__0 : 1 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__1 : Minterrupts) .
+ sail2_state_monad$returnS (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 : 1 words$word))
+ (((( 8 : int):ii) * ((id width))))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits
+ ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__3 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint<8>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__4)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__5 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__5 (( 64 : int):ii) : 64 words$word)) : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint-hi<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits
+ ((subrange_vec_dec w__6 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__7 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__7 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__8)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__9 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__9 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__10)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__11 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__11 (( 64 : int):ii) : 64 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__12 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__12)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__13 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__13 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint[" ((STRCAT ((string_of_bits addr)) "] -> <not-mapped>"))))
+ else () ) in
+ sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val clint_dispatch : unit -> M unit*)
+
+val _ = Define `
+ ((clint_dispatch:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT "clint::tick mtime <- " ((string_of_bits w__0)))))))
+ else sail2_state_monad$returnS () )
+ (set_Minterrupts_MTI mip_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ if ((zopz0zIzJ_u w__1 w__2)) then sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT " clint timer pending at mtime " ((string_of_bits w__3)))))))
+ else sail2_state_monad$returnS () )
+ (set_Minterrupts_MTI mip_ref ((bool_to_bits T : 1 words$word)))
+ else sail2_state_monad$returnS () ))))`;
+
+
+(*val clint_store : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((clint_store:(32)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+ (let addr = ((sub_vec addr ((plat_clint_base () : 32 words$word)) : 32 words$word)) in
+ if ((((((addr = MSIP_BASE))) /\ ((((((((id width)) = (( 8 : int):ii)))) \/ (((((id width)) = (( 4 : int):ii)))))))))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- "
+ ((STRCAT ((string_of_bits data))
+ ((STRCAT " (mip.MSI <- "
+ ((STRCAT
+ ((string_of_bits
+ ((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word))))
+ ")"))))))))))))
+ else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Minterrupts_MSI mip_ref
+ ((bool_to_bits
+ (((((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word))))
+ : 1 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then
+ let (data : 64 words$word) = ((words$w2w data : 64 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<8>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtimecmp_ref ((zero_extend data (( 64 : int):ii) : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) ((zero_extend data (( 32 : int):ii) : 32 words$word))
+ : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T)))
+ else if ((((((addr = MTIMECMP_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__1 (( 63 : int):ii) (( 32 : int):ii) ((zero_extend data (( 32 : int):ii) : 32 words$word))
+ : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T)))
+ else
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (<unmapped>)"))))))))
+ else () ) in
+ sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val tick_clock : unit -> M unit*)
+
+val _ = Define `
+ ((tick_clock:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii) : 64 words$word)))
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtime_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))) (clint_dispatch () )))))`;
+
+
+(*val Mk_htif_cmd : mword ty64 -> htif_cmd*)
+
+val _ = Define `
+ ((Mk_htif_cmd:(64)words$word -> htif_cmd) v=
+ (<| htif_cmd_htif_cmd_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*)
+
+val _ = Define `
+ ((get_htif_cmd_bits:htif_cmd ->(64)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_bits:((regstate),(register_value),(htif_cmd))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_bits:htif_cmd ->(64)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_device : htif_cmd -> mword ty8*)
+
+val _ = Define `
+ ((get_htif_cmd_device:htif_cmd ->(8)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_device:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_device:htif_cmd ->(8)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*)
+
+val _ = Define `
+ ((get_htif_cmd_cmd:htif_cmd ->(8)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_cmd:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_cmd:htif_cmd ->(8)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*)
+
+val _ = Define `
+ ((get_htif_cmd_payload:htif_cmd ->(48)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))`;
+
+
+(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_payload:((regstate),(register_value),(htif_cmd))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_payload:htif_cmd ->(48)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val htif_load : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((htif_load:(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "htif["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__0)))))))))))
+ else sail2_state_monad$returnS () )
+ (if ((((((width = (( 8 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 32 words$word)))))))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__1 (( 64 : int):ii) : 64 words$word)) : 'int8_times_n words$word))))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 32 words$word))))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((add_vec_int ((plat_htif_tohost () : 32 words$word)) (( 4 : int):ii) : 32 words$word))))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__3 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault))))`;
+
+
+(*val htif_store : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((htif_store:(32)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+ (let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif["
+ ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))
+ else () ) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if (((width = (( 8 : int):ii)))) then
+ let (data : 64 words$word) = ((words$w2w data : 64 words$word)) in
+ sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) data : 64 words$word))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 32 words$word))))))))
+ then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$write_regS htif_tohost_ref ((update_subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) data : 64 words$word)))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((add_vec_int ((plat_htif_tohost () : 32 words$word)) (( 4 : int):ii) : 32 words$word))))))))
+ then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$write_regS htif_tohost_ref ((update_subrange_vec_dec w__1 (( 63 : int):ii) (( 32 : int):ii) data : 64 words$word)))
+ else sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) data : 64 words$word)))
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M)) (\ (w__2 : 64 words$word) .
+ let cmd = (Mk_htif_cmd w__2) in
+ let b__0 = ((get_htif_cmd_device cmd : 8 words$word)) in sail2_state_monad$seqS
+ (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif-syscall-proxy cmd: "
+ ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))
+ else () ) in
+ if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 0 : int):ii)))
+ : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$seqS
+ (sail2_state_monad$write_regS htif_done_ref T)
+ (sail2_state_monad$write_regS
+ htif_exit_code_ref
+ ((shiftr ((zero_extend ((get_htif_cmd_payload cmd : 48 words$word)) (( 64 : int):ii) : 64 words$word))
+ (( 1 : int):ii)
+ : 64 words$word)))
+ else sail2_state_monad$returnS ()
+ else
+ sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif-term cmd: "
+ ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))
+ else () ) in
+ let b__2 = ((get_htif_cmd_cmd cmd : 8 words$word)) in
+ if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then ()
+ else if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then
+ plat_term_write
+ ((subrange_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 7 : int):ii) (( 0 : int):ii)
+ : 8 words$word))
+ else print_endline ((STRCAT "Unknown term cmd: " ((string_of_bits b__2))))
+ else print_endline ((STRCAT "htif-???? cmd: " ((string_of_bits data))))))
+ (sail2_state_monad$returnS (MemValue T)))))`;
+
+
+(*val htif_tick : unit -> M unit*)
+
+val _ = Define `
+ ((htif_tick:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT "htif::tick " ((string_of_bits w__0)))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`;
+
+
+(*val within_mmio_readable : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_mmio_readable:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((within_clint addr width)) \/ (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= ((id width)))))))))`;
+
+
+(*val within_mmio_writable : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((within_mmio_writable:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((within_clint addr width)) \/ (((((within_htif_writable addr width)) /\ ((((id width)) <= (( 8 : int):ii))))))))`;
+
+
+(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mmio_read:(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int)=
+ (if ((within_clint addr width)) then (clint_load addr width )
+ else if (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= ((id width))))))) then
+ (htif_load addr width )
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val mmio_write : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mmio_write:(32)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) data=
+ (if ((within_clint addr width)) then clint_store addr width data
+ else if (((((within_htif_writable addr width)) /\ ((((id width)) <= (( 8 : int):ii)))))) then
+ htif_store addr width data
+ else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val init_platform : unit -> M unit*)
+
+val _ = Define `
+ ((init_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))
+ (sail2_state_monad$write_regS htif_done_ref F))
+ (sail2_state_monad$write_regS htif_exit_code_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`;
+
+
+(*val tick_platform : unit -> M unit*)
+
+val _ = Define `
+ ((tick_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (htif_tick () ))`;
+
+
+(*val handle_illegal : unit -> M unit*)
+
+val _ = Define `
+ ((handle_illegal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (if ((plat_mtval_has_illegal_inst_bits () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS instbits_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$returnS (SOME w__0))
+ else sail2_state_monad$returnS NONE) (\ info .
+ let (t : sync_exception) =
+ (<| sync_exception_trap := E_Illegal_Instr;
+ sync_exception_excinfo := info;
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_TRAP t) w__2 : ( 32 words$word) M) (\ (w__3 : 32 words$word) .
+ set_next_pc w__3))))))`;
+
+
+(*val platform_wfi : unit -> M unit*)
+
+val _ = Define `
+ ((platform_wfi:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ if ((zopz0zI_u w__0 w__1)) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtime_ref w__2)
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$write_regS mcycle_ref w__3))
+ else sail2_state_monad$returnS () ))))`;
+
+
+(*val is_aligned_addr : mword ty32 -> integer -> bool*)
+
+val _ = Define `
+ ((is_aligned_addr:(32)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((((lem$w2ui addr)) % width)) = (( 0 : int):ii)))`;
+
+
+(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((phys_mem_read:AccessType ->(32)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)= (sail2_state_monad$bindS
+ (case (aq, rl, res) of
+ (F, F, F) => sail2_state_monad$bindS
+ (read_ram Read_plain addr width : ( 'int8_times_n words$word) M) (\ (w__0 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__0))
+ | (T, F, F) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__1 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__1))
+ | (T, T, F) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_strong_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__2 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__2))
+ | (F, F, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved addr width : ( 'int8_times_n words$word) M) (\ (w__3 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__3))
+ | (T, F, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__4 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__4))
+ | (T, T, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved_strong_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__5 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__5))
+ | (F, T, F) => sail2_state_monad$returnS NONE
+ | (F, T, T) => sail2_state_monad$returnS NONE
+ ) (\ w__6 .
+ let result = w__6 in
+ sail2_state_monad$returnS ((case (t, result) of
+ (Execute, NONE) => MemException E_Fetch_Access_Fault
+ | (Read, NONE) => MemException E_Load_Access_Fault
+ | (_, NONE) => MemException E_SAMO_Access_Fault
+ | (_, SOME (v)) =>
+ let (_ : unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ ((STRCAT "mem["
+ ((STRCAT ((accessType_to_str t))
+ ((STRCAT ","
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits v))))))))))))
+ else () ) in
+ MemValue v
+ )))))`;
+
+
+(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((checked_mem_read:AccessType ->(32)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)=
+ (if ((within_mmio_readable addr width)) then (mmio_read addr width )
+ else if ((within_phys_mem addr width)) then (phys_mem_read t addr width aq rl res )
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val pmp_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((pmp_mem_read:AccessType ->(32)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)=
+ (if ((~ ((plat_enable_pmp () )))) then (checked_mem_read t addr width aq rl res )
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . sail2_state_monad$bindS
+ (effectivePrivilege w__1 w__2) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (pmpCheck addr width t w__3) (\ (w__4 : ExceptionType option) .
+ (case w__4 of
+ NONE => (checked_mem_read t addr width aq rl res )
+ | SOME (e) => sail2_state_monad$returnS (MemException e)
+ )))))))`;
+
+
+(*val rvfi_read : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> MemoryOpResult (mword 'int8_times_n) -> unit*)
+
+val _ = Define `
+ ((rvfi_read:(32)words$word -> int ->('int8_times_n words$word)MemoryOpResult -> unit) addr width value= () )`;
+
+
+(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mem_read:AccessType ->(32)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ addr width aq rl res= (sail2_state_monad$bindS
+ (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_Load_Addr_Align)
+ else
+ (case (aq, rl, res) of
+ (F, T, F) => sail2_state_monad$throwS (Error_not_implemented "load.rl")
+ | (F, T, T) => sail2_state_monad$throwS (Error_not_implemented "lr.rl")
+ | (_, _, _) => (pmp_mem_read typ addr width aq rl res )
+ )) (\ result .
+ let (_ : unit) = (rvfi_read addr width result) in
+ sail2_state_monad$returnS result)))`;
+
+
+(*val mem_write_ea : mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_ea:(32)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl con=
+ (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (F, F, F) => sail2_state_monad$seqS (write_ram_ea Write_plain addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, T, F) => sail2_state_monad$seqS (write_ram_ea Write_RISCV_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, F, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, T, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+ | (T, T, F) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+ | (T, T, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ )))`;
+
+
+(*val rvfi_write : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> unit*)
+
+val _ = Define `
+ ((rvfi_write:(32)words$word -> int -> 'int8_times_n words$word -> unit) addr width value= () )`;
+
+
+(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((phys_mem_write:write_kind ->(32)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (let (_ : unit) = (rvfi_write addr width data) in sail2_state_monad$bindS
+ (write_ram wk addr width data meta) (\ (w__0 : bool) .
+ let result = (MemValue w__0) in
+ let (_ : unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ ((STRCAT "mem["
+ ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))
+ else () ) in
+ sail2_state_monad$returnS result)))`;
+
+
+(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((checked_mem_write:write_kind ->(32)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (if ((within_mmio_writable addr width)) then mmio_write addr width data
+ else if ((within_phys_mem addr width)) then phys_mem_write wk addr width data meta
+ else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val pmp_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((pmp_mem_write:write_kind ->(32)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (if ((~ ((plat_enable_pmp () )))) then checked_mem_write wk addr width data meta
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . sail2_state_monad$bindS
+ (effectivePrivilege w__1 w__2) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (pmpCheck addr width Write w__3) (\ (w__4 : ExceptionType option) .
+ (case w__4 of
+ NONE => checked_mem_write wk addr width data meta
+ | SOME (e) => sail2_state_monad$returnS (MemException e)
+ )))))))`;
+
+
+(*val mem_write_value_meta : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> unit -> bool -> bool -> bool -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mem_write_value_meta:(32)words$word -> int -> 'int8_times_n words$word -> unit -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value meta aq rl con=
+ (let (_ : unit) = (rvfi_write addr width value) in
+ if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (F, F, F) => pmp_mem_write Write_plain addr width value meta
+ | (F, T, F) => pmp_mem_write Write_RISCV_release addr width value meta
+ | (F, F, T) => pmp_mem_write Write_RISCV_conditional addr width value meta
+ | (F, T, T) => pmp_mem_write Write_RISCV_conditional_release addr width value meta
+ | (T, T, F) => pmp_mem_write Write_RISCV_strong_release addr width value meta
+ | (T, T, T) =>
+ pmp_mem_write Write_RISCV_conditional_strong_release addr width value meta
+ | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+ | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+ )))`;
+
+
+(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mem_write_value:(32)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value aq rl con=
+ (mem_write_value_meta addr width value default_meta aq rl con))`;
+
+
+val _ = Define `
+ ((PAGESIZE_BITS:int)= ((( 12 : int):ii)))`;
+
+
+(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((Mk_PTE_Bits:(8)words$word -> PTE_Bits) v=
+ (<| PTE_Bits_PTE_Bits_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) |>))`;
+
+
+(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*)
+
+val _ = Define `
+ ((get_PTE_Bits_bits:PTE_Bits ->(8)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_PTE_Bits_bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits_bits:PTE_Bits ->(8)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val isPTEPtr : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isPTEPtr:(8)words$word -> bool) p=
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`;
+
+
+(*val isInvalidPTE : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isInvalidPTE:(8)words$word -> bool) p=
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_V a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`;
+
+
+(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+
+val _ = Define `
+ ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p :
+ PTE_Bits)=
+ ((case (ac, priv) of
+ (Read, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))
+ | (Write, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (ReadWrite, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))))))
+ | (Execute, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (Read, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))
+ | (Write, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (ReadWrite, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))))))
+ | (Execute, Supervisor) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (_, Machine) => internal_error "m-mode mem perm check"
+ )))`;
+
+
+(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)=
+ (let update_d =
+ (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in
+ let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in
+ if (((update_d \/ update_a))) then
+ let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in
+ let np = (if update_d then update_PTE_Bits_D np ((bool_to_bits T : 1 words$word)) else np) in
+ SOME np
+ else NONE))`;
+
+
+(*val PTW_Error_of_num : integer -> PTW_Error*)
+
+val _ = Define `
+ ((PTW_Error_of_num:int -> PTW_Error) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PTW_Access
+ else if (((p0_ = (( 1 : int):ii)))) then PTW_Invalid_PTE
+ else if (((p0_ = (( 2 : int):ii)))) then PTW_No_Permission
+ else if (((p0_ = (( 3 : int):ii)))) then PTW_Misaligned
+ else PTW_PTE_Update))`;
+
+
+(*val num_of_PTW_Error : PTW_Error -> integer*)
+
+val _ = Define `
+ ((num_of_PTW_Error:PTW_Error -> int) arg_=
+ ((case arg_ of
+ PTW_Access => (( 0 : int):ii)
+ | PTW_Invalid_PTE => (( 1 : int):ii)
+ | PTW_No_Permission => (( 2 : int):ii)
+ | PTW_Misaligned => (( 3 : int):ii)
+ | PTW_PTE_Update => (( 4 : int):ii)
+ )))`;
+
+
+(*val ptw_error_to_str : PTW_Error -> string*)
+
+val _ = Define `
+ ((ptw_error_to_str:PTW_Error -> string) e=
+ ((case e of
+ PTW_Access => "mem-access-error"
+ | PTW_Invalid_PTE => "invalid-pte"
+ | PTW_No_Permission => "no-permission"
+ | PTW_Misaligned => "misaligned-superpage"
+ | PTW_PTE_Update => "pte-update-needed"
+ )))`;
+
+
+(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+
+val _ = Define `
+ ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)=
+ ((case (a, f) of
+ (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+ | (ReadWrite, _) => E_SAMO_Page_Fault
+ | (Read, PTW_Access) => E_Load_Access_Fault
+ | (Read, _) => E_Load_Page_Fault
+ | (Write, PTW_Access) => E_SAMO_Access_Fault
+ | (Write, _) => E_SAMO_Page_Fault
+ | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+ | (Fetch, _) => E_Fetch_Page_Fault
+ )))`;
+
+
+(*val curAsid32 : mword ty32 -> mword ty9*)
+
+val _ = Define `
+ ((curAsid32:(32)words$word ->(9)words$word) satp1=
+ (let s = (Mk_Satp32 satp1) in
+ (get_Satp32_Asid s : 9 words$word)))`;
+
+
+(*val curPTB32 : mword ty32 -> mword ty34*)
+
+val _ = Define `
+ ((curPTB32:(32)words$word ->(34)words$word) satp1=
+ (let (s : Satp32) = (Mk_Satp32 satp1) in
+ (shiftl ((EXTZ (( 34 : int):ii) ((get_Satp32_PPN s : 22 words$word)) : 34 words$word)) PAGESIZE_BITS
+ : 34 words$word)))`;
+
+
+val _ = Define `
+ ((SV32_LEVEL_BITS:int)= ((( 10 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV32_LEVELS:int)= ((( 2 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE32_LOG_SIZE:int)= ((( 2 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE32_SIZE:int)= ((( 4 : int):ii)))`;
+
+
+(*val Mk_SV32_Vaddr : mword ty32 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV32_Vaddr:(32)words$word -> SV32_Vaddr) v=
+ (<| SV32_Vaddr_SV32_Vaddr_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_bits:SV32_Vaddr ->(32)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_bits : register_ref regstate register_value SV32_Vaddr -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_bits:((regstate),(register_value),(SV32_Vaddr))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_bits:SV32_Vaddr ->(32)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_VPNi:SV32_Vaddr ->(20)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_VPNi : register_ref regstate register_value SV32_Vaddr -> mword ty20 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_VPNi:((regstate),(register_value),(SV32_Vaddr))register_ref ->(20)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 19 : int):ii) (( 0 : int):ii) : 20 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_VPNi:SV32_Vaddr ->(20)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 19 : int):ii) (( 0 : int):ii) : 20 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27 -> SV48_Vaddr*)
+
+(*val _get_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27*)
+
+(*val _set_SV48_Vaddr_VPNi : register_ref regstate register_value SV48_Vaddr -> mword ty27 -> M unit*)
+
+(*val _get_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_PgOfs:SV32_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_PgOfs : register_ref regstate register_value SV32_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_PgOfs:((regstate),(register_value),(SV32_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_PgOfs:SV32_Vaddr ->(12)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12 -> SV48_Paddr*)
+
+(*val _get_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12*)
+
+(*val _set_SV48_Paddr_PgOfs : register_ref regstate register_value SV48_Paddr -> mword ty12 -> M unit*)
+
+(*val Mk_SV32_Paddr : mword ty34 -> SV32_Paddr*)
+
+val _ = Define `
+ ((Mk_SV32_Paddr:(34)words$word -> SV32_Paddr) v=
+ (<| SV32_Paddr_SV32_Paddr_chunk_0 := ((subrange_vec_dec v (( 33 : int):ii) (( 0 : int):ii) : 34 words$word)) |>))`;
+
+
+(*val _get_SV32_Paddr_bits : SV32_Paddr -> mword ty34*)
+
+val _ = Define `
+ ((get_SV32_Paddr_bits:SV32_Paddr ->(34)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii) : 34 words$word)))`;
+
+
+(*val _set_SV32_Paddr_bits : register_ref regstate register_value SV32_Paddr -> mword ty34 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_bits:((regstate),(register_value),(SV32_Paddr))register_ref ->(34)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 33 : int):ii) (( 0 : int):ii) : 34 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_bits : SV32_Paddr -> mword ty34 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_bits:SV32_Paddr ->(34)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 33 : int):ii) (( 0 : int):ii) : 34 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val _get_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22*)
+
+val _ = Define `
+ ((get_SV32_Paddr_PPNi:SV32_Paddr ->(22)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii) : 22 words$word)))`;
+
+
+(*val _set_SV32_Paddr_PPNi : register_ref regstate register_value SV32_Paddr -> mword ty22 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_PPNi:((regstate),(register_value),(SV32_Paddr))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_PPNi:SV32_Paddr ->(22)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_PPNi : SV48_PTE -> mword ty44 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_PPNi : SV48_PTE -> mword ty44*)
+
+(*val _set_SV48_PTE_PPNi : register_ref regstate register_value SV48_PTE -> mword ty44 -> M unit*)
+
+(*val _get_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV32_Paddr_PgOfs:SV32_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV32_Paddr_PgOfs : register_ref regstate register_value SV32_Paddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_PgOfs:((regstate),(register_value),(SV32_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_PgOfs:SV32_Paddr ->(12)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val Mk_SV32_PTE : mword ty32 -> SV32_PTE*)
+
+val _ = Define `
+ ((Mk_SV32_PTE:(32)words$word -> SV32_PTE) v=
+ (<| SV32_PTE_SV32_PTE_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_SV32_PTE_bits : SV32_PTE -> mword ty32*)
+
+val _ = Define `
+ ((get_SV32_PTE_bits:SV32_PTE ->(32)words$word) v=
+ ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_SV32_PTE_bits : register_ref regstate register_value SV32_PTE -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_bits:((regstate),(register_value),(SV32_PTE))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_bits : SV32_PTE -> mword ty32 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_bits:SV32_PTE ->(32)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_PTE_PPNi : SV32_PTE -> mword ty22*)
+
+val _ = Define `
+ ((get_SV32_PTE_PPNi:SV32_PTE ->(22)words$word) v=
+ ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii) : 22 words$word)))`;
+
+
+(*val _set_SV32_PTE_PPNi : register_ref regstate register_value SV32_PTE -> mword ty22 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_PPNi:((regstate),(register_value),(SV32_PTE))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_PPNi : SV32_PTE -> mword ty22 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_PPNi:SV32_PTE ->(22)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_PTE_RSW : SV32_PTE -> mword ty2*)
+
+val _ = Define `
+ ((get_SV32_PTE_RSW:SV32_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_SV32_PTE_RSW : register_ref regstate register_value SV32_PTE -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_RSW:((regstate),(register_value),(SV32_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_RSW : SV32_PTE -> mword ty2 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_RSW:SV32_PTE ->(2)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_RSW : SV48_PTE -> mword ty2 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_RSW : SV48_PTE -> mword ty2*)
+
+(*val _set_SV48_PTE_RSW : register_ref regstate register_value SV48_PTE -> mword ty2 -> M unit*)
+
+(*val _get_SV32_PTE_BITS : SV32_PTE -> mword ty8*)
+
+val _ = Define `
+ ((get_SV32_PTE_BITS:SV32_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_SV32_PTE_BITS : register_ref regstate register_value SV32_PTE -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_BITS:((regstate),(register_value),(SV32_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_BITS : SV32_PTE -> mword ty8 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_BITS:SV32_PTE ->(8)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_BITS : SV48_PTE -> mword ty8 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_BITS : SV48_PTE -> mword ty8*)
+
+(*val _set_SV48_PTE_BITS : register_ref regstate register_value SV48_PTE -> mword ty8 -> M unit*)
+
+(*val curAsid64 : mword ty64 -> mword ty16*)
+
+val _ = Define `
+ ((curAsid64:(64)words$word ->(16)words$word) satp1=
+ (let s = (Mk_Satp64 satp1) in
+ (get_Satp64_Asid s : 16 words$word)))`;
+
+
+(*val curPTB64 : mword ty64 -> mword ty56*)
+
+val _ = Define `
+ ((curPTB64:(64)words$word ->(56)words$word) satp1=
+ (let s = (Mk_Satp64 satp1) in
+ (shiftl ((EXTZ (( 56 : int):ii) ((get_Satp64_PPN s : 44 words$word)) : 56 words$word)) PAGESIZE_BITS
+ : 56 words$word)))`;
+
+
+val _ = Define `
+ ((SV39_LEVEL_BITS:int)= ((( 9 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV39_LEVELS:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_LOG_SIZE:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_SIZE:int)= ((( 8 : int):ii)))`;
+
+
+(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV39_Vaddr:(39)words$word -> SV39_Vaddr) v=
+ (<| SV39_Vaddr_SV39_Vaddr_chunk_0 := ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) |>))`;
+
+
+(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_bits:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((Mk_SV39_Paddr:(56)words$word -> SV39_Paddr) v=
+ (<| SV39_Paddr_SV39_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) |>))`;
+
+
+(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*)
+
+val _ = Define `
+ ((get_SV39_Paddr_bits:SV39_Paddr ->(56)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)))`;
+
+
+(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_bits:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_bits:SV39_Paddr ->(56)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*)
+
+val _ = Define `
+ ((Mk_SV39_PTE:(64)words$word -> SV39_PTE) v=
+ (<| SV39_PTE_SV39_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*)
+
+val _ = Define `
+ ((get_SV39_PTE_bits:SV39_PTE ->(64)words$word) v=
+ ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_bits:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_bits:SV39_PTE ->(64)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+
+val _ = Define `
+ ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) v=
+ ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
+
+val _ = Define `
+ ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+
+val _ = Define `
+ ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((SV48_LEVEL_BITS:int)= ((( 9 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV48_LEVELS:int)= ((( 4 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE48_LOG_SIZE:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE48_SIZE:int)= ((( 8 : int):ii)))`;
+
+
+(*val Mk_SV48_Vaddr : mword ty48 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV48_Vaddr:(48)words$word -> SV48_Vaddr) v=
+ (<| SV48_Vaddr_SV48_Vaddr_chunk_0 := ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) |>))`;
+
+
+(*val _get_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48*)
+
+val _ = Define `
+ ((get_SV48_Vaddr_bits:SV48_Vaddr ->(48)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))`;
+
+
+(*val _set_SV48_Vaddr_bits : register_ref regstate register_value SV48_Vaddr -> mword ty48 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Vaddr_bits:((regstate),(register_value),(SV48_Vaddr))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((update_SV48_Vaddr_bits:SV48_Vaddr ->(48)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 48 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_Vaddr_VPNi:SV48_Vaddr ->(27)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_Vaddr_VPNi:((regstate),(register_value),(SV48_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_Vaddr_VPNi:SV48_Vaddr ->(27)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 48 words$word))|>)))`;
+
+
+(*val _get_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV48_Vaddr_PgOfs:SV48_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV48_Vaddr_PgOfs : register_ref regstate register_value SV48_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Vaddr_PgOfs:((regstate),(register_value),(SV48_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((update_SV48_Vaddr_PgOfs:SV48_Vaddr ->(12)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 48 words$word))|>)))`;
+
+
+(*val Mk_SV48_Paddr : mword ty56 -> SV48_Paddr*)
+
+val _ = Define `
+ ((Mk_SV48_Paddr:(56)words$word -> SV48_Paddr) v=
+ (<| SV48_Paddr_SV48_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) |>))`;
+
+
+(*val _get_SV48_Paddr_bits : SV48_Paddr -> mword ty56*)
+
+val _ = Define `
+ ((get_SV48_Paddr_bits:SV48_Paddr ->(56)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)))`;
+
+
+(*val _set_SV48_Paddr_bits : register_ref regstate register_value SV48_Paddr -> mword ty56 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Paddr_bits:((regstate),(register_value),(SV48_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Paddr_bits : SV48_Paddr -> mword ty56 -> SV48_Paddr*)
+
+val _ = Define `
+ ((update_SV48_Paddr_bits:SV48_Paddr ->(56)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44*)
+
+val _ = Define `
+ ((get_SV48_Paddr_PPNi:SV48_Paddr ->(44)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV48_Paddr_PPNi : register_ref regstate register_value SV48_Paddr -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Paddr_PPNi:((regstate),(register_value),(SV48_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44 -> SV48_Paddr*)
+
+val _ = Define `
+ ((update_SV48_Paddr_PPNi:SV48_Paddr ->(44)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_Paddr_PgOfs:SV48_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_Paddr_PgOfs:((regstate),(register_value),(SV48_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_Paddr_PgOfs:SV48_Paddr ->(12)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val Mk_SV48_PTE : mword ty64 -> SV48_PTE*)
+
+val _ = Define `
+ ((Mk_SV48_PTE:(64)words$word -> SV48_PTE) v=
+ (<| SV48_PTE_SV48_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_bits:SV48_PTE ->(64)words$word) v=
+ ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_bits:((regstate),(register_value),(SV48_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_bits:SV48_PTE ->(64)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_PPNi:SV48_PTE ->(44)words$word) v=
+ ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_PPNi:((regstate),(register_value),(SV48_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_PPNi:SV48_PTE ->(44)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_RSW:SV48_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_RSW:((regstate),(register_value),(SV48_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_RSW:SV48_PTE ->(2)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_BITS:SV48_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_BITS:((regstate),(register_value),(SV48_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_BITS:SV48_PTE ->(8)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val make_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'palen, Size 'ptelen, Size 'valen => mword 'asidlen -> bool -> mword 'valen -> mword 'palen -> mword 'ptelen -> ii -> mword 'palen -> ii -> M (TLB_Entry 'asidlen 'valen 'palen 'ptelen)*)
+
+val _ = Define `
+ ((make_TLB_Entry:'asidlen words$word -> bool -> 'valen words$word -> 'palen words$word -> 'ptelen words$word -> int -> 'palen words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('asidlen,'valen,'palen,'ptelen)TLB_Entry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr levelBitSize=
+ (let (shift : ii) = (PAGESIZE_BITS + ((level * levelBitSize))) in
+ let vAddrMask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec vAddr
+ ((xor_vec vAddr
+ ((EXTZ ((int_of_num (words$word_len vAddr))) (vec_of_bits [B1] : 1 words$word) : 'valen words$word))
+ : 'valen words$word))
+ : 'valen words$word)) shift
+ : 'valen words$word)) (( 1 : int):ii)
+ : 'valen words$word)) in
+ let vMatchMask = ((not_vec vAddrMask : 'valen words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS (<| TLB_Entry_asid := asid;
+ TLB_Entry_global := global;
+ TLB_Entry_pte := pte;
+ TLB_Entry_pteAddr := pteAddr;
+ TLB_Entry_vAddrMask := vAddrMask;
+ TLB_Entry_vMatchMask := vMatchMask;
+ TLB_Entry_vAddr := ((and_vec vAddr vMatchMask : 'valen words$word));
+ TLB_Entry_pAddr :=
+ ((shiftl ((shiftr pAddr shift : 'palen words$word)) shift : 'palen words$word));
+ TLB_Entry_age := w__0 |>))))`;
+
+
+(*val match_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> mword 'asidlen -> mword 'valen -> bool*)
+
+val _ = Define `
+ ((match_TLB_Entry:('asidlen,'valen,'palen,'ptelen)TLB_Entry -> 'asidlen words$word -> 'valen words$word -> bool) ent asid vaddr=
+ ((((ent.TLB_Entry_global \/ (((ent.TLB_Entry_asid = asid)))))) /\ (((ent.TLB_Entry_vAddr = ((and_vec ent.TLB_Entry_vMatchMask vaddr : 'valen words$word)))))))`;
+
+
+(*val flush_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> maybe (mword 'asidlen) -> maybe (mword 'valen) -> bool*)
+
+val _ = Define `
+ ((flush_TLB_Entry:('asidlen,'valen,'palen,'ptelen)TLB_Entry ->('asidlen words$word)option ->('valen words$word)option -> bool) e asid addr=
+ ((case (asid, addr) of
+ (NONE, NONE) => T
+ | (NONE, SOME (a)) =>
+ (e.TLB_Entry_vAddr = ((and_vec e.TLB_Entry_vMatchMask a : 'valen words$word)))
+ | (SOME (i), NONE) => ((((e.TLB_Entry_asid = i))) /\ ((~ e.TLB_Entry_global)))
+ | (SOME (i), SOME (a)) =>
+ ((((e.TLB_Entry_asid = i))) /\ ((((((e.TLB_Entry_vAddr = ((and_vec a e.TLB_Entry_vMatchMask : 'valen words$word))))) /\ ((~ e.TLB_Entry_global))))))
+ )))`;
+
+
+(*val to_phys_addr : mword ty34 -> mword ty32*)
+
+val _ = Define `
+ ((to_phys_addr:(34)words$word ->(32)words$word) a= ((subrange_vec_dec a (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val walk32 : mword ty32 -> AccessType -> Privilege -> bool -> bool -> mword ty34 -> ii -> bool -> M (PTW_Result (mword ty34) SV32_PTE)*)
+
+ val walk32_defn = Hol_defn "walk32" `
+ ((walk32:(32)words$word -> AccessType -> Privilege -> bool -> bool ->(34)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->((((((34)words$word),(SV32_PTE))PTW_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global=
+ (let va = (Mk_SV32_Vaddr vaddr) in
+ let (pt_ofs : paddr32) =
+ ((shiftl
+ ((EXTZ (( 34 : int):ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV32_Vaddr_VPNi va : 20 words$word))
+ ((level * SV32_LEVEL_BITS))
+ : 20 words$word)) ((SV32_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii)
+ : 10 words$word))
+ : 34 words$word)) PTE32_LOG_SIZE
+ : 34 words$word)) in
+ let pte_addr = ((add_vec ptb pt_ofs : 34 words$word)) in sail2_state_monad$bindS
+ (mem_read ac ((to_phys_addr pte_addr : 32 words$word)) (( 4 : int):ii) F F F
+ : ( ( 32 words$word)MemoryOpResult) M) (\ (w__0 : ( 32 words$word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => sail2_state_monad$returnS (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ let pte = (Mk_SV32_PTE v) in
+ let pbits = ((get_SV32_PTE_BITS pte : 8 words$word)) in
+ let pattr = (Mk_PTE_Bits pbits) in
+ let is_global =
+ (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in
+ if ((isInvalidPTE pbits)) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 : int):ii)))) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk32 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 34 : int):ii) ((get_SV32_PTE_PPNi pte : 22 words$word)) : 34 words$word))
+ PAGESIZE_BITS
+ : 34 words$word)) ((level - (( 1 : int):ii))) is_global
+ : ( (( 34 words$word), SV32_PTE)PTW_Result) M)
+ else sail2_state_monad$bindS
+ (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) .
+ sail2_state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 : int):ii))) then
+ let mask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV32_PTE_PPNi pte : 22 words$word))
+ ((xor_vec ((get_SV32_PTE_PPNi pte : 22 words$word))
+ ((EXTZ (( 22 : int):ii) (vec_of_bits [B1] : 1 words$word) : 22 words$word))
+ : 22 words$word))
+ : 22 words$word)) ((level * SV32_LEVEL_BITS))
+ : 22 words$word)) (( 1 : int):ii)
+ : 22 words$word)) in
+ if (((((and_vec ((get_SV32_PTE_PPNi pte : 22 words$word)) mask : 22 words$word)) <> ((EXTZ (( 22 : int):ii) (vec_of_bits [B0] : 1 words$word) : 22 words$word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ let ppn =
+ ((or_vec ((get_SV32_PTE_PPNi pte : 22 words$word))
+ ((and_vec
+ ((EXTZ (( 22 : int):ii) ((get_SV32_Vaddr_VPNi va : 20 words$word)) : 22 words$word))
+ mask
+ : 22 words$word))
+ : 22 words$word)) in
+ PTW_Success ((concat_vec ppn ((get_SV32_Vaddr_PgOfs va : 12 words$word))
+ : 34 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)
+ else
+ PTW_Success ((concat_vec ((get_SV32_PTE_PPNi pte : 22 words$word))
+ ((get_SV32_Vaddr_PgOfs va : 12 words$word))
+ : 34 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ ))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk32_defn;
+
+(*val lookup_TLB32 : mword ty9 -> mword ty32 -> M (maybe ((ii * TLB_Entry ty9 ty32 ty34 ty32)))*)
+
+val _ = Define `
+ ((lookup_TLB32:(9)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((int#((9),(32),(34),(32))TLB_Entry)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vaddr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb32_ref) (\ (w__0 : ( (9, 32, 34, 32)TLB_Entry)option) .
+ sail2_state_monad$returnS ((case w__0 of
+ NONE => NONE
+ | SOME (e) => if ((match_TLB_Entry e asid vaddr)) then SOME ((( 0 : int):ii), e) else NONE
+ )))))`;
+
+
+(*val add_to_TLB32 : mword ty9 -> mword ty32 -> mword ty34 -> SV32_PTE -> mword ty34 -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((add_to_TLB32:(9)words$word ->(32)words$word ->(34)words$word -> SV32_PTE ->(34)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (sail2_state_monad$bindS
+ (make_TLB_Entry asid global vAddr pAddr ((get_SV32_PTE_bits pte : 32 words$word)) level pteAddr
+ SV32_LEVEL_BITS) (\ (ent : TLB32_Entry) .
+ sail2_state_monad$write_regS tlb32_ref (SOME ent))))`;
+
+
+(*val write_TLB32 : ii -> TLB_Entry ty9 ty32 ty34 ty32 -> M unit*)
+
+val _ = Define `
+ ((write_TLB32:int ->((9),(32),(34),(32))TLB_Entry ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (idx : ii) (ent : TLB32_Entry)= (sail2_state_monad$write_regS tlb32_ref (SOME ent)))`;
+
+
+(*val flush_TLB32 : maybe (mword ty9) -> maybe (mword ty32) -> M unit*)
+
+val _ = Define `
+ ((flush_TLB32:((9)words$word)option ->((32)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid addr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb32_ref) (\ (w__0 : ( (9, 32, 34, 32)TLB_Entry)option) .
+ (case w__0 of
+ NONE => sail2_state_monad$returnS ()
+ | SOME (e) => if ((flush_TLB_Entry e asid addr)) then sail2_state_monad$write_regS tlb32_ref NONE else sail2_state_monad$returnS ()
+ ))))`;
+
+
+(*val translate32 : mword ty9 -> mword ty34 -> mword ty32 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty34) PTW_Error)*)
+
+val _ = Define `
+ ((translate32:(9)words$word ->(34)words$word ->(32)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->((((((34)words$word),(PTW_Error))TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid ptb vAddr ac priv mxr do_sum level= (sail2_state_monad$bindS
+ (lookup_TLB32 asid vAddr) (\ (w__0 : ((ii # (9, 32, 34, 32) TLB_Entry))option) .
+ (case w__0 of
+ SOME ((idx, ent)) =>
+ let pte = (Mk_SV32_PTE ent.TLB_Entry_pte) in
+ let pteBits = (Mk_PTE_Bits ((get_SV32_PTE_BITS pte : 8 words$word))) in sail2_state_monad$bindS
+ (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) .
+ if ((~ w__1)) then sail2_state_monad$returnS (TR_Failure PTW_No_Permission)
+ else
+ (case ((update_PTE_Bits pteBits ac)) of
+ NONE =>
+ sail2_state_monad$returnS (TR_Address ((or_vec ent.TLB_Entry_pAddr
+ ((EXTZ (( 34 : int):ii)
+ ((and_vec vAddr ent.TLB_Entry_vAddrMask : 32 words$word))
+ : 34 words$word))
+ : 34 words$word)))
+ | SOME (pbits) =>
+ if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR_Failure PTW_PTE_Update)
+ else
+ let n_pte = (update_SV32_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in
+ let (n_ent : TLB32_Entry) = ent in
+ let n_ent = ((n_ent with<| TLB_Entry_pte := ((get_SV32_PTE_bits n_pte : 32 words$word))|>)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (write_TLB32 idx n_ent)
+ (mem_write_value
+ ((to_phys_addr ((EXTZ (( 34 : int):ii) ent.TLB_Entry_pteAddr : 34 words$word)) : 32 words$word))
+ (( 4 : int):ii) ((get_SV32_PTE_bits n_pte : 32 words$word)) F F F)) (\ (w__2 : bool
+ MemoryOpResult) . sail2_state_monad$seqS
+ (case w__2 of
+ MemValue (_) => sail2_state_monad$returnS ()
+ | MemException (e) => internal_error "invalid physical address in TLB"
+ )
+ (sail2_state_monad$returnS (TR_Address ((or_vec ent.TLB_Entry_pAddr
+ ((EXTZ (( 34 : int):ii)
+ ((and_vec vAddr ent.TLB_Entry_vAddrMask : 32 words$word))
+ : 34 words$word))
+ : 34 words$word)))))
+ ))
+ | NONE => sail2_state_monad$bindS
+ (walk32 vAddr ac priv mxr do_sum ptb level F : ( (( 34 words$word), SV32_PTE)PTW_Result) M) (\ (w__6 : (( 34 words$word), SV32_PTE)
+ PTW_Result) .
+ (case w__6 of
+ PTW_Failure (f) => sail2_state_monad$returnS (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV32_PTE_BITS pte : 8 words$word)))) ac)) of
+ NONE => sail2_state_monad$seqS
+ (add_to_TLB32 asid vAddr pAddr pte pteAddr level global) (sail2_state_monad$returnS (TR_Address pAddr))
+ | SOME (pbits) =>
+ if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR_Failure PTW_PTE_Update)
+ else
+ let (w_pte : SV32_PTE) =
+ (update_SV32_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in sail2_state_monad$bindS
+ (mem_write_value ((to_phys_addr pteAddr : 32 words$word)) (( 4 : int):ii)
+ ((get_SV32_PTE_bits w_pte : 32 words$word)) F F F) (\ (w__7 : bool
+ MemoryOpResult) .
+ (case w__7 of
+ MemValue (_) => sail2_state_monad$seqS
+ (add_to_TLB32 asid vAddr pAddr w_pte pteAddr level global)
+ (sail2_state_monad$returnS (TR_Address pAddr))
+ | MemException (e) => sail2_state_monad$returnS (TR_Failure PTW_Access)
+ ))
+ )
+ ))
+ ))))`;
+
+
+(*val init_vmem_sv32 : unit -> M unit*)
+
+val _ = Define `
+ ((init_vmem_sv32:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS tlb32_ref NONE))`;
+
+
+(*val legalize_satp : Architecture -> mword ty32 -> mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((legalize_satp:Architecture ->(32)words$word ->(32)words$word ->(32)words$word) (a : Architecture) (o1 : xlenbits) (v : xlenbits)=
+ ((legalize_satp32 a o1 v : 32 words$word)))`;
+
+
+(*val translationMode : Privilege -> M SATPMode*)
+
+val _ = Define `
+ ((translationMode:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((SATPMode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv=
+ (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ then
+ sail2_state_monad$returnS Sbare
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ let arch = (architecture ((get_mstatus_SXL w__0 : 2 words$word))) in
+ (case arch of
+ SOME (RV32) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ let s = (Mk_Satp32 ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in
+ sail2_state_monad$returnS (if (((((get_Satp32_Mode s : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))
+ then
+ Sbare
+ else Sv32))
+ | _ => internal_error "unsupported address translation arch"
+ ))))`;
+
+
+(*val translateAddr : mword ty32 -> AccessType -> M (TR_Result (mword ty32) ExceptionType)*)
+
+val _ = Define `
+ ((translateAddr:(32)words$word -> AccessType ->(regstate)sail2_state_monad$sequential_state ->((((((32)words$word),(ExceptionType))TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac= (sail2_state_monad$bindS
+ (case ac of
+ Execute => sail2_state_monad$read_regS cur_privilege_ref
+ | _ => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . effectivePrivilege w__1 w__2))
+ ) (\ (effPriv : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ let (mxr : bool) =
+ (((get_Mstatus_MXR w__4 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) .
+ let (do_sum : bool) =
+ (((get_Mstatus_SUM w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS
+ (translationMode effPriv) (\ (mode : SATPMode) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) .
+ let asid = ((curAsid32 w__6 : 9 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M) (\ (w__7 : 32 words$word) .
+ let ptb = ((curPTB32 w__7 : 34 words$word)) in
+ (case mode of
+ Sbare => sail2_state_monad$returnS (TR_Address vAddr)
+ | Sv32 => sail2_state_monad$bindS
+ (translate32 asid ptb vAddr ac effPriv mxr do_sum ((SV32_LEVELS - (( 1 : int):ii)))
+ : ( (( 34 words$word), PTW_Error)TR_Result) M) (\ (w__8 : (( 34 words$word), PTW_Error) TR_Result) .
+ sail2_state_monad$returnS ((case w__8 of
+ TR_Address (pa) => TR_Address ((to_phys_addr pa : 32 words$word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | _ =>
+ (internal_error "unsupported address translation scheme"
+ : ( (( 32 words$word), ExceptionType)TR_Result) M)
+ )))))))))`;
+
+
+(*val flush_TLB : maybe (mword ty32) -> maybe (mword ty32) -> M unit*)
+
+val _ = Define `
+ ((flush_TLB:((32)words$word)option ->((32)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid_xlen addr_xlen=
+ (let (asid : asid32 option) =
+ ((case asid_xlen of
+ NONE => NONE
+ | SOME (a) => SOME ((subrange_vec_dec a (( 8 : int):ii) (( 0 : int):ii) : 9 words$word))
+ )) in
+ flush_TLB32 asid addr_xlen))`;
+
+
+(*val init_vmem : unit -> M unit*)
+
+val _ = Define `
+ ((init_vmem:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (init_vmem_sv32 () ))`;
+
+
+(*val execute : ast -> M Retired*)
+
+(*val encdec_uop_forwards : uop -> mword ty7*)
+
+val _ = Define `
+ ((encdec_uop_forwards:uop ->(7)words$word) arg_=
+ ((case arg_ of
+ RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)
+ | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)
+ )))`;
+
+
+(*val encdec_uop_backwards : mword ty7 -> M uop*)
+
+val _ = Define `
+ ((encdec_uop_backwards:(7)words$word ->(regstate)sail2_state_monad$sequential_state ->(((uop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then sail2_state_monad$returnS RISCV_LUI
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then sail2_state_monad$returnS RISCV_AUIPC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_uop_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((encdec_uop_forwards_matches:uop -> bool) arg_=
+ ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val encdec_uop_backwards_matches : mword ty7 -> bool*)
+
+val _ = Define `
+ ((encdec_uop_backwards_matches:(7)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then T
+ else F))`;
+
+
+(*val utype_mnemonic_forwards : uop -> string*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards:uop -> string) arg_= ((case arg_ of RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" )))`;
+
+
+(*val utype_mnemonic_backwards : string -> M uop*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((uop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "lui"))) then sail2_state_monad$returnS RISCV_LUI
+ else if (((p0_ = "auipc"))) then sail2_state_monad$returnS RISCV_AUIPC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val utype_mnemonic_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards_matches:uop -> bool) arg_=
+ ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val utype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "lui"))) then T
+ else if (((p0_ = "auipc"))) then T
+ else F))`;
+
+
+(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*)
+
+(*val _s496_ : string -> maybe string*)
+
+val _ = Define `
+ ((s496_:string ->(string)option) s497_0=
+ (let s498_0 = s497_0 in
+ if ((string_startswith s498_0 "auipc")) then
+ (case ((string_drop s498_0 ((string_length "auipc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s492_ : string -> maybe string*)
+
+val _ = Define `
+ ((s492_:string ->(string)option) s493_0=
+ (let s494_0 = s493_0 in
+ if ((string_startswith s494_0 "lui")) then
+ (case ((string_drop s494_0 ((string_length "lui")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((utype_mnemonic_matches_prefix:string ->(uop#int)option) arg_=
+ (let s495_0 = arg_ in
+ if ((case ((s492_ s495_0)) of SOME (s_) => T | _ => F )) then
+ (case s492_ s495_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_LUI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s496_ s495_0)) of SOME (s_) => T | _ => F )) then
+ (case s496_ s495_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_AUIPC, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_bop_forwards : bop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_bop_forwards:bop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_BEQ => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | RISCV_BNE => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | RISCV_BLT => (vec_of_bits [B1;B0;B0] : 3 words$word)
+ | RISCV_BGE => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : 3 words$word)
+ | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_bop_backwards : mword ty3 -> M bop*)
+
+val _ = Define `
+ ((encdec_bop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BEQ
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BNE
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BLT
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BGE
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BLTU
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BGEU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_bop_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((encdec_bop_forwards_matches:bop -> bool) arg_=
+ ((case arg_ of
+ RISCV_BEQ => T
+ | RISCV_BNE => T
+ | RISCV_BLT => T
+ | RISCV_BGE => T
+ | RISCV_BLTU => T
+ | RISCV_BGEU => T
+ )))`;
+
+
+(*val encdec_bop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_bop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val btype_mnemonic_forwards : bop -> string*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards:bop -> string) arg_=
+ ((case arg_ of
+ RISCV_BEQ => "beq"
+ | RISCV_BNE => "bne"
+ | RISCV_BLT => "blt"
+ | RISCV_BGE => "bge"
+ | RISCV_BLTU => "bltu"
+ | RISCV_BGEU => "bgeu"
+ )))`;
+
+
+(*val btype_mnemonic_backwards : string -> M bop*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "beq"))) then sail2_state_monad$returnS RISCV_BEQ
+ else if (((p0_ = "bne"))) then sail2_state_monad$returnS RISCV_BNE
+ else if (((p0_ = "blt"))) then sail2_state_monad$returnS RISCV_BLT
+ else if (((p0_ = "bge"))) then sail2_state_monad$returnS RISCV_BGE
+ else if (((p0_ = "bltu"))) then sail2_state_monad$returnS RISCV_BLTU
+ else if (((p0_ = "bgeu"))) then sail2_state_monad$returnS RISCV_BGEU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val btype_mnemonic_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards_matches:bop -> bool) arg_=
+ ((case arg_ of
+ RISCV_BEQ => T
+ | RISCV_BNE => T
+ | RISCV_BLT => T
+ | RISCV_BGE => T
+ | RISCV_BLTU => T
+ | RISCV_BGEU => T
+ )))`;
+
+
+(*val btype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "beq"))) then T
+ else if (((p0_ = "bne"))) then T
+ else if (((p0_ = "blt"))) then T
+ else if (((p0_ = "bge"))) then T
+ else if (((p0_ = "bltu"))) then T
+ else if (((p0_ = "bgeu"))) then T
+ else F))`;
+
+
+(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*)
+
+(*val _s520_ : string -> maybe string*)
+
+val _ = Define `
+ ((s520_:string ->(string)option) s521_0=
+ (let s522_0 = s521_0 in
+ if ((string_startswith s522_0 "bgeu")) then
+ (case ((string_drop s522_0 ((string_length "bgeu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s516_ : string -> maybe string*)
+
+val _ = Define `
+ ((s516_:string ->(string)option) s517_0=
+ (let s518_0 = s517_0 in
+ if ((string_startswith s518_0 "bltu")) then
+ (case ((string_drop s518_0 ((string_length "bltu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s512_ : string -> maybe string*)
+
+val _ = Define `
+ ((s512_:string ->(string)option) s513_0=
+ (let s514_0 = s513_0 in
+ if ((string_startswith s514_0 "bge")) then
+ (case ((string_drop s514_0 ((string_length "bge")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s508_ : string -> maybe string*)
+
+val _ = Define `
+ ((s508_:string ->(string)option) s509_0=
+ (let s510_0 = s509_0 in
+ if ((string_startswith s510_0 "blt")) then
+ (case ((string_drop s510_0 ((string_length "blt")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s504_ : string -> maybe string*)
+
+val _ = Define `
+ ((s504_:string ->(string)option) s505_0=
+ (let s506_0 = s505_0 in
+ if ((string_startswith s506_0 "bne")) then
+ (case ((string_drop s506_0 ((string_length "bne")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s500_ : string -> maybe string*)
+
+val _ = Define `
+ ((s500_:string ->(string)option) s501_0=
+ (let s502_0 = s501_0 in
+ if ((string_startswith s502_0 "beq")) then
+ (case ((string_drop s502_0 ((string_length "beq")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((btype_mnemonic_matches_prefix:string ->(bop#int)option) arg_=
+ (let s503_0 = arg_ in
+ if ((case ((s500_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s500_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BEQ, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s504_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s504_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BNE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s508_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s508_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BLT, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s512_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s512_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BGE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s516_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s516_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BLTU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s520_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s520_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BGEU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_iop_forwards : iop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_iop_forwards:iop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_ADDI => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : 3 words$word)
+ | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : 3 words$word)
+ | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : 3 words$word)
+ | RISCV_ORI => (vec_of_bits [B1;B1;B0] : 3 words$word)
+ | RISCV_XORI => (vec_of_bits [B1;B0;B0] : 3 words$word)
+ )))`;
+
+
+(*val encdec_iop_backwards : mword ty3 -> M iop*)
+
+val _ = Define `
+ ((encdec_iop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((iop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ADDI
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLTI
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLTIU
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ANDI
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ORI
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_XORI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_iop_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((encdec_iop_forwards_matches:iop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDI => T
+ | RISCV_SLTI => T
+ | RISCV_SLTIU => T
+ | RISCV_ANDI => T
+ | RISCV_ORI => T
+ | RISCV_XORI => T
+ )))`;
+
+
+(*val encdec_iop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_iop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val itype_mnemonic_forwards : iop -> string*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards:iop -> string) arg_=
+ ((case arg_ of
+ RISCV_ADDI => "addi"
+ | RISCV_SLTI => "slti"
+ | RISCV_SLTIU => "sltiu"
+ | RISCV_XORI => "xori"
+ | RISCV_ORI => "ori"
+ | RISCV_ANDI => "andi"
+ )))`;
+
+
+(*val itype_mnemonic_backwards : string -> M iop*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((iop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addi"))) then sail2_state_monad$returnS RISCV_ADDI
+ else if (((p0_ = "slti"))) then sail2_state_monad$returnS RISCV_SLTI
+ else if (((p0_ = "sltiu"))) then sail2_state_monad$returnS RISCV_SLTIU
+ else if (((p0_ = "xori"))) then sail2_state_monad$returnS RISCV_XORI
+ else if (((p0_ = "ori"))) then sail2_state_monad$returnS RISCV_ORI
+ else if (((p0_ = "andi"))) then sail2_state_monad$returnS RISCV_ANDI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val itype_mnemonic_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards_matches:iop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDI => T
+ | RISCV_SLTI => T
+ | RISCV_SLTIU => T
+ | RISCV_XORI => T
+ | RISCV_ORI => T
+ | RISCV_ANDI => T
+ )))`;
+
+
+(*val itype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addi"))) then T
+ else if (((p0_ = "slti"))) then T
+ else if (((p0_ = "sltiu"))) then T
+ else if (((p0_ = "xori"))) then T
+ else if (((p0_ = "ori"))) then T
+ else if (((p0_ = "andi"))) then T
+ else F))`;
+
+
+(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*)
+
+(*val _s544_ : string -> maybe string*)
+
+val _ = Define `
+ ((s544_:string ->(string)option) s545_0=
+ (let s546_0 = s545_0 in
+ if ((string_startswith s546_0 "andi")) then
+ (case ((string_drop s546_0 ((string_length "andi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s540_ : string -> maybe string*)
+
+val _ = Define `
+ ((s540_:string ->(string)option) s541_0=
+ (let s542_0 = s541_0 in
+ if ((string_startswith s542_0 "ori")) then
+ (case ((string_drop s542_0 ((string_length "ori")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s536_ : string -> maybe string*)
+
+val _ = Define `
+ ((s536_:string ->(string)option) s537_0=
+ (let s538_0 = s537_0 in
+ if ((string_startswith s538_0 "xori")) then
+ (case ((string_drop s538_0 ((string_length "xori")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s532_ : string -> maybe string*)
+
+val _ = Define `
+ ((s532_:string ->(string)option) s533_0=
+ (let s534_0 = s533_0 in
+ if ((string_startswith s534_0 "sltiu")) then
+ (case ((string_drop s534_0 ((string_length "sltiu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s528_ : string -> maybe string*)
+
+val _ = Define `
+ ((s528_:string ->(string)option) s529_0=
+ (let s530_0 = s529_0 in
+ if ((string_startswith s530_0 "slti")) then
+ (case ((string_drop s530_0 ((string_length "slti")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s524_ : string -> maybe string*)
+
+val _ = Define `
+ ((s524_:string ->(string)option) s525_0=
+ (let s526_0 = s525_0 in
+ if ((string_startswith s526_0 "addi")) then
+ (case ((string_drop s526_0 ((string_length "addi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((itype_mnemonic_matches_prefix:string ->(iop#int)option) arg_=
+ (let s527_0 = arg_ in
+ if ((case ((s524_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s524_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADDI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s528_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s528_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s532_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s532_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTIU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s536_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s536_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_XORI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s540_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s540_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ORI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s544_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s544_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ANDI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_sop_forwards : sop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_sop_forwards:sop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_SLLI => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_sop_backwards : mword ty3 -> M sop*)
+
+val _ = Define `
+ ((encdec_sop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_sop_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((encdec_sop_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val encdec_sop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_sop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val shiftiop_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards:sop -> string) arg_=
+ ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftiop_mnemonic_backwards : string -> M sop*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((p0_ = "srli"))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((p0_ = "srai"))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftiop_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftiop_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then T
+ else if (((p0_ = "srli"))) then T
+ else if (((p0_ = "srai"))) then T
+ else F))`;
+
+
+(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+(*val _s556_ : string -> maybe string*)
+
+val _ = Define `
+ ((s556_:string ->(string)option) s557_0=
+ (let s558_0 = s557_0 in
+ if ((string_startswith s558_0 "srai")) then
+ (case ((string_drop s558_0 ((string_length "srai")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s552_ : string -> maybe string*)
+
+val _ = Define `
+ ((s552_:string ->(string)option) s553_0=
+ (let s554_0 = s553_0 in
+ if ((string_startswith s554_0 "srli")) then
+ (case ((string_drop s554_0 ((string_length "srli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s548_ : string -> maybe string*)
+
+val _ = Define `
+ ((s548_:string ->(string)option) s549_0=
+ (let s550_0 = s549_0 in
+ if ((string_startswith s550_0 "slli")) then
+ (case ((string_drop s550_0 ((string_length "slli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftiop_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+ (let s551_0 = arg_ in
+ if ((case ((s548_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s548_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s552_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s552_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s556_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s556_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val rtype_mnemonic_forwards : rop -> string*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards:rop -> string) arg_=
+ ((case arg_ of
+ RISCV_ADD => "add"
+ | RISCV_SLT => "slt"
+ | RISCV_SLTU => "sltu"
+ | RISCV_AND => "and"
+ | RISCV_OR => "or"
+ | RISCV_XOR => "xor"
+ | RISCV_SLL => "sll"
+ | RISCV_SRL => "srl"
+ | RISCV_SUB => "sub"
+ | RISCV_SRA => "sra"
+ )))`;
+
+
+(*val rtype_mnemonic_backwards : string -> M rop*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((rop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "add"))) then sail2_state_monad$returnS RISCV_ADD
+ else if (((p0_ = "slt"))) then sail2_state_monad$returnS RISCV_SLT
+ else if (((p0_ = "sltu"))) then sail2_state_monad$returnS RISCV_SLTU
+ else if (((p0_ = "and"))) then sail2_state_monad$returnS RISCV_AND
+ else if (((p0_ = "or"))) then sail2_state_monad$returnS RISCV_OR
+ else if (((p0_ = "xor"))) then sail2_state_monad$returnS RISCV_XOR
+ else if (((p0_ = "sll"))) then sail2_state_monad$returnS RISCV_SLL
+ else if (((p0_ = "srl"))) then sail2_state_monad$returnS RISCV_SRL
+ else if (((p0_ = "sub"))) then sail2_state_monad$returnS RISCV_SUB
+ else if (((p0_ = "sra"))) then sail2_state_monad$returnS RISCV_SRA
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val rtype_mnemonic_forwards_matches : rop -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards_matches:rop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADD => T
+ | RISCV_SLT => T
+ | RISCV_SLTU => T
+ | RISCV_AND => T
+ | RISCV_OR => T
+ | RISCV_XOR => T
+ | RISCV_SLL => T
+ | RISCV_SRL => T
+ | RISCV_SUB => T
+ | RISCV_SRA => T
+ )))`;
+
+
+(*val rtype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "add"))) then T
+ else if (((p0_ = "slt"))) then T
+ else if (((p0_ = "sltu"))) then T
+ else if (((p0_ = "and"))) then T
+ else if (((p0_ = "or"))) then T
+ else if (((p0_ = "xor"))) then T
+ else if (((p0_ = "sll"))) then T
+ else if (((p0_ = "srl"))) then T
+ else if (((p0_ = "sub"))) then T
+ else if (((p0_ = "sra"))) then T
+ else F))`;
+
+
+(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*)
+
+(*val _s596_ : string -> maybe string*)
+
+val _ = Define `
+ ((s596_:string ->(string)option) s597_0=
+ (let s598_0 = s597_0 in
+ if ((string_startswith s598_0 "sra")) then
+ (case ((string_drop s598_0 ((string_length "sra")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s592_ : string -> maybe string*)
+
+val _ = Define `
+ ((s592_:string ->(string)option) s593_0=
+ (let s594_0 = s593_0 in
+ if ((string_startswith s594_0 "sub")) then
+ (case ((string_drop s594_0 ((string_length "sub")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s588_ : string -> maybe string*)
+
+val _ = Define `
+ ((s588_:string ->(string)option) s589_0=
+ (let s590_0 = s589_0 in
+ if ((string_startswith s590_0 "srl")) then
+ (case ((string_drop s590_0 ((string_length "srl")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s584_ : string -> maybe string*)
+
+val _ = Define `
+ ((s584_:string ->(string)option) s585_0=
+ (let s586_0 = s585_0 in
+ if ((string_startswith s586_0 "sll")) then
+ (case ((string_drop s586_0 ((string_length "sll")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s580_ : string -> maybe string*)
+
+val _ = Define `
+ ((s580_:string ->(string)option) s581_0=
+ (let s582_0 = s581_0 in
+ if ((string_startswith s582_0 "xor")) then
+ (case ((string_drop s582_0 ((string_length "xor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s576_ : string -> maybe string*)
+
+val _ = Define `
+ ((s576_:string ->(string)option) s577_0=
+ (let s578_0 = s577_0 in
+ if ((string_startswith s578_0 "or")) then
+ (case ((string_drop s578_0 ((string_length "or")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s572_ : string -> maybe string*)
+
+val _ = Define `
+ ((s572_:string ->(string)option) s573_0=
+ (let s574_0 = s573_0 in
+ if ((string_startswith s574_0 "and")) then
+ (case ((string_drop s574_0 ((string_length "and")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s568_ : string -> maybe string*)
+
+val _ = Define `
+ ((s568_:string ->(string)option) s569_0=
+ (let s570_0 = s569_0 in
+ if ((string_startswith s570_0 "sltu")) then
+ (case ((string_drop s570_0 ((string_length "sltu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s564_ : string -> maybe string*)
+
+val _ = Define `
+ ((s564_:string ->(string)option) s565_0=
+ (let s566_0 = s565_0 in
+ if ((string_startswith s566_0 "slt")) then
+ (case ((string_drop s566_0 ((string_length "slt")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s560_ : string -> maybe string*)
+
+val _ = Define `
+ ((s560_:string ->(string)option) s561_0=
+ (let s562_0 = s561_0 in
+ if ((string_startswith s562_0 "add")) then
+ (case ((string_drop s562_0 ((string_length "add")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((rtype_mnemonic_matches_prefix:string ->(rop#int)option) arg_=
+ (let s563_0 = arg_ in
+ if ((case ((s560_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s560_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s564_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s564_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLT, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s568_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s568_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s572_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s572_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_AND, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s576_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s576_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_OR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s580_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s580_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_XOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s584_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s584_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLL, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s588_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s588_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRL, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s592_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s592_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SUB, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s596_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s596_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRA, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val extend_value : forall 'int8_times_n. Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty32)*)
+
+val _ = Define `
+ ((extend_value:bool ->('int8_times_n words$word)MemoryOpResult ->((32)words$word)MemoryOpResult) is_unsigned value=
+ ((case value of
+ MemValue (v) =>
+ MemValue (if is_unsigned then (EXTZ (( 32 : int):ii) v : 32 words$word)
+ else (EXTS (( 32 : int):ii) v : 32 words$word))
+ | MemException (e) => MemException e
+ )))`;
+
+
+(*val process_load : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty32 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired*)
+
+val _ = Define `
+ ((process_load:(5)words$word ->(32)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+ ((case ((extend_value is_unsigned value : ( 32 words$word) MemoryOpResult)) of
+ MemValue (result) => sail2_state_monad$seqS (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))`;
+
+
+(*val check_misaligned : mword ty32 -> word_width -> bool*)
+
+val _ = Define `
+ ((check_misaligned:(32)words$word -> word_width -> bool) (vaddr : xlenbits) (width : word_width)=
+ (if ((plat_enable_misaligned_access () )) then F
+ else
+ (case width of
+ BYTE => F
+ | HALF => (((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T)
+ | WORD =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T))) \/ (((((bit_to_bool ((access_vec_dec vaddr (( 1 : int):ii))))) = T))))
+ | DOUBLE =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T))) \/ ((((((((bit_to_bool ((access_vec_dec vaddr (( 1 : int):ii))))) = T))) \/ (((((bit_to_bool ((access_vec_dec vaddr (( 2 : int):ii))))) = T)))))))
+ )))`;
+
+
+(*val maybe_aq_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_aq_forwards:bool -> string) arg_= ((case arg_ of T => ".aq" | F => "" )))`;
+
+
+(*val maybe_aq_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".aq"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_aq_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_aq_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_aq_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".aq"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s604_ : string -> maybe string*)
+
+val _ = Define `
+ ((s604_:string ->(string)option) s605_0=
+ (let s606_0 = s605_0 in
+ if ((string_startswith s606_0 "")) then
+ (case ((string_drop s606_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s600_ : string -> maybe string*)
+
+val _ = Define `
+ ((s600_:string ->(string)option) s601_0=
+ (let s602_0 = s601_0 in
+ if ((string_startswith s602_0 ".aq")) then
+ (case ((string_drop s602_0 ((string_length ".aq")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_aq_matches_prefix:string ->(bool#int)option) arg_=
+ (let s603_0 = arg_ in
+ if ((case ((s600_ s603_0)) of SOME (s_) => T | _ => F )) then
+ (case s600_ s603_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s604_ s603_0)) of SOME (s_) => T | _ => F )) then
+ (case s604_ s603_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_rl_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_rl_forwards:bool -> string) arg_= ((case arg_ of T => ".rl" | F => "" )))`;
+
+
+(*val maybe_rl_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".rl"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_rl_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_rl_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_rl_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".rl"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s612_ : string -> maybe string*)
+
+val _ = Define `
+ ((s612_:string ->(string)option) s613_0=
+ (let s614_0 = s613_0 in
+ if ((string_startswith s614_0 "")) then
+ (case ((string_drop s614_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s608_ : string -> maybe string*)
+
+val _ = Define `
+ ((s608_:string ->(string)option) s609_0=
+ (let s610_0 = s609_0 in
+ if ((string_startswith s610_0 ".rl")) then
+ (case ((string_drop s610_0 ((string_length ".rl")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_rl_matches_prefix:string ->(bool#int)option) arg_=
+ (let s611_0 = arg_ in
+ if ((case ((s608_ s611_0)) of SOME (s_) => T | _ => F )) then
+ (case s608_ s611_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s612_ s611_0)) of SOME (s_) => T | _ => F )) then
+ (case s612_ s611_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_u_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_u_forwards:bool -> string) arg_= ((case arg_ of T => "u" | F => "" )))`;
+
+
+(*val maybe_u_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_u_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_u_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_u_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_u_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_u_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s620_ : string -> maybe string*)
+
+val _ = Define `
+ ((s620_:string ->(string)option) s621_0=
+ (let s622_0 = s621_0 in
+ if ((string_startswith s622_0 "")) then
+ (case ((string_drop s622_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s616_ : string -> maybe string*)
+
+val _ = Define `
+ ((s616_:string ->(string)option) s617_0=
+ (let s618_0 = s617_0 in
+ if ((string_startswith s618_0 "u")) then
+ (case ((string_drop s618_0 ((string_length "u")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_u_matches_prefix:string ->(bool#int)option) arg_=
+ (let s619_0 = arg_ in
+ if ((case ((s616_ s619_0)) of SOME (s_) => T | _ => F )) then
+ (case s616_ s619_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s620_ s619_0)) of SOME (s_) => T | _ => F )) then
+ (case s620_ s619_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val shiftw_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards:sop -> string) arg_=
+ ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftw_mnemonic_backwards : string -> M sop*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((p0_ = "srli"))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((p0_ = "srai"))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftw_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftw_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then T
+ else if (((p0_ = "srli"))) then T
+ else if (((p0_ = "srai"))) then T
+ else F))`;
+
+
+(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+(*val _s632_ : string -> maybe string*)
+
+val _ = Define `
+ ((s632_:string ->(string)option) s633_0=
+ (let s634_0 = s633_0 in
+ if ((string_startswith s634_0 "srai")) then
+ (case ((string_drop s634_0 ((string_length "srai")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s628_ : string -> maybe string*)
+
+val _ = Define `
+ ((s628_:string ->(string)option) s629_0=
+ (let s630_0 = s629_0 in
+ if ((string_startswith s630_0 "srli")) then
+ (case ((string_drop s630_0 ((string_length "srli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s624_ : string -> maybe string*)
+
+val _ = Define `
+ ((s624_:string ->(string)option) s625_0=
+ (let s626_0 = s625_0 in
+ if ((string_startswith s626_0 "slli")) then
+ (case ((string_drop s626_0 ((string_length "slli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftw_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+ (let s627_0 = arg_ in
+ if ((case ((s624_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s624_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s628_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s628_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s632_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s632_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val rtypew_mnemonic_forwards : ropw -> string*)
+
+val _ = Define `
+ ((rtypew_mnemonic_forwards:ropw -> string) arg_=
+ ((case arg_ of
+ RISCV_ADDW => "addw"
+ | RISCV_SUBW => "subw"
+ | RISCV_SLLW => "sllw"
+ | RISCV_SRLW => "srlw"
+ | RISCV_SRAW => "sraw"
+ )))`;
+
+
+(*val rtypew_mnemonic_backwards : string -> M ropw*)
+
+val _ = Define `
+ ((rtypew_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((ropw),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addw"))) then sail2_state_monad$returnS RISCV_ADDW
+ else if (((p0_ = "subw"))) then sail2_state_monad$returnS RISCV_SUBW
+ else if (((p0_ = "sllw"))) then sail2_state_monad$returnS RISCV_SLLW
+ else if (((p0_ = "srlw"))) then sail2_state_monad$returnS RISCV_SRLW
+ else if (((p0_ = "sraw"))) then sail2_state_monad$returnS RISCV_SRAW
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val rtypew_mnemonic_forwards_matches : ropw -> bool*)
+
+val _ = Define `
+ ((rtypew_mnemonic_forwards_matches:ropw -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDW => T
+ | RISCV_SUBW => T
+ | RISCV_SLLW => T
+ | RISCV_SRLW => T
+ | RISCV_SRAW => T
+ )))`;
+
+
+(*val rtypew_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((rtypew_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addw"))) then T
+ else if (((p0_ = "subw"))) then T
+ else if (((p0_ = "sllw"))) then T
+ else if (((p0_ = "srlw"))) then T
+ else if (((p0_ = "sraw"))) then T
+ else F))`;
+
+
+(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*)
+
+(*val _s652_ : string -> maybe string*)
+
+val _ = Define `
+ ((s652_:string ->(string)option) s653_0=
+ (let s654_0 = s653_0 in
+ if ((string_startswith s654_0 "sraw")) then
+ (case ((string_drop s654_0 ((string_length "sraw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s648_ : string -> maybe string*)
+
+val _ = Define `
+ ((s648_:string ->(string)option) s649_0=
+ (let s650_0 = s649_0 in
+ if ((string_startswith s650_0 "srlw")) then
+ (case ((string_drop s650_0 ((string_length "srlw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s644_ : string -> maybe string*)
+
+val _ = Define `
+ ((s644_:string ->(string)option) s645_0=
+ (let s646_0 = s645_0 in
+ if ((string_startswith s646_0 "sllw")) then
+ (case ((string_drop s646_0 ((string_length "sllw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s640_ : string -> maybe string*)
+
+val _ = Define `
+ ((s640_:string ->(string)option) s641_0=
+ (let s642_0 = s641_0 in
+ if ((string_startswith s642_0 "subw")) then
+ (case ((string_drop s642_0 ((string_length "subw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s636_ : string -> maybe string*)
+
+val _ = Define `
+ ((s636_:string ->(string)option) s637_0=
+ (let s638_0 = s637_0 in
+ if ((string_startswith s638_0 "addw")) then
+ (case ((string_drop s638_0 ((string_length "addw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((rtypew_mnemonic_matches_prefix:string ->(ropw#int)option) arg_=
+ (let s639_0 = arg_ in
+ if ((case ((s636_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s636_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADDW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s640_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s640_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SUBW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s644_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s644_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s648_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s648_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s652_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s652_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val shiftiwop_mnemonic_forwards : sopw -> string*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_forwards:sopw -> string) arg_=
+ ((case arg_ of RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" )))`;
+
+
+(*val shiftiwop_mnemonic_backwards : string -> M sopw*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sopw),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slliw"))) then sail2_state_monad$returnS RISCV_SLLIW
+ else if (((p0_ = "srliw"))) then sail2_state_monad$returnS RISCV_SRLIW
+ else if (((p0_ = "sraiw"))) then sail2_state_monad$returnS RISCV_SRAIW
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftiwop_mnemonic_forwards_matches : sopw -> bool*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_forwards_matches:sopw -> bool) arg_=
+ ((case arg_ of RISCV_SLLIW => T | RISCV_SRLIW => T | RISCV_SRAIW => T )))`;
+
+
+(*val shiftiwop_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slliw"))) then T
+ else if (((p0_ = "srliw"))) then T
+ else if (((p0_ = "sraiw"))) then T
+ else F))`;
+
+
+(*val shiftiwop_mnemonic_matches_prefix : string -> maybe ((sopw * ii))*)
+
+(*val _s664_ : string -> maybe string*)
+
+val _ = Define `
+ ((s664_:string ->(string)option) s665_0=
+ (let s666_0 = s665_0 in
+ if ((string_startswith s666_0 "sraiw")) then
+ (case ((string_drop s666_0 ((string_length "sraiw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s660_ : string -> maybe string*)
+
+val _ = Define `
+ ((s660_:string ->(string)option) s661_0=
+ (let s662_0 = s661_0 in
+ if ((string_startswith s662_0 "srliw")) then
+ (case ((string_drop s662_0 ((string_length "srliw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s656_ : string -> maybe string*)
+
+val _ = Define `
+ ((s656_:string ->(string)option) s657_0=
+ (let s658_0 = s657_0 in
+ if ((string_startswith s658_0 "slliw")) then
+ (case ((string_drop s658_0 ((string_length "slliw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftiwop_mnemonic_matches_prefix:string ->(sopw#int)option) arg_=
+ (let s659_0 = arg_ in
+ if ((case ((s656_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s656_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s660_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s660_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s664_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s664_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_r_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_r_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "r"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_r_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_r_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "r"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_r_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_r_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_r_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "r"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s672_ : string -> maybe string*)
+
+val _ = Define `
+ ((s672_:string ->(string)option) s673_0=
+ (let s674_0 = s673_0 in
+ if ((string_startswith s674_0 "")) then
+ (case ((string_drop s674_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s668_ : string -> maybe string*)
+
+val _ = Define `
+ ((s668_:string ->(string)option) s669_0=
+ (let s670_0 = s669_0 in
+ if ((string_startswith s670_0 "r")) then
+ (case ((string_drop s670_0 ((string_length "r")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_r_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s671_0 = arg_ in
+ if ((case ((s668_ s671_0)) of SOME (s_) => T | _ => F )) then
+ (case s668_ s671_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s672_ s671_0)) of SOME (s_) => T | _ => F )) then
+ (case s672_ s671_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_w_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_w_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "w"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_w_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_w_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "w"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_w_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_w_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_w_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "w"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s680_ : string -> maybe string*)
+
+val _ = Define `
+ ((s680_:string ->(string)option) s681_0=
+ (let s682_0 = s681_0 in
+ if ((string_startswith s682_0 "")) then
+ (case ((string_drop s682_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s676_ : string -> maybe string*)
+
+val _ = Define `
+ ((s676_:string ->(string)option) s677_0=
+ (let s678_0 = s677_0 in
+ if ((string_startswith s678_0 "w")) then
+ (case ((string_drop s678_0 ((string_length "w")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_w_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s679_0 = arg_ in
+ if ((case ((s676_ s679_0)) of SOME (s_) => T | _ => F )) then
+ (case s676_ s679_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s680_ s679_0)) of SOME (s_) => T | _ => F )) then
+ (case s680_ s679_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_i_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_i_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "i"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_i_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_i_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_i_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_i_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_i_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s688_ : string -> maybe string*)
+
+val _ = Define `
+ ((s688_:string ->(string)option) s689_0=
+ (let s690_0 = s689_0 in
+ if ((string_startswith s690_0 "")) then
+ (case ((string_drop s690_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s684_ : string -> maybe string*)
+
+val _ = Define `
+ ((s684_:string ->(string)option) s685_0=
+ (let s686_0 = s685_0 in
+ if ((string_startswith s686_0 "i")) then
+ (case ((string_drop s686_0 ((string_length "i")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_i_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s687_0 = arg_ in
+ if ((case ((s684_ s687_0)) of SOME (s_) => T | _ => F )) then
+ (case s684_ s687_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s688_ s687_0)) of SOME (s_) => T | _ => F )) then
+ (case s688_ s687_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_o_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_o_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "o"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_o_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_o_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "o"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_o_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_o_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_o_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "o"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s696_ : string -> maybe string*)
+
+val _ = Define `
+ ((s696_:string ->(string)option) s697_0=
+ (let s698_0 = s697_0 in
+ if ((string_startswith s698_0 "")) then
+ (case ((string_drop s698_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s692_ : string -> maybe string*)
+
+val _ = Define `
+ ((s692_:string ->(string)option) s693_0=
+ (let s694_0 = s693_0 in
+ if ((string_startswith s694_0 "o")) then
+ (case ((string_drop s694_0 ((string_length "o")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_o_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s695_0 = arg_ in
+ if ((case ((s692_ s695_0)) of SOME (s_) => T | _ => F )) then
+ (case s692_ s695_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s696_ s695_0)) of SOME (s_) => T | _ => F )) then
+ (case s696_ s695_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val fence_bits_forwards : mword ty4 -> M string*)
+
+val _ = Define `
+ ((fence_bits_forwards:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ v__0 =>
+ let (i : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (w : 1 bits) = ((subrange_vec_dec v__0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ let (r : 1 bits) = ((subrange_vec_dec v__0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (o1 : 1 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bit_maybe_i_forwards i) (\ (w__0 : string) . sail2_state_monad$bindS
+ (bit_maybe_o_forwards o1) (\ (w__1 : string) . sail2_state_monad$bindS
+ (bit_maybe_r_forwards r) (\ (w__2 : string) . sail2_state_monad$bindS
+ (bit_maybe_w_forwards w) (\ (w__3 : string) .
+ sail2_state_monad$returnS ((string_append w__0
+ ((string_append w__1 ((string_append w__2 ((string_append w__3 ""))))))))))))
+ )))`;
+
+
+(*val fence_bits_backwards : string -> M (mword ty4)*)
+
+(*val _s700_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))*)
+
+val _ = Define `
+ ((s700_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word)option) s701_0=
+ ((case s701_0 of
+ s702_0 =>
+ (case ((bit_maybe_i_matches_prefix s702_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s703_0)) =>
+ (case ((string_drop s702_0 s703_0)) of
+ s704_0 =>
+ (case ((bit_maybe_o_matches_prefix s704_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s705_0)) =>
+ (case ((string_drop s704_0 s705_0)) of
+ s706_0 =>
+ (case ((bit_maybe_r_matches_prefix s706_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s707_0)) =>
+ (case ((string_drop s706_0 s707_0)) of
+ s708_0 =>
+ (case ((bit_maybe_w_matches_prefix s708_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s709_0)) =>
+ let p0_ = (string_drop s708_0 s709_0) in
+ if (((p0_ = ""))) then SOME (i, o1, r, w) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s710_0 = arg_ in
+ if ((case ((s700_ s710_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word))option)) of
+ SOME ((i, o1, r, w)) => T
+ | _ => F
+ )) then (case
+ (s700_ s710_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word)) option) of
+ (SOME ((i, o1, r, w))) =>
+ sail2_state_monad$returnS
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w : 2 words$word)) : 3 words$word))
+ : 4 words$word))
+ )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val fence_bits_forwards_matches : mword ty4 -> bool*)
+
+val _ = Define `
+ ((fence_bits_forwards_matches:(4)words$word -> bool) arg_=
+ ((case arg_ of v__1 => T )))`;
+
+
+(*val fence_bits_backwards_matches : string -> bool*)
+
+(*val _s711_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))*)
+
+val _ = Define `
+ ((s711_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word)option) s712_0=
+ ((case s712_0 of
+ s713_0 =>
+ (case ((bit_maybe_i_matches_prefix s713_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s714_0)) =>
+ (case ((string_drop s713_0 s714_0)) of
+ s715_0 =>
+ (case ((bit_maybe_o_matches_prefix s715_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s716_0)) =>
+ (case ((string_drop s715_0 s716_0)) of
+ s717_0 =>
+ (case ((bit_maybe_r_matches_prefix s717_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s718_0)) =>
+ (case ((string_drop s717_0 s718_0)) of
+ s719_0 =>
+ (case ((bit_maybe_w_matches_prefix s719_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s720_0)) =>
+ let p0_ = (string_drop s719_0 s720_0) in
+ if (((p0_ = ""))) then SOME (i, o1, r, w) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_backwards_matches:string -> bool) arg_=
+ (let s721_0 = arg_ in
+ if ((case ((s711_ s721_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word))option)) of
+ SOME ((i, o1, r, w)) => T
+ | _ => F
+ )) then (case
+ (s711_ s721_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word)) option) of
+ (SOME ((i, o1, r, w))) =>
+ T
+ )
+ else F))`;
+
+
+(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*)
+
+(*val _s722_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1 * string))*)
+
+val _ = Define `
+ ((s722_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word#string)option) s723_0=
+ ((case s723_0 of
+ s724_0 =>
+ (case ((bit_maybe_i_matches_prefix s724_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s725_0)) =>
+ (case ((string_drop s724_0 s725_0)) of
+ s726_0 =>
+ (case ((bit_maybe_o_matches_prefix s726_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s727_0)) =>
+ (case ((string_drop s726_0 s727_0)) of
+ s728_0 =>
+ (case ((bit_maybe_r_matches_prefix s728_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s729_0)) =>
+ (case ((string_drop s728_0 s729_0)) of
+ s730_0 =>
+ (case ((bit_maybe_w_matches_prefix s730_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s731_0)) =>
+ (case ((string_drop s730_0 s731_0)) of s_ => SOME (i, o1, r, w, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_matches_prefix:string ->((4)words$word#int)option) arg_=
+ (let s732_0 = arg_ in
+ if ((case ((s722_ s732_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word # string))option)) of
+ SOME ((i, o1, r, w, s_)) => T
+ | _ => F
+ )) then (case
+ (s722_ s732_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word # string)) option) of
+ (SOME ((i, o1, r, w, s_))) =>
+ SOME
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w : 2 words$word)) : 3 words$word)) : 4 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val aqrl_str : bool -> bool -> string*)
+
+val _ = Define `
+ ((aqrl_str:bool -> bool -> string) (aq : bool) (rl : bool)=
+ ((case (aq, rl) of
+ (F, F) => ""
+ | (F, T) => ".rl"
+ | (T, F) => ".aq"
+ | (T, T) => ".aqrl"
+ )))`;
+
+
+(*val lrsc_width_str : word_width -> string*)
+
+val _ = Define `
+ ((lrsc_width_str:word_width -> string) width=
+ ((case width of BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" )))`;
+
+
+(*val process_loadres : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty32 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired*)
+
+val _ = Define `
+ ((process_loadres:(5)words$word ->(32)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+ ((case ((extend_value is_unsigned value : ( 32 words$word) MemoryOpResult)) of
+ MemValue (result) =>
+ let (_ : unit) = (load_reservation addr) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))`;
+
+
+(*val encdec_amoop_forwards : amoop -> mword ty5*)
+
+val _ = Define `
+ ((encdec_amoop_forwards:amoop ->(5)words$word) arg_=
+ ((case arg_ of
+ AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)
+ | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)
+ | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)
+ | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)
+ | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)
+ | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)
+ | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)
+ | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)
+ )))`;
+
+
+(*val encdec_amoop_backwards : mword ty5 -> M amoop*)
+
+val _ = Define `
+ ((encdec_amoop_backwards:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((amoop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS AMOSWAP
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOADD
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOXOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOAND
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMIN
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMAX
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMINU
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMAXU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_amoop_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_forwards_matches:amoop -> bool) arg_=
+ ((case arg_ of
+ AMOSWAP => T
+ | AMOADD => T
+ | AMOXOR => T
+ | AMOAND => T
+ | AMOOR => T
+ | AMOMIN => T
+ | AMOMAX => T
+ | AMOMINU => T
+ | AMOMAXU => T
+ )))`;
+
+
+(*val encdec_amoop_backwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_backwards_matches:(5)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))
+ then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else F))`;
+
+
+(*val amo_mnemonic_forwards : amoop -> string*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards:amoop -> string) arg_=
+ ((case arg_ of
+ AMOSWAP => "amoswap"
+ | AMOADD => "amoadd"
+ | AMOXOR => "amoxor"
+ | AMOAND => "amoand"
+ | AMOOR => "amoor"
+ | AMOMIN => "amomin"
+ | AMOMAX => "amomax"
+ | AMOMINU => "amominu"
+ | AMOMAXU => "amomaxu"
+ )))`;
+
+
+(*val amo_mnemonic_backwards : string -> M amoop*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((amoop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "amoswap"))) then sail2_state_monad$returnS AMOSWAP
+ else if (((p0_ = "amoadd"))) then sail2_state_monad$returnS AMOADD
+ else if (((p0_ = "amoxor"))) then sail2_state_monad$returnS AMOXOR
+ else if (((p0_ = "amoand"))) then sail2_state_monad$returnS AMOAND
+ else if (((p0_ = "amoor"))) then sail2_state_monad$returnS AMOOR
+ else if (((p0_ = "amomin"))) then sail2_state_monad$returnS AMOMIN
+ else if (((p0_ = "amomax"))) then sail2_state_monad$returnS AMOMAX
+ else if (((p0_ = "amominu"))) then sail2_state_monad$returnS AMOMINU
+ else if (((p0_ = "amomaxu"))) then sail2_state_monad$returnS AMOMAXU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val amo_mnemonic_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards_matches:amoop -> bool) arg_=
+ ((case arg_ of
+ AMOSWAP => T
+ | AMOADD => T
+ | AMOXOR => T
+ | AMOAND => T
+ | AMOOR => T
+ | AMOMIN => T
+ | AMOMAX => T
+ | AMOMINU => T
+ | AMOMAXU => T
+ )))`;
+
+
+(*val amo_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "amoswap"))) then T
+ else if (((p0_ = "amoadd"))) then T
+ else if (((p0_ = "amoxor"))) then T
+ else if (((p0_ = "amoand"))) then T
+ else if (((p0_ = "amoor"))) then T
+ else if (((p0_ = "amomin"))) then T
+ else if (((p0_ = "amomax"))) then T
+ else if (((p0_ = "amominu"))) then T
+ else if (((p0_ = "amomaxu"))) then T
+ else F))`;
+
+
+(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*)
+
+(*val _s765_ : string -> maybe string*)
+
+val _ = Define `
+ ((s765_:string ->(string)option) s766_0=
+ (let s767_0 = s766_0 in
+ if ((string_startswith s767_0 "amomaxu")) then
+ (case ((string_drop s767_0 ((string_length "amomaxu")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s761_ : string -> maybe string*)
+
+val _ = Define `
+ ((s761_:string ->(string)option) s762_0=
+ (let s763_0 = s762_0 in
+ if ((string_startswith s763_0 "amominu")) then
+ (case ((string_drop s763_0 ((string_length "amominu")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s757_ : string -> maybe string*)
+
+val _ = Define `
+ ((s757_:string ->(string)option) s758_0=
+ (let s759_0 = s758_0 in
+ if ((string_startswith s759_0 "amomax")) then
+ (case ((string_drop s759_0 ((string_length "amomax")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s753_ : string -> maybe string*)
+
+val _ = Define `
+ ((s753_:string ->(string)option) s754_0=
+ (let s755_0 = s754_0 in
+ if ((string_startswith s755_0 "amomin")) then
+ (case ((string_drop s755_0 ((string_length "amomin")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s749_ : string -> maybe string*)
+
+val _ = Define `
+ ((s749_:string ->(string)option) s750_0=
+ (let s751_0 = s750_0 in
+ if ((string_startswith s751_0 "amoor")) then
+ (case ((string_drop s751_0 ((string_length "amoor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s745_ : string -> maybe string*)
+
+val _ = Define `
+ ((s745_:string ->(string)option) s746_0=
+ (let s747_0 = s746_0 in
+ if ((string_startswith s747_0 "amoand")) then
+ (case ((string_drop s747_0 ((string_length "amoand")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s741_ : string -> maybe string*)
+
+val _ = Define `
+ ((s741_:string ->(string)option) s742_0=
+ (let s743_0 = s742_0 in
+ if ((string_startswith s743_0 "amoxor")) then
+ (case ((string_drop s743_0 ((string_length "amoxor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s737_ : string -> maybe string*)
+
+val _ = Define `
+ ((s737_:string ->(string)option) s738_0=
+ (let s739_0 = s738_0 in
+ if ((string_startswith s739_0 "amoadd")) then
+ (case ((string_drop s739_0 ((string_length "amoadd")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s733_ : string -> maybe string*)
+
+val _ = Define `
+ ((s733_:string ->(string)option) s734_0=
+ (let s735_0 = s734_0 in
+ if ((string_startswith s735_0 "amoswap")) then
+ (case ((string_drop s735_0 ((string_length "amoswap")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((amo_mnemonic_matches_prefix:string ->(amoop#int)option) arg_=
+ (let s736_0 = arg_ in
+ if ((case ((s733_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s733_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOSWAP, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s737_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s737_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOADD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s741_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s741_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOXOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s745_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s745_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOAND, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s749_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s749_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s753_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s753_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMIN, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s757_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s757_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMAX, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s761_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s761_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMINU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s765_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s765_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMAXU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_mul_op_forwards : (bool * bool * bool) -> mword ty3*)
+
+val _ = Define `
+ ((encdec_mul_op_forwards:bool#bool#bool ->(3)words$word) arg_=
+ ((case arg_ of
+ (F, T, T) => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | (T, T, T) => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | (T, T, F) => (vec_of_bits [B0;B1;B0] : 3 words$word)
+ | (T, F, F) => (vec_of_bits [B0;B1;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_mul_op_backwards : mword ty3 -> M (bool * bool * bool)*)
+
+val _ = Define `
+ ((encdec_mul_op_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS (F, T, T)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS (T, T, T)
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS (T, T, F)
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS (T, F, F)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_mul_op_forwards_matches : (bool * bool * bool) -> bool*)
+
+val _ = Define `
+ ((encdec_mul_op_forwards_matches:bool#bool#bool -> bool) arg_=
+ ((case arg_ of
+ (F, T, T) => T
+ | (T, T, T) => T
+ | (T, T, F) => T
+ | (T, F, F) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_mul_op_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val mul_mnemonic_forwards : (bool * bool * bool) -> string*)
+
+val _ = Define `
+ ((mul_mnemonic_forwards:bool#bool#bool -> string) arg_=
+ ((case arg_ of
+ (F, T, T) => "mul"
+ | (T, T, T) => "mulh"
+ | (T, T, F) => "mulhsu"
+ | (T, F, F) => "mulhu"
+ )))`;
+
+
+(*val mul_mnemonic_backwards : string -> M (bool * bool * bool)*)
+
+val _ = Define `
+ ((mul_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "mul"))) then sail2_state_monad$returnS (F, T, T)
+ else if (((p0_ = "mulh"))) then sail2_state_monad$returnS (T, T, T)
+ else if (((p0_ = "mulhsu"))) then sail2_state_monad$returnS (T, T, F)
+ else if (((p0_ = "mulhu"))) then sail2_state_monad$returnS (T, F, F)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val mul_mnemonic_forwards_matches : (bool * bool * bool) -> bool*)
+
+val _ = Define `
+ ((mul_mnemonic_forwards_matches:bool#bool#bool -> bool) arg_=
+ ((case arg_ of
+ (F, T, T) => T
+ | (T, T, T) => T
+ | (T, T, F) => T
+ | (T, F, F) => T
+ | _ => F
+ )))`;
+
+
+(*val mul_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((mul_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "mul"))) then T
+ else if (((p0_ = "mulh"))) then T
+ else if (((p0_ = "mulhsu"))) then T
+ else if (((p0_ = "mulhu"))) then T
+ else F))`;
+
+
+(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*)
+
+(*val _s781_ : string -> maybe string*)
+
+val _ = Define `
+ ((s781_:string ->(string)option) s782_0=
+ (let s783_0 = s782_0 in
+ if ((string_startswith s783_0 "mulhu")) then
+ (case ((string_drop s783_0 ((string_length "mulhu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s777_ : string -> maybe string*)
+
+val _ = Define `
+ ((s777_:string ->(string)option) s778_0=
+ (let s779_0 = s778_0 in
+ if ((string_startswith s779_0 "mulhsu")) then
+ (case ((string_drop s779_0 ((string_length "mulhsu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s773_ : string -> maybe string*)
+
+val _ = Define `
+ ((s773_:string ->(string)option) s774_0=
+ (let s775_0 = s774_0 in
+ if ((string_startswith s775_0 "mulh")) then
+ (case ((string_drop s775_0 ((string_length "mulh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s769_ : string -> maybe string*)
+
+val _ = Define `
+ ((s769_:string ->(string)option) s770_0=
+ (let s771_0 = s770_0 in
+ if ((string_startswith s771_0 "mul")) then
+ (case ((string_drop s771_0 ((string_length "mul")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((mul_mnemonic_matches_prefix:string ->((bool#bool#bool)#int)option) arg_=
+ (let s772_0 = arg_ in
+ if ((case ((s769_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s769_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((F, T, T), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s773_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s773_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, T, T), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s777_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s777_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, T, F), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s781_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s781_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, F, F), ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_not_u_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_not_u_forwards:bool -> string) arg_= ((case arg_ of F => "u" | T => "" )))`;
+
+
+(*val maybe_not_u_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_not_u_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then sail2_state_monad$returnS F
+ else if (((p0_ = ""))) then sail2_state_monad$returnS T
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_not_u_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_not_u_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of F => T | T => T )))`;
+
+
+(*val maybe_not_u_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_not_u_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s789_ : string -> maybe string*)
+
+val _ = Define `
+ ((s789_:string ->(string)option) s790_0=
+ (let s791_0 = s790_0 in
+ if ((string_startswith s791_0 "")) then
+ (case ((string_drop s791_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s785_ : string -> maybe string*)
+
+val _ = Define `
+ ((s785_:string ->(string)option) s786_0=
+ (let s787_0 = s786_0 in
+ if ((string_startswith s787_0 "u")) then
+ (case ((string_drop s787_0 ((string_length "u")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_not_u_matches_prefix:string ->(bool#int)option) arg_=
+ (let s788_0 = arg_ in
+ if ((case ((s785_ s788_0)) of SOME (s_) => T | _ => F )) then
+ (case s785_ s788_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s789_ s788_0)) of SOME (s_) => T | _ => F )) then
+ (case s789_ s788_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_csrop_forwards : csrop -> mword ty2*)
+
+val _ = Define `
+ ((encdec_csrop_forwards:csrop ->(2)words$word) arg_=
+ ((case arg_ of
+ CSRRW => (vec_of_bits [B0;B1] : 2 words$word)
+ | CSRRS => (vec_of_bits [B1;B0] : 2 words$word)
+ | CSRRC => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val encdec_csrop_backwards : mword ty2 -> M csrop*)
+
+val _ = Define `
+ ((encdec_csrop_backwards:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((csrop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS CSRRW
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS CSRRS
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS CSRRC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_csrop_forwards_matches : csrop -> bool*)
+
+val _ = Define `
+ ((encdec_csrop_forwards_matches:csrop -> bool) arg_=
+ ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`;
+
+
+(*val encdec_csrop_backwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((encdec_csrop_backwards_matches:(2)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then T
+ else F))`;
+
+
+(*val readCSR : mword ty12 -> M (mword ty32)*)
+
+val _ = Define `
+ ((readCSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr= (sail2_state_monad$bindS
+ (case (csr, (( 32 : int):ii)) of
+ (b__0, g__3) =>
+ if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mvendorid_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ sail2_state_monad$returnS ((EXTZ (( 32 : int):ii) w__0 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS marchid_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mimpid_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mhartid_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ sail2_state_monad$returnS ((get_Mstatus_bits w__4 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__5 : Misa) . sail2_state_monad$returnS ((get_Misa_bits w__5 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) .
+ sail2_state_monad$returnS ((get_Medeleg_bits w__6 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__7 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__8 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ (get_mtvec () : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__10 : Counteren) .
+ sail2_state_monad$returnS ((EXTZ (( 32 : int):ii) ((get_Counteren_bits w__10 : 32 words$word)) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mscratch_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target Machine : ( 32 words$word) M) (\ (w__12 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__13 : 32 words$word) .
+ sail2_state_monad$returnS ((and_vec w__12 w__13 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcause_ref) (\ (w__14 : Mcause) .
+ sail2_state_monad$returnS ((get_Mcause_bits w__14 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mtval_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__16 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__16 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (pmpReadCfgReg (( 0 : int):ii) : ( 32 words$word) M)
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))))))
+ then
+ (pmpReadCfgReg (( 1 : int):ii) : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ (pmpReadCfgReg (( 2 : int):ii) : ( 32 words$word) M)
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))))))
+ then
+ (pmpReadCfgReg (( 3 : int):ii) : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__37 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__37 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__38 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__38 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)))
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__39 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__39 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__40 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__40 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tselect_ref : ( 32 words$word) M) (\ (w__41 : 32 words$word) .
+ sail2_state_monad$returnS ((not_vec w__41 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__42 : Mstatus) .
+ sail2_state_monad$returnS ((get_Sstatus_bits ((lower_mstatus w__42)) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sedeleg_ref) (\ (w__43 : Sedeleg) .
+ sail2_state_monad$returnS ((get_Sedeleg_bits w__43 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__44 : Sinterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits w__44 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__45 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__46 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mie w__45 w__46)) : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ (get_stvec () : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scounteren_ref) (\ (w__48 : Counteren) .
+ sail2_state_monad$returnS ((EXTZ (( 32 : int):ii) ((get_Counteren_bits w__48 : 32 words$word)) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS sscratch_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target Supervisor : ( 32 words$word) M) (\ (w__50 : 32 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 32 words$word) M) (\ (w__51 : 32 words$word) .
+ sail2_state_monad$returnS ((and_vec w__50 w__51 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scause_ref) (\ (w__52 : Mcause) .
+ sail2_state_monad$returnS ((get_Mcause_bits w__52 : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS stval_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__54 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__55 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mip w__54 w__55)) : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__57 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__57 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__58 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__58 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__59 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__59 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)))
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__60 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__60 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__61 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__61 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))
+ else if ((((((g__3 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__62 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__62 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))
+ else sail2_state_monad$bindS
+ (ext_read_CSR csr : ( ( 32 words$word)option) M) (\ (w__63 : ( 32 words$word)option) .
+ sail2_state_monad$returnS ((case w__63 of
+ SOME (res) => res
+ | NONE =>
+ let (_ : unit) = (print_bits0 "unhandled read to CSR " csr) in
+ (EXTZ (( 32 : int):ii) (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 32 words$word)
+ )))
+ ) (\ (res : xlenbits) .
+ let (_ : unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr)) ((STRCAT " -> " ((string_of_bits res))))))))
+ else () ) in
+ sail2_state_monad$returnS res)))`;
+
+
+(*val writeCSR : mword ty12 -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((writeCSR:(12)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= (sail2_state_monad$bindS
+ (case (csr, (( 32 : int):ii)) of
+ (b__0, g__2) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (legalize_mstatus w__0 value) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__1)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__2 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__3 : Misa) . sail2_state_monad$bindS
+ (legalize_misa w__3 value) (\ (w__4 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS misa_ref w__4)
+ (sail2_state_monad$read_regS misa_ref)) (\ (w__5 : Misa) .
+ sail2_state_monad$returnS (SOME ((get_Misa_bits w__5 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS medeleg_ref ((legalize_medeleg w__6 value)))
+ (sail2_state_monad$read_regS medeleg_ref)) (\ (w__7 : Medeleg) .
+ sail2_state_monad$returnS (SOME ((get_Medeleg_bits w__7 : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__8 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mideleg_ref ((legalize_mideleg w__8 value)))
+ (sail2_state_monad$read_regS mideleg_ref)) (\ (w__9 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__9 : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__10 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_mie w__10 value) (\ (w__11 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__11)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__12 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__12 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_mtvec value : ( 32 words$word) M) (\ (w__13 : 32 words$word) . sail2_state_monad$returnS (SOME w__13))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__14 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mcounteren_ref ((legalize_mcounteren w__14 value)))
+ (sail2_state_monad$read_regS mcounteren_ref)) (\ (w__15 : Counteren) .
+ sail2_state_monad$returnS (SOME ((EXTZ (( 32 : int):ii) ((get_Counteren_bits w__15 : 32 words$word)) : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mscratch_ref value)
+ (sail2_state_monad$read_regS mscratch_ref : ( 32 words$word) M)) (\ (w__16 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__16))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target Machine value : ( 32 words$word) M) (\ (w__17 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__17))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits mcause_ref value)
+ (sail2_state_monad$read_regS mcause_ref)) (\ (w__18 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__18 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtval_ref value)
+ (sail2_state_monad$read_regS mtval_ref : ( 32 words$word) M)) (\ (w__19 : 32 words$word) . sail2_state_monad$returnS (SOME w__19))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__20 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_mip w__20 value) (\ (w__21 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__21)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__22 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__22 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 0 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if ((((((g__2 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))))))
+ then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 1 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 2 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if ((((((g__2 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))))))
+ then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 3 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__23 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 32 words$word) M) (\ (w__24 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr0_ref ((pmpWriteAddr w__23 w__24 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 32 words$word) M)) (\ (w__25 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__25))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__26 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 32 words$word) M) (\ (w__27 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr1_ref ((pmpWriteAddr w__26 w__27 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 32 words$word) M)) (\ (w__28 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__28))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__29 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 32 words$word) M) (\ (w__30 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr2_ref ((pmpWriteAddr w__29 w__30 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 32 words$word) M)) (\ (w__31 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__31))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__32 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 32 words$word) M) (\ (w__33 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr3_ref ((pmpWriteAddr w__32 w__33 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 32 words$word) M)) (\ (w__34 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__34))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__35 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 32 words$word) M) (\ (w__36 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr4_ref ((pmpWriteAddr w__35 w__36 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 32 words$word) M)) (\ (w__37 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__37))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__38 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 32 words$word) M) (\ (w__39 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr5_ref ((pmpWriteAddr w__38 w__39 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 32 words$word) M)) (\ (w__40 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__40))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__41 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 32 words$word) M) (\ (w__42 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr6_ref ((pmpWriteAddr w__41 w__42 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 32 words$word) M)) (\ (w__43 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__43))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__44 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 32 words$word) M) (\ (w__45 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr7_ref ((pmpWriteAddr w__44 w__45 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 32 words$word) M)) (\ (w__46 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__46))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__47 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 32 words$word) M) (\ (w__48 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr8_ref ((pmpWriteAddr w__47 w__48 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 32 words$word) M)) (\ (w__49 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__49))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__50 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 32 words$word) M) (\ (w__51 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr9_ref ((pmpWriteAddr w__50 w__51 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 32 words$word) M)) (\ (w__52 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__52))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__53 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 32 words$word) M) (\ (w__54 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr10_ref ((pmpWriteAddr w__53 w__54 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 32 words$word) M)) (\ (w__55 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__55))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__56 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 32 words$word) M) (\ (w__57 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr11_ref ((pmpWriteAddr w__56 w__57 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 32 words$word) M)) (\ (w__58 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__58))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__59 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 32 words$word) M) (\ (w__60 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr12_ref ((pmpWriteAddr w__59 w__60 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 32 words$word) M)) (\ (w__61 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__61))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__62 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 32 words$word) M) (\ (w__63 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr13_ref ((pmpWriteAddr w__62 w__63 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 32 words$word) M)) (\ (w__64 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__64))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__65 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 32 words$word) M) (\ (w__66 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr14_ref ((pmpWriteAddr w__65 w__66 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 32 words$word) M)) (\ (w__67 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__67))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__68 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 32 words$word) M) (\ (w__69 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr15_ref ((pmpWriteAddr w__68 w__69 value : 32 words$word)))
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 32 words$word) M)) (\ (w__70 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__70))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__71 : 64 words$word) . sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mcycle_ref
+ ((update_subrange_vec_dec w__71 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$returnS (SOME value)))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__72 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ minstret_ref
+ ((update_subrange_vec_dec w__72 (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$write_regS minstret_written_ref T)) (sail2_state_monad$returnS (SOME value)))
+ else if ((((((g__2 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__73 : 64 words$word) . sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mcycle_ref ((update_subrange_vec_dec w__73 (( 63 : int):ii) (( 32 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$returnS (SOME value)))
+ else if ((((((g__2 = (( 32 : int):ii)))) /\ (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__74 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS minstret_ref ((update_subrange_vec_dec w__74 (( 63 : int):ii) (( 32 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$write_regS minstret_written_ref T)) (sail2_state_monad$returnS (SOME value)))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS tselect_ref value)
+ (sail2_state_monad$read_regS tselect_ref : ( 32 words$word) M)) (\ (w__75 : 32 words$word) . sail2_state_monad$returnS (SOME w__75))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__76 : Mstatus) . sail2_state_monad$bindS
+ (legalize_sstatus w__76 value) (\ (w__77 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__77)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__78 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__78 : 32 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sedeleg_ref) (\ (w__79 : Sedeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__79 value)))
+ (sail2_state_monad$read_regS sedeleg_ref)) (\ (w__80 : Sedeleg) .
+ sail2_state_monad$returnS (SOME ((get_Sedeleg_bits w__80 : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Sinterrupts_bits sideleg_ref value)
+ (sail2_state_monad$read_regS sideleg_ref)) (\ (w__81 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Sinterrupts_bits w__81 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__82 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__83 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_sie w__82 w__83 value) (\ (w__84 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__84)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__85 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__85 : 32 words$word)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_stvec value : ( 32 words$word) M) (\ (w__86 : 32 words$word) . sail2_state_monad$returnS (SOME w__86))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scounteren_ref) (\ (w__87 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS scounteren_ref ((legalize_scounteren w__87 value)))
+ (sail2_state_monad$read_regS scounteren_ref)) (\ (w__88 : Counteren) .
+ sail2_state_monad$returnS (SOME ((EXTZ (( 32 : int):ii) ((get_Counteren_bits w__88 : 32 words$word)) : 32 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS sscratch_ref value)
+ (sail2_state_monad$read_regS sscratch_ref : ( 32 words$word) M)) (\ (w__89 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__89))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target Supervisor value : ( 32 words$word) M) (\ (w__90 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__90))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits scause_ref value)
+ (sail2_state_monad$read_regS scause_ref)) (\ (w__91 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__91 : 32 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS stval_ref value)
+ (sail2_state_monad$read_regS stval_ref : ( 32 words$word) M)) (\ (w__92 : 32 words$word) . sail2_state_monad$returnS (SOME w__92))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__93 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__94 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_sip w__93 w__94 value) (\ (w__95 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__95)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__96 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__96 : 32 words$word)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (cur_Architecture () ) (\ (w__97 : Architecture) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M) (\ (w__98 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS satp_ref ((legalize_satp w__97 w__98 value : 32 words$word)))
+ (sail2_state_monad$read_regS satp_ref : ( 32 words$word) M)) (\ (w__99 : 32 words$word) . sail2_state_monad$returnS (SOME w__99))))
+ else sail2_state_monad$returnS NONE
+ ) (\ (res : xlenbits option) .
+ (case res of
+ SOME (v) =>
+ sail2_state_monad$returnS (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr))
+ ((STRCAT " <- "
+ ((STRCAT ((string_of_bits v))
+ ((STRCAT " (input: "
+ ((STRCAT ((string_of_bits value)) ")"))))))))))))
+ else () )
+ | NONE => sail2_state_monad$bindS
+ (ext_write_CSR csr value) (\ (w__149 : bool) .
+ sail2_state_monad$returnS (if w__149 then ()
+ else print_bits0 "unhandled write to CSR " csr))
+ ))))`;
+
+
+(*val maybe_i_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_i_forwards:bool -> string) arg_= ((case arg_ of T => "i" | F => "" )))`;
+
+
+(*val maybe_i_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_i_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_i_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_i_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_i_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_i_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s797_ : string -> maybe string*)
+
+val _ = Define `
+ ((s797_:string ->(string)option) s798_0=
+ (let s799_0 = s798_0 in
+ if ((string_startswith s799_0 "")) then
+ (case ((string_drop s799_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s793_ : string -> maybe string*)
+
+val _ = Define `
+ ((s793_:string ->(string)option) s794_0=
+ (let s795_0 = s794_0 in
+ if ((string_startswith s795_0 "i")) then
+ (case ((string_drop s795_0 ((string_length "i")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_i_matches_prefix:string ->(bool#int)option) arg_=
+ (let s796_0 = arg_ in
+ if ((case ((s793_ s796_0)) of SOME (s_) => T | _ => F )) then
+ (case s793_ s796_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s797_ s796_0)) of SOME (s_) => T | _ => F )) then
+ (case s797_ s796_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val csr_mnemonic_forwards : csrop -> string*)
+
+val _ = Define `
+ ((csr_mnemonic_forwards:csrop -> string) arg_=
+ ((case arg_ of CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" )))`;
+
+
+(*val csr_mnemonic_backwards : string -> M csrop*)
+
+val _ = Define `
+ ((csr_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((csrop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "csrrw"))) then sail2_state_monad$returnS CSRRW
+ else if (((p0_ = "csrrs"))) then sail2_state_monad$returnS CSRRS
+ else if (((p0_ = "csrrc"))) then sail2_state_monad$returnS CSRRC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_mnemonic_forwards_matches : csrop -> bool*)
+
+val _ = Define `
+ ((csr_mnemonic_forwards_matches:csrop -> bool) arg_=
+ ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`;
+
+
+(*val csr_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((csr_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "csrrw"))) then T
+ else if (((p0_ = "csrrs"))) then T
+ else if (((p0_ = "csrrc"))) then T
+ else F))`;
+
+
+(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*)
+
+(*val _s809_ : string -> maybe string*)
+
+val _ = Define `
+ ((s809_:string ->(string)option) s810_0=
+ (let s811_0 = s810_0 in
+ if ((string_startswith s811_0 "csrrc")) then
+ (case ((string_drop s811_0 ((string_length "csrrc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s805_ : string -> maybe string*)
+
+val _ = Define `
+ ((s805_:string ->(string)option) s806_0=
+ (let s807_0 = s806_0 in
+ if ((string_startswith s807_0 "csrrs")) then
+ (case ((string_drop s807_0 ((string_length "csrrs")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s801_ : string -> maybe string*)
+
+val _ = Define `
+ ((s801_:string ->(string)option) s802_0=
+ (let s803_0 = s802_0 in
+ if ((string_startswith s803_0 "csrrw")) then
+ (case ((string_drop s803_0 ((string_length "csrrw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((csr_mnemonic_matches_prefix:string ->(csrop#int)option) arg_=
+ (let s804_0 = arg_ in
+ if ((case ((s801_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s801_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s805_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s805_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRS, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s809_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s809_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRC, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_forwards : ast -> M (mword ty32)*)
+
+val _ = Define `
+ ((encdec_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rd ((encdec_uop_forwards op : 7 words$word)) : 12 words$word))
+ : 32 words$word))
+ | RISCV_JAL ((v__2, rd)) =>
+ if (((((subrange_vec_dec v__2 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__2 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_8 : 1 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__2 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__2 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in
+ let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm_19
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9
+ ((concat_vec imm_8
+ ((concat_vec imm_7_0
+ ((concat_vec rd (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 20 words$word))
+ : 21 words$word))
+ : 25 words$word))
+ : 31 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | BTYPE ((v__4, rs2, rs1, op)) =>
+ if (((((subrange_vec_dec v__4 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__4 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__4 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__4 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in
+ let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__4 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in
+ let (imm5_0 : 1 bits) = ((subrange_vec_dec v__4 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm7_6
+ ((concat_vec imm7_5_0
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec ((encdec_bop_forwards op : 3 words$word))
+ ((concat_vec imm5_4_1
+ ((concat_vec imm5_0
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)
+ : 8 words$word))
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 31 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | ITYPE ((imm, rs1, rd, op)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((encdec_iop_forwards op : 3 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, F, F)) =>
+ if (((((((word_width_bytes size1)) < (( 4 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 4 : int):ii))))))))) then
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_unsigned : 1 words$word))
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | STORE ((v__6, rs2, rs1, size1, F, F)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__6 (( 11 : int):ii) (( 5 : int):ii) : 7 words$word)) in
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__6 (( 11 : int):ii) (( 5 : int):ii) : 7 words$word)) in
+ let (imm5 : 5 bits) = ((subrange_vec_dec v__6 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm7
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec imm5
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | FENCE ((pred, succ)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 24 words$word))
+ : 28 words$word))
+ : 32 words$word))
+ | FENCE_TSO ((pred, succ)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0;B0] : 4 words$word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 24 words$word))
+ : 28 words$word))
+ : 32 words$word))
+ | FENCEI (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | ECALL (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | MRET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | SRET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | EBREAK (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | WFI (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | SFENCE_VMA ((rs1, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | LOADRES ((aq, rl, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | AMO ((op, aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec ((encdec_amoop_forwards op : 5 words$word))
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec
+ ((encdec_mul_op_forwards (high, signed1, signed2) : 3 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | DIV0 ((rs2, rs1, rd, s)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | REM ((rs2, rs1, rd, s)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ sail2_state_monad$returnS ((concat_vec csr
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_imm : 1 words$word))
+ ((concat_vec ((encdec_csrop_forwards op : 2 words$word))
+ ((concat_vec rd (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | URET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | ILLEGAL (s) => sail2_state_monad$returnS s
+ | _ => sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val encdec_backwards : mword ty32 -> M ast*)
+
+val _ = Define `
+ ((encdec_backwards:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let v__7 = arg_ in
+ let (mappingpatterns_23_0 : 7 words$word) = ((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_uop_backwards_matches mappingpatterns_23_0)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_23_0)) then sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_23_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__1 : bool) .
+ if w__1 then
+ let (imm : 20 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 20 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in
+ let (mappingpatterns_23_0 : 7 words$word) = ((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_23_0) (\ op . sail2_state_monad$returnS (UTYPE (imm, rd, op)))
+ else if (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm_8 : 1 bits) = ((subrange_vec_dec v__7 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__7 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in
+ let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 21 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (RISCV_JAL ((concat_vec imm_19
+ ((concat_vec imm_7_0
+ ((concat_vec imm_8
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9 (vec_of_bits [B0] : 1 words$word)
+ : 5 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 20 words$word))
+ : 21 words$word),
+ rd))
+ else if ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ sail2_state_monad$returnS (RISCV_JALR (imm, rs1, rd))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_24_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_bop_backwards_matches mappingpatterns_24_0)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_24_0)) then sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_24_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__4 : bool) .
+ if w__4 then
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__7 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in
+ let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in
+ let (imm5_0 : 1 bits) = ((subrange_vec_dec v__7 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_24_0 : 3 words$word) = ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_24_0) (\ op .
+ sail2_state_monad$returnS (BTYPE ((concat_vec imm7_6
+ ((concat_vec imm5_0
+ ((concat_vec imm7_5_0
+ ((concat_vec imm5_4_1 (vec_of_bits [B0] : 1 words$word) : 5 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word),
+ rs2,
+ rs1,
+ op)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_25_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_iop_backwards_matches mappingpatterns_25_0)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_25_0)) then sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_25_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__7 : bool) .
+ if w__7 then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_25_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_25_0) (\ op . sail2_state_monad$returnS (ITYPE (imm, rs1, rd, op)))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SLLI))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SRLI))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SRAI))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_ADD))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLT))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLTU))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_AND))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_OR))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_XOR))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLL))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SRL))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SUB))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SRA))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_27_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_26_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_27_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_27_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_27_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_26_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_26_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_26_0) (\ is_unsigned .
+ sail2_state_monad$returnS (((((((word_width_bytes size1)) < (( 4 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 4 : int):ii))))))))))
+ else sail2_state_monad$returnS F)) (\ (w__9 : bool) .
+ sail2_state_monad$returnS w__9))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__12 : bool) .
+ if w__12 then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_27_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_26_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_27_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_26_0) (\ is_unsigned .
+ sail2_state_monad$returnS (LOAD (imm, rs1, rd, is_unsigned, size1, F, F))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_28_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_28_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_28_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_28_0) (\ size1 .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__15 :
+ bool) .
+ if w__15 then
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in
+ let (imm5 : 5 bits) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_28_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_28_0) (\ size1 .
+ sail2_state_monad$returnS (STORE ((concat_vec imm7 imm5 : 12 words$word), rs2, rs1, size1, F, F)))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ sail2_state_monad$returnS (ADDIW (imm, rs1, rd))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SLLI))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SRLI))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SRAI))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_ADDW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SUBW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SLLW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SRLW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SRAW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SLLIW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SRLIW))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SRAIW))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__7 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ let (succ : 4 words$word) = ((subrange_vec_dec v__7 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in
+ let (pred : 4 words$word) = ((subrange_vec_dec v__7 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (FENCE (pred, succ))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__7 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ let (succ : 4 words$word) = ((subrange_vec_dec v__7 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in
+ let (pred : 4 words$word) = ((subrange_vec_dec v__7 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (FENCE_TSO (pred, succ))
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (FENCEI () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (ECALL () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (MRET () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (SRET () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (EBREAK () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (WFI () )
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__7 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word)))))))
+ then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SFENCE_VMA (rs1, rs2))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_31_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_30_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_29_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_31_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_31_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_31_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_30_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_30_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_30_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_29_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_29_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_29_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__17 : bool) .
+ sail2_state_monad$returnS w__17))
+ else sail2_state_monad$returnS F)) (\ (w__19 : bool) .
+ sail2_state_monad$returnS w__19))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))))) (\ (w__22 :
+ bool) .
+ if w__22 then
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_31_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_30_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_29_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_31_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_30_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_29_0) (\ aq .
+ sail2_state_monad$returnS (LOADRES (aq, rl, rs1, size1, rd)))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_34_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_33_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_32_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_34_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_34_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_34_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_33_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_33_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_33_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_32_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_32_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_32_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__24 : bool) .
+ sail2_state_monad$returnS w__24))
+ else sail2_state_monad$returnS F)) (\ (w__26 : bool) .
+ sail2_state_monad$returnS w__26))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))))) (\ (w__29 :
+ bool) .
+ if w__29 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_34_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_33_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_32_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_34_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_33_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_32_0) (\ aq .
+ sail2_state_monad$returnS (STORECON (aq, rl, rs2, rs1, size1, rd)))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_38_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_37_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_36_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_38_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_38_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_38_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_37_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_37_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_37_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_36_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_36_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_36_0) (\ aq . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_amoop_backwards_matches mappingpatterns_35_0)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_35_0)) then sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_35_0) (\ op .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__31 : bool) .
+ sail2_state_monad$returnS w__31))
+ else sail2_state_monad$returnS F)) (\ (w__33 : bool) .
+ sail2_state_monad$returnS w__33))
+ else sail2_state_monad$returnS F)) (\ (w__35 : bool) .
+ sail2_state_monad$returnS w__35))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))) (\ (w__38 :
+ bool) .
+ if w__38 then
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_38_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_37_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_36_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_38_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_37_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_36_0) (\ aq . sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_35_0) (\ op .
+ sail2_state_monad$returnS (AMO (op, aq, rl, rs2, rs1, size1, rd))))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_39_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_mul_op_backwards_matches mappingpatterns_39_0)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_39_0)) then sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_39_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__41 :
+ bool) .
+ if w__41 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_39_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_39_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS (MUL (rs2, rs1, rd, high, signed1, signed2)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_40_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_40_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_40_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_40_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__44 :
+ bool) .
+ if w__44 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_40_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_40_0) (\ s .
+ sail2_state_monad$returnS (DIV0 (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_41_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_41_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_41_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_41_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__47 :
+ bool) .
+ if w__47 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_41_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_41_0) (\ s .
+ sail2_state_monad$returnS (REM (rs2, rs1, rd, s)))
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))))
+ then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (MULW (rs2, rs1, rd))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_42_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_42_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_42_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_42_0) (\ s .
+ sail2_state_monad$returnS ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__50 :
+ bool) .
+ if w__50 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_42_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_42_0) (\ s .
+ sail2_state_monad$returnS (DIVW (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_43_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_43_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_43_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_43_0) (\ s .
+ sail2_state_monad$returnS ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__53 :
+ bool) .
+ if w__53 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_43_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_43_0) (\ s .
+ sail2_state_monad$returnS (REMW (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_45_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_44_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_csrop_backwards_matches mappingpatterns_45_0)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_45_0)) then sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_45_0) (\ op . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_44_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_44_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_44_0) (\ is_imm .
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__55 : bool) .
+ sail2_state_monad$returnS w__55))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__58 :
+ bool) .
+ if w__58 then
+ let (csr : 12 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (csr : 12 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_45_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_44_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_45_0) (\ op . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_44_0) (\ is_imm .
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, is_imm, op))))
+ else
+ sail2_state_monad$returnS (if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+ B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ URET ()
+ else ILLEGAL v__7)))))))))))))))))`;
+
+
+(*val encdec_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((encdec_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => T
+ | RISCV_JAL ((v__220, rd)) =>
+ if (((((subrange_vec_dec v__220 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ T
+ else F
+ | RISCV_JALR ((imm, rs1, rd)) => T
+ | BTYPE ((v__222, rs2, rs1, op)) =>
+ if (((((subrange_vec_dec v__222 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ T
+ else F
+ | ITYPE ((imm, rs1, rd, op)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) => T
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, F, F)) =>
+ if (((((((word_width_bytes size1)) < (( 4 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 4 : int):ii))))))))) then
+ T
+ else F
+ | STORE ((v__224, rs2, rs1, size1, F, F)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then T else F
+ | ADDIW ((imm, rs1, rd)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | FENCE ((pred, succ)) => T
+ | FENCE_TSO ((pred, succ)) => T
+ | FENCEI (() ) => T
+ | ECALL (() ) => T
+ | MRET (() ) => T
+ | SRET (() ) => T
+ | EBREAK (() ) => T
+ | WFI (() ) => T
+ | SFENCE_VMA ((rs1, rs2)) => T
+ | LOADRES ((aq, rl, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then T else F
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then T else F
+ | AMO ((op, aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 4 : int):ii))) then T else F
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => T
+ | DIV0 ((rs2, rs1, rd, s)) => T
+ | REM ((rs2, rs1, rd, s)) => T
+ | MULW ((rs2, rs1, rd)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | DIVW ((rs2, rs1, rd, s)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | REMW ((rs2, rs1, rd, s)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | CSR ((csr, rs1, rd, is_imm, op)) => T
+ | URET (() ) => T
+ | ILLEGAL (s) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_backwards_matches : mword ty32 -> M bool*)
+
+val _ = Define `
+ ((encdec_backwards_matches:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let v__225 = arg_ in
+ let (mappingpatterns_0_0 : 7 words$word) = ((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_uop_backwards_matches mappingpatterns_0_0)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_0_0)) then sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_0_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__1 : bool) .
+ if w__1 then
+ let (mappingpatterns_0_0 : 7 words$word) = ((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_0_0) (\ op . sail2_state_monad$returnS T)
+ else if (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_1_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_bop_backwards_matches mappingpatterns_1_0)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_1_0)) then sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_1_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__4 : bool) .
+ if w__4 then
+ let (mappingpatterns_1_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_1_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_2_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_iop_backwards_matches mappingpatterns_2_0)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_2_0)) then sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_2_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__7 : bool) .
+ if w__7 then
+ let (mappingpatterns_2_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_2_0) (\ op . sail2_state_monad$returnS T)
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_4_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_3_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_4_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_4_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_4_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_3_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_3_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_3_0) (\ is_unsigned .
+ sail2_state_monad$returnS (((((((word_width_bytes size1)) < (( 4 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 4 : int):ii))))))))))
+ else sail2_state_monad$returnS F)) (\ (w__9 : bool) .
+ sail2_state_monad$returnS w__9))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__12 : bool) .
+ if w__12 then
+ let (mappingpatterns_4_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_3_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_4_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_3_0) (\ is_unsigned . sail2_state_monad$returnS T))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_5_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_5_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_5_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_5_0) (\ size1 .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__15 :
+ bool) .
+ if w__15 then
+ let (mappingpatterns_5_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_5_0) (\ size1 . sail2_state_monad$returnS T)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__225 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__225 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__225 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word)))))))
+ then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_8_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_7_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_6_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_8_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_8_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_8_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_7_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_7_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_7_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_6_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_6_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_6_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__17 : bool) .
+ sail2_state_monad$returnS w__17))
+ else sail2_state_monad$returnS F)) (\ (w__19 : bool) .
+ sail2_state_monad$returnS w__19))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))))) (\ (w__22 :
+ bool) .
+ if w__22 then
+ let (mappingpatterns_8_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_7_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_6_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_8_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_7_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_6_0) (\ aq . sail2_state_monad$returnS T)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_9_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_11_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_10_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_11_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_11_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_11_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_10_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_10_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_10_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_9_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_9_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_9_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__24 : bool) .
+ sail2_state_monad$returnS w__24))
+ else sail2_state_monad$returnS F)) (\ (w__26 : bool) .
+ sail2_state_monad$returnS w__26))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))))) (\ (w__29 :
+ bool) .
+ if w__29 then
+ let (mappingpatterns_9_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_11_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_10_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_11_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_10_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_9_0) (\ aq . sail2_state_monad$returnS T)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_15_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_14_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_13_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_15_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_15_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_15_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_14_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_14_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_14_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_13_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_13_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_13_0) (\ aq . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_amoop_backwards_matches mappingpatterns_12_0)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_12_0)) then sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_12_0) (\ op .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 4 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__31 : bool) .
+ sail2_state_monad$returnS w__31))
+ else sail2_state_monad$returnS F)) (\ (w__33 : bool) .
+ sail2_state_monad$returnS w__33))
+ else sail2_state_monad$returnS F)) (\ (w__35 : bool) .
+ sail2_state_monad$returnS w__35))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))) (\ (w__38 :
+ bool) .
+ if w__38 then
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_15_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_14_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_13_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_15_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_14_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_13_0) (\ aq . sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_12_0) (\ op . sail2_state_monad$returnS T))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_16_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_mul_op_backwards_matches mappingpatterns_16_0)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_16_0)) then sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_16_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__41 :
+ bool) .
+ if w__41 then
+ let (mappingpatterns_16_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_16_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_17_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_17_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_17_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_17_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__44 :
+ bool) .
+ if w__44 then
+ let (mappingpatterns_17_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_17_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_18_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_18_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_18_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_18_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__47 :
+ bool) .
+ if w__47 then
+ let (mappingpatterns_18_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_18_0) (\ s . sail2_state_monad$returnS T)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii)
+ : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))))
+ then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_19_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_19_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_19_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_19_0) (\ s .
+ sail2_state_monad$returnS ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__50 :
+ bool) .
+ if w__50 then
+ let (mappingpatterns_19_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_19_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_20_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_20_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_20_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_20_0) (\ s .
+ sail2_state_monad$returnS ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii)
+ : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__53 :
+ bool) .
+ if w__53 then
+ let (mappingpatterns_20_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_20_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_22_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_21_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_csrop_backwards_matches mappingpatterns_22_0)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_22_0)) then sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_22_0) (\ op . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_21_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_21_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_21_0) (\ is_imm .
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__55 : bool) .
+ sail2_state_monad$returnS w__55))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__58 :
+ bool) .
+ if w__58 then
+ let (mappingpatterns_22_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_21_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_22_0) (\ op . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_21_0) (\ is_imm .
+ sail2_state_monad$returnS T))
+ else
+ sail2_state_monad$returnS (if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+ B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ T
+ else T)))))))))))))))))`;
+
+
+(*val encdec_compressed_forwards : ast -> M (mword ty16)*)
+
+val _ = Define `
+ ((encdec_compressed_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ C_NOP (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B1] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_ADDI4SPN ((rd, v__438)) =>
+ if (let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__438 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__438 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__438 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) then
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__438 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__438 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__438 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nz54
+ ((concat_vec nz96
+ ((concat_vec nz2
+ ((concat_vec nz3
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 11 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LW ((v__439, rs1, rd)) =>
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__439 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__439 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__439 (( 3 : int):ii) (( 1 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__439 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_LD ((v__440, rs1, rd)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__440 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__440 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__440 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SW ((v__441, rs1, rs2)) =>
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__441 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__441 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__441 (( 3 : int):ii) (( 1 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__441 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rs2 (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SD ((v__442, rs1, rs2)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__442 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__442 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__442 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDI ((v__443, rsd)) =>
+ if (let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__443 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) then
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__443 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nzi5
+ ((concat_vec rsd
+ ((concat_vec nzi40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JAL (v__444) =>
+ if ((((( 32 : int):ii) = (( 32 : int):ii)))) then
+ let (i11 : 1 bits) = ((subrange_vec_dec v__444 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i98 : 2 bits) = ((subrange_vec_dec v__444 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__444 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__444 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__444 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__444 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__444 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__444 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__444 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 8 words$word))
+ : 9 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDIW ((v__445, rsd)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))))
+ then
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__445 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__445 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__445 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec imm5
+ ((concat_vec rsd
+ ((concat_vec imm40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LI ((v__446, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__446 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__446 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__446 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec imm5
+ ((concat_vec rd
+ ((concat_vec imm40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDI16SP (v__447) =>
+ if (let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__447 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__447 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__447 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__447 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__447 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__447 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__447 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__447 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec nzi9
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec nzi4
+ ((concat_vec nzi6
+ ((concat_vec nzi87
+ ((concat_vec nzi5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LUI ((v__448, rd)) =>
+ if (let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__448 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) then
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__448 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec imm17
+ ((concat_vec rd
+ ((concat_vec imm1612 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SRLI ((v__449, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__449 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__449 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SRAI ((v__450, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__450 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__450 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ANDI ((v__451, rsd)) =>
+ let (i5 : 1 bits) = ((subrange_vec_dec v__451 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__451 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i40 : 5 bits) = ((subrange_vec_dec v__451 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec i5
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec i40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SUB ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_XOR ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_OR ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_AND ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_J (v__452) =>
+ let (i11 : 1 bits) = ((subrange_vec_dec v__452 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i98 : 2 bits) = ((subrange_vec_dec v__452 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__452 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__452 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__452 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__452 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__452 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__452 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__452 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 8 words$word))
+ : 9 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_BEQZ ((v__453, rs)) =>
+ let (i8 : 1 bits) = ((subrange_vec_dec v__453 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__453 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__453 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__453 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__453 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__453 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word) : 3 words$word))
+ : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_BNEZ ((v__454, rs)) =>
+ let (i8 : 1 bits) = ((subrange_vec_dec v__454 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__454 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__454 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__454 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__454 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__454 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word) : 3 words$word))
+ : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SLLI ((v__455, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__455 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word)))))))))))))
+ then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__455 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LWSP ((v__456, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__456 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__456 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__456 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (ui42 : 3 bits) = ((subrange_vec_dec v__456 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui42
+ ((concat_vec ui76 (vec_of_bits [B1;B0] : 2 words$word) : 4 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LDSP ((v__457, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))))
+ then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__457 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__457 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__457 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (ui43 : 2 bits) = ((subrange_vec_dec v__457 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui43
+ ((concat_vec ui86 (vec_of_bits [B1;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SWSP ((v__458, rs2)) =>
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__458 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__458 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui52 : 4 bits) = ((subrange_vec_dec v__458 (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec ui52
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 9 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SDSP ((v__459, rs2)) =>
+ if ((((( 32 : int):ii) = (( 64 : int):ii)))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__459 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__459 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__459 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec ui86
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec rd
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_EBREAK (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec rsd
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ILLEGAL (s) => sail2_state_monad$returnS s
+ | _ => sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val encdec_compressed_backwards : mword ty16 -> ast*)
+
+val _ = Define `
+ ((encdec_compressed_backwards:(16)words$word -> ast) arg_=
+ (let v__460 = arg_ in
+ if (((v__460 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))
+ then
+ C_NOP ()
+ else if ((((let (nz96 : 4 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ C_ADDI4SPN (rd,
+ (concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word))
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_LW ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word), rs1, rd)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_LD ((concat_vec ui76 ui53 : 5 words$word), rs1, rd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ C_SW ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word), rs1, rs2)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs2 : 3 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (rs1 : 3 bits) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ C_SD ((concat_vec ui76 ui53 : 5 words$word), rs1, rs2)
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADDI ((concat_vec nzi5 nzi40 : 6 words$word), rsd)
+ else if (((((((( 32 : int):ii) = (( 32 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (i98 : 2 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__460 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in
+ C_JAL ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 9 words$word))
+ : 10 words$word))
+ : 11 words$word))
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADDIW ((concat_vec imm5 imm40 : 6 words$word), rsd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_LI ((concat_vec imm5 imm40 : 6 words$word), rd)
+ else if ((((let (nzi9 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regidx_to_regno ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ C_ADDI16SP ((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word))
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_LUI ((concat_vec imm17 imm1612 : 6 words$word), rd)
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SRLI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SRAI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ANDI ((concat_vec i5 i40 : 6 words$word), rsd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_SUB (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_XOR (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_OR (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_AND (rsd, rs2)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_SUBW (rsd, rs2)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_ADDW (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (i98 : 2 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__460 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in
+ C_J ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 9 words$word))
+ : 10 words$word))
+ : 11 words$word))
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (rs : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ C_BEQZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word))
+ : 7 words$word))
+ : 8 words$word),
+ rs)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (rs : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ C_BNEZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word))
+ : 7 words$word))
+ : 8 words$word),
+ rs)
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word))))))))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SLLI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (ui42 : 3 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 4 : int):ii) : 3 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_LWSP ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word), rd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (ui43 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_LDSP ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word), rd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (ui52 : 4 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SWSP ((concat_vec ui76 ui52 : 6 words$word), rs2)
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SDSP ((concat_vec ui86 ui53 : 6 words$word), rs2)
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_JR rs1
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_JALR rs1
+ else if ((((let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_MV (rd, rs2)
+ else if (((v__460 = (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 16 words$word)))) then
+ C_EBREAK ()
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADD (rsd, rs2)
+ else C_ILLEGAL v__460))`;
+
+
+(*val encdec_compressed_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((encdec_compressed_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ C_NOP (() ) => T
+ | C_ADDI4SPN ((rd, v__596)) =>
+ if (let (nz96 : 4 bits) = ((subrange_vec_dec v__596 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__596 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__596 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__596 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__596 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) then
+ T
+ else F
+ | C_LW ((v__597, rs1, rd)) => T
+ | C_LD ((v__598, rs1, rd)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_SW ((v__599, rs1, rs2)) => T
+ | C_SD ((v__600, rs1, rs2)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_ADDI ((v__601, rsd)) =>
+ if (let (nzi5 : 1 bits) = ((subrange_vec_dec v__601 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__601 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__601 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) then
+ T
+ else F
+ | C_JAL (v__602) => if ((((( 32 : int):ii) = (( 32 : int):ii)))) then T else F
+ | C_ADDIW ((v__603, rsd)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))))
+ then
+ T
+ else F
+ | C_LI ((v__604, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_ADDI16SP (v__605) =>
+ if (let (nzi9 : 1 bits) = ((subrange_vec_dec v__605 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__605 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__605 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__605 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__605 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__605 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_LUI ((v__606, rd)) =>
+ if (let (imm17 : 1 bits) = ((subrange_vec_dec v__606 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__606 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__606 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) then
+ T
+ else F
+ | C_SRLI ((v__607, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__607 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__607 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__607 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_SRAI ((v__608, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__608 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__608 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__608 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_ANDI ((v__609, rsd)) => T
+ | C_SUB ((rsd, rs2)) => T
+ | C_XOR ((rsd, rs2)) => T
+ | C_OR ((rsd, rs2)) => T
+ | C_AND ((rsd, rs2)) => T
+ | C_SUBW ((rsd, rs2)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_ADDW ((rsd, rs2)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_J (v__610) => T
+ | C_BEQZ ((v__611, rs)) => T
+ | C_BNEZ ((v__612, rs)) => T
+ | C_SLLI ((v__613, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__613 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__613 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__613 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word)))))))))))))
+ then
+ T
+ else F
+ | C_LWSP ((v__614, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_LDSP ((v__615, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))))
+ then
+ T
+ else F
+ | C_SWSP ((v__616, rs2)) => T
+ | C_SDSP ((v__617, rs2)) => if ((((( 32 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_JR (rs1) => if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T
+ else F
+ | C_EBREAK (() ) => T
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T
+ else F
+ | C_ILLEGAL (s) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_compressed_backwards_matches : mword ty16 -> bool*)
+
+val _ = Define `
+ ((encdec_compressed_backwards_matches:(16)words$word -> bool) arg_=
+ (let v__618 = arg_ in
+ if (((v__618 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))
+ then
+ T
+ else if ((((let (nz96 : 4 bits) = ((subrange_vec_dec v__618 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__618 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 32 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (nzi9 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__618 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__618 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__618 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regidx_to_regno ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 32 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word))))))))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 32 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ T
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ T
+ else if ((((let (rs2 : regidx) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if (((v__618 = (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 16 words$word)))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else T))`;
+
+
+(*val execute_WFI : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_WFI:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .
+ (case w__0 of
+ Machine => sail2_state_monad$seqS (platform_wfi () ) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .
+ if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS
+ (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$seqS (platform_wfi () ) (sail2_state_monad$returnS RETIRE_SUCCESS))
+ | User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ ))))`;
+
+
+(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M Retired*)
+
+val _ = Define `
+ ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd op=
+ (let (off : xlenbits) =
+ ((EXTS (( 32 : int):ii)
+ ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ : 32 words$word))
+ : 32 words$word)) in sail2_state_monad$bindS
+ (case op of
+ RISCV_LUI => sail2_state_monad$returnS off
+ | RISCV_AUIPC => sail2_state_monad$bindS
+ (get_arch_pc () : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ sail2_state_monad$returnS ((add_vec w__0 off : 32 words$word)))
+ ) (\ (ret : xlenbits) . sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ret) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_URET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_URET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$seqS
+ (if ((~ w__0)) then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_URET () ) w__2 : ( 32 words$word) M) (\ (w__3 : 32 words$word) .
+ set_next_pc w__3))))
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (sail2_state_monad$bindS
+ (speculate_conditional_success () ) (\ (w__0 : bool) .
+ if (((w__0 = F))) then sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTZ (( 32 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)
+ else sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__1 : bool) .
+ if w__1 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 32 : int):ii) : 32 words$word)) Write width) (\ (w__2 : unit
+ Ext_DataAddr_Check) .
+ (case w__2 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ let (aligned : bool) =
+ ((case width of
+ BYTE => T
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))
+ )) in
+ if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else if (((((match_reservation vaddr)) = F))) then sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTZ (( 32 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Write : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__3 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__3 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) => mem_write_ea addr (( 4 : int):ii) aq rl T
+ | _ => internal_error "STORECON expected word or double"
+ ) (\ (eares : unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val . sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) =>
+ mem_write_value addr (( 4 : int):ii)
+ ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq rl T
+ | _ => internal_error "STORECON expected word or double"
+ ) (\ (res : bool MemoryOpResult) .
+ (case res of
+ MemValue (T) => sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemValue (F) => sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTZ (( 32 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))
+ ))
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))))`;
+
+
+(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 width aq rl=
+ (let (offset : xlenbits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in sail2_state_monad$bindS
+ (ext_data_get_addr rs1 offset Write width) (\ (w__0 : unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Write : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__1 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case width of
+ BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F
+ | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F
+ | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F
+ | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F
+ ) (\ (eares : unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val . sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (BYTE, _) =>
+ mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ aq rl F
+ | (HALF, _) =>
+ mem_write_value addr (( 2 : int):ii)
+ ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) aq rl F
+ | (WORD, _) =>
+ mem_write_value addr (( 4 : int):ii)
+ ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq rl F
+ ) (\ (res : bool MemoryOpResult) .
+ (case res of
+ MemValue (T) => sail2_state_monad$returnS RETIRE_SUCCESS
+ | MemValue (F) => internal_error "store got false from mem_write_value"
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))
+ ))
+ ))
+ ))))`;
+
+
+(*val execute_SRET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_SRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS
+ (case w__0 of
+ User => handle_illegal ()
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_TSR w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) (\ (w__3 :
+ bool) .
+ if w__3 then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__4 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__4 (CTL_SRET () ) w__5 : ( 32 words$word) M) (\ (w__6 : 32 words$word) .
+ set_next_pc w__6))))
+ | Machine => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__7 : bool) .
+ if ((~ w__7)) then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__8 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__8 (CTL_SRET () ) w__9 : ( 32 words$word) M) (\ (w__10 : 32 words$word) .
+ set_next_pc w__10))))
+ )
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word)
+ | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 32 : int):ii) result : 32 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SHIFTIWOP : mword ty5 -> mword ty5 -> mword ty5 -> sopw -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTIWOP:(5)words$word ->(5)words$word ->(5)words$word -> sopw ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val .
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_SLLIW =>
+ (shift_bits_left ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ | RISCV_SRLIW =>
+ (shift_bits_right ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ | RISCV_SRAIW =>
+ (shift_right_arith32 ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 32 : int):ii) result : 32 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val .
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_SLLI =>
+ (shift_bits_left rs1_val ((subrange_vec_dec shamt (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) : 32 words$word)
+ | RISCV_SRLI =>
+ (shift_bits_right rs1_val ((subrange_vec_dec shamt (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRAI =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec shamt (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs1 rs2= (sail2_state_monad$bindS
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__0))) (\ (addr : xlenbits option) . sail2_state_monad$bindS
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ sail2_state_monad$returnS (SOME w__1))) (\ (asid : xlenbits option) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) .
+ (case w__2 of
+ User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ let p__1 =
+ (architecture ((get_mstatus_SXL w__3 : 2 words$word)), (get_Mstatus_TVM w__4 : 1 words$word)) in
+ (case p__1 of
+ (SOME (g__0), v_0) =>
+ if (((v_0 = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS
+ (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else if (((v_0 = ((bool_to_bits F : 1 words$word))))) then sail2_state_monad$seqS
+ (flush_TLB asid addr) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ else
+ (case (SOME g__0, v_0) of
+ (_, _) => internal_error "unimplemented sfence architecture"
+ )
+ | (_, _) => internal_error "unimplemented sfence architecture"
+ )))
+ | Machine => sail2_state_monad$seqS (flush_TLB asid addr) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ ))))))`;
+
+
+(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M Retired*)
+
+val _ = Define `
+ ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_ADDW => (add_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SUBW => (sub_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SLLW =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRLW =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRAW =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 32 : int):ii) result : 32 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M Retired*)
+
+val _ = Define `
+ ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val .
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_ADD => (add_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SLT =>
+ (EXTZ (( 32 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) : 1 words$word)) : 32 words$word)
+ | RISCV_SLTU =>
+ (EXTZ (( 32 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) : 1 words$word)) : 32 words$word)
+ | RISCV_AND => (and_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_OR => (or_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_XOR => (xor_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SLL =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRL =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SUB => (sub_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SRA =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 32 : int):ii) imm : 32 words$word)) : 32 words$word)) in
+ (case ((ext_control_check_addr t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (addr) =>
+ let target = ((update_vec_dec addr (( 0 : int):ii) B0 : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (get_next_pc () : ( 32 words$word) M) (\ (w__3 : 32 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) w__3) (set_next_pc target)) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ ))))`;
+
+
+(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 32 : int):ii) imm : 32 words$word)) : 32 words$word)) in
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (target) => sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (get_next_pc () : ( 32 words$word) M) (\ (w__3 : 32 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) w__3) (set_next_pc target)) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ ))))`;
+
+
+(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (w__2 : 32 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 32 : int):ii) ((to_bits (( 32 : int):ii) r : 32 words$word)) : 32 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((to_bits (( 32 : int):ii) r : 32 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (w__2 : 32 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (integer_word$w2i rs1_val) in
+ let (rs2_int : ii) = (integer_word$w2i rs2_val) in
+ let result32 =
+ ((subrange_vec_dec ((to_bits (( 64 : int):ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):ii)
+ (( 0 : int):ii)
+ : 32 words$word)) in
+ let (result : xlenbits) = ((EXTS (( 32 : int):ii) result32 : 32 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let result_wide =
+ ((to_bits (((( 2 : int):ii) * (( 32 : int):ii))) ((rs1_int * rs2_int)) : 64 words$word)) in
+ let result =
+ (if high then
+ (subrange_vec_dec result_wide (((((( 2 : int):ii) * (( 32 : int):ii))) - (( 1 : int):ii)))
+ (( 32 : int):ii)
+ : 32 words$word)
+ else (subrange_vec_dec result_wide (((( 32 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MRET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_MRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS
+ (if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_MRET () ) w__2 : ( 32 words$word) M) (\ (w__3 : 32 words$word) .
+ set_next_pc w__3)))
+ else handle_illegal () )
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs1 width rd= (sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 32 : int):ii) : 32 words$word)) Read width) (\ (w__1 : unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ let (aligned : bool) =
+ ((case width of
+ BYTE => T
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))
+ )) in
+ if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Read : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__2 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) =>
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) => sail2_state_monad$bindS
+ (mem_read Read addr (( 4 : int):ii) aq rl T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__3 : ( 32 words$word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__3 F)
+ | _ => internal_error "LOADRES expected WORD or DOUBLE"
+ )
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl=
+ (let (offset : xlenbits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in sail2_state_monad$bindS
+ (ext_data_get_addr rs1 offset Read width) (\ (w__0 : unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+ (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Read : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__1 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) =>
+ (case (width, (( 32 : int):ii)) of
+ (BYTE, _) => sail2_state_monad$bindS
+ (mem_read Read addr (( 1 : int):ii) aq rl F : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word)
+ MemoryOpResult) .
+ process_load rd vaddr w__2 is_unsigned)
+ | (HALF, _) => sail2_state_monad$bindS
+ (mem_read Read addr (( 2 : int):ii) aq rl F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__4 : ( 16 words$word)
+ MemoryOpResult) .
+ process_load rd vaddr w__4 is_unsigned)
+ | (WORD, _) => sail2_state_monad$bindS
+ (mem_read Read addr (( 4 : int):ii) aq rl F : ( ( 32 words$word)MemoryOpResult) M) (\ (w__6 : ( 32 words$word)
+ MemoryOpResult) .
+ process_load rd vaddr w__6 is_unsigned)
+ )
+ ))
+ ))))`;
+
+
+(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M Retired*)
+
+val _ = Define `
+ ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val .
+ let (immext : xlenbits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_ADDI => (add_vec rs1_val immext : 32 words$word)
+ | RISCV_SLTI =>
+ (EXTZ (( 32 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) : 1 words$word)) : 32 words$word)
+ | RISCV_SLTIU =>
+ (EXTZ (( 32 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) : 1 words$word)) : 32 words$word)
+ | RISCV_ANDI => (and_vec rs1_val immext : 32 words$word)
+ | RISCV_ORI => (or_vec rs1_val immext : 32 words$word)
+ | RISCV_XORI => (xor_vec rs1_val immext : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_ILLEGAL : mword ty32 -> M Retired*)
+
+val _ = Define `
+ ((execute_ILLEGAL:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))`;
+
+
+(*val execute_FENCE_TSO : mword ty4 -> mword ty4 -> M Retired*)
+
+val _ = Define `
+ ((execute_FENCE_TSO:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ= (sail2_state_monad$seqS
+ (case (pred, succ) of
+ (v__794, v__795) =>
+ if ((((((((subrange_vec_dec v__794 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__795 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_tso
+ else
+ sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__794 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__795 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ ()
+ else
+ let (_ : unit) = (print_endline "FIXME: unsupported fence") in
+ () )
+ )
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))`;
+
+
+(*val execute_FENCEI : unit -> Retired*)
+
+val _ = Define `
+ ((execute_FENCEI:unit -> Retired) () = RETIRE_SUCCESS)`;
+
+
+(*val execute_FENCE : mword ty4 -> mword ty4 -> M Retired*)
+
+val _ = Define `
+ ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ= (sail2_state_monad$seqS
+ (case (pred, succ) of
+ (v__754, v__755) =>
+ if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_r
+ else
+ sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ ()
+ else
+ let (_ : unit) = (print_endline "FIXME: unsupported fence") in
+ () )
+ )
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))`;
+
+
+(*val execute_ECALL : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_ECALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .
+ let (t : sync_exception) =
+ (<| sync_exception_trap :=
+ ((case w__0 of
+ User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ ));
+ sync_exception_excinfo := NONE;
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_TRAP t) w__2 : ( 32 words$word) M) (\ (w__3 : 32 words$word) . sail2_state_monad$seqS
+ (set_next_pc w__3) (sail2_state_monad$returnS RETIRE_FAIL)))))))`;
+
+
+(*val execute_EBREAK : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_EBREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$seqS
+ (handle_mem_exception w__0 E_Breakpoint) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (w__2 : 32 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in
+ let (q' : ii) =
+ (if (((s /\ ((q > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then
+ (( 0 : int):ii) - ((pow0 (( 2 : int):ii) (( 31 : int):ii)))
+ else q) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 32 : int):ii) ((to_bits (( 32 : int):ii) q' : 32 words$word)) : 32 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in
+ let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((to_bits (( 32 : int):ii) q' : 32 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_C_NOP : unit -> Retired*)
+
+val _ = Define `
+ ((execute_C_NOP:unit -> Retired) () = RETIRE_SUCCESS)`;
+
+
+(*val execute_C_ILLEGAL : mword ty16 -> M Retired*)
+
+val _ = Define `
+ ((execute_C_ILLEGAL:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))`;
+
+
+(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M Retired*)
+
+val _ = Define `
+ ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr rs1 rd is_imm op= (sail2_state_monad$bindS
+ (if is_imm then sail2_state_monad$returnS ((EXTZ (( 32 : int):ii) rs1 : 32 words$word))
+ else (rX ((regidx_to_regno rs1)) : ( 32 words$word) M)) (\ (rs1_val : xlenbits) .
+ let (isWrite : bool) =
+ ((case op of
+ CSRRW => T
+ | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii))
+ )) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (check_CSR csr w__1 isWrite) (\ (w__2 : bool) .
+ if ((~ w__2)) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (readCSR csr : ( 32 words$word) M) (\ csr_val . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (if isWrite then
+ let (new_val : xlenbits) =
+ ((case op of
+ CSRRW => rs1_val
+ | CSRRS => (or_vec csr_val rs1_val : 32 words$word)
+ | CSRRC => (and_vec csr_val ((not_vec rs1_val : 32 words$word)) : 32 words$word)
+ )) in
+ writeCSR csr new_val
+ else sail2_state_monad$returnS () )
+ (wX ((regidx_to_regno rd)) csr_val)) (sail2_state_monad$returnS RETIRE_SUCCESS)))))))`;
+
+
+(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M Retired*)
+
+val _ = Define `
+ ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ rs2_val .
+ let (taken : bool) =
+ ((case op of
+ RISCV_BEQ => (rs1_val = rs2_val)
+ | RISCV_BNE => (rs1_val <> rs2_val)
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ )) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 32 : int):ii) imm : 32 words$word)) : 32 words$word)) in
+ if taken then
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (target) => sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$seqS (set_next_pc target) (sail2_state_monad$returnS RETIRE_SUCCESS))
+ )
+ else sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 32 : int):ii) : 32 words$word)) ReadWrite width) (\ (w__1 : unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) => sail2_state_monad$bindS
+ (translateAddr vaddr ReadWrite : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__2 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) => mem_write_ea addr (( 4 : int):ii) (((aq /\ rl))) rl T
+ | _ => internal_error "AMO expected WORD or DOUBLE"
+ ) (\ (eares : unit MemoryOpResult) . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 32 words$word) M) (\ (rs2_val : xlenbits) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) => sail2_state_monad$bindS
+ (mem_read ReadWrite addr (( 4 : int):ii) aq (((aq /\ rl))) T
+ : ( ( 32 words$word)MemoryOpResult) M) (\ (w__5 : ( 32 words$word) MemoryOpResult) .
+ sail2_state_monad$returnS ((extend_value F w__5 : ( 32 words$word) MemoryOpResult)))
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE" : ( ( 32 words$word)MemoryOpResult) M)
+ ) (\ (rval : xlenbits MemoryOpResult) .
+ (case rval of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (loaded) =>
+ let (result : xlenbits) =
+ ((case op of
+ AMOSWAP => rs2_val
+ | AMOADD => (add_vec rs2_val loaded : 32 words$word)
+ | AMOXOR => (xor_vec rs2_val loaded : 32 words$word)
+ | AMOAND => (and_vec rs2_val loaded : 32 words$word)
+ | AMOOR => (or_vec rs2_val loaded : 32 words$word)
+ | AMOMIN =>
+ (to_bits (( 32 : int):ii) ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 32 words$word)
+ | AMOMAX =>
+ (to_bits (( 32 : int):ii) ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 32 words$word)
+ | AMOMINU =>
+ (to_bits (( 32 : int):ii) ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 32 words$word)
+ | AMOMAXU =>
+ (to_bits (( 32 : int):ii) ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 32 words$word)
+ )) in sail2_state_monad$bindS
+ (case (width, (( 32 : int):ii)) of
+ (WORD, _) =>
+ mem_write_value addr (( 4 : int):ii)
+ ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) (((aq /\ rl))) rl
+ T
+ | _ => internal_error "AMO expected WORD or DOUBLE"
+ ) (\ (wval : bool MemoryOpResult) .
+ (case wval of
+ MemValue (T) => sail2_state_monad$seqS (wX ((regidx_to_regno rd)) loaded) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemValue (F) => internal_error "AMO got false from mem_write_value"
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ ))
+ ))
+ )))
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ let (result : xlenbits) = ((add_vec ((EXTS (( 32 : int):ii) imm : 32 words$word)) w__0 : 32 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTS (( 32 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 32 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+ val execute_defn = Hol_defn "execute" `
+ ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var=
+ ((case merge_var of
+ C_ADDI4SPN ((rdc, nzimm)) =>
+ let (imm : 12 bits) =
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec nzimm (vec_of_bits [B0;B0] : 2 words$word) : 10 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ execute (ITYPE (imm, sp, rd, RISCV_ADDI))
+ | C_LW ((uimm, rsc, rdc)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ let rs = ((creg2reg_idx rsc : 5 words$word)) in
+ execute (LOAD (imm, rs, rd, F, WORD, F, F))
+ | C_LD ((uimm, rsc, rdc)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ let rs = ((creg2reg_idx rsc : 5 words$word)) in
+ execute (LOAD (imm, rs, rd, F, DOUBLE, F, F))
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word)) in
+ let rs1 = ((creg2reg_idx rsc1 : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rsc2 : 5 words$word)) in
+ execute (STORE (imm, rs2, rs1, WORD, F, F))
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word))
+ : 12 words$word)) in
+ let rs1 = ((creg2reg_idx rsc1 : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rsc2 : 5 words$word)) in
+ execute (STORE (imm, rs2, rs1, DOUBLE, F, F))
+ | C_ADDI ((nzi, rsd)) =>
+ let (imm : 12 bits) = ((EXTS (( 12 : int):ii) nzi : 12 words$word)) in
+ execute (ITYPE (imm, rsd, rsd, RISCV_ADDI))
+ | C_JAL (imm) =>
+ execute
+ (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))
+ : 21 words$word),
+ ra))
+ | C_ADDIW ((imm, rsd)) => execute (ADDIW ((EXTS (( 12 : int):ii) imm : 12 words$word), rsd, rsd))
+ | C_LI ((imm, rd)) =>
+ let (imm : 12 bits) = ((EXTS (( 12 : int):ii) imm : 12 words$word)) in
+ execute (ITYPE (imm, zreg, rd, RISCV_ADDI))
+ | C_ADDI16SP (imm) =>
+ let (imm : 12 bits) =
+ ((EXTS (( 12 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 10 words$word))
+ : 12 words$word)) in
+ execute (ITYPE (imm, sp, sp, RISCV_ADDI))
+ | C_LUI ((imm, rd)) =>
+ let (res : 20 bits) = ((EXTS (( 20 : int):ii) imm : 20 words$word)) in
+ execute (UTYPE (res, rd, RISCV_LUI))
+ | C_SRLI ((shamt, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))
+ | C_SRAI ((shamt, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))
+ | C_ANDI ((imm, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (ITYPE ((EXTS (( 12 : int):ii) imm : 12 words$word), rsd, rsd, RISCV_ANDI))
+ | C_SUB ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_SUB))
+ | C_XOR ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_XOR))
+ | C_OR ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_OR))
+ | C_AND ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_AND))
+ | C_SUBW ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_SUBW))
+ | C_ADDW ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_ADDW))
+ | C_J (imm) =>
+ execute
+ (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))
+ : 21 words$word),
+ zreg))
+ | C_BEQZ ((imm, rs)) =>
+ execute
+ (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word))
+ : 13 words$word),
+ zreg,
+ (creg2reg_idx rs : 5 words$word),
+ RISCV_BEQ))
+ | C_BNEZ ((imm, rs)) =>
+ execute
+ (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word))
+ : 13 words$word),
+ zreg,
+ (creg2reg_idx rs : 5 words$word),
+ RISCV_BNE))
+ | C_SLLI ((shamt, rsd)) => execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI))
+ | C_LWSP ((uimm, rd)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word))
+ : 12 words$word)) in
+ execute (LOAD (imm, sp, rd, F, WORD, F, F))
+ | C_LDSP ((uimm, rd)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word))
+ : 12 words$word)) in
+ execute (LOAD (imm, sp, rd, F, DOUBLE, F, F))
+ | C_SWSP ((uimm, rs2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word))
+ : 12 words$word)) in
+ execute (STORE (imm, rs2, sp, WORD, F, F))
+ | C_SDSP ((uimm, rs2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word))
+ : 12 words$word)) in
+ execute (STORE (imm, rs2, sp, DOUBLE, F, F))
+ | C_JR (rs1) =>
+ execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word), rs1, zreg))
+ | C_JALR (rs1) =>
+ execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word), rs1, ra))
+ | C_MV ((rd, rs2)) => execute (RTYPE (rs2, zreg, rd, RISCV_ADD))
+ | C_EBREAK (() ) => execute (EBREAK () )
+ | C_ADD ((rsd, rs2)) => execute (RTYPE (rs2, rsd, rsd, RISCV_ADD))
+ | UTYPE ((imm, rd, op)) => execute_UTYPE imm rd op
+ | RISCV_JAL ((imm, rd)) => execute_RISCV_JAL imm rd
+ | BTYPE ((imm, rs2, rs1, op)) => execute_BTYPE imm rs2 rs1 op
+ | ITYPE ((imm, rs1, rd, op)) => execute_ITYPE imm rs1 rd op
+ | SHIFTIOP ((shamt, rs1, rd, op)) => execute_SHIFTIOP shamt rs1 rd op
+ | RTYPE ((rs2, rs1, rd, op)) => execute_RTYPE rs2 rs1 rd op
+ | LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl)) =>
+ execute_LOAD imm rs1 rd is_unsigned width aq rl
+ | STORE ((imm, rs2, rs1, width, aq, rl)) => execute_STORE imm rs2 rs1 width aq rl
+ | ADDIW ((imm, rs1, rd)) => execute_ADDIW imm rs1 rd
+ | SHIFTW ((shamt, rs1, rd, op)) => execute_SHIFTW shamt rs1 rd op
+ | RTYPEW ((rs2, rs1, rd, op)) => execute_RTYPEW rs2 rs1 rd op
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => execute_SHIFTIWOP shamt rs1 rd op
+ | FENCE ((pred, succ)) => execute_FENCE pred succ
+ | FENCE_TSO ((pred, succ)) => execute_FENCE_TSO pred succ
+ | FENCEI (arg0) => sail2_state_monad$returnS ((execute_FENCEI arg0))
+ | ECALL (arg0) => execute_ECALL arg0
+ | MRET (arg0) => execute_MRET arg0
+ | SRET (arg0) => execute_SRET arg0
+ | EBREAK (arg0) => execute_EBREAK arg0
+ | WFI (arg0) => execute_WFI arg0
+ | SFENCE_VMA ((rs1, rs2)) => execute_SFENCE_VMA rs1 rs2
+ | LOADRES ((aq, rl, rs1, width, rd)) => execute_LOADRES aq rl rs1 width rd
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) => execute_STORECON aq rl rs2 rs1 width rd
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => execute_AMO op aq rl rs2 rs1 width rd
+ | C_NOP (arg0) => sail2_state_monad$returnS ((execute_C_NOP arg0))
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => execute_MUL rs2 rs1 rd high signed1 signed2
+ | DIV0 ((rs2, rs1, rd, s)) => execute_DIV rs2 rs1 rd s
+ | REM ((rs2, rs1, rd, s)) => execute_REM rs2 rs1 rd s
+ | MULW ((rs2, rs1, rd)) => execute_MULW rs2 rs1 rd
+ | DIVW ((rs2, rs1, rd, s)) => execute_DIVW rs2 rs1 rd s
+ | REMW ((rs2, rs1, rd, s)) => execute_REMW rs2 rs1 rd s
+ | CSR ((csr, rs1, rd, is_imm, op)) => execute_CSR csr rs1 rd is_imm op
+ | URET (arg0) => execute_URET arg0
+ | RISCV_JALR ((imm, rs1, rd)) => execute_RISCV_JALR imm rs1 rd
+ | ILLEGAL (s) => execute_ILLEGAL s
+ | C_ILLEGAL (s) => execute_C_ILLEGAL s
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn;
+
+(*val assembly_forwards : ast -> M string*)
+
+val _ = Define `
+ ((assembly_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__0 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((utype_mnemonic_forwards op))
+ ((string_append
+ ((spc_forwards () ))
+ ((string_append w__0
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm))
+ "")))))))))))
+ | RISCV_JAL ((imm, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__1 : string) .
+ sail2_state_monad$returnS
+ ((string_append "jal"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__1
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | RISCV_JALR ((imm, rs1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__2 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__3 : string) .
+ sail2_state_monad$returnS
+ ((
+ string_append
+ "jalr"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__2
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__3
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | BTYPE ((imm, rs2, rs1, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__4 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__5 : string) .
+ sail2_state_monad$returnS
+ ((
+ string_append
+ (
+ (
+ btype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__4
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__5
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | ITYPE ((imm, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__6 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__7 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ (
+ (
+ itype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__6
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__7
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | SHIFTIOP ((shamt, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__8 : string) . sail2_state_monad$bindS
+ (
+ reg_name_forwards
+ rs1)
+ (
+ \ (w__9 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ shiftiop_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__8
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__9
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ | RTYPE ((rs2, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__10 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__11 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__12 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ rtype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__10
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__11
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__12
+ "")))))))))))))))))
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl)) => sail2_state_monad$bindS
+ (reg_name_forwards
+ rd)
+ (\ (w__13 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__14 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "l"
+ (
+ (
+ string_append
+ (
+ (
+ size_mnemonic_forwards
+ size1))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_u_forwards
+ is_unsigned))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__13
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ "("
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__14
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ ")"
+ ""))))))))))))))))))))))))))))))))
+ | STORE ((imm, rs2, rs1, size1, aq, rl)) => sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__15 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__16 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "s"
+ ((string_append
+ ((size_mnemonic_forwards
+ size1))
+ ((string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__15
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ "("
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__16
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ ")"
+ ""))))))))))))))))))))))))))))))
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__17 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__18 : string) .
+ sail2_state_monad$returnS
+ ((string_append "addiw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__17
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__18
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__21 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__22 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((shiftw_mnemonic_forwards op))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__21
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__22
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__25 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__26 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__27 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((rtypew_mnemonic_forwards
+ op))
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__25
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__26
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__27
+ "")))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__30 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__31 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((shiftiwop_mnemonic_forwards op))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__30
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__31
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | FENCE ((pred, succ)) => sail2_state_monad$bindS
+ (fence_bits_forwards pred)
+ (\ (w__34 : string) . sail2_state_monad$bindS
+ (fence_bits_forwards
+ succ)
+ (\ (w__35 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "fence"
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__34
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__35
+ ""))))))))))))
+ | FENCE_TSO ((pred, succ)) => sail2_state_monad$bindS
+ (fence_bits_forwards pred)
+ (\ (w__36 : string) . sail2_state_monad$bindS
+ (fence_bits_forwards
+ succ)
+ (\ (w__37 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "fence.tso"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__36
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__37
+ ""))))))))))))
+ | FENCEI (() ) => sail2_state_monad$returnS "fence.i"
+ | ECALL (() ) => sail2_state_monad$returnS "ecall"
+ | MRET (() ) => sail2_state_monad$returnS "mret"
+ | SRET (() ) => sail2_state_monad$returnS "sret"
+ | EBREAK (() ) => sail2_state_monad$returnS "ebreak"
+ | WFI (() ) => sail2_state_monad$returnS "wfi"
+ | SFENCE_VMA ((rs1, rs2)) => sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__38 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__39 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "sfence.vma"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__38
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__39
+ ""))))))))))))
+ | LOADRES ((aq, rl, rs1, size1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__40 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__41 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "lr."
+ ((string_append
+ ((size_mnemonic_forwards
+ size1))
+ ((string_append
+ ((maybe_aq_forwards
+ aq))
+ ((string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__40
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__41
+ ""))))))))))))))))))
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__42 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__43 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__44 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "sc."
+ ((string_append
+ (
+ (
+ size_mnemonic_forwards
+ size1))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__42
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__43
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__44
+ "")))))))))))))))))))))))
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__45 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__46 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__47 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((amo_mnemonic_forwards
+ op))
+ ((string_append
+ "."
+ (
+ (
+ string_append
+ (
+ (
+ size_mnemonic_forwards
+ width))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__45
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__46
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__47
+ "")))))))))))))))))))))))))
+ | C_NOP (() ) => sail2_state_monad$returnS "c.nop"
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if (((nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rdc)
+ (\ (w__48 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addi4spn"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__48
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec nzimm
+ (vec_of_bits [B0;B0] : 2 words$word)
+ : 10 words$word)))) ""))))))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LW ((uimm, rsc, rdc)) => sail2_state_monad$bindS
+ (creg_name_forwards rdc)
+ (\ (w__51 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rsc)
+ (\ (w__52 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.lw"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__51
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__52
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ (
+ (
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0] : 2 words$word)
+ : 7 words$word))))
+ ""))))))))))))))))
+ | C_LD ((uimm, rsc, rdc)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rdc)
+ (\ (w__53 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rsc)
+ (\ (w__54 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.ld"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__53
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__54
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0;B0] : 3 words$word)
+ : 8 words$word))))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SW ((uimm, rsc1, rsc2)) => sail2_state_monad$bindS
+ (creg_name_forwards rsc1)
+ (\ (w__57 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rsc2)
+ (\ (w__58 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.sw"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__57
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__58
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ (
+ (
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0] : 2 words$word)
+ : 7 words$word))))
+ ""))))))))))))))))
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsc1)
+ (\ (w__59 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rsc2)
+ (\ (w__60 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.sd"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__59
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__60
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0;B0] : 3 words$word)
+ : 8 words$word))))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDI ((nzi, rsd)) =>
+ if ((((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__63 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addi"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__63
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits nzi)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JAL (imm) =>
+ if ((((( 32 : int): ii) = (( 32 : int): ii)))) then
+ sail2_state_monad$returnS
+ ((string_append "c.jal"
+ ((string_append ((spc_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))))
+ "")))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDIW ((imm, rsd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__68 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addiw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__68
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LI ((imm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__71 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.li"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__71
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDI16SP (imm) =>
+ if (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$returnS
+ ((string_append "c.addi16sp"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LUI ((imm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\
+ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__76 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.lui"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__76
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SRLI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__79 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.srli"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__79
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SRAI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__82 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.srai"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__82
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ANDI ((imm, rsd)) => sail2_state_monad$bindS
+ (creg_name_forwards rsd)
+ (\ (w__85 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.andi"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__85
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_SUB ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__86 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__87 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.sub"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__86
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__87
+ ""))))))))))))
+ | C_XOR ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__88 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__89 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.xor"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__88
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__89
+ ""))))))))))))
+ | C_OR ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__90 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__91 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.or"
+ ((string_append
+ ((spc_forwards
+ () ))
+ ((string_append
+ w__90
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__91
+ ""))))))))))))
+ | C_AND ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__92 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__93 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.and"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__92
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__93
+ ""))))))))))))
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__94 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rs2)
+ (\ (w__95 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.subw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__94
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__95 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__98 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rs2)
+ (\ (w__99 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__98
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__99 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_J (imm) =>
+ sail2_state_monad$returnS
+ ((string_append "c.j"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ""))))))
+ | C_BEQZ ((imm, rs)) => sail2_state_monad$bindS (creg_name_forwards rs)
+ (\ (w__102 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.beqz"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__102
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_BNEZ ((imm, rs)) => sail2_state_monad$bindS (creg_name_forwards rs)
+ (\ (w__103 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.bnez"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__103
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_SLLI ((shamt, rsd)) =>
+ if ((((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__104 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.slli"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__104
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LWSP ((uimm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__107 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.lwsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__107
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LDSP ((uimm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((( 32 : int): ii) = (( 64 : int): ii))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__110 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.ldsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__110
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SWSP ((uimm, rd)) => sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__113 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.swsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__113
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ uimm)) "")))))))))))
+ | C_SDSP ((uimm, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rs2)
+ (\ (w__114 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.sdsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__114
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__117 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.jr"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__117 ""))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__120 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.jalr"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__120 ""))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__123 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__124 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.mv"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__123
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__124 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_EBREAK (() ) => sail2_state_monad$returnS "c.ebreak"
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__127 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__128 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.add"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__127
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__128 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => sail2_state_monad$bindS
+ (reg_name_forwards
+ rd)
+ (\ (w__131 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__132 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__133 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ (
+ (
+ mul_mnemonic_forwards
+ (high, signed1, signed2)))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__131
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__132
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__133
+ "")))))))))))))))))
+ | DIV0 ((rs2, rs1, rd, s)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__134 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__135 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__136 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "div"
+ (
+ (
+ string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__134
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__135
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__136
+ "")))))))))))))))))))
+ | REM ((rs2, rs1, rd, s)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__137 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__138 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__139 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "rem"
+ (
+ (
+ string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__137
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__138
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__139
+ "")))))))))))))))))))
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__140 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__141 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__142 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "mulw"
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__140
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__141
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__142
+ "")))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__145 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__146 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__147 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "div"
+ ((string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ "w"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__145
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__146
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__147
+ "")))))))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__150 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__151 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__152 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "rem"
+ ((string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ "w"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__150
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__151
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__152
+ "")))))))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | CSR ((csr, rs1, rd, T, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__155 : string) . sail2_state_monad$bindS
+ (csr_name_map_forwards
+ csr)
+ (\ (w__156 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ csr_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ "i"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__155
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ rs1))
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__156
+ ""))))))))))))))))))
+ | CSR ((csr, rs1, rd, F, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__157 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__158 : string) .
+ sail2_state_monad$bindS
+ (
+ csr_name_map_forwards
+ csr)
+ (
+ \ (w__159 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ csr_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__157
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__158
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__159
+ "")))))))))))))))))
+ | URET (() ) => sail2_state_monad$returnS "uret"
+ | ILLEGAL (s) =>
+ sail2_state_monad$returnS
+ ((string_append "illegal"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) ""))))))
+ | C_ILLEGAL (s) =>
+ sail2_state_monad$returnS
+ ((string_append "c.illegal"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) ""))))))
+ )))`;
+
+
+(*val assembly_backwards : string -> M ast*)
+
+(*val _s1677_ : string -> maybe (mword ty16)*)
+
+val _ = Define `
+ ((s1677_:string ->((16)words$word)option) s1678_0=
+ (let s1679_0 = s1678_0 in
+ if ((string_startswith s1679_0 "c.illegal")) then
+ (case ((string_drop s1679_0 ((string_length "c.illegal")))) of
+ s1680_0 =>
+ (case ((spc_matches_prefix0 s1680_0)) of
+ SOME ((() , s1681_0)) =>
+ (case ((string_drop s1680_0 s1681_0)) of
+ s1682_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1682_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s1683_0)) =>
+ let p0_ = (string_drop s1682_0 s1683_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1669_ : string -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((s1669_:string ->((32)words$word)option) s1670_0=
+ (let s1671_0 = s1670_0 in
+ if ((string_startswith s1671_0 "illegal")) then
+ (case ((string_drop s1671_0 ((string_length "illegal")))) of
+ s1672_0 =>
+ (case ((spc_matches_prefix0 s1672_0)) of
+ SOME ((() , s1673_0)) =>
+ (case ((string_drop s1672_0 s1673_0)) of
+ s1674_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1674_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s1675_0)) =>
+ let p0_ = (string_drop s1674_0 s1675_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1652_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1652_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s1653_0=
+ ((case s1653_0 of
+ s1654_0 =>
+ (case ((csr_mnemonic_matches_prefix s1654_0)) of
+ SOME ((op, s1655_0)) =>
+ (case ((string_drop s1654_0 s1655_0)) of
+ s1656_0 =>
+ (case ((spc_matches_prefix0 s1656_0)) of
+ SOME ((() , s1657_0)) =>
+ (case ((string_drop s1656_0 s1657_0)) of
+ s1658_0 =>
+ (case ((reg_name_matches_prefix s1658_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1659_0)) =>
+ (case ((string_drop s1658_0 s1659_0)) of
+ s1660_0 =>
+ (case ((sep_matches_prefix s1660_0)) of
+ SOME ((() , s1661_0)) =>
+ (case ((string_drop s1660_0 s1661_0)) of
+ s1662_0 =>
+ (case ((reg_name_matches_prefix s1662_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1663_0)) =>
+ (case ((string_drop s1662_0 s1663_0)) of
+ s1664_0 =>
+ (case ((sep_matches_prefix s1664_0)) of
+ SOME ((() , s1665_0)) =>
+ (case ((string_drop s1664_0 s1665_0)) of
+ s1666_0 =>
+ (case ((csr_name_map_matches_prefix s1666_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s1667_0)) =>
+ let p0_ = (string_drop s1666_0 s1667_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1634_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1634_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s1635_0=
+ ((case s1635_0 of
+ s1636_0 =>
+ (case ((csr_mnemonic_matches_prefix s1636_0)) of
+ SOME ((op, s1637_0)) =>
+ let s1638_0 = (string_drop s1636_0 s1637_0) in
+ if ((string_startswith s1638_0 "i")) then
+ (case ((string_drop s1638_0 ((string_length "i")))) of
+ s1639_0 =>
+ (case ((spc_matches_prefix0 s1639_0)) of
+ SOME ((() , s1640_0)) =>
+ (case ((string_drop s1639_0 s1640_0)) of
+ s1641_0 =>
+ (case ((reg_name_matches_prefix s1641_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1642_0)) =>
+ (case ((string_drop s1641_0 s1642_0)) of
+ s1643_0 =>
+ (case ((sep_matches_prefix s1643_0)) of
+ SOME ((() , s1644_0)) =>
+ (case ((string_drop s1643_0 s1644_0)) of
+ s1645_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1645_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1646_0)) =>
+ (case ((string_drop s1645_0 s1646_0)) of
+ s1647_0 =>
+ (case ((sep_matches_prefix s1647_0)) of
+ SOME ((() , s1648_0)) =>
+ (case ((string_drop s1647_0 s1648_0)) of
+ s1649_0 =>
+ (case ((csr_name_map_matches_prefix s1649_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s1650_0)) =>
+ let p0_ = (string_drop s1649_0 s1650_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1615_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1615_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1616_0=
+ (let s1617_0 = s1616_0 in
+ if ((string_startswith s1617_0 "rem")) then
+ (case ((string_drop s1617_0 ((string_length "rem")))) of
+ s1618_0 =>
+ (case ((maybe_not_u_matches_prefix s1618_0)) of
+ SOME ((s, s1619_0)) =>
+ let s1620_0 = (string_drop s1618_0 s1619_0) in
+ if ((string_startswith s1620_0 "w")) then
+ (case ((string_drop s1620_0 ((string_length "w")))) of
+ s1621_0 =>
+ (case ((spc_matches_prefix0 s1621_0)) of
+ SOME ((() , s1622_0)) =>
+ (case ((string_drop s1621_0 s1622_0)) of
+ s1623_0 =>
+ (case ((reg_name_matches_prefix s1623_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1624_0)) =>
+ (case ((string_drop s1623_0 s1624_0)) of
+ s1625_0 =>
+ (case ((sep_matches_prefix s1625_0)) of
+ SOME ((() , s1626_0)) =>
+ (case ((string_drop s1625_0 s1626_0)) of
+ s1627_0 =>
+ (case ((reg_name_matches_prefix s1627_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1628_0)) =>
+ (case ((string_drop s1627_0 s1628_0)) of
+ s1629_0 =>
+ (case ((sep_matches_prefix s1629_0)) of
+ SOME ((() , s1630_0)) =>
+ (case ((string_drop s1629_0 s1630_0)) of
+ s1631_0 =>
+ (case ((reg_name_matches_prefix s1631_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1632_0)) =>
+ let p0_ = (string_drop s1631_0 s1632_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1596_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1596_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1597_0=
+ (let s1598_0 = s1597_0 in
+ if ((string_startswith s1598_0 "div")) then
+ (case ((string_drop s1598_0 ((string_length "div")))) of
+ s1599_0 =>
+ (case ((maybe_not_u_matches_prefix s1599_0)) of
+ SOME ((s, s1600_0)) =>
+ let s1601_0 = (string_drop s1599_0 s1600_0) in
+ if ((string_startswith s1601_0 "w")) then
+ (case ((string_drop s1601_0 ((string_length "w")))) of
+ s1602_0 =>
+ (case ((spc_matches_prefix0 s1602_0)) of
+ SOME ((() , s1603_0)) =>
+ (case ((string_drop s1602_0 s1603_0)) of
+ s1604_0 =>
+ (case ((reg_name_matches_prefix s1604_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1605_0)) =>
+ (case ((string_drop s1604_0 s1605_0)) of
+ s1606_0 =>
+ (case ((sep_matches_prefix s1606_0)) of
+ SOME ((() , s1607_0)) =>
+ (case ((string_drop s1606_0 s1607_0)) of
+ s1608_0 =>
+ (case ((reg_name_matches_prefix s1608_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1609_0)) =>
+ (case ((string_drop s1608_0 s1609_0)) of
+ s1610_0 =>
+ (case ((sep_matches_prefix s1610_0)) of
+ SOME ((() , s1611_0)) =>
+ (case ((string_drop s1610_0 s1611_0)) of
+ s1612_0 =>
+ (case ((reg_name_matches_prefix s1612_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1613_0)) =>
+ let p0_ = (string_drop s1612_0 s1613_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1580_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1580_:string ->((5)words$word#(5)words$word#(5)words$word)option) s1581_0=
+ (let s1582_0 = s1581_0 in
+ if ((string_startswith s1582_0 "mulw")) then
+ (case ((string_drop s1582_0 ((string_length "mulw")))) of
+ s1583_0 =>
+ (case ((spc_matches_prefix0 s1583_0)) of
+ SOME ((() , s1584_0)) =>
+ (case ((string_drop s1583_0 s1584_0)) of
+ s1585_0 =>
+ (case ((reg_name_matches_prefix s1585_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1586_0)) =>
+ (case ((string_drop s1585_0 s1586_0)) of
+ s1587_0 =>
+ (case ((sep_matches_prefix s1587_0)) of
+ SOME ((() , s1588_0)) =>
+ (case ((string_drop s1587_0 s1588_0)) of
+ s1589_0 =>
+ (case ((reg_name_matches_prefix s1589_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1590_0)) =>
+ (case ((string_drop s1589_0 s1590_0)) of
+ s1591_0 =>
+ (case ((sep_matches_prefix s1591_0)) of
+ SOME ((() , s1592_0)) =>
+ (case ((string_drop s1591_0 s1592_0)) of
+ s1593_0 =>
+ (case ((reg_name_matches_prefix s1593_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1594_0)) =>
+ let p0_ = (string_drop s1593_0 s1594_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1562_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1562_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1563_0=
+ (let s1564_0 = s1563_0 in
+ if ((string_startswith s1564_0 "rem")) then
+ (case ((string_drop s1564_0 ((string_length "rem")))) of
+ s1565_0 =>
+ (case ((maybe_not_u_matches_prefix s1565_0)) of
+ SOME ((s, s1566_0)) =>
+ (case ((string_drop s1565_0 s1566_0)) of
+ s1567_0 =>
+ (case ((spc_matches_prefix0 s1567_0)) of
+ SOME ((() , s1568_0)) =>
+ (case ((string_drop s1567_0 s1568_0)) of
+ s1569_0 =>
+ (case ((reg_name_matches_prefix s1569_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1570_0)) =>
+ (case ((string_drop s1569_0 s1570_0)) of
+ s1571_0 =>
+ (case ((sep_matches_prefix s1571_0)) of
+ SOME ((() , s1572_0)) =>
+ (case ((string_drop s1571_0 s1572_0)) of
+ s1573_0 =>
+ (case ((reg_name_matches_prefix s1573_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1574_0)) =>
+ (case ((string_drop s1573_0 s1574_0)) of
+ s1575_0 =>
+ (case ((sep_matches_prefix s1575_0)) of
+ SOME ((() , s1576_0)) =>
+ (case ((string_drop s1575_0 s1576_0)) of
+ s1577_0 =>
+ (case ((reg_name_matches_prefix s1577_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1578_0)) =>
+ let p0_ = (string_drop s1577_0 s1578_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1544_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1544_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1545_0=
+ (let s1546_0 = s1545_0 in
+ if ((string_startswith s1546_0 "div")) then
+ (case ((string_drop s1546_0 ((string_length "div")))) of
+ s1547_0 =>
+ (case ((maybe_not_u_matches_prefix s1547_0)) of
+ SOME ((s, s1548_0)) =>
+ (case ((string_drop s1547_0 s1548_0)) of
+ s1549_0 =>
+ (case ((spc_matches_prefix0 s1549_0)) of
+ SOME ((() , s1550_0)) =>
+ (case ((string_drop s1549_0 s1550_0)) of
+ s1551_0 =>
+ (case ((reg_name_matches_prefix s1551_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1552_0)) =>
+ (case ((string_drop s1551_0 s1552_0)) of
+ s1553_0 =>
+ (case ((sep_matches_prefix s1553_0)) of
+ SOME ((() , s1554_0)) =>
+ (case ((string_drop s1553_0 s1554_0)) of
+ s1555_0 =>
+ (case ((reg_name_matches_prefix s1555_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1556_0)) =>
+ (case ((string_drop s1555_0 s1556_0)) of
+ s1557_0 =>
+ (case ((sep_matches_prefix s1557_0)) of
+ SOME ((() , s1558_0)) =>
+ (case ((string_drop s1557_0 s1558_0)) of
+ s1559_0 =>
+ (case ((reg_name_matches_prefix s1559_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1560_0)) =>
+ let p0_ = (string_drop s1559_0 s1560_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1527_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1527_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1528_0=
+ ((case s1528_0 of
+ s1529_0 =>
+ (case ((mul_mnemonic_matches_prefix s1529_0)) of
+ SOME (((high, signed1, signed2), s1530_0)) =>
+ (case ((string_drop s1529_0 s1530_0)) of
+ s1531_0 =>
+ (case ((spc_matches_prefix0 s1531_0)) of
+ SOME ((() , s1532_0)) =>
+ (case ((string_drop s1531_0 s1532_0)) of
+ s1533_0 =>
+ (case ((reg_name_matches_prefix s1533_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1534_0)) =>
+ (case ((string_drop s1533_0 s1534_0)) of
+ s1535_0 =>
+ (case ((sep_matches_prefix s1535_0)) of
+ SOME ((() , s1536_0)) =>
+ (case ((string_drop s1535_0 s1536_0)) of
+ s1537_0 =>
+ (case ((reg_name_matches_prefix s1537_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1538_0)) =>
+ (case ((string_drop s1537_0 s1538_0)) of
+ s1539_0 =>
+ (case ((sep_matches_prefix s1539_0)) of
+ SOME ((() , s1540_0)) =>
+ (case ((string_drop s1539_0 s1540_0)) of
+ s1541_0 =>
+ (case ((reg_name_matches_prefix s1541_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1542_0)) =>
+ let p0_ = (string_drop s1541_0 s1542_0) in
+ if (((p0_ = ""))) then SOME (high, signed1, signed2, rd, rs1, rs2) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1515_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1515_:string ->((5)words$word#(5)words$word)option) s1516_0=
+ (let s1517_0 = s1516_0 in
+ if ((string_startswith s1517_0 "c.add")) then
+ (case ((string_drop s1517_0 ((string_length "c.add")))) of
+ s1518_0 =>
+ (case ((spc_matches_prefix0 s1518_0)) of
+ SOME ((() , s1519_0)) =>
+ (case ((string_drop s1518_0 s1519_0)) of
+ s1520_0 =>
+ (case ((reg_name_matches_prefix s1520_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1521_0)) =>
+ (case ((string_drop s1520_0 s1521_0)) of
+ s1522_0 =>
+ (case ((sep_matches_prefix s1522_0)) of
+ SOME ((() , s1523_0)) =>
+ (case ((string_drop s1522_0 s1523_0)) of
+ s1524_0 =>
+ (case ((reg_name_matches_prefix s1524_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1525_0)) =>
+ let p0_ = (string_drop s1524_0 s1525_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1503_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1503_:string ->((5)words$word#(5)words$word)option) s1504_0=
+ (let s1505_0 = s1504_0 in
+ if ((string_startswith s1505_0 "c.mv")) then
+ (case ((string_drop s1505_0 ((string_length "c.mv")))) of
+ s1506_0 =>
+ (case ((spc_matches_prefix0 s1506_0)) of
+ SOME ((() , s1507_0)) =>
+ (case ((string_drop s1506_0 s1507_0)) of
+ s1508_0 =>
+ (case ((reg_name_matches_prefix s1508_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1509_0)) =>
+ (case ((string_drop s1508_0 s1509_0)) of
+ s1510_0 =>
+ (case ((sep_matches_prefix s1510_0)) of
+ SOME ((() , s1511_0)) =>
+ (case ((string_drop s1510_0 s1511_0)) of
+ s1512_0 =>
+ (case ((reg_name_matches_prefix s1512_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1513_0)) =>
+ let p0_ = (string_drop s1512_0 s1513_0) in
+ if (((p0_ = ""))) then SOME (rd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1495_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s1495_:string ->((5)words$word)option) s1496_0=
+ (let s1497_0 = s1496_0 in
+ if ((string_startswith s1497_0 "c.jalr")) then
+ (case ((string_drop s1497_0 ((string_length "c.jalr")))) of
+ s1498_0 =>
+ (case ((spc_matches_prefix0 s1498_0)) of
+ SOME ((() , s1499_0)) =>
+ (case ((string_drop s1498_0 s1499_0)) of
+ s1500_0 =>
+ (case ((reg_name_matches_prefix s1500_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1501_0)) =>
+ let p0_ = (string_drop s1500_0 s1501_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1487_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s1487_:string ->((5)words$word)option) s1488_0=
+ (let s1489_0 = s1488_0 in
+ if ((string_startswith s1489_0 "c.jr")) then
+ (case ((string_drop s1489_0 ((string_length "c.jr")))) of
+ s1490_0 =>
+ (case ((spc_matches_prefix0 s1490_0)) of
+ SOME ((() , s1491_0)) =>
+ (case ((string_drop s1490_0 s1491_0)) of
+ s1492_0 =>
+ (case ((reg_name_matches_prefix s1492_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1493_0)) =>
+ let p0_ = (string_drop s1492_0 s1493_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1475_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1475_:string ->((5)words$word#(6)words$word)option) s1476_0=
+ (let s1477_0 = s1476_0 in
+ if ((string_startswith s1477_0 "c.sdsp")) then
+ (case ((string_drop s1477_0 ((string_length "c.sdsp")))) of
+ s1478_0 =>
+ (case ((spc_matches_prefix0 s1478_0)) of
+ SOME ((() , s1479_0)) =>
+ (case ((string_drop s1478_0 s1479_0)) of
+ s1480_0 =>
+ (case ((reg_name_matches_prefix s1480_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1481_0)) =>
+ (case ((string_drop s1480_0 s1481_0)) of
+ s1482_0 =>
+ (case ((sep_matches_prefix s1482_0)) of
+ SOME ((() , s1483_0)) =>
+ (case ((string_drop s1482_0 s1483_0)) of
+ s1484_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1484_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1485_0)) =>
+ let p0_ = (string_drop s1484_0 s1485_0) in
+ if (((p0_ = ""))) then SOME (rs2, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1463_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1463_:string ->((5)words$word#(6)words$word)option) s1464_0=
+ (let s1465_0 = s1464_0 in
+ if ((string_startswith s1465_0 "c.swsp")) then
+ (case ((string_drop s1465_0 ((string_length "c.swsp")))) of
+ s1466_0 =>
+ (case ((spc_matches_prefix0 s1466_0)) of
+ SOME ((() , s1467_0)) =>
+ (case ((string_drop s1466_0 s1467_0)) of
+ s1468_0 =>
+ (case ((reg_name_matches_prefix s1468_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1469_0)) =>
+ (case ((string_drop s1468_0 s1469_0)) of
+ s1470_0 =>
+ (case ((sep_matches_prefix s1470_0)) of
+ SOME ((() , s1471_0)) =>
+ (case ((string_drop s1470_0 s1471_0)) of
+ s1472_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1472_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1473_0)) =>
+ let p0_ = (string_drop s1472_0 s1473_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1451_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1451_:string ->((5)words$word#(6)words$word)option) s1452_0=
+ (let s1453_0 = s1452_0 in
+ if ((string_startswith s1453_0 "c.ldsp")) then
+ (case ((string_drop s1453_0 ((string_length "c.ldsp")))) of
+ s1454_0 =>
+ (case ((spc_matches_prefix0 s1454_0)) of
+ SOME ((() , s1455_0)) =>
+ (case ((string_drop s1454_0 s1455_0)) of
+ s1456_0 =>
+ (case ((reg_name_matches_prefix s1456_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1457_0)) =>
+ (case ((string_drop s1456_0 s1457_0)) of
+ s1458_0 =>
+ (case ((sep_matches_prefix s1458_0)) of
+ SOME ((() , s1459_0)) =>
+ (case ((string_drop s1458_0 s1459_0)) of
+ s1460_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1460_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1461_0)) =>
+ let p0_ = (string_drop s1460_0 s1461_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1439_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1439_:string ->((5)words$word#(6)words$word)option) s1440_0=
+ (let s1441_0 = s1440_0 in
+ if ((string_startswith s1441_0 "c.lwsp")) then
+ (case ((string_drop s1441_0 ((string_length "c.lwsp")))) of
+ s1442_0 =>
+ (case ((spc_matches_prefix0 s1442_0)) of
+ SOME ((() , s1443_0)) =>
+ (case ((string_drop s1442_0 s1443_0)) of
+ s1444_0 =>
+ (case ((reg_name_matches_prefix s1444_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1445_0)) =>
+ (case ((string_drop s1444_0 s1445_0)) of
+ s1446_0 =>
+ (case ((sep_matches_prefix s1446_0)) of
+ SOME ((() , s1447_0)) =>
+ (case ((string_drop s1446_0 s1447_0)) of
+ s1448_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1448_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1449_0)) =>
+ let p0_ = (string_drop s1448_0 s1449_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1427_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1427_:string ->((5)words$word#(6)words$word)option) s1428_0=
+ (let s1429_0 = s1428_0 in
+ if ((string_startswith s1429_0 "c.slli")) then
+ (case ((string_drop s1429_0 ((string_length "c.slli")))) of
+ s1430_0 =>
+ (case ((spc_matches_prefix0 s1430_0)) of
+ SOME ((() , s1431_0)) =>
+ (case ((string_drop s1430_0 s1431_0)) of
+ s1432_0 =>
+ (case ((reg_name_matches_prefix s1432_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1433_0)) =>
+ (case ((string_drop s1432_0 s1433_0)) of
+ s1434_0 =>
+ (case ((sep_matches_prefix s1434_0)) of
+ SOME ((() , s1435_0)) =>
+ (case ((string_drop s1434_0 s1435_0)) of
+ s1436_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1436_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1437_0)) =>
+ let p0_ = (string_drop s1436_0 s1437_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1415_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1415_:string ->((3)words$word#(8)words$word)option) s1416_0=
+ (let s1417_0 = s1416_0 in
+ if ((string_startswith s1417_0 "c.bnez")) then
+ (case ((string_drop s1417_0 ((string_length "c.bnez")))) of
+ s1418_0 =>
+ (case ((spc_matches_prefix0 s1418_0)) of
+ SOME ((() , s1419_0)) =>
+ (case ((string_drop s1418_0 s1419_0)) of
+ s1420_0 =>
+ (case ((creg_name_matches_prefix s1420_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s1421_0)) =>
+ (case ((string_drop s1420_0 s1421_0)) of
+ s1422_0 =>
+ (case ((sep_matches_prefix s1422_0)) of
+ SOME ((() , s1423_0)) =>
+ (case ((string_drop s1422_0 s1423_0)) of
+ s1424_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1424_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s1425_0)) =>
+ let p0_ = (string_drop s1424_0 s1425_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1403_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1403_:string ->((3)words$word#(8)words$word)option) s1404_0=
+ (let s1405_0 = s1404_0 in
+ if ((string_startswith s1405_0 "c.beqz")) then
+ (case ((string_drop s1405_0 ((string_length "c.beqz")))) of
+ s1406_0 =>
+ (case ((spc_matches_prefix0 s1406_0)) of
+ SOME ((() , s1407_0)) =>
+ (case ((string_drop s1406_0 s1407_0)) of
+ s1408_0 =>
+ (case ((creg_name_matches_prefix s1408_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s1409_0)) =>
+ (case ((string_drop s1408_0 s1409_0)) of
+ s1410_0 =>
+ (case ((sep_matches_prefix s1410_0)) of
+ SOME ((() , s1411_0)) =>
+ (case ((string_drop s1410_0 s1411_0)) of
+ s1412_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1412_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s1413_0)) =>
+ let p0_ = (string_drop s1412_0 s1413_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1395_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s1395_:string ->((11)words$word)option) s1396_0=
+ (let s1397_0 = s1396_0 in
+ if ((string_startswith s1397_0 "c.j")) then
+ (case ((string_drop s1397_0 ((string_length "c.j")))) of
+ s1398_0 =>
+ (case ((spc_matches_prefix0 s1398_0)) of
+ SOME ((() , s1399_0)) =>
+ (case ((string_drop s1398_0 s1399_0)) of
+ s1400_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1400_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s1401_0)) =>
+ let p0_ = (string_drop s1400_0 s1401_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1383_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1383_:string ->((3)words$word#(3)words$word)option) s1384_0=
+ (let s1385_0 = s1384_0 in
+ if ((string_startswith s1385_0 "c.addw")) then
+ (case ((string_drop s1385_0 ((string_length "c.addw")))) of
+ s1386_0 =>
+ (case ((spc_matches_prefix0 s1386_0)) of
+ SOME ((() , s1387_0)) =>
+ (case ((string_drop s1386_0 s1387_0)) of
+ s1388_0 =>
+ (case ((creg_name_matches_prefix s1388_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1389_0)) =>
+ (case ((string_drop s1388_0 s1389_0)) of
+ s1390_0 =>
+ (case ((sep_matches_prefix s1390_0)) of
+ SOME ((() , s1391_0)) =>
+ (case ((string_drop s1390_0 s1391_0)) of
+ s1392_0 =>
+ (case ((creg_name_matches_prefix s1392_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1393_0)) =>
+ let p0_ = (string_drop s1392_0 s1393_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1371_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1371_:string ->((3)words$word#(3)words$word)option) s1372_0=
+ (let s1373_0 = s1372_0 in
+ if ((string_startswith s1373_0 "c.subw")) then
+ (case ((string_drop s1373_0 ((string_length "c.subw")))) of
+ s1374_0 =>
+ (case ((spc_matches_prefix0 s1374_0)) of
+ SOME ((() , s1375_0)) =>
+ (case ((string_drop s1374_0 s1375_0)) of
+ s1376_0 =>
+ (case ((creg_name_matches_prefix s1376_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1377_0)) =>
+ (case ((string_drop s1376_0 s1377_0)) of
+ s1378_0 =>
+ (case ((sep_matches_prefix s1378_0)) of
+ SOME ((() , s1379_0)) =>
+ (case ((string_drop s1378_0 s1379_0)) of
+ s1380_0 =>
+ (case ((creg_name_matches_prefix s1380_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1381_0)) =>
+ let p0_ = (string_drop s1380_0 s1381_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1359_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1359_:string ->((3)words$word#(3)words$word)option) s1360_0=
+ (let s1361_0 = s1360_0 in
+ if ((string_startswith s1361_0 "c.and")) then
+ (case ((string_drop s1361_0 ((string_length "c.and")))) of
+ s1362_0 =>
+ (case ((spc_matches_prefix0 s1362_0)) of
+ SOME ((() , s1363_0)) =>
+ (case ((string_drop s1362_0 s1363_0)) of
+ s1364_0 =>
+ (case ((creg_name_matches_prefix s1364_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1365_0)) =>
+ (case ((string_drop s1364_0 s1365_0)) of
+ s1366_0 =>
+ (case ((sep_matches_prefix s1366_0)) of
+ SOME ((() , s1367_0)) =>
+ (case ((string_drop s1366_0 s1367_0)) of
+ s1368_0 =>
+ (case ((creg_name_matches_prefix s1368_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1369_0)) =>
+ let p0_ = (string_drop s1368_0 s1369_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1347_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1347_:string ->((3)words$word#(3)words$word)option) s1348_0=
+ (let s1349_0 = s1348_0 in
+ if ((string_startswith s1349_0 "c.or")) then
+ (case ((string_drop s1349_0 ((string_length "c.or")))) of
+ s1350_0 =>
+ (case ((spc_matches_prefix0 s1350_0)) of
+ SOME ((() , s1351_0)) =>
+ (case ((string_drop s1350_0 s1351_0)) of
+ s1352_0 =>
+ (case ((creg_name_matches_prefix s1352_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1353_0)) =>
+ (case ((string_drop s1352_0 s1353_0)) of
+ s1354_0 =>
+ (case ((sep_matches_prefix s1354_0)) of
+ SOME ((() , s1355_0)) =>
+ (case ((string_drop s1354_0 s1355_0)) of
+ s1356_0 =>
+ (case ((creg_name_matches_prefix s1356_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1357_0)) =>
+ let p0_ = (string_drop s1356_0 s1357_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1335_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1335_:string ->((3)words$word#(3)words$word)option) s1336_0=
+ (let s1337_0 = s1336_0 in
+ if ((string_startswith s1337_0 "c.xor")) then
+ (case ((string_drop s1337_0 ((string_length "c.xor")))) of
+ s1338_0 =>
+ (case ((spc_matches_prefix0 s1338_0)) of
+ SOME ((() , s1339_0)) =>
+ (case ((string_drop s1338_0 s1339_0)) of
+ s1340_0 =>
+ (case ((creg_name_matches_prefix s1340_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1341_0)) =>
+ (case ((string_drop s1340_0 s1341_0)) of
+ s1342_0 =>
+ (case ((sep_matches_prefix s1342_0)) of
+ SOME ((() , s1343_0)) =>
+ (case ((string_drop s1342_0 s1343_0)) of
+ s1344_0 =>
+ (case ((creg_name_matches_prefix s1344_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1345_0)) =>
+ let p0_ = (string_drop s1344_0 s1345_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1323_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1323_:string ->((3)words$word#(3)words$word)option) s1324_0=
+ (let s1325_0 = s1324_0 in
+ if ((string_startswith s1325_0 "c.sub")) then
+ (case ((string_drop s1325_0 ((string_length "c.sub")))) of
+ s1326_0 =>
+ (case ((spc_matches_prefix0 s1326_0)) of
+ SOME ((() , s1327_0)) =>
+ (case ((string_drop s1326_0 s1327_0)) of
+ s1328_0 =>
+ (case ((creg_name_matches_prefix s1328_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1329_0)) =>
+ (case ((string_drop s1328_0 s1329_0)) of
+ s1330_0 =>
+ (case ((sep_matches_prefix s1330_0)) of
+ SOME ((() , s1331_0)) =>
+ (case ((string_drop s1330_0 s1331_0)) of
+ s1332_0 =>
+ (case ((creg_name_matches_prefix s1332_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1333_0)) =>
+ let p0_ = (string_drop s1332_0 s1333_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1311_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1311_:string ->((3)words$word#(6)words$word)option) s1312_0=
+ (let s1313_0 = s1312_0 in
+ if ((string_startswith s1313_0 "c.andi")) then
+ (case ((string_drop s1313_0 ((string_length "c.andi")))) of
+ s1314_0 =>
+ (case ((spc_matches_prefix0 s1314_0)) of
+ SOME ((() , s1315_0)) =>
+ (case ((string_drop s1314_0 s1315_0)) of
+ s1316_0 =>
+ (case ((creg_name_matches_prefix s1316_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1317_0)) =>
+ (case ((string_drop s1316_0 s1317_0)) of
+ s1318_0 =>
+ (case ((sep_matches_prefix s1318_0)) of
+ SOME ((() , s1319_0)) =>
+ (case ((string_drop s1318_0 s1319_0)) of
+ s1320_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1320_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1321_0)) =>
+ let p0_ = (string_drop s1320_0 s1321_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1299_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1299_:string ->((3)words$word#(6)words$word)option) s1300_0=
+ (let s1301_0 = s1300_0 in
+ if ((string_startswith s1301_0 "c.srai")) then
+ (case ((string_drop s1301_0 ((string_length "c.srai")))) of
+ s1302_0 =>
+ (case ((spc_matches_prefix0 s1302_0)) of
+ SOME ((() , s1303_0)) =>
+ (case ((string_drop s1302_0 s1303_0)) of
+ s1304_0 =>
+ (case ((creg_name_matches_prefix s1304_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1305_0)) =>
+ (case ((string_drop s1304_0 s1305_0)) of
+ s1306_0 =>
+ (case ((sep_matches_prefix s1306_0)) of
+ SOME ((() , s1307_0)) =>
+ (case ((string_drop s1306_0 s1307_0)) of
+ s1308_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1308_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1309_0)) =>
+ let p0_ = (string_drop s1308_0 s1309_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1287_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1287_:string ->((3)words$word#(6)words$word)option) s1288_0=
+ (let s1289_0 = s1288_0 in
+ if ((string_startswith s1289_0 "c.srli")) then
+ (case ((string_drop s1289_0 ((string_length "c.srli")))) of
+ s1290_0 =>
+ (case ((spc_matches_prefix0 s1290_0)) of
+ SOME ((() , s1291_0)) =>
+ (case ((string_drop s1290_0 s1291_0)) of
+ s1292_0 =>
+ (case ((creg_name_matches_prefix s1292_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1293_0)) =>
+ (case ((string_drop s1292_0 s1293_0)) of
+ s1294_0 =>
+ (case ((sep_matches_prefix s1294_0)) of
+ SOME ((() , s1295_0)) =>
+ (case ((string_drop s1294_0 s1295_0)) of
+ s1296_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1296_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1297_0)) =>
+ let p0_ = (string_drop s1296_0 s1297_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1275_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1275_:string ->((5)words$word#(6)words$word)option) s1276_0=
+ (let s1277_0 = s1276_0 in
+ if ((string_startswith s1277_0 "c.lui")) then
+ (case ((string_drop s1277_0 ((string_length "c.lui")))) of
+ s1278_0 =>
+ (case ((spc_matches_prefix0 s1278_0)) of
+ SOME ((() , s1279_0)) =>
+ (case ((string_drop s1278_0 s1279_0)) of
+ s1280_0 =>
+ (case ((reg_name_matches_prefix s1280_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1281_0)) =>
+ (case ((string_drop s1280_0 s1281_0)) of
+ s1282_0 =>
+ (case ((sep_matches_prefix s1282_0)) of
+ SOME ((() , s1283_0)) =>
+ (case ((string_drop s1282_0 s1283_0)) of
+ s1284_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1284_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1285_0)) =>
+ let p0_ = (string_drop s1284_0 s1285_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1267_ : string -> maybe (mword ty6)*)
+
+val _ = Define `
+ ((s1267_:string ->((6)words$word)option) s1268_0=
+ (let s1269_0 = s1268_0 in
+ if ((string_startswith s1269_0 "c.addi16sp")) then
+ (case ((string_drop s1269_0 ((string_length "c.addi16sp")))) of
+ s1270_0 =>
+ (case ((spc_matches_prefix0 s1270_0)) of
+ SOME ((() , s1271_0)) =>
+ (case ((string_drop s1270_0 s1271_0)) of
+ s1272_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1272_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1273_0)) =>
+ let p0_ = (string_drop s1272_0 s1273_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1255_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1255_:string ->((5)words$word#(6)words$word)option) s1256_0=
+ (let s1257_0 = s1256_0 in
+ if ((string_startswith s1257_0 "c.li")) then
+ (case ((string_drop s1257_0 ((string_length "c.li")))) of
+ s1258_0 =>
+ (case ((spc_matches_prefix0 s1258_0)) of
+ SOME ((() , s1259_0)) =>
+ (case ((string_drop s1258_0 s1259_0)) of
+ s1260_0 =>
+ (case ((reg_name_matches_prefix s1260_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1261_0)) =>
+ (case ((string_drop s1260_0 s1261_0)) of
+ s1262_0 =>
+ (case ((sep_matches_prefix s1262_0)) of
+ SOME ((() , s1263_0)) =>
+ (case ((string_drop s1262_0 s1263_0)) of
+ s1264_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1264_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1265_0)) =>
+ let p0_ = (string_drop s1264_0 s1265_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1243_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1243_:string ->((5)words$word#(6)words$word)option) s1244_0=
+ (let s1245_0 = s1244_0 in
+ if ((string_startswith s1245_0 "c.addiw")) then
+ (case ((string_drop s1245_0 ((string_length "c.addiw")))) of
+ s1246_0 =>
+ (case ((spc_matches_prefix0 s1246_0)) of
+ SOME ((() , s1247_0)) =>
+ (case ((string_drop s1246_0 s1247_0)) of
+ s1248_0 =>
+ (case ((reg_name_matches_prefix s1248_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1249_0)) =>
+ (case ((string_drop s1248_0 s1249_0)) of
+ s1250_0 =>
+ (case ((sep_matches_prefix s1250_0)) of
+ SOME ((() , s1251_0)) =>
+ (case ((string_drop s1250_0 s1251_0)) of
+ s1252_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1252_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1253_0)) =>
+ let p0_ = (string_drop s1252_0 s1253_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1235_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s1235_:string ->((11)words$word)option) s1236_0=
+ (let s1237_0 = s1236_0 in
+ if ((string_startswith s1237_0 "c.jal")) then
+ (case ((string_drop s1237_0 ((string_length "c.jal")))) of
+ s1238_0 =>
+ (case ((spc_matches_prefix0 s1238_0)) of
+ SOME ((() , s1239_0)) =>
+ (case ((string_drop s1238_0 s1239_0)) of
+ s1240_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1240_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__802, s1241_0)) =>
+ if (((((subrange_vec_dec v__802 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__802 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__802 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let p0_ = (string_drop s1240_0 s1241_0) in
+ if (((p0_ = ""))) then SOME imm else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1223_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1223_:string ->((5)words$word#(6)words$word)option) s1224_0=
+ (let s1225_0 = s1224_0 in
+ if ((string_startswith s1225_0 "c.addi")) then
+ (case ((string_drop s1225_0 ((string_length "c.addi")))) of
+ s1226_0 =>
+ (case ((spc_matches_prefix0 s1226_0)) of
+ SOME ((() , s1227_0)) =>
+ (case ((string_drop s1226_0 s1227_0)) of
+ s1228_0 =>
+ (case ((reg_name_matches_prefix s1228_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1229_0)) =>
+ (case ((string_drop s1228_0 s1229_0)) of
+ s1230_0 =>
+ (case ((sep_matches_prefix s1230_0)) of
+ SOME ((() , s1231_0)) =>
+ (case ((string_drop s1230_0 s1231_0)) of
+ s1232_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1232_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s1233_0)) =>
+ let p0_ = (string_drop s1232_0 s1233_0) in
+ if (((p0_ = ""))) then SOME (rsd, nzi) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1207_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1207_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1208_0=
+ (let s1209_0 = s1208_0 in
+ if ((string_startswith s1209_0 "c.sd")) then
+ (case ((string_drop s1209_0 ((string_length "c.sd")))) of
+ s1210_0 =>
+ (case ((spc_matches_prefix0 s1210_0)) of
+ SOME ((() , s1211_0)) =>
+ (case ((string_drop s1210_0 s1211_0)) of
+ s1212_0 =>
+ (case ((creg_name_matches_prefix s1212_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s1213_0)) =>
+ (case ((string_drop s1212_0 s1213_0)) of
+ s1214_0 =>
+ (case ((sep_matches_prefix s1214_0)) of
+ SOME ((() , s1215_0)) =>
+ (case ((string_drop s1214_0 s1215_0)) of
+ s1216_0 =>
+ (case ((creg_name_matches_prefix s1216_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s1217_0)) =>
+ (case ((string_drop s1216_0 s1217_0)) of
+ s1218_0 =>
+ (case ((sep_matches_prefix s1218_0)) of
+ SOME ((() , s1219_0)) =>
+ (case ((string_drop s1218_0 s1219_0)) of
+ s1220_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1220_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__804, s1221_0)) =>
+ if (((((subrange_vec_dec v__804 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__804 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__804 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1220_0 s1221_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1191_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1191_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1192_0=
+ (let s1193_0 = s1192_0 in
+ if ((string_startswith s1193_0 "c.sw")) then
+ (case ((string_drop s1193_0 ((string_length "c.sw")))) of
+ s1194_0 =>
+ (case ((spc_matches_prefix0 s1194_0)) of
+ SOME ((() , s1195_0)) =>
+ (case ((string_drop s1194_0 s1195_0)) of
+ s1196_0 =>
+ (case ((creg_name_matches_prefix s1196_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s1197_0)) =>
+ (case ((string_drop s1196_0 s1197_0)) of
+ s1198_0 =>
+ (case ((sep_matches_prefix s1198_0)) of
+ SOME ((() , s1199_0)) =>
+ (case ((string_drop s1198_0 s1199_0)) of
+ s1200_0 =>
+ (case ((creg_name_matches_prefix s1200_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s1201_0)) =>
+ (case ((string_drop s1200_0 s1201_0)) of
+ s1202_0 =>
+ (case ((sep_matches_prefix s1202_0)) of
+ SOME ((() , s1203_0)) =>
+ (case ((string_drop s1202_0 s1203_0)) of
+ s1204_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1204_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__806, s1205_0)) =>
+ if (((((subrange_vec_dec v__806 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__806 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__806 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1204_0 s1205_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1175_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1175_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1176_0=
+ (let s1177_0 = s1176_0 in
+ if ((string_startswith s1177_0 "c.ld")) then
+ (case ((string_drop s1177_0 ((string_length "c.ld")))) of
+ s1178_0 =>
+ (case ((spc_matches_prefix0 s1178_0)) of
+ SOME ((() , s1179_0)) =>
+ (case ((string_drop s1178_0 s1179_0)) of
+ s1180_0 =>
+ (case ((creg_name_matches_prefix s1180_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1181_0)) =>
+ (case ((string_drop s1180_0 s1181_0)) of
+ s1182_0 =>
+ (case ((sep_matches_prefix s1182_0)) of
+ SOME ((() , s1183_0)) =>
+ (case ((string_drop s1182_0 s1183_0)) of
+ s1184_0 =>
+ (case ((creg_name_matches_prefix s1184_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s1185_0)) =>
+ (case ((string_drop s1184_0 s1185_0)) of
+ s1186_0 =>
+ (case ((sep_matches_prefix s1186_0)) of
+ SOME ((() , s1187_0)) =>
+ (case ((string_drop s1186_0 s1187_0)) of
+ s1188_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1188_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__808, s1189_0)) =>
+ if (((((subrange_vec_dec v__808 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__808 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__808 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1188_0 s1189_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1159_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1159_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1160_0=
+ (let s1161_0 = s1160_0 in
+ if ((string_startswith s1161_0 "c.lw")) then
+ (case ((string_drop s1161_0 ((string_length "c.lw")))) of
+ s1162_0 =>
+ (case ((spc_matches_prefix0 s1162_0)) of
+ SOME ((() , s1163_0)) =>
+ (case ((string_drop s1162_0 s1163_0)) of
+ s1164_0 =>
+ (case ((creg_name_matches_prefix s1164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1165_0)) =>
+ (case ((string_drop s1164_0 s1165_0)) of
+ s1166_0 =>
+ (case ((sep_matches_prefix s1166_0)) of
+ SOME ((() , s1167_0)) =>
+ (case ((string_drop s1166_0 s1167_0)) of
+ s1168_0 =>
+ (case ((creg_name_matches_prefix s1168_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s1169_0)) =>
+ (case ((string_drop s1168_0 s1169_0)) of
+ s1170_0 =>
+ (case ((sep_matches_prefix s1170_0)) of
+ SOME ((() , s1171_0)) =>
+ (case ((string_drop s1170_0 s1171_0)) of
+ s1172_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1172_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__810, s1173_0)) =>
+ if (((((subrange_vec_dec v__810 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__810 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__810 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1172_0 s1173_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1147_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1147_:string ->((3)words$word#(8)words$word)option) s1148_0=
+ (let s1149_0 = s1148_0 in
+ if ((string_startswith s1149_0 "c.addi4spn")) then
+ (case ((string_drop s1149_0 ((string_length "c.addi4spn")))) of
+ s1150_0 =>
+ (case ((spc_matches_prefix0 s1150_0)) of
+ SOME ((() , s1151_0)) =>
+ (case ((string_drop s1150_0 s1151_0)) of
+ s1152_0 =>
+ (case ((creg_name_matches_prefix s1152_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1153_0)) =>
+ (case ((string_drop s1152_0 s1153_0)) of
+ s1154_0 =>
+ (case ((sep_matches_prefix s1154_0)) of
+ SOME ((() , s1155_0)) =>
+ (case ((string_drop s1154_0 s1155_0)) of
+ s1156_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1156_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__812, s1157_0)) =>
+ if (((((subrange_vec_dec v__812 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__812 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__812 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let p0_ = (string_drop s1156_0 s1157_0) in
+ if (((p0_ = ""))) then SOME (rdc, nzimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1123_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1123_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1124_0=
+ ((case s1124_0 of
+ s1125_0 =>
+ (case ((amo_mnemonic_matches_prefix s1125_0)) of
+ SOME ((op, s1126_0)) =>
+ let s1127_0 = (string_drop s1125_0 s1126_0) in
+ if ((string_startswith s1127_0 ".")) then
+ (case ((string_drop s1127_0 ((string_length ".")))) of
+ s1128_0 =>
+ (case ((size_mnemonic_matches_prefix s1128_0)) of
+ SOME ((width, s1129_0)) =>
+ (case ((string_drop s1128_0 s1129_0)) of
+ s1130_0 =>
+ (case ((maybe_aq_matches_prefix s1130_0)) of
+ SOME ((aq, s1131_0)) =>
+ (case ((string_drop s1130_0 s1131_0)) of
+ s1132_0 =>
+ (case ((maybe_rl_matches_prefix s1132_0)) of
+ SOME ((rl, s1133_0)) =>
+ (case ((string_drop s1132_0 s1133_0)) of
+ s1134_0 =>
+ (case ((spc_matches_prefix0 s1134_0)) of
+ SOME ((() , s1135_0)) =>
+ (case ((string_drop s1134_0 s1135_0)) of
+ s1136_0 =>
+ (case ((reg_name_matches_prefix s1136_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1137_0)) =>
+ (case ((string_drop s1136_0 s1137_0)) of
+ s1138_0 =>
+ (case ((sep_matches_prefix s1138_0)) of
+ SOME ((() , s1139_0)) =>
+ (case ((string_drop s1138_0 s1139_0)) of
+ s1140_0 =>
+ (case ((reg_name_matches_prefix s1140_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1141_0)) =>
+ (case ((string_drop s1140_0 s1141_0)) of
+ s1142_0 =>
+ (case ((sep_matches_prefix s1142_0)) of
+ SOME ((() , s1143_0)) =>
+ (case ((string_drop s1142_0 s1143_0)) of
+ s1144_0 =>
+ (case ((reg_name_matches_prefix s1144_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1145_0)) =>
+ let p0_ = (string_drop s1144_0 s1145_0) in
+ if (((p0_ = ""))) then SOME (op, width, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1101_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1101_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1102_0=
+ (let s1103_0 = s1102_0 in
+ if ((string_startswith s1103_0 "sc.")) then
+ (case ((string_drop s1103_0 ((string_length "sc.")))) of
+ s1104_0 =>
+ (case ((size_mnemonic_matches_prefix s1104_0)) of
+ SOME ((size1, s1105_0)) =>
+ (case ((string_drop s1104_0 s1105_0)) of
+ s1106_0 =>
+ (case ((maybe_aq_matches_prefix s1106_0)) of
+ SOME ((aq, s1107_0)) =>
+ (case ((string_drop s1106_0 s1107_0)) of
+ s1108_0 =>
+ (case ((maybe_rl_matches_prefix s1108_0)) of
+ SOME ((rl, s1109_0)) =>
+ (case ((string_drop s1108_0 s1109_0)) of
+ s1110_0 =>
+ (case ((spc_matches_prefix0 s1110_0)) of
+ SOME ((() , s1111_0)) =>
+ (case ((string_drop s1110_0 s1111_0)) of
+ s1112_0 =>
+ (case ((reg_name_matches_prefix s1112_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1113_0)) =>
+ (case ((string_drop s1112_0 s1113_0)) of
+ s1114_0 =>
+ (case ((sep_matches_prefix s1114_0)) of
+ SOME ((() , s1115_0)) =>
+ (case ((string_drop s1114_0 s1115_0)) of
+ s1116_0 =>
+ (case ((reg_name_matches_prefix s1116_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1117_0)) =>
+ (case ((string_drop s1116_0 s1117_0)) of
+ s1118_0 =>
+ (case ((sep_matches_prefix s1118_0)) of
+ SOME ((() , s1119_0)) =>
+ (case ((string_drop s1118_0 s1119_0)) of
+ s1120_0 =>
+ (case ((reg_name_matches_prefix s1120_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1121_0)) =>
+ let p0_ = (string_drop s1120_0 s1121_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1083_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1083_:string ->(word_width#bool#bool#(5)words$word#(5)words$word)option) s1084_0=
+ (let s1085_0 = s1084_0 in
+ if ((string_startswith s1085_0 "lr.")) then
+ (case ((string_drop s1085_0 ((string_length "lr.")))) of
+ s1086_0 =>
+ (case ((size_mnemonic_matches_prefix s1086_0)) of
+ SOME ((size1, s1087_0)) =>
+ (case ((string_drop s1086_0 s1087_0)) of
+ s1088_0 =>
+ (case ((maybe_aq_matches_prefix s1088_0)) of
+ SOME ((aq, s1089_0)) =>
+ (case ((string_drop s1088_0 s1089_0)) of
+ s1090_0 =>
+ (case ((maybe_rl_matches_prefix s1090_0)) of
+ SOME ((rl, s1091_0)) =>
+ (case ((string_drop s1090_0 s1091_0)) of
+ s1092_0 =>
+ (case ((spc_matches_prefix0 s1092_0)) of
+ SOME ((() , s1093_0)) =>
+ (case ((string_drop s1092_0 s1093_0)) of
+ s1094_0 =>
+ (case ((reg_name_matches_prefix s1094_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1095_0)) =>
+ (case ((string_drop s1094_0 s1095_0)) of
+ s1096_0 =>
+ (case ((sep_matches_prefix s1096_0)) of
+ SOME ((() , s1097_0)) =>
+ (case ((string_drop s1096_0 s1097_0)) of
+ s1098_0 =>
+ (case ((reg_name_matches_prefix s1098_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1099_0)) =>
+ let p0_ = (string_drop s1098_0 s1099_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1071_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1071_:string ->((5)words$word#(5)words$word)option) s1072_0=
+ (let s1073_0 = s1072_0 in
+ if ((string_startswith s1073_0 "sfence.vma")) then
+ (case ((string_drop s1073_0 ((string_length "sfence.vma")))) of
+ s1074_0 =>
+ (case ((spc_matches_prefix0 s1074_0)) of
+ SOME ((() , s1075_0)) =>
+ (case ((string_drop s1074_0 s1075_0)) of
+ s1076_0 =>
+ (case ((reg_name_matches_prefix s1076_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1077_0)) =>
+ (case ((string_drop s1076_0 s1077_0)) of
+ s1078_0 =>
+ (case ((sep_matches_prefix s1078_0)) of
+ SOME ((() , s1079_0)) =>
+ (case ((string_drop s1078_0 s1079_0)) of
+ s1080_0 =>
+ (case ((reg_name_matches_prefix s1080_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1081_0)) =>
+ let p0_ = (string_drop s1080_0 s1081_0) in
+ if (((p0_ = ""))) then SOME (rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1059_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1059_:string ->((4)words$word#(4)words$word)option) s1060_0=
+ (let s1061_0 = s1060_0 in
+ if ((string_startswith s1061_0 "fence.tso")) then
+ (case ((string_drop s1061_0 ((string_length "fence.tso")))) of
+ s1062_0 =>
+ (case ((spc_matches_prefix0 s1062_0)) of
+ SOME ((() , s1063_0)) =>
+ (case ((string_drop s1062_0 s1063_0)) of
+ s1064_0 =>
+ (case ((fence_bits_matches_prefix s1064_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1065_0)) =>
+ (case ((string_drop s1064_0 s1065_0)) of
+ s1066_0 =>
+ (case ((sep_matches_prefix s1066_0)) of
+ SOME ((() , s1067_0)) =>
+ (case ((string_drop s1066_0 s1067_0)) of
+ s1068_0 =>
+ (case ((fence_bits_matches_prefix s1068_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1069_0)) =>
+ let p0_ = (string_drop s1068_0 s1069_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1047_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1047_:string ->((4)words$word#(4)words$word)option) s1048_0=
+ (let s1049_0 = s1048_0 in
+ if ((string_startswith s1049_0 "fence")) then
+ (case ((string_drop s1049_0 ((string_length "fence")))) of
+ s1050_0 =>
+ (case ((spc_matches_prefix0 s1050_0)) of
+ SOME ((() , s1051_0)) =>
+ (case ((string_drop s1050_0 s1051_0)) of
+ s1052_0 =>
+ (case ((fence_bits_matches_prefix s1052_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1053_0)) =>
+ (case ((string_drop s1052_0 s1053_0)) of
+ s1054_0 =>
+ (case ((sep_matches_prefix s1054_0)) of
+ SOME ((() , s1055_0)) =>
+ (case ((string_drop s1054_0 s1055_0)) of
+ s1056_0 =>
+ (case ((fence_bits_matches_prefix s1056_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1057_0)) =>
+ let p0_ = (string_drop s1056_0 s1057_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1030_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1030_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word)option) s1031_0=
+ ((case s1031_0 of
+ s1032_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s1032_0)) of
+ SOME ((op, s1033_0)) =>
+ (case ((string_drop s1032_0 s1033_0)) of
+ s1034_0 =>
+ (case ((spc_matches_prefix0 s1034_0)) of
+ SOME ((() , s1035_0)) =>
+ (case ((string_drop s1034_0 s1035_0)) of
+ s1036_0 =>
+ (case ((reg_name_matches_prefix s1036_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1037_0)) =>
+ (case ((string_drop s1036_0 s1037_0)) of
+ s1038_0 =>
+ (case ((sep_matches_prefix s1038_0)) of
+ SOME ((() , s1039_0)) =>
+ (case ((string_drop s1038_0 s1039_0)) of
+ s1040_0 =>
+ (case ((reg_name_matches_prefix s1040_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1041_0)) =>
+ (case ((string_drop s1040_0 s1041_0)) of
+ s1042_0 =>
+ (case ((sep_matches_prefix s1042_0)) of
+ SOME ((() , s1043_0)) =>
+ (case ((string_drop s1042_0 s1043_0)) of
+ s1044_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1044_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1045_0)) =>
+ let p0_ = (string_drop s1044_0 s1045_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1013_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1013_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word)option) s1014_0=
+ ((case s1014_0 of
+ s1015_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s1015_0)) of
+ SOME ((op, s1016_0)) =>
+ (case ((string_drop s1015_0 s1016_0)) of
+ s1017_0 =>
+ (case ((spc_matches_prefix0 s1017_0)) of
+ SOME ((() , s1018_0)) =>
+ (case ((string_drop s1017_0 s1018_0)) of
+ s1019_0 =>
+ (case ((reg_name_matches_prefix s1019_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1020_0)) =>
+ (case ((string_drop s1019_0 s1020_0)) of
+ s1021_0 =>
+ (case ((sep_matches_prefix s1021_0)) of
+ SOME ((() , s1022_0)) =>
+ (case ((string_drop s1021_0 s1022_0)) of
+ s1023_0 =>
+ (case ((reg_name_matches_prefix s1023_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1024_0)) =>
+ (case ((string_drop s1023_0 s1024_0)) of
+ s1025_0 =>
+ (case ((sep_matches_prefix s1025_0)) of
+ SOME ((() , s1026_0)) =>
+ (case ((string_drop s1025_0 s1026_0)) of
+ s1027_0 =>
+ (case ((reg_name_matches_prefix s1027_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1028_0)) =>
+ let p0_ = (string_drop s1027_0 s1028_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s996_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s996_:string ->(sop#(5)words$word#(5)words$word#(5)words$word)option) s997_0=
+ ((case s997_0 of
+ s998_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s998_0)) of
+ SOME ((op, s999_0)) =>
+ (case ((string_drop s998_0 s999_0)) of
+ s1000_0 =>
+ (case ((spc_matches_prefix0 s1000_0)) of
+ SOME ((() , s1001_0)) =>
+ (case ((string_drop s1000_0 s1001_0)) of
+ s1002_0 =>
+ (case ((reg_name_matches_prefix s1002_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1003_0)) =>
+ (case ((string_drop s1002_0 s1003_0)) of
+ s1004_0 =>
+ (case ((sep_matches_prefix s1004_0)) of
+ SOME ((() , s1005_0)) =>
+ (case ((string_drop s1004_0 s1005_0)) of
+ s1006_0 =>
+ (case ((reg_name_matches_prefix s1006_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1007_0)) =>
+ (case ((string_drop s1006_0 s1007_0)) of
+ s1008_0 =>
+ (case ((sep_matches_prefix s1008_0)) of
+ SOME ((() , s1009_0)) =>
+ (case ((string_drop s1008_0 s1009_0)) of
+ s1010_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1010_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1011_0)) =>
+ let p0_ = (string_drop s1010_0 s1011_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s980_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s980_:string ->((5)words$word#(5)words$word#(12)words$word)option) s981_0=
+ (let s982_0 = s981_0 in
+ if ((string_startswith s982_0 "addiw")) then
+ (case ((string_drop s982_0 ((string_length "addiw")))) of
+ s983_0 =>
+ (case ((spc_matches_prefix0 s983_0)) of
+ SOME ((() , s984_0)) =>
+ (case ((string_drop s983_0 s984_0)) of
+ s985_0 =>
+ (case ((reg_name_matches_prefix s985_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s986_0)) =>
+ (case ((string_drop s985_0 s986_0)) of
+ s987_0 =>
+ (case ((sep_matches_prefix s987_0)) of
+ SOME ((() , s988_0)) =>
+ (case ((string_drop s987_0 s988_0)) of
+ s989_0 =>
+ (case ((reg_name_matches_prefix s989_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s990_0)) =>
+ (case ((string_drop s989_0 s990_0)) of
+ s991_0 =>
+ (case ((sep_matches_prefix s991_0)) of
+ SOME ((() , s992_0)) =>
+ (case ((string_drop s991_0 s992_0)) of
+ s993_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s993_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s994_0)) =>
+ let p0_ = (string_drop s993_0 s994_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s952_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s952_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s953_0=
+ (let s954_0 = s953_0 in
+ if ((string_startswith s954_0 "s")) then
+ (case ((string_drop s954_0 ((string_length "s")))) of
+ s955_0 =>
+ (case ((size_mnemonic_matches_prefix s955_0)) of
+ SOME ((size1, s956_0)) =>
+ (case ((string_drop s955_0 s956_0)) of
+ s957_0 =>
+ (case ((maybe_aq_matches_prefix s957_0)) of
+ SOME ((aq, s958_0)) =>
+ (case ((string_drop s957_0 s958_0)) of
+ s959_0 =>
+ (case ((maybe_rl_matches_prefix s959_0)) of
+ SOME ((rl, s960_0)) =>
+ (case ((string_drop s959_0 s960_0)) of
+ s961_0 =>
+ (case ((spc_matches_prefix0 s961_0)) of
+ SOME ((() , s962_0)) =>
+ (case ((string_drop s961_0 s962_0)) of
+ s963_0 =>
+ (case ((reg_name_matches_prefix s963_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s964_0)) =>
+ (case ((string_drop s963_0 s964_0)) of
+ s965_0 =>
+ (case ((sep_matches_prefix s965_0)) of
+ SOME ((() , s966_0)) =>
+ (case ((string_drop s965_0 s966_0)) of
+ s967_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s967_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s968_0)) =>
+ (case ((string_drop s967_0 s968_0)) of
+ s969_0 =>
+ (case ((opt_spc_matches_prefix0 s969_0)) of
+ SOME ((() , s970_0)) =>
+ let s971_0 = (string_drop s969_0 s970_0) in
+ if ((string_startswith s971_0 "(")) then
+ (case ((string_drop s971_0 ((string_length "(")))) of
+ s972_0 =>
+ (case ((opt_spc_matches_prefix0 s972_0)) of
+ SOME ((() , s973_0)) =>
+ (case ((string_drop s972_0 s973_0)) of
+ s974_0 =>
+ (case ((reg_name_matches_prefix s974_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s975_0)) =>
+ (case ((string_drop s974_0 s975_0)) of
+ s976_0 =>
+ (case ((opt_spc_matches_prefix0 s976_0)) of
+ SOME ((() , s977_0)) =>
+ let s978_0 = (string_drop s976_0 s977_0) in
+ if ((string_startswith s978_0 ")")) then
+ let p0_ = (string_drop s978_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rs2, imm, rs1) else NONE
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s922_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s922_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s923_0=
+ (let s924_0 = s923_0 in
+ if ((string_startswith s924_0 "l")) then
+ (case ((string_drop s924_0 ((string_length "l")))) of
+ s925_0 =>
+ (case ((size_mnemonic_matches_prefix s925_0)) of
+ SOME ((size1, s926_0)) =>
+ (case ((string_drop s925_0 s926_0)) of
+ s927_0 =>
+ (case ((maybe_u_matches_prefix s927_0)) of
+ SOME ((is_unsigned, s928_0)) =>
+ (case ((string_drop s927_0 s928_0)) of
+ s929_0 =>
+ (case ((maybe_aq_matches_prefix s929_0)) of
+ SOME ((aq, s930_0)) =>
+ (case ((string_drop s929_0 s930_0)) of
+ s931_0 =>
+ (case ((maybe_rl_matches_prefix s931_0)) of
+ SOME ((rl, s932_0)) =>
+ (case ((string_drop s931_0 s932_0)) of
+ s933_0 =>
+ (case ((spc_matches_prefix0 s933_0)) of
+ SOME ((() , s934_0)) =>
+ (case ((string_drop s933_0 s934_0)) of
+ s935_0 =>
+ (case ((reg_name_matches_prefix s935_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s936_0)) =>
+ (case ((string_drop s935_0 s936_0)) of
+ s937_0 =>
+ (case ((sep_matches_prefix s937_0)) of
+ SOME ((() , s938_0)) =>
+ (case ((string_drop s937_0 s938_0)) of
+ s939_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s939_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s940_0)) =>
+ (case ((string_drop s939_0 s940_0)) of
+ s941_0 =>
+ (case ((opt_spc_matches_prefix0 s941_0)) of
+ SOME ((() , s942_0)) =>
+ let s943_0 = (string_drop s941_0 s942_0) in
+ if ((string_startswith s943_0 "(")) then
+ (case ((string_drop s943_0 ((string_length "(")))) of
+ s944_0 =>
+ (case ((opt_spc_matches_prefix0 s944_0)) of
+ SOME ((() , s945_0)) =>
+ (case ((string_drop s944_0 s945_0)) of
+ s946_0 =>
+ (case ((reg_name_matches_prefix s946_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s947_0)) =>
+ (case ((string_drop s946_0 s947_0)) of
+ s948_0 =>
+ (case ((opt_spc_matches_prefix0 s948_0)) of
+ SOME ((() , s949_0)) =>
+ let s950_0 = (string_drop s948_0 s949_0) in
+ if ((string_startswith s950_0 ")")) then
+ let p0_ = (string_drop s950_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, is_unsigned, aq, rl, rd, imm, rs1)
+ else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s905_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s905_:string ->(rop#(5)words$word#(5)words$word#(5)words$word)option) s906_0=
+ ((case s906_0 of
+ s907_0 =>
+ (case ((rtype_mnemonic_matches_prefix s907_0)) of
+ SOME ((op, s908_0)) =>
+ (case ((string_drop s907_0 s908_0)) of
+ s909_0 =>
+ (case ((spc_matches_prefix0 s909_0)) of
+ SOME ((() , s910_0)) =>
+ (case ((string_drop s909_0 s910_0)) of
+ s911_0 =>
+ (case ((reg_name_matches_prefix s911_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s912_0)) =>
+ (case ((string_drop s911_0 s912_0)) of
+ s913_0 =>
+ (case ((sep_matches_prefix s913_0)) of
+ SOME ((() , s914_0)) =>
+ (case ((string_drop s913_0 s914_0)) of
+ s915_0 =>
+ (case ((reg_name_matches_prefix s915_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s916_0)) =>
+ (case ((string_drop s915_0 s916_0)) of
+ s917_0 =>
+ (case ((sep_matches_prefix s917_0)) of
+ SOME ((() , s918_0)) =>
+ (case ((string_drop s917_0 s918_0)) of
+ s919_0 =>
+ (case ((reg_name_matches_prefix s919_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s920_0)) =>
+ let p0_ = (string_drop s919_0 s920_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s888_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s888_:string ->(sop#(5)words$word#(5)words$word#(6)words$word)option) s889_0=
+ ((case s889_0 of
+ s890_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s890_0)) of
+ SOME ((op, s891_0)) =>
+ (case ((string_drop s890_0 s891_0)) of
+ s892_0 =>
+ (case ((spc_matches_prefix0 s892_0)) of
+ SOME ((() , s893_0)) =>
+ (case ((string_drop s892_0 s893_0)) of
+ s894_0 =>
+ (case ((reg_name_matches_prefix s894_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s895_0)) =>
+ (case ((string_drop s894_0 s895_0)) of
+ s896_0 =>
+ (case ((sep_matches_prefix s896_0)) of
+ SOME ((() , s897_0)) =>
+ (case ((string_drop s896_0 s897_0)) of
+ s898_0 =>
+ (case ((reg_name_matches_prefix s898_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s899_0)) =>
+ (case ((string_drop s898_0 s899_0)) of
+ s900_0 =>
+ (case ((sep_matches_prefix s900_0)) of
+ SOME ((() , s901_0)) =>
+ (case ((string_drop s900_0 s901_0)) of
+ s902_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s902_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s903_0)) =>
+ let p0_ = (string_drop s902_0 s903_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s871_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s871_:string ->(iop#(5)words$word#(5)words$word#(12)words$word)option) s872_0=
+ ((case s872_0 of
+ s873_0 =>
+ (case ((itype_mnemonic_matches_prefix s873_0)) of
+ SOME ((op, s874_0)) =>
+ (case ((string_drop s873_0 s874_0)) of
+ s875_0 =>
+ (case ((spc_matches_prefix0 s875_0)) of
+ SOME ((() , s876_0)) =>
+ (case ((string_drop s875_0 s876_0)) of
+ s877_0 =>
+ (case ((reg_name_matches_prefix s877_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s878_0)) =>
+ (case ((string_drop s877_0 s878_0)) of
+ s879_0 =>
+ (case ((sep_matches_prefix s879_0)) of
+ SOME ((() , s880_0)) =>
+ (case ((string_drop s879_0 s880_0)) of
+ s881_0 =>
+ (case ((reg_name_matches_prefix s881_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s882_0)) =>
+ (case ((string_drop s881_0 s882_0)) of
+ s883_0 =>
+ (case ((sep_matches_prefix s883_0)) of
+ SOME ((() , s884_0)) =>
+ (case ((string_drop s883_0 s884_0)) of
+ s885_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s885_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s886_0)) =>
+ let p0_ = (string_drop s885_0 s886_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s854_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))*)
+
+val _ = Define `
+ ((s854_:string ->(bop#(5)words$word#(5)words$word#(13)words$word)option) s855_0=
+ ((case s855_0 of
+ s856_0 =>
+ (case ((btype_mnemonic_matches_prefix s856_0)) of
+ SOME ((op, s857_0)) =>
+ (case ((string_drop s856_0 s857_0)) of
+ s858_0 =>
+ (case ((spc_matches_prefix0 s858_0)) of
+ SOME ((() , s859_0)) =>
+ (case ((string_drop s858_0 s859_0)) of
+ s860_0 =>
+ (case ((reg_name_matches_prefix s860_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s861_0)) =>
+ (case ((string_drop s860_0 s861_0)) of
+ s862_0 =>
+ (case ((sep_matches_prefix s862_0)) of
+ SOME ((() , s863_0)) =>
+ (case ((string_drop s862_0 s863_0)) of
+ s864_0 =>
+ (case ((reg_name_matches_prefix s864_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s865_0)) =>
+ (case ((string_drop s864_0 s865_0)) of
+ s866_0 =>
+ (case ((sep_matches_prefix s866_0)) of
+ SOME ((() , s867_0)) =>
+ (case ((string_drop s866_0 s867_0)) of
+ s868_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s868_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s869_0)) =>
+ let p0_ = (string_drop s868_0 s869_0) in
+ if (((p0_ = ""))) then SOME (op, rs1, rs2, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s838_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s838_:string ->((5)words$word#(5)words$word#(12)words$word)option) s839_0=
+ (let s840_0 = s839_0 in
+ if ((string_startswith s840_0 "jalr")) then
+ (case ((string_drop s840_0 ((string_length "jalr")))) of
+ s841_0 =>
+ (case ((spc_matches_prefix0 s841_0)) of
+ SOME ((() , s842_0)) =>
+ (case ((string_drop s841_0 s842_0)) of
+ s843_0 =>
+ (case ((reg_name_matches_prefix s843_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s844_0)) =>
+ (case ((string_drop s843_0 s844_0)) of
+ s845_0 =>
+ (case ((sep_matches_prefix s845_0)) of
+ SOME ((() , s846_0)) =>
+ (case ((string_drop s845_0 s846_0)) of
+ s847_0 =>
+ (case ((reg_name_matches_prefix s847_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s848_0)) =>
+ (case ((string_drop s847_0 s848_0)) of
+ s849_0 =>
+ (case ((sep_matches_prefix s849_0)) of
+ SOME ((() , s850_0)) =>
+ (case ((string_drop s849_0 s850_0)) of
+ s851_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s851_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s852_0)) =>
+ let p0_ = (string_drop s851_0 s852_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s826_ : string -> maybe ((mword ty5 * mword ty21))*)
+
+val _ = Define `
+ ((s826_:string ->((5)words$word#(21)words$word)option) s827_0=
+ (let s828_0 = s827_0 in
+ if ((string_startswith s828_0 "jal")) then
+ (case ((string_drop s828_0 ((string_length "jal")))) of
+ s829_0 =>
+ (case ((spc_matches_prefix0 s829_0)) of
+ SOME ((() , s830_0)) =>
+ (case ((string_drop s829_0 s830_0)) of
+ s831_0 =>
+ (case ((reg_name_matches_prefix s831_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s832_0)) =>
+ (case ((string_drop s831_0 s832_0)) of
+ s833_0 =>
+ (case ((sep_matches_prefix s833_0)) of
+ SOME ((() , s834_0)) =>
+ (case ((string_drop s833_0 s834_0)) of
+ s835_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s835_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s836_0)) =>
+ let p0_ = (string_drop s835_0 s836_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s813_ : string -> maybe ((uop * mword ty5 * mword ty20))*)
+
+val _ = Define `
+ ((s813_:string ->(uop#(5)words$word#(20)words$word)option) s814_0=
+ ((case s814_0 of
+ s815_0 =>
+ (case ((utype_mnemonic_matches_prefix s815_0)) of
+ SOME ((op, s816_0)) =>
+ (case ((string_drop s815_0 s816_0)) of
+ s817_0 =>
+ (case ((spc_matches_prefix0 s817_0)) of
+ SOME ((() , s818_0)) =>
+ (case ((string_drop s817_0 s818_0)) of
+ s819_0 =>
+ (case ((reg_name_matches_prefix s819_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s820_0)) =>
+ (case ((string_drop s819_0 s820_0)) of
+ s821_0 =>
+ (case ((sep_matches_prefix s821_0)) of
+ SOME ((() , s822_0)) =>
+ (case ((string_drop s821_0 s822_0)) of
+ s823_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s823_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s824_0)) =>
+ let p0_ = (string_drop s823_0 s824_0) in
+ if (((p0_ = ""))) then SOME (op, rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s825_0 = arg_ in
+ if ((case ((s813_ s825_0 : ((uop # 5 words$word # 20 words$word))option)) of
+ SOME ((op, rd, imm)) => T
+ | _ => F
+ )) then (case (s813_ s825_0 : (( uop # 5 words$word # 20 words$word)) option) of
+ (SOME ((op, rd, imm))) =>
+ sail2_state_monad$returnS (UTYPE (imm, rd, op))
+ )
+ else if ((case ((s826_ s825_0 : (( 5 words$word # 21 words$word))option)) of
+ SOME ((rd, imm)) => T
+ | _ => F
+ )) then (case (s826_ s825_0 : (( 5 words$word # 21 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (RISCV_JAL (imm, rd))
+ )
+ else if ((case ((s838_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => T
+ | _ => F
+ )) then (case (s838_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ sail2_state_monad$returnS (RISCV_JALR (imm, rs1, rd))
+ )
+ else if ((case ((s854_ s825_0 : ((bop # 5 words$word # 5 words$word # 13 words$word))option)) of
+ SOME ((op, rs1, rs2, imm)) => T
+ | _ => F
+ )) then (case
+ (s854_ s825_0 : (( bop # 5 words$word # 5 words$word # 13 words$word)) option) of
+ (SOME ((op, rs1, rs2, imm))) =>
+ sail2_state_monad$returnS (BTYPE (imm, rs2, rs1, op))
+ )
+ else if ((case ((s871_ s825_0 : ((iop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, imm)) => T
+ | _ => F
+ )) then (case
+ (s871_ s825_0 : (( iop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, imm))) =>
+ sail2_state_monad$returnS (ITYPE (imm, rs1, rd, op))
+ )
+ else if ((case ((s888_ s825_0 : ((sop # 5 words$word # 5 words$word # 6 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => T
+ | _ => F
+ )) then (case
+ (s888_ s825_0 : (( sop # 5 words$word # 5 words$word # 6 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, op))
+ )
+ else if ((case ((s905_ s825_0 : ((rop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s905_ s825_0 : (( rop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, op))
+ )
+ else if ((case ((s922_ s825_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s922_ s825_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ sail2_state_monad$returnS (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl))
+ )
+ else if ((case ((s952_ s825_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s952_ s825_0 : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1))) =>
+ sail2_state_monad$returnS (STORE (imm, rs2, rs1, size1, aq, rl))
+ )
+ else if ((case ((s980_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s980_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ sail2_state_monad$returnS (ADDIW (imm, rs1, rd))
+ )
+ else if ((case ((s996_ s825_0 : ((sop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s996_ s825_0 : (( sop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, op))
+ )
+ else if ((case ((s1013_ s825_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1013_ s825_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, op))
+ )
+ else if ((case ((s1030_ s825_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1030_ s825_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, op))
+ )
+ else if ((case ((s1047_ s825_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1047_ s825_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ sail2_state_monad$returnS (FENCE (pred, succ))
+ )
+ else if ((case ((s1059_ s825_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1059_ s825_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ sail2_state_monad$returnS (FENCE_TSO (pred, succ))
+ )
+ else if (((s825_0 = "fence.i"))) then sail2_state_monad$returnS (FENCEI () )
+ else if (((s825_0 = "ecall"))) then sail2_state_monad$returnS (ECALL () )
+ else if (((s825_0 = "mret"))) then sail2_state_monad$returnS (MRET () )
+ else if (((s825_0 = "sret"))) then sail2_state_monad$returnS (SRET () )
+ else if (((s825_0 = "ebreak"))) then sail2_state_monad$returnS (EBREAK () )
+ else if (((s825_0 = "wfi"))) then sail2_state_monad$returnS (WFI () )
+ else if ((case ((s1071_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rs1, rs2)) => T
+ | _ => F
+ )) then (case (s1071_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rs1, rs2))) =>
+ sail2_state_monad$returnS (SFENCE_VMA (rs1, rs2))
+ )
+ else if ((case ((s1083_ s825_0 : ((word_width # bool # bool # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1083_ s825_0 : (( word_width # bool # bool # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1))) =>
+ sail2_state_monad$returnS (LOADRES (aq, rl, rs1, size1, rd))
+ )
+ else if ((case ((s1101_ s825_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1101_ s825_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (STORECON (aq, rl, rs2, rs1, size1, rd))
+ )
+ else if ((case ((s1123_ s825_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1123_ s825_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (AMO (op, aq, rl, rs2, rs1, width, rd))
+ )
+ else if (((s825_0 = "c.nop"))) then sail2_state_monad$returnS (C_NOP () )
+ else if ((case ((s1147_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rdc, nzimm)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s1147_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rdc, nzimm))) =>
+ sail2_state_monad$returnS (C_ADDI4SPN (rdc, nzimm))
+ )
+ else if ((case ((s1159_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => T
+ | _ => F
+ )) then (case (s1159_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ sail2_state_monad$returnS (C_LW (uimm, rsc, rdc))
+ )
+ else if ((case ((s1175_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1175_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ sail2_state_monad$returnS (C_LD (uimm, rsc, rdc))
+ )
+ else if ((case ((s1191_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => T
+ | _ => F
+ )) then (case
+ (s1191_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ sail2_state_monad$returnS (C_SW (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1207_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1207_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ sail2_state_monad$returnS (C_SD (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1223_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, nzi)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1223_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, nzi))) =>
+ sail2_state_monad$returnS (C_ADDI (nzi, rsd))
+ )
+ else if ((case ((s1235_ s825_0 : ( 11 words$word)option)) of
+ SOME (imm) => ((( 32 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s1235_ s825_0 : ( 11 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_JAL imm)
+ )
+ else if ((case ((s1243_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1243_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ sail2_state_monad$returnS (C_ADDIW (imm, rsd))
+ )
+ else if ((case ((s1255_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1255_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (C_LI (imm, rd))
+ )
+ else if ((case ((s1267_ s825_0 : ( 6 words$word)option)) of
+ SOME (imm) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1267_ s825_0 : ( 6 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_ADDI16SP imm)
+ )
+ else if ((case ((s1275_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s1275_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (C_LUI (imm, rd))
+ )
+ else if ((case ((s1287_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1287_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SRLI (shamt, rsd))
+ )
+ else if ((case ((s1299_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1299_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SRAI (shamt, rsd))
+ )
+ else if ((case ((s1311_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => T
+ | _ => F
+ )) then (case (s1311_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ sail2_state_monad$returnS (C_ANDI (imm, rsd))
+ )
+ else if ((case ((s1323_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1323_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_SUB (rsd, rs2))
+ )
+ else if ((case ((s1335_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1335_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_XOR (rsd, rs2))
+ )
+ else if ((case ((s1347_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1347_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_OR (rsd, rs2))
+ )
+ else if ((case ((s1359_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1359_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_AND (rsd, rs2))
+ )
+ else if ((case ((s1371_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1371_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_SUBW (rsd, rs2))
+ )
+ else if ((case ((s1383_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1383_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_ADDW (rsd, rs2))
+ )
+ else if ((case ((s1395_ s825_0 : ( 11 words$word)option)) of
+ SOME (imm) => T
+ | _ => F
+ )) then (case (s1395_ s825_0 : ( 11 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_J imm)
+ )
+ else if ((case ((s1403_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s1403_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ sail2_state_monad$returnS (C_BEQZ (imm, rs))
+ )
+ else if ((case ((s1415_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s1415_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ sail2_state_monad$returnS (C_BNEZ (imm, rs))
+ )
+ else if ((case ((s1427_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1427_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SLLI (shamt, rsd))
+ )
+ else if ((case ((s1439_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1439_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_LWSP (uimm, rd))
+ )
+ else if ((case ((s1451_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s1451_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_LDSP (uimm, rd))
+ )
+ else if ((case ((s1463_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => T
+ | _ => F
+ )) then (case (s1463_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_SWSP (uimm, rd))
+ )
+ else if ((case ((s1475_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rs2, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1475_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rs2, uimm))) =>
+ sail2_state_monad$returnS (C_SDSP (uimm, rs2))
+ )
+ else if ((case ((s1487_ s825_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1487_ s825_0 : ( 5 words$word) option) of
+ (SOME (rs1)) =>
+ sail2_state_monad$returnS (C_JR rs1)
+ )
+ else if ((case ((s1495_ s825_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1495_ s825_0 : ( 5 words$word) option) of
+ (SOME (rs1)) =>
+ sail2_state_monad$returnS (C_JALR rs1)
+ )
+ else if ((case ((s1503_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1503_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs2))) =>
+ sail2_state_monad$returnS (C_MV (rd, rs2))
+ )
+ else if (((s825_0 = "c.ebreak"))) then sail2_state_monad$returnS (C_EBREAK () )
+ else if ((case ((s1515_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1515_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_ADD (rsd, rs2))
+ )
+ else if ((case ((s1527_ s825_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1527_ s825_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (MUL (rs2, rs1, rd, high, signed1, signed2))
+ )
+ else if ((case ((s1544_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1544_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (DIV0 (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1562_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1562_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (REM (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1580_ s825_0 : (( 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1580_ s825_0 : (( 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (MULW (rs2, rs1, rd))
+ )
+ else if ((case ((s1596_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1596_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (DIVW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1615_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1615_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (REMW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1634_ s825_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s1634_ s825_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, T, op))
+ )
+ else if ((case ((s1652_ s825_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s1652_ s825_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, F, op))
+ )
+ else if (((s825_0 = "uret"))) then sail2_state_monad$returnS (URET () )
+ else if ((case ((s1669_ s825_0 : ( 32 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s1669_ s825_0 : ( 32 words$word) option) of
+ (SOME (s)) =>
+ sail2_state_monad$returnS (ILLEGAL s)
+ )
+ else if ((case ((s1677_ s825_0 : ( 16 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s1677_ s825_0 : ( 16 words$word) option) of
+ (SOME (s)) =>
+ sail2_state_monad$returnS (C_ILLEGAL s)
+ )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val assembly_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((assembly_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => T
+ | RISCV_JAL ((imm, rd)) => T
+ | RISCV_JALR ((imm, rs1, rd)) => T
+ | BTYPE ((imm, rs2, rs1, op)) => T
+ | ITYPE ((imm, rs1, rd, op)) => T
+ | SHIFTIOP ((shamt, rs1, rd, op)) => T
+ | RTYPE ((rs2, rs1, rd, op)) => T
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl)) => T
+ | STORE ((imm, rs2, rs1, size1, aq, rl)) => T
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | FENCE ((pred, succ)) => T
+ | FENCE_TSO ((pred, succ)) => T
+ | FENCEI (() ) => T
+ | ECALL (() ) => T
+ | MRET (() ) => T
+ | SRET (() ) => T
+ | EBREAK (() ) => T
+ | WFI (() ) => T
+ | SFENCE_VMA ((rs1, rs2)) => T
+ | LOADRES ((aq, rl, rs1, size1, rd)) => T
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) => T
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => T
+ | C_NOP (() ) => T
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if (((nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ T else F
+ | C_LW ((uimm, rsc, rdc)) => T
+ | C_LD ((uimm, rsc, rdc)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_SW ((uimm, rsc1, rsc2)) => T
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_ADDI ((nzi, rsd)) =>
+ if ((((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_JAL (imm) =>
+ if ((((( 32 : int): ii) = (( 32 : int): ii)))) then T else F
+ | C_ADDIW ((imm, rsd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_LI ((imm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_ADDI16SP (imm) =>
+ if (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_LUI ((imm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\
+ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then
+ T else F
+ | C_SRLI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_SRAI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_ANDI ((imm, rsd)) => T
+ | C_SUB ((rsd, rs2)) => T
+ | C_XOR ((rsd, rs2)) => T
+ | C_OR ((rsd, rs2)) => T
+ | C_AND ((rsd, rs2)) => T
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_J (imm) => T
+ | C_BEQZ ((imm, rs)) => T
+ | C_BNEZ ((imm, rs)) => T
+ | C_SLLI ((shamt, rsd)) =>
+ if ((((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_LWSP ((uimm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_LDSP ((uimm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((( 32 : int): ii) = (( 64 : int): ii))))))) then T else
+ F
+ | C_SWSP ((uimm, rd)) => T
+ | C_SDSP ((uimm, rs2)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_EBREAK (() ) => T
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => T
+ | DIV0 ((rs2, rs1, rd, s)) => T
+ | REM ((rs2, rs1, rd, s)) => T
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 32 : int): ii) = (( 64 : int): ii)))) then T else F
+ | CSR ((csr, rs1, rd, T, op)) => T
+ | CSR ((csr, rs1, rd, F, op)) => T
+ | URET (() ) => T
+ | ILLEGAL (s) => T
+ | C_ILLEGAL (s) => T
+ )))`;
+
+
+(*val assembly_backwards_matches : string -> bool*)
+
+(*val _s2549_ : string -> maybe (mword ty16)*)
+
+val _ = Define `
+ ((s2549_:string ->((16)words$word)option) s2550_0=
+ (let s2551_0 = s2550_0 in
+ if ((string_startswith s2551_0 "c.illegal")) then
+ (case ((string_drop s2551_0 ((string_length "c.illegal")))) of
+ s2552_0 =>
+ (case ((spc_matches_prefix0 s2552_0)) of
+ SOME ((() , s2553_0)) =>
+ (case ((string_drop s2552_0 s2553_0)) of
+ s2554_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2554_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s2555_0)) =>
+ let p0_ = (string_drop s2554_0 s2555_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2541_ : string -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((s2541_:string ->((32)words$word)option) s2542_0=
+ (let s2543_0 = s2542_0 in
+ if ((string_startswith s2543_0 "illegal")) then
+ (case ((string_drop s2543_0 ((string_length "illegal")))) of
+ s2544_0 =>
+ (case ((spc_matches_prefix0 s2544_0)) of
+ SOME ((() , s2545_0)) =>
+ (case ((string_drop s2544_0 s2545_0)) of
+ s2546_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2546_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s2547_0)) =>
+ let p0_ = (string_drop s2546_0 s2547_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2524_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s2524_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s2525_0=
+ ((case s2525_0 of
+ s2526_0 =>
+ (case ((csr_mnemonic_matches_prefix s2526_0)) of
+ SOME ((op, s2527_0)) =>
+ (case ((string_drop s2526_0 s2527_0)) of
+ s2528_0 =>
+ (case ((spc_matches_prefix0 s2528_0)) of
+ SOME ((() , s2529_0)) =>
+ (case ((string_drop s2528_0 s2529_0)) of
+ s2530_0 =>
+ (case ((reg_name_matches_prefix s2530_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2531_0)) =>
+ (case ((string_drop s2530_0 s2531_0)) of
+ s2532_0 =>
+ (case ((sep_matches_prefix s2532_0)) of
+ SOME ((() , s2533_0)) =>
+ (case ((string_drop s2532_0 s2533_0)) of
+ s2534_0 =>
+ (case ((reg_name_matches_prefix s2534_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2535_0)) =>
+ (case ((string_drop s2534_0 s2535_0)) of
+ s2536_0 =>
+ (case ((sep_matches_prefix s2536_0)) of
+ SOME ((() , s2537_0)) =>
+ (case ((string_drop s2536_0 s2537_0)) of
+ s2538_0 =>
+ (case ((csr_name_map_matches_prefix s2538_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s2539_0)) =>
+ let p0_ = (string_drop s2538_0 s2539_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2506_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s2506_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s2507_0=
+ ((case s2507_0 of
+ s2508_0 =>
+ (case ((csr_mnemonic_matches_prefix s2508_0)) of
+ SOME ((op, s2509_0)) =>
+ let s2510_0 = (string_drop s2508_0 s2509_0) in
+ if ((string_startswith s2510_0 "i")) then
+ (case ((string_drop s2510_0 ((string_length "i")))) of
+ s2511_0 =>
+ (case ((spc_matches_prefix0 s2511_0)) of
+ SOME ((() , s2512_0)) =>
+ (case ((string_drop s2511_0 s2512_0)) of
+ s2513_0 =>
+ (case ((reg_name_matches_prefix s2513_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2514_0)) =>
+ (case ((string_drop s2513_0 s2514_0)) of
+ s2515_0 =>
+ (case ((sep_matches_prefix s2515_0)) of
+ SOME ((() , s2516_0)) =>
+ (case ((string_drop s2515_0 s2516_0)) of
+ s2517_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2517_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2518_0)) =>
+ (case ((string_drop s2517_0 s2518_0)) of
+ s2519_0 =>
+ (case ((sep_matches_prefix s2519_0)) of
+ SOME ((() , s2520_0)) =>
+ (case ((string_drop s2519_0 s2520_0)) of
+ s2521_0 =>
+ (case ((csr_name_map_matches_prefix s2521_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s2522_0)) =>
+ let p0_ = (string_drop s2521_0 s2522_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2487_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2487_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2488_0=
+ (let s2489_0 = s2488_0 in
+ if ((string_startswith s2489_0 "rem")) then
+ (case ((string_drop s2489_0 ((string_length "rem")))) of
+ s2490_0 =>
+ (case ((maybe_not_u_matches_prefix s2490_0)) of
+ SOME ((s, s2491_0)) =>
+ let s2492_0 = (string_drop s2490_0 s2491_0) in
+ if ((string_startswith s2492_0 "w")) then
+ (case ((string_drop s2492_0 ((string_length "w")))) of
+ s2493_0 =>
+ (case ((spc_matches_prefix0 s2493_0)) of
+ SOME ((() , s2494_0)) =>
+ (case ((string_drop s2493_0 s2494_0)) of
+ s2495_0 =>
+ (case ((reg_name_matches_prefix s2495_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2496_0)) =>
+ (case ((string_drop s2495_0 s2496_0)) of
+ s2497_0 =>
+ (case ((sep_matches_prefix s2497_0)) of
+ SOME ((() , s2498_0)) =>
+ (case ((string_drop s2497_0 s2498_0)) of
+ s2499_0 =>
+ (case ((reg_name_matches_prefix s2499_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2500_0)) =>
+ (case ((string_drop s2499_0 s2500_0)) of
+ s2501_0 =>
+ (case ((sep_matches_prefix s2501_0)) of
+ SOME ((() , s2502_0)) =>
+ (case ((string_drop s2501_0 s2502_0)) of
+ s2503_0 =>
+ (case ((reg_name_matches_prefix s2503_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2504_0)) =>
+ let p0_ = (string_drop s2503_0 s2504_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2468_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2468_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2469_0=
+ (let s2470_0 = s2469_0 in
+ if ((string_startswith s2470_0 "div")) then
+ (case ((string_drop s2470_0 ((string_length "div")))) of
+ s2471_0 =>
+ (case ((maybe_not_u_matches_prefix s2471_0)) of
+ SOME ((s, s2472_0)) =>
+ let s2473_0 = (string_drop s2471_0 s2472_0) in
+ if ((string_startswith s2473_0 "w")) then
+ (case ((string_drop s2473_0 ((string_length "w")))) of
+ s2474_0 =>
+ (case ((spc_matches_prefix0 s2474_0)) of
+ SOME ((() , s2475_0)) =>
+ (case ((string_drop s2474_0 s2475_0)) of
+ s2476_0 =>
+ (case ((reg_name_matches_prefix s2476_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2477_0)) =>
+ (case ((string_drop s2476_0 s2477_0)) of
+ s2478_0 =>
+ (case ((sep_matches_prefix s2478_0)) of
+ SOME ((() , s2479_0)) =>
+ (case ((string_drop s2478_0 s2479_0)) of
+ s2480_0 =>
+ (case ((reg_name_matches_prefix s2480_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2481_0)) =>
+ (case ((string_drop s2480_0 s2481_0)) of
+ s2482_0 =>
+ (case ((sep_matches_prefix s2482_0)) of
+ SOME ((() , s2483_0)) =>
+ (case ((string_drop s2482_0 s2483_0)) of
+ s2484_0 =>
+ (case ((reg_name_matches_prefix s2484_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2485_0)) =>
+ let p0_ = (string_drop s2484_0 s2485_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2452_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2452_:string ->((5)words$word#(5)words$word#(5)words$word)option) s2453_0=
+ (let s2454_0 = s2453_0 in
+ if ((string_startswith s2454_0 "mulw")) then
+ (case ((string_drop s2454_0 ((string_length "mulw")))) of
+ s2455_0 =>
+ (case ((spc_matches_prefix0 s2455_0)) of
+ SOME ((() , s2456_0)) =>
+ (case ((string_drop s2455_0 s2456_0)) of
+ s2457_0 =>
+ (case ((reg_name_matches_prefix s2457_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2458_0)) =>
+ (case ((string_drop s2457_0 s2458_0)) of
+ s2459_0 =>
+ (case ((sep_matches_prefix s2459_0)) of
+ SOME ((() , s2460_0)) =>
+ (case ((string_drop s2459_0 s2460_0)) of
+ s2461_0 =>
+ (case ((reg_name_matches_prefix s2461_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2462_0)) =>
+ (case ((string_drop s2461_0 s2462_0)) of
+ s2463_0 =>
+ (case ((sep_matches_prefix s2463_0)) of
+ SOME ((() , s2464_0)) =>
+ (case ((string_drop s2463_0 s2464_0)) of
+ s2465_0 =>
+ (case ((reg_name_matches_prefix s2465_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2466_0)) =>
+ let p0_ = (string_drop s2465_0 s2466_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2434_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2434_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2435_0=
+ (let s2436_0 = s2435_0 in
+ if ((string_startswith s2436_0 "rem")) then
+ (case ((string_drop s2436_0 ((string_length "rem")))) of
+ s2437_0 =>
+ (case ((maybe_not_u_matches_prefix s2437_0)) of
+ SOME ((s, s2438_0)) =>
+ (case ((string_drop s2437_0 s2438_0)) of
+ s2439_0 =>
+ (case ((spc_matches_prefix0 s2439_0)) of
+ SOME ((() , s2440_0)) =>
+ (case ((string_drop s2439_0 s2440_0)) of
+ s2441_0 =>
+ (case ((reg_name_matches_prefix s2441_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2442_0)) =>
+ (case ((string_drop s2441_0 s2442_0)) of
+ s2443_0 =>
+ (case ((sep_matches_prefix s2443_0)) of
+ SOME ((() , s2444_0)) =>
+ (case ((string_drop s2443_0 s2444_0)) of
+ s2445_0 =>
+ (case ((reg_name_matches_prefix s2445_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2446_0)) =>
+ (case ((string_drop s2445_0 s2446_0)) of
+ s2447_0 =>
+ (case ((sep_matches_prefix s2447_0)) of
+ SOME ((() , s2448_0)) =>
+ (case ((string_drop s2447_0 s2448_0)) of
+ s2449_0 =>
+ (case ((reg_name_matches_prefix s2449_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2450_0)) =>
+ let p0_ = (string_drop s2449_0 s2450_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2416_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2416_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2417_0=
+ (let s2418_0 = s2417_0 in
+ if ((string_startswith s2418_0 "div")) then
+ (case ((string_drop s2418_0 ((string_length "div")))) of
+ s2419_0 =>
+ (case ((maybe_not_u_matches_prefix s2419_0)) of
+ SOME ((s, s2420_0)) =>
+ (case ((string_drop s2419_0 s2420_0)) of
+ s2421_0 =>
+ (case ((spc_matches_prefix0 s2421_0)) of
+ SOME ((() , s2422_0)) =>
+ (case ((string_drop s2421_0 s2422_0)) of
+ s2423_0 =>
+ (case ((reg_name_matches_prefix s2423_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2424_0)) =>
+ (case ((string_drop s2423_0 s2424_0)) of
+ s2425_0 =>
+ (case ((sep_matches_prefix s2425_0)) of
+ SOME ((() , s2426_0)) =>
+ (case ((string_drop s2425_0 s2426_0)) of
+ s2427_0 =>
+ (case ((reg_name_matches_prefix s2427_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2428_0)) =>
+ (case ((string_drop s2427_0 s2428_0)) of
+ s2429_0 =>
+ (case ((sep_matches_prefix s2429_0)) of
+ SOME ((() , s2430_0)) =>
+ (case ((string_drop s2429_0 s2430_0)) of
+ s2431_0 =>
+ (case ((reg_name_matches_prefix s2431_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2432_0)) =>
+ let p0_ = (string_drop s2431_0 s2432_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2399_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2399_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s2400_0=
+ ((case s2400_0 of
+ s2401_0 =>
+ (case ((mul_mnemonic_matches_prefix s2401_0)) of
+ SOME (((high, signed1, signed2), s2402_0)) =>
+ (case ((string_drop s2401_0 s2402_0)) of
+ s2403_0 =>
+ (case ((spc_matches_prefix0 s2403_0)) of
+ SOME ((() , s2404_0)) =>
+ (case ((string_drop s2403_0 s2404_0)) of
+ s2405_0 =>
+ (case ((reg_name_matches_prefix s2405_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2406_0)) =>
+ (case ((string_drop s2405_0 s2406_0)) of
+ s2407_0 =>
+ (case ((sep_matches_prefix s2407_0)) of
+ SOME ((() , s2408_0)) =>
+ (case ((string_drop s2407_0 s2408_0)) of
+ s2409_0 =>
+ (case ((reg_name_matches_prefix s2409_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2410_0)) =>
+ (case ((string_drop s2409_0 s2410_0)) of
+ s2411_0 =>
+ (case ((sep_matches_prefix s2411_0)) of
+ SOME ((() , s2412_0)) =>
+ (case ((string_drop s2411_0 s2412_0)) of
+ s2413_0 =>
+ (case ((reg_name_matches_prefix s2413_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2414_0)) =>
+ let p0_ = (string_drop s2413_0 s2414_0) in
+ if (((p0_ = ""))) then SOME (high, signed1, signed2, rd, rs1, rs2) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2387_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2387_:string ->((5)words$word#(5)words$word)option) s2388_0=
+ (let s2389_0 = s2388_0 in
+ if ((string_startswith s2389_0 "c.add")) then
+ (case ((string_drop s2389_0 ((string_length "c.add")))) of
+ s2390_0 =>
+ (case ((spc_matches_prefix0 s2390_0)) of
+ SOME ((() , s2391_0)) =>
+ (case ((string_drop s2390_0 s2391_0)) of
+ s2392_0 =>
+ (case ((reg_name_matches_prefix s2392_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2393_0)) =>
+ (case ((string_drop s2392_0 s2393_0)) of
+ s2394_0 =>
+ (case ((sep_matches_prefix s2394_0)) of
+ SOME ((() , s2395_0)) =>
+ (case ((string_drop s2394_0 s2395_0)) of
+ s2396_0 =>
+ (case ((reg_name_matches_prefix s2396_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2397_0)) =>
+ let p0_ = (string_drop s2396_0 s2397_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2375_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2375_:string ->((5)words$word#(5)words$word)option) s2376_0=
+ (let s2377_0 = s2376_0 in
+ if ((string_startswith s2377_0 "c.mv")) then
+ (case ((string_drop s2377_0 ((string_length "c.mv")))) of
+ s2378_0 =>
+ (case ((spc_matches_prefix0 s2378_0)) of
+ SOME ((() , s2379_0)) =>
+ (case ((string_drop s2378_0 s2379_0)) of
+ s2380_0 =>
+ (case ((reg_name_matches_prefix s2380_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2381_0)) =>
+ (case ((string_drop s2380_0 s2381_0)) of
+ s2382_0 =>
+ (case ((sep_matches_prefix s2382_0)) of
+ SOME ((() , s2383_0)) =>
+ (case ((string_drop s2382_0 s2383_0)) of
+ s2384_0 =>
+ (case ((reg_name_matches_prefix s2384_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2385_0)) =>
+ let p0_ = (string_drop s2384_0 s2385_0) in
+ if (((p0_ = ""))) then SOME (rd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2367_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s2367_:string ->((5)words$word)option) s2368_0=
+ (let s2369_0 = s2368_0 in
+ if ((string_startswith s2369_0 "c.jalr")) then
+ (case ((string_drop s2369_0 ((string_length "c.jalr")))) of
+ s2370_0 =>
+ (case ((spc_matches_prefix0 s2370_0)) of
+ SOME ((() , s2371_0)) =>
+ (case ((string_drop s2370_0 s2371_0)) of
+ s2372_0 =>
+ (case ((reg_name_matches_prefix s2372_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2373_0)) =>
+ let p0_ = (string_drop s2372_0 s2373_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2359_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s2359_:string ->((5)words$word)option) s2360_0=
+ (let s2361_0 = s2360_0 in
+ if ((string_startswith s2361_0 "c.jr")) then
+ (case ((string_drop s2361_0 ((string_length "c.jr")))) of
+ s2362_0 =>
+ (case ((spc_matches_prefix0 s2362_0)) of
+ SOME ((() , s2363_0)) =>
+ (case ((string_drop s2362_0 s2363_0)) of
+ s2364_0 =>
+ (case ((reg_name_matches_prefix s2364_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2365_0)) =>
+ let p0_ = (string_drop s2364_0 s2365_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2347_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2347_:string ->((5)words$word#(6)words$word)option) s2348_0=
+ (let s2349_0 = s2348_0 in
+ if ((string_startswith s2349_0 "c.sdsp")) then
+ (case ((string_drop s2349_0 ((string_length "c.sdsp")))) of
+ s2350_0 =>
+ (case ((spc_matches_prefix0 s2350_0)) of
+ SOME ((() , s2351_0)) =>
+ (case ((string_drop s2350_0 s2351_0)) of
+ s2352_0 =>
+ (case ((reg_name_matches_prefix s2352_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2353_0)) =>
+ (case ((string_drop s2352_0 s2353_0)) of
+ s2354_0 =>
+ (case ((sep_matches_prefix s2354_0)) of
+ SOME ((() , s2355_0)) =>
+ (case ((string_drop s2354_0 s2355_0)) of
+ s2356_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2356_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2357_0)) =>
+ let p0_ = (string_drop s2356_0 s2357_0) in
+ if (((p0_ = ""))) then SOME (rs2, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2335_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2335_:string ->((5)words$word#(6)words$word)option) s2336_0=
+ (let s2337_0 = s2336_0 in
+ if ((string_startswith s2337_0 "c.swsp")) then
+ (case ((string_drop s2337_0 ((string_length "c.swsp")))) of
+ s2338_0 =>
+ (case ((spc_matches_prefix0 s2338_0)) of
+ SOME ((() , s2339_0)) =>
+ (case ((string_drop s2338_0 s2339_0)) of
+ s2340_0 =>
+ (case ((reg_name_matches_prefix s2340_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2341_0)) =>
+ (case ((string_drop s2340_0 s2341_0)) of
+ s2342_0 =>
+ (case ((sep_matches_prefix s2342_0)) of
+ SOME ((() , s2343_0)) =>
+ (case ((string_drop s2342_0 s2343_0)) of
+ s2344_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2344_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2345_0)) =>
+ let p0_ = (string_drop s2344_0 s2345_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2323_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2323_:string ->((5)words$word#(6)words$word)option) s2324_0=
+ (let s2325_0 = s2324_0 in
+ if ((string_startswith s2325_0 "c.ldsp")) then
+ (case ((string_drop s2325_0 ((string_length "c.ldsp")))) of
+ s2326_0 =>
+ (case ((spc_matches_prefix0 s2326_0)) of
+ SOME ((() , s2327_0)) =>
+ (case ((string_drop s2326_0 s2327_0)) of
+ s2328_0 =>
+ (case ((reg_name_matches_prefix s2328_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2329_0)) =>
+ (case ((string_drop s2328_0 s2329_0)) of
+ s2330_0 =>
+ (case ((sep_matches_prefix s2330_0)) of
+ SOME ((() , s2331_0)) =>
+ (case ((string_drop s2330_0 s2331_0)) of
+ s2332_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2332_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2333_0)) =>
+ let p0_ = (string_drop s2332_0 s2333_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2311_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2311_:string ->((5)words$word#(6)words$word)option) s2312_0=
+ (let s2313_0 = s2312_0 in
+ if ((string_startswith s2313_0 "c.lwsp")) then
+ (case ((string_drop s2313_0 ((string_length "c.lwsp")))) of
+ s2314_0 =>
+ (case ((spc_matches_prefix0 s2314_0)) of
+ SOME ((() , s2315_0)) =>
+ (case ((string_drop s2314_0 s2315_0)) of
+ s2316_0 =>
+ (case ((reg_name_matches_prefix s2316_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2317_0)) =>
+ (case ((string_drop s2316_0 s2317_0)) of
+ s2318_0 =>
+ (case ((sep_matches_prefix s2318_0)) of
+ SOME ((() , s2319_0)) =>
+ (case ((string_drop s2318_0 s2319_0)) of
+ s2320_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2320_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2321_0)) =>
+ let p0_ = (string_drop s2320_0 s2321_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2299_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2299_:string ->((5)words$word#(6)words$word)option) s2300_0=
+ (let s2301_0 = s2300_0 in
+ if ((string_startswith s2301_0 "c.slli")) then
+ (case ((string_drop s2301_0 ((string_length "c.slli")))) of
+ s2302_0 =>
+ (case ((spc_matches_prefix0 s2302_0)) of
+ SOME ((() , s2303_0)) =>
+ (case ((string_drop s2302_0 s2303_0)) of
+ s2304_0 =>
+ (case ((reg_name_matches_prefix s2304_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2305_0)) =>
+ (case ((string_drop s2304_0 s2305_0)) of
+ s2306_0 =>
+ (case ((sep_matches_prefix s2306_0)) of
+ SOME ((() , s2307_0)) =>
+ (case ((string_drop s2306_0 s2307_0)) of
+ s2308_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2308_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2309_0)) =>
+ let p0_ = (string_drop s2308_0 s2309_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2287_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2287_:string ->((3)words$word#(8)words$word)option) s2288_0=
+ (let s2289_0 = s2288_0 in
+ if ((string_startswith s2289_0 "c.bnez")) then
+ (case ((string_drop s2289_0 ((string_length "c.bnez")))) of
+ s2290_0 =>
+ (case ((spc_matches_prefix0 s2290_0)) of
+ SOME ((() , s2291_0)) =>
+ (case ((string_drop s2290_0 s2291_0)) of
+ s2292_0 =>
+ (case ((creg_name_matches_prefix s2292_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s2293_0)) =>
+ (case ((string_drop s2292_0 s2293_0)) of
+ s2294_0 =>
+ (case ((sep_matches_prefix s2294_0)) of
+ SOME ((() , s2295_0)) =>
+ (case ((string_drop s2294_0 s2295_0)) of
+ s2296_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2296_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s2297_0)) =>
+ let p0_ = (string_drop s2296_0 s2297_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2275_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2275_:string ->((3)words$word#(8)words$word)option) s2276_0=
+ (let s2277_0 = s2276_0 in
+ if ((string_startswith s2277_0 "c.beqz")) then
+ (case ((string_drop s2277_0 ((string_length "c.beqz")))) of
+ s2278_0 =>
+ (case ((spc_matches_prefix0 s2278_0)) of
+ SOME ((() , s2279_0)) =>
+ (case ((string_drop s2278_0 s2279_0)) of
+ s2280_0 =>
+ (case ((creg_name_matches_prefix s2280_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s2281_0)) =>
+ (case ((string_drop s2280_0 s2281_0)) of
+ s2282_0 =>
+ (case ((sep_matches_prefix s2282_0)) of
+ SOME ((() , s2283_0)) =>
+ (case ((string_drop s2282_0 s2283_0)) of
+ s2284_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2284_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s2285_0)) =>
+ let p0_ = (string_drop s2284_0 s2285_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2267_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s2267_:string ->((11)words$word)option) s2268_0=
+ (let s2269_0 = s2268_0 in
+ if ((string_startswith s2269_0 "c.j")) then
+ (case ((string_drop s2269_0 ((string_length "c.j")))) of
+ s2270_0 =>
+ (case ((spc_matches_prefix0 s2270_0)) of
+ SOME ((() , s2271_0)) =>
+ (case ((string_drop s2270_0 s2271_0)) of
+ s2272_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2272_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s2273_0)) =>
+ let p0_ = (string_drop s2272_0 s2273_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2255_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2255_:string ->((3)words$word#(3)words$word)option) s2256_0=
+ (let s2257_0 = s2256_0 in
+ if ((string_startswith s2257_0 "c.addw")) then
+ (case ((string_drop s2257_0 ((string_length "c.addw")))) of
+ s2258_0 =>
+ (case ((spc_matches_prefix0 s2258_0)) of
+ SOME ((() , s2259_0)) =>
+ (case ((string_drop s2258_0 s2259_0)) of
+ s2260_0 =>
+ (case ((creg_name_matches_prefix s2260_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2261_0)) =>
+ (case ((string_drop s2260_0 s2261_0)) of
+ s2262_0 =>
+ (case ((sep_matches_prefix s2262_0)) of
+ SOME ((() , s2263_0)) =>
+ (case ((string_drop s2262_0 s2263_0)) of
+ s2264_0 =>
+ (case ((creg_name_matches_prefix s2264_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2265_0)) =>
+ let p0_ = (string_drop s2264_0 s2265_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2243_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2243_:string ->((3)words$word#(3)words$word)option) s2244_0=
+ (let s2245_0 = s2244_0 in
+ if ((string_startswith s2245_0 "c.subw")) then
+ (case ((string_drop s2245_0 ((string_length "c.subw")))) of
+ s2246_0 =>
+ (case ((spc_matches_prefix0 s2246_0)) of
+ SOME ((() , s2247_0)) =>
+ (case ((string_drop s2246_0 s2247_0)) of
+ s2248_0 =>
+ (case ((creg_name_matches_prefix s2248_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2249_0)) =>
+ (case ((string_drop s2248_0 s2249_0)) of
+ s2250_0 =>
+ (case ((sep_matches_prefix s2250_0)) of
+ SOME ((() , s2251_0)) =>
+ (case ((string_drop s2250_0 s2251_0)) of
+ s2252_0 =>
+ (case ((creg_name_matches_prefix s2252_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2253_0)) =>
+ let p0_ = (string_drop s2252_0 s2253_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2231_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2231_:string ->((3)words$word#(3)words$word)option) s2232_0=
+ (let s2233_0 = s2232_0 in
+ if ((string_startswith s2233_0 "c.and")) then
+ (case ((string_drop s2233_0 ((string_length "c.and")))) of
+ s2234_0 =>
+ (case ((spc_matches_prefix0 s2234_0)) of
+ SOME ((() , s2235_0)) =>
+ (case ((string_drop s2234_0 s2235_0)) of
+ s2236_0 =>
+ (case ((creg_name_matches_prefix s2236_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2237_0)) =>
+ (case ((string_drop s2236_0 s2237_0)) of
+ s2238_0 =>
+ (case ((sep_matches_prefix s2238_0)) of
+ SOME ((() , s2239_0)) =>
+ (case ((string_drop s2238_0 s2239_0)) of
+ s2240_0 =>
+ (case ((creg_name_matches_prefix s2240_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2241_0)) =>
+ let p0_ = (string_drop s2240_0 s2241_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2219_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2219_:string ->((3)words$word#(3)words$word)option) s2220_0=
+ (let s2221_0 = s2220_0 in
+ if ((string_startswith s2221_0 "c.or")) then
+ (case ((string_drop s2221_0 ((string_length "c.or")))) of
+ s2222_0 =>
+ (case ((spc_matches_prefix0 s2222_0)) of
+ SOME ((() , s2223_0)) =>
+ (case ((string_drop s2222_0 s2223_0)) of
+ s2224_0 =>
+ (case ((creg_name_matches_prefix s2224_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2225_0)) =>
+ (case ((string_drop s2224_0 s2225_0)) of
+ s2226_0 =>
+ (case ((sep_matches_prefix s2226_0)) of
+ SOME ((() , s2227_0)) =>
+ (case ((string_drop s2226_0 s2227_0)) of
+ s2228_0 =>
+ (case ((creg_name_matches_prefix s2228_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2229_0)) =>
+ let p0_ = (string_drop s2228_0 s2229_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2207_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2207_:string ->((3)words$word#(3)words$word)option) s2208_0=
+ (let s2209_0 = s2208_0 in
+ if ((string_startswith s2209_0 "c.xor")) then
+ (case ((string_drop s2209_0 ((string_length "c.xor")))) of
+ s2210_0 =>
+ (case ((spc_matches_prefix0 s2210_0)) of
+ SOME ((() , s2211_0)) =>
+ (case ((string_drop s2210_0 s2211_0)) of
+ s2212_0 =>
+ (case ((creg_name_matches_prefix s2212_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2213_0)) =>
+ (case ((string_drop s2212_0 s2213_0)) of
+ s2214_0 =>
+ (case ((sep_matches_prefix s2214_0)) of
+ SOME ((() , s2215_0)) =>
+ (case ((string_drop s2214_0 s2215_0)) of
+ s2216_0 =>
+ (case ((creg_name_matches_prefix s2216_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2217_0)) =>
+ let p0_ = (string_drop s2216_0 s2217_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2195_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2195_:string ->((3)words$word#(3)words$word)option) s2196_0=
+ (let s2197_0 = s2196_0 in
+ if ((string_startswith s2197_0 "c.sub")) then
+ (case ((string_drop s2197_0 ((string_length "c.sub")))) of
+ s2198_0 =>
+ (case ((spc_matches_prefix0 s2198_0)) of
+ SOME ((() , s2199_0)) =>
+ (case ((string_drop s2198_0 s2199_0)) of
+ s2200_0 =>
+ (case ((creg_name_matches_prefix s2200_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2201_0)) =>
+ (case ((string_drop s2200_0 s2201_0)) of
+ s2202_0 =>
+ (case ((sep_matches_prefix s2202_0)) of
+ SOME ((() , s2203_0)) =>
+ (case ((string_drop s2202_0 s2203_0)) of
+ s2204_0 =>
+ (case ((creg_name_matches_prefix s2204_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2205_0)) =>
+ let p0_ = (string_drop s2204_0 s2205_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2183_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2183_:string ->((3)words$word#(6)words$word)option) s2184_0=
+ (let s2185_0 = s2184_0 in
+ if ((string_startswith s2185_0 "c.andi")) then
+ (case ((string_drop s2185_0 ((string_length "c.andi")))) of
+ s2186_0 =>
+ (case ((spc_matches_prefix0 s2186_0)) of
+ SOME ((() , s2187_0)) =>
+ (case ((string_drop s2186_0 s2187_0)) of
+ s2188_0 =>
+ (case ((creg_name_matches_prefix s2188_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2189_0)) =>
+ (case ((string_drop s2188_0 s2189_0)) of
+ s2190_0 =>
+ (case ((sep_matches_prefix s2190_0)) of
+ SOME ((() , s2191_0)) =>
+ (case ((string_drop s2190_0 s2191_0)) of
+ s2192_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2192_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2193_0)) =>
+ let p0_ = (string_drop s2192_0 s2193_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2171_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2171_:string ->((3)words$word#(6)words$word)option) s2172_0=
+ (let s2173_0 = s2172_0 in
+ if ((string_startswith s2173_0 "c.srai")) then
+ (case ((string_drop s2173_0 ((string_length "c.srai")))) of
+ s2174_0 =>
+ (case ((spc_matches_prefix0 s2174_0)) of
+ SOME ((() , s2175_0)) =>
+ (case ((string_drop s2174_0 s2175_0)) of
+ s2176_0 =>
+ (case ((creg_name_matches_prefix s2176_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2177_0)) =>
+ (case ((string_drop s2176_0 s2177_0)) of
+ s2178_0 =>
+ (case ((sep_matches_prefix s2178_0)) of
+ SOME ((() , s2179_0)) =>
+ (case ((string_drop s2178_0 s2179_0)) of
+ s2180_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2180_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2181_0)) =>
+ let p0_ = (string_drop s2180_0 s2181_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2159_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2159_:string ->((3)words$word#(6)words$word)option) s2160_0=
+ (let s2161_0 = s2160_0 in
+ if ((string_startswith s2161_0 "c.srli")) then
+ (case ((string_drop s2161_0 ((string_length "c.srli")))) of
+ s2162_0 =>
+ (case ((spc_matches_prefix0 s2162_0)) of
+ SOME ((() , s2163_0)) =>
+ (case ((string_drop s2162_0 s2163_0)) of
+ s2164_0 =>
+ (case ((creg_name_matches_prefix s2164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2165_0)) =>
+ (case ((string_drop s2164_0 s2165_0)) of
+ s2166_0 =>
+ (case ((sep_matches_prefix s2166_0)) of
+ SOME ((() , s2167_0)) =>
+ (case ((string_drop s2166_0 s2167_0)) of
+ s2168_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2168_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2169_0)) =>
+ let p0_ = (string_drop s2168_0 s2169_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2147_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2147_:string ->((5)words$word#(6)words$word)option) s2148_0=
+ (let s2149_0 = s2148_0 in
+ if ((string_startswith s2149_0 "c.lui")) then
+ (case ((string_drop s2149_0 ((string_length "c.lui")))) of
+ s2150_0 =>
+ (case ((spc_matches_prefix0 s2150_0)) of
+ SOME ((() , s2151_0)) =>
+ (case ((string_drop s2150_0 s2151_0)) of
+ s2152_0 =>
+ (case ((reg_name_matches_prefix s2152_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2153_0)) =>
+ (case ((string_drop s2152_0 s2153_0)) of
+ s2154_0 =>
+ (case ((sep_matches_prefix s2154_0)) of
+ SOME ((() , s2155_0)) =>
+ (case ((string_drop s2154_0 s2155_0)) of
+ s2156_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2156_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2157_0)) =>
+ let p0_ = (string_drop s2156_0 s2157_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2139_ : string -> maybe (mword ty6)*)
+
+val _ = Define `
+ ((s2139_:string ->((6)words$word)option) s2140_0=
+ (let s2141_0 = s2140_0 in
+ if ((string_startswith s2141_0 "c.addi16sp")) then
+ (case ((string_drop s2141_0 ((string_length "c.addi16sp")))) of
+ s2142_0 =>
+ (case ((spc_matches_prefix0 s2142_0)) of
+ SOME ((() , s2143_0)) =>
+ (case ((string_drop s2142_0 s2143_0)) of
+ s2144_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2144_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2145_0)) =>
+ let p0_ = (string_drop s2144_0 s2145_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2127_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2127_:string ->((5)words$word#(6)words$word)option) s2128_0=
+ (let s2129_0 = s2128_0 in
+ if ((string_startswith s2129_0 "c.li")) then
+ (case ((string_drop s2129_0 ((string_length "c.li")))) of
+ s2130_0 =>
+ (case ((spc_matches_prefix0 s2130_0)) of
+ SOME ((() , s2131_0)) =>
+ (case ((string_drop s2130_0 s2131_0)) of
+ s2132_0 =>
+ (case ((reg_name_matches_prefix s2132_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2133_0)) =>
+ (case ((string_drop s2132_0 s2133_0)) of
+ s2134_0 =>
+ (case ((sep_matches_prefix s2134_0)) of
+ SOME ((() , s2135_0)) =>
+ (case ((string_drop s2134_0 s2135_0)) of
+ s2136_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2136_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2137_0)) =>
+ let p0_ = (string_drop s2136_0 s2137_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2115_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2115_:string ->((5)words$word#(6)words$word)option) s2116_0=
+ (let s2117_0 = s2116_0 in
+ if ((string_startswith s2117_0 "c.addiw")) then
+ (case ((string_drop s2117_0 ((string_length "c.addiw")))) of
+ s2118_0 =>
+ (case ((spc_matches_prefix0 s2118_0)) of
+ SOME ((() , s2119_0)) =>
+ (case ((string_drop s2118_0 s2119_0)) of
+ s2120_0 =>
+ (case ((reg_name_matches_prefix s2120_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2121_0)) =>
+ (case ((string_drop s2120_0 s2121_0)) of
+ s2122_0 =>
+ (case ((sep_matches_prefix s2122_0)) of
+ SOME ((() , s2123_0)) =>
+ (case ((string_drop s2122_0 s2123_0)) of
+ s2124_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2124_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2125_0)) =>
+ let p0_ = (string_drop s2124_0 s2125_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2107_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s2107_:string ->((11)words$word)option) s2108_0=
+ (let s2109_0 = s2108_0 in
+ if ((string_startswith s2109_0 "c.jal")) then
+ (case ((string_drop s2109_0 ((string_length "c.jal")))) of
+ s2110_0 =>
+ (case ((spc_matches_prefix0 s2110_0)) of
+ SOME ((() , s2111_0)) =>
+ (case ((string_drop s2110_0 s2111_0)) of
+ s2112_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2112_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__814, s2113_0)) =>
+ if (((((subrange_vec_dec v__814 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__814 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__814 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let p0_ = (string_drop s2112_0 s2113_0) in
+ if (((p0_ = ""))) then SOME imm else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2095_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2095_:string ->((5)words$word#(6)words$word)option) s2096_0=
+ (let s2097_0 = s2096_0 in
+ if ((string_startswith s2097_0 "c.addi")) then
+ (case ((string_drop s2097_0 ((string_length "c.addi")))) of
+ s2098_0 =>
+ (case ((spc_matches_prefix0 s2098_0)) of
+ SOME ((() , s2099_0)) =>
+ (case ((string_drop s2098_0 s2099_0)) of
+ s2100_0 =>
+ (case ((reg_name_matches_prefix s2100_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2101_0)) =>
+ (case ((string_drop s2100_0 s2101_0)) of
+ s2102_0 =>
+ (case ((sep_matches_prefix s2102_0)) of
+ SOME ((() , s2103_0)) =>
+ (case ((string_drop s2102_0 s2103_0)) of
+ s2104_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2104_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s2105_0)) =>
+ let p0_ = (string_drop s2104_0 s2105_0) in
+ if (((p0_ = ""))) then SOME (rsd, nzi) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2079_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2079_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2080_0=
+ (let s2081_0 = s2080_0 in
+ if ((string_startswith s2081_0 "c.sd")) then
+ (case ((string_drop s2081_0 ((string_length "c.sd")))) of
+ s2082_0 =>
+ (case ((spc_matches_prefix0 s2082_0)) of
+ SOME ((() , s2083_0)) =>
+ (case ((string_drop s2082_0 s2083_0)) of
+ s2084_0 =>
+ (case ((creg_name_matches_prefix s2084_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2085_0)) =>
+ (case ((string_drop s2084_0 s2085_0)) of
+ s2086_0 =>
+ (case ((sep_matches_prefix s2086_0)) of
+ SOME ((() , s2087_0)) =>
+ (case ((string_drop s2086_0 s2087_0)) of
+ s2088_0 =>
+ (case ((creg_name_matches_prefix s2088_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2089_0)) =>
+ (case ((string_drop s2088_0 s2089_0)) of
+ s2090_0 =>
+ (case ((sep_matches_prefix s2090_0)) of
+ SOME ((() , s2091_0)) =>
+ (case ((string_drop s2090_0 s2091_0)) of
+ s2092_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2092_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__816, s2093_0)) =>
+ if (((((subrange_vec_dec v__816 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__816 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__816 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2092_0 s2093_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2063_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2063_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2064_0=
+ (let s2065_0 = s2064_0 in
+ if ((string_startswith s2065_0 "c.sw")) then
+ (case ((string_drop s2065_0 ((string_length "c.sw")))) of
+ s2066_0 =>
+ (case ((spc_matches_prefix0 s2066_0)) of
+ SOME ((() , s2067_0)) =>
+ (case ((string_drop s2066_0 s2067_0)) of
+ s2068_0 =>
+ (case ((creg_name_matches_prefix s2068_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2069_0)) =>
+ (case ((string_drop s2068_0 s2069_0)) of
+ s2070_0 =>
+ (case ((sep_matches_prefix s2070_0)) of
+ SOME ((() , s2071_0)) =>
+ (case ((string_drop s2070_0 s2071_0)) of
+ s2072_0 =>
+ (case ((creg_name_matches_prefix s2072_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2073_0)) =>
+ (case ((string_drop s2072_0 s2073_0)) of
+ s2074_0 =>
+ (case ((sep_matches_prefix s2074_0)) of
+ SOME ((() , s2075_0)) =>
+ (case ((string_drop s2074_0 s2075_0)) of
+ s2076_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2076_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__818, s2077_0)) =>
+ if (((((subrange_vec_dec v__818 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__818 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__818 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2076_0 s2077_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2047_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2047_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2048_0=
+ (let s2049_0 = s2048_0 in
+ if ((string_startswith s2049_0 "c.ld")) then
+ (case ((string_drop s2049_0 ((string_length "c.ld")))) of
+ s2050_0 =>
+ (case ((spc_matches_prefix0 s2050_0)) of
+ SOME ((() , s2051_0)) =>
+ (case ((string_drop s2050_0 s2051_0)) of
+ s2052_0 =>
+ (case ((creg_name_matches_prefix s2052_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2053_0)) =>
+ (case ((string_drop s2052_0 s2053_0)) of
+ s2054_0 =>
+ (case ((sep_matches_prefix s2054_0)) of
+ SOME ((() , s2055_0)) =>
+ (case ((string_drop s2054_0 s2055_0)) of
+ s2056_0 =>
+ (case ((creg_name_matches_prefix s2056_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2057_0)) =>
+ (case ((string_drop s2056_0 s2057_0)) of
+ s2058_0 =>
+ (case ((sep_matches_prefix s2058_0)) of
+ SOME ((() , s2059_0)) =>
+ (case ((string_drop s2058_0 s2059_0)) of
+ s2060_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2060_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__820, s2061_0)) =>
+ if (((((subrange_vec_dec v__820 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__820 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__820 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2060_0 s2061_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2031_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2031_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2032_0=
+ (let s2033_0 = s2032_0 in
+ if ((string_startswith s2033_0 "c.lw")) then
+ (case ((string_drop s2033_0 ((string_length "c.lw")))) of
+ s2034_0 =>
+ (case ((spc_matches_prefix0 s2034_0)) of
+ SOME ((() , s2035_0)) =>
+ (case ((string_drop s2034_0 s2035_0)) of
+ s2036_0 =>
+ (case ((creg_name_matches_prefix s2036_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2037_0)) =>
+ (case ((string_drop s2036_0 s2037_0)) of
+ s2038_0 =>
+ (case ((sep_matches_prefix s2038_0)) of
+ SOME ((() , s2039_0)) =>
+ (case ((string_drop s2038_0 s2039_0)) of
+ s2040_0 =>
+ (case ((creg_name_matches_prefix s2040_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2041_0)) =>
+ (case ((string_drop s2040_0 s2041_0)) of
+ s2042_0 =>
+ (case ((sep_matches_prefix s2042_0)) of
+ SOME ((() , s2043_0)) =>
+ (case ((string_drop s2042_0 s2043_0)) of
+ s2044_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2044_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__822, s2045_0)) =>
+ if (((((subrange_vec_dec v__822 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__822 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__822 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2044_0 s2045_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2019_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2019_:string ->((3)words$word#(8)words$word)option) s2020_0=
+ (let s2021_0 = s2020_0 in
+ if ((string_startswith s2021_0 "c.addi4spn")) then
+ (case ((string_drop s2021_0 ((string_length "c.addi4spn")))) of
+ s2022_0 =>
+ (case ((spc_matches_prefix0 s2022_0)) of
+ SOME ((() , s2023_0)) =>
+ (case ((string_drop s2022_0 s2023_0)) of
+ s2024_0 =>
+ (case ((creg_name_matches_prefix s2024_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2025_0)) =>
+ (case ((string_drop s2024_0 s2025_0)) of
+ s2026_0 =>
+ (case ((sep_matches_prefix s2026_0)) of
+ SOME ((() , s2027_0)) =>
+ (case ((string_drop s2026_0 s2027_0)) of
+ s2028_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2028_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__824, s2029_0)) =>
+ if (((((subrange_vec_dec v__824 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__824 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__824 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let p0_ = (string_drop s2028_0 s2029_0) in
+ if (((p0_ = ""))) then SOME (rdc, nzimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1995_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1995_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1996_0=
+ ((case s1996_0 of
+ s1997_0 =>
+ (case ((amo_mnemonic_matches_prefix s1997_0)) of
+ SOME ((op, s1998_0)) =>
+ let s1999_0 = (string_drop s1997_0 s1998_0) in
+ if ((string_startswith s1999_0 ".")) then
+ (case ((string_drop s1999_0 ((string_length ".")))) of
+ s2000_0 =>
+ (case ((size_mnemonic_matches_prefix s2000_0)) of
+ SOME ((width, s2001_0)) =>
+ (case ((string_drop s2000_0 s2001_0)) of
+ s2002_0 =>
+ (case ((maybe_aq_matches_prefix s2002_0)) of
+ SOME ((aq, s2003_0)) =>
+ (case ((string_drop s2002_0 s2003_0)) of
+ s2004_0 =>
+ (case ((maybe_rl_matches_prefix s2004_0)) of
+ SOME ((rl, s2005_0)) =>
+ (case ((string_drop s2004_0 s2005_0)) of
+ s2006_0 =>
+ (case ((spc_matches_prefix0 s2006_0)) of
+ SOME ((() , s2007_0)) =>
+ (case ((string_drop s2006_0 s2007_0)) of
+ s2008_0 =>
+ (case ((reg_name_matches_prefix s2008_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2009_0)) =>
+ (case ((string_drop s2008_0 s2009_0)) of
+ s2010_0 =>
+ (case ((sep_matches_prefix s2010_0)) of
+ SOME ((() , s2011_0)) =>
+ (case ((string_drop s2010_0 s2011_0)) of
+ s2012_0 =>
+ (case ((reg_name_matches_prefix s2012_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2013_0)) =>
+ (case ((string_drop s2012_0 s2013_0)) of
+ s2014_0 =>
+ (case ((sep_matches_prefix s2014_0)) of
+ SOME ((() , s2015_0)) =>
+ (case ((string_drop s2014_0 s2015_0)) of
+ s2016_0 =>
+ (case ((reg_name_matches_prefix s2016_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2017_0)) =>
+ let p0_ = (string_drop s2016_0 s2017_0) in
+ if (((p0_ = ""))) then SOME (op, width, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1973_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1973_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1974_0=
+ (let s1975_0 = s1974_0 in
+ if ((string_startswith s1975_0 "sc.")) then
+ (case ((string_drop s1975_0 ((string_length "sc.")))) of
+ s1976_0 =>
+ (case ((size_mnemonic_matches_prefix s1976_0)) of
+ SOME ((size1, s1977_0)) =>
+ (case ((string_drop s1976_0 s1977_0)) of
+ s1978_0 =>
+ (case ((maybe_aq_matches_prefix s1978_0)) of
+ SOME ((aq, s1979_0)) =>
+ (case ((string_drop s1978_0 s1979_0)) of
+ s1980_0 =>
+ (case ((maybe_rl_matches_prefix s1980_0)) of
+ SOME ((rl, s1981_0)) =>
+ (case ((string_drop s1980_0 s1981_0)) of
+ s1982_0 =>
+ (case ((spc_matches_prefix0 s1982_0)) of
+ SOME ((() , s1983_0)) =>
+ (case ((string_drop s1982_0 s1983_0)) of
+ s1984_0 =>
+ (case ((reg_name_matches_prefix s1984_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1985_0)) =>
+ (case ((string_drop s1984_0 s1985_0)) of
+ s1986_0 =>
+ (case ((sep_matches_prefix s1986_0)) of
+ SOME ((() , s1987_0)) =>
+ (case ((string_drop s1986_0 s1987_0)) of
+ s1988_0 =>
+ (case ((reg_name_matches_prefix s1988_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1989_0)) =>
+ (case ((string_drop s1988_0 s1989_0)) of
+ s1990_0 =>
+ (case ((sep_matches_prefix s1990_0)) of
+ SOME ((() , s1991_0)) =>
+ (case ((string_drop s1990_0 s1991_0)) of
+ s1992_0 =>
+ (case ((reg_name_matches_prefix s1992_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1993_0)) =>
+ let p0_ = (string_drop s1992_0 s1993_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1955_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1955_:string ->(word_width#bool#bool#(5)words$word#(5)words$word)option) s1956_0=
+ (let s1957_0 = s1956_0 in
+ if ((string_startswith s1957_0 "lr.")) then
+ (case ((string_drop s1957_0 ((string_length "lr.")))) of
+ s1958_0 =>
+ (case ((size_mnemonic_matches_prefix s1958_0)) of
+ SOME ((size1, s1959_0)) =>
+ (case ((string_drop s1958_0 s1959_0)) of
+ s1960_0 =>
+ (case ((maybe_aq_matches_prefix s1960_0)) of
+ SOME ((aq, s1961_0)) =>
+ (case ((string_drop s1960_0 s1961_0)) of
+ s1962_0 =>
+ (case ((maybe_rl_matches_prefix s1962_0)) of
+ SOME ((rl, s1963_0)) =>
+ (case ((string_drop s1962_0 s1963_0)) of
+ s1964_0 =>
+ (case ((spc_matches_prefix0 s1964_0)) of
+ SOME ((() , s1965_0)) =>
+ (case ((string_drop s1964_0 s1965_0)) of
+ s1966_0 =>
+ (case ((reg_name_matches_prefix s1966_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1967_0)) =>
+ (case ((string_drop s1966_0 s1967_0)) of
+ s1968_0 =>
+ (case ((sep_matches_prefix s1968_0)) of
+ SOME ((() , s1969_0)) =>
+ (case ((string_drop s1968_0 s1969_0)) of
+ s1970_0 =>
+ (case ((reg_name_matches_prefix s1970_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1971_0)) =>
+ let p0_ = (string_drop s1970_0 s1971_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1943_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1943_:string ->((5)words$word#(5)words$word)option) s1944_0=
+ (let s1945_0 = s1944_0 in
+ if ((string_startswith s1945_0 "sfence.vma")) then
+ (case ((string_drop s1945_0 ((string_length "sfence.vma")))) of
+ s1946_0 =>
+ (case ((spc_matches_prefix0 s1946_0)) of
+ SOME ((() , s1947_0)) =>
+ (case ((string_drop s1946_0 s1947_0)) of
+ s1948_0 =>
+ (case ((reg_name_matches_prefix s1948_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1949_0)) =>
+ (case ((string_drop s1948_0 s1949_0)) of
+ s1950_0 =>
+ (case ((sep_matches_prefix s1950_0)) of
+ SOME ((() , s1951_0)) =>
+ (case ((string_drop s1950_0 s1951_0)) of
+ s1952_0 =>
+ (case ((reg_name_matches_prefix s1952_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1953_0)) =>
+ let p0_ = (string_drop s1952_0 s1953_0) in
+ if (((p0_ = ""))) then SOME (rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1931_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1931_:string ->((4)words$word#(4)words$word)option) s1932_0=
+ (let s1933_0 = s1932_0 in
+ if ((string_startswith s1933_0 "fence.tso")) then
+ (case ((string_drop s1933_0 ((string_length "fence.tso")))) of
+ s1934_0 =>
+ (case ((spc_matches_prefix0 s1934_0)) of
+ SOME ((() , s1935_0)) =>
+ (case ((string_drop s1934_0 s1935_0)) of
+ s1936_0 =>
+ (case ((fence_bits_matches_prefix s1936_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1937_0)) =>
+ (case ((string_drop s1936_0 s1937_0)) of
+ s1938_0 =>
+ (case ((sep_matches_prefix s1938_0)) of
+ SOME ((() , s1939_0)) =>
+ (case ((string_drop s1938_0 s1939_0)) of
+ s1940_0 =>
+ (case ((fence_bits_matches_prefix s1940_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1941_0)) =>
+ let p0_ = (string_drop s1940_0 s1941_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1919_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1919_:string ->((4)words$word#(4)words$word)option) s1920_0=
+ (let s1921_0 = s1920_0 in
+ if ((string_startswith s1921_0 "fence")) then
+ (case ((string_drop s1921_0 ((string_length "fence")))) of
+ s1922_0 =>
+ (case ((spc_matches_prefix0 s1922_0)) of
+ SOME ((() , s1923_0)) =>
+ (case ((string_drop s1922_0 s1923_0)) of
+ s1924_0 =>
+ (case ((fence_bits_matches_prefix s1924_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1925_0)) =>
+ (case ((string_drop s1924_0 s1925_0)) of
+ s1926_0 =>
+ (case ((sep_matches_prefix s1926_0)) of
+ SOME ((() , s1927_0)) =>
+ (case ((string_drop s1926_0 s1927_0)) of
+ s1928_0 =>
+ (case ((fence_bits_matches_prefix s1928_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1929_0)) =>
+ let p0_ = (string_drop s1928_0 s1929_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1902_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1902_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word)option) s1903_0=
+ ((case s1903_0 of
+ s1904_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s1904_0)) of
+ SOME ((op, s1905_0)) =>
+ (case ((string_drop s1904_0 s1905_0)) of
+ s1906_0 =>
+ (case ((spc_matches_prefix0 s1906_0)) of
+ SOME ((() , s1907_0)) =>
+ (case ((string_drop s1906_0 s1907_0)) of
+ s1908_0 =>
+ (case ((reg_name_matches_prefix s1908_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1909_0)) =>
+ (case ((string_drop s1908_0 s1909_0)) of
+ s1910_0 =>
+ (case ((sep_matches_prefix s1910_0)) of
+ SOME ((() , s1911_0)) =>
+ (case ((string_drop s1910_0 s1911_0)) of
+ s1912_0 =>
+ (case ((reg_name_matches_prefix s1912_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1913_0)) =>
+ (case ((string_drop s1912_0 s1913_0)) of
+ s1914_0 =>
+ (case ((sep_matches_prefix s1914_0)) of
+ SOME ((() , s1915_0)) =>
+ (case ((string_drop s1914_0 s1915_0)) of
+ s1916_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1916_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1917_0)) =>
+ let p0_ = (string_drop s1916_0 s1917_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1885_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1885_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word)option) s1886_0=
+ ((case s1886_0 of
+ s1887_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s1887_0)) of
+ SOME ((op, s1888_0)) =>
+ (case ((string_drop s1887_0 s1888_0)) of
+ s1889_0 =>
+ (case ((spc_matches_prefix0 s1889_0)) of
+ SOME ((() , s1890_0)) =>
+ (case ((string_drop s1889_0 s1890_0)) of
+ s1891_0 =>
+ (case ((reg_name_matches_prefix s1891_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1892_0)) =>
+ (case ((string_drop s1891_0 s1892_0)) of
+ s1893_0 =>
+ (case ((sep_matches_prefix s1893_0)) of
+ SOME ((() , s1894_0)) =>
+ (case ((string_drop s1893_0 s1894_0)) of
+ s1895_0 =>
+ (case ((reg_name_matches_prefix s1895_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1896_0)) =>
+ (case ((string_drop s1895_0 s1896_0)) of
+ s1897_0 =>
+ (case ((sep_matches_prefix s1897_0)) of
+ SOME ((() , s1898_0)) =>
+ (case ((string_drop s1897_0 s1898_0)) of
+ s1899_0 =>
+ (case ((reg_name_matches_prefix s1899_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1900_0)) =>
+ let p0_ = (string_drop s1899_0 s1900_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1868_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1868_:string ->(sop#(5)words$word#(5)words$word#(5)words$word)option) s1869_0=
+ ((case s1869_0 of
+ s1870_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s1870_0)) of
+ SOME ((op, s1871_0)) =>
+ (case ((string_drop s1870_0 s1871_0)) of
+ s1872_0 =>
+ (case ((spc_matches_prefix0 s1872_0)) of
+ SOME ((() , s1873_0)) =>
+ (case ((string_drop s1872_0 s1873_0)) of
+ s1874_0 =>
+ (case ((reg_name_matches_prefix s1874_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1875_0)) =>
+ (case ((string_drop s1874_0 s1875_0)) of
+ s1876_0 =>
+ (case ((sep_matches_prefix s1876_0)) of
+ SOME ((() , s1877_0)) =>
+ (case ((string_drop s1876_0 s1877_0)) of
+ s1878_0 =>
+ (case ((reg_name_matches_prefix s1878_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1879_0)) =>
+ (case ((string_drop s1878_0 s1879_0)) of
+ s1880_0 =>
+ (case ((sep_matches_prefix s1880_0)) of
+ SOME ((() , s1881_0)) =>
+ (case ((string_drop s1880_0 s1881_0)) of
+ s1882_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1882_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1883_0)) =>
+ let p0_ = (string_drop s1882_0 s1883_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1852_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1852_:string ->((5)words$word#(5)words$word#(12)words$word)option) s1853_0=
+ (let s1854_0 = s1853_0 in
+ if ((string_startswith s1854_0 "addiw")) then
+ (case ((string_drop s1854_0 ((string_length "addiw")))) of
+ s1855_0 =>
+ (case ((spc_matches_prefix0 s1855_0)) of
+ SOME ((() , s1856_0)) =>
+ (case ((string_drop s1855_0 s1856_0)) of
+ s1857_0 =>
+ (case ((reg_name_matches_prefix s1857_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1858_0)) =>
+ (case ((string_drop s1857_0 s1858_0)) of
+ s1859_0 =>
+ (case ((sep_matches_prefix s1859_0)) of
+ SOME ((() , s1860_0)) =>
+ (case ((string_drop s1859_0 s1860_0)) of
+ s1861_0 =>
+ (case ((reg_name_matches_prefix s1861_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1862_0)) =>
+ (case ((string_drop s1861_0 s1862_0)) of
+ s1863_0 =>
+ (case ((sep_matches_prefix s1863_0)) of
+ SOME ((() , s1864_0)) =>
+ (case ((string_drop s1863_0 s1864_0)) of
+ s1865_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1865_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1866_0)) =>
+ let p0_ = (string_drop s1865_0 s1866_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1824_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s1824_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s1825_0=
+ (let s1826_0 = s1825_0 in
+ if ((string_startswith s1826_0 "s")) then
+ (case ((string_drop s1826_0 ((string_length "s")))) of
+ s1827_0 =>
+ (case ((size_mnemonic_matches_prefix s1827_0)) of
+ SOME ((size1, s1828_0)) =>
+ (case ((string_drop s1827_0 s1828_0)) of
+ s1829_0 =>
+ (case ((maybe_aq_matches_prefix s1829_0)) of
+ SOME ((aq, s1830_0)) =>
+ (case ((string_drop s1829_0 s1830_0)) of
+ s1831_0 =>
+ (case ((maybe_rl_matches_prefix s1831_0)) of
+ SOME ((rl, s1832_0)) =>
+ (case ((string_drop s1831_0 s1832_0)) of
+ s1833_0 =>
+ (case ((spc_matches_prefix0 s1833_0)) of
+ SOME ((() , s1834_0)) =>
+ (case ((string_drop s1833_0 s1834_0)) of
+ s1835_0 =>
+ (case ((reg_name_matches_prefix s1835_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1836_0)) =>
+ (case ((string_drop s1835_0 s1836_0)) of
+ s1837_0 =>
+ (case ((sep_matches_prefix s1837_0)) of
+ SOME ((() , s1838_0)) =>
+ (case ((string_drop s1837_0 s1838_0)) of
+ s1839_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1839_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1840_0)) =>
+ (case ((string_drop s1839_0 s1840_0)) of
+ s1841_0 =>
+ (case ((opt_spc_matches_prefix0 s1841_0)) of
+ SOME ((() , s1842_0)) =>
+ let s1843_0 = (string_drop s1841_0 s1842_0) in
+ if ((string_startswith s1843_0 "(")) then
+ (case ((string_drop s1843_0 ((string_length "(")))) of
+ s1844_0 =>
+ (case ((opt_spc_matches_prefix0 s1844_0)) of
+ SOME ((() , s1845_0)) =>
+ (case ((string_drop s1844_0 s1845_0)) of
+ s1846_0 =>
+ (case ((reg_name_matches_prefix s1846_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1847_0)) =>
+ (case ((string_drop s1846_0 s1847_0)) of
+ s1848_0 =>
+ (case ((opt_spc_matches_prefix0 s1848_0)) of
+ SOME ((() , s1849_0)) =>
+ let s1850_0 = (string_drop s1848_0 s1849_0) in
+ if ((string_startswith s1850_0 ")")) then
+ let p0_ = (string_drop s1850_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rs2, imm, rs1) else NONE
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1794_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s1794_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s1795_0=
+ (let s1796_0 = s1795_0 in
+ if ((string_startswith s1796_0 "l")) then
+ (case ((string_drop s1796_0 ((string_length "l")))) of
+ s1797_0 =>
+ (case ((size_mnemonic_matches_prefix s1797_0)) of
+ SOME ((size1, s1798_0)) =>
+ (case ((string_drop s1797_0 s1798_0)) of
+ s1799_0 =>
+ (case ((maybe_u_matches_prefix s1799_0)) of
+ SOME ((is_unsigned, s1800_0)) =>
+ (case ((string_drop s1799_0 s1800_0)) of
+ s1801_0 =>
+ (case ((maybe_aq_matches_prefix s1801_0)) of
+ SOME ((aq, s1802_0)) =>
+ (case ((string_drop s1801_0 s1802_0)) of
+ s1803_0 =>
+ (case ((maybe_rl_matches_prefix s1803_0)) of
+ SOME ((rl, s1804_0)) =>
+ (case ((string_drop s1803_0 s1804_0)) of
+ s1805_0 =>
+ (case ((spc_matches_prefix0 s1805_0)) of
+ SOME ((() , s1806_0)) =>
+ (case ((string_drop s1805_0 s1806_0)) of
+ s1807_0 =>
+ (case ((reg_name_matches_prefix s1807_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1808_0)) =>
+ (case ((string_drop s1807_0 s1808_0)) of
+ s1809_0 =>
+ (case ((sep_matches_prefix s1809_0)) of
+ SOME ((() , s1810_0)) =>
+ (case ((string_drop s1809_0 s1810_0)) of
+ s1811_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1811_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1812_0)) =>
+ (case ((string_drop s1811_0 s1812_0)) of
+ s1813_0 =>
+ (case ((opt_spc_matches_prefix0 s1813_0)) of
+ SOME ((() , s1814_0)) =>
+ let s1815_0 = (string_drop s1813_0 s1814_0) in
+ if ((string_startswith s1815_0 "(")) then
+ (case ((string_drop s1815_0 ((string_length "(")))) of
+ s1816_0 =>
+ (case ((opt_spc_matches_prefix0 s1816_0)) of
+ SOME ((() , s1817_0)) =>
+ (case ((string_drop s1816_0 s1817_0)) of
+ s1818_0 =>
+ (case ((reg_name_matches_prefix s1818_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1819_0)) =>
+ (case ((string_drop s1818_0 s1819_0)) of
+ s1820_0 =>
+ (case ((opt_spc_matches_prefix0 s1820_0)) of
+ SOME ((() , s1821_0)) =>
+ let s1822_0 = (string_drop s1820_0 s1821_0) in
+ if ((string_startswith s1822_0 ")")) then
+ let p0_ = (string_drop s1822_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, is_unsigned, aq, rl, rd, imm, rs1)
+ else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1777_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1777_:string ->(rop#(5)words$word#(5)words$word#(5)words$word)option) s1778_0=
+ ((case s1778_0 of
+ s1779_0 =>
+ (case ((rtype_mnemonic_matches_prefix s1779_0)) of
+ SOME ((op, s1780_0)) =>
+ (case ((string_drop s1779_0 s1780_0)) of
+ s1781_0 =>
+ (case ((spc_matches_prefix0 s1781_0)) of
+ SOME ((() , s1782_0)) =>
+ (case ((string_drop s1781_0 s1782_0)) of
+ s1783_0 =>
+ (case ((reg_name_matches_prefix s1783_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1784_0)) =>
+ (case ((string_drop s1783_0 s1784_0)) of
+ s1785_0 =>
+ (case ((sep_matches_prefix s1785_0)) of
+ SOME ((() , s1786_0)) =>
+ (case ((string_drop s1785_0 s1786_0)) of
+ s1787_0 =>
+ (case ((reg_name_matches_prefix s1787_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1788_0)) =>
+ (case ((string_drop s1787_0 s1788_0)) of
+ s1789_0 =>
+ (case ((sep_matches_prefix s1789_0)) of
+ SOME ((() , s1790_0)) =>
+ (case ((string_drop s1789_0 s1790_0)) of
+ s1791_0 =>
+ (case ((reg_name_matches_prefix s1791_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1792_0)) =>
+ let p0_ = (string_drop s1791_0 s1792_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1760_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1760_:string ->(sop#(5)words$word#(5)words$word#(6)words$word)option) s1761_0=
+ ((case s1761_0 of
+ s1762_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s1762_0)) of
+ SOME ((op, s1763_0)) =>
+ (case ((string_drop s1762_0 s1763_0)) of
+ s1764_0 =>
+ (case ((spc_matches_prefix0 s1764_0)) of
+ SOME ((() , s1765_0)) =>
+ (case ((string_drop s1764_0 s1765_0)) of
+ s1766_0 =>
+ (case ((reg_name_matches_prefix s1766_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1767_0)) =>
+ (case ((string_drop s1766_0 s1767_0)) of
+ s1768_0 =>
+ (case ((sep_matches_prefix s1768_0)) of
+ SOME ((() , s1769_0)) =>
+ (case ((string_drop s1768_0 s1769_0)) of
+ s1770_0 =>
+ (case ((reg_name_matches_prefix s1770_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1771_0)) =>
+ (case ((string_drop s1770_0 s1771_0)) of
+ s1772_0 =>
+ (case ((sep_matches_prefix s1772_0)) of
+ SOME ((() , s1773_0)) =>
+ (case ((string_drop s1772_0 s1773_0)) of
+ s1774_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1774_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1775_0)) =>
+ let p0_ = (string_drop s1774_0 s1775_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1743_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1743_:string ->(iop#(5)words$word#(5)words$word#(12)words$word)option) s1744_0=
+ ((case s1744_0 of
+ s1745_0 =>
+ (case ((itype_mnemonic_matches_prefix s1745_0)) of
+ SOME ((op, s1746_0)) =>
+ (case ((string_drop s1745_0 s1746_0)) of
+ s1747_0 =>
+ (case ((spc_matches_prefix0 s1747_0)) of
+ SOME ((() , s1748_0)) =>
+ (case ((string_drop s1747_0 s1748_0)) of
+ s1749_0 =>
+ (case ((reg_name_matches_prefix s1749_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1750_0)) =>
+ (case ((string_drop s1749_0 s1750_0)) of
+ s1751_0 =>
+ (case ((sep_matches_prefix s1751_0)) of
+ SOME ((() , s1752_0)) =>
+ (case ((string_drop s1751_0 s1752_0)) of
+ s1753_0 =>
+ (case ((reg_name_matches_prefix s1753_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1754_0)) =>
+ (case ((string_drop s1753_0 s1754_0)) of
+ s1755_0 =>
+ (case ((sep_matches_prefix s1755_0)) of
+ SOME ((() , s1756_0)) =>
+ (case ((string_drop s1755_0 s1756_0)) of
+ s1757_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1757_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1758_0)) =>
+ let p0_ = (string_drop s1757_0 s1758_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1726_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))*)
+
+val _ = Define `
+ ((s1726_:string ->(bop#(5)words$word#(5)words$word#(13)words$word)option) s1727_0=
+ ((case s1727_0 of
+ s1728_0 =>
+ (case ((btype_mnemonic_matches_prefix s1728_0)) of
+ SOME ((op, s1729_0)) =>
+ (case ((string_drop s1728_0 s1729_0)) of
+ s1730_0 =>
+ (case ((spc_matches_prefix0 s1730_0)) of
+ SOME ((() , s1731_0)) =>
+ (case ((string_drop s1730_0 s1731_0)) of
+ s1732_0 =>
+ (case ((reg_name_matches_prefix s1732_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1733_0)) =>
+ (case ((string_drop s1732_0 s1733_0)) of
+ s1734_0 =>
+ (case ((sep_matches_prefix s1734_0)) of
+ SOME ((() , s1735_0)) =>
+ (case ((string_drop s1734_0 s1735_0)) of
+ s1736_0 =>
+ (case ((reg_name_matches_prefix s1736_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1737_0)) =>
+ (case ((string_drop s1736_0 s1737_0)) of
+ s1738_0 =>
+ (case ((sep_matches_prefix s1738_0)) of
+ SOME ((() , s1739_0)) =>
+ (case ((string_drop s1738_0 s1739_0)) of
+ s1740_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1740_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s1741_0)) =>
+ let p0_ = (string_drop s1740_0 s1741_0) in
+ if (((p0_ = ""))) then SOME (op, rs1, rs2, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1710_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1710_:string ->((5)words$word#(5)words$word#(12)words$word)option) s1711_0=
+ (let s1712_0 = s1711_0 in
+ if ((string_startswith s1712_0 "jalr")) then
+ (case ((string_drop s1712_0 ((string_length "jalr")))) of
+ s1713_0 =>
+ (case ((spc_matches_prefix0 s1713_0)) of
+ SOME ((() , s1714_0)) =>
+ (case ((string_drop s1713_0 s1714_0)) of
+ s1715_0 =>
+ (case ((reg_name_matches_prefix s1715_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1716_0)) =>
+ (case ((string_drop s1715_0 s1716_0)) of
+ s1717_0 =>
+ (case ((sep_matches_prefix s1717_0)) of
+ SOME ((() , s1718_0)) =>
+ (case ((string_drop s1717_0 s1718_0)) of
+ s1719_0 =>
+ (case ((reg_name_matches_prefix s1719_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1720_0)) =>
+ (case ((string_drop s1719_0 s1720_0)) of
+ s1721_0 =>
+ (case ((sep_matches_prefix s1721_0)) of
+ SOME ((() , s1722_0)) =>
+ (case ((string_drop s1721_0 s1722_0)) of
+ s1723_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1723_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1724_0)) =>
+ let p0_ = (string_drop s1723_0 s1724_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1698_ : string -> maybe ((mword ty5 * mword ty21))*)
+
+val _ = Define `
+ ((s1698_:string ->((5)words$word#(21)words$word)option) s1699_0=
+ (let s1700_0 = s1699_0 in
+ if ((string_startswith s1700_0 "jal")) then
+ (case ((string_drop s1700_0 ((string_length "jal")))) of
+ s1701_0 =>
+ (case ((spc_matches_prefix0 s1701_0)) of
+ SOME ((() , s1702_0)) =>
+ (case ((string_drop s1701_0 s1702_0)) of
+ s1703_0 =>
+ (case ((reg_name_matches_prefix s1703_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1704_0)) =>
+ (case ((string_drop s1703_0 s1704_0)) of
+ s1705_0 =>
+ (case ((sep_matches_prefix s1705_0)) of
+ SOME ((() , s1706_0)) =>
+ (case ((string_drop s1705_0 s1706_0)) of
+ s1707_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1707_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s1708_0)) =>
+ let p0_ = (string_drop s1707_0 s1708_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1685_ : string -> maybe ((uop * mword ty5 * mword ty20))*)
+
+val _ = Define `
+ ((s1685_:string ->(uop#(5)words$word#(20)words$word)option) s1686_0=
+ ((case s1686_0 of
+ s1687_0 =>
+ (case ((utype_mnemonic_matches_prefix s1687_0)) of
+ SOME ((op, s1688_0)) =>
+ (case ((string_drop s1687_0 s1688_0)) of
+ s1689_0 =>
+ (case ((spc_matches_prefix0 s1689_0)) of
+ SOME ((() , s1690_0)) =>
+ (case ((string_drop s1689_0 s1690_0)) of
+ s1691_0 =>
+ (case ((reg_name_matches_prefix s1691_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1692_0)) =>
+ (case ((string_drop s1691_0 s1692_0)) of
+ s1693_0 =>
+ (case ((sep_matches_prefix s1693_0)) of
+ SOME ((() , s1694_0)) =>
+ (case ((string_drop s1693_0 s1694_0)) of
+ s1695_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1695_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s1696_0)) =>
+ let p0_ = (string_drop s1695_0 s1696_0) in
+ if (((p0_ = ""))) then SOME (op, rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_backwards_matches:string -> bool) arg_=
+ (let s1697_0 = arg_ in
+ if ((case ((s1685_ s1697_0 : ((uop # 5 words$word # 20 words$word))option)) of
+ SOME ((op, rd, imm)) => T
+ | _ => F
+ )) then (case (s1685_ s1697_0 : (( uop # 5 words$word # 20 words$word)) option) of
+ (SOME ((op, rd, imm))) =>
+ T
+ )
+ else if ((case ((s1698_ s1697_0 : (( 5 words$word # 21 words$word))option)) of
+ SOME ((rd, imm)) => T
+ | _ => F
+ )) then (case (s1698_ s1697_0 : (( 5 words$word # 21 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s1710_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => T
+ | _ => F
+ )) then (case (s1710_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1726_ s1697_0 : ((bop # 5 words$word # 5 words$word # 13 words$word))option)) of
+ SOME ((op, rs1, rs2, imm)) => T
+ | _ => F
+ )) then (case
+ (s1726_ s1697_0 : (( bop # 5 words$word # 5 words$word # 13 words$word)) option) of
+ (SOME ((op, rs1, rs2, imm))) =>
+ T
+ )
+ else if ((case ((s1743_ s1697_0 : ((iop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, imm)) => T
+ | _ => F
+ )) then (case
+ (s1743_ s1697_0 : (( iop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1760_ s1697_0 : ((sop # 5 words$word # 5 words$word # 6 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => T
+ | _ => F
+ )) then (case
+ (s1760_ s1697_0 : (( sop # 5 words$word # 5 words$word # 6 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1777_ s1697_0 : ((rop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1777_ s1697_0 : (( rop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1794_ s1697_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1794_ s1697_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ T
+ )
+ else if ((case ((s1824_ s1697_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1824_ s1697_0 : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1))) =>
+ T
+ )
+ else if ((case ((s1852_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1852_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1868_ s1697_0 : ((sop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1868_ s1697_0 : (( sop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1885_ s1697_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1885_ s1697_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1902_ s1697_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1902_ s1697_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1919_ s1697_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1919_ s1697_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ T
+ )
+ else if ((case ((s1931_ s1697_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1931_ s1697_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ T
+ )
+ else if (((s1697_0 = "fence.i"))) then T
+ else if (((s1697_0 = "ecall"))) then T
+ else if (((s1697_0 = "mret"))) then T
+ else if (((s1697_0 = "sret"))) then T
+ else if (((s1697_0 = "ebreak"))) then T
+ else if (((s1697_0 = "wfi"))) then T
+ else if ((case ((s1943_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rs1, rs2)) => T
+ | _ => F
+ )) then (case (s1943_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1955_ s1697_0 : ((word_width # bool # bool # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1955_ s1697_0 : (( word_width # bool # bool # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1))) =>
+ T
+ )
+ else if ((case ((s1973_ s1697_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1973_ s1697_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1995_ s1697_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1995_ s1697_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2))) =>
+ T
+ )
+ else if (((s1697_0 = "c.nop"))) then T
+ else if ((case ((s2019_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rdc, nzimm)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s2019_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rdc, nzimm))) =>
+ T
+ )
+ else if ((case ((s2031_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => T
+ | _ => F
+ )) then (case
+ (s2031_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ T
+ )
+ else if ((case ((s2047_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2047_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ T
+ )
+ else if ((case ((s2063_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => T
+ | _ => F
+ )) then (case
+ (s2063_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ T
+ )
+ else if ((case ((s2079_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2079_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ T
+ )
+ else if ((case ((s2095_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, nzi)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2095_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, nzi))) =>
+ T
+ )
+ else if ((case ((s2107_ s1697_0 : ( 11 words$word)option)) of
+ SOME (imm) => ((( 32 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s2107_ s1697_0 : ( 11 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2115_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2115_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ T
+ )
+ else if ((case ((s2127_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2127_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s2139_ s1697_0 : ( 6 words$word)option)) of
+ SOME (imm) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2139_ s1697_0 : ( 6 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2147_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s2147_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s2159_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2159_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2171_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2171_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2183_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => T
+ | _ => F
+ )) then (case (s2183_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ T
+ )
+ else if ((case ((s2195_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2195_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2207_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2207_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2219_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2219_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2231_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2231_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2243_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2243_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2255_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2255_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2267_ s1697_0 : ( 11 words$word)option)) of
+ SOME (imm) => T
+ | _ => F
+ )) then (case (s2267_ s1697_0 : ( 11 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2275_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s2275_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ T
+ )
+ else if ((case ((s2287_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s2287_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ T
+ )
+ else if ((case ((s2299_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2299_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2311_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2311_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2323_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s2323_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2335_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => T
+ | _ => F
+ )) then (case (s2335_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2347_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rs2, uimm)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2347_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rs2, uimm))) =>
+ T
+ )
+ else if ((case ((s2359_ s1697_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2359_ s1697_0 : ( 5 words$word) option) of (SOME (rs1)) => T )
+ else if ((case ((s2367_ s1697_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2367_ s1697_0 : ( 5 words$word) option) of (SOME (rs1)) => T )
+ else if ((case ((s2375_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2375_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs2))) =>
+ T
+ )
+ else if (((s1697_0 = "c.ebreak"))) then T
+ else if ((case ((s2387_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2387_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2399_ s1697_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2399_ s1697_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2416_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2416_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2434_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2434_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2452_ s1697_0 : (( 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2452_ s1697_0 : (( 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2468_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2468_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2487_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2487_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2506_ s1697_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s2506_ s1697_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ T
+ )
+ else if ((case ((s2524_ s1697_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s2524_ s1697_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ T
+ )
+ else if (((s1697_0 = "uret"))) then T
+ else if ((case ((s2541_ s1697_0 : ( 32 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s2541_ s1697_0 : ( 32 words$word) option) of (SOME (s)) => T )
+ else if ((case ((s2549_ s1697_0 : ( 16 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s2549_ s1697_0 : ( 16 words$word) option) of (SOME (s)) => T )
+ else F))`;
+
+
+(*val assembly_matches_prefix : string -> maybe ((ast * ii))*)
+
+(*val _s3457_ : string -> maybe ((mword ty16 * string))*)
+
+val _ = Define `
+ ((s3457_:string ->((16)words$word#string)option) s3458_0=
+ (let s3459_0 = s3458_0 in
+ if ((string_startswith s3459_0 "c.illegal")) then
+ (case ((string_drop s3459_0 ((string_length "c.illegal")))) of
+ s3460_0 =>
+ (case ((spc_matches_prefix0 s3460_0)) of
+ SOME ((() , s3461_0)) =>
+ (case ((string_drop s3460_0 s3461_0)) of
+ s3462_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3462_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s3463_0)) =>
+ (case ((string_drop s3462_0 s3463_0)) of s_ => SOME (s, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3449_ : string -> maybe ((mword ty32 * string))*)
+
+val _ = Define `
+ ((s3449_:string ->((32)words$word#string)option) s3450_0=
+ (let s3451_0 = s3450_0 in
+ if ((string_startswith s3451_0 "illegal")) then
+ (case ((string_drop s3451_0 ((string_length "illegal")))) of
+ s3452_0 =>
+ (case ((spc_matches_prefix0 s3452_0)) of
+ SOME ((() , s3453_0)) =>
+ (case ((string_drop s3452_0 s3453_0)) of
+ s3454_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3454_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s3455_0)) =>
+ (case ((string_drop s3454_0 s3455_0)) of s_ => SOME (s, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3445_ : string -> maybe string*)
+
+val _ = Define `
+ ((s3445_:string ->(string)option) s3446_0=
+ (let s3447_0 = s3446_0 in
+ if ((string_startswith s3447_0 "uret")) then
+ (case ((string_drop s3447_0 ((string_length "uret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s3428_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s3428_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word#string)option) s3429_0=
+ ((case s3429_0 of
+ s3430_0 =>
+ (case ((csr_mnemonic_matches_prefix s3430_0)) of
+ SOME ((op, s3431_0)) =>
+ (case ((string_drop s3430_0 s3431_0)) of
+ s3432_0 =>
+ (case ((spc_matches_prefix0 s3432_0)) of
+ SOME ((() , s3433_0)) =>
+ (case ((string_drop s3432_0 s3433_0)) of
+ s3434_0 =>
+ (case ((reg_name_matches_prefix s3434_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3435_0)) =>
+ (case ((string_drop s3434_0 s3435_0)) of
+ s3436_0 =>
+ (case ((sep_matches_prefix s3436_0)) of
+ SOME ((() , s3437_0)) =>
+ (case ((string_drop s3436_0 s3437_0)) of
+ s3438_0 =>
+ (case ((reg_name_matches_prefix s3438_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3439_0)) =>
+ (case ((string_drop s3438_0 s3439_0)) of
+ s3440_0 =>
+ (case ((sep_matches_prefix s3440_0)) of
+ SOME ((() , s3441_0)) =>
+ (case ((string_drop s3440_0 s3441_0)) of
+ s3442_0 =>
+ (case ((csr_name_map_matches_prefix s3442_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s3443_0)) =>
+ (case ((string_drop s3442_0 s3443_0)) of
+ s_ => SOME (op, rd, rs1, csr, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3410_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s3410_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word#string)option) s3411_0=
+ ((case s3411_0 of
+ s3412_0 =>
+ (case ((csr_mnemonic_matches_prefix s3412_0)) of
+ SOME ((op, s3413_0)) =>
+ let s3414_0 = (string_drop s3412_0 s3413_0) in
+ if ((string_startswith s3414_0 "i")) then
+ (case ((string_drop s3414_0 ((string_length "i")))) of
+ s3415_0 =>
+ (case ((spc_matches_prefix0 s3415_0)) of
+ SOME ((() , s3416_0)) =>
+ (case ((string_drop s3415_0 s3416_0)) of
+ s3417_0 =>
+ (case ((reg_name_matches_prefix s3417_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3418_0)) =>
+ (case ((string_drop s3417_0 s3418_0)) of
+ s3419_0 =>
+ (case ((sep_matches_prefix s3419_0)) of
+ SOME ((() , s3420_0)) =>
+ (case ((string_drop s3419_0 s3420_0)) of
+ s3421_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s3421_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3422_0)) =>
+ (case ((string_drop s3421_0 s3422_0)) of
+ s3423_0 =>
+ (case ((sep_matches_prefix s3423_0)) of
+ SOME ((() , s3424_0)) =>
+ (case ((string_drop s3423_0 s3424_0)) of
+ s3425_0 =>
+ (case ((csr_name_map_matches_prefix s3425_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s3426_0)) =>
+ (case ((string_drop s3425_0 s3426_0)) of
+ s_ => SOME (op, rd, rs1, csr, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3391_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3391_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3392_0=
+ (let s3393_0 = s3392_0 in
+ if ((string_startswith s3393_0 "rem")) then
+ (case ((string_drop s3393_0 ((string_length "rem")))) of
+ s3394_0 =>
+ (case ((maybe_not_u_matches_prefix s3394_0)) of
+ SOME ((s, s3395_0)) =>
+ let s3396_0 = (string_drop s3394_0 s3395_0) in
+ if ((string_startswith s3396_0 "w")) then
+ (case ((string_drop s3396_0 ((string_length "w")))) of
+ s3397_0 =>
+ (case ((spc_matches_prefix0 s3397_0)) of
+ SOME ((() , s3398_0)) =>
+ (case ((string_drop s3397_0 s3398_0)) of
+ s3399_0 =>
+ (case ((reg_name_matches_prefix s3399_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3400_0)) =>
+ (case ((string_drop s3399_0 s3400_0)) of
+ s3401_0 =>
+ (case ((sep_matches_prefix s3401_0)) of
+ SOME ((() , s3402_0)) =>
+ (case ((string_drop s3401_0 s3402_0)) of
+ s3403_0 =>
+ (case ((reg_name_matches_prefix s3403_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3404_0)) =>
+ (case ((string_drop s3403_0 s3404_0)) of
+ s3405_0 =>
+ (case ((sep_matches_prefix s3405_0)) of
+ SOME ((() , s3406_0)) =>
+ (case ((string_drop s3405_0 s3406_0)) of
+ s3407_0 =>
+ (case ((reg_name_matches_prefix s3407_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3408_0)) =>
+ (case ((string_drop s3407_0 s3408_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3372_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3372_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3373_0=
+ (let s3374_0 = s3373_0 in
+ if ((string_startswith s3374_0 "div")) then
+ (case ((string_drop s3374_0 ((string_length "div")))) of
+ s3375_0 =>
+ (case ((maybe_not_u_matches_prefix s3375_0)) of
+ SOME ((s, s3376_0)) =>
+ let s3377_0 = (string_drop s3375_0 s3376_0) in
+ if ((string_startswith s3377_0 "w")) then
+ (case ((string_drop s3377_0 ((string_length "w")))) of
+ s3378_0 =>
+ (case ((spc_matches_prefix0 s3378_0)) of
+ SOME ((() , s3379_0)) =>
+ (case ((string_drop s3378_0 s3379_0)) of
+ s3380_0 =>
+ (case ((reg_name_matches_prefix s3380_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3381_0)) =>
+ (case ((string_drop s3380_0 s3381_0)) of
+ s3382_0 =>
+ (case ((sep_matches_prefix s3382_0)) of
+ SOME ((() , s3383_0)) =>
+ (case ((string_drop s3382_0 s3383_0)) of
+ s3384_0 =>
+ (case ((reg_name_matches_prefix s3384_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3385_0)) =>
+ (case ((string_drop s3384_0 s3385_0)) of
+ s3386_0 =>
+ (case ((sep_matches_prefix s3386_0)) of
+ SOME ((() , s3387_0)) =>
+ (case ((string_drop s3386_0 s3387_0)) of
+ s3388_0 =>
+ (case ((reg_name_matches_prefix s3388_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3389_0)) =>
+ (case ((string_drop s3388_0 s3389_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3356_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3356_:string ->((5)words$word#(5)words$word#(5)words$word#string)option) s3357_0=
+ (let s3358_0 = s3357_0 in
+ if ((string_startswith s3358_0 "mulw")) then
+ (case ((string_drop s3358_0 ((string_length "mulw")))) of
+ s3359_0 =>
+ (case ((spc_matches_prefix0 s3359_0)) of
+ SOME ((() , s3360_0)) =>
+ (case ((string_drop s3359_0 s3360_0)) of
+ s3361_0 =>
+ (case ((reg_name_matches_prefix s3361_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3362_0)) =>
+ (case ((string_drop s3361_0 s3362_0)) of
+ s3363_0 =>
+ (case ((sep_matches_prefix s3363_0)) of
+ SOME ((() , s3364_0)) =>
+ (case ((string_drop s3363_0 s3364_0)) of
+ s3365_0 =>
+ (case ((reg_name_matches_prefix s3365_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3366_0)) =>
+ (case ((string_drop s3365_0 s3366_0)) of
+ s3367_0 =>
+ (case ((sep_matches_prefix s3367_0)) of
+ SOME ((() , s3368_0)) =>
+ (case ((string_drop s3367_0 s3368_0)) of
+ s3369_0 =>
+ (case ((reg_name_matches_prefix s3369_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3370_0)) =>
+ (case ((string_drop s3369_0 s3370_0)) of s_ => SOME (rd, rs1, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3338_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3338_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3339_0=
+ (let s3340_0 = s3339_0 in
+ if ((string_startswith s3340_0 "rem")) then
+ (case ((string_drop s3340_0 ((string_length "rem")))) of
+ s3341_0 =>
+ (case ((maybe_not_u_matches_prefix s3341_0)) of
+ SOME ((s, s3342_0)) =>
+ (case ((string_drop s3341_0 s3342_0)) of
+ s3343_0 =>
+ (case ((spc_matches_prefix0 s3343_0)) of
+ SOME ((() , s3344_0)) =>
+ (case ((string_drop s3343_0 s3344_0)) of
+ s3345_0 =>
+ (case ((reg_name_matches_prefix s3345_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3346_0)) =>
+ (case ((string_drop s3345_0 s3346_0)) of
+ s3347_0 =>
+ (case ((sep_matches_prefix s3347_0)) of
+ SOME ((() , s3348_0)) =>
+ (case ((string_drop s3347_0 s3348_0)) of
+ s3349_0 =>
+ (case ((reg_name_matches_prefix s3349_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3350_0)) =>
+ (case ((string_drop s3349_0 s3350_0)) of
+ s3351_0 =>
+ (case ((sep_matches_prefix s3351_0)) of
+ SOME ((() , s3352_0)) =>
+ (case ((string_drop s3351_0 s3352_0)) of
+ s3353_0 =>
+ (case ((reg_name_matches_prefix s3353_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3354_0)) =>
+ (case ((string_drop s3353_0 s3354_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3320_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3320_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3321_0=
+ (let s3322_0 = s3321_0 in
+ if ((string_startswith s3322_0 "div")) then
+ (case ((string_drop s3322_0 ((string_length "div")))) of
+ s3323_0 =>
+ (case ((maybe_not_u_matches_prefix s3323_0)) of
+ SOME ((s, s3324_0)) =>
+ (case ((string_drop s3323_0 s3324_0)) of
+ s3325_0 =>
+ (case ((spc_matches_prefix0 s3325_0)) of
+ SOME ((() , s3326_0)) =>
+ (case ((string_drop s3325_0 s3326_0)) of
+ s3327_0 =>
+ (case ((reg_name_matches_prefix s3327_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3328_0)) =>
+ (case ((string_drop s3327_0 s3328_0)) of
+ s3329_0 =>
+ (case ((sep_matches_prefix s3329_0)) of
+ SOME ((() , s3330_0)) =>
+ (case ((string_drop s3329_0 s3330_0)) of
+ s3331_0 =>
+ (case ((reg_name_matches_prefix s3331_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3332_0)) =>
+ (case ((string_drop s3331_0 s3332_0)) of
+ s3333_0 =>
+ (case ((sep_matches_prefix s3333_0)) of
+ SOME ((() , s3334_0)) =>
+ (case ((string_drop s3333_0 s3334_0)) of
+ s3335_0 =>
+ (case ((reg_name_matches_prefix s3335_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3336_0)) =>
+ (case ((string_drop s3335_0 s3336_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3303_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3303_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3304_0=
+ ((case s3304_0 of
+ s3305_0 =>
+ (case ((mul_mnemonic_matches_prefix s3305_0)) of
+ SOME (((high, signed1, signed2), s3306_0)) =>
+ (case ((string_drop s3305_0 s3306_0)) of
+ s3307_0 =>
+ (case ((spc_matches_prefix0 s3307_0)) of
+ SOME ((() , s3308_0)) =>
+ (case ((string_drop s3307_0 s3308_0)) of
+ s3309_0 =>
+ (case ((reg_name_matches_prefix s3309_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3310_0)) =>
+ (case ((string_drop s3309_0 s3310_0)) of
+ s3311_0 =>
+ (case ((sep_matches_prefix s3311_0)) of
+ SOME ((() , s3312_0)) =>
+ (case ((string_drop s3311_0 s3312_0)) of
+ s3313_0 =>
+ (case ((reg_name_matches_prefix s3313_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3314_0)) =>
+ (case ((string_drop s3313_0 s3314_0)) of
+ s3315_0 =>
+ (case ((sep_matches_prefix s3315_0)) of
+ SOME ((() , s3316_0)) =>
+ (case ((string_drop s3315_0 s3316_0)) of
+ s3317_0 =>
+ (case ((reg_name_matches_prefix s3317_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3318_0)) =>
+ (case ((string_drop s3317_0 s3318_0)) of
+ s_ => SOME (high, signed1, signed2, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3291_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3291_:string ->((5)words$word#(5)words$word#string)option) s3292_0=
+ (let s3293_0 = s3292_0 in
+ if ((string_startswith s3293_0 "c.add")) then
+ (case ((string_drop s3293_0 ((string_length "c.add")))) of
+ s3294_0 =>
+ (case ((spc_matches_prefix0 s3294_0)) of
+ SOME ((() , s3295_0)) =>
+ (case ((string_drop s3294_0 s3295_0)) of
+ s3296_0 =>
+ (case ((reg_name_matches_prefix s3296_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3297_0)) =>
+ (case ((string_drop s3296_0 s3297_0)) of
+ s3298_0 =>
+ (case ((sep_matches_prefix s3298_0)) of
+ SOME ((() , s3299_0)) =>
+ (case ((string_drop s3298_0 s3299_0)) of
+ s3300_0 =>
+ (case ((reg_name_matches_prefix s3300_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3301_0)) =>
+ (case ((string_drop s3300_0 s3301_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3287_ : string -> maybe string*)
+
+val _ = Define `
+ ((s3287_:string ->(string)option) s3288_0=
+ (let s3289_0 = s3288_0 in
+ if ((string_startswith s3289_0 "c.ebreak")) then
+ (case ((string_drop s3289_0 ((string_length "c.ebreak")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s3275_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3275_:string ->((5)words$word#(5)words$word#string)option) s3276_0=
+ (let s3277_0 = s3276_0 in
+ if ((string_startswith s3277_0 "c.mv")) then
+ (case ((string_drop s3277_0 ((string_length "c.mv")))) of
+ s3278_0 =>
+ (case ((spc_matches_prefix0 s3278_0)) of
+ SOME ((() , s3279_0)) =>
+ (case ((string_drop s3278_0 s3279_0)) of
+ s3280_0 =>
+ (case ((reg_name_matches_prefix s3280_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3281_0)) =>
+ (case ((string_drop s3280_0 s3281_0)) of
+ s3282_0 =>
+ (case ((sep_matches_prefix s3282_0)) of
+ SOME ((() , s3283_0)) =>
+ (case ((string_drop s3282_0 s3283_0)) of
+ s3284_0 =>
+ (case ((reg_name_matches_prefix s3284_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3285_0)) =>
+ (case ((string_drop s3284_0 s3285_0)) of s_ => SOME (rd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3267_ : string -> maybe ((mword ty5 * string))*)
+
+val _ = Define `
+ ((s3267_:string ->((5)words$word#string)option) s3268_0=
+ (let s3269_0 = s3268_0 in
+ if ((string_startswith s3269_0 "c.jalr")) then
+ (case ((string_drop s3269_0 ((string_length "c.jalr")))) of
+ s3270_0 =>
+ (case ((spc_matches_prefix0 s3270_0)) of
+ SOME ((() , s3271_0)) =>
+ (case ((string_drop s3270_0 s3271_0)) of
+ s3272_0 =>
+ (case ((reg_name_matches_prefix s3272_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3273_0)) =>
+ (case ((string_drop s3272_0 s3273_0)) of s_ => SOME (rs1, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3259_ : string -> maybe ((mword ty5 * string))*)
+
+val _ = Define `
+ ((s3259_:string ->((5)words$word#string)option) s3260_0=
+ (let s3261_0 = s3260_0 in
+ if ((string_startswith s3261_0 "c.jr")) then
+ (case ((string_drop s3261_0 ((string_length "c.jr")))) of
+ s3262_0 =>
+ (case ((spc_matches_prefix0 s3262_0)) of
+ SOME ((() , s3263_0)) =>
+ (case ((string_drop s3262_0 s3263_0)) of
+ s3264_0 =>
+ (case ((reg_name_matches_prefix s3264_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3265_0)) =>
+ (case ((string_drop s3264_0 s3265_0)) of s_ => SOME (rs1, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3247_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3247_:string ->((5)words$word#(6)words$word#string)option) s3248_0=
+ (let s3249_0 = s3248_0 in
+ if ((string_startswith s3249_0 "c.sdsp")) then
+ (case ((string_drop s3249_0 ((string_length "c.sdsp")))) of
+ s3250_0 =>
+ (case ((spc_matches_prefix0 s3250_0)) of
+ SOME ((() , s3251_0)) =>
+ (case ((string_drop s3250_0 s3251_0)) of
+ s3252_0 =>
+ (case ((reg_name_matches_prefix s3252_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3253_0)) =>
+ (case ((string_drop s3252_0 s3253_0)) of
+ s3254_0 =>
+ (case ((sep_matches_prefix s3254_0)) of
+ SOME ((() , s3255_0)) =>
+ (case ((string_drop s3254_0 s3255_0)) of
+ s3256_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3256_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3257_0)) =>
+ (case ((string_drop s3256_0 s3257_0)) of s_ => SOME (rs2, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3235_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3235_:string ->((5)words$word#(6)words$word#string)option) s3236_0=
+ (let s3237_0 = s3236_0 in
+ if ((string_startswith s3237_0 "c.swsp")) then
+ (case ((string_drop s3237_0 ((string_length "c.swsp")))) of
+ s3238_0 =>
+ (case ((spc_matches_prefix0 s3238_0)) of
+ SOME ((() , s3239_0)) =>
+ (case ((string_drop s3238_0 s3239_0)) of
+ s3240_0 =>
+ (case ((reg_name_matches_prefix s3240_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3241_0)) =>
+ (case ((string_drop s3240_0 s3241_0)) of
+ s3242_0 =>
+ (case ((sep_matches_prefix s3242_0)) of
+ SOME ((() , s3243_0)) =>
+ (case ((string_drop s3242_0 s3243_0)) of
+ s3244_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3244_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3245_0)) =>
+ (case ((string_drop s3244_0 s3245_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3223_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3223_:string ->((5)words$word#(6)words$word#string)option) s3224_0=
+ (let s3225_0 = s3224_0 in
+ if ((string_startswith s3225_0 "c.ldsp")) then
+ (case ((string_drop s3225_0 ((string_length "c.ldsp")))) of
+ s3226_0 =>
+ (case ((spc_matches_prefix0 s3226_0)) of
+ SOME ((() , s3227_0)) =>
+ (case ((string_drop s3226_0 s3227_0)) of
+ s3228_0 =>
+ (case ((reg_name_matches_prefix s3228_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3229_0)) =>
+ (case ((string_drop s3228_0 s3229_0)) of
+ s3230_0 =>
+ (case ((sep_matches_prefix s3230_0)) of
+ SOME ((() , s3231_0)) =>
+ (case ((string_drop s3230_0 s3231_0)) of
+ s3232_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3232_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3233_0)) =>
+ (case ((string_drop s3232_0 s3233_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3211_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3211_:string ->((5)words$word#(6)words$word#string)option) s3212_0=
+ (let s3213_0 = s3212_0 in
+ if ((string_startswith s3213_0 "c.lwsp")) then
+ (case ((string_drop s3213_0 ((string_length "c.lwsp")))) of
+ s3214_0 =>
+ (case ((spc_matches_prefix0 s3214_0)) of
+ SOME ((() , s3215_0)) =>
+ (case ((string_drop s3214_0 s3215_0)) of
+ s3216_0 =>
+ (case ((reg_name_matches_prefix s3216_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3217_0)) =>
+ (case ((string_drop s3216_0 s3217_0)) of
+ s3218_0 =>
+ (case ((sep_matches_prefix s3218_0)) of
+ SOME ((() , s3219_0)) =>
+ (case ((string_drop s3218_0 s3219_0)) of
+ s3220_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3220_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3221_0)) =>
+ (case ((string_drop s3220_0 s3221_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3199_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3199_:string ->((5)words$word#(6)words$word#string)option) s3200_0=
+ (let s3201_0 = s3200_0 in
+ if ((string_startswith s3201_0 "c.slli")) then
+ (case ((string_drop s3201_0 ((string_length "c.slli")))) of
+ s3202_0 =>
+ (case ((spc_matches_prefix0 s3202_0)) of
+ SOME ((() , s3203_0)) =>
+ (case ((string_drop s3202_0 s3203_0)) of
+ s3204_0 =>
+ (case ((reg_name_matches_prefix s3204_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3205_0)) =>
+ (case ((string_drop s3204_0 s3205_0)) of
+ s3206_0 =>
+ (case ((sep_matches_prefix s3206_0)) of
+ SOME ((() , s3207_0)) =>
+ (case ((string_drop s3206_0 s3207_0)) of
+ s3208_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3208_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3209_0)) =>
+ (case ((string_drop s3208_0 s3209_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3187_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s3187_:string ->((3)words$word#(8)words$word#string)option) s3188_0=
+ (let s3189_0 = s3188_0 in
+ if ((string_startswith s3189_0 "c.bnez")) then
+ (case ((string_drop s3189_0 ((string_length "c.bnez")))) of
+ s3190_0 =>
+ (case ((spc_matches_prefix0 s3190_0)) of
+ SOME ((() , s3191_0)) =>
+ (case ((string_drop s3190_0 s3191_0)) of
+ s3192_0 =>
+ (case ((creg_name_matches_prefix s3192_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s3193_0)) =>
+ (case ((string_drop s3192_0 s3193_0)) of
+ s3194_0 =>
+ (case ((sep_matches_prefix s3194_0)) of
+ SOME ((() , s3195_0)) =>
+ (case ((string_drop s3194_0 s3195_0)) of
+ s3196_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3196_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s3197_0)) =>
+ (case ((string_drop s3196_0 s3197_0)) of s_ => SOME (rs, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3175_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s3175_:string ->((3)words$word#(8)words$word#string)option) s3176_0=
+ (let s3177_0 = s3176_0 in
+ if ((string_startswith s3177_0 "c.beqz")) then
+ (case ((string_drop s3177_0 ((string_length "c.beqz")))) of
+ s3178_0 =>
+ (case ((spc_matches_prefix0 s3178_0)) of
+ SOME ((() , s3179_0)) =>
+ (case ((string_drop s3178_0 s3179_0)) of
+ s3180_0 =>
+ (case ((creg_name_matches_prefix s3180_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s3181_0)) =>
+ (case ((string_drop s3180_0 s3181_0)) of
+ s3182_0 =>
+ (case ((sep_matches_prefix s3182_0)) of
+ SOME ((() , s3183_0)) =>
+ (case ((string_drop s3182_0 s3183_0)) of
+ s3184_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3184_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s3185_0)) =>
+ (case ((string_drop s3184_0 s3185_0)) of s_ => SOME (rs, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3167_ : string -> maybe ((mword ty11 * string))*)
+
+val _ = Define `
+ ((s3167_:string ->((11)words$word#string)option) s3168_0=
+ (let s3169_0 = s3168_0 in
+ if ((string_startswith s3169_0 "c.j")) then
+ (case ((string_drop s3169_0 ((string_length "c.j")))) of
+ s3170_0 =>
+ (case ((spc_matches_prefix0 s3170_0)) of
+ SOME ((() , s3171_0)) =>
+ (case ((string_drop s3170_0 s3171_0)) of
+ s3172_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3172_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s3173_0)) =>
+ (case ((string_drop s3172_0 s3173_0)) of s_ => SOME (imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3155_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3155_:string ->((3)words$word#(3)words$word#string)option) s3156_0=
+ (let s3157_0 = s3156_0 in
+ if ((string_startswith s3157_0 "c.addw")) then
+ (case ((string_drop s3157_0 ((string_length "c.addw")))) of
+ s3158_0 =>
+ (case ((spc_matches_prefix0 s3158_0)) of
+ SOME ((() , s3159_0)) =>
+ (case ((string_drop s3158_0 s3159_0)) of
+ s3160_0 =>
+ (case ((creg_name_matches_prefix s3160_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3161_0)) =>
+ (case ((string_drop s3160_0 s3161_0)) of
+ s3162_0 =>
+ (case ((sep_matches_prefix s3162_0)) of
+ SOME ((() , s3163_0)) =>
+ (case ((string_drop s3162_0 s3163_0)) of
+ s3164_0 =>
+ (case ((creg_name_matches_prefix s3164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3165_0)) =>
+ (case ((string_drop s3164_0 s3165_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3143_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3143_:string ->((3)words$word#(3)words$word#string)option) s3144_0=
+ (let s3145_0 = s3144_0 in
+ if ((string_startswith s3145_0 "c.subw")) then
+ (case ((string_drop s3145_0 ((string_length "c.subw")))) of
+ s3146_0 =>
+ (case ((spc_matches_prefix0 s3146_0)) of
+ SOME ((() , s3147_0)) =>
+ (case ((string_drop s3146_0 s3147_0)) of
+ s3148_0 =>
+ (case ((creg_name_matches_prefix s3148_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3149_0)) =>
+ (case ((string_drop s3148_0 s3149_0)) of
+ s3150_0 =>
+ (case ((sep_matches_prefix s3150_0)) of
+ SOME ((() , s3151_0)) =>
+ (case ((string_drop s3150_0 s3151_0)) of
+ s3152_0 =>
+ (case ((creg_name_matches_prefix s3152_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3153_0)) =>
+ (case ((string_drop s3152_0 s3153_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3131_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3131_:string ->((3)words$word#(3)words$word#string)option) s3132_0=
+ (let s3133_0 = s3132_0 in
+ if ((string_startswith s3133_0 "c.and")) then
+ (case ((string_drop s3133_0 ((string_length "c.and")))) of
+ s3134_0 =>
+ (case ((spc_matches_prefix0 s3134_0)) of
+ SOME ((() , s3135_0)) =>
+ (case ((string_drop s3134_0 s3135_0)) of
+ s3136_0 =>
+ (case ((creg_name_matches_prefix s3136_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3137_0)) =>
+ (case ((string_drop s3136_0 s3137_0)) of
+ s3138_0 =>
+ (case ((sep_matches_prefix s3138_0)) of
+ SOME ((() , s3139_0)) =>
+ (case ((string_drop s3138_0 s3139_0)) of
+ s3140_0 =>
+ (case ((creg_name_matches_prefix s3140_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3141_0)) =>
+ (case ((string_drop s3140_0 s3141_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3119_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3119_:string ->((3)words$word#(3)words$word#string)option) s3120_0=
+ (let s3121_0 = s3120_0 in
+ if ((string_startswith s3121_0 "c.or")) then
+ (case ((string_drop s3121_0 ((string_length "c.or")))) of
+ s3122_0 =>
+ (case ((spc_matches_prefix0 s3122_0)) of
+ SOME ((() , s3123_0)) =>
+ (case ((string_drop s3122_0 s3123_0)) of
+ s3124_0 =>
+ (case ((creg_name_matches_prefix s3124_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3125_0)) =>
+ (case ((string_drop s3124_0 s3125_0)) of
+ s3126_0 =>
+ (case ((sep_matches_prefix s3126_0)) of
+ SOME ((() , s3127_0)) =>
+ (case ((string_drop s3126_0 s3127_0)) of
+ s3128_0 =>
+ (case ((creg_name_matches_prefix s3128_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3129_0)) =>
+ (case ((string_drop s3128_0 s3129_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3107_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3107_:string ->((3)words$word#(3)words$word#string)option) s3108_0=
+ (let s3109_0 = s3108_0 in
+ if ((string_startswith s3109_0 "c.xor")) then
+ (case ((string_drop s3109_0 ((string_length "c.xor")))) of
+ s3110_0 =>
+ (case ((spc_matches_prefix0 s3110_0)) of
+ SOME ((() , s3111_0)) =>
+ (case ((string_drop s3110_0 s3111_0)) of
+ s3112_0 =>
+ (case ((creg_name_matches_prefix s3112_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3113_0)) =>
+ (case ((string_drop s3112_0 s3113_0)) of
+ s3114_0 =>
+ (case ((sep_matches_prefix s3114_0)) of
+ SOME ((() , s3115_0)) =>
+ (case ((string_drop s3114_0 s3115_0)) of
+ s3116_0 =>
+ (case ((creg_name_matches_prefix s3116_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3117_0)) =>
+ (case ((string_drop s3116_0 s3117_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3095_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3095_:string ->((3)words$word#(3)words$word#string)option) s3096_0=
+ (let s3097_0 = s3096_0 in
+ if ((string_startswith s3097_0 "c.sub")) then
+ (case ((string_drop s3097_0 ((string_length "c.sub")))) of
+ s3098_0 =>
+ (case ((spc_matches_prefix0 s3098_0)) of
+ SOME ((() , s3099_0)) =>
+ (case ((string_drop s3098_0 s3099_0)) of
+ s3100_0 =>
+ (case ((creg_name_matches_prefix s3100_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3101_0)) =>
+ (case ((string_drop s3100_0 s3101_0)) of
+ s3102_0 =>
+ (case ((sep_matches_prefix s3102_0)) of
+ SOME ((() , s3103_0)) =>
+ (case ((string_drop s3102_0 s3103_0)) of
+ s3104_0 =>
+ (case ((creg_name_matches_prefix s3104_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3105_0)) =>
+ (case ((string_drop s3104_0 s3105_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3083_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3083_:string ->((3)words$word#(6)words$word#string)option) s3084_0=
+ (let s3085_0 = s3084_0 in
+ if ((string_startswith s3085_0 "c.andi")) then
+ (case ((string_drop s3085_0 ((string_length "c.andi")))) of
+ s3086_0 =>
+ (case ((spc_matches_prefix0 s3086_0)) of
+ SOME ((() , s3087_0)) =>
+ (case ((string_drop s3086_0 s3087_0)) of
+ s3088_0 =>
+ (case ((creg_name_matches_prefix s3088_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3089_0)) =>
+ (case ((string_drop s3088_0 s3089_0)) of
+ s3090_0 =>
+ (case ((sep_matches_prefix s3090_0)) of
+ SOME ((() , s3091_0)) =>
+ (case ((string_drop s3090_0 s3091_0)) of
+ s3092_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3092_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3093_0)) =>
+ (case ((string_drop s3092_0 s3093_0)) of s_ => SOME (rsd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3071_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3071_:string ->((3)words$word#(6)words$word#string)option) s3072_0=
+ (let s3073_0 = s3072_0 in
+ if ((string_startswith s3073_0 "c.srai")) then
+ (case ((string_drop s3073_0 ((string_length "c.srai")))) of
+ s3074_0 =>
+ (case ((spc_matches_prefix0 s3074_0)) of
+ SOME ((() , s3075_0)) =>
+ (case ((string_drop s3074_0 s3075_0)) of
+ s3076_0 =>
+ (case ((creg_name_matches_prefix s3076_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3077_0)) =>
+ (case ((string_drop s3076_0 s3077_0)) of
+ s3078_0 =>
+ (case ((sep_matches_prefix s3078_0)) of
+ SOME ((() , s3079_0)) =>
+ (case ((string_drop s3078_0 s3079_0)) of
+ s3080_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3080_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3081_0)) =>
+ (case ((string_drop s3080_0 s3081_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3059_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3059_:string ->((3)words$word#(6)words$word#string)option) s3060_0=
+ (let s3061_0 = s3060_0 in
+ if ((string_startswith s3061_0 "c.srli")) then
+ (case ((string_drop s3061_0 ((string_length "c.srli")))) of
+ s3062_0 =>
+ (case ((spc_matches_prefix0 s3062_0)) of
+ SOME ((() , s3063_0)) =>
+ (case ((string_drop s3062_0 s3063_0)) of
+ s3064_0 =>
+ (case ((creg_name_matches_prefix s3064_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3065_0)) =>
+ (case ((string_drop s3064_0 s3065_0)) of
+ s3066_0 =>
+ (case ((sep_matches_prefix s3066_0)) of
+ SOME ((() , s3067_0)) =>
+ (case ((string_drop s3066_0 s3067_0)) of
+ s3068_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3068_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3069_0)) =>
+ (case ((string_drop s3068_0 s3069_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3047_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3047_:string ->((5)words$word#(6)words$word#string)option) s3048_0=
+ (let s3049_0 = s3048_0 in
+ if ((string_startswith s3049_0 "c.lui")) then
+ (case ((string_drop s3049_0 ((string_length "c.lui")))) of
+ s3050_0 =>
+ (case ((spc_matches_prefix0 s3050_0)) of
+ SOME ((() , s3051_0)) =>
+ (case ((string_drop s3050_0 s3051_0)) of
+ s3052_0 =>
+ (case ((reg_name_matches_prefix s3052_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3053_0)) =>
+ (case ((string_drop s3052_0 s3053_0)) of
+ s3054_0 =>
+ (case ((sep_matches_prefix s3054_0)) of
+ SOME ((() , s3055_0)) =>
+ (case ((string_drop s3054_0 s3055_0)) of
+ s3056_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3056_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3057_0)) =>
+ (case ((string_drop s3056_0 s3057_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3039_ : string -> maybe ((mword ty6 * string))*)
+
+val _ = Define `
+ ((s3039_:string ->((6)words$word#string)option) s3040_0=
+ (let s3041_0 = s3040_0 in
+ if ((string_startswith s3041_0 "c.addi16sp")) then
+ (case ((string_drop s3041_0 ((string_length "c.addi16sp")))) of
+ s3042_0 =>
+ (case ((spc_matches_prefix0 s3042_0)) of
+ SOME ((() , s3043_0)) =>
+ (case ((string_drop s3042_0 s3043_0)) of
+ s3044_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3044_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3045_0)) =>
+ (case ((string_drop s3044_0 s3045_0)) of s_ => SOME (imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3027_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3027_:string ->((5)words$word#(6)words$word#string)option) s3028_0=
+ (let s3029_0 = s3028_0 in
+ if ((string_startswith s3029_0 "c.li")) then
+ (case ((string_drop s3029_0 ((string_length "c.li")))) of
+ s3030_0 =>
+ (case ((spc_matches_prefix0 s3030_0)) of
+ SOME ((() , s3031_0)) =>
+ (case ((string_drop s3030_0 s3031_0)) of
+ s3032_0 =>
+ (case ((reg_name_matches_prefix s3032_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3033_0)) =>
+ (case ((string_drop s3032_0 s3033_0)) of
+ s3034_0 =>
+ (case ((sep_matches_prefix s3034_0)) of
+ SOME ((() , s3035_0)) =>
+ (case ((string_drop s3034_0 s3035_0)) of
+ s3036_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3036_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3037_0)) =>
+ (case ((string_drop s3036_0 s3037_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3015_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3015_:string ->((5)words$word#(6)words$word#string)option) s3016_0=
+ (let s3017_0 = s3016_0 in
+ if ((string_startswith s3017_0 "c.addiw")) then
+ (case ((string_drop s3017_0 ((string_length "c.addiw")))) of
+ s3018_0 =>
+ (case ((spc_matches_prefix0 s3018_0)) of
+ SOME ((() , s3019_0)) =>
+ (case ((string_drop s3018_0 s3019_0)) of
+ s3020_0 =>
+ (case ((reg_name_matches_prefix s3020_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3021_0)) =>
+ (case ((string_drop s3020_0 s3021_0)) of
+ s3022_0 =>
+ (case ((sep_matches_prefix s3022_0)) of
+ SOME ((() , s3023_0)) =>
+ (case ((string_drop s3022_0 s3023_0)) of
+ s3024_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3024_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3025_0)) =>
+ (case ((string_drop s3024_0 s3025_0)) of s_ => SOME (rsd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3007_ : string -> maybe ((mword ty11 * string))*)
+
+val _ = Define `
+ ((s3007_:string ->((11)words$word#string)option) s3008_0=
+ (let s3009_0 = s3008_0 in
+ if ((string_startswith s3009_0 "c.jal")) then
+ (case ((string_drop s3009_0 ((string_length "c.jal")))) of
+ s3010_0 =>
+ (case ((spc_matches_prefix0 s3010_0)) of
+ SOME ((() , s3011_0)) =>
+ (case ((string_drop s3010_0 s3011_0)) of
+ s3012_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3012_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__826, s3013_0)) =>
+ if (((((subrange_vec_dec v__826 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__826 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__826 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ (case ((string_drop s3012_0 s3013_0)) of s_ => SOME (imm, s_) ) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2995_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s2995_:string ->((5)words$word#(6)words$word#string)option) s2996_0=
+ (let s2997_0 = s2996_0 in
+ if ((string_startswith s2997_0 "c.addi")) then
+ (case ((string_drop s2997_0 ((string_length "c.addi")))) of
+ s2998_0 =>
+ (case ((spc_matches_prefix0 s2998_0)) of
+ SOME ((() , s2999_0)) =>
+ (case ((string_drop s2998_0 s2999_0)) of
+ s3000_0 =>
+ (case ((reg_name_matches_prefix s3000_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3001_0)) =>
+ (case ((string_drop s3000_0 s3001_0)) of
+ s3002_0 =>
+ (case ((sep_matches_prefix s3002_0)) of
+ SOME ((() , s3003_0)) =>
+ (case ((string_drop s3002_0 s3003_0)) of
+ s3004_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3004_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s3005_0)) =>
+ (case ((string_drop s3004_0 s3005_0)) of s_ => SOME (rsd, nzi, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2979_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2979_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2980_0=
+ (let s2981_0 = s2980_0 in
+ if ((string_startswith s2981_0 "c.sd")) then
+ (case ((string_drop s2981_0 ((string_length "c.sd")))) of
+ s2982_0 =>
+ (case ((spc_matches_prefix0 s2982_0)) of
+ SOME ((() , s2983_0)) =>
+ (case ((string_drop s2982_0 s2983_0)) of
+ s2984_0 =>
+ (case ((creg_name_matches_prefix s2984_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2985_0)) =>
+ (case ((string_drop s2984_0 s2985_0)) of
+ s2986_0 =>
+ (case ((sep_matches_prefix s2986_0)) of
+ SOME ((() , s2987_0)) =>
+ (case ((string_drop s2986_0 s2987_0)) of
+ s2988_0 =>
+ (case ((creg_name_matches_prefix s2988_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2989_0)) =>
+ (case ((string_drop s2988_0 s2989_0)) of
+ s2990_0 =>
+ (case ((sep_matches_prefix s2990_0)) of
+ SOME ((() , s2991_0)) =>
+ (case ((string_drop s2990_0 s2991_0)) of
+ s2992_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2992_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__828, s2993_0)) =>
+ if (((((subrange_vec_dec v__828 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__828 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__828 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2992_0 s2993_0)) of
+ s_ => SOME (rsc1, rsc2, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2963_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2963_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2964_0=
+ (let s2965_0 = s2964_0 in
+ if ((string_startswith s2965_0 "c.sw")) then
+ (case ((string_drop s2965_0 ((string_length "c.sw")))) of
+ s2966_0 =>
+ (case ((spc_matches_prefix0 s2966_0)) of
+ SOME ((() , s2967_0)) =>
+ (case ((string_drop s2966_0 s2967_0)) of
+ s2968_0 =>
+ (case ((creg_name_matches_prefix s2968_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2969_0)) =>
+ (case ((string_drop s2968_0 s2969_0)) of
+ s2970_0 =>
+ (case ((sep_matches_prefix s2970_0)) of
+ SOME ((() , s2971_0)) =>
+ (case ((string_drop s2970_0 s2971_0)) of
+ s2972_0 =>
+ (case ((creg_name_matches_prefix s2972_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2973_0)) =>
+ (case ((string_drop s2972_0 s2973_0)) of
+ s2974_0 =>
+ (case ((sep_matches_prefix s2974_0)) of
+ SOME ((() , s2975_0)) =>
+ (case ((string_drop s2974_0 s2975_0)) of
+ s2976_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2976_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__830, s2977_0)) =>
+ if (((((subrange_vec_dec v__830 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__830 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__830 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2976_0 s2977_0)) of
+ s_ => SOME (rsc1, rsc2, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2947_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2947_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2948_0=
+ (let s2949_0 = s2948_0 in
+ if ((string_startswith s2949_0 "c.ld")) then
+ (case ((string_drop s2949_0 ((string_length "c.ld")))) of
+ s2950_0 =>
+ (case ((spc_matches_prefix0 s2950_0)) of
+ SOME ((() , s2951_0)) =>
+ (case ((string_drop s2950_0 s2951_0)) of
+ s2952_0 =>
+ (case ((creg_name_matches_prefix s2952_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2953_0)) =>
+ (case ((string_drop s2952_0 s2953_0)) of
+ s2954_0 =>
+ (case ((sep_matches_prefix s2954_0)) of
+ SOME ((() , s2955_0)) =>
+ (case ((string_drop s2954_0 s2955_0)) of
+ s2956_0 =>
+ (case ((creg_name_matches_prefix s2956_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2957_0)) =>
+ (case ((string_drop s2956_0 s2957_0)) of
+ s2958_0 =>
+ (case ((sep_matches_prefix s2958_0)) of
+ SOME ((() , s2959_0)) =>
+ (case ((string_drop s2958_0 s2959_0)) of
+ s2960_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2960_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__832, s2961_0)) =>
+ if (((((subrange_vec_dec v__832 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__832 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__832 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2960_0 s2961_0)) of
+ s_ => SOME (rdc, rsc, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2931_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2931_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2932_0=
+ (let s2933_0 = s2932_0 in
+ if ((string_startswith s2933_0 "c.lw")) then
+ (case ((string_drop s2933_0 ((string_length "c.lw")))) of
+ s2934_0 =>
+ (case ((spc_matches_prefix0 s2934_0)) of
+ SOME ((() , s2935_0)) =>
+ (case ((string_drop s2934_0 s2935_0)) of
+ s2936_0 =>
+ (case ((creg_name_matches_prefix s2936_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2937_0)) =>
+ (case ((string_drop s2936_0 s2937_0)) of
+ s2938_0 =>
+ (case ((sep_matches_prefix s2938_0)) of
+ SOME ((() , s2939_0)) =>
+ (case ((string_drop s2938_0 s2939_0)) of
+ s2940_0 =>
+ (case ((creg_name_matches_prefix s2940_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2941_0)) =>
+ (case ((string_drop s2940_0 s2941_0)) of
+ s2942_0 =>
+ (case ((sep_matches_prefix s2942_0)) of
+ SOME ((() , s2943_0)) =>
+ (case ((string_drop s2942_0 s2943_0)) of
+ s2944_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2944_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__834, s2945_0)) =>
+ if (((((subrange_vec_dec v__834 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__834 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__834 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2944_0 s2945_0)) of
+ s_ => SOME (rdc, rsc, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2919_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s2919_:string ->((3)words$word#(8)words$word#string)option) s2920_0=
+ (let s2921_0 = s2920_0 in
+ if ((string_startswith s2921_0 "c.addi4spn")) then
+ (case ((string_drop s2921_0 ((string_length "c.addi4spn")))) of
+ s2922_0 =>
+ (case ((spc_matches_prefix0 s2922_0)) of
+ SOME ((() , s2923_0)) =>
+ (case ((string_drop s2922_0 s2923_0)) of
+ s2924_0 =>
+ (case ((creg_name_matches_prefix s2924_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2925_0)) =>
+ (case ((string_drop s2924_0 s2925_0)) of
+ s2926_0 =>
+ (case ((sep_matches_prefix s2926_0)) of
+ SOME ((() , s2927_0)) =>
+ (case ((string_drop s2926_0 s2927_0)) of
+ s2928_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2928_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__836, s2929_0)) =>
+ if (((((subrange_vec_dec v__836 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__836 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__836 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ (case ((string_drop s2928_0 s2929_0)) of s_ => SOME (rdc, nzimm, s_) )
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2915_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2915_:string ->(string)option) s2916_0=
+ (let s2917_0 = s2916_0 in
+ if ((string_startswith s2917_0 "c.nop")) then
+ (case ((string_drop s2917_0 ((string_length "c.nop")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2891_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2891_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s2892_0=
+ ((case s2892_0 of
+ s2893_0 =>
+ (case ((amo_mnemonic_matches_prefix s2893_0)) of
+ SOME ((op, s2894_0)) =>
+ let s2895_0 = (string_drop s2893_0 s2894_0) in
+ if ((string_startswith s2895_0 ".")) then
+ (case ((string_drop s2895_0 ((string_length ".")))) of
+ s2896_0 =>
+ (case ((size_mnemonic_matches_prefix s2896_0)) of
+ SOME ((width, s2897_0)) =>
+ (case ((string_drop s2896_0 s2897_0)) of
+ s2898_0 =>
+ (case ((maybe_aq_matches_prefix s2898_0)) of
+ SOME ((aq, s2899_0)) =>
+ (case ((string_drop s2898_0 s2899_0)) of
+ s2900_0 =>
+ (case ((maybe_rl_matches_prefix s2900_0)) of
+ SOME ((rl, s2901_0)) =>
+ (case ((string_drop s2900_0 s2901_0)) of
+ s2902_0 =>
+ (case ((spc_matches_prefix0 s2902_0)) of
+ SOME ((() , s2903_0)) =>
+ (case ((string_drop s2902_0 s2903_0)) of
+ s2904_0 =>
+ (case ((reg_name_matches_prefix s2904_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2905_0)) =>
+ (case ((string_drop s2904_0 s2905_0)) of
+ s2906_0 =>
+ (case ((sep_matches_prefix s2906_0)) of
+ SOME ((() , s2907_0)) =>
+ (case ((string_drop s2906_0 s2907_0)) of
+ s2908_0 =>
+ (case ((reg_name_matches_prefix s2908_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2909_0)) =>
+ (case ((string_drop s2908_0 s2909_0)) of
+ s2910_0 =>
+ (case ((sep_matches_prefix s2910_0)) of
+ SOME ((() , s2911_0)) =>
+ (case ((string_drop s2910_0 s2911_0)) of
+ s2912_0 =>
+ (case ((reg_name_matches_prefix s2912_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2913_0)) =>
+ (case ((string_drop s2912_0 s2913_0)) of
+ s_ =>
+ SOME (op, width, aq, rl, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2869_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2869_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s2870_0=
+ (let s2871_0 = s2870_0 in
+ if ((string_startswith s2871_0 "sc.")) then
+ (case ((string_drop s2871_0 ((string_length "sc.")))) of
+ s2872_0 =>
+ (case ((size_mnemonic_matches_prefix s2872_0)) of
+ SOME ((size1, s2873_0)) =>
+ (case ((string_drop s2872_0 s2873_0)) of
+ s2874_0 =>
+ (case ((maybe_aq_matches_prefix s2874_0)) of
+ SOME ((aq, s2875_0)) =>
+ (case ((string_drop s2874_0 s2875_0)) of
+ s2876_0 =>
+ (case ((maybe_rl_matches_prefix s2876_0)) of
+ SOME ((rl, s2877_0)) =>
+ (case ((string_drop s2876_0 s2877_0)) of
+ s2878_0 =>
+ (case ((spc_matches_prefix0 s2878_0)) of
+ SOME ((() , s2879_0)) =>
+ (case ((string_drop s2878_0 s2879_0)) of
+ s2880_0 =>
+ (case ((reg_name_matches_prefix s2880_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2881_0)) =>
+ (case ((string_drop s2880_0 s2881_0)) of
+ s2882_0 =>
+ (case ((sep_matches_prefix s2882_0)) of
+ SOME ((() , s2883_0)) =>
+ (case ((string_drop s2882_0 s2883_0)) of
+ s2884_0 =>
+ (case ((reg_name_matches_prefix s2884_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2885_0)) =>
+ (case ((string_drop s2884_0 s2885_0)) of
+ s2886_0 =>
+ (case ((sep_matches_prefix s2886_0)) of
+ SOME ((() , s2887_0)) =>
+ (case ((string_drop s2886_0 s2887_0)) of
+ s2888_0 =>
+ (case ((reg_name_matches_prefix s2888_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2889_0)) =>
+ (case ((string_drop s2888_0 s2889_0)) of
+ s_ =>
+ SOME (size1, aq, rl, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2851_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2851_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#string)option) s2852_0=
+ (let s2853_0 = s2852_0 in
+ if ((string_startswith s2853_0 "lr.")) then
+ (case ((string_drop s2853_0 ((string_length "lr.")))) of
+ s2854_0 =>
+ (case ((size_mnemonic_matches_prefix s2854_0)) of
+ SOME ((size1, s2855_0)) =>
+ (case ((string_drop s2854_0 s2855_0)) of
+ s2856_0 =>
+ (case ((maybe_aq_matches_prefix s2856_0)) of
+ SOME ((aq, s2857_0)) =>
+ (case ((string_drop s2856_0 s2857_0)) of
+ s2858_0 =>
+ (case ((maybe_rl_matches_prefix s2858_0)) of
+ SOME ((rl, s2859_0)) =>
+ (case ((string_drop s2858_0 s2859_0)) of
+ s2860_0 =>
+ (case ((spc_matches_prefix0 s2860_0)) of
+ SOME ((() , s2861_0)) =>
+ (case ((string_drop s2860_0 s2861_0)) of
+ s2862_0 =>
+ (case ((reg_name_matches_prefix s2862_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2863_0)) =>
+ (case ((string_drop s2862_0 s2863_0)) of
+ s2864_0 =>
+ (case ((sep_matches_prefix s2864_0)) of
+ SOME ((() , s2865_0)) =>
+ (case ((string_drop s2864_0 s2865_0)) of
+ s2866_0 =>
+ (case ((reg_name_matches_prefix s2866_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2867_0)) =>
+ (case ((string_drop s2866_0 s2867_0)) of
+ s_ => SOME (size1, aq, rl, rd, rs1, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2839_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2839_:string ->((5)words$word#(5)words$word#string)option) s2840_0=
+ (let s2841_0 = s2840_0 in
+ if ((string_startswith s2841_0 "sfence.vma")) then
+ (case ((string_drop s2841_0 ((string_length "sfence.vma")))) of
+ s2842_0 =>
+ (case ((spc_matches_prefix0 s2842_0)) of
+ SOME ((() , s2843_0)) =>
+ (case ((string_drop s2842_0 s2843_0)) of
+ s2844_0 =>
+ (case ((reg_name_matches_prefix s2844_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2845_0)) =>
+ (case ((string_drop s2844_0 s2845_0)) of
+ s2846_0 =>
+ (case ((sep_matches_prefix s2846_0)) of
+ SOME ((() , s2847_0)) =>
+ (case ((string_drop s2846_0 s2847_0)) of
+ s2848_0 =>
+ (case ((reg_name_matches_prefix s2848_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2849_0)) =>
+ (case ((string_drop s2848_0 s2849_0)) of s_ => SOME (rs1, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2835_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2835_:string ->(string)option) s2836_0=
+ (let s2837_0 = s2836_0 in
+ if ((string_startswith s2837_0 "wfi")) then
+ (case ((string_drop s2837_0 ((string_length "wfi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2831_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2831_:string ->(string)option) s2832_0=
+ (let s2833_0 = s2832_0 in
+ if ((string_startswith s2833_0 "ebreak")) then
+ (case ((string_drop s2833_0 ((string_length "ebreak")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s2827_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2827_:string ->(string)option) s2828_0=
+ (let s2829_0 = s2828_0 in
+ if ((string_startswith s2829_0 "sret")) then
+ (case ((string_drop s2829_0 ((string_length "sret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2823_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2823_:string ->(string)option) s2824_0=
+ (let s2825_0 = s2824_0 in
+ if ((string_startswith s2825_0 "mret")) then
+ (case ((string_drop s2825_0 ((string_length "mret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2819_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2819_:string ->(string)option) s2820_0=
+ (let s2821_0 = s2820_0 in
+ if ((string_startswith s2821_0 "ecall")) then
+ (case ((string_drop s2821_0 ((string_length "ecall")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2815_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2815_:string ->(string)option) s2816_0=
+ (let s2817_0 = s2816_0 in
+ if ((string_startswith s2817_0 "fence.i")) then
+ (case ((string_drop s2817_0 ((string_length "fence.i")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s2803_ : string -> maybe ((mword ty4 * mword ty4 * string))*)
+
+val _ = Define `
+ ((s2803_:string ->((4)words$word#(4)words$word#string)option) s2804_0=
+ (let s2805_0 = s2804_0 in
+ if ((string_startswith s2805_0 "fence.tso")) then
+ (case ((string_drop s2805_0 ((string_length "fence.tso")))) of
+ s2806_0 =>
+ (case ((spc_matches_prefix0 s2806_0)) of
+ SOME ((() , s2807_0)) =>
+ (case ((string_drop s2806_0 s2807_0)) of
+ s2808_0 =>
+ (case ((fence_bits_matches_prefix s2808_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s2809_0)) =>
+ (case ((string_drop s2808_0 s2809_0)) of
+ s2810_0 =>
+ (case ((sep_matches_prefix s2810_0)) of
+ SOME ((() , s2811_0)) =>
+ (case ((string_drop s2810_0 s2811_0)) of
+ s2812_0 =>
+ (case ((fence_bits_matches_prefix s2812_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s2813_0)) =>
+ (case ((string_drop s2812_0 s2813_0)) of s_ => SOME (pred, succ, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2791_ : string -> maybe ((mword ty4 * mword ty4 * string))*)
+
+val _ = Define `
+ ((s2791_:string ->((4)words$word#(4)words$word#string)option) s2792_0=
+ (let s2793_0 = s2792_0 in
+ if ((string_startswith s2793_0 "fence")) then
+ (case ((string_drop s2793_0 ((string_length "fence")))) of
+ s2794_0 =>
+ (case ((spc_matches_prefix0 s2794_0)) of
+ SOME ((() , s2795_0)) =>
+ (case ((string_drop s2794_0 s2795_0)) of
+ s2796_0 =>
+ (case ((fence_bits_matches_prefix s2796_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s2797_0)) =>
+ (case ((string_drop s2796_0 s2797_0)) of
+ s2798_0 =>
+ (case ((sep_matches_prefix s2798_0)) of
+ SOME ((() , s2799_0)) =>
+ (case ((string_drop s2798_0 s2799_0)) of
+ s2800_0 =>
+ (case ((fence_bits_matches_prefix s2800_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s2801_0)) =>
+ (case ((string_drop s2800_0 s2801_0)) of s_ => SOME (pred, succ, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2774_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2774_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word#string)option) s2775_0=
+ ((case s2775_0 of
+ s2776_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s2776_0)) of
+ SOME ((op, s2777_0)) =>
+ (case ((string_drop s2776_0 s2777_0)) of
+ s2778_0 =>
+ (case ((spc_matches_prefix0 s2778_0)) of
+ SOME ((() , s2779_0)) =>
+ (case ((string_drop s2778_0 s2779_0)) of
+ s2780_0 =>
+ (case ((reg_name_matches_prefix s2780_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2781_0)) =>
+ (case ((string_drop s2780_0 s2781_0)) of
+ s2782_0 =>
+ (case ((sep_matches_prefix s2782_0)) of
+ SOME ((() , s2783_0)) =>
+ (case ((string_drop s2782_0 s2783_0)) of
+ s2784_0 =>
+ (case ((reg_name_matches_prefix s2784_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2785_0)) =>
+ (case ((string_drop s2784_0 s2785_0)) of
+ s2786_0 =>
+ (case ((sep_matches_prefix s2786_0)) of
+ SOME ((() , s2787_0)) =>
+ (case ((string_drop s2786_0 s2787_0)) of
+ s2788_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2788_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s2789_0)) =>
+ (case ((string_drop s2788_0 s2789_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2757_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2757_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word#string)option) s2758_0=
+ ((case s2758_0 of
+ s2759_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s2759_0)) of
+ SOME ((op, s2760_0)) =>
+ (case ((string_drop s2759_0 s2760_0)) of
+ s2761_0 =>
+ (case ((spc_matches_prefix0 s2761_0)) of
+ SOME ((() , s2762_0)) =>
+ (case ((string_drop s2761_0 s2762_0)) of
+ s2763_0 =>
+ (case ((reg_name_matches_prefix s2763_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2764_0)) =>
+ (case ((string_drop s2763_0 s2764_0)) of
+ s2765_0 =>
+ (case ((sep_matches_prefix s2765_0)) of
+ SOME ((() , s2766_0)) =>
+ (case ((string_drop s2765_0 s2766_0)) of
+ s2767_0 =>
+ (case ((reg_name_matches_prefix s2767_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2768_0)) =>
+ (case ((string_drop s2767_0 s2768_0)) of
+ s2769_0 =>
+ (case ((sep_matches_prefix s2769_0)) of
+ SOME ((() , s2770_0)) =>
+ (case ((string_drop s2769_0 s2770_0)) of
+ s2771_0 =>
+ (case ((reg_name_matches_prefix s2771_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2772_0)) =>
+ (case ((string_drop s2771_0 s2772_0)) of
+ s_ => SOME (op, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2740_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2740_:string ->(sop#(5)words$word#(5)words$word#(5)words$word#string)option) s2741_0=
+ ((case s2741_0 of
+ s2742_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s2742_0)) of
+ SOME ((op, s2743_0)) =>
+ (case ((string_drop s2742_0 s2743_0)) of
+ s2744_0 =>
+ (case ((spc_matches_prefix0 s2744_0)) of
+ SOME ((() , s2745_0)) =>
+ (case ((string_drop s2744_0 s2745_0)) of
+ s2746_0 =>
+ (case ((reg_name_matches_prefix s2746_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2747_0)) =>
+ (case ((string_drop s2746_0 s2747_0)) of
+ s2748_0 =>
+ (case ((sep_matches_prefix s2748_0)) of
+ SOME ((() , s2749_0)) =>
+ (case ((string_drop s2748_0 s2749_0)) of
+ s2750_0 =>
+ (case ((reg_name_matches_prefix s2750_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2751_0)) =>
+ (case ((string_drop s2750_0 s2751_0)) of
+ s2752_0 =>
+ (case ((sep_matches_prefix s2752_0)) of
+ SOME ((() , s2753_0)) =>
+ (case ((string_drop s2752_0 s2753_0)) of
+ s2754_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2754_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s2755_0)) =>
+ (case ((string_drop s2754_0 s2755_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2724_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2724_:string ->((5)words$word#(5)words$word#(12)words$word#string)option) s2725_0=
+ (let s2726_0 = s2725_0 in
+ if ((string_startswith s2726_0 "addiw")) then
+ (case ((string_drop s2726_0 ((string_length "addiw")))) of
+ s2727_0 =>
+ (case ((spc_matches_prefix0 s2727_0)) of
+ SOME ((() , s2728_0)) =>
+ (case ((string_drop s2727_0 s2728_0)) of
+ s2729_0 =>
+ (case ((reg_name_matches_prefix s2729_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2730_0)) =>
+ (case ((string_drop s2729_0 s2730_0)) of
+ s2731_0 =>
+ (case ((sep_matches_prefix s2731_0)) of
+ SOME ((() , s2732_0)) =>
+ (case ((string_drop s2731_0 s2732_0)) of
+ s2733_0 =>
+ (case ((reg_name_matches_prefix s2733_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2734_0)) =>
+ (case ((string_drop s2733_0 s2734_0)) of
+ s2735_0 =>
+ (case ((sep_matches_prefix s2735_0)) of
+ SOME ((() , s2736_0)) =>
+ (case ((string_drop s2735_0 s2736_0)) of
+ s2737_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2737_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2738_0)) =>
+ (case ((string_drop s2737_0 s2738_0)) of s_ => SOME (rd, rs1, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2696_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2696_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word#string)option) s2697_0=
+ (let s2698_0 = s2697_0 in
+ if ((string_startswith s2698_0 "s")) then
+ (case ((string_drop s2698_0 ((string_length "s")))) of
+ s2699_0 =>
+ (case ((size_mnemonic_matches_prefix s2699_0)) of
+ SOME ((size1, s2700_0)) =>
+ (case ((string_drop s2699_0 s2700_0)) of
+ s2701_0 =>
+ (case ((maybe_aq_matches_prefix s2701_0)) of
+ SOME ((aq, s2702_0)) =>
+ (case ((string_drop s2701_0 s2702_0)) of
+ s2703_0 =>
+ (case ((maybe_rl_matches_prefix s2703_0)) of
+ SOME ((rl, s2704_0)) =>
+ (case ((string_drop s2703_0 s2704_0)) of
+ s2705_0 =>
+ (case ((spc_matches_prefix0 s2705_0)) of
+ SOME ((() , s2706_0)) =>
+ (case ((string_drop s2705_0 s2706_0)) of
+ s2707_0 =>
+ (case ((reg_name_matches_prefix s2707_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2708_0)) =>
+ (case ((string_drop s2707_0 s2708_0)) of
+ s2709_0 =>
+ (case ((sep_matches_prefix s2709_0)) of
+ SOME ((() , s2710_0)) =>
+ (case ((string_drop s2709_0 s2710_0)) of
+ s2711_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2711_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2712_0)) =>
+ (case ((string_drop s2711_0 s2712_0)) of
+ s2713_0 =>
+ (case ((opt_spc_matches_prefix0 s2713_0)) of
+ SOME ((() , s2714_0)) =>
+ let s2715_0 = (string_drop s2713_0 s2714_0) in
+ if ((string_startswith s2715_0 "(")) then
+ (case ((string_drop s2715_0 ((string_length "(")))) of
+ s2716_0 =>
+ (case ((opt_spc_matches_prefix0 s2716_0)) of
+ SOME ((() , s2717_0)) =>
+ (case ((string_drop s2716_0 s2717_0)) of
+ s2718_0 =>
+ (case ((reg_name_matches_prefix s2718_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2719_0)) =>
+ (case ((string_drop s2718_0 s2719_0)) of
+ s2720_0 =>
+ (case ((opt_spc_matches_prefix0 s2720_0)) of
+ SOME ((() , s2721_0)) =>
+ let s2722_0 = (string_drop s2720_0 s2721_0) in
+ if ((string_startswith s2722_0 ")")) then
+ (case ((string_drop s2722_0 ((string_length ")")))) of
+ s_ =>
+ SOME (size1, aq, rl, rs2, imm, rs1, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2666_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2666_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word#string)option) s2667_0=
+ (let s2668_0 = s2667_0 in
+ if ((string_startswith s2668_0 "l")) then
+ (case ((string_drop s2668_0 ((string_length "l")))) of
+ s2669_0 =>
+ (case ((size_mnemonic_matches_prefix s2669_0)) of
+ SOME ((size1, s2670_0)) =>
+ (case ((string_drop s2669_0 s2670_0)) of
+ s2671_0 =>
+ (case ((maybe_u_matches_prefix s2671_0)) of
+ SOME ((is_unsigned, s2672_0)) =>
+ (case ((string_drop s2671_0 s2672_0)) of
+ s2673_0 =>
+ (case ((maybe_aq_matches_prefix s2673_0)) of
+ SOME ((aq, s2674_0)) =>
+ (case ((string_drop s2673_0 s2674_0)) of
+ s2675_0 =>
+ (case ((maybe_rl_matches_prefix s2675_0)) of
+ SOME ((rl, s2676_0)) =>
+ (case ((string_drop s2675_0 s2676_0)) of
+ s2677_0 =>
+ (case ((spc_matches_prefix0 s2677_0)) of
+ SOME ((() , s2678_0)) =>
+ (case ((string_drop s2677_0 s2678_0)) of
+ s2679_0 =>
+ (case ((reg_name_matches_prefix s2679_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2680_0)) =>
+ (case ((string_drop s2679_0 s2680_0)) of
+ s2681_0 =>
+ (case ((sep_matches_prefix s2681_0)) of
+ SOME ((() , s2682_0)) =>
+ (case ((string_drop s2681_0 s2682_0)) of
+ s2683_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2683_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2684_0)) =>
+ (case ((string_drop s2683_0 s2684_0)) of
+ s2685_0 =>
+ (case ((opt_spc_matches_prefix0 s2685_0)) of
+ SOME ((() , s2686_0)) =>
+ let s2687_0 = (string_drop s2685_0 s2686_0) in
+ if ((string_startswith s2687_0 "(")) then
+ (case ((string_drop s2687_0 ((string_length "(")))) of
+ s2688_0 =>
+ (case ((opt_spc_matches_prefix0 s2688_0)) of
+ SOME ((() , s2689_0)) =>
+ (case ((string_drop s2688_0 s2689_0)) of
+ s2690_0 =>
+ (case ((reg_name_matches_prefix s2690_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2691_0)) =>
+ (case ((string_drop s2690_0 s2691_0)) of
+ s2692_0 =>
+ (case ((opt_spc_matches_prefix0 s2692_0)) of
+ SOME ((() , s2693_0)) =>
+ let s2694_0 = (string_drop s2692_0 s2693_0) in
+ if ((string_startswith s2694_0 ")")) then
+ (case ((string_drop s2694_0 ((string_length ")")))) of
+ s_ =>
+ SOME (size1, is_unsigned, aq, rl, rd, imm, rs1, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2649_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2649_:string ->(rop#(5)words$word#(5)words$word#(5)words$word#string)option) s2650_0=
+ ((case s2650_0 of
+ s2651_0 =>
+ (case ((rtype_mnemonic_matches_prefix s2651_0)) of
+ SOME ((op, s2652_0)) =>
+ (case ((string_drop s2651_0 s2652_0)) of
+ s2653_0 =>
+ (case ((spc_matches_prefix0 s2653_0)) of
+ SOME ((() , s2654_0)) =>
+ (case ((string_drop s2653_0 s2654_0)) of
+ s2655_0 =>
+ (case ((reg_name_matches_prefix s2655_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2656_0)) =>
+ (case ((string_drop s2655_0 s2656_0)) of
+ s2657_0 =>
+ (case ((sep_matches_prefix s2657_0)) of
+ SOME ((() , s2658_0)) =>
+ (case ((string_drop s2657_0 s2658_0)) of
+ s2659_0 =>
+ (case ((reg_name_matches_prefix s2659_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2660_0)) =>
+ (case ((string_drop s2659_0 s2660_0)) of
+ s2661_0 =>
+ (case ((sep_matches_prefix s2661_0)) of
+ SOME ((() , s2662_0)) =>
+ (case ((string_drop s2661_0 s2662_0)) of
+ s2663_0 =>
+ (case ((reg_name_matches_prefix s2663_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2664_0)) =>
+ (case ((string_drop s2663_0 s2664_0)) of
+ s_ => SOME (op, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2632_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s2632_:string ->(sop#(5)words$word#(5)words$word#(6)words$word#string)option) s2633_0=
+ ((case s2633_0 of
+ s2634_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s2634_0)) of
+ SOME ((op, s2635_0)) =>
+ (case ((string_drop s2634_0 s2635_0)) of
+ s2636_0 =>
+ (case ((spc_matches_prefix0 s2636_0)) of
+ SOME ((() , s2637_0)) =>
+ (case ((string_drop s2636_0 s2637_0)) of
+ s2638_0 =>
+ (case ((reg_name_matches_prefix s2638_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2639_0)) =>
+ (case ((string_drop s2638_0 s2639_0)) of
+ s2640_0 =>
+ (case ((sep_matches_prefix s2640_0)) of
+ SOME ((() , s2641_0)) =>
+ (case ((string_drop s2640_0 s2641_0)) of
+ s2642_0 =>
+ (case ((reg_name_matches_prefix s2642_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2643_0)) =>
+ (case ((string_drop s2642_0 s2643_0)) of
+ s2644_0 =>
+ (case ((sep_matches_prefix s2644_0)) of
+ SOME ((() , s2645_0)) =>
+ (case ((string_drop s2644_0 s2645_0)) of
+ s2646_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2646_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2647_0)) =>
+ (case ((string_drop s2646_0 s2647_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2615_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2615_:string ->(iop#(5)words$word#(5)words$word#(12)words$word#string)option) s2616_0=
+ ((case s2616_0 of
+ s2617_0 =>
+ (case ((itype_mnemonic_matches_prefix s2617_0)) of
+ SOME ((op, s2618_0)) =>
+ (case ((string_drop s2617_0 s2618_0)) of
+ s2619_0 =>
+ (case ((spc_matches_prefix0 s2619_0)) of
+ SOME ((() , s2620_0)) =>
+ (case ((string_drop s2619_0 s2620_0)) of
+ s2621_0 =>
+ (case ((reg_name_matches_prefix s2621_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2622_0)) =>
+ (case ((string_drop s2621_0 s2622_0)) of
+ s2623_0 =>
+ (case ((sep_matches_prefix s2623_0)) of
+ SOME ((() , s2624_0)) =>
+ (case ((string_drop s2623_0 s2624_0)) of
+ s2625_0 =>
+ (case ((reg_name_matches_prefix s2625_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2626_0)) =>
+ (case ((string_drop s2625_0 s2626_0)) of
+ s2627_0 =>
+ (case ((sep_matches_prefix s2627_0)) of
+ SOME ((() , s2628_0)) =>
+ (case ((string_drop s2627_0 s2628_0)) of
+ s2629_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2629_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2630_0)) =>
+ (case ((string_drop s2629_0 s2630_0)) of
+ s_ => SOME (op, rd, rs1, imm, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2598_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13 * string))*)
+
+val _ = Define `
+ ((s2598_:string ->(bop#(5)words$word#(5)words$word#(13)words$word#string)option) s2599_0=
+ ((case s2599_0 of
+ s2600_0 =>
+ (case ((btype_mnemonic_matches_prefix s2600_0)) of
+ SOME ((op, s2601_0)) =>
+ (case ((string_drop s2600_0 s2601_0)) of
+ s2602_0 =>
+ (case ((spc_matches_prefix0 s2602_0)) of
+ SOME ((() , s2603_0)) =>
+ (case ((string_drop s2602_0 s2603_0)) of
+ s2604_0 =>
+ (case ((reg_name_matches_prefix s2604_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2605_0)) =>
+ (case ((string_drop s2604_0 s2605_0)) of
+ s2606_0 =>
+ (case ((sep_matches_prefix s2606_0)) of
+ SOME ((() , s2607_0)) =>
+ (case ((string_drop s2606_0 s2607_0)) of
+ s2608_0 =>
+ (case ((reg_name_matches_prefix s2608_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2609_0)) =>
+ (case ((string_drop s2608_0 s2609_0)) of
+ s2610_0 =>
+ (case ((sep_matches_prefix s2610_0)) of
+ SOME ((() , s2611_0)) =>
+ (case ((string_drop s2610_0 s2611_0)) of
+ s2612_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2612_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s2613_0)) =>
+ (case ((string_drop s2612_0 s2613_0)) of
+ s_ => SOME (op, rs1, rs2, imm, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2582_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2582_:string ->((5)words$word#(5)words$word#(12)words$word#string)option) s2583_0=
+ (let s2584_0 = s2583_0 in
+ if ((string_startswith s2584_0 "jalr")) then
+ (case ((string_drop s2584_0 ((string_length "jalr")))) of
+ s2585_0 =>
+ (case ((spc_matches_prefix0 s2585_0)) of
+ SOME ((() , s2586_0)) =>
+ (case ((string_drop s2585_0 s2586_0)) of
+ s2587_0 =>
+ (case ((reg_name_matches_prefix s2587_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2588_0)) =>
+ (case ((string_drop s2587_0 s2588_0)) of
+ s2589_0 =>
+ (case ((sep_matches_prefix s2589_0)) of
+ SOME ((() , s2590_0)) =>
+ (case ((string_drop s2589_0 s2590_0)) of
+ s2591_0 =>
+ (case ((reg_name_matches_prefix s2591_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2592_0)) =>
+ (case ((string_drop s2591_0 s2592_0)) of
+ s2593_0 =>
+ (case ((sep_matches_prefix s2593_0)) of
+ SOME ((() , s2594_0)) =>
+ (case ((string_drop s2593_0 s2594_0)) of
+ s2595_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2595_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2596_0)) =>
+ (case ((string_drop s2595_0 s2596_0)) of s_ => SOME (rd, rs1, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2570_ : string -> maybe ((mword ty5 * mword ty21 * string))*)
+
+val _ = Define `
+ ((s2570_:string ->((5)words$word#(21)words$word#string)option) s2571_0=
+ (let s2572_0 = s2571_0 in
+ if ((string_startswith s2572_0 "jal")) then
+ (case ((string_drop s2572_0 ((string_length "jal")))) of
+ s2573_0 =>
+ (case ((spc_matches_prefix0 s2573_0)) of
+ SOME ((() , s2574_0)) =>
+ (case ((string_drop s2573_0 s2574_0)) of
+ s2575_0 =>
+ (case ((reg_name_matches_prefix s2575_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2576_0)) =>
+ (case ((string_drop s2575_0 s2576_0)) of
+ s2577_0 =>
+ (case ((sep_matches_prefix s2577_0)) of
+ SOME ((() , s2578_0)) =>
+ (case ((string_drop s2577_0 s2578_0)) of
+ s2579_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2579_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s2580_0)) =>
+ (case ((string_drop s2579_0 s2580_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2557_ : string -> maybe ((uop * mword ty5 * mword ty20 * string))*)
+
+val _ = Define `
+ ((s2557_:string ->(uop#(5)words$word#(20)words$word#string)option) s2558_0=
+ ((case s2558_0 of
+ s2559_0 =>
+ (case ((utype_mnemonic_matches_prefix s2559_0)) of
+ SOME ((op, s2560_0)) =>
+ (case ((string_drop s2559_0 s2560_0)) of
+ s2561_0 =>
+ (case ((spc_matches_prefix0 s2561_0)) of
+ SOME ((() , s2562_0)) =>
+ (case ((string_drop s2561_0 s2562_0)) of
+ s2563_0 =>
+ (case ((reg_name_matches_prefix s2563_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2564_0)) =>
+ (case ((string_drop s2563_0 s2564_0)) of
+ s2565_0 =>
+ (case ((sep_matches_prefix s2565_0)) of
+ SOME ((() , s2566_0)) =>
+ (case ((string_drop s2565_0 s2566_0)) of
+ s2567_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2567_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s2568_0)) =>
+ (case ((string_drop s2567_0 s2568_0)) of s_ => SOME (op, rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_matches_prefix:string ->(ast#int)option) arg_=
+ (let s2569_0 = arg_ in
+ if ((case ((s2557_ s2569_0 : ((uop # 5 words$word # 20 words$word # string))option)) of
+ SOME ((op, rd, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2557_ s2569_0 : (( uop # 5 words$word # 20 words$word # string)) option) of
+ (SOME ((op, rd, imm, s_))) =>
+ SOME (UTYPE (imm, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2570_ s2569_0 : (( 5 words$word # 21 words$word # string))option)) of
+ SOME ((rd, imm, s_)) => T
+ | _ => F
+ )) then (case (s2570_ s2569_0 : (( 5 words$word # 21 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (RISCV_JAL (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2582_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((rd, rs1, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2582_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((rd, rs1, imm, s_))) =>
+ SOME
+ (RISCV_JALR (imm, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2598_ s2569_0 : ((bop # 5 words$word # 5 words$word # 13 words$word # string))option)) of
+ SOME ((op, rs1, rs2, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2598_ s2569_0 : (( bop # 5 words$word # 5 words$word # 13 words$word # string)) option) of
+ (SOME ((op, rs1, rs2, imm, s_))) =>
+ SOME
+ (BTYPE (imm, rs2, rs1, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2615_ s2569_0 : ((iop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2615_ s2569_0 : (( iop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, imm, s_))) =>
+ SOME
+ (ITYPE (imm, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2632_ s2569_0 : ((sop # 5 words$word # 5 words$word # 6 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => T
+ | _ => F
+ )) then (case
+ (s2632_ s2569_0 : (( sop # 5 words$word # 5 words$word # 6 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTIOP (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2649_ s2569_0 : ((rop # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2649_ s2569_0 : (( rop # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, rs2, s_))) =>
+ SOME
+ (RTYPE (rs2, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2666_ s2569_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word # string))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2666_ s2569_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1, s_))) =>
+ SOME
+ (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2696_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2696_ s2569_0
+ : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1, s_))) =>
+ SOME
+ (STORE (imm, rs2, rs1, size1, aq, rl),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2724_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((rd, rs1, imm, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2724_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((rd, rs1, imm, s_))) =>
+ SOME (ADDIW (imm, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2740_ s2569_0 : ((sop # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2740_ s2569_0 : (( sop # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTW (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2757_ s2569_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2757_ s2569_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, rs2, s_))) =>
+ SOME
+ (RTYPEW (rs2, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2774_ s2569_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2774_ s2569_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTIWOP (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2791_ s2569_0 : (( 4 words$word # 4 words$word # string))option)) of
+ SOME ((pred, succ, s_)) => T
+ | _ => F
+ )) then (case (s2791_ s2569_0 : (( 4 words$word # 4 words$word # string)) option) of
+ (SOME ((pred, succ, s_))) =>
+ SOME (FENCE (pred, succ), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2803_ s2569_0 : (( 4 words$word # 4 words$word # string))option)) of
+ SOME ((pred, succ, s_)) => T
+ | _ => F
+ )) then (case (s2803_ s2569_0 : (( 4 words$word # 4 words$word # string)) option) of
+ (SOME ((pred, succ, s_))) =>
+ SOME (FENCE_TSO (pred, succ), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2815_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2815_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (FENCEI () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2819_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2819_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (ECALL () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2823_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2823_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (MRET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2827_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2827_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (SRET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2831_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2831_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (EBREAK () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2835_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2835_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (WFI () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2839_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case (s2839_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rs1, rs2, s_))) =>
+ SOME (SFENCE_VMA (rs1, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2851_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rd, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2851_ s2569_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, s_))) =>
+ SOME
+ (LOADRES (aq, rl, rs1, size1, rd), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2869_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2869_ s2569_0
+ : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2, s_))) =>
+ SOME
+ (STORECON (aq, rl, rs2, rs1, size1, rd),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2891_ s2569_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2891_ s2569_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2, s_))) =>
+ SOME
+ (AMO (op, aq, rl, rs2, rs1, width, rd),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2915_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2915_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (C_NOP () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2919_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rdc, nzimm, s_)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s2919_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rdc, nzimm, s_))) =>
+ SOME
+ (C_ADDI4SPN (rdc, nzimm), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2931_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rdc, rsc, uimm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2931_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rdc, rsc, uimm, s_))) =>
+ SOME (C_LW (uimm, rsc, rdc), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2947_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rdc, rsc, uimm, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2947_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rdc, rsc, uimm, s_))) =>
+ SOME (C_LD (uimm, rsc, rdc), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2963_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rsc1, rsc2, uimm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2963_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rsc1, rsc2, uimm, s_))) =>
+ SOME
+ (C_SW (uimm, rsc1, rsc2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2979_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rsc1, rsc2, uimm, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2979_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rsc1, rsc2, uimm, s_))) =>
+ SOME
+ (C_SD (uimm, rsc1, rsc2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2995_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, nzi, s_)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2995_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, nzi, s_))) =>
+ SOME (C_ADDI (nzi, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3007_ s2569_0 : (( 11 words$word # string))option)) of
+ SOME ((imm, s_)) => ((( 32 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s3007_ s2569_0 : (( 11 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_JAL imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3015_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, imm, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3015_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, imm, s_))) =>
+ SOME (C_ADDIW (imm, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3027_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, imm, s_)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3027_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (C_LI (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3039_ s2569_0 : (( 6 words$word # string))option)) of
+ SOME ((imm, s_)) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3039_ s2569_0 : (( 6 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_ADDI16SP imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3047_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, imm, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s3047_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (C_LUI (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3059_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3059_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SRLI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3071_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3071_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SRAI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3083_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, imm, s_)) => T
+ | _ => F
+ )) then (case (s3083_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, imm, s_))) =>
+ SOME (C_ANDI (imm, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3095_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3095_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_SUB (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3107_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3107_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_XOR (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3119_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3119_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_OR (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3131_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3131_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_AND (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3143_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3143_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_SUBW (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3155_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3155_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_ADDW (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3167_ s2569_0 : (( 11 words$word # string))option)) of
+ SOME ((imm, s_)) => T
+ | _ => F
+ )) then (case (s3167_ s2569_0 : (( 11 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_J imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3175_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rs, imm, s_)) => T
+ | _ => F
+ )) then (case (s3175_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rs, imm, s_))) =>
+ SOME (C_BEQZ (imm, rs), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3187_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rs, imm, s_)) => T
+ | _ => F
+ )) then (case (s3187_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rs, imm, s_))) =>
+ SOME (C_BNEZ (imm, rs), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3199_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3199_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SLLI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3211_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3211_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_LWSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3223_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 32 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s3223_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_LDSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3235_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) => T
+ | _ => F
+ )) then (case (s3235_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_SWSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3247_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rs2, uimm, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3247_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rs2, uimm, s_))) =>
+ SOME (C_SDSP (uimm, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3259_ s2569_0 : (( 5 words$word # string))option)) of
+ SOME ((rs1, s_)) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3259_ s2569_0 : (( 5 words$word # string)) option) of
+ (SOME ((rs1, s_))) =>
+ SOME (C_JR rs1, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3267_ s2569_0 : (( 5 words$word # string))option)) of
+ SOME ((rs1, s_)) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3267_ s2569_0 : (( 5 words$word # string)) option) of
+ (SOME ((rs1, s_))) =>
+ SOME (C_JALR rs1, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3275_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rd, rs2, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3275_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rd, rs2, s_))) =>
+ SOME (C_MV (rd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3287_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s3287_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (C_EBREAK () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3291_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3291_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_ADD (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3303_ s2569_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3303_ s2569_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2, s_))) =>
+ SOME
+ (MUL (rs2, rs1, rd, high, signed1, signed2),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3320_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3320_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (DIV0 (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3338_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3338_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (REM (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3356_ s2569_0 : (( 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((rd, rs1, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3356_ s2569_0 : (( 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rd, rs1, rs2, s_))) =>
+ SOME (MULW (rs2, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3372_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3372_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (DIVW (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3391_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => ((( 32 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3391_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (REMW (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3410_ s2569_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, csr, s_)) => T
+ | _ => F
+ )) then (case
+ (s3410_ s2569_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, csr, s_))) =>
+ SOME
+ (CSR (csr, rs1, rd, T, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3428_ s2569_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, csr, s_)) => T
+ | _ => F
+ )) then (case
+ (s3428_ s2569_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, csr, s_))) =>
+ SOME
+ (CSR (csr, rs1, rd, F, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3445_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s3445_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (URET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3449_ s2569_0 : (( 32 words$word # string))option)) of
+ SOME ((s, s_)) => T
+ | _ => F
+ )) then (case (s3449_ s2569_0 : (( 32 words$word # string)) option) of
+ (SOME ((s, s_))) =>
+ SOME (ILLEGAL s, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3457_ s2569_0 : (( 16 words$word # string))option)) of
+ SOME ((s, s_)) => T
+ | _ => F
+ )) then (case (s3457_ s2569_0 : (( 16 words$word # string)) option) of
+ (SOME ((s, s_))) =>
+ SOME (C_ILLEGAL s, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((print_insn:ast ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) insn= (assembly_forwards insn))`;
+
+
+(*val decode : mword ty32 -> M ast*)
+
+val _ = Define `
+ ((decode:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bv= (encdec_backwards bv))`;
+
+
+(*val decodeCompressed : mword ty16 -> ast*)
+
+val _ = Define `
+ ((decodeCompressed:(16)words$word -> ast) bv= (encdec_compressed_backwards bv))`;
+
+
+(*val ext_init : unit -> unit*)
+
+val _ = Define `
+ ((ext_init:unit -> unit) () = () )`;
+
+
+(*val ext_fetch_hook : FetchResult -> FetchResult*)
+
+val _ = Define `
+ ((ext_fetch_hook:FetchResult -> FetchResult) f= f)`;
+
+
+(*val ext_pre_step_hook : unit -> unit*)
+
+val _ = Define `
+ ((ext_pre_step_hook:unit -> unit) () = () )`;
+
+
+(*val ext_post_step_hook : unit -> unit*)
+
+val _ = Define `
+ ((ext_post_step_hook:unit -> unit) () = () )`;
+
+
+(*val ext_post_decode_hook : ast -> M ast*)
+
+val _ = Define `
+ ((ext_post_decode_hook:ast ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= (sail2_state_monad$returnS x))`;
+
+
+(*val isRVC : mword ty16 -> bool*)
+
+val _ = Define `
+ ((isRVC:(16)words$word -> bool) h=
+ (~ (((((subrange_vec_dec h (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))`;
+
+
+(*val fetch : unit -> M FetchResult*)
+
+val _ = Define `
+ ((fetch:unit ->(regstate)sail2_state_monad$sequential_state ->(((FetchResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) .
+ (case ((ext_fetch_check_pc w__0 w__1)) of
+ Ext_FetchAddr_Error (e) => sail2_state_monad$returnS (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc) => sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec use_pc (( 0 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec use_pc (( 1 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) .
+ if w__4 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) .
+ sail2_state_monad$returnS (F_Error (E_Fetch_Addr_Align, w__5)))
+ else sail2_state_monad$bindS
+ (translateAddr use_pc Execute : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__6 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__6 of
+ TR_Failure (e) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__7 : 32 words$word) .
+ sail2_state_monad$returnS (F_Error (e, w__7)))
+ | TR_Address (ppclo) => sail2_state_monad$bindS
+ (mem_read Execute ppclo (( 2 : int):ii) F F F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__8 : ( 16 words$word)
+ MemoryOpResult) .
+ (case w__8 of
+ MemException (e) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) .
+ sail2_state_monad$returnS (F_Error (E_Fetch_Access_Fault, w__9)))
+ | MemValue (ilo) =>
+ if ((isRVC ilo)) then sail2_state_monad$returnS (F_RVC ilo)
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) .
+ let (PC_hi : xlenbits) = ((add_vec_int w__10 (( 2 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__11 : 32 words$word) .
+ (case ((ext_fetch_check_pc w__11 PC_hi)) of
+ Ext_FetchAddr_Error (e) => sail2_state_monad$returnS (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc_hi) => sail2_state_monad$bindS
+ (translateAddr use_pc_hi Execute : ( (( 32 words$word), ExceptionType)TR_Result) M) (\ (w__12 : (( 32 words$word), ExceptionType)
+ TR_Result) .
+ (case w__12 of
+ TR_Failure (e) => sail2_state_monad$returnS (F_Error (e, PC_hi))
+ | TR_Address (ppchi) => sail2_state_monad$bindS
+ (mem_read Execute ppchi (( 2 : int):ii) F F F
+ : ( ( 16 words$word)MemoryOpResult) M) (\ (w__13 : ( 16 words$word)
+ MemoryOpResult) .
+ sail2_state_monad$returnS ((case w__13 of
+ MemException (e) => F_Error (E_Fetch_Access_Fault, PC_hi)
+ | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word))
+ )))
+ ))
+ )))
+ ))
+ )))
+ )))))`;
+
+
+(*val step : ii -> M bool*)
+
+val _ = Define `
+ ((step:int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) step_no=
+ (let (_ : unit) = (ext_pre_step_hook () ) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS minstret_written_ref F)
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (dispatchInterrupt w__0) (\ (w__1 : ((InterruptType # Privilege))option) . sail2_state_monad$bindS
+ (case w__1 of
+ SOME ((intr, priv)) =>
+ let (_ : unit) =
+ (if ((get_config_print_instr () )) then
+ print_bits0 "Handling interrupt: " ((interruptType_to_bits intr : 8 words$word))
+ else () ) in sail2_state_monad$seqS
+ (handle_interrupt intr priv) (sail2_state_monad$returnS (RETIRE_FAIL, F))
+ | NONE => sail2_state_monad$bindS
+ (fetch () ) (\ (w__2 : FetchResult) .
+ let (f : FetchResult) = (ext_fetch_hook w__2) in
+ (case f of
+ F_Ext_Error (e) =>
+ let (_ : unit) = (ext_handle_fetch_check_error e) in
+ sail2_state_monad$returnS (RETIRE_FAIL, F)
+ | F_Error ((e, addr)) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS (RETIRE_FAIL, F))
+ | F_RVC (h) =>
+ let ast = (decodeCompressed h) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_instr () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS
+ (print_insn ast) (\ (w__5 : string) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "["
+ ((STRCAT ((stringFromInteger step_no))
+ ((STRCAT "] ["
+ ((STRCAT ((privLevel_to_str w__3))
+ ((STRCAT "]: "
+ ((STRCAT ((string_of_bits w__4))
+ ((STRCAT " ("
+ ((STRCAT ((string_of_bits h))
+ ((STRCAT ") " w__5)))))))))))))))))))))))
+ else sail2_state_monad$returnS () )
+ (haveRVC () )) (\ (w__6 : bool) .
+ if w__6 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__7 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__7 (( 2 : int):ii) : 32 words$word)))
+ (ext_post_decode_hook ast)) (\ (w__8 : ast) . sail2_state_monad$bindS
+ (execute w__8) (\ (w__9 : Retired) . sail2_state_monad$returnS (w__9, T))))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS (RETIRE_FAIL, T)))
+ | F_Base (w) => sail2_state_monad$bindS
+ (decode w) (\ ast . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_instr () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__11 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . sail2_state_monad$bindS
+ (print_insn ast) (\ (w__13 : string) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "["
+ ((STRCAT ((stringFromInteger step_no))
+ ((STRCAT "] ["
+ ((STRCAT ((privLevel_to_str w__11))
+ ((STRCAT "]: "
+ ((STRCAT ((string_of_bits w__12))
+ ((STRCAT " ("
+ ((STRCAT ((string_of_bits w))
+ ((STRCAT ") " w__13)))))))))))))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS PC_ref : ( 32 words$word) M)) (\ (w__14 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__14 (( 4 : int):ii) : 32 words$word)))
+ (ext_post_decode_hook ast)) (\ (w__15 : ast) . sail2_state_monad$bindS
+ (execute w__15) (\ (w__16 : Retired) . sail2_state_monad$returnS (w__16, T)))))
+ ))
+ ) (\ varstup . let ((retired : Retired), (stepped : bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (tick_pc () )
+ (case retired of RETIRE_SUCCESS => retire_instruction () | RETIRE_FAIL => sail2_state_monad$returnS () ))
+ (let (_ : unit) = (ext_post_step_hook () ) in
+ sail2_state_monad$returnS stepped))))))`;
+
+
+(*val loop : unit -> M unit*)
+
+val _ = Define `
+ ((loop:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+ (let insns_per_tick = (plat_insns_per_tick () ) in
+ let (i : ii) = ((( 0 : int):ii)) in
+ let (step_no : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+ (sail2_state$whileS (i, step_no)
+ (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_done_ref) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))
+ (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS
+ (step step_no) (\ stepped .
+ let (step_no : ii) = (if stepped then step_no + (( 1 : int):ii) else step_no) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_done_ref) (\ (w__1 : bool) . sail2_state_monad$bindS
+ (if w__1 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_exit_code_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ let exit_val = (lem$w2ui w__2) in
+ sail2_state_monad$returnS (let _ =
+ (if (((exit_val = (( 0 : int):ii)))) then print_endline "SUCCESS"
+ else print_int "FAILURE: " exit_val) in
+ i))
+ else
+ let i = (i + (( 1 : int):ii)) in
+ if (((i = insns_per_tick))) then sail2_state_monad$seqS (sail2_state_monad$seqS (tick_clock () ) (tick_platform () )) (sail2_state_monad$returnS (( 0 : int):ii))
+ else sail2_state_monad$returnS i) (\ (i : ii) .
+ sail2_state_monad$returnS (i, step_no)))))) (\ varstup . let ((i : ii), (step_no : ii)) = varstup in
+ sail2_state_monad$returnS () )))`;
+
+
+(*val init_model : unit -> M unit*)
+
+val _ = Define `
+ ((init_model:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (init_platform () )
+ (init_sys () ))
+ (init_vmem () ))
+ (let (_ : unit) = (ext_init () ) in
+ ext_init_regs () )))`;
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV32/riscv_extrasScript.sml b/prover_snapshots/hol4/RV32/riscv_extrasScript.sml
new file mode 100644
index 0000000..c6d4fe2
--- /dev/null
+++ b/prover_snapshots/hol4/RV32/riscv_extrasScript.sml
@@ -0,0 +1,276 @@
+(*Generated by Lem from handwritten_support/riscv_extras.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_extras"
+
+(*open import Pervasives*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+val _ = type_abbrev((* 'a *) "bitvector" , ``: 'a words$word``);
+
+val _ = Define `
+ ((MEM_fence_rw_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_r))`;
+
+val _ = Define `
+ ((MEM_fence_rw_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_rw))`;
+
+val _ = Define `
+ ((MEM_fence_rw_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_r))`;
+
+val _ = Define `
+ ((MEM_fence_r_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_r))`;
+
+val _ = Define `
+ ((MEM_fence_tso:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_tso))`;
+
+val _ = Define `
+ ((MEM_fence_i:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_i))`;
+
+
+(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+
+val _ = Define `
+ ((MEMea:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=
+ (sail2_state_monad$returnS () ))`;
+
+
+(*val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+
+val _ = Define `
+ ((MEMr:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addrsize addr size1))`;
+
+
+(*val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+
+val _ = Define `
+ ((MEMw:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_strong_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional_strong_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addrsize addr size1))`;
+
+
+(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((load_reservation:'a words$word -> unit) addr= () )`;
+
+
+val _ = Define `
+ ((speculate_conditional_success:unit -> 'a sail2_state_monad$sequential_state ->(((bool),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$excl_resultS () ))`;
+
+
+val _ = Define `
+ ((match_reservation:'a -> bool) _= T)`;
+
+val _ = Define `
+ ((cancel_reservation:unit -> unit) () = () )`;
+
+
+(*val sys_enable_writable_misa : unit -> bool*)
+val _ = Define `
+ ((sys_enable_writable_misa:unit -> bool) () = T)`;
+
+
+(*val sys_enable_rvc : unit -> bool*)
+val _ = Define `
+ ((sys_enable_rvc:unit -> bool) () = T)`;
+
+
+(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_ram_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_ram_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_rom_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_rom_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_enable_dirty_update : unit -> bool*)
+val _ = Define `
+ ((plat_enable_dirty_update:unit -> bool) () = F)`;
+
+
+(*val plat_enable_misaligned_access : unit -> bool*)
+val _ = Define `
+ ((plat_enable_misaligned_access:unit -> bool) () = F)`;
+
+
+(*val plat_enable_pmp : unit -> bool*)
+val _ = Define `
+ ((plat_enable_pmp:unit -> bool) () = F)`;
+
+
+(*val plat_mtval_has_illegal_inst_bits : unit -> bool*)
+val _ = Define `
+ ((plat_mtval_has_illegal_inst_bits:unit -> bool) () = F)`;
+
+
+(*val plat_insns_per_tick : unit -> integer*)
+val _ = Define `
+ ((plat_insns_per_tick:unit -> int) () = (( 1 : int)))`;
+
+
+(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_htif_tohost:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((plat_term_write:'a words$word -> unit) _= () )`;
+
+
+(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_term_read:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_right:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftr v (lem$w2ui m)))`;
+
+(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_left:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftl v (lem$w2ui m)))`;
+
+
+(*val print_string : string -> string -> unit*)
+val _ = Define `
+ ((print_string:string -> string -> unit) msg s= () )`;
+ (* print_endline (msg ^ s) *)
+
+(*val prerr_string : string -> string -> unit*)
+val _ = Define `
+ ((prerr_string:string -> string -> unit) msg s= (prerr_endline ( STRCAT msg s)))`;
+
+
+(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((prerr_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`;
+
+
+(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((print_bits0:string -> 'a words$word -> unit) msg bs= () )`;
+ (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
+
+(*val print_dbg : string -> unit*)
+val _ = Define `
+ ((print_dbg:string -> unit) msg= () )`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV32/riscv_typesScript.sml b/prover_snapshots/hol4/RV32/riscv_typesScript.sml
new file mode 100644
index 0000000..14b1a48
--- /dev/null
+++ b/prover_snapshots/hol4/RV32/riscv_typesScript.sml
@@ -0,0 +1,2208 @@
+(*Generated by Lem from generated_definitions/lem/RV32/riscv_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_types"
+
+(*Generated by Sail from riscv.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+
+val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``);
+
+val _ = Hol_datatype `
+ regfp =
+ RFull of (string)
+ | RSlice of ((string # ii # ii))
+ | RSliceBit of ((string # ii))
+ | RField of ((string # string))`;
+
+
+
+
+val _ = type_abbrev( "regfps" , ``: regfp list``);
+
+val _ = Hol_datatype `
+ niafp =
+ NIAFP_successor of (unit)
+ | NIAFP_concrete_address of ( 64 bits)
+ | NIAFP_indirect_address of (unit)`;
+
+
+
+
+val _ = type_abbrev( "niafps" , ``: niafp list``);
+
+val _ = Hol_datatype `
+ diafp = DIAFP_none of (unit) | DIAFP_concrete of ( 64 bits) | DIAFP_reg of (regfp)`;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+val _ = type_abbrev( "xlenbits" , ``: 32 bits``);
+
+val _ = type_abbrev( "mem_meta" , ``: unit``);
+
+
+
+val _ = type_abbrev( "half" , ``: 16 bits``);
+
+val _ = type_abbrev( "word" , ``: 32 bits``);
+
+val _ = type_abbrev( "regidx" , ``: 5 bits``);
+
+val _ = type_abbrev( "cregidx" , ``: 3 bits``);
+
+val _ = type_abbrev( "csreg" , ``: 12 bits``);
+
+val _ = type_abbrev((* 'n *) "regno" , ``: int``);
+
+val _ = type_abbrev( "opcode" , ``: 7 bits``);
+
+val _ = type_abbrev( "imm12" , ``: 12 bits``);
+
+val _ = type_abbrev( "imm20" , ``: 20 bits``);
+
+val _ = type_abbrev( "amo" , ``: 1 bits``);
+
+val _ = Hol_datatype `
+ Architecture = RV32 | RV64 | RV128`;
+
+
+
+
+val _ = type_abbrev( "arch_xlen" , ``: 2 bits``);
+
+val _ = type_abbrev( "priv_level" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ Privilege = User | Supervisor | Machine`;
+
+
+
+
+val _ = Hol_datatype `
+ amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU`;
+
+
+
+
+val _ = Hol_datatype `
+ bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU`;
+
+
+
+
+val _ = Hol_datatype `
+ csrop = CSRRW | CSRRS | CSRRC`;
+
+
+
+
+val _ = Hol_datatype `
+ iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI`;
+
+
+
+
+val _ = Hol_datatype `
+ rop =
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND`;
+
+
+
+
+val _ = Hol_datatype `
+ ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW`;
+
+
+
+
+val _ = Hol_datatype `
+ sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI`;
+
+
+
+
+val _ = Hol_datatype `
+ sopw = RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW`;
+
+
+
+
+val _ = Hol_datatype `
+ uop = RISCV_LUI | RISCV_AUIPC`;
+
+
+
+
+val _ = Hol_datatype `
+ word_width = BYTE | HALF | WORD | DOUBLE`;
+
+
+
+
+val _ = Hol_datatype `
+ ast =
+ UTYPE of (( 20 bits # regidx # uop))
+ | RISCV_JAL of (( 21 bits # regidx))
+ | RISCV_JALR of (( 12 bits # regidx # regidx))
+ | BTYPE of (( 13 bits # regidx # regidx # bop))
+ | ITYPE of (( 12 bits # regidx # regidx # iop))
+ | SHIFTIOP of (( 6 bits # regidx # regidx # sop))
+ | RTYPE of ((regidx # regidx # regidx # rop))
+ | LOAD of (( 12 bits # regidx # regidx # bool # word_width # bool # bool))
+ | STORE of (( 12 bits # regidx # regidx # word_width # bool # bool))
+ | ADDIW of (( 12 bits # regidx # regidx))
+ | SHIFTW of (( 5 bits # regidx # regidx # sop))
+ | RTYPEW of ((regidx # regidx # regidx # ropw))
+ | SHIFTIWOP of (( 5 bits # regidx # regidx # sopw))
+ | FENCE of (( 4 bits # 4 bits))
+ | FENCE_TSO of (( 4 bits # 4 bits))
+ | FENCEI of (unit)
+ | ECALL of (unit)
+ | MRET of (unit)
+ | SRET of (unit)
+ | EBREAK of (unit)
+ | WFI of (unit)
+ | SFENCE_VMA of ((regidx # regidx))
+ | LOADRES of ((bool # bool # regidx # word_width # regidx))
+ | STORECON of ((bool # bool # regidx # regidx # word_width # regidx))
+ | AMO of ((amoop # bool # bool # regidx # regidx # word_width # regidx))
+ | C_NOP of (unit)
+ | C_ADDI4SPN of ((cregidx # 8 bits))
+ | C_LW of (( 5 bits # cregidx # cregidx))
+ | C_LD of (( 5 bits # cregidx # cregidx))
+ | C_SW of (( 5 bits # cregidx # cregidx))
+ | C_SD of (( 5 bits # cregidx # cregidx))
+ | C_ADDI of (( 6 bits # regidx))
+ | C_JAL of ( 11 bits)
+ | C_ADDIW of (( 6 bits # regidx))
+ | C_LI of (( 6 bits # regidx))
+ | C_ADDI16SP of ( 6 bits)
+ | C_LUI of (( 6 bits # regidx))
+ | C_SRLI of (( 6 bits # cregidx))
+ | C_SRAI of (( 6 bits # cregidx))
+ | C_ANDI of (( 6 bits # cregidx))
+ | C_SUB of ((cregidx # cregidx))
+ | C_XOR of ((cregidx # cregidx))
+ | C_OR of ((cregidx # cregidx))
+ | C_AND of ((cregidx # cregidx))
+ | C_SUBW of ((cregidx # cregidx))
+ | C_ADDW of ((cregidx # cregidx))
+ | C_J of ( 11 bits)
+ | C_BEQZ of (( 8 bits # cregidx))
+ | C_BNEZ of (( 8 bits # cregidx))
+ | C_SLLI of (( 6 bits # regidx))
+ | C_LWSP of (( 6 bits # regidx))
+ | C_LDSP of (( 6 bits # regidx))
+ | C_SWSP of (( 6 bits # regidx))
+ | C_SDSP of (( 6 bits # regidx))
+ | C_JR of (regidx)
+ | C_JALR of (regidx)
+ | C_MV of ((regidx # regidx))
+ | C_EBREAK of (unit)
+ | C_ADD of ((regidx # regidx))
+ | MUL of ((regidx # regidx # regidx # bool # bool # bool))
+ | DIV0 of ((regidx # regidx # regidx # bool))
+ | REM of ((regidx # regidx # regidx # bool))
+ | MULW of ((regidx # regidx # regidx))
+ | DIVW of ((regidx # regidx # regidx # bool))
+ | REMW of ((regidx # regidx # regidx # bool))
+ | CSR of (( 12 bits # regidx # regidx # bool # csrop))
+ | URET of (unit)
+ | ILLEGAL of (word)
+ | C_ILLEGAL of (half)`;
+
+
+
+
+val _ = Hol_datatype `
+ Retired = RETIRE_SUCCESS | RETIRE_FAIL`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessType = Read | Write | ReadWrite | Execute`;
+
+
+
+
+val _ = type_abbrev( "exc_code" , ``: 8 bits``);
+
+val _ = Hol_datatype `
+ InterruptType =
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External`;
+
+
+
+
+val _ = Hol_datatype `
+ ExceptionType =
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI`;
+
+
+
+
+val _ = Hol_datatype `
+ exception = Error_not_implemented of (string) | Error_internal_error of (unit)`;
+
+
+
+
+val _ = type_abbrev( "tv_mode" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved`;
+
+
+
+
+val _ = type_abbrev( "ext_status" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ ExtStatus = Off | Initial | Clean | Dirty`;
+
+
+
+
+val _ = type_abbrev( "satp_mode" , ``: 4 bits``);
+
+val _ = Hol_datatype `
+ SATPMode = Sbare | Sv32 | Sv39 | Sv48`;
+
+
+
+
+val _ = type_abbrev( "csrRW" , ``: 2 bits``);
+
+val _ = type_abbrev( "regtype" , ``: xlenbits``);
+
+val _ = Hol_datatype `
+ Misa = <| Misa_Misa_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_PTE = <| SV48_PTE_SV48_PTE_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ PTE_Bits = <| PTE_Bits_PTE_Bits_chunk_0 : 8 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Pmpcfg_ent = <| Pmpcfg_ent_Pmpcfg_ent_chunk_0 : 8 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mstatus = <| Mstatus_Mstatus_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sstatus = <| Sstatus_Sstatus_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Ustatus = <| Ustatus_Ustatus_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Minterrupts = <| Minterrupts_Minterrupts_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sinterrupts = <| Sinterrupts_Sinterrupts_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Uinterrupts = <| Uinterrupts_Uinterrupts_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Medeleg = <| Medeleg_Medeleg_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sedeleg = <| Sedeleg_Sedeleg_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mtvec = <| Mtvec_Mtvec_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Satp32 = <| Satp32_Satp32_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mcause = <| Mcause_Mcause_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Counteren = <| Counteren_Counteren_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Satp64 = <| Satp64_Satp64_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ PmpAddrMatchType = OFF | TOR | NA4 | NAPOT`;
+
+
+
+
+val _ = type_abbrev( "pmp_addr_range" , ``: ((xlenbits # xlenbits))option``);
+
+val _ = Hol_datatype `
+ pmpAddrMatch = PMP_NoMatch | PMP_PartialMatch | PMP_Match`;
+
+
+
+
+val _ = Hol_datatype `
+ pmpMatch = PMP_Success | PMP_Continue | PMP_Fail`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_FetchAddr_Check = Ext_FetchAddr_OK of (xlenbits) | Ext_FetchAddr_Error of ('a)`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_ControlAddr_Check = Ext_ControlAddr_OK of (xlenbits) | Ext_ControlAddr_Error of ('a)`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_DataAddr_Check = Ext_DataAddr_OK of (xlenbits) | Ext_DataAddr_Error of ('a)`;
+
+
+
+
+val _ = type_abbrev( "ext_fetch_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_control_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_data_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_exception" , ``: unit``);
+
+val _ = Hol_datatype `
+ sync_exception =
+ <| sync_exception_trap : ExceptionType;
+ sync_exception_excinfo : xlenbits option;
+ sync_exception_ext : ext_exception option |>`;
+
+
+
+val _ = Hol_datatype `
+ interrupt_set =
+ Ints_Pending of (xlenbits) | Ints_Delegated of (xlenbits) | Ints_Empty of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ ctl_result =
+ CTL_TRAP of (sync_exception) | CTL_SRET of (unit) | CTL_MRET of (unit) | CTL_URET of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ MemoryOpResult = MemValue of ('a) | MemException of (ExceptionType)`;
+
+
+
+
+val _ = Hol_datatype `
+ htif_cmd = <| htif_cmd_htif_cmd_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = type_abbrev( "pteAttribs" , ``: 8 bits``);
+
+val _ = Hol_datatype `
+ PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update`;
+
+
+
+
+val _ = type_abbrev( "vaddr32" , ``: 32 bits``);
+
+val _ = type_abbrev( "paddr32" , ``: 34 bits``);
+
+val _ = type_abbrev( "pte32" , ``: 32 bits``);
+
+val _ = type_abbrev( "asid32" , ``: 9 bits``);
+
+val _ = Hol_datatype `
+ SV32_Vaddr = <| SV32_Vaddr_SV32_Vaddr_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_Vaddr = <| SV48_Vaddr_SV48_Vaddr_chunk_0 : 48 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_Paddr = <| SV48_Paddr_SV48_Paddr_chunk_0 : 56 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV32_Paddr = <| SV32_Paddr_SV32_Paddr_chunk_0 : 34 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV32_PTE = <| SV32_PTE_SV32_PTE_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = type_abbrev( "paddr64" , ``: 56 bits``);
+
+val _ = type_abbrev( "pte64" , ``: 64 bits``);
+
+val _ = type_abbrev( "asid64" , ``: 16 bits``);
+
+val _ = type_abbrev( "vaddr39" , ``: 39 bits``);
+
+val _ = Hol_datatype `
+ SV39_Vaddr = <| SV39_Vaddr_SV39_Vaddr_chunk_0 : 39 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV39_Paddr = <| SV39_Paddr_SV39_Paddr_chunk_0 : 56 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV39_PTE = <| SV39_PTE_SV39_PTE_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = type_abbrev( "vaddr48" , ``: 48 bits``);
+
+val _ = type_abbrev( "pte48" , ``: 64 bits``);
+
+val _ = Hol_datatype `
+ PTW_Result =
+ PTW_Success of (('paddr # 'pte # 'paddr # ii # bool)) | PTW_Failure of (PTW_Error)`;
+
+
+
+
+val _ = Hol_datatype `
+ TR_Result = TR_Address of ('a_paddr) | TR_Failure of ('b_failure)`;
+
+
+
+
+val _ = Hol_datatype `
+(* ( 'a_asidlen, 'b_valen, 'c_palen, 'd_ptelen) *) TLB_Entry =
+ <| TLB_Entry_asid :'a_asidlen bits;
+ TLB_Entry_global : bool;
+ TLB_Entry_vAddr :'b_valen bits;
+ TLB_Entry_pAddr :'c_palen bits;
+ TLB_Entry_vMatchMask :'b_valen bits;
+ TLB_Entry_vAddrMask :'b_valen bits;
+ TLB_Entry_pte :'d_ptelen bits;
+ TLB_Entry_pteAddr :'c_palen bits;
+ TLB_Entry_age : 64 bits |>`;
+
+
+
+val _ = type_abbrev( "TLB32_Entry" , ``: (9, 32, 34, 32) TLB_Entry``);
+
+val _ = Hol_datatype `
+ FetchResult =
+ F_Ext_Error of (ext_fetch_addr_error)
+ | F_Base of (word)
+ | F_RVC of (half)
+ | F_Error of ((ExceptionType # xlenbits))`;
+
+
+
+
+val _ = Hol_datatype `
+ register_value =
+ Regval_vector of ((ii # bool # register_value list))
+ | Regval_list of ( register_value list)
+ | Regval_option of ( register_value option)
+ | Regval_Counteren of (Counteren)
+ | Regval_Mcause of (Mcause)
+ | Regval_Medeleg of (Medeleg)
+ | Regval_Minterrupts of (Minterrupts)
+ | Regval_Misa of (Misa)
+ | Regval_Mstatus of (Mstatus)
+ | Regval_Mtvec of (Mtvec)
+ | Regval_Pmpcfg_ent of (Pmpcfg_ent)
+ | Regval_Privilege of (Privilege)
+ | Regval_Sedeleg of (Sedeleg)
+ | Regval_Sinterrupts of (Sinterrupts)
+ | Regval_TLB_Entry_9_32_34_32 of ( (9, 32, 34, 32)TLB_Entry)
+ | Regval_bool of (bool)
+ | Regval_vector_32_dec_bit of ( 32 words$word)
+ | Regval_vector_64_dec_bit of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate =
+ <| satp : 32 words$word;
+ tlb32 : ( (9, 32, 34, 32)TLB_Entry)option;
+ htif_exit_code : 64 words$word;
+ htif_done : bool;
+ htif_tohost : 64 words$word;
+ mtimecmp : 64 words$word;
+ utval : 32 words$word;
+ ucause : Mcause;
+ uepc : 32 words$word;
+ uscratch : 32 words$word;
+ utvec : Mtvec;
+ pmpaddr15 : 32 words$word;
+ pmpaddr14 : 32 words$word;
+ pmpaddr13 : 32 words$word;
+ pmpaddr12 : 32 words$word;
+ pmpaddr11 : 32 words$word;
+ pmpaddr10 : 32 words$word;
+ pmpaddr9 : 32 words$word;
+ pmpaddr8 : 32 words$word;
+ pmpaddr7 : 32 words$word;
+ pmpaddr6 : 32 words$word;
+ pmpaddr5 : 32 words$word;
+ pmpaddr4 : 32 words$word;
+ pmpaddr3 : 32 words$word;
+ pmpaddr2 : 32 words$word;
+ pmpaddr1 : 32 words$word;
+ pmpaddr0 : 32 words$word;
+ pmp15cfg : Pmpcfg_ent;
+ pmp14cfg : Pmpcfg_ent;
+ pmp13cfg : Pmpcfg_ent;
+ pmp12cfg : Pmpcfg_ent;
+ pmp11cfg : Pmpcfg_ent;
+ pmp10cfg : Pmpcfg_ent;
+ pmp9cfg : Pmpcfg_ent;
+ pmp8cfg : Pmpcfg_ent;
+ pmp7cfg : Pmpcfg_ent;
+ pmp6cfg : Pmpcfg_ent;
+ pmp5cfg : Pmpcfg_ent;
+ pmp4cfg : Pmpcfg_ent;
+ pmp3cfg : Pmpcfg_ent;
+ pmp2cfg : Pmpcfg_ent;
+ pmp1cfg : Pmpcfg_ent;
+ pmp0cfg : Pmpcfg_ent;
+ tselect : 32 words$word;
+ stval : 32 words$word;
+ scause : Mcause;
+ sepc : 32 words$word;
+ sscratch : 32 words$word;
+ stvec : Mtvec;
+ sideleg : Sinterrupts;
+ sedeleg : Sedeleg;
+ mhartid : 32 words$word;
+ marchid : 32 words$word;
+ mimpid : 32 words$word;
+ mvendorid : 32 words$word;
+ minstret_written : bool;
+ minstret : 64 words$word;
+ mtime : 64 words$word;
+ mcycle : 64 words$word;
+ scounteren : Counteren;
+ mcounteren : Counteren;
+ mscratch : 32 words$word;
+ mtval : 32 words$word;
+ mepc : 32 words$word;
+ mcause : Mcause;
+ mtvec : Mtvec;
+ medeleg : Medeleg;
+ mideleg : Minterrupts;
+ mie : Minterrupts;
+ mip : Minterrupts;
+ mstatus : Mstatus;
+ misa : Misa;
+ cur_inst : 32 words$word;
+ cur_privilege : Privilege;
+ x31 : 32 words$word;
+ x30 : 32 words$word;
+ x29 : 32 words$word;
+ x28 : 32 words$word;
+ x27 : 32 words$word;
+ x26 : 32 words$word;
+ x25 : 32 words$word;
+ x24 : 32 words$word;
+ x23 : 32 words$word;
+ x22 : 32 words$word;
+ x21 : 32 words$word;
+ x20 : 32 words$word;
+ x19 : 32 words$word;
+ x18 : 32 words$word;
+ x17 : 32 words$word;
+ x16 : 32 words$word;
+ x15 : 32 words$word;
+ x14 : 32 words$word;
+ x13 : 32 words$word;
+ x12 : 32 words$word;
+ x11 : 32 words$word;
+ x10 : 32 words$word;
+ x9 : 32 words$word;
+ x8 : 32 words$word;
+ x7 : 32 words$word;
+ x6 : 32 words$word;
+ x5 : 32 words$word;
+ x4 : 32 words$word;
+ x3 : 32 words$word;
+ x2 : 32 words$word;
+ x1 : 32 words$word;
+ Xs : ( 32 words$word) list;
+ instbits : 32 words$word;
+ nextPC : 32 words$word;
+ PC : 32 words$word |>`;
+
+
+
+
+
+(*val Counteren_of_regval : register_value -> maybe Counteren*)
+
+val _ = Define `
+ ((Counteren_of_regval:register_value ->(Counteren)option) merge_var=
+ ((case merge_var of Regval_Counteren (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Counteren : Counteren -> register_value*)
+
+val _ = Define `
+ ((regval_of_Counteren:Counteren -> register_value) v= (Regval_Counteren v))`;
+
+
+(*val Mcause_of_regval : register_value -> maybe Mcause*)
+
+val _ = Define `
+ ((Mcause_of_regval:register_value ->(Mcause)option) merge_var=
+ ((case merge_var of Regval_Mcause (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mcause : Mcause -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mcause:Mcause -> register_value) v= (Regval_Mcause v))`;
+
+
+(*val Medeleg_of_regval : register_value -> maybe Medeleg*)
+
+val _ = Define `
+ ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var=
+ ((case merge_var of Regval_Medeleg (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Medeleg : Medeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Medeleg:Medeleg -> register_value) v= (Regval_Medeleg v))`;
+
+
+(*val Minterrupts_of_regval : register_value -> maybe Minterrupts*)
+
+val _ = Define `
+ ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var=
+ ((case merge_var of Regval_Minterrupts (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Minterrupts : Minterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Minterrupts:Minterrupts -> register_value) v= (Regval_Minterrupts v))`;
+
+
+(*val Misa_of_regval : register_value -> maybe Misa*)
+
+val _ = Define `
+ ((Misa_of_regval:register_value ->(Misa)option) merge_var= ((case merge_var of Regval_Misa (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Misa : Misa -> register_value*)
+
+val _ = Define `
+ ((regval_of_Misa:Misa -> register_value) v= (Regval_Misa v))`;
+
+
+(*val Mstatus_of_regval : register_value -> maybe Mstatus*)
+
+val _ = Define `
+ ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var=
+ ((case merge_var of Regval_Mstatus (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mstatus : Mstatus -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mstatus:Mstatus -> register_value) v= (Regval_Mstatus v))`;
+
+
+(*val Mtvec_of_regval : register_value -> maybe Mtvec*)
+
+val _ = Define `
+ ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= ((case merge_var of Regval_Mtvec (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mtvec : Mtvec -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mtvec:Mtvec -> register_value) v= (Regval_Mtvec v))`;
+
+
+(*val Pmpcfg_ent_of_regval : register_value -> maybe Pmpcfg_ent*)
+
+val _ = Define `
+ ((Pmpcfg_ent_of_regval:register_value ->(Pmpcfg_ent)option) merge_var=
+ ((case merge_var of Regval_Pmpcfg_ent (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Pmpcfg_ent : Pmpcfg_ent -> register_value*)
+
+val _ = Define `
+ ((regval_of_Pmpcfg_ent:Pmpcfg_ent -> register_value) v= (Regval_Pmpcfg_ent v))`;
+
+
+(*val Privilege_of_regval : register_value -> maybe Privilege*)
+
+val _ = Define `
+ ((Privilege_of_regval:register_value ->(Privilege)option) merge_var=
+ ((case merge_var of Regval_Privilege (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Privilege : Privilege -> register_value*)
+
+val _ = Define `
+ ((regval_of_Privilege:Privilege -> register_value) v= (Regval_Privilege v))`;
+
+
+(*val Sedeleg_of_regval : register_value -> maybe Sedeleg*)
+
+val _ = Define `
+ ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var=
+ ((case merge_var of Regval_Sedeleg (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Sedeleg : Sedeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sedeleg:Sedeleg -> register_value) v= (Regval_Sedeleg v))`;
+
+
+(*val Sinterrupts_of_regval : register_value -> maybe Sinterrupts*)
+
+val _ = Define `
+ ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var=
+ ((case merge_var of Regval_Sinterrupts (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Sinterrupts : Sinterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sinterrupts:Sinterrupts -> register_value) v= (Regval_Sinterrupts v))`;
+
+
+(*val TLB_Entry_9_32_34_32_of_regval : register_value -> maybe (TLB_Entry ty9 ty32 ty34 ty32)*)
+
+val _ = Define `
+ ((TLB_Entry_9_32_34_32_of_regval:register_value ->(((9),(32),(34),(32))TLB_Entry)option) merge_var=
+ ((case merge_var of Regval_TLB_Entry_9_32_34_32 (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_TLB_Entry_9_32_34_32 : TLB_Entry ty9 ty32 ty34 ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLB_Entry_9_32_34_32:((9),(32),(34),(32))TLB_Entry -> register_value) v= (Regval_TLB_Entry_9_32_34_32 v))`;
+
+
+(*val bool_of_regval : register_value -> maybe bool*)
+
+val _ = Define `
+ ((bool_of_regval:register_value ->(bool)option) merge_var= ((case merge_var of Regval_bool (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_bool : bool -> register_value*)
+
+val _ = Define `
+ ((regval_of_bool:bool -> register_value) v= (Regval_bool v))`;
+
+
+(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=
+ ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
+ ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1=
+ (\x . (case x of
+ Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1=
+ (\x . (case x of
+ Regval_list v => just_list (MAP of_regval1 v)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1=
+ (\x . (case x of
+ Regval_option v => SOME (OPTION_BIND v of_regval1)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`;
+
+
+
+val _ = Define `
+ ((satp_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "satp";
+ read_from := (\ s . s.satp);
+ write_to := (\ v s . (( s with<| satp := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((tlb32_ref:((regstate),(register_value),((((9),(32),(34),(32))TLB_Entry)option))register_ref)= (<|
+ name := "tlb32";
+ read_from := (\ s . s.tlb32);
+ write_to := (\ v s . (( s with<| tlb32 := v |>)));
+ of_regval := (\ v . option_of_regval (\ v . TLB_Entry_9_32_34_32_of_regval v) v);
+ regval_of := (\ v . regval_of_option (\ v . regval_of_TLB_Entry_9_32_34_32 v) v) |>))`;
+
+
+val _ = Define `
+ ((htif_exit_code_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "htif_exit_code";
+ read_from := (\ s . s.htif_exit_code);
+ write_to := (\ v s . (( s with<| htif_exit_code := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((htif_done_ref:((regstate),(register_value),(bool))register_ref)= (<|
+ name := "htif_done";
+ read_from := (\ s . s.htif_done);
+ write_to := (\ v s . (( s with<| htif_done := v |>)));
+ of_regval := (\ v . bool_of_regval v);
+ regval_of := (\ v . regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((htif_tohost_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "htif_tohost";
+ read_from := (\ s . s.htif_tohost);
+ write_to := (\ v s . (( s with<| htif_tohost := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtimecmp_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mtimecmp";
+ read_from := (\ s . s.mtimecmp);
+ write_to := (\ v s . (( s with<| mtimecmp := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((utval_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "utval";
+ read_from := (\ s . s.utval);
+ write_to := (\ v s . (( s with<| utval := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ucause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "ucause";
+ read_from := (\ s . s.ucause);
+ write_to := (\ v s . (( s with<| ucause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((uepc_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "uepc";
+ read_from := (\ s . s.uepc);
+ write_to := (\ v s . (( s with<| uepc := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((uscratch_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "uscratch";
+ read_from := (\ s . s.uscratch);
+ write_to := (\ v s . (( s with<| uscratch := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((utvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "utvec";
+ read_from := (\ s . s.utvec);
+ write_to := (\ v s . (( s with<| utvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr15_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr15";
+ read_from := (\ s . s.pmpaddr15);
+ write_to := (\ v s . (( s with<| pmpaddr15 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr14_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr14";
+ read_from := (\ s . s.pmpaddr14);
+ write_to := (\ v s . (( s with<| pmpaddr14 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr13_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr13";
+ read_from := (\ s . s.pmpaddr13);
+ write_to := (\ v s . (( s with<| pmpaddr13 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr12_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr12";
+ read_from := (\ s . s.pmpaddr12);
+ write_to := (\ v s . (( s with<| pmpaddr12 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr11_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr11";
+ read_from := (\ s . s.pmpaddr11);
+ write_to := (\ v s . (( s with<| pmpaddr11 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr10_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr10";
+ read_from := (\ s . s.pmpaddr10);
+ write_to := (\ v s . (( s with<| pmpaddr10 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr9_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr9";
+ read_from := (\ s . s.pmpaddr9);
+ write_to := (\ v s . (( s with<| pmpaddr9 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr8_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr8";
+ read_from := (\ s . s.pmpaddr8);
+ write_to := (\ v s . (( s with<| pmpaddr8 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr7_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr7";
+ read_from := (\ s . s.pmpaddr7);
+ write_to := (\ v s . (( s with<| pmpaddr7 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr6_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr6";
+ read_from := (\ s . s.pmpaddr6);
+ write_to := (\ v s . (( s with<| pmpaddr6 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr5_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr5";
+ read_from := (\ s . s.pmpaddr5);
+ write_to := (\ v s . (( s with<| pmpaddr5 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr4_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr4";
+ read_from := (\ s . s.pmpaddr4);
+ write_to := (\ v s . (( s with<| pmpaddr4 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr3";
+ read_from := (\ s . s.pmpaddr3);
+ write_to := (\ v s . (( s with<| pmpaddr3 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr2";
+ read_from := (\ s . s.pmpaddr2);
+ write_to := (\ v s . (( s with<| pmpaddr2 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr1";
+ read_from := (\ s . s.pmpaddr1);
+ write_to := (\ v s . (( s with<| pmpaddr1 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr0_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "pmpaddr0";
+ read_from := (\ s . s.pmpaddr0);
+ write_to := (\ v s . (( s with<| pmpaddr0 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmp15cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp15cfg";
+ read_from := (\ s . s.pmp15cfg);
+ write_to := (\ v s . (( s with<| pmp15cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp14cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp14cfg";
+ read_from := (\ s . s.pmp14cfg);
+ write_to := (\ v s . (( s with<| pmp14cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp13cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp13cfg";
+ read_from := (\ s . s.pmp13cfg);
+ write_to := (\ v s . (( s with<| pmp13cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp12cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp12cfg";
+ read_from := (\ s . s.pmp12cfg);
+ write_to := (\ v s . (( s with<| pmp12cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp11cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp11cfg";
+ read_from := (\ s . s.pmp11cfg);
+ write_to := (\ v s . (( s with<| pmp11cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp10cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp10cfg";
+ read_from := (\ s . s.pmp10cfg);
+ write_to := (\ v s . (( s with<| pmp10cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp9cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp9cfg";
+ read_from := (\ s . s.pmp9cfg);
+ write_to := (\ v s . (( s with<| pmp9cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp8cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp8cfg";
+ read_from := (\ s . s.pmp8cfg);
+ write_to := (\ v s . (( s with<| pmp8cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp7cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp7cfg";
+ read_from := (\ s . s.pmp7cfg);
+ write_to := (\ v s . (( s with<| pmp7cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp6cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp6cfg";
+ read_from := (\ s . s.pmp6cfg);
+ write_to := (\ v s . (( s with<| pmp6cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp5cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp5cfg";
+ read_from := (\ s . s.pmp5cfg);
+ write_to := (\ v s . (( s with<| pmp5cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp4cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp4cfg";
+ read_from := (\ s . s.pmp4cfg);
+ write_to := (\ v s . (( s with<| pmp4cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp3cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp3cfg";
+ read_from := (\ s . s.pmp3cfg);
+ write_to := (\ v s . (( s with<| pmp3cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp2cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp2cfg";
+ read_from := (\ s . s.pmp2cfg);
+ write_to := (\ v s . (( s with<| pmp2cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp1cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp1cfg";
+ read_from := (\ s . s.pmp1cfg);
+ write_to := (\ v s . (( s with<| pmp1cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp0cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp0cfg";
+ read_from := (\ s . s.pmp0cfg);
+ write_to := (\ v s . (( s with<| pmp0cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((tselect_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "tselect";
+ read_from := (\ s . s.tselect);
+ write_to := (\ v s . (( s with<| tselect := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((stval_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "stval";
+ read_from := (\ s . s.stval);
+ write_to := (\ v s . (( s with<| stval := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((scause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "scause";
+ read_from := (\ s . s.scause);
+ write_to := (\ v s . (( s with<| scause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((sepc_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "sepc";
+ read_from := (\ s . s.sepc);
+ write_to := (\ v s . (( s with<| sepc := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((sscratch_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "sscratch";
+ read_from := (\ s . s.sscratch);
+ write_to := (\ v s . (( s with<| sscratch := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((stvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "stvec";
+ read_from := (\ s . s.stvec);
+ write_to := (\ v s . (( s with<| stvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((sideleg_ref:((regstate),(register_value),(Sinterrupts))register_ref)= (<|
+ name := "sideleg";
+ read_from := (\ s . s.sideleg);
+ write_to := (\ v s . (( s with<| sideleg := v |>)));
+ of_regval := (\ v . Sinterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Sinterrupts v) |>))`;
+
+
+val _ = Define `
+ ((sedeleg_ref:((regstate),(register_value),(Sedeleg))register_ref)= (<|
+ name := "sedeleg";
+ read_from := (\ s . s.sedeleg);
+ write_to := (\ v s . (( s with<| sedeleg := v |>)));
+ of_regval := (\ v . Sedeleg_of_regval v);
+ regval_of := (\ v . regval_of_Sedeleg v) |>))`;
+
+
+val _ = Define `
+ ((mhartid_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mhartid";
+ read_from := (\ s . s.mhartid);
+ write_to := (\ v s . (( s with<| mhartid := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((marchid_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "marchid";
+ read_from := (\ s . s.marchid);
+ write_to := (\ v s . (( s with<| marchid := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mimpid_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mimpid";
+ read_from := (\ s . s.mimpid);
+ write_to := (\ v s . (( s with<| mimpid := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mvendorid_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mvendorid";
+ read_from := (\ s . s.mvendorid);
+ write_to := (\ v s . (( s with<| mvendorid := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((minstret_written_ref:((regstate),(register_value),(bool))register_ref)= (<|
+ name := "minstret_written";
+ read_from := (\ s . s.minstret_written);
+ write_to := (\ v s . (( s with<| minstret_written := v |>)));
+ of_regval := (\ v . bool_of_regval v);
+ regval_of := (\ v . regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((minstret_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "minstret";
+ read_from := (\ s . s.minstret);
+ write_to := (\ v s . (( s with<| minstret := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtime_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mtime";
+ read_from := (\ s . s.mtime);
+ write_to := (\ v s . (( s with<| mtime := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcycle_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mcycle";
+ read_from := (\ s . s.mcycle);
+ write_to := (\ v s . (( s with<| mcycle := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((scounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<|
+ name := "scounteren";
+ read_from := (\ s . s.scounteren);
+ write_to := (\ v s . (( s with<| scounteren := v |>)));
+ of_regval := (\ v . Counteren_of_regval v);
+ regval_of := (\ v . regval_of_Counteren v) |>))`;
+
+
+val _ = Define `
+ ((mcounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<|
+ name := "mcounteren";
+ read_from := (\ s . s.mcounteren);
+ write_to := (\ v s . (( s with<| mcounteren := v |>)));
+ of_regval := (\ v . Counteren_of_regval v);
+ regval_of := (\ v . regval_of_Counteren v) |>))`;
+
+
+val _ = Define `
+ ((mscratch_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mscratch";
+ read_from := (\ s . s.mscratch);
+ write_to := (\ v s . (( s with<| mscratch := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtval_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mtval";
+ read_from := (\ s . s.mtval);
+ write_to := (\ v s . (( s with<| mtval := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mepc_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mepc";
+ read_from := (\ s . s.mepc);
+ write_to := (\ v s . (( s with<| mepc := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "mcause";
+ read_from := (\ s . s.mcause);
+ write_to := (\ v s . (( s with<| mcause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((mtvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "mtvec";
+ read_from := (\ s . s.mtvec);
+ write_to := (\ v s . (( s with<| mtvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((medeleg_ref:((regstate),(register_value),(Medeleg))register_ref)= (<|
+ name := "medeleg";
+ read_from := (\ s . s.medeleg);
+ write_to := (\ v s . (( s with<| medeleg := v |>)));
+ of_regval := (\ v . Medeleg_of_regval v);
+ regval_of := (\ v . regval_of_Medeleg v) |>))`;
+
+
+val _ = Define `
+ ((mideleg_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mideleg";
+ read_from := (\ s . s.mideleg);
+ write_to := (\ v s . (( s with<| mideleg := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mie_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mie";
+ read_from := (\ s . s.mie);
+ write_to := (\ v s . (( s with<| mie := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mip_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mip";
+ read_from := (\ s . s.mip);
+ write_to := (\ v s . (( s with<| mip := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mstatus_ref:((regstate),(register_value),(Mstatus))register_ref)= (<|
+ name := "mstatus";
+ read_from := (\ s . s.mstatus);
+ write_to := (\ v s . (( s with<| mstatus := v |>)));
+ of_regval := (\ v . Mstatus_of_regval v);
+ regval_of := (\ v . regval_of_Mstatus v) |>))`;
+
+
+val _ = Define `
+ ((misa_ref:((regstate),(register_value),(Misa))register_ref)= (<|
+ name := "misa";
+ read_from := (\ s . s.misa);
+ write_to := (\ v s . (( s with<| misa := v |>)));
+ of_regval := (\ v . Misa_of_regval v);
+ regval_of := (\ v . regval_of_Misa v) |>))`;
+
+
+val _ = Define `
+ ((cur_inst_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "cur_inst";
+ read_from := (\ s . s.cur_inst);
+ write_to := (\ v s . (( s with<| cur_inst := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((cur_privilege_ref:((regstate),(register_value),(Privilege))register_ref)= (<|
+ name := "cur_privilege";
+ read_from := (\ s . s.cur_privilege);
+ write_to := (\ v s . (( s with<| cur_privilege := v |>)));
+ of_regval := (\ v . Privilege_of_regval v);
+ regval_of := (\ v . regval_of_Privilege v) |>))`;
+
+
+val _ = Define `
+ ((x31_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x31";
+ read_from := (\ s . s.x31);
+ write_to := (\ v s . (( s with<| x31 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x30_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x30";
+ read_from := (\ s . s.x30);
+ write_to := (\ v s . (( s with<| x30 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x29_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x29";
+ read_from := (\ s . s.x29);
+ write_to := (\ v s . (( s with<| x29 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x28_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x28";
+ read_from := (\ s . s.x28);
+ write_to := (\ v s . (( s with<| x28 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x27_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x27";
+ read_from := (\ s . s.x27);
+ write_to := (\ v s . (( s with<| x27 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x26_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x26";
+ read_from := (\ s . s.x26);
+ write_to := (\ v s . (( s with<| x26 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x25_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x25";
+ read_from := (\ s . s.x25);
+ write_to := (\ v s . (( s with<| x25 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x24_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x24";
+ read_from := (\ s . s.x24);
+ write_to := (\ v s . (( s with<| x24 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x23_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x23";
+ read_from := (\ s . s.x23);
+ write_to := (\ v s . (( s with<| x23 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x22_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x22";
+ read_from := (\ s . s.x22);
+ write_to := (\ v s . (( s with<| x22 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x21_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x21";
+ read_from := (\ s . s.x21);
+ write_to := (\ v s . (( s with<| x21 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x20_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x20";
+ read_from := (\ s . s.x20);
+ write_to := (\ v s . (( s with<| x20 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x19_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x19";
+ read_from := (\ s . s.x19);
+ write_to := (\ v s . (( s with<| x19 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x18_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x18";
+ read_from := (\ s . s.x18);
+ write_to := (\ v s . (( s with<| x18 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x17_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x17";
+ read_from := (\ s . s.x17);
+ write_to := (\ v s . (( s with<| x17 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x16_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x16";
+ read_from := (\ s . s.x16);
+ write_to := (\ v s . (( s with<| x16 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x15_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x15";
+ read_from := (\ s . s.x15);
+ write_to := (\ v s . (( s with<| x15 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x14_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x14";
+ read_from := (\ s . s.x14);
+ write_to := (\ v s . (( s with<| x14 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x13_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x13";
+ read_from := (\ s . s.x13);
+ write_to := (\ v s . (( s with<| x13 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x12_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x12";
+ read_from := (\ s . s.x12);
+ write_to := (\ v s . (( s with<| x12 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x11_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x11";
+ read_from := (\ s . s.x11);
+ write_to := (\ v s . (( s with<| x11 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x10_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x10";
+ read_from := (\ s . s.x10);
+ write_to := (\ v s . (( s with<| x10 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x9_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x9";
+ read_from := (\ s . s.x9);
+ write_to := (\ v s . (( s with<| x9 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x8_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x8";
+ read_from := (\ s . s.x8);
+ write_to := (\ v s . (( s with<| x8 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x7_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x7";
+ read_from := (\ s . s.x7);
+ write_to := (\ v s . (( s with<| x7 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x6_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x6";
+ read_from := (\ s . s.x6);
+ write_to := (\ v s . (( s with<| x6 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x5_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x5";
+ read_from := (\ s . s.x5);
+ write_to := (\ v s . (( s with<| x5 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x4_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x4";
+ read_from := (\ s . s.x4);
+ write_to := (\ v s . (( s with<| x4 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x3";
+ read_from := (\ s . s.x3);
+ write_to := (\ v s . (( s with<| x3 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x2";
+ read_from := (\ s . s.x2);
+ write_to := (\ v s . (( s with<| x2 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "x1";
+ read_from := (\ s . s.x1);
+ write_to := (\ v s . (( s with<| x1 := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((Xs_ref:((regstate),(register_value),(((32)words$word)list))register_ref)= (<|
+ name := "Xs";
+ read_from := (\ s . s.Xs);
+ write_to := (\ v s . (( s with<| Xs := v |>)));
+ of_regval := (\ v . vector_of_regval (\ v . vector_32_dec_bit_of_regval v) v);
+ regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_32_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((instbits_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "instbits";
+ read_from := (\ s . s.instbits);
+ write_to := (\ v s . (( s with<| instbits := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((nextPC_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "nextPC";
+ read_from := (\ s . s.nextPC);
+ write_to := (\ v s . (( s with<| nextPC := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "PC";
+ read_from := (\ s . s.PC);
+ write_to := (\ v s . (( s with<| PC := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+(*val get_regval : string -> regstate -> maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=
+ (if reg_name = "satp" then SOME (satp_ref.regval_of (satp_ref.read_from s)) else
+ if reg_name = "tlb32" then SOME (tlb32_ref.regval_of (tlb32_ref.read_from s)) else
+ if reg_name = "htif_exit_code" then SOME (htif_exit_code_ref.regval_of (htif_exit_code_ref.read_from s)) else
+ if reg_name = "htif_done" then SOME (htif_done_ref.regval_of (htif_done_ref.read_from s)) else
+ if reg_name = "htif_tohost" then SOME (htif_tohost_ref.regval_of (htif_tohost_ref.read_from s)) else
+ if reg_name = "mtimecmp" then SOME (mtimecmp_ref.regval_of (mtimecmp_ref.read_from s)) else
+ if reg_name = "utval" then SOME (utval_ref.regval_of (utval_ref.read_from s)) else
+ if reg_name = "ucause" then SOME (ucause_ref.regval_of (ucause_ref.read_from s)) else
+ if reg_name = "uepc" then SOME (uepc_ref.regval_of (uepc_ref.read_from s)) else
+ if reg_name = "uscratch" then SOME (uscratch_ref.regval_of (uscratch_ref.read_from s)) else
+ if reg_name = "utvec" then SOME (utvec_ref.regval_of (utvec_ref.read_from s)) else
+ if reg_name = "pmpaddr15" then SOME (pmpaddr15_ref.regval_of (pmpaddr15_ref.read_from s)) else
+ if reg_name = "pmpaddr14" then SOME (pmpaddr14_ref.regval_of (pmpaddr14_ref.read_from s)) else
+ if reg_name = "pmpaddr13" then SOME (pmpaddr13_ref.regval_of (pmpaddr13_ref.read_from s)) else
+ if reg_name = "pmpaddr12" then SOME (pmpaddr12_ref.regval_of (pmpaddr12_ref.read_from s)) else
+ if reg_name = "pmpaddr11" then SOME (pmpaddr11_ref.regval_of (pmpaddr11_ref.read_from s)) else
+ if reg_name = "pmpaddr10" then SOME (pmpaddr10_ref.regval_of (pmpaddr10_ref.read_from s)) else
+ if reg_name = "pmpaddr9" then SOME (pmpaddr9_ref.regval_of (pmpaddr9_ref.read_from s)) else
+ if reg_name = "pmpaddr8" then SOME (pmpaddr8_ref.regval_of (pmpaddr8_ref.read_from s)) else
+ if reg_name = "pmpaddr7" then SOME (pmpaddr7_ref.regval_of (pmpaddr7_ref.read_from s)) else
+ if reg_name = "pmpaddr6" then SOME (pmpaddr6_ref.regval_of (pmpaddr6_ref.read_from s)) else
+ if reg_name = "pmpaddr5" then SOME (pmpaddr5_ref.regval_of (pmpaddr5_ref.read_from s)) else
+ if reg_name = "pmpaddr4" then SOME (pmpaddr4_ref.regval_of (pmpaddr4_ref.read_from s)) else
+ if reg_name = "pmpaddr3" then SOME (pmpaddr3_ref.regval_of (pmpaddr3_ref.read_from s)) else
+ if reg_name = "pmpaddr2" then SOME (pmpaddr2_ref.regval_of (pmpaddr2_ref.read_from s)) else
+ if reg_name = "pmpaddr1" then SOME (pmpaddr1_ref.regval_of (pmpaddr1_ref.read_from s)) else
+ if reg_name = "pmpaddr0" then SOME (pmpaddr0_ref.regval_of (pmpaddr0_ref.read_from s)) else
+ if reg_name = "pmp15cfg" then SOME (pmp15cfg_ref.regval_of (pmp15cfg_ref.read_from s)) else
+ if reg_name = "pmp14cfg" then SOME (pmp14cfg_ref.regval_of (pmp14cfg_ref.read_from s)) else
+ if reg_name = "pmp13cfg" then SOME (pmp13cfg_ref.regval_of (pmp13cfg_ref.read_from s)) else
+ if reg_name = "pmp12cfg" then SOME (pmp12cfg_ref.regval_of (pmp12cfg_ref.read_from s)) else
+ if reg_name = "pmp11cfg" then SOME (pmp11cfg_ref.regval_of (pmp11cfg_ref.read_from s)) else
+ if reg_name = "pmp10cfg" then SOME (pmp10cfg_ref.regval_of (pmp10cfg_ref.read_from s)) else
+ if reg_name = "pmp9cfg" then SOME (pmp9cfg_ref.regval_of (pmp9cfg_ref.read_from s)) else
+ if reg_name = "pmp8cfg" then SOME (pmp8cfg_ref.regval_of (pmp8cfg_ref.read_from s)) else
+ if reg_name = "pmp7cfg" then SOME (pmp7cfg_ref.regval_of (pmp7cfg_ref.read_from s)) else
+ if reg_name = "pmp6cfg" then SOME (pmp6cfg_ref.regval_of (pmp6cfg_ref.read_from s)) else
+ if reg_name = "pmp5cfg" then SOME (pmp5cfg_ref.regval_of (pmp5cfg_ref.read_from s)) else
+ if reg_name = "pmp4cfg" then SOME (pmp4cfg_ref.regval_of (pmp4cfg_ref.read_from s)) else
+ if reg_name = "pmp3cfg" then SOME (pmp3cfg_ref.regval_of (pmp3cfg_ref.read_from s)) else
+ if reg_name = "pmp2cfg" then SOME (pmp2cfg_ref.regval_of (pmp2cfg_ref.read_from s)) else
+ if reg_name = "pmp1cfg" then SOME (pmp1cfg_ref.regval_of (pmp1cfg_ref.read_from s)) else
+ if reg_name = "pmp0cfg" then SOME (pmp0cfg_ref.regval_of (pmp0cfg_ref.read_from s)) else
+ if reg_name = "tselect" then SOME (tselect_ref.regval_of (tselect_ref.read_from s)) else
+ if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else
+ if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else
+ if reg_name = "sepc" then SOME (sepc_ref.regval_of (sepc_ref.read_from s)) else
+ if reg_name = "sscratch" then SOME (sscratch_ref.regval_of (sscratch_ref.read_from s)) else
+ if reg_name = "stvec" then SOME (stvec_ref.regval_of (stvec_ref.read_from s)) else
+ if reg_name = "sideleg" then SOME (sideleg_ref.regval_of (sideleg_ref.read_from s)) else
+ if reg_name = "sedeleg" then SOME (sedeleg_ref.regval_of (sedeleg_ref.read_from s)) else
+ if reg_name = "mhartid" then SOME (mhartid_ref.regval_of (mhartid_ref.read_from s)) else
+ if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else
+ if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else
+ if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else
+ if reg_name = "minstret_written" then SOME (minstret_written_ref.regval_of (minstret_written_ref.read_from s)) else
+ if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else
+ if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else
+ if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else
+ if reg_name = "scounteren" then SOME (scounteren_ref.regval_of (scounteren_ref.read_from s)) else
+ if reg_name = "mcounteren" then SOME (mcounteren_ref.regval_of (mcounteren_ref.read_from s)) else
+ if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else
+ if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else
+ if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else
+ if reg_name = "mcause" then SOME (mcause_ref.regval_of (mcause_ref.read_from s)) else
+ if reg_name = "mtvec" then SOME (mtvec_ref.regval_of (mtvec_ref.read_from s)) else
+ if reg_name = "medeleg" then SOME (medeleg_ref.regval_of (medeleg_ref.read_from s)) else
+ if reg_name = "mideleg" then SOME (mideleg_ref.regval_of (mideleg_ref.read_from s)) else
+ if reg_name = "mie" then SOME (mie_ref.regval_of (mie_ref.read_from s)) else
+ if reg_name = "mip" then SOME (mip_ref.regval_of (mip_ref.read_from s)) else
+ if reg_name = "mstatus" then SOME (mstatus_ref.regval_of (mstatus_ref.read_from s)) else
+ if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else
+ if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else
+ if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else
+ if reg_name = "x31" then SOME (x31_ref.regval_of (x31_ref.read_from s)) else
+ if reg_name = "x30" then SOME (x30_ref.regval_of (x30_ref.read_from s)) else
+ if reg_name = "x29" then SOME (x29_ref.regval_of (x29_ref.read_from s)) else
+ if reg_name = "x28" then SOME (x28_ref.regval_of (x28_ref.read_from s)) else
+ if reg_name = "x27" then SOME (x27_ref.regval_of (x27_ref.read_from s)) else
+ if reg_name = "x26" then SOME (x26_ref.regval_of (x26_ref.read_from s)) else
+ if reg_name = "x25" then SOME (x25_ref.regval_of (x25_ref.read_from s)) else
+ if reg_name = "x24" then SOME (x24_ref.regval_of (x24_ref.read_from s)) else
+ if reg_name = "x23" then SOME (x23_ref.regval_of (x23_ref.read_from s)) else
+ if reg_name = "x22" then SOME (x22_ref.regval_of (x22_ref.read_from s)) else
+ if reg_name = "x21" then SOME (x21_ref.regval_of (x21_ref.read_from s)) else
+ if reg_name = "x20" then SOME (x20_ref.regval_of (x20_ref.read_from s)) else
+ if reg_name = "x19" then SOME (x19_ref.regval_of (x19_ref.read_from s)) else
+ if reg_name = "x18" then SOME (x18_ref.regval_of (x18_ref.read_from s)) else
+ if reg_name = "x17" then SOME (x17_ref.regval_of (x17_ref.read_from s)) else
+ if reg_name = "x16" then SOME (x16_ref.regval_of (x16_ref.read_from s)) else
+ if reg_name = "x15" then SOME (x15_ref.regval_of (x15_ref.read_from s)) else
+ if reg_name = "x14" then SOME (x14_ref.regval_of (x14_ref.read_from s)) else
+ if reg_name = "x13" then SOME (x13_ref.regval_of (x13_ref.read_from s)) else
+ if reg_name = "x12" then SOME (x12_ref.regval_of (x12_ref.read_from s)) else
+ if reg_name = "x11" then SOME (x11_ref.regval_of (x11_ref.read_from s)) else
+ if reg_name = "x10" then SOME (x10_ref.regval_of (x10_ref.read_from s)) else
+ if reg_name = "x9" then SOME (x9_ref.regval_of (x9_ref.read_from s)) else
+ if reg_name = "x8" then SOME (x8_ref.regval_of (x8_ref.read_from s)) else
+ if reg_name = "x7" then SOME (x7_ref.regval_of (x7_ref.read_from s)) else
+ if reg_name = "x6" then SOME (x6_ref.regval_of (x6_ref.read_from s)) else
+ if reg_name = "x5" then SOME (x5_ref.regval_of (x5_ref.read_from s)) else
+ if reg_name = "x4" then SOME (x4_ref.regval_of (x4_ref.read_from s)) else
+ if reg_name = "x3" then SOME (x3_ref.regval_of (x3_ref.read_from s)) else
+ if reg_name = "x2" then SOME (x2_ref.regval_of (x2_ref.read_from s)) else
+ if reg_name = "x1" then SOME (x1_ref.regval_of (x1_ref.read_from s)) else
+ if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else
+ if reg_name = "instbits" then SOME (instbits_ref.regval_of (instbits_ref.read_from s)) else
+ if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
+ if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+ NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
+ (if reg_name = "satp" then OPTION_MAP (\ v . satp_ref.write_to v s) (satp_ref.of_regval v) else
+ if reg_name = "tlb32" then OPTION_MAP (\ v . tlb32_ref.write_to v s) (tlb32_ref.of_regval v) else
+ if reg_name = "htif_exit_code" then OPTION_MAP (\ v . htif_exit_code_ref.write_to v s) (htif_exit_code_ref.of_regval v) else
+ if reg_name = "htif_done" then OPTION_MAP (\ v . htif_done_ref.write_to v s) (htif_done_ref.of_regval v) else
+ if reg_name = "htif_tohost" then OPTION_MAP (\ v . htif_tohost_ref.write_to v s) (htif_tohost_ref.of_regval v) else
+ if reg_name = "mtimecmp" then OPTION_MAP (\ v . mtimecmp_ref.write_to v s) (mtimecmp_ref.of_regval v) else
+ if reg_name = "utval" then OPTION_MAP (\ v . utval_ref.write_to v s) (utval_ref.of_regval v) else
+ if reg_name = "ucause" then OPTION_MAP (\ v . ucause_ref.write_to v s) (ucause_ref.of_regval v) else
+ if reg_name = "uepc" then OPTION_MAP (\ v . uepc_ref.write_to v s) (uepc_ref.of_regval v) else
+ if reg_name = "uscratch" then OPTION_MAP (\ v . uscratch_ref.write_to v s) (uscratch_ref.of_regval v) else
+ if reg_name = "utvec" then OPTION_MAP (\ v . utvec_ref.write_to v s) (utvec_ref.of_regval v) else
+ if reg_name = "pmpaddr15" then OPTION_MAP (\ v . pmpaddr15_ref.write_to v s) (pmpaddr15_ref.of_regval v) else
+ if reg_name = "pmpaddr14" then OPTION_MAP (\ v . pmpaddr14_ref.write_to v s) (pmpaddr14_ref.of_regval v) else
+ if reg_name = "pmpaddr13" then OPTION_MAP (\ v . pmpaddr13_ref.write_to v s) (pmpaddr13_ref.of_regval v) else
+ if reg_name = "pmpaddr12" then OPTION_MAP (\ v . pmpaddr12_ref.write_to v s) (pmpaddr12_ref.of_regval v) else
+ if reg_name = "pmpaddr11" then OPTION_MAP (\ v . pmpaddr11_ref.write_to v s) (pmpaddr11_ref.of_regval v) else
+ if reg_name = "pmpaddr10" then OPTION_MAP (\ v . pmpaddr10_ref.write_to v s) (pmpaddr10_ref.of_regval v) else
+ if reg_name = "pmpaddr9" then OPTION_MAP (\ v . pmpaddr9_ref.write_to v s) (pmpaddr9_ref.of_regval v) else
+ if reg_name = "pmpaddr8" then OPTION_MAP (\ v . pmpaddr8_ref.write_to v s) (pmpaddr8_ref.of_regval v) else
+ if reg_name = "pmpaddr7" then OPTION_MAP (\ v . pmpaddr7_ref.write_to v s) (pmpaddr7_ref.of_regval v) else
+ if reg_name = "pmpaddr6" then OPTION_MAP (\ v . pmpaddr6_ref.write_to v s) (pmpaddr6_ref.of_regval v) else
+ if reg_name = "pmpaddr5" then OPTION_MAP (\ v . pmpaddr5_ref.write_to v s) (pmpaddr5_ref.of_regval v) else
+ if reg_name = "pmpaddr4" then OPTION_MAP (\ v . pmpaddr4_ref.write_to v s) (pmpaddr4_ref.of_regval v) else
+ if reg_name = "pmpaddr3" then OPTION_MAP (\ v . pmpaddr3_ref.write_to v s) (pmpaddr3_ref.of_regval v) else
+ if reg_name = "pmpaddr2" then OPTION_MAP (\ v . pmpaddr2_ref.write_to v s) (pmpaddr2_ref.of_regval v) else
+ if reg_name = "pmpaddr1" then OPTION_MAP (\ v . pmpaddr1_ref.write_to v s) (pmpaddr1_ref.of_regval v) else
+ if reg_name = "pmpaddr0" then OPTION_MAP (\ v . pmpaddr0_ref.write_to v s) (pmpaddr0_ref.of_regval v) else
+ if reg_name = "pmp15cfg" then OPTION_MAP (\ v . pmp15cfg_ref.write_to v s) (pmp15cfg_ref.of_regval v) else
+ if reg_name = "pmp14cfg" then OPTION_MAP (\ v . pmp14cfg_ref.write_to v s) (pmp14cfg_ref.of_regval v) else
+ if reg_name = "pmp13cfg" then OPTION_MAP (\ v . pmp13cfg_ref.write_to v s) (pmp13cfg_ref.of_regval v) else
+ if reg_name = "pmp12cfg" then OPTION_MAP (\ v . pmp12cfg_ref.write_to v s) (pmp12cfg_ref.of_regval v) else
+ if reg_name = "pmp11cfg" then OPTION_MAP (\ v . pmp11cfg_ref.write_to v s) (pmp11cfg_ref.of_regval v) else
+ if reg_name = "pmp10cfg" then OPTION_MAP (\ v . pmp10cfg_ref.write_to v s) (pmp10cfg_ref.of_regval v) else
+ if reg_name = "pmp9cfg" then OPTION_MAP (\ v . pmp9cfg_ref.write_to v s) (pmp9cfg_ref.of_regval v) else
+ if reg_name = "pmp8cfg" then OPTION_MAP (\ v . pmp8cfg_ref.write_to v s) (pmp8cfg_ref.of_regval v) else
+ if reg_name = "pmp7cfg" then OPTION_MAP (\ v . pmp7cfg_ref.write_to v s) (pmp7cfg_ref.of_regval v) else
+ if reg_name = "pmp6cfg" then OPTION_MAP (\ v . pmp6cfg_ref.write_to v s) (pmp6cfg_ref.of_regval v) else
+ if reg_name = "pmp5cfg" then OPTION_MAP (\ v . pmp5cfg_ref.write_to v s) (pmp5cfg_ref.of_regval v) else
+ if reg_name = "pmp4cfg" then OPTION_MAP (\ v . pmp4cfg_ref.write_to v s) (pmp4cfg_ref.of_regval v) else
+ if reg_name = "pmp3cfg" then OPTION_MAP (\ v . pmp3cfg_ref.write_to v s) (pmp3cfg_ref.of_regval v) else
+ if reg_name = "pmp2cfg" then OPTION_MAP (\ v . pmp2cfg_ref.write_to v s) (pmp2cfg_ref.of_regval v) else
+ if reg_name = "pmp1cfg" then OPTION_MAP (\ v . pmp1cfg_ref.write_to v s) (pmp1cfg_ref.of_regval v) else
+ if reg_name = "pmp0cfg" then OPTION_MAP (\ v . pmp0cfg_ref.write_to v s) (pmp0cfg_ref.of_regval v) else
+ if reg_name = "tselect" then OPTION_MAP (\ v . tselect_ref.write_to v s) (tselect_ref.of_regval v) else
+ if reg_name = "stval" then OPTION_MAP (\ v . stval_ref.write_to v s) (stval_ref.of_regval v) else
+ if reg_name = "scause" then OPTION_MAP (\ v . scause_ref.write_to v s) (scause_ref.of_regval v) else
+ if reg_name = "sepc" then OPTION_MAP (\ v . sepc_ref.write_to v s) (sepc_ref.of_regval v) else
+ if reg_name = "sscratch" then OPTION_MAP (\ v . sscratch_ref.write_to v s) (sscratch_ref.of_regval v) else
+ if reg_name = "stvec" then OPTION_MAP (\ v . stvec_ref.write_to v s) (stvec_ref.of_regval v) else
+ if reg_name = "sideleg" then OPTION_MAP (\ v . sideleg_ref.write_to v s) (sideleg_ref.of_regval v) else
+ if reg_name = "sedeleg" then OPTION_MAP (\ v . sedeleg_ref.write_to v s) (sedeleg_ref.of_regval v) else
+ if reg_name = "mhartid" then OPTION_MAP (\ v . mhartid_ref.write_to v s) (mhartid_ref.of_regval v) else
+ if reg_name = "marchid" then OPTION_MAP (\ v . marchid_ref.write_to v s) (marchid_ref.of_regval v) else
+ if reg_name = "mimpid" then OPTION_MAP (\ v . mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else
+ if reg_name = "mvendorid" then OPTION_MAP (\ v . mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else
+ if reg_name = "minstret_written" then OPTION_MAP (\ v . minstret_written_ref.write_to v s) (minstret_written_ref.of_regval v) else
+ if reg_name = "minstret" then OPTION_MAP (\ v . minstret_ref.write_to v s) (minstret_ref.of_regval v) else
+ if reg_name = "mtime" then OPTION_MAP (\ v . mtime_ref.write_to v s) (mtime_ref.of_regval v) else
+ if reg_name = "mcycle" then OPTION_MAP (\ v . mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else
+ if reg_name = "scounteren" then OPTION_MAP (\ v . scounteren_ref.write_to v s) (scounteren_ref.of_regval v) else
+ if reg_name = "mcounteren" then OPTION_MAP (\ v . mcounteren_ref.write_to v s) (mcounteren_ref.of_regval v) else
+ if reg_name = "mscratch" then OPTION_MAP (\ v . mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else
+ if reg_name = "mtval" then OPTION_MAP (\ v . mtval_ref.write_to v s) (mtval_ref.of_regval v) else
+ if reg_name = "mepc" then OPTION_MAP (\ v . mepc_ref.write_to v s) (mepc_ref.of_regval v) else
+ if reg_name = "mcause" then OPTION_MAP (\ v . mcause_ref.write_to v s) (mcause_ref.of_regval v) else
+ if reg_name = "mtvec" then OPTION_MAP (\ v . mtvec_ref.write_to v s) (mtvec_ref.of_regval v) else
+ if reg_name = "medeleg" then OPTION_MAP (\ v . medeleg_ref.write_to v s) (medeleg_ref.of_regval v) else
+ if reg_name = "mideleg" then OPTION_MAP (\ v . mideleg_ref.write_to v s) (mideleg_ref.of_regval v) else
+ if reg_name = "mie" then OPTION_MAP (\ v . mie_ref.write_to v s) (mie_ref.of_regval v) else
+ if reg_name = "mip" then OPTION_MAP (\ v . mip_ref.write_to v s) (mip_ref.of_regval v) else
+ if reg_name = "mstatus" then OPTION_MAP (\ v . mstatus_ref.write_to v s) (mstatus_ref.of_regval v) else
+ if reg_name = "misa" then OPTION_MAP (\ v . misa_ref.write_to v s) (misa_ref.of_regval v) else
+ if reg_name = "cur_inst" then OPTION_MAP (\ v . cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else
+ if reg_name = "cur_privilege" then OPTION_MAP (\ v . cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else
+ if reg_name = "x31" then OPTION_MAP (\ v . x31_ref.write_to v s) (x31_ref.of_regval v) else
+ if reg_name = "x30" then OPTION_MAP (\ v . x30_ref.write_to v s) (x30_ref.of_regval v) else
+ if reg_name = "x29" then OPTION_MAP (\ v . x29_ref.write_to v s) (x29_ref.of_regval v) else
+ if reg_name = "x28" then OPTION_MAP (\ v . x28_ref.write_to v s) (x28_ref.of_regval v) else
+ if reg_name = "x27" then OPTION_MAP (\ v . x27_ref.write_to v s) (x27_ref.of_regval v) else
+ if reg_name = "x26" then OPTION_MAP (\ v . x26_ref.write_to v s) (x26_ref.of_regval v) else
+ if reg_name = "x25" then OPTION_MAP (\ v . x25_ref.write_to v s) (x25_ref.of_regval v) else
+ if reg_name = "x24" then OPTION_MAP (\ v . x24_ref.write_to v s) (x24_ref.of_regval v) else
+ if reg_name = "x23" then OPTION_MAP (\ v . x23_ref.write_to v s) (x23_ref.of_regval v) else
+ if reg_name = "x22" then OPTION_MAP (\ v . x22_ref.write_to v s) (x22_ref.of_regval v) else
+ if reg_name = "x21" then OPTION_MAP (\ v . x21_ref.write_to v s) (x21_ref.of_regval v) else
+ if reg_name = "x20" then OPTION_MAP (\ v . x20_ref.write_to v s) (x20_ref.of_regval v) else
+ if reg_name = "x19" then OPTION_MAP (\ v . x19_ref.write_to v s) (x19_ref.of_regval v) else
+ if reg_name = "x18" then OPTION_MAP (\ v . x18_ref.write_to v s) (x18_ref.of_regval v) else
+ if reg_name = "x17" then OPTION_MAP (\ v . x17_ref.write_to v s) (x17_ref.of_regval v) else
+ if reg_name = "x16" then OPTION_MAP (\ v . x16_ref.write_to v s) (x16_ref.of_regval v) else
+ if reg_name = "x15" then OPTION_MAP (\ v . x15_ref.write_to v s) (x15_ref.of_regval v) else
+ if reg_name = "x14" then OPTION_MAP (\ v . x14_ref.write_to v s) (x14_ref.of_regval v) else
+ if reg_name = "x13" then OPTION_MAP (\ v . x13_ref.write_to v s) (x13_ref.of_regval v) else
+ if reg_name = "x12" then OPTION_MAP (\ v . x12_ref.write_to v s) (x12_ref.of_regval v) else
+ if reg_name = "x11" then OPTION_MAP (\ v . x11_ref.write_to v s) (x11_ref.of_regval v) else
+ if reg_name = "x10" then OPTION_MAP (\ v . x10_ref.write_to v s) (x10_ref.of_regval v) else
+ if reg_name = "x9" then OPTION_MAP (\ v . x9_ref.write_to v s) (x9_ref.of_regval v) else
+ if reg_name = "x8" then OPTION_MAP (\ v . x8_ref.write_to v s) (x8_ref.of_regval v) else
+ if reg_name = "x7" then OPTION_MAP (\ v . x7_ref.write_to v s) (x7_ref.of_regval v) else
+ if reg_name = "x6" then OPTION_MAP (\ v . x6_ref.write_to v s) (x6_ref.of_regval v) else
+ if reg_name = "x5" then OPTION_MAP (\ v . x5_ref.write_to v s) (x5_ref.of_regval v) else
+ if reg_name = "x4" then OPTION_MAP (\ v . x4_ref.write_to v s) (x4_ref.of_regval v) else
+ if reg_name = "x3" then OPTION_MAP (\ v . x3_ref.write_to v s) (x3_ref.of_regval v) else
+ if reg_name = "x2" then OPTION_MAP (\ v . x2_ref.write_to v s) (x2_ref.of_regval v) else
+ if reg_name = "x1" then OPTION_MAP (\ v . x1_ref.write_to v s) (x1_ref.of_regval v) else
+ if reg_name = "Xs" then OPTION_MAP (\ v . Xs_ref.write_to v s) (Xs_ref.of_regval v) else
+ if reg_name = "instbits" then OPTION_MAP (\ v . instbits_ref.write_to v s) (instbits_ref.of_regval v) else
+ if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
+ if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else
+ NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``);
+val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``);
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV64/Holmakefile b/prover_snapshots/hol4/RV64/Holmakefile
new file mode 100644
index 0000000..d90fcbe
--- /dev/null
+++ b/prover_snapshots/hol4/RV64/Holmakefile
@@ -0,0 +1,13 @@
+INCLUDES = ../lib/lem ../lib/sail
+
+SCRIPTS = riscv_extrasScript.sml riscv_typesScript.sml riscvScript.sml
+
+THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
+
+all: $(THYS)
+.PHONY: all
+
+ifdef POLY
+BASE_HEAP = ../lib/sail/sail-heap
+
+endif
diff --git a/prover_snapshots/hol4/RV64/riscvAuxiliaryScript.sml b/prover_snapshots/hol4/RV64/riscvAuxiliaryScript.sml
new file mode 100644
index 0000000..abcd699
--- /dev/null
+++ b/prover_snapshots/hol4/RV64/riscvAuxiliaryScript.sml
@@ -0,0 +1,59 @@
+(*Generated by Lem from generated_definitions/lem/RV64/riscv.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory riscvTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "riscvAuxiliary"
+
+
+(****************************************************)
+(* *)
+(* Termination Proofs *)
+(* *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (n_leading_spaces0_def, n_leading_spaces0_ind) *)
+val (n_leading_spaces0_rw, n_leading_spaces0_ind_rw) =
+ Defn.tprove_no_defn ((n_leading_spaces0_def, n_leading_spaces0_ind),
+ cheat (* the termination proof *)
+ )
+val n_leading_spaces0_rw = save_thm ("n_leading_spaces0_rw", n_leading_spaces0_rw);
+val n_leading_spaces0_ind_rw = save_thm ("n_leading_spaces0_ind_rw", n_leading_spaces0_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (walk39_def, walk39_ind) *)
+val (walk39_rw, walk39_ind_rw) =
+ Defn.tprove_no_defn ((walk39_def, walk39_ind),
+ cheat (* the termination proof *)
+ )
+val walk39_rw = save_thm ("walk39_rw", walk39_rw);
+val walk39_ind_rw = save_thm ("walk39_ind_rw", walk39_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (walk48_def, walk48_ind) *)
+val (walk48_rw, walk48_ind_rw) =
+ Defn.tprove_no_defn ((walk48_def, walk48_ind),
+ cheat (* the termination proof *)
+ )
+val walk48_rw = save_thm ("walk48_rw", walk48_rw);
+val walk48_ind_rw = save_thm ("walk48_ind_rw", walk48_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (execute_def, execute_ind) *)
+val (execute_rw, execute_ind_rw) =
+ Defn.tprove_no_defn ((execute_def, execute_ind),
+ cheat (* the termination proof *)
+ )
+val execute_rw = save_thm ("execute_rw", execute_rw);
+val execute_ind_rw = save_thm ("execute_ind_rw", execute_ind_rw);
+
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV64/riscvScript.sml b/prover_snapshots/hol4/RV64/riscvScript.sml
new file mode 100644
index 0000000..25de446
--- /dev/null
+++ b/prover_snapshots/hol4/RV64/riscvScript.sml
@@ -0,0 +1,35352 @@
+(*Generated by Lem from generated_definitions/lem/RV64/riscv.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv"
+
+(*Generated by Sail from riscv.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+(*open import Riscv_types*)
+(*open import Riscv_extras*)
+
+(*val is_none : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_none:'a option -> bool) opt= ((case opt of SOME (_) => F | NONE => T )))`;
+
+
+(*val is_some : forall 'a. maybe 'a -> bool*)
+
+val _ = Define `
+ ((is_some:'a option -> bool) opt= ((case opt of SOME (_) => T | NONE => F )))`;
+
+
+(*val eq_unit : unit -> unit -> bool*)
+
+val _ = Define `
+ ((eq_unit:unit -> unit -> bool) _ _= T)`;
+
+
+
+
+(*val neq_bool : bool -> bool -> bool*)
+
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`;
+
+
+(*val __id : integer -> integer*)
+
+val _ = Define `
+ ((id:int -> int) x= x)`;
+
+
+(*val concat_str_bits : forall 'n. Size 'n => string -> mword 'n -> string*)
+
+val _ = Define `
+ ((concat_str_bits:string -> 'n words$word -> string) str x= (STRCAT str ((string_of_bits x))))`;
+
+
+(*val concat_str_dec : string -> ii -> string*)
+
+val _ = Define `
+ ((concat_str_dec:string -> int -> string) str x= (STRCAT str ((dec_str x))))`;
+
+
+
+
+(*val sail_mask : forall 'len 'v. Size 'len, Size 'v => integer -> mword 'v -> mword 'len*)
+
+val _ = Define `
+ ((sail_mask:int -> 'v words$word -> 'len words$word) len v=
+ (if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len : 'len words$word)
+ else (zero_extend v len : 'len words$word)))`;
+
+
+(*val sail_ones : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((sail_ones:int -> 'n words$word) n= ((not_vec ((zeros n : 'n words$word)) : 'n words$word)))`;
+
+
+(*val slice_mask : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*)
+
+val _ = Define `
+ ((slice_mask:int -> int -> int -> 'n words$word) n i l=
+ (if ((l >= n)) then (shiftl ((sail_ones n : 'n words$word)) i : 'n words$word)
+ else
+ let one1 = ((sail_mask n (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in
+ (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`;
+
+
+(*val read_kind_of_num : integer -> read_kind*)
+
+val _ = Define `
+ ((read_kind_of_num:int -> read_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Read_plain
+ else if (((p0_ = (( 1 : int):ii)))) then Read_reserve
+ else if (((p0_ = (( 2 : int):ii)))) then Read_acquire
+ else if (((p0_ = (( 3 : int):ii)))) then Read_exclusive
+ else if (((p0_ = (( 4 : int):ii)))) then Read_exclusive_acquire
+ else if (((p0_ = (( 5 : int):ii)))) then Read_stream
+ else if (((p0_ = (( 6 : int):ii)))) then Read_RISCV_acquire
+ else if (((p0_ = (( 7 : int):ii)))) then Read_RISCV_strong_acquire
+ else if (((p0_ = (( 8 : int):ii)))) then Read_RISCV_reserved
+ else if (((p0_ = (( 9 : int):ii)))) then Read_RISCV_reserved_acquire
+ else if (((p0_ = (( 10 : int):ii)))) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked))`;
+
+
+(*val num_of_read_kind : read_kind -> integer*)
+
+val _ = Define `
+ ((num_of_read_kind:read_kind -> int) arg_=
+ ((case arg_ of
+ Read_plain => (( 0 : int):ii)
+ | Read_reserve => (( 1 : int):ii)
+ | Read_acquire => (( 2 : int):ii)
+ | Read_exclusive => (( 3 : int):ii)
+ | Read_exclusive_acquire => (( 4 : int):ii)
+ | Read_stream => (( 5 : int):ii)
+ | Read_RISCV_acquire => (( 6 : int):ii)
+ | Read_RISCV_strong_acquire => (( 7 : int):ii)
+ | Read_RISCV_reserved => (( 8 : int):ii)
+ | Read_RISCV_reserved_acquire => (( 9 : int):ii)
+ | Read_RISCV_reserved_strong_acquire => (( 10 : int):ii)
+ | Read_X86_locked => (( 11 : int):ii)
+ )))`;
+
+
+(*val write_kind_of_num : integer -> write_kind*)
+
+val _ = Define `
+ ((write_kind_of_num:int -> write_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Write_plain
+ else if (((p0_ = (( 1 : int):ii)))) then Write_conditional
+ else if (((p0_ = (( 2 : int):ii)))) then Write_release
+ else if (((p0_ = (( 3 : int):ii)))) then Write_exclusive
+ else if (((p0_ = (( 4 : int):ii)))) then Write_exclusive_release
+ else if (((p0_ = (( 5 : int):ii)))) then Write_RISCV_release
+ else if (((p0_ = (( 6 : int):ii)))) then Write_RISCV_strong_release
+ else if (((p0_ = (( 7 : int):ii)))) then Write_RISCV_conditional
+ else if (((p0_ = (( 8 : int):ii)))) then Write_RISCV_conditional_release
+ else if (((p0_ = (( 9 : int):ii)))) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked))`;
+
+
+(*val num_of_write_kind : write_kind -> integer*)
+
+val _ = Define `
+ ((num_of_write_kind:write_kind -> int) arg_=
+ ((case arg_ of
+ Write_plain => (( 0 : int):ii)
+ | Write_conditional => (( 1 : int):ii)
+ | Write_release => (( 2 : int):ii)
+ | Write_exclusive => (( 3 : int):ii)
+ | Write_exclusive_release => (( 4 : int):ii)
+ | Write_RISCV_release => (( 5 : int):ii)
+ | Write_RISCV_strong_release => (( 6 : int):ii)
+ | Write_RISCV_conditional => (( 7 : int):ii)
+ | Write_RISCV_conditional_release => (( 8 : int):ii)
+ | Write_RISCV_conditional_strong_release => (( 9 : int):ii)
+ | Write_X86_locked => (( 10 : int):ii)
+ )))`;
+
+
+(*val barrier_kind_of_num : integer -> barrier_kind*)
+
+val _ = Define `
+ ((barrier_kind_of_num:int -> barrier_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Barrier_Sync
+ else if (((p0_ = (( 1 : int):ii)))) then Barrier_LwSync
+ else if (((p0_ = (( 2 : int):ii)))) then Barrier_Eieio
+ else if (((p0_ = (( 3 : int):ii)))) then Barrier_Isync
+ else if (((p0_ = (( 4 : int):ii)))) then Barrier_DMB
+ else if (((p0_ = (( 5 : int):ii)))) then Barrier_DMB_ST
+ else if (((p0_ = (( 6 : int):ii)))) then Barrier_DMB_LD
+ else if (((p0_ = (( 7 : int):ii)))) then Barrier_DSB
+ else if (((p0_ = (( 8 : int):ii)))) then Barrier_DSB_ST
+ else if (((p0_ = (( 9 : int):ii)))) then Barrier_DSB_LD
+ else if (((p0_ = (( 10 : int):ii)))) then Barrier_ISB
+ else if (((p0_ = (( 11 : int):ii)))) then Barrier_MIPS_SYNC
+ else if (((p0_ = (( 12 : int):ii)))) then Barrier_RISCV_rw_rw
+ else if (((p0_ = (( 13 : int):ii)))) then Barrier_RISCV_r_rw
+ else if (((p0_ = (( 14 : int):ii)))) then Barrier_RISCV_r_r
+ else if (((p0_ = (( 15 : int):ii)))) then Barrier_RISCV_rw_w
+ else if (((p0_ = (( 16 : int):ii)))) then Barrier_RISCV_w_w
+ else if (((p0_ = (( 17 : int):ii)))) then Barrier_RISCV_w_rw
+ else if (((p0_ = (( 18 : int):ii)))) then Barrier_RISCV_rw_r
+ else if (((p0_ = (( 19 : int):ii)))) then Barrier_RISCV_r_w
+ else if (((p0_ = (( 20 : int):ii)))) then Barrier_RISCV_w_r
+ else if (((p0_ = (( 21 : int):ii)))) then Barrier_RISCV_tso
+ else if (((p0_ = (( 22 : int):ii)))) then Barrier_RISCV_i
+ else Barrier_x86_MFENCE))`;
+
+
+(*val num_of_barrier_kind : barrier_kind -> integer*)
+
+val _ = Define `
+ ((num_of_barrier_kind:barrier_kind -> int) arg_=
+ ((case arg_ of
+ Barrier_Sync => (( 0 : int):ii)
+ | Barrier_LwSync => (( 1 : int):ii)
+ | Barrier_Eieio => (( 2 : int):ii)
+ | Barrier_Isync => (( 3 : int):ii)
+ | Barrier_DMB => (( 4 : int):ii)
+ | Barrier_DMB_ST => (( 5 : int):ii)
+ | Barrier_DMB_LD => (( 6 : int):ii)
+ | Barrier_DSB => (( 7 : int):ii)
+ | Barrier_DSB_ST => (( 8 : int):ii)
+ | Barrier_DSB_LD => (( 9 : int):ii)
+ | Barrier_ISB => (( 10 : int):ii)
+ | Barrier_MIPS_SYNC => (( 11 : int):ii)
+ | Barrier_RISCV_rw_rw => (( 12 : int):ii)
+ | Barrier_RISCV_r_rw => (( 13 : int):ii)
+ | Barrier_RISCV_r_r => (( 14 : int):ii)
+ | Barrier_RISCV_rw_w => (( 15 : int):ii)
+ | Barrier_RISCV_w_w => (( 16 : int):ii)
+ | Barrier_RISCV_w_rw => (( 17 : int):ii)
+ | Barrier_RISCV_rw_r => (( 18 : int):ii)
+ | Barrier_RISCV_r_w => (( 19 : int):ii)
+ | Barrier_RISCV_w_r => (( 20 : int):ii)
+ | Barrier_RISCV_tso => (( 21 : int):ii)
+ | Barrier_RISCV_i => (( 22 : int):ii)
+ | Barrier_x86_MFENCE => (( 23 : int):ii)
+ )))`;
+
+
+(*val trans_kind_of_num : integer -> trans_kind*)
+
+val _ = Define `
+ ((trans_kind_of_num:int -> trans_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Transaction_start
+ else if (((p0_ = (( 1 : int):ii)))) then Transaction_commit
+ else Transaction_abort))`;
+
+
+(*val num_of_trans_kind : trans_kind -> integer*)
+
+val _ = Define `
+ ((num_of_trans_kind:trans_kind -> int) arg_=
+ ((case arg_ of
+ Transaction_start => (( 0 : int):ii)
+ | Transaction_commit => (( 1 : int):ii)
+ | Transaction_abort => (( 2 : int):ii)
+ )))`;
+
+
+(*val cache_op_kind_of_num : integer -> cache_op_kind*)
+
+val _ = Define `
+ ((cache_op_kind_of_num:int -> cache_op_kind) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Cache_op_D_IVAC
+ else if (((p0_ = (( 1 : int):ii)))) then Cache_op_D_ISW
+ else if (((p0_ = (( 2 : int):ii)))) then Cache_op_D_CSW
+ else if (((p0_ = (( 3 : int):ii)))) then Cache_op_D_CISW
+ else if (((p0_ = (( 4 : int):ii)))) then Cache_op_D_ZVA
+ else if (((p0_ = (( 5 : int):ii)))) then Cache_op_D_CVAC
+ else if (((p0_ = (( 6 : int):ii)))) then Cache_op_D_CVAU
+ else if (((p0_ = (( 7 : int):ii)))) then Cache_op_D_CIVAC
+ else if (((p0_ = (( 8 : int):ii)))) then Cache_op_I_IALLUIS
+ else if (((p0_ = (( 9 : int):ii)))) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU))`;
+
+
+(*val num_of_cache_op_kind : cache_op_kind -> integer*)
+
+val _ = Define `
+ ((num_of_cache_op_kind:cache_op_kind -> int) arg_=
+ ((case arg_ of
+ Cache_op_D_IVAC => (( 0 : int):ii)
+ | Cache_op_D_ISW => (( 1 : int):ii)
+ | Cache_op_D_CSW => (( 2 : int):ii)
+ | Cache_op_D_CISW => (( 3 : int):ii)
+ | Cache_op_D_ZVA => (( 4 : int):ii)
+ | Cache_op_D_CVAC => (( 5 : int):ii)
+ | Cache_op_D_CVAU => (( 6 : int):ii)
+ | Cache_op_D_CIVAC => (( 7 : int):ii)
+ | Cache_op_I_IALLUIS => (( 8 : int):ii)
+ | Cache_op_I_IALLU => (( 9 : int):ii)
+ | Cache_op_I_IVAU => (( 10 : int):ii)
+ )))`;
+
+
+
+
+
+
+(*val cast_unit_vec : bitU -> mword ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(1)words$word) b=
+ ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`;
+
+
+(*val get_config_print_instr : unit -> bool*)
+
+(*val get_config_print_reg : unit -> bool*)
+
+(*val get_config_print_mem : unit -> bool*)
+
+(*val get_config_print_platform : unit -> bool*)
+
+val _ = Define `
+ ((get_config_print_instr:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_reg:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_mem:unit -> bool) () = F)`;
+
+
+val _ = Define `
+ ((get_config_print_platform:unit -> bool) () = F)`;
+
+
+(*val EXTS : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+(*val EXTZ : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*)
+
+val _ = Define `
+ ((EXTS:int -> 'n words$word -> 'm words$word) m v= ((sign_extend v m : 'm words$word)))`;
+
+
+val _ = Define `
+ ((EXTZ:int -> 'n words$word -> 'm words$word) m v= ((zero_extend v m : 'm words$word)))`;
+
+
+(*val zeros_implicit : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((zeros_implicit:int -> 'n words$word) n= ((zeros n : 'n words$word)))`;
+
+
+(*val ones : forall 'n. Size 'n => integer -> mword 'n*)
+
+val _ = Define `
+ ((ones:int -> 'n words$word) n= ((sail_ones n : 'n words$word)))`;
+
+
+(*val bool_to_bits : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`;
+
+
+(*val bit_to_bool : bitU -> bool*)
+
+val _ = Define `
+ ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | B0 => F )))`;
+
+
+(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*)
+
+val _ = Define `
+ ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int l n (( 0 : int):ii) : 'l words$word)))`;
+
+
+(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*)
+
+val _ = Define `
+ ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) >= ((integer_word$w2i y))))`;
+
+
+val _ = Define `
+ ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) < ((lem$w2ui y))))`;
+
+
+val _ = Define `
+ ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) >= ((lem$w2ui y))))`;
+
+
+val _ = Define `
+ ((zopz0zIzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) <= ((lem$w2ui y))))`;
+
+
+(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*)
+
+val _ = Define `
+ ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 bits) (shift : 6 bits)=
+ (let (v128 : 128 bits) = ((EXTS (( 128 : int):ii) v : 128 words$word)) in
+ (subrange_vec_dec ((shift_bits_right v128 shift : 128 words$word)) (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*)
+
+val _ = Define `
+ ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 bits) (shift : 5 bits)=
+ (let (v64 : 64 bits) = ((EXTS (( 64 : int):ii) v : 64 words$word)) in
+ (subrange_vec_dec ((shift_bits_right v64 shift : 64 words$word)) (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val n_leading_spaces : string -> ii*)
+
+ val n_leading_spaces0_defn = Hol_defn "n_leading_spaces0" `
+ ((n_leading_spaces0:string -> int) s=
+ (let p0_ = s in
+ if (((p0_ = ""))) then (( 0 : int):ii)
+ else
+ let p0_ = (string_take s (( 1 : int):ii)) in
+ if (((p0_ = " "))) then (( 1 : int):ii) + ((n_leading_spaces0 ((string_drop s (( 1 : int):ii)))))
+ else (( 0 : int):ii)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn n_leading_spaces0_defn;
+
+(*val spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((spc_forwards:unit -> string) () = " ")`;
+
+
+(*val spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((spc_backwards:string -> unit) s= () )`;
+
+
+(*val spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((spc_matches_prefix0:string ->(unit#int)option) s=
+ (let n = (n_leading_spaces0 s) in
+ let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then NONE
+ else SOME (() , n)))`;
+
+
+(*val opt_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((opt_spc_forwards:unit -> string) () = "")`;
+
+
+(*val opt_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((opt_spc_backwards:string -> unit) s= () )`;
+
+
+(*val opt_spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((opt_spc_matches_prefix0:string ->(unit#int)option) s= (SOME (() , n_leading_spaces0 s)))`;
+
+
+(*val def_spc_forwards : unit -> string*)
+
+val _ = Define `
+ ((def_spc_forwards:unit -> string) () = " ")`;
+
+
+(*val def_spc_backwards : string -> unit*)
+
+val _ = Define `
+ ((def_spc_backwards:string -> unit) s= () )`;
+
+
+(*val def_spc_matches_prefix : string -> maybe ((unit * ii))*)
+
+val _ = Define `
+ ((def_spc_matches_prefix:string ->(unit#ii)option) s= (opt_spc_matches_prefix0 s))`;
+
+
+(*val hex_bits_1_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((hex_bits_1_forwards_matches:(1)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_1_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_1_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 1 words$word # ii)) option)) of
+ SOME ((g__51, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_1_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((hex_bits_1_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 1 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_2_forwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((hex_bits_2_forwards_matches:(2)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_2_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_2_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 2 words$word # ii)) option)) of
+ SOME ((g__50, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_2_backwards : string -> M (mword ty2)*)
+
+val _ = Define `
+ ((hex_bits_2_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 2 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_3_forwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((hex_bits_3_forwards_matches:(3)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_3_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_3_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 3 words$word # ii)) option)) of
+ SOME ((g__49, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_3_backwards : string -> M (mword ty3)*)
+
+val _ = Define `
+ ((hex_bits_3_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((3)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 3 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_4_forwards_matches : mword ty4 -> bool*)
+
+val _ = Define `
+ ((hex_bits_4_forwards_matches:(4)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_4_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_4_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 4 words$word # ii)) option)) of
+ SOME ((g__48, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_4_backwards : string -> M (mword ty4)*)
+
+val _ = Define `
+ ((hex_bits_4_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 4 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_5_forwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((hex_bits_5_forwards_matches:(5)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_5_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_5_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 5 words$word # ii)) option)) of
+ SOME ((g__47, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_5_backwards : string -> M (mword ty5)*)
+
+val _ = Define `
+ ((hex_bits_5_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 5 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_6_forwards_matches : mword ty6 -> bool*)
+
+val _ = Define `
+ ((hex_bits_6_forwards_matches:(6)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_6_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_6_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 6 words$word # ii)) option)) of
+ SOME ((g__46, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_6_backwards : string -> M (mword ty6)*)
+
+val _ = Define `
+ ((hex_bits_6_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((6)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 6 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_7_forwards_matches : mword ty7 -> bool*)
+
+val _ = Define `
+ ((hex_bits_7_forwards_matches:(7)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_7_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_7_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 7 words$word # ii)) option)) of
+ SOME ((g__45, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_7_backwards : string -> M (mword ty7)*)
+
+val _ = Define `
+ ((hex_bits_7_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((7)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 7 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_8_forwards_matches : mword ty8 -> bool*)
+
+val _ = Define `
+ ((hex_bits_8_forwards_matches:(8)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_8_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_8_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 8 words$word # ii)) option)) of
+ SOME ((g__44, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_8_backwards : string -> M (mword ty8)*)
+
+val _ = Define `
+ ((hex_bits_8_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((8)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 8 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_9_forwards_matches : mword ty9 -> bool*)
+
+val _ = Define `
+ ((hex_bits_9_forwards_matches:(9)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_9_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_9_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 9 words$word # ii)) option)) of
+ SOME ((g__43, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_9_backwards : string -> M (mword ty9)*)
+
+val _ = Define `
+ ((hex_bits_9_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((9)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 9 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_10_forwards_matches : mword ty10 -> bool*)
+
+val _ = Define `
+ ((hex_bits_10_forwards_matches:(10)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_10_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_10_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 10 words$word # ii)) option)) of
+ SOME ((g__42, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_10_backwards : string -> M (mword ty10)*)
+
+val _ = Define `
+ ((hex_bits_10_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((10)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 10 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_11_forwards_matches : mword ty11 -> bool*)
+
+val _ = Define `
+ ((hex_bits_11_forwards_matches:(11)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_11_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_11_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 11 words$word # ii)) option)) of
+ SOME ((g__41, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_11_backwards : string -> M (mword ty11)*)
+
+val _ = Define `
+ ((hex_bits_11_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((11)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 11 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_12_forwards_matches : mword ty12 -> bool*)
+
+val _ = Define `
+ ((hex_bits_12_forwards_matches:(12)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_12_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_12_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 12 words$word # ii)) option)) of
+ SOME ((g__40, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_12_backwards : string -> M (mword ty12)*)
+
+val _ = Define `
+ ((hex_bits_12_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((12)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 12 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_13_forwards_matches : mword ty13 -> bool*)
+
+val _ = Define `
+ ((hex_bits_13_forwards_matches:(13)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_13_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_13_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 13 words$word # ii)) option)) of
+ SOME ((g__39, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_13_backwards : string -> M (mword ty13)*)
+
+val _ = Define `
+ ((hex_bits_13_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((13)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 13 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_14_forwards_matches : mword ty14 -> bool*)
+
+val _ = Define `
+ ((hex_bits_14_forwards_matches:(14)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_14_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_14_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 14 words$word # ii)) option)) of
+ SOME ((g__38, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_14_backwards : string -> M (mword ty14)*)
+
+val _ = Define `
+ ((hex_bits_14_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((14)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 14 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_15_forwards_matches : mword ty15 -> bool*)
+
+val _ = Define `
+ ((hex_bits_15_forwards_matches:(15)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_15_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_15_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 15 words$word # ii)) option)) of
+ SOME ((g__37, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_15_backwards : string -> M (mword ty15)*)
+
+val _ = Define `
+ ((hex_bits_15_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((15)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 15 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_16_forwards_matches : mword ty16 -> bool*)
+
+val _ = Define `
+ ((hex_bits_16_forwards_matches:(16)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_16_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_16_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 16 words$word # ii)) option)) of
+ SOME ((g__36, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_16_backwards : string -> M (mword ty16)*)
+
+val _ = Define `
+ ((hex_bits_16_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 16 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_17_forwards_matches : mword ty17 -> bool*)
+
+val _ = Define `
+ ((hex_bits_17_forwards_matches:(17)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_17_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_17_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 17 words$word # ii)) option)) of
+ SOME ((g__35, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_17_backwards : string -> M (mword ty17)*)
+
+val _ = Define `
+ ((hex_bits_17_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((17)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 17 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_18_forwards_matches : mword ty18 -> bool*)
+
+val _ = Define `
+ ((hex_bits_18_forwards_matches:(18)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_18_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_18_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 18 words$word # ii)) option)) of
+ SOME ((g__34, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_18_backwards : string -> M (mword ty18)*)
+
+val _ = Define `
+ ((hex_bits_18_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((18)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 18 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_19_forwards_matches : mword ty19 -> bool*)
+
+val _ = Define `
+ ((hex_bits_19_forwards_matches:(19)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_19_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_19_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 19 words$word # ii)) option)) of
+ SOME ((g__33, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_19_backwards : string -> M (mword ty19)*)
+
+val _ = Define `
+ ((hex_bits_19_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((19)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 19 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_20_forwards_matches : mword ty20 -> bool*)
+
+val _ = Define `
+ ((hex_bits_20_forwards_matches:(20)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_20_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_20_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 20 words$word # ii)) option)) of
+ SOME ((g__32, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_20_backwards : string -> M (mword ty20)*)
+
+val _ = Define `
+ ((hex_bits_20_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((20)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 20 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_21_forwards_matches : mword ty21 -> bool*)
+
+val _ = Define `
+ ((hex_bits_21_forwards_matches:(21)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_21_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_21_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 21 words$word # ii)) option)) of
+ SOME ((g__31, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_21_backwards : string -> M (mword ty21)*)
+
+val _ = Define `
+ ((hex_bits_21_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((21)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 21 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_22_forwards_matches : mword ty22 -> bool*)
+
+val _ = Define `
+ ((hex_bits_22_forwards_matches:(22)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_22_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_22_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 22 words$word # ii)) option)) of
+ SOME ((g__30, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_22_backwards : string -> M (mword ty22)*)
+
+val _ = Define `
+ ((hex_bits_22_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((22)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 22 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_23_forwards_matches : mword ty23 -> bool*)
+
+val _ = Define `
+ ((hex_bits_23_forwards_matches:(23)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_23_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_23_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 23 words$word # ii)) option)) of
+ SOME ((g__29, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_23_backwards : string -> M (mword ty23)*)
+
+val _ = Define `
+ ((hex_bits_23_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((23)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 23 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_24_forwards_matches : mword ty24 -> bool*)
+
+val _ = Define `
+ ((hex_bits_24_forwards_matches:(24)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_24_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_24_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 24 words$word # ii)) option)) of
+ SOME ((g__28, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_24_backwards : string -> M (mword ty24)*)
+
+val _ = Define `
+ ((hex_bits_24_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((24)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 24 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_25_forwards_matches : mword ty25 -> bool*)
+
+val _ = Define `
+ ((hex_bits_25_forwards_matches:(25)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_25_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_25_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 25 words$word # ii)) option)) of
+ SOME ((g__27, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_25_backwards : string -> M (mword ty25)*)
+
+val _ = Define `
+ ((hex_bits_25_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 25 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_26_forwards_matches : mword ty26 -> bool*)
+
+val _ = Define `
+ ((hex_bits_26_forwards_matches:(26)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_26_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_26_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 26 words$word # ii)) option)) of
+ SOME ((g__26, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_26_backwards : string -> M (mword ty26)*)
+
+val _ = Define `
+ ((hex_bits_26_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((26)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 26 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_27_forwards_matches : mword ty27 -> bool*)
+
+val _ = Define `
+ ((hex_bits_27_forwards_matches:(27)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_27_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_27_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 27 words$word # ii)) option)) of
+ SOME ((g__25, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_27_backwards : string -> M (mword ty27)*)
+
+val _ = Define `
+ ((hex_bits_27_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((27)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 27 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_28_forwards_matches : mword ty28 -> bool*)
+
+val _ = Define `
+ ((hex_bits_28_forwards_matches:(28)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_28_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_28_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 28 words$word # ii)) option)) of
+ SOME ((g__24, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_28_backwards : string -> M (mword ty28)*)
+
+val _ = Define `
+ ((hex_bits_28_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((28)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 28 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_29_forwards_matches : mword ty29 -> bool*)
+
+val _ = Define `
+ ((hex_bits_29_forwards_matches:(29)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_29_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_29_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 29 words$word # ii)) option)) of
+ SOME ((g__23, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_29_backwards : string -> M (mword ty29)*)
+
+val _ = Define `
+ ((hex_bits_29_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((29)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 29 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_30_forwards_matches : mword ty30 -> bool*)
+
+val _ = Define `
+ ((hex_bits_30_forwards_matches:(30)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_30_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_30_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 30 words$word # ii)) option)) of
+ SOME ((g__22, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_30_backwards : string -> M (mword ty30)*)
+
+val _ = Define `
+ ((hex_bits_30_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((30)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 30 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_31_forwards_matches : mword ty31 -> bool*)
+
+val _ = Define `
+ ((hex_bits_31_forwards_matches:(31)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_31_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_31_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 31 words$word # ii)) option)) of
+ SOME ((g__21, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_31_backwards : string -> M (mword ty31)*)
+
+val _ = Define `
+ ((hex_bits_31_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((31)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 31 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_32_forwards_matches : mword ty32 -> bool*)
+
+val _ = Define `
+ ((hex_bits_32_forwards_matches:(32)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_32_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_32_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 32 words$word # ii)) option)) of
+ SOME ((g__20, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_32_backwards : string -> M (mword ty32)*)
+
+val _ = Define `
+ ((hex_bits_32_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 32 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_33_forwards_matches : mword ty33 -> bool*)
+
+val _ = Define `
+ ((hex_bits_33_forwards_matches:(33)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_33_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_33_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 33 words$word # ii)) option)) of
+ SOME ((g__19, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_33_backwards : string -> M (mword ty33)*)
+
+val _ = Define `
+ ((hex_bits_33_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((33)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 33 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_48_forwards_matches : mword ty48 -> bool*)
+
+val _ = Define `
+ ((hex_bits_48_forwards_matches:(48)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_48_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_48_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 48 words$word # ii)) option)) of
+ SOME ((g__18, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_48_backwards : string -> M (mword ty48)*)
+
+val _ = Define `
+ ((hex_bits_48_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((48)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 48 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val hex_bits_64_forwards_matches : mword ty64 -> bool*)
+
+val _ = Define `
+ ((hex_bits_64_forwards_matches:(64)words$word -> bool) bv= T)`;
+
+
+(*val hex_bits_64_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((hex_bits_64_backwards_matches:string -> bool) s=
+ ((case s of
+ s =>
+ if ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s : (( 64 words$word # ii)) option)) of
+ SOME ((g__17, n)) =>
+ if (((n = ((string_length s))))) then T else F
+ | _ => F
+ )) then T else F
+ )))`;
+
+
+(*val hex_bits_64_backwards : string -> M (mword ty64)*)
+
+val _ = Define `
+ ((hex_bits_64_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s=
+ ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s : (( 64 words$word # ii))option)) of
+ SOME ((bv, n)) =>
+ if (((n = ((string_length s))))) then sail2_state_monad$returnS bv
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3")
+ (sail2_state_monad$exitS () )
+ | _ => sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3")
+ (sail2_state_monad$exitS () )
+ )))`;
+
+
+val _ = Define `
+((default_meta:unit)= () )`;
+
+
+(*val __WriteRAM_Meta : mword ty64 -> integer -> unit -> M unit*)
+
+val _ = Define `
+ ((WriteRAM_Meta:(64)words$word -> int -> unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width meta= (sail2_state_monad$returnS () ))`;
+
+
+(*val __ReadRAM_Meta : mword ty64 -> integer -> M unit*)
+
+val _ = Define `
+ ((ReadRAM_Meta:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= (sail2_state_monad$returnS () ))`;
+
+
+(*val write_ram : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M bool*)
+
+val _ = Define `
+ ((write_ram:write_kind ->(64)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) wk addr width data meta= (sail2_state_monad$bindS
+ (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 64 : int):ii) addr width data) (\ (ret : bool) . sail2_state_monad$seqS
+ (if ret then WriteRAM_Meta addr width meta else sail2_state_monad$returnS () ) (sail2_state_monad$returnS ret))))`;
+
+
+(*val write_ram_ea : write_kind -> mword ty64 -> integer -> M unit*)
+
+val _ = Define `
+ ((write_ram_ea:write_kind ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) wk addr width= (sail2_state_monad$returnS () ))`;
+
+
+(*val read_ram : forall 'int8_times_n. Size 'int8_times_n => read_kind -> mword ty64 -> integer -> M (mword 'int8_times_n)*)
+
+val _ = Define `
+ ((read_ram:read_kind ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('int8_times_n words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rk addr width= ((sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rk (( 64 : int):ii) addr width : ( 'int8_times_n words$word) M)))`;
+
+
+(*val __TraceMemoryWrite : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit*)
+
+(*val __TraceMemoryRead : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit*)
+
+val _ = Define `
+ ((xlen_val:int)= ((( 64 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_unsigned:int)= (((pow2 (( 64 : int):ii))) - (( 1 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_signed:int)= (((pow2 (((( 64 : int):ii) - (( 1 : int):ii))))) - (( 1 : int):ii)))`;
+
+
+val _ = Define `
+ ((xlen_min_signed:int)= ((( 0 : int):ii) - ((pow2 (((( 64 : int):ii) - (( 1 : int):ii)))))))`;
+
+
+(*val regidx_to_regno : mword ty5 -> integer*)
+
+val _ = Define `
+ ((regidx_to_regno:(5)words$word -> int) b=
+ (let r = (lem$w2ui b) in
+ r))`;
+
+
+(*val creg2reg_idx : mword ty3 -> mword ty5*)
+
+val _ = Define `
+ ((creg2reg_idx:(3)words$word ->(5)words$word) creg= ((concat_vec (vec_of_bits [B0;B1] : 2 words$word) creg : 5 words$word)))`;
+
+
+val _ = Define `
+((zreg:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`;
+
+
+val _ = Define `
+((ra:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))`;
+
+
+val _ = Define `
+((sp:(5)words$word)= ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))`;
+
+
+(*val Architecture_of_num : integer -> Architecture*)
+
+val _ = Define `
+ ((Architecture_of_num:int -> Architecture) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RV32
+ else if (((p0_ = (( 1 : int):ii)))) then RV64
+ else RV128))`;
+
+
+(*val num_of_Architecture : Architecture -> integer*)
+
+val _ = Define `
+ ((num_of_Architecture:Architecture -> int) arg_=
+ ((case arg_ of RV32 => (( 0 : int):ii) | RV64 => (( 1 : int):ii) | RV128 => (( 2 : int):ii) )))`;
+
+
+(*val architecture : mword ty2 -> maybe Architecture*)
+
+val _ = Define `
+ ((architecture:(2)words$word ->(Architecture)option) a=
+ (let b__0 = a in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then SOME RV32
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then SOME RV64
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then SOME RV128
+ else NONE))`;
+
+
+(*val arch_to_bits : Architecture -> mword ty2*)
+
+val _ = Define `
+ ((arch_to_bits:Architecture ->(2)words$word) a=
+ ((case a of
+ RV32 => (vec_of_bits [B0;B1] : 2 words$word)
+ | RV64 => (vec_of_bits [B1;B0] : 2 words$word)
+ | RV128 => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val Privilege_of_num : integer -> Privilege*)
+
+val _ = Define `
+ ((Privilege_of_num:int -> Privilege) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then User
+ else if (((p0_ = (( 1 : int):ii)))) then Supervisor
+ else Machine))`;
+
+
+(*val num_of_Privilege : Privilege -> integer*)
+
+val _ = Define `
+ ((num_of_Privilege:Privilege -> int) arg_=
+ ((case arg_ of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Machine => (( 2 : int):ii) )))`;
+
+
+(*val privLevel_to_bits : Privilege -> mword ty2*)
+
+val _ = Define `
+ ((privLevel_to_bits:Privilege ->(2)words$word) p=
+ ((case p of
+ User => (vec_of_bits [B0;B0] : 2 words$word)
+ | Supervisor => (vec_of_bits [B0;B1] : 2 words$word)
+ | Machine => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val privLevel_of_bits : mword ty2 -> M Privilege*)
+
+val _ = Define `
+ ((privLevel_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p=
+ (let b__0 = p in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS User
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS Supervisor
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS Machine
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_types.sail 78:2 - 82:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val privLevel_to_str : Privilege -> string*)
+
+val _ = Define `
+ ((privLevel_to_str:Privilege -> string) p= ((case p of User => "U" | Supervisor => "S" | Machine => "M" )))`;
+
+
+(*val print_insn : ast -> M string*)
+
+(*val Retired_of_num : integer -> Retired*)
+
+val _ = Define `
+ ((Retired_of_num:int -> Retired) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RETIRE_SUCCESS
+ else RETIRE_FAIL))`;
+
+
+(*val num_of_Retired : Retired -> integer*)
+
+val _ = Define `
+ ((num_of_Retired:Retired -> int) arg_= ((case arg_ of RETIRE_SUCCESS => (( 0 : int):ii) | RETIRE_FAIL => (( 1 : int):ii) )))`;
+
+
+(*val AccessType_of_num : integer -> AccessType*)
+
+val _ = Define `
+ ((AccessType_of_num:int -> AccessType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Read
+ else if (((p0_ = (( 1 : int):ii)))) then Write
+ else if (((p0_ = (( 2 : int):ii)))) then ReadWrite
+ else Execute))`;
+
+
+(*val num_of_AccessType : AccessType -> integer*)
+
+val _ = Define `
+ ((num_of_AccessType:AccessType -> int) arg_=
+ ((case arg_ of Read => (( 0 : int):ii) | Write => (( 1 : int):ii) | ReadWrite => (( 2 : int):ii) | Execute => (( 3 : int):ii) )))`;
+
+
+(*val accessType_to_str : AccessType -> string*)
+
+val _ = Define `
+ ((accessType_to_str:AccessType -> string) a=
+ ((case a of Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" )))`;
+
+
+(*val word_width_of_num : integer -> word_width*)
+
+val _ = Define `
+ ((word_width_of_num:int -> word_width) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then BYTE
+ else if (((p0_ = (( 1 : int):ii)))) then HALF
+ else if (((p0_ = (( 2 : int):ii)))) then WORD
+ else DOUBLE))`;
+
+
+(*val num_of_word_width : word_width -> integer*)
+
+val _ = Define `
+ ((num_of_word_width:word_width -> int) arg_=
+ ((case arg_ of BYTE => (( 0 : int):ii) | HALF => (( 1 : int):ii) | WORD => (( 2 : int):ii) | DOUBLE => (( 3 : int):ii) )))`;
+
+
+(*val InterruptType_of_num : integer -> InterruptType*)
+
+val _ = Define `
+ ((InterruptType_of_num:int -> InterruptType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then I_U_Software
+ else if (((p0_ = (( 1 : int):ii)))) then I_S_Software
+ else if (((p0_ = (( 2 : int):ii)))) then I_M_Software
+ else if (((p0_ = (( 3 : int):ii)))) then I_U_Timer
+ else if (((p0_ = (( 4 : int):ii)))) then I_S_Timer
+ else if (((p0_ = (( 5 : int):ii)))) then I_M_Timer
+ else if (((p0_ = (( 6 : int):ii)))) then I_U_External
+ else if (((p0_ = (( 7 : int):ii)))) then I_S_External
+ else I_M_External))`;
+
+
+(*val num_of_InterruptType : InterruptType -> integer*)
+
+val _ = Define `
+ ((num_of_InterruptType:InterruptType -> int) arg_=
+ ((case arg_ of
+ I_U_Software => (( 0 : int):ii)
+ | I_S_Software => (( 1 : int):ii)
+ | I_M_Software => (( 2 : int):ii)
+ | I_U_Timer => (( 3 : int):ii)
+ | I_S_Timer => (( 4 : int):ii)
+ | I_M_Timer => (( 5 : int):ii)
+ | I_U_External => (( 6 : int):ii)
+ | I_S_External => (( 7 : int):ii)
+ | I_M_External => (( 8 : int):ii)
+ )))`;
+
+
+(*val interruptType_to_bits : InterruptType -> mword ty8*)
+
+val _ = Define `
+ ((interruptType_to_bits:InterruptType ->(8)words$word) i=
+ ((case i of
+ I_U_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)
+ | I_S_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)
+ | I_M_Software => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word)
+ | I_U_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word)
+ | I_S_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word)
+ | I_M_Timer => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word)
+ | I_U_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word)
+ | I_S_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word)
+ | I_M_External => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word)
+ )))`;
+
+
+(*val ExceptionType_of_num : integer -> ExceptionType*)
+
+val _ = Define `
+ ((ExceptionType_of_num:int -> ExceptionType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then E_Fetch_Addr_Align
+ else if (((p0_ = (( 1 : int):ii)))) then E_Fetch_Access_Fault
+ else if (((p0_ = (( 2 : int):ii)))) then E_Illegal_Instr
+ else if (((p0_ = (( 3 : int):ii)))) then E_Breakpoint
+ else if (((p0_ = (( 4 : int):ii)))) then E_Load_Addr_Align
+ else if (((p0_ = (( 5 : int):ii)))) then E_Load_Access_Fault
+ else if (((p0_ = (( 6 : int):ii)))) then E_SAMO_Addr_Align
+ else if (((p0_ = (( 7 : int):ii)))) then E_SAMO_Access_Fault
+ else if (((p0_ = (( 8 : int):ii)))) then E_U_EnvCall
+ else if (((p0_ = (( 9 : int):ii)))) then E_S_EnvCall
+ else if (((p0_ = (( 10 : int):ii)))) then E_Reserved_10
+ else if (((p0_ = (( 11 : int):ii)))) then E_M_EnvCall
+ else if (((p0_ = (( 12 : int):ii)))) then E_Fetch_Page_Fault
+ else if (((p0_ = (( 13 : int):ii)))) then E_Load_Page_Fault
+ else if (((p0_ = (( 14 : int):ii)))) then E_Reserved_14
+ else if (((p0_ = (( 15 : int):ii)))) then E_SAMO_Page_Fault
+ else E_CHERI))`;
+
+
+(*val num_of_ExceptionType : ExceptionType -> integer*)
+
+val _ = Define `
+ ((num_of_ExceptionType:ExceptionType -> int) arg_=
+ ((case arg_ of
+ E_Fetch_Addr_Align => (( 0 : int):ii)
+ | E_Fetch_Access_Fault => (( 1 : int):ii)
+ | E_Illegal_Instr => (( 2 : int):ii)
+ | E_Breakpoint => (( 3 : int):ii)
+ | E_Load_Addr_Align => (( 4 : int):ii)
+ | E_Load_Access_Fault => (( 5 : int):ii)
+ | E_SAMO_Addr_Align => (( 6 : int):ii)
+ | E_SAMO_Access_Fault => (( 7 : int):ii)
+ | E_U_EnvCall => (( 8 : int):ii)
+ | E_S_EnvCall => (( 9 : int):ii)
+ | E_Reserved_10 => (( 10 : int):ii)
+ | E_M_EnvCall => (( 11 : int):ii)
+ | E_Fetch_Page_Fault => (( 12 : int):ii)
+ | E_Load_Page_Fault => (( 13 : int):ii)
+ | E_Reserved_14 => (( 14 : int):ii)
+ | E_SAMO_Page_Fault => (( 15 : int):ii)
+ | E_CHERI => (( 16 : int):ii)
+ )))`;
+
+
+(*val exceptionType_to_bits : ExceptionType -> mword ty8*)
+
+val _ = Define `
+ ((exceptionType_to_bits:ExceptionType ->(8)words$word) e=
+ ((case e of
+ E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)
+ | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)
+ | E_Illegal_Instr => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word)
+ | E_Breakpoint => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word)
+ | E_Load_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word)
+ | E_Load_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word)
+ | E_SAMO_Addr_Align => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : 8 words$word)
+ | E_SAMO_Access_Fault => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word)
+ | E_U_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word)
+ | E_S_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word)
+ | E_Reserved_10 => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word)
+ | E_M_EnvCall => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word)
+ | E_Fetch_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word)
+ | E_Load_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word)
+ | E_Reserved_14 => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B0] : 8 words$word)
+ | E_SAMO_Page_Fault => (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1] : 8 words$word)
+ | E_CHERI => (vec_of_bits [B0;B0;B1;B0;B0;B0;B0;B0] : 8 words$word)
+ )))`;
+
+
+(*val exceptionType_to_str : ExceptionType -> string*)
+
+val _ = Define `
+ ((exceptionType_to_str:ExceptionType -> string) e=
+ ((case e of
+ E_Fetch_Addr_Align => "misaligned-fetch"
+ | E_Fetch_Access_Fault => "fetch-access-fault"
+ | E_Illegal_Instr => "illegal-instruction"
+ | E_Breakpoint => "breakpoint"
+ | E_Load_Addr_Align => "misaligned-load"
+ | E_Load_Access_Fault => "load-access-fault"
+ | E_SAMO_Addr_Align => "misaliged-store/amo"
+ | E_SAMO_Access_Fault => "store/amo-access-fault"
+ | E_U_EnvCall => "u-call"
+ | E_S_EnvCall => "s-call"
+ | E_Reserved_10 => "reserved-0"
+ | E_M_EnvCall => "m-call"
+ | E_Fetch_Page_Fault => "fetch-page-fault"
+ | E_Load_Page_Fault => "load-page-fault"
+ | E_Reserved_14 => "reserved-1"
+ | E_SAMO_Page_Fault => "store/amo-page-fault"
+ | E_CHERI => "CHERI"
+ )))`;
+
+
+(*val not_implemented : forall 'a. string -> M 'a*)
+
+val _ = Define `
+ ((not_implemented:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) message= (sail2_state_monad$throwS (Error_not_implemented message)))`;
+
+
+(*val internal_error : forall 'a. string -> M 'a*)
+
+val _ = Define `
+ ((internal_error:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (sail2_state_monad$assert_expS F s) (sail2_state_monad$exitS () )))`;
+
+
+(*val TrapVectorMode_of_num : integer -> TrapVectorMode*)
+
+val _ = Define `
+ ((TrapVectorMode_of_num:int -> TrapVectorMode) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then TV_Direct
+ else if (((p0_ = (( 1 : int):ii)))) then TV_Vector
+ else TV_Reserved))`;
+
+
+(*val num_of_TrapVectorMode : TrapVectorMode -> integer*)
+
+val _ = Define `
+ ((num_of_TrapVectorMode:TrapVectorMode -> int) arg_=
+ ((case arg_ of TV_Direct => (( 0 : int):ii) | TV_Vector => (( 1 : int):ii) | TV_Reserved => (( 2 : int):ii) )))`;
+
+
+(*val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode*)
+
+val _ = Define `
+ ((trapVectorMode_of_bits:(2)words$word -> TrapVectorMode) m=
+ (let b__0 = m in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then TV_Direct
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then TV_Vector
+ else TV_Reserved))`;
+
+
+(*val ExtStatus_of_num : integer -> ExtStatus*)
+
+val _ = Define `
+ ((ExtStatus_of_num:int -> ExtStatus) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Off
+ else if (((p0_ = (( 1 : int):ii)))) then Initial
+ else if (((p0_ = (( 2 : int):ii)))) then Clean
+ else Dirty))`;
+
+
+(*val num_of_ExtStatus : ExtStatus -> integer*)
+
+val _ = Define `
+ ((num_of_ExtStatus:ExtStatus -> int) arg_=
+ ((case arg_ of Off => (( 0 : int):ii) | Initial => (( 1 : int):ii) | Clean => (( 2 : int):ii) | Dirty => (( 3 : int):ii) )))`;
+
+
+(*val extStatus_to_bits : ExtStatus -> mword ty2*)
+
+val _ = Define `
+ ((extStatus_to_bits:ExtStatus ->(2)words$word) e=
+ ((case e of
+ Off => (vec_of_bits [B0;B0] : 2 words$word)
+ | Initial => (vec_of_bits [B0;B1] : 2 words$word)
+ | Clean => (vec_of_bits [B1;B0] : 2 words$word)
+ | Dirty => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val extStatus_of_bits : mword ty2 -> M ExtStatus*)
+
+val _ = Define `
+ ((extStatus_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ExtStatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) e=
+ (let b__0 = e in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS Off
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS Initial
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS Clean
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS Dirty
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_types.sail 264:2 - 269:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val SATPMode_of_num : integer -> SATPMode*)
+
+val _ = Define `
+ ((SATPMode_of_num:int -> SATPMode) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then Sbare
+ else if (((p0_ = (( 1 : int):ii)))) then Sv32
+ else if (((p0_ = (( 2 : int):ii)))) then Sv39
+ else Sv48))`;
+
+
+(*val num_of_SATPMode : SATPMode -> integer*)
+
+val _ = Define `
+ ((num_of_SATPMode:SATPMode -> int) arg_=
+ ((case arg_ of Sbare => (( 0 : int):ii) | Sv32 => (( 1 : int):ii) | Sv39 => (( 2 : int):ii) | Sv48 => (( 3 : int):ii) )))`;
+
+
+(*val satp64Mode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*)
+
+val _ = Define `
+ ((satp64Mode_of_bits:Architecture ->(4)words$word ->(SATPMode)option) (a : Architecture) (m : satp_mode)=
+ ((case (a, m) of
+ (g__16, b__0) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then SOME Sbare
+ else
+ (case (g__16, b__0) of
+ (RV32, b__0) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then SOME Sv32
+ else (case (RV32, b__0) of (_, _) => NONE )
+ | (RV64, b__0) =>
+ if (((b__0 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then SOME Sv39
+ else if (((b__0 = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) then SOME Sv48
+ else (case (RV64, b__0) of (_, _) => NONE )
+ | (_, _) => NONE
+ )
+ )))`;
+
+
+(*val uop_of_num : integer -> uop*)
+
+val _ = Define `
+ ((uop_of_num:int -> uop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_LUI
+ else RISCV_AUIPC))`;
+
+
+(*val num_of_uop : uop -> integer*)
+
+val _ = Define `
+ ((num_of_uop:uop -> int) arg_= ((case arg_ of RISCV_LUI => (( 0 : int):ii) | RISCV_AUIPC => (( 1 : int):ii) )))`;
+
+
+(*val bop_of_num : integer -> bop*)
+
+val _ = Define `
+ ((bop_of_num:int -> bop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_BEQ
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_BNE
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_BLT
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_BGE
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_BLTU
+ else RISCV_BGEU))`;
+
+
+(*val num_of_bop : bop -> integer*)
+
+val _ = Define `
+ ((num_of_bop:bop -> int) arg_=
+ ((case arg_ of
+ RISCV_BEQ => (( 0 : int):ii)
+ | RISCV_BNE => (( 1 : int):ii)
+ | RISCV_BLT => (( 2 : int):ii)
+ | RISCV_BGE => (( 3 : int):ii)
+ | RISCV_BLTU => (( 4 : int):ii)
+ | RISCV_BGEU => (( 5 : int):ii)
+ )))`;
+
+
+(*val iop_of_num : integer -> iop*)
+
+val _ = Define `
+ ((iop_of_num:int -> iop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDI
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SLTI
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLTIU
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_XORI
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_ORI
+ else RISCV_ANDI))`;
+
+
+(*val num_of_iop : iop -> integer*)
+
+val _ = Define `
+ ((num_of_iop:iop -> int) arg_=
+ ((case arg_ of
+ RISCV_ADDI => (( 0 : int):ii)
+ | RISCV_SLTI => (( 1 : int):ii)
+ | RISCV_SLTIU => (( 2 : int):ii)
+ | RISCV_XORI => (( 3 : int):ii)
+ | RISCV_ORI => (( 4 : int):ii)
+ | RISCV_ANDI => (( 5 : int):ii)
+ )))`;
+
+
+(*val sop_of_num : integer -> sop*)
+
+val _ = Define `
+ ((sop_of_num:int -> sop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLI
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLI
+ else RISCV_SRAI))`;
+
+
+(*val num_of_sop : sop -> integer*)
+
+val _ = Define `
+ ((num_of_sop:sop -> int) arg_=
+ ((case arg_ of RISCV_SLLI => (( 0 : int):ii) | RISCV_SRLI => (( 1 : int):ii) | RISCV_SRAI => (( 2 : int):ii) )))`;
+
+
+(*val rop_of_num : integer -> rop*)
+
+val _ = Define `
+ ((rop_of_num:int -> rop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADD
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUB
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLL
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_SLT
+ else if (((p0_ = (( 4 : int):ii)))) then RISCV_SLTU
+ else if (((p0_ = (( 5 : int):ii)))) then RISCV_XOR
+ else if (((p0_ = (( 6 : int):ii)))) then RISCV_SRL
+ else if (((p0_ = (( 7 : int):ii)))) then RISCV_SRA
+ else if (((p0_ = (( 8 : int):ii)))) then RISCV_OR
+ else RISCV_AND))`;
+
+
+(*val num_of_rop : rop -> integer*)
+
+val _ = Define `
+ ((num_of_rop:rop -> int) arg_=
+ ((case arg_ of
+ RISCV_ADD => (( 0 : int):ii)
+ | RISCV_SUB => (( 1 : int):ii)
+ | RISCV_SLL => (( 2 : int):ii)
+ | RISCV_SLT => (( 3 : int):ii)
+ | RISCV_SLTU => (( 4 : int):ii)
+ | RISCV_XOR => (( 5 : int):ii)
+ | RISCV_SRL => (( 6 : int):ii)
+ | RISCV_SRA => (( 7 : int):ii)
+ | RISCV_OR => (( 8 : int):ii)
+ | RISCV_AND => (( 9 : int):ii)
+ )))`;
+
+
+(*val ropw_of_num : integer -> ropw*)
+
+val _ = Define `
+ ((ropw_of_num:int -> ropw) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDW
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUBW
+ else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLLW
+ else if (((p0_ = (( 3 : int):ii)))) then RISCV_SRLW
+ else RISCV_SRAW))`;
+
+
+(*val num_of_ropw : ropw -> integer*)
+
+val _ = Define `
+ ((num_of_ropw:ropw -> int) arg_=
+ ((case arg_ of
+ RISCV_ADDW => (( 0 : int):ii)
+ | RISCV_SUBW => (( 1 : int):ii)
+ | RISCV_SLLW => (( 2 : int):ii)
+ | RISCV_SRLW => (( 3 : int):ii)
+ | RISCV_SRAW => (( 4 : int):ii)
+ )))`;
+
+
+(*val sopw_of_num : integer -> sopw*)
+
+val _ = Define `
+ ((sopw_of_num:int -> sopw) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLIW
+ else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLIW
+ else RISCV_SRAIW))`;
+
+
+(*val num_of_sopw : sopw -> integer*)
+
+val _ = Define `
+ ((num_of_sopw:sopw -> int) arg_=
+ ((case arg_ of RISCV_SLLIW => (( 0 : int):ii) | RISCV_SRLIW => (( 1 : int):ii) | RISCV_SRAIW => (( 2 : int):ii) )))`;
+
+
+(*val amoop_of_num : integer -> amoop*)
+
+val _ = Define `
+ ((amoop_of_num:int -> amoop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then AMOSWAP
+ else if (((p0_ = (( 1 : int):ii)))) then AMOADD
+ else if (((p0_ = (( 2 : int):ii)))) then AMOXOR
+ else if (((p0_ = (( 3 : int):ii)))) then AMOAND
+ else if (((p0_ = (( 4 : int):ii)))) then AMOOR
+ else if (((p0_ = (( 5 : int):ii)))) then AMOMIN
+ else if (((p0_ = (( 6 : int):ii)))) then AMOMAX
+ else if (((p0_ = (( 7 : int):ii)))) then AMOMINU
+ else AMOMAXU))`;
+
+
+(*val num_of_amoop : amoop -> integer*)
+
+val _ = Define `
+ ((num_of_amoop:amoop -> int) arg_=
+ ((case arg_ of
+ AMOSWAP => (( 0 : int):ii)
+ | AMOADD => (( 1 : int):ii)
+ | AMOXOR => (( 2 : int):ii)
+ | AMOAND => (( 3 : int):ii)
+ | AMOOR => (( 4 : int):ii)
+ | AMOMIN => (( 5 : int):ii)
+ | AMOMAX => (( 6 : int):ii)
+ | AMOMINU => (( 7 : int):ii)
+ | AMOMAXU => (( 8 : int):ii)
+ )))`;
+
+
+(*val csrop_of_num : integer -> csrop*)
+
+val _ = Define `
+ ((csrop_of_num:int -> csrop) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then CSRRW
+ else if (((p0_ = (( 1 : int):ii)))) then CSRRS
+ else CSRRC))`;
+
+
+(*val num_of_csrop : csrop -> integer*)
+
+val _ = Define `
+ ((num_of_csrop:csrop -> int) arg_= ((case arg_ of CSRRW => (( 0 : int):ii) | CSRRS => (( 1 : int):ii) | CSRRC => (( 2 : int):ii) )))`;
+
+
+(*val sep_forwards : unit -> string*)
+
+val _ = Define `
+ ((sep_forwards:unit -> string) arg_=
+ ((case arg_ of
+ () =>
+ string_append ((opt_spc_forwards () ))
+ ((string_append "," ((string_append ((def_spc_forwards () )) ""))))
+ )))`;
+
+
+(*val sep_backwards : string -> M unit*)
+
+(*val _s0_ : string -> maybe unit*)
+
+val _ = Define `
+ ((s0_:string ->(unit)option) s1_0=
+ ((case s1_0 of
+ s2_0 =>
+ (case ((opt_spc_matches_prefix0 s2_0)) of
+ SOME ((() , s3_0)) =>
+ let s4_0 = (string_drop s2_0 s3_0) in
+ if ((string_startswith s4_0 ",")) then
+ (case ((string_drop s4_0 ((string_length ",")))) of
+ s5_0 =>
+ (case ((def_spc_matches_prefix s5_0)) of
+ SOME ((() , s6_0)) =>
+ let p0_ = (string_drop s5_0 s6_0) in
+ if (((p0_ = ""))) then SOME () else NONE
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s7_0 = arg_ in
+ if ((case ((s0_ s7_0)) of SOME (() ) => T | _ => F )) then
+ (case s0_ s7_0 of (SOME (() )) => sail2_state_monad$returnS () )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val sep_forwards_matches : unit -> bool*)
+
+val _ = Define `
+ ((sep_forwards_matches:unit -> bool) arg_=
+ ((case arg_ of () => T )))`;
+
+
+(*val sep_backwards_matches : string -> bool*)
+
+(*val _s8_ : string -> maybe unit*)
+
+val _ = Define `
+ ((s8_:string ->(unit)option) s9_0=
+ ((case s9_0 of
+ s10_0 =>
+ (case ((opt_spc_matches_prefix0 s10_0)) of
+ SOME ((() , s11_0)) =>
+ let s12_0 = (string_drop s10_0 s11_0) in
+ if ((string_startswith s12_0 ",")) then
+ (case ((string_drop s12_0 ((string_length ",")))) of
+ s13_0 =>
+ (case ((def_spc_matches_prefix s13_0)) of
+ SOME ((() , s14_0)) =>
+ let p0_ = (string_drop s13_0 s14_0) in
+ if (((p0_ = ""))) then SOME () else NONE
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_backwards_matches:string -> bool) arg_=
+ (let s15_0 = arg_ in
+ if ((case ((s8_ s15_0)) of SOME (() ) => T | _ => F )) then
+ (case s8_ s15_0 of (SOME (() )) => T )
+ else F))`;
+
+
+(*val sep_matches_prefix : string -> maybe ((unit * ii))*)
+
+(*val _s16_ : string -> maybe string*)
+
+val _ = Define `
+ ((s16_:string ->(string)option) s17_0=
+ ((case s17_0 of
+ s18_0 =>
+ (case ((opt_spc_matches_prefix0 s18_0)) of
+ SOME ((() , s19_0)) =>
+ let s20_0 = (string_drop s18_0 s19_0) in
+ if ((string_startswith s20_0 ",")) then
+ (case ((string_drop s20_0 ((string_length ",")))) of
+ s21_0 =>
+ (case ((def_spc_matches_prefix s21_0)) of
+ SOME ((() , s22_0)) =>
+ (case ((string_drop s21_0 s22_0)) of s_ => SOME s_ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((sep_matches_prefix:string ->(unit#int)option) arg_=
+ (let s23_0 = arg_ in
+ if ((case ((s16_ s23_0)) of SOME (s_) => T | _ => F )) then
+ (case s16_ s23_0 of
+ (SOME (s_)) =>
+ SOME (() , ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bool_bits_forwards : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_bits_forwards:bool ->(1)words$word) arg_=
+ ((case arg_ of
+ T => (vec_of_bits [B1] : 1 words$word)
+ | F => (vec_of_bits [B0] : 1 words$word)
+ )))`;
+
+
+(*val bool_bits_backwards : mword ty1 -> M bool*)
+
+val _ = Define `
+ ((bool_bits_backwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bool_bits_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((bool_bits_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val bool_bits_backwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bool_bits_backwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bool_not_bits_forwards : bool -> mword ty1*)
+
+val _ = Define `
+ ((bool_not_bits_forwards:bool ->(1)words$word) arg_=
+ ((case arg_ of
+ T => (vec_of_bits [B0] : 1 words$word)
+ | F => (vec_of_bits [B1] : 1 words$word)
+ )))`;
+
+
+(*val bool_not_bits_backwards : mword ty1 -> M bool*)
+
+val _ = Define `
+ ((bool_not_bits_backwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS T
+ else if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bool_not_bits_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((bool_not_bits_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val bool_not_bits_backwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bool_not_bits_backwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val size_bits_forwards : word_width -> mword ty2*)
+
+val _ = Define `
+ ((size_bits_forwards:word_width ->(2)words$word) arg_=
+ ((case arg_ of
+ BYTE => (vec_of_bits [B0;B0] : 2 words$word)
+ | HALF => (vec_of_bits [B0;B1] : 2 words$word)
+ | WORD => (vec_of_bits [B1;B0] : 2 words$word)
+ | DOUBLE => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val size_bits_backwards : mword ty2 -> M word_width*)
+
+val _ = Define `
+ ((size_bits_backwards:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((word_width),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS BYTE
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS HALF
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS WORD
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS DOUBLE
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val size_bits_forwards_matches : word_width -> bool*)
+
+val _ = Define `
+ ((size_bits_forwards_matches:word_width -> bool) arg_=
+ ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
+
+
+(*val size_bits_backwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((size_bits_backwards_matches:(2)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then T
+ else F))`;
+
+
+(*val size_mnemonic_forwards : word_width -> string*)
+
+val _ = Define `
+ ((size_mnemonic_forwards:word_width -> string) arg_=
+ ((case arg_ of BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" )))`;
+
+
+(*val size_mnemonic_backwards : string -> M word_width*)
+
+val _ = Define `
+ ((size_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((word_width),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "b"))) then sail2_state_monad$returnS BYTE
+ else if (((p0_ = "h"))) then sail2_state_monad$returnS HALF
+ else if (((p0_ = "w"))) then sail2_state_monad$returnS WORD
+ else if (((p0_ = "d"))) then sail2_state_monad$returnS DOUBLE
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val size_mnemonic_forwards_matches : word_width -> bool*)
+
+val _ = Define `
+ ((size_mnemonic_forwards_matches:word_width -> bool) arg_=
+ ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`;
+
+
+(*val size_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((size_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "b"))) then T
+ else if (((p0_ = "h"))) then T
+ else if (((p0_ = "w"))) then T
+ else if (((p0_ = "d"))) then T
+ else F))`;
+
+
+(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*)
+
+(*val _s36_ : string -> maybe string*)
+
+val _ = Define `
+ ((s36_:string ->(string)option) s37_0=
+ (let s38_0 = s37_0 in
+ if ((string_startswith s38_0 "d")) then
+ (case ((string_drop s38_0 ((string_length "d")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s32_ : string -> maybe string*)
+
+val _ = Define `
+ ((s32_:string ->(string)option) s33_0=
+ (let s34_0 = s33_0 in
+ if ((string_startswith s34_0 "w")) then
+ (case ((string_drop s34_0 ((string_length "w")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s28_ : string -> maybe string*)
+
+val _ = Define `
+ ((s28_:string ->(string)option) s29_0=
+ (let s30_0 = s29_0 in
+ if ((string_startswith s30_0 "h")) then
+ (case ((string_drop s30_0 ((string_length "h")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s24_ : string -> maybe string*)
+
+val _ = Define `
+ ((s24_:string ->(string)option) s25_0=
+ (let s26_0 = s25_0 in
+ if ((string_startswith s26_0 "b")) then
+ (case ((string_drop s26_0 ((string_length "b")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((size_mnemonic_matches_prefix:string ->(word_width#int)option) arg_=
+ (let s27_0 = arg_ in
+ if ((case ((s24_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s24_ s27_0 of
+ (SOME (s_)) =>
+ SOME (BYTE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s28_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s28_ s27_0 of
+ (SOME (s_)) =>
+ SOME (HALF, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s32_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s32_ s27_0 of
+ (SOME (s_)) =>
+ SOME (WORD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s36_ s27_0)) of SOME (s_) => T | _ => F )) then
+ (case s36_ s27_0 of
+ (SOME (s_)) =>
+ SOME (DOUBLE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val word_width_bytes : word_width -> integer*)
+
+val _ = Define `
+ ((word_width_bytes:word_width -> int) width=
+ ((case width of BYTE => (( 1 : int):ii) | HALF => (( 2 : int):ii) | WORD => (( 4 : int):ii) | DOUBLE => (( 8 : int):ii) )))`;
+
+
+val _ = Define `
+((zero_reg:(64)words$word)= ((EXTZ (( 64 : int):ii) (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 64 words$word)))`;
+
+
+(*val RegStr : mword ty64 -> string*)
+
+val _ = Define `
+ ((RegStr:(64)words$word -> string) r= (string_of_bits r))`;
+
+
+(*val regval_from_reg : mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((regval_from_reg:(64)words$word ->(64)words$word) r= r)`;
+
+
+(*val regval_into_reg : mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((regval_into_reg:(64)words$word ->(64)words$word) v= v)`;
+
+
+(*val rX : integer -> M (mword ty64)*)
+
+val _ = Define `
+ ((rX:int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+ (let p0_ = r in sail2_state_monad$bindS
+ (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS zero_reg
+ else if (((p0_ = (( 1 : int):ii)))) then (sail2_state_monad$read_regS x1_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 2 : int):ii)))) then (sail2_state_monad$read_regS x2_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 3 : int):ii)))) then (sail2_state_monad$read_regS x3_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 4 : int):ii)))) then (sail2_state_monad$read_regS x4_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 5 : int):ii)))) then (sail2_state_monad$read_regS x5_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 6 : int):ii)))) then (sail2_state_monad$read_regS x6_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 7 : int):ii)))) then (sail2_state_monad$read_regS x7_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 8 : int):ii)))) then (sail2_state_monad$read_regS x8_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 9 : int):ii)))) then (sail2_state_monad$read_regS x9_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 10 : int):ii)))) then (sail2_state_monad$read_regS x10_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 11 : int):ii)))) then (sail2_state_monad$read_regS x11_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 12 : int):ii)))) then (sail2_state_monad$read_regS x12_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 13 : int):ii)))) then (sail2_state_monad$read_regS x13_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 14 : int):ii)))) then (sail2_state_monad$read_regS x14_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 15 : int):ii)))) then (sail2_state_monad$read_regS x15_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 16 : int):ii)))) then (sail2_state_monad$read_regS x16_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 17 : int):ii)))) then (sail2_state_monad$read_regS x17_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 18 : int):ii)))) then (sail2_state_monad$read_regS x18_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 19 : int):ii)))) then (sail2_state_monad$read_regS x19_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 20 : int):ii)))) then (sail2_state_monad$read_regS x20_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 21 : int):ii)))) then (sail2_state_monad$read_regS x21_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 22 : int):ii)))) then (sail2_state_monad$read_regS x22_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 23 : int):ii)))) then (sail2_state_monad$read_regS x23_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 24 : int):ii)))) then (sail2_state_monad$read_regS x24_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 25 : int):ii)))) then (sail2_state_monad$read_regS x25_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 26 : int):ii)))) then (sail2_state_monad$read_regS x26_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 27 : int):ii)))) then (sail2_state_monad$read_regS x27_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 28 : int):ii)))) then (sail2_state_monad$read_regS x28_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 29 : int):ii)))) then (sail2_state_monad$read_regS x29_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 30 : int):ii)))) then (sail2_state_monad$read_regS x30_ref : ( 64 words$word) M)
+ else if (((p0_ = (( 31 : int):ii)))) then (sail2_state_monad$read_regS x31_ref : ( 64 words$word) M)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "invalid register number") (sail2_state_monad$exitS () )) (\ (v : regtype) .
+ sail2_state_monad$returnS ((regval_from_reg v : 64 words$word)))))`;
+
+
+(*val rvfi_wX : integer -> mword ty64 -> unit*)
+
+val _ = Define `
+ ((rvfi_wX:int ->(64)words$word -> unit) r v= () )`;
+
+
+(*val wX : integer -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((wX:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r in_v=
+ (let v = ((regval_into_reg in_v : 64 words$word)) in
+ let p0_ = r in sail2_state_monad$seqS
+ (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS ()
+ else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$write_regS x1_ref v
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$write_regS x2_ref v
+ else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$write_regS x3_ref v
+ else if (((p0_ = (( 4 : int):ii)))) then sail2_state_monad$write_regS x4_ref v
+ else if (((p0_ = (( 5 : int):ii)))) then sail2_state_monad$write_regS x5_ref v
+ else if (((p0_ = (( 6 : int):ii)))) then sail2_state_monad$write_regS x6_ref v
+ else if (((p0_ = (( 7 : int):ii)))) then sail2_state_monad$write_regS x7_ref v
+ else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$write_regS x8_ref v
+ else if (((p0_ = (( 9 : int):ii)))) then sail2_state_monad$write_regS x9_ref v
+ else if (((p0_ = (( 10 : int):ii)))) then sail2_state_monad$write_regS x10_ref v
+ else if (((p0_ = (( 11 : int):ii)))) then sail2_state_monad$write_regS x11_ref v
+ else if (((p0_ = (( 12 : int):ii)))) then sail2_state_monad$write_regS x12_ref v
+ else if (((p0_ = (( 13 : int):ii)))) then sail2_state_monad$write_regS x13_ref v
+ else if (((p0_ = (( 14 : int):ii)))) then sail2_state_monad$write_regS x14_ref v
+ else if (((p0_ = (( 15 : int):ii)))) then sail2_state_monad$write_regS x15_ref v
+ else if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$write_regS x16_ref v
+ else if (((p0_ = (( 17 : int):ii)))) then sail2_state_monad$write_regS x17_ref v
+ else if (((p0_ = (( 18 : int):ii)))) then sail2_state_monad$write_regS x18_ref v
+ else if (((p0_ = (( 19 : int):ii)))) then sail2_state_monad$write_regS x19_ref v
+ else if (((p0_ = (( 20 : int):ii)))) then sail2_state_monad$write_regS x20_ref v
+ else if (((p0_ = (( 21 : int):ii)))) then sail2_state_monad$write_regS x21_ref v
+ else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$write_regS x22_ref v
+ else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$write_regS x23_ref v
+ else if (((p0_ = (( 24 : int):ii)))) then sail2_state_monad$write_regS x24_ref v
+ else if (((p0_ = (( 25 : int):ii)))) then sail2_state_monad$write_regS x25_ref v
+ else if (((p0_ = (( 26 : int):ii)))) then sail2_state_monad$write_regS x26_ref v
+ else if (((p0_ = (( 27 : int):ii)))) then sail2_state_monad$write_regS x27_ref v
+ else if (((p0_ = (( 28 : int):ii)))) then sail2_state_monad$write_regS x28_ref v
+ else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$write_regS x29_ref v
+ else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$write_regS x30_ref v
+ else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$write_regS x31_ref v
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "invalid register number") (sail2_state_monad$exitS () ))
+ (sail2_state_monad$returnS (if (((r <> (( 0 : int):ii)))) then
+ let (_ : unit) = (rvfi_wX r in_v) in
+ if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "x"
+ ((STRCAT ((stringFromInteger r)) ((STRCAT " <- " ((RegStr v))))))))
+ else ()
+ else () ))))`;
+
+
+(*val reg_name_abi : mword ty5 -> M string*)
+
+val _ = Define `
+ ((reg_name_abi:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r=
+ (let b__0 = r in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS "zero"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "ra"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "sp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "gp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "tp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "fp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s8"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s9"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s10"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s11"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t6"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_regs.sail 149:2 - 182:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_forwards : mword ty5 -> M string*)
+
+val _ = Define `
+ ((reg_name_forwards:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS "zero"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "ra"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "sp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "gp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "tp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "fp"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a0"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a1"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "a7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s2"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s6"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s7"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s8"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s9"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s10"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "s11"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t3"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t4"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t5"
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ sail2_state_monad$returnS "t6"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_backwards : string -> M (mword ty5)*)
+
+val _ = Define `
+ ((reg_name_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "zero"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "ra"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "sp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "gp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "tp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "t0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "t1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "t2"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "fp"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "s1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "a0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "a1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "a2"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "a3"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "a4"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "a5"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "a6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "a7"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "s2"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "s3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "s4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "s5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "s6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "s7"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)
+ else if (((p0_ = "s8"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)
+ else if (((p0_ = "s9"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)
+ else if (((p0_ = "s10"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)
+ else if (((p0_ = "s11"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)
+ else if (((p0_ = "t3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)
+ else if (((p0_ = "t4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)
+ else if (((p0_ = "t5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)
+ else if (((p0_ = "t6"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val reg_name_forwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((reg_name_forwards_matches:(5)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))
+ then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then
+ T
+ else F))`;
+
+
+(*val reg_name_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((reg_name_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "zero"))) then T
+ else if (((p0_ = "ra"))) then T
+ else if (((p0_ = "sp"))) then T
+ else if (((p0_ = "gp"))) then T
+ else if (((p0_ = "tp"))) then T
+ else if (((p0_ = "t0"))) then T
+ else if (((p0_ = "t1"))) then T
+ else if (((p0_ = "t2"))) then T
+ else if (((p0_ = "fp"))) then T
+ else if (((p0_ = "s1"))) then T
+ else if (((p0_ = "a0"))) then T
+ else if (((p0_ = "a1"))) then T
+ else if (((p0_ = "a2"))) then T
+ else if (((p0_ = "a3"))) then T
+ else if (((p0_ = "a4"))) then T
+ else if (((p0_ = "a5"))) then T
+ else if (((p0_ = "a6"))) then T
+ else if (((p0_ = "a7"))) then T
+ else if (((p0_ = "s2"))) then T
+ else if (((p0_ = "s3"))) then T
+ else if (((p0_ = "s4"))) then T
+ else if (((p0_ = "s5"))) then T
+ else if (((p0_ = "s6"))) then T
+ else if (((p0_ = "s7"))) then T
+ else if (((p0_ = "s8"))) then T
+ else if (((p0_ = "s9"))) then T
+ else if (((p0_ = "s10"))) then T
+ else if (((p0_ = "s11"))) then T
+ else if (((p0_ = "t3"))) then T
+ else if (((p0_ = "t4"))) then T
+ else if (((p0_ = "t5"))) then T
+ else if (((p0_ = "t6"))) then T
+ else F))`;
+
+
+(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*)
+
+(*val _s164_ : string -> maybe string*)
+
+val _ = Define `
+ ((s164_:string ->(string)option) s165_0=
+ (let s166_0 = s165_0 in
+ if ((string_startswith s166_0 "t6")) then
+ (case ((string_drop s166_0 ((string_length "t6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s160_ : string -> maybe string*)
+
+val _ = Define `
+ ((s160_:string ->(string)option) s161_0=
+ (let s162_0 = s161_0 in
+ if ((string_startswith s162_0 "t5")) then
+ (case ((string_drop s162_0 ((string_length "t5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s156_ : string -> maybe string*)
+
+val _ = Define `
+ ((s156_:string ->(string)option) s157_0=
+ (let s158_0 = s157_0 in
+ if ((string_startswith s158_0 "t4")) then
+ (case ((string_drop s158_0 ((string_length "t4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s152_ : string -> maybe string*)
+
+val _ = Define `
+ ((s152_:string ->(string)option) s153_0=
+ (let s154_0 = s153_0 in
+ if ((string_startswith s154_0 "t3")) then
+ (case ((string_drop s154_0 ((string_length "t3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s148_ : string -> maybe string*)
+
+val _ = Define `
+ ((s148_:string ->(string)option) s149_0=
+ (let s150_0 = s149_0 in
+ if ((string_startswith s150_0 "s11")) then
+ (case ((string_drop s150_0 ((string_length "s11")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s144_ : string -> maybe string*)
+
+val _ = Define `
+ ((s144_:string ->(string)option) s145_0=
+ (let s146_0 = s145_0 in
+ if ((string_startswith s146_0 "s10")) then
+ (case ((string_drop s146_0 ((string_length "s10")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s140_ : string -> maybe string*)
+
+val _ = Define `
+ ((s140_:string ->(string)option) s141_0=
+ (let s142_0 = s141_0 in
+ if ((string_startswith s142_0 "s9")) then
+ (case ((string_drop s142_0 ((string_length "s9")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s136_ : string -> maybe string*)
+
+val _ = Define `
+ ((s136_:string ->(string)option) s137_0=
+ (let s138_0 = s137_0 in
+ if ((string_startswith s138_0 "s8")) then
+ (case ((string_drop s138_0 ((string_length "s8")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s132_ : string -> maybe string*)
+
+val _ = Define `
+ ((s132_:string ->(string)option) s133_0=
+ (let s134_0 = s133_0 in
+ if ((string_startswith s134_0 "s7")) then
+ (case ((string_drop s134_0 ((string_length "s7")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s128_ : string -> maybe string*)
+
+val _ = Define `
+ ((s128_:string ->(string)option) s129_0=
+ (let s130_0 = s129_0 in
+ if ((string_startswith s130_0 "s6")) then
+ (case ((string_drop s130_0 ((string_length "s6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s124_ : string -> maybe string*)
+
+val _ = Define `
+ ((s124_:string ->(string)option) s125_0=
+ (let s126_0 = s125_0 in
+ if ((string_startswith s126_0 "s5")) then
+ (case ((string_drop s126_0 ((string_length "s5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s120_ : string -> maybe string*)
+
+val _ = Define `
+ ((s120_:string ->(string)option) s121_0=
+ (let s122_0 = s121_0 in
+ if ((string_startswith s122_0 "s4")) then
+ (case ((string_drop s122_0 ((string_length "s4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s116_ : string -> maybe string*)
+
+val _ = Define `
+ ((s116_:string ->(string)option) s117_0=
+ (let s118_0 = s117_0 in
+ if ((string_startswith s118_0 "s3")) then
+ (case ((string_drop s118_0 ((string_length "s3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s112_ : string -> maybe string*)
+
+val _ = Define `
+ ((s112_:string ->(string)option) s113_0=
+ (let s114_0 = s113_0 in
+ if ((string_startswith s114_0 "s2")) then
+ (case ((string_drop s114_0 ((string_length "s2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s108_ : string -> maybe string*)
+
+val _ = Define `
+ ((s108_:string ->(string)option) s109_0=
+ (let s110_0 = s109_0 in
+ if ((string_startswith s110_0 "a7")) then
+ (case ((string_drop s110_0 ((string_length "a7")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s104_ : string -> maybe string*)
+
+val _ = Define `
+ ((s104_:string ->(string)option) s105_0=
+ (let s106_0 = s105_0 in
+ if ((string_startswith s106_0 "a6")) then
+ (case ((string_drop s106_0 ((string_length "a6")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s100_ : string -> maybe string*)
+
+val _ = Define `
+ ((s100_:string ->(string)option) s101_0=
+ (let s102_0 = s101_0 in
+ if ((string_startswith s102_0 "a5")) then
+ (case ((string_drop s102_0 ((string_length "a5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s96_ : string -> maybe string*)
+
+val _ = Define `
+ ((s96_:string ->(string)option) s97_0=
+ (let s98_0 = s97_0 in
+ if ((string_startswith s98_0 "a4")) then
+ (case ((string_drop s98_0 ((string_length "a4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s92_ : string -> maybe string*)
+
+val _ = Define `
+ ((s92_:string ->(string)option) s93_0=
+ (let s94_0 = s93_0 in
+ if ((string_startswith s94_0 "a3")) then
+ (case ((string_drop s94_0 ((string_length "a3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s88_ : string -> maybe string*)
+
+val _ = Define `
+ ((s88_:string ->(string)option) s89_0=
+ (let s90_0 = s89_0 in
+ if ((string_startswith s90_0 "a2")) then
+ (case ((string_drop s90_0 ((string_length "a2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s84_ : string -> maybe string*)
+
+val _ = Define `
+ ((s84_:string ->(string)option) s85_0=
+ (let s86_0 = s85_0 in
+ if ((string_startswith s86_0 "a1")) then
+ (case ((string_drop s86_0 ((string_length "a1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s80_ : string -> maybe string*)
+
+val _ = Define `
+ ((s80_:string ->(string)option) s81_0=
+ (let s82_0 = s81_0 in
+ if ((string_startswith s82_0 "a0")) then
+ (case ((string_drop s82_0 ((string_length "a0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s76_ : string -> maybe string*)
+
+val _ = Define `
+ ((s76_:string ->(string)option) s77_0=
+ (let s78_0 = s77_0 in
+ if ((string_startswith s78_0 "s1")) then
+ (case ((string_drop s78_0 ((string_length "s1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s72_ : string -> maybe string*)
+
+val _ = Define `
+ ((s72_:string ->(string)option) s73_0=
+ (let s74_0 = s73_0 in
+ if ((string_startswith s74_0 "fp")) then
+ (case ((string_drop s74_0 ((string_length "fp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s68_ : string -> maybe string*)
+
+val _ = Define `
+ ((s68_:string ->(string)option) s69_0=
+ (let s70_0 = s69_0 in
+ if ((string_startswith s70_0 "t2")) then
+ (case ((string_drop s70_0 ((string_length "t2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s64_ : string -> maybe string*)
+
+val _ = Define `
+ ((s64_:string ->(string)option) s65_0=
+ (let s66_0 = s65_0 in
+ if ((string_startswith s66_0 "t1")) then
+ (case ((string_drop s66_0 ((string_length "t1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s60_ : string -> maybe string*)
+
+val _ = Define `
+ ((s60_:string ->(string)option) s61_0=
+ (let s62_0 = s61_0 in
+ if ((string_startswith s62_0 "t0")) then
+ (case ((string_drop s62_0 ((string_length "t0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s56_ : string -> maybe string*)
+
+val _ = Define `
+ ((s56_:string ->(string)option) s57_0=
+ (let s58_0 = s57_0 in
+ if ((string_startswith s58_0 "tp")) then
+ (case ((string_drop s58_0 ((string_length "tp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s52_ : string -> maybe string*)
+
+val _ = Define `
+ ((s52_:string ->(string)option) s53_0=
+ (let s54_0 = s53_0 in
+ if ((string_startswith s54_0 "gp")) then
+ (case ((string_drop s54_0 ((string_length "gp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s48_ : string -> maybe string*)
+
+val _ = Define `
+ ((s48_:string ->(string)option) s49_0=
+ (let s50_0 = s49_0 in
+ if ((string_startswith s50_0 "sp")) then
+ (case ((string_drop s50_0 ((string_length "sp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s44_ : string -> maybe string*)
+
+val _ = Define `
+ ((s44_:string ->(string)option) s45_0=
+ (let s46_0 = s45_0 in
+ if ((string_startswith s46_0 "ra")) then
+ (case ((string_drop s46_0 ((string_length "ra")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s40_ : string -> maybe string*)
+
+val _ = Define `
+ ((s40_:string ->(string)option) s41_0=
+ (let s42_0 = s41_0 in
+ if ((string_startswith s42_0 "zero")) then
+ (case ((string_drop s42_0 ((string_length "zero")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((reg_name_matches_prefix:string ->((5)words$word#int)option) arg_=
+ (let s43_0 = arg_ in
+ if ((case ((s40_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s40_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s44_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s44_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s48_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s48_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s52_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s52_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s56_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s56_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s60_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s60_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s64_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s64_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s68_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s68_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s72_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s72_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s76_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s76_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s80_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s80_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s84_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s84_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s88_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s88_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s92_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s92_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s96_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s96_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s100_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s100_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s104_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s104_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s108_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s108_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s112_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s112_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s116_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s116_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s120_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s120_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s124_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s124_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s128_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s128_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s132_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s132_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s136_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s136_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s140_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s140_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s144_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s144_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s148_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s148_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s152_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s152_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s156_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s156_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s160_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s160_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s164_ s43_0)) of SOME (s_) => T | _ => F )) then
+ (case s164_ s43_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val creg_name_forwards : mword ty3 -> M string*)
+
+val _ = Define `
+ ((creg_name_forwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS "s0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS "s1"
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS "a0"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS "a1"
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS "a2"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS "a3"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS "a4"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS "a5"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val creg_name_backwards : string -> M (mword ty3)*)
+
+val _ = Define `
+ ((creg_name_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((3)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "s0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B0] : 3 words$word)
+ else if (((p0_ = "s1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B0;B1] : 3 words$word)
+ else if (((p0_ = "a0"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B0] : 3 words$word)
+ else if (((p0_ = "a1"))) then sail2_state_monad$returnS (vec_of_bits [B0;B1;B1] : 3 words$word)
+ else if (((p0_ = "a2"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B0] : 3 words$word)
+ else if (((p0_ = "a3"))) then sail2_state_monad$returnS (vec_of_bits [B1;B0;B1] : 3 words$word)
+ else if (((p0_ = "a4"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B0] : 3 words$word)
+ else if (((p0_ = "a5"))) then sail2_state_monad$returnS (vec_of_bits [B1;B1;B1] : 3 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val creg_name_forwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((creg_name_forwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val creg_name_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((creg_name_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "s0"))) then T
+ else if (((p0_ = "s1"))) then T
+ else if (((p0_ = "a0"))) then T
+ else if (((p0_ = "a1"))) then T
+ else if (((p0_ = "a2"))) then T
+ else if (((p0_ = "a3"))) then T
+ else if (((p0_ = "a4"))) then T
+ else if (((p0_ = "a5"))) then T
+ else F))`;
+
+
+(*val creg_name_matches_prefix : string -> maybe ((mword ty3 * ii))*)
+
+(*val _s196_ : string -> maybe string*)
+
+val _ = Define `
+ ((s196_:string ->(string)option) s197_0=
+ (let s198_0 = s197_0 in
+ if ((string_startswith s198_0 "a5")) then
+ (case ((string_drop s198_0 ((string_length "a5")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s192_ : string -> maybe string*)
+
+val _ = Define `
+ ((s192_:string ->(string)option) s193_0=
+ (let s194_0 = s193_0 in
+ if ((string_startswith s194_0 "a4")) then
+ (case ((string_drop s194_0 ((string_length "a4")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s188_ : string -> maybe string*)
+
+val _ = Define `
+ ((s188_:string ->(string)option) s189_0=
+ (let s190_0 = s189_0 in
+ if ((string_startswith s190_0 "a3")) then
+ (case ((string_drop s190_0 ((string_length "a3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s184_ : string -> maybe string*)
+
+val _ = Define `
+ ((s184_:string ->(string)option) s185_0=
+ (let s186_0 = s185_0 in
+ if ((string_startswith s186_0 "a2")) then
+ (case ((string_drop s186_0 ((string_length "a2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s180_ : string -> maybe string*)
+
+val _ = Define `
+ ((s180_:string ->(string)option) s181_0=
+ (let s182_0 = s181_0 in
+ if ((string_startswith s182_0 "a1")) then
+ (case ((string_drop s182_0 ((string_length "a1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s176_ : string -> maybe string*)
+
+val _ = Define `
+ ((s176_:string ->(string)option) s177_0=
+ (let s178_0 = s177_0 in
+ if ((string_startswith s178_0 "a0")) then
+ (case ((string_drop s178_0 ((string_length "a0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s172_ : string -> maybe string*)
+
+val _ = Define `
+ ((s172_:string ->(string)option) s173_0=
+ (let s174_0 = s173_0 in
+ if ((string_startswith s174_0 "s1")) then
+ (case ((string_drop s174_0 ((string_length "s1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s168_ : string -> maybe string*)
+
+val _ = Define `
+ ((s168_:string ->(string)option) s169_0=
+ (let s170_0 = s169_0 in
+ if ((string_startswith s170_0 "s0")) then
+ (case ((string_drop s170_0 ((string_length "s0")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((creg_name_matches_prefix:string ->((3)words$word#int)option) arg_=
+ (let s171_0 = arg_ in
+ if ((case ((s168_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s168_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s172_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s172_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s176_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s176_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s180_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s180_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s184_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s184_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s188_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s188_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s192_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s192_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s196_ s171_0)) of SOME (s_) => T | _ => F )) then
+ (case s196_ s171_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1] : 3 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val init_base_regs : unit -> M unit*)
+
+val _ = Define `
+ ((init_base_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS x1_ref zero_reg)
+ (sail2_state_monad$write_regS x2_ref zero_reg))
+ (sail2_state_monad$write_regS x3_ref zero_reg))
+ (sail2_state_monad$write_regS x4_ref zero_reg))
+ (sail2_state_monad$write_regS x5_ref zero_reg))
+ (sail2_state_monad$write_regS x6_ref zero_reg))
+ (sail2_state_monad$write_regS x7_ref zero_reg))
+ (sail2_state_monad$write_regS x8_ref zero_reg))
+ (sail2_state_monad$write_regS x9_ref zero_reg))
+ (sail2_state_monad$write_regS x10_ref zero_reg))
+ (sail2_state_monad$write_regS x11_ref zero_reg))
+ (sail2_state_monad$write_regS x12_ref zero_reg))
+ (sail2_state_monad$write_regS x13_ref zero_reg))
+ (sail2_state_monad$write_regS x14_ref zero_reg))
+ (sail2_state_monad$write_regS x15_ref zero_reg))
+ (sail2_state_monad$write_regS x16_ref zero_reg))
+ (sail2_state_monad$write_regS x17_ref zero_reg))
+ (sail2_state_monad$write_regS x18_ref zero_reg))
+ (sail2_state_monad$write_regS x19_ref zero_reg))
+ (sail2_state_monad$write_regS x20_ref zero_reg))
+ (sail2_state_monad$write_regS x21_ref zero_reg))
+ (sail2_state_monad$write_regS x22_ref zero_reg))
+ (sail2_state_monad$write_regS x23_ref zero_reg))
+ (sail2_state_monad$write_regS x24_ref zero_reg))
+ (sail2_state_monad$write_regS x25_ref zero_reg))
+ (sail2_state_monad$write_regS x26_ref zero_reg))
+ (sail2_state_monad$write_regS x27_ref zero_reg))
+ (sail2_state_monad$write_regS x28_ref zero_reg))
+ (sail2_state_monad$write_regS x29_ref zero_reg)) (sail2_state_monad$write_regS x30_ref zero_reg)) (sail2_state_monad$write_regS x31_ref zero_reg)))`;
+
+
+(*
+ Retrieves the architectural PC value. This is not necessarily the value
+ found in the PC register as extensions may choose to override this function.
+ The value in the PC register is the absolute virtual address of the instruction
+ to fetch.
+ *)
+(*val get_arch_pc : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_arch_pc:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)))`;
+
+
+(*val get_next_pc : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M)))`;
+
+
+(*val set_next_pc : mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_next_pc:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc= (sail2_state_monad$write_regS nextPC_ref pc))`;
+
+
+(*val tick_pc : unit -> M unit*)
+
+val _ = Define `
+ ((tick_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$write_regS PC_ref w__0)))`;
+
+
+(*val Mk_Misa : mword ty64 -> Misa*)
+
+val _ = Define `
+ ((Mk_Misa:(64)words$word -> Misa) v= (<| Misa_Misa_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Misa_bits : Misa -> mword ty64*)
+
+val _ = Define `
+ ((get_Misa_bits:Misa ->(64)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_bits:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_bits : Misa -> mword ty64 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_bits:Misa ->(64)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_bits : SV48_PTE -> mword ty64 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_bits : SV48_PTE -> mword ty64*)
+
+(*val _set_SV48_PTE_bits : register_ref regstate register_value SV48_PTE -> mword ty64 -> M unit*)
+
+(*val _get_Misa_MXL : Misa -> mword ty2*)
+
+val _ = Define `
+ ((get_Misa_MXL:Misa ->(2)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_MXL:Misa ->(2)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_Z : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Z:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Z : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Z:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_Y : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Y:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Y : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Y:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_X : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_X:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_X : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_X:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_X : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_W : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_W:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_W : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_W:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_W : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_V : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_V:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_V : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_V:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_V : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_U : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_U:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_U : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_U:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_U : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_T : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_T:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_T : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_T:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_S : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_S:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_S : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_S:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_R : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_R:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_R : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_R:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_R : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_Q : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_Q:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_Q : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_Q:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_P : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_P:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_P : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_P:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_O : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_O:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_O : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_O:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_N : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_N:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_N : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_N:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_M : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_M:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_M : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_M:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_L : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_L:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_L : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_L:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+(*val _get_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1*)
+
+(*val _set_Pmpcfg_ent_L : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+(*val _get_Misa_K : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_K:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_K : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_K:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_J : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_J:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_J : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_J:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_I : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_I:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_I : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_I:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_H : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_H:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_H : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_H:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_G : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_G:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_G : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_G:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_G : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_F : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_F:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_F : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_F:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_E : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_E:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_E : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_E:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_D : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_D:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_D : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_D:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_D : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val _get_Misa_C : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_C:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_C : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_C:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_B : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_B:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_B : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_B:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Misa_A : Misa -> mword ty1*)
+
+val _ = Define `
+ ((get_Misa_A:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Misa_A : Misa -> mword ty1 -> Misa*)
+
+val _ = Define `
+ ((update_Misa_A:Misa ->(1)words$word -> Misa) v x=
+ ((v with<|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*)
+
+(*val _get_PTE_Bits_A : PTE_Bits -> mword ty1*)
+
+(*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*)
+
+(*val legalize_misa : Misa -> mword ty64 -> M Misa*)
+
+val _ = Define `
+ ((legalize_misa:Misa ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Misa),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Misa) (v : xlenbits)=
+ (if ((sys_enable_writable_misa () )) then
+ let v = (Mk_Misa v) in sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((get_Misa_C v : 1 words$word)) = ((bool_to_bits F : 1 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS (((((bit_to_bool ((access_vec_dec w__0 (( 1 : int):ii))))) = T)))))) (\ (w__1 : bool) .
+ sail2_state_monad$returnS (if w__1 then m
+ else update_Misa_C m ((get_Misa_C v : 1 words$word))))
+ else sail2_state_monad$returnS m))`;
+
+
+(*val haveAtomics : unit -> M bool*)
+
+val _ = Define `
+ ((haveAtomics:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveRVC : unit -> M bool*)
+
+val _ = Define `
+ ((haveRVC:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveMulDiv : unit -> M bool*)
+
+val _ = Define `
+ ((haveMulDiv:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveSupMode : unit -> M bool*)
+
+val _ = Define `
+ ((haveSupMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_S w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveUsrMode : unit -> M bool*)
+
+val _ = Define `
+ ((haveUsrMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_U w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val haveNExt : unit -> M bool*)
+
+val _ = Define `
+ ((haveNExt:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_N w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`;
+
+
+(*val Mk_Mstatus : mword ty64 -> Mstatus*)
+
+val _ = Define `
+ ((Mk_Mstatus:(64)words$word -> Mstatus) v=
+ (<| Mstatus_Mstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Mstatus_bits : Mstatus -> mword ty64*)
+
+val _ = Define `
+ ((get_Mstatus_bits:Mstatus ->(64)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_bits:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_bits:Mstatus ->(64)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SD : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SD:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SD : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_TSR : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TSR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_TW : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TW:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_TVM : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TVM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_MXR : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MXR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_MXR : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_SUM : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SUM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SUM : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MPRV : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPRV:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_XS : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_XS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*)
+
+(*val _get_Sstatus_XS : Sstatus -> mword ty2*)
+
+(*val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*)
+
+(*val _get_Mstatus_FS : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_FS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*)
+
+(*val _get_Sstatus_FS : Sstatus -> mword ty2*)
+
+(*val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*)
+
+(*val _get_Mstatus_MPP : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_Mstatus_MPP:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SPP : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPP:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SPP : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SPIE : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_UPIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Ustatus_UPIE : Ustatus -> mword ty1 -> Ustatus*)
+
+(*val _get_Ustatus_UPIE : Ustatus -> mword ty1*)
+
+(*val _set_Ustatus_UPIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_MIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mstatus_SIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*)
+
+(*val _get_Sstatus_SIE : Sstatus -> mword ty1*)
+
+(*val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+(*val _get_Mstatus_UIE : Mstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) v x=
+ ((v with<|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Ustatus_UIE : Ustatus -> mword ty1 -> Ustatus*)
+
+(*val _get_Ustatus_UIE : Ustatus -> mword ty1*)
+
+(*val _set_Ustatus_UIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit*)
+
+(*val effectivePrivilege : Mstatus -> Privilege -> M Privilege*)
+
+val _ = Define `
+ ((effectivePrivilege:Mstatus -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (priv : Privilege)=
+ (if (((((get_Mstatus_MPRV m : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__0 : 2 words$word)))
+ else sail2_state_monad$read_regS cur_privilege_ref))`;
+
+
+(*val get_mstatus_SXL : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_mstatus_SXL:Mstatus ->(2)words$word) m=
+ ((subrange_vec_dec ((get_Mstatus_bits m : 64 words$word)) (( 35 : int):ii) (( 34 : int):ii) : 2 words$word)))`;
+
+
+(*val set_mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((set_mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) (m : Mstatus) (a : arch_xlen)=
+ (let m =
+ ((update_subrange_vec_dec ((get_Mstatus_bits m : 64 words$word)) (( 35 : int):ii) (( 34 : int):ii) a : 64 words$word)) in
+ Mk_Mstatus m))`;
+
+
+(*val get_mstatus_UXL : Mstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_mstatus_UXL:Mstatus ->(2)words$word) m=
+ ((subrange_vec_dec ((get_Mstatus_bits m : 64 words$word)) (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`;
+
+
+(*val set_mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*)
+
+val _ = Define `
+ ((set_mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) (m : Mstatus) (a : arch_xlen)=
+ (let m =
+ ((update_subrange_vec_dec ((get_Mstatus_bits m : 64 words$word)) (( 33 : int):ii) (( 32 : int):ii) a : 64 words$word)) in
+ Mk_Mstatus m))`;
+
+
+(*val legalize_mstatus : Mstatus -> mword ty64 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_mstatus:Mstatus ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Mstatus) (v : xlenbits)=
+ (let (m : Mstatus) = (Mk_Mstatus v) in
+ let m = (update_Mstatus_XS m ((extStatus_to_bits Off : 2 words$word))) in sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_FS m : 2 words$word))) (\ (w__0 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__0 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_XS m : 2 words$word))) (\ (w__1 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__1 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) (\ (w__2 : bool) .
+ let m = (update_Mstatus_SD m ((bool_to_bits w__2 : 1 words$word))) in
+ let m = (set_mstatus_SXL m ((get_mstatus_SXL o1 : 2 words$word))) in
+ let m = (set_mstatus_UXL m ((get_mstatus_UXL o1 : 2 words$word))) in
+ let m = (update_Mstatus_UPIE m ((bool_to_bits F : 1 words$word))) in
+ let m = (update_Mstatus_UIE m ((bool_to_bits F : 1 words$word))) in
+ sail2_state_monad$returnS m)))`;
+
+
+(*val cur_Architecture : unit -> M Architecture*)
+
+val _ = Define `
+ ((cur_Architecture:unit ->(regstate)sail2_state_monad$sequential_state ->(((Architecture),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (case w__0 of
+ Machine => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . sail2_state_monad$returnS ((get_Misa_MXL w__1 : 2 words$word)))
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . sail2_state_monad$returnS ((get_mstatus_SXL w__2 : 2 words$word)))
+ | User => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . sail2_state_monad$returnS ((get_mstatus_UXL w__3 : 2 words$word)))
+ ) (\ (a : arch_xlen) .
+ (case ((architecture a)) of
+ SOME (a) => sail2_state_monad$returnS a
+ | NONE => internal_error "Invalid current architecture"
+ )))))`;
+
+
+(*val in32BitMode : unit -> M bool*)
+
+val _ = Define `
+ ((in32BitMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) . sail2_state_monad$returnS (((w__0 = RV32))))))`;
+
+
+(*val Mk_Minterrupts : mword ty64 -> Minterrupts*)
+
+val _ = Define `
+ ((Mk_Minterrupts:(64)words$word -> Minterrupts) v=
+ (<| Minterrupts_Minterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Minterrupts_bits : Minterrupts -> mword ty64*)
+
+val _ = Define `
+ ((get_Minterrupts_bits:Minterrupts ->(64)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_bits:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_bits:Minterrupts ->(64)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_UEI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_UEI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_UEI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_STI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_STI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_STI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_UTI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_UTI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_UTI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+(*val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1*)
+
+(*val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+(*val _get_Minterrupts_USI : Minterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_USI:Minterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) v x=
+ ((v with<|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Uinterrupts_USI : Uinterrupts -> mword ty1 -> Uinterrupts*)
+
+(*val _get_Uinterrupts_USI : Uinterrupts -> mword ty1*)
+
+(*val _set_Uinterrupts_USI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit*)
+
+(*val legalize_mip : Minterrupts -> mword ty64 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_mip:Minterrupts ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (v : xlenbits)=
+ (let v = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v : 1 words$word))) in
+ let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in
+ let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))) in sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v : 1 words$word))) in
+ let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v : 1 words$word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v : 1 words$word))
+ else m))))`;
+
+
+(*val legalize_mie : Minterrupts -> mword ty64 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_mie:Minterrupts ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (v : xlenbits)=
+ (let v = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v : 1 words$word))) in
+ let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v : 1 words$word))) in
+ let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v : 1 words$word))) in
+ let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v : 1 words$word))) in
+ let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in
+ let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))) in sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v : 1 words$word))) in
+ let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v : 1 words$word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v : 1 words$word))
+ else m))))`;
+
+
+(*val legalize_mideleg : Minterrupts -> mword ty64 -> Minterrupts*)
+
+val _ = Define `
+ ((legalize_mideleg:Minterrupts ->(64)words$word -> Minterrupts) (o1 : Minterrupts) (v : xlenbits)=
+ (let m = (Mk_Minterrupts v) in
+ let m = (update_Minterrupts_MEI m ((bool_to_bits F : 1 words$word))) in
+ let m = (update_Minterrupts_MTI m ((bool_to_bits F : 1 words$word))) in
+ update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`;
+
+
+(*val Mk_Medeleg : mword ty64 -> Medeleg*)
+
+val _ = Define `
+ ((Mk_Medeleg:(64)words$word -> Medeleg) v=
+ (<| Medeleg_Medeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Medeleg_bits : Medeleg -> mword ty64*)
+
+val _ = Define `
+ ((get_Medeleg_bits:Medeleg ->(64)words$word) v= ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_bits:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_bits:Medeleg ->(64)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x=
+ ((v with<|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1*)
+
+(*val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*)
+
+(*val legalize_medeleg : Medeleg -> mword ty64 -> Medeleg*)
+
+val _ = Define `
+ ((legalize_medeleg:Medeleg ->(64)words$word -> Medeleg) (o1 : Medeleg) (v : xlenbits)=
+ (let m = (Mk_Medeleg v) in
+ update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`;
+
+
+(*val Mk_Mtvec : mword ty64 -> Mtvec*)
+
+val _ = Define `
+ ((Mk_Mtvec:(64)words$word -> Mtvec) v= (<| Mtvec_Mtvec_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Mtvec_bits : Mtvec -> mword ty64*)
+
+val _ = Define `
+ ((get_Mtvec_bits:Mtvec ->(64)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_bits:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_bits:Mtvec ->(64)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mtvec_Base : Mtvec -> mword ty62*)
+
+val _ = Define `
+ ((get_Mtvec_Base:Mtvec ->(62)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)))`;
+
+
+(*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 61 : int):ii) (( 0 : int):ii) : 62 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 61 : int):ii) (( 0 : int):ii) : 62 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mtvec_Mode : Mtvec -> mword ty2*)
+
+val _ = Define `
+ ((get_Mtvec_Mode:Mtvec ->(2)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) v x=
+ ((v with<|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Satp32_Mode : Satp32 -> mword ty1 -> Satp32*)
+
+(*val _get_Satp32_Mode : Satp32 -> mword ty1*)
+
+(*val _set_Satp32_Mode : register_ref regstate register_value Satp32 -> mword ty1 -> M unit*)
+
+(*val legalize_tvec : Mtvec -> mword ty64 -> Mtvec*)
+
+val _ = Define `
+ ((legalize_tvec:Mtvec ->(64)words$word -> Mtvec) (o1 : Mtvec) (v : xlenbits)=
+ (let v = (Mk_Mtvec v) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v : 2 words$word)))) of
+ TV_Direct => v
+ | TV_Vector => v
+ | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 : 2 words$word))
+ )))`;
+
+
+(*val Mk_Mcause : mword ty64 -> Mcause*)
+
+val _ = Define `
+ ((Mk_Mcause:(64)words$word -> Mcause) v= (<| Mcause_Mcause_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Mcause_bits : Mcause -> mword ty64*)
+
+val _ = Define `
+ ((get_Mcause_bits:Mcause ->(64)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_bits:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_bits:Mcause ->(64)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*)
+
+val _ = Define `
+ ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) v=
+ ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Mcause_Cause : Mcause -> mword ty63*)
+
+val _ = Define `
+ ((get_Mcause_Cause:Mcause ->(63)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)))`;
+
+
+(*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*)
+
+val _ = Define `
+ ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) : 63 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*)
+
+val _ = Define `
+ ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) v x=
+ ((v with<|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 62 : int):ii) (( 0 : int):ii) : 63 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*)
+
+val _ = Define `
+ ((tvec_addr:Mtvec -> Mcause ->((64)words$word)option) (m : Mtvec) (c : Mcause)=
+ (let (base : xlenbits) =
+ ((concat_vec ((get_Mtvec_Base m : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word)
+ : 64 words$word)) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m : 2 words$word)))) of
+ TV_Direct => SOME base
+ | TV_Vector =>
+ if (((((get_Mcause_IsInterrupt c : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME ((add_vec base
+ ((shiftl ((EXTZ (( 64 : int):ii) ((get_Mcause_Cause c : 63 words$word)) : 64 words$word))
+ (( 2 : int):ii)
+ : 64 words$word))
+ : 64 words$word))
+ else SOME base
+ | TV_Reserved => NONE
+ )))`;
+
+
+(*val legalize_xepc : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((legalize_xepc:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS
+ (sail2_state$or_boolS (sail2_state_monad$returnS ((sys_enable_writable_misa () )))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) (\ (w__1 :
+ bool) .
+ sail2_state_monad$returnS (if w__1 then (update_vec_dec v (( 0 : int):ii) B0 : 64 words$word)
+ else
+ (and_vec v ((EXTS (( 64 : int):ii) (vec_of_bits [B1;B0;B0] : 3 words$word) : 64 words$word))
+ : 64 words$word)))))`;
+
+
+(*val pc_alignment_mask : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((pc_alignment_mask:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) .
+ sail2_state_monad$returnS ((not_vec
+ ((EXTZ (( 64 : int):ii)
+ (if (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ (vec_of_bits [B0;B0] : 2 words$word)
+ else (vec_of_bits [B1;B0] : 2 words$word))
+ : 64 words$word))
+ : 64 words$word)))))`;
+
+
+(*val Mk_Counteren : mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((Mk_Counteren:(32)words$word -> Counteren) v=
+ (<| Counteren_Counteren_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Counteren_bits : Counteren -> mword ty32*)
+
+val _ = Define `
+ ((get_Counteren_bits:Counteren ->(32)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_bits:((regstate),(register_value),(Counteren))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_bits:Counteren ->(32)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_HPM : Counteren -> mword ty29*)
+
+val _ = Define `
+ ((get_Counteren_HPM:Counteren ->(29)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii) : 29 words$word)))`;
+
+
+(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_HPM:((regstate),(register_value),(Counteren))register_ref ->(29)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 28 : int):ii) (( 0 : int):ii) : 29 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_HPM:Counteren ->(29)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 28 : int):ii) (( 0 : int):ii) : 29 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_IR : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_IR:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_IR:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_IR:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_TM : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_TM:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_TM:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_TM:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_Counteren_CY : Counteren -> mword ty1*)
+
+val _ = Define `
+ ((get_Counteren_CY:Counteren ->(1)words$word) v=
+ ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Counteren_CY:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*)
+
+val _ = Define `
+ ((update_Counteren_CY:Counteren ->(1)words$word -> Counteren) v x=
+ ((v with<|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val legalize_mcounteren : Counteren -> mword ty64 -> Counteren*)
+
+val _ = Define `
+ ((legalize_mcounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in
+ let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`;
+
+
+(*val legalize_scounteren : Counteren -> mword ty64 -> Counteren*)
+
+val _ = Define `
+ ((legalize_scounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)=
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in
+ let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`;
+
+
+(*val retire_instruction : unit -> M unit*)
+
+val _ = Define `
+ ((retire_instruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_written_ref) (\ (w__0 : bool) .
+ if (((w__0 = T))) then sail2_state_monad$write_regS minstret_written_ref F
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$write_regS minstret_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))))))`;
+
+
+(*val Mk_Sstatus : mword ty64 -> Sstatus*)
+
+val _ = Define `
+ ((Mk_Sstatus:(64)words$word -> Sstatus) v=
+ (<| Sstatus_Sstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Sstatus_bits : Sstatus -> mword ty64*)
+
+val _ = Define `
+ ((get_Sstatus_bits:Sstatus ->(64)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_bits:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_bits:Sstatus ->(64)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SD:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_MXR:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SUM:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_XS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_FS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPP:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Sstatus_UPIE : Sstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Sstatus_UPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Sstatus_UIE : Sstatus -> mword ty1*)
+
+val _ = Define `
+ ((get_Sstatus_UIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*)
+
+val _ = Define `
+ ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) v x=
+ ((v with<|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val get_sstatus_UXL : Sstatus -> mword ty2*)
+
+val _ = Define `
+ ((get_sstatus_UXL:Sstatus ->(2)words$word) s=
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s : 64 words$word))) in
+ (get_mstatus_UXL m : 2 words$word)))`;
+
+
+(*val set_sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*)
+
+val _ = Define `
+ ((set_sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) (s : Sstatus) (a : arch_xlen)=
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s : 64 words$word))) in
+ let m = (set_mstatus_UXL m a) in
+ Mk_Sstatus ((get_Mstatus_bits m : 64 words$word))))`;
+
+
+(*val lower_mstatus : Mstatus -> Sstatus*)
+
+val _ = Define `
+ ((lower_mstatus:Mstatus -> Sstatus) m=
+ (let s = (Mk_Sstatus ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let s = (update_Sstatus_SD s ((get_Mstatus_SD m : 1 words$word))) in
+ let s = (set_sstatus_UXL s ((get_mstatus_UXL m : 2 words$word))) in
+ let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m : 1 words$word))) in
+ let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m : 1 words$word))) in
+ let s = (update_Sstatus_XS s ((get_Mstatus_XS m : 2 words$word))) in
+ let s = (update_Sstatus_FS s ((get_Mstatus_FS m : 2 words$word))) in
+ let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m : 1 words$word))) in
+ let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m : 1 words$word))) in
+ let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m : 1 words$word))) in
+ let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m : 1 words$word))) in
+ update_Sstatus_UIE s ((get_Mstatus_UIE m : 1 words$word))))`;
+
+
+(*val lift_sstatus : Mstatus -> Sstatus -> M Mstatus*)
+
+val _ = Define `
+ ((lift_sstatus:Mstatus -> Sstatus ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (s : Sstatus)=
+ (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in
+ let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in
+ let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in
+ let m = (update_Mstatus_FS m ((get_Sstatus_FS s : 2 words$word))) in sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_FS m : 2 words$word))) (\ (w__0 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__0 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))
+ ( sail2_state_monad$bindS(extStatus_of_bits ((get_Mstatus_XS m : 2 words$word))) (\ (w__1 : ExtStatus) .
+ sail2_state_monad$returnS (((((extStatus_to_bits w__1 : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) (\ (w__2 : bool) .
+ let m = (update_Mstatus_SD m ((bool_to_bits w__2 : 1 words$word))) in
+ let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s : 1 words$word))) in
+ let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s : 1 words$word))) in
+ let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s : 1 words$word))) in
+ let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s : 1 words$word))) in
+ let m = (update_Mstatus_UIE m ((get_Sstatus_UIE s : 1 words$word))) in
+ sail2_state_monad$returnS m)))`;
+
+
+(*val legalize_sstatus : Mstatus -> mword ty64 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_sstatus:Mstatus ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (v : xlenbits)= (lift_sstatus m ((Mk_Sstatus v))))`;
+
+
+(*val Mk_Sedeleg : mword ty64 -> Sedeleg*)
+
+val _ = Define `
+ ((Mk_Sedeleg:(64)words$word -> Sedeleg) v=
+ (<| Sedeleg_Sedeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Sedeleg_bits : Sedeleg -> mword ty64*)
+
+val _ = Define `
+ ((get_Sedeleg_bits:Sedeleg ->(64)words$word) v= ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Sedeleg_bits:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg*)
+
+val _ = Define `
+ ((update_Sedeleg_bits:Sedeleg ->(64)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) v=
+ ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x=
+ ((v with<|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*)
+
+val _ = Define `
+ ((legalize_sedeleg:Sedeleg ->(64)words$word -> Sedeleg) (s : Sedeleg) (v : xlenbits)=
+ (Mk_Sedeleg ((EXTZ (( 64 : int):ii) ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word)) : 64 words$word))))`;
+
+
+(*val Mk_Sinterrupts : mword ty64 -> Sinterrupts*)
+
+val _ = Define `
+ ((Mk_Sinterrupts:(64)words$word -> Sinterrupts) v=
+ (<| Sinterrupts_Sinterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty64*)
+
+val _ = Define `
+ ((get_Sinterrupts_bits:Sinterrupts ->(64)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_bits:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_bits:Sinterrupts ->(64)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Sinterrupts_USI : Sinterrupts -> mword ty1*)
+
+val _ = Define `
+ ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*)
+
+val _ = Define `
+ ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) v x=
+ ((v with<|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lower_mip:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)=
+ (let (s : Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lower_mie:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)=
+ (let (s : Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts*)
+
+val _ = Define `
+ ((lift_sip:Minterrupts -> Minterrupts -> Sinterrupts ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)=
+ (let (m : Minterrupts) = o1 in
+ let m =
+ (update_Minterrupts_SSI m
+ ((and_vec ((get_Sinterrupts_SSI s : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word))
+ : 1 words$word))) in sail2_state_monad$bindS
+ (haveNExt () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m =
+ (if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word))
+ else m) in
+ if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word))
+ else m
+ else m))))`;
+
+
+(*val legalize_sip : Minterrupts -> Minterrupts -> mword ty64 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_sip:Minterrupts -> Minterrupts ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
+ (lift_sip m d ((Mk_Sinterrupts v))))`;
+
+
+(*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts*)
+
+val _ = Define `
+ ((lift_sie:Minterrupts -> Minterrupts -> Sinterrupts ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)=
+ (let (m : Minterrupts) = o1 in
+ let m =
+ (if (((((get_Minterrupts_SEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_SEI m ((get_Sinterrupts_SEI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_STI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_STI m ((get_Sinterrupts_STI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_SSI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_SSI m ((get_Sinterrupts_SSI s : 1 words$word))
+ else m) in sail2_state_monad$bindS
+ (haveNExt () ) (\ (w__0 : bool) .
+ sail2_state_monad$returnS (if w__0 then
+ let m =
+ (if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word))
+ else m) in
+ let m =
+ (if (((((get_Minterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Minterrupts_UTI m ((get_Sinterrupts_UTI s : 1 words$word))
+ else m) in
+ if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word))
+ else m
+ else m))))`;
+
+
+(*val legalize_sie : Minterrupts -> Minterrupts -> mword ty64 -> M Minterrupts*)
+
+val _ = Define `
+ ((legalize_sie:Minterrupts -> Minterrupts ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Minterrupts),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)=
+ (lift_sie m d ((Mk_Sinterrupts v))))`;
+
+
+(*val Mk_Satp64 : mword ty64 -> Satp64*)
+
+val _ = Define `
+ ((Mk_Satp64:(64)words$word -> Satp64) v= (<| Satp64_Satp64_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Satp64_bits : Satp64 -> mword ty64*)
+
+val _ = Define `
+ ((get_Satp64_bits:Satp64 ->(64)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_bits:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_bits:Satp64 ->(64)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Satp64_Mode : Satp64 -> mword ty4*)
+
+val _ = Define `
+ ((get_Satp64_Mode:Satp64 ->(4)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii) : 4 words$word)))`;
+
+
+(*val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+ ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii) : 4 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii)
+ ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii) : 4 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_Satp64_Asid : Satp64 -> mword ty16*)
+
+val _ = Define `
+ ((get_Satp64_Asid:Satp64 ->(16)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii) : 16 words$word)))`;
+
+
+(*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+ ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii)
+ ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Satp32_Asid : Satp32 -> mword ty9 -> Satp32*)
+
+(*val _get_Satp32_Asid : Satp32 -> mword ty9*)
+
+(*val _set_Satp32_Asid : register_ref regstate register_value Satp32 -> mword ty9 -> M unit*)
+
+(*val _get_Satp64_PPN : Satp64 -> mword ty44*)
+
+val _ = Define `
+ ((get_Satp64_PPN:Satp64 ->(44)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*)
+
+val _ = Define `
+ ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) v x=
+ ((v with<|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _update_Satp32_PPN : Satp32 -> mword ty22 -> Satp32*)
+
+(*val _get_Satp32_PPN : Satp32 -> mword ty22*)
+
+(*val _set_Satp32_PPN : register_ref regstate register_value Satp32 -> mword ty22 -> M unit*)
+
+(*val legalize_satp64 : Architecture -> mword ty64 -> mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((legalize_satp64:Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : Architecture) (o1 : 64 bits) (v : 64 bits)=
+ (let s = (Mk_Satp64 v) in
+ (case ((satp64Mode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of
+ NONE => o1
+ | SOME (Sv32) => o1
+ | SOME (_) => (get_Satp64_bits s : 64 words$word)
+ )))`;
+
+
+(*val Mk_Satp32 : mword ty32 -> Satp32*)
+
+val _ = Define `
+ ((Mk_Satp32:(32)words$word -> Satp32) v= (<| Satp32_Satp32_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_Satp32_bits : Satp32 -> mword ty32*)
+
+val _ = Define `
+ ((get_Satp32_bits:Satp32 ->(32)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_Satp32_bits : register_ref regstate register_value Satp32 -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_Satp32_bits:((regstate),(register_value),(Satp32))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Satp32_bits : Satp32 -> mword ty32 -> Satp32*)
+
+val _ = Define `
+ ((update_Satp32_bits:Satp32 ->(32)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_Mode:Satp32 ->(1)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_Mode:((regstate),(register_value),(Satp32))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_Mode:Satp32 ->(1)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 31 : int):ii) (( 31 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_Asid:Satp32 ->(9)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii) : 9 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_Asid:((regstate),(register_value),(Satp32))register_ref ->(9)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_Asid:Satp32 ->(9)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 30 : int):ii) (( 22 : int):ii)
+ ((subrange_vec_dec x (( 8 : int):ii) (( 0 : int):ii) : 9 words$word))
+ : 32 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Satp32_PPN:Satp32 ->(22)words$word) v= ((subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii) : 22 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp32_PPN:((regstate),(register_value),(Satp32))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec r.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Satp32_PPN:Satp32 ->(22)words$word -> Satp32) v x=
+ ((v with<|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec v.Satp32_Satp32_chunk_0 (( 21 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val legalize_satp32 : Architecture -> mword ty32 -> mword ty32 -> mword ty32*)
+
+val _ = Define `
+ ((legalize_satp32:Architecture ->(32)words$word ->(32)words$word ->(32)words$word) (a : Architecture) (o1 : 32 bits) (v : 32 bits)= v)`;
+
+
+(*val PmpAddrMatchType_of_num : integer -> PmpAddrMatchType*)
+
+val _ = Define `
+ ((PmpAddrMatchType_of_num:int -> PmpAddrMatchType) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then OFF
+ else if (((p0_ = (( 1 : int):ii)))) then TOR
+ else if (((p0_ = (( 2 : int):ii)))) then NA4
+ else NAPOT))`;
+
+
+(*val num_of_PmpAddrMatchType : PmpAddrMatchType -> integer*)
+
+val _ = Define `
+ ((num_of_PmpAddrMatchType:PmpAddrMatchType -> int) arg_=
+ ((case arg_ of OFF => (( 0 : int):ii) | TOR => (( 1 : int):ii) | NA4 => (( 2 : int):ii) | NAPOT => (( 3 : int):ii) )))`;
+
+
+(*val pmpAddrMatchType_of_bits : mword ty2 -> M PmpAddrMatchType*)
+
+val _ = Define `
+ ((pmpAddrMatchType_of_bits:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((PmpAddrMatchType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bs=
+ (let b__0 = bs in
+ if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS OFF
+ else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS TOR
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS NA4
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS NAPOT
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpAddrMatchType_to_bits : PmpAddrMatchType -> mword ty2*)
+
+val _ = Define `
+ ((pmpAddrMatchType_to_bits:PmpAddrMatchType ->(2)words$word) bs=
+ ((case bs of
+ OFF => (vec_of_bits [B0;B0] : 2 words$word)
+ | TOR => (vec_of_bits [B0;B1] : 2 words$word)
+ | NA4 => (vec_of_bits [B1;B0] : 2 words$word)
+ | NAPOT => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val Mk_Pmpcfg_ent : mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((Mk_Pmpcfg_ent:(8)words$word -> Pmpcfg_ent) v=
+ (<| Pmpcfg_ent_Pmpcfg_ent_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) |>))`;
+
+
+(*val _get_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_bits:Pmpcfg_ent ->(8)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_bits : register_ref regstate register_value Pmpcfg_ent -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_bits:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_bits:Pmpcfg_ent ->(8)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Pmpcfg_ent_L:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Pmpcfg_ent_L:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Pmpcfg_ent_L:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_A:Pmpcfg_ent ->(2)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_A : register_ref regstate register_value Pmpcfg_ent -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_A:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_A:Pmpcfg_ent ->(2)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 4 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_X:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_X : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_X:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_X:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_W:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_W : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_W:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_W:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val _get_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1*)
+
+val _ = Define `
+ ((get_Pmpcfg_ent_R:Pmpcfg_ent ->(1)words$word) v=
+ ((subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+(*val _set_Pmpcfg_ent_R : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit*)
+
+val _ = Define `
+ ((set_Pmpcfg_ent_R:((regstate),(register_value),(Pmpcfg_ent))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec r.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((update_Pmpcfg_ent_R:Pmpcfg_ent ->(1)words$word -> Pmpcfg_ent) v x=
+ ((v with<|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec v.Pmpcfg_ent_Pmpcfg_ent_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val pmpReadCfgReg : integer -> M (mword ty64)*)
+
+val _ = Define `
+ ((pmpReadCfgReg:int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n=
+ (let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__7 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__0 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__1 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__2 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__3 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__4 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__5 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__6 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__7 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))
+ : 40 words$word))
+ : 48 words$word))
+ : 56 words$word))
+ : 64 words$word))))))))))
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__8 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__9 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$returnS ((concat_vec ((get_Pmpcfg_ent_bits w__8 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__9 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__10 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__11 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__12 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__13 : 8 words$word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__14 : 8 words$word))
+ ((get_Pmpcfg_ent_bits w__15 : 8 words$word))
+ : 16 words$word))
+ : 24 words$word))
+ : 32 words$word))
+ : 40 words$word))
+ : 48 words$word))
+ : 56 words$word))
+ : 64 words$word))))))))))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpWriteCfg : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent*)
+
+val _ = Define `
+ ((pmpWriteCfg:Pmpcfg_ent ->(8)words$word -> Pmpcfg_ent) (cfg : Pmpcfg_ent) (v : 8 bits)=
+ (if (((((get_Pmpcfg_ent_L cfg : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then cfg
+ else Mk_Pmpcfg_ent v))`;
+
+
+(*val pmpWriteCfgReg : integer -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((pmpWriteCfgReg:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n v=
+ (let p0_ = n in
+ if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp0cfg_ref ((pmpWriteCfg w__0 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp1cfg_ref)) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp1cfg_ref ((pmpWriteCfg w__1 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp2cfg_ref)) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp2cfg_ref ((pmpWriteCfg w__2 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp3cfg_ref)) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp3cfg_ref ((pmpWriteCfg w__3 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp4cfg_ref)) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp4cfg_ref ((pmpWriteCfg w__4 ((subrange_vec_dec v (( 39 : int):ii) (( 32 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp5cfg_ref)) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp5cfg_ref ((pmpWriteCfg w__5 ((subrange_vec_dec v (( 47 : int):ii) (( 40 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp6cfg_ref)) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp6cfg_ref ((pmpWriteCfg w__6 ((subrange_vec_dec v (( 55 : int):ii) (( 48 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp7cfg_ref)) (\ (w__7 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS pmp7cfg_ref ((pmpWriteCfg w__7 ((subrange_vec_dec v (( 63 : int):ii) (( 56 : int):ii) : 8 words$word))))))))))))
+ else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__8 : Pmpcfg_ent) .
+ let pmp8cfg8 = (pmpWriteCfg w__8 ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__9 : Pmpcfg_ent) .
+ let pmp9cfg9 = (pmpWriteCfg w__9 ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp10cfg_ref
+ ((pmpWriteCfg w__10 ((subrange_vec_dec v (( 23 : int):ii) (( 16 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp11cfg_ref)) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp11cfg_ref
+ ((pmpWriteCfg w__11 ((subrange_vec_dec v (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp12cfg_ref)) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp12cfg_ref
+ ((pmpWriteCfg w__12 ((subrange_vec_dec v (( 39 : int):ii) (( 32 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp13cfg_ref)) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp13cfg_ref
+ ((pmpWriteCfg w__13 ((subrange_vec_dec v (( 47 : int):ii) (( 40 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp14cfg_ref)) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp14cfg_ref
+ ((pmpWriteCfg w__14 ((subrange_vec_dec v (( 55 : int):ii) (( 48 : int):ii) : 8 words$word)))))
+ (sail2_state_monad$read_regS pmp15cfg_ref)) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS
+ pmp15cfg_ref
+ ((pmpWriteCfg w__15 ((subrange_vec_dec v (( 63 : int):ii) (( 56 : int):ii) : 8 words$word))))))))))))
+ else sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F "Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8") (sail2_state_monad$exitS () )))`;
+
+
+(*val pmpWriteAddr : Pmpcfg_ent -> mword ty64 -> mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((pmpWriteAddr:Pmpcfg_ent ->(64)words$word ->(64)words$word ->(64)words$word) (cfg : Pmpcfg_ent) (reg : xlenbits) (v : xlenbits)=
+ (if (((((get_Pmpcfg_ent_L cfg : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then reg
+ else (EXTZ (( 64 : int):ii) ((subrange_vec_dec v (( 53 : int):ii) (( 0 : int):ii) : 54 words$word)) : 64 words$word)))`;
+
+
+(*val pmpAddrRange : Pmpcfg_ent -> mword ty64 -> mword ty64 -> M (maybe ((mword ty64 * mword ty64)))*)
+
+val _ = Define `
+ ((pmpAddrRange:Pmpcfg_ent ->(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((64)words$word#(64)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cfg : Pmpcfg_ent) (pmpaddr : xlenbits) (prev_pmpaddr : xlenbits)= (sail2_state_monad$bindS
+ (pmpAddrMatchType_of_bits ((get_Pmpcfg_ent_A cfg : 2 words$word))) (\ (w__0 : PmpAddrMatchType) .
+ sail2_state_monad$returnS ((case w__0 of
+ OFF => NONE
+ | TOR => SOME ((shiftl prev_pmpaddr (( 2 : int):ii) : 64 words$word), (shiftl pmpaddr (( 2 : int):ii) : 64 words$word))
+ | NA4 =>
+ let lo = ((shiftl pmpaddr (( 2 : int):ii) : 64 words$word)) in
+ SOME (lo, (add_vec_int lo (( 4 : int):ii) : 64 words$word))
+ | NAPOT =>
+ let mask = ((xor_vec pmpaddr ((add_vec_int pmpaddr (( 1 : int):ii) : 64 words$word)) : 64 words$word)) in
+ let lo = ((and_vec pmpaddr ((not_vec mask : 64 words$word)) : 64 words$word)) in
+ let len = ((add_vec_int mask (( 1 : int):ii) : 64 words$word)) in
+ SOME ((shiftl lo (( 2 : int):ii) : 64 words$word),
+ (shiftl ((add_vec lo len : 64 words$word)) (( 2 : int):ii) : 64 words$word))
+ )))))`;
+
+
+(*val pmpCheckRWX : Pmpcfg_ent -> AccessType -> bool*)
+
+val _ = Define `
+ ((pmpCheckRWX:Pmpcfg_ent -> AccessType -> bool) ent acc=
+ ((case acc of
+ Read => (((get_Pmpcfg_ent_R ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ | Write => (((get_Pmpcfg_ent_W ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ | ReadWrite =>
+ ((((((get_Pmpcfg_ent_R ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_Pmpcfg_ent_W ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ | Execute => (((get_Pmpcfg_ent_X ent : 1 words$word)) = ((bool_to_bits T : 1 words$word)))
+ )))`;
+
+
+(*val pmpCheckPerms : Pmpcfg_ent -> AccessType -> Privilege -> bool*)
+
+val _ = Define `
+ ((pmpCheckPerms:Pmpcfg_ent -> AccessType -> Privilege -> bool) ent acc priv=
+ ((case priv of
+ Machine =>
+ if (((((get_Pmpcfg_ent_L ent : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ pmpCheckRWX ent acc
+ else T
+ | _ => pmpCheckRWX ent acc
+ )))`;
+
+
+(*val pmpAddrMatch_of_num : integer -> pmpAddrMatch*)
+
+val _ = Define `
+ ((pmpAddrMatch_of_num:int -> pmpAddrMatch) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PMP_NoMatch
+ else if (((p0_ = (( 1 : int):ii)))) then PMP_PartialMatch
+ else PMP_Match))`;
+
+
+(*val num_of_pmpAddrMatch : pmpAddrMatch -> integer*)
+
+val _ = Define `
+ ((num_of_pmpAddrMatch:pmpAddrMatch -> int) arg_=
+ ((case arg_ of PMP_NoMatch => (( 0 : int):ii) | PMP_PartialMatch => (( 1 : int):ii) | PMP_Match => (( 2 : int):ii) )))`;
+
+
+(*val pmpMatchAddr : mword ty64 -> mword ty64 -> maybe ((mword ty64 * mword ty64)) -> pmpAddrMatch*)
+
+val _ = Define `
+ ((pmpMatchAddr:(64)words$word ->(64)words$word ->(xlenbits#xlenbits)option -> pmpAddrMatch) (addr : xlenbits) (width : xlenbits) (rng : pmp_addr_range)=
+ ((case rng of
+ NONE => PMP_NoMatch
+ | SOME ((lo, hi)) =>
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if (((((zopz0zI_u ((add_vec addr width : 64 words$word)) lo)) \/ ((zopz0zI_u hi addr)))))
+ then
+ PMP_NoMatch
+ else if (((((zopz0zIzJ_u lo addr)) /\ ((zopz0zIzJ_u ((add_vec addr width : 64 words$word)) hi))))) then
+ PMP_Match
+ else PMP_PartialMatch
+ )))`;
+
+
+(*val pmpMatch_of_num : integer -> pmpMatch*)
+
+val _ = Define `
+ ((pmpMatch_of_num:int -> pmpMatch) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PMP_Success
+ else if (((p0_ = (( 1 : int):ii)))) then PMP_Continue
+ else PMP_Fail))`;
+
+
+(*val num_of_pmpMatch : pmpMatch -> integer*)
+
+val _ = Define `
+ ((num_of_pmpMatch:pmpMatch -> int) arg_=
+ ((case arg_ of PMP_Success => (( 0 : int):ii) | PMP_Continue => (( 1 : int):ii) | PMP_Fail => (( 2 : int):ii) )))`;
+
+
+(*val pmpMatchEntry : mword ty64 -> mword ty64 -> AccessType -> Privilege -> Pmpcfg_ent -> mword ty64 -> mword ty64 -> M pmpMatch*)
+
+val _ = Define `
+ ((pmpMatchEntry:(64)words$word ->(64)words$word -> AccessType -> Privilege -> Pmpcfg_ent ->(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((pmpMatch),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : xlenbits) (acc : AccessType) (priv : Privilege) (ent :
+ Pmpcfg_ent) (pmpaddr : xlenbits) (prev_pmpaddr : xlenbits)= (sail2_state_monad$bindS
+ (pmpAddrRange ent pmpaddr prev_pmpaddr : ( (( 64 words$word # 64 words$word))option) M) (\ rng .
+ sail2_state_monad$returnS ((case ((pmpMatchAddr addr width rng)) of
+ PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc priv)) then PMP_Success else PMP_Fail
+ )))))`;
+
+
+(*val pmpCheck : mword ty64 -> integer -> AccessType -> Privilege -> M (maybe ExceptionType)*)
+
+val _ = Define `
+ ((pmpCheck:(64)words$word -> int -> AccessType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->((((ExceptionType)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (acc : AccessType) (priv : Privilege)=
+ (let (width : xlenbits) = ((to_bits (( 64 : int):ii) width : 64 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__0 w__1 ((zeros_implicit (( 64 : int):ii) : 64 words$word))) (\ (w__2 :
+ pmpMatch) . sail2_state_monad$bindS
+ (case w__2 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__3 w__4 w__5) (\ (w__6 : pmpMatch) .
+ (case w__6 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__7 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 64 words$word) M) (\ (w__9 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__7 w__8 w__9) (\ (w__10 : pmpMatch) .
+ (case w__10 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 64 words$word) M) (\ (w__12 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 64 words$word) M) (\ (w__13 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__11 w__12 w__13) (\ (w__14 : pmpMatch) .
+ (case w__14 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__15 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 64 words$word) M) (\ (w__16 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 64 words$word) M) (\ (w__17 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__15 w__16 w__17) (\ (w__18 : pmpMatch) .
+ (case w__18 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__19 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 64 words$word) M) (\ (w__20 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 64 words$word) M) (\ (w__21 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__19 w__20 w__21) (\ (w__22 : pmpMatch) .
+ (case w__22 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__23 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 64 words$word) M) (\ (w__24 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 64 words$word) M) (\ (w__25 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__23 w__24 w__25) (\ (w__26 : pmpMatch) .
+ (case w__26 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__27 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 64 words$word) M) (\ (w__28 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 64 words$word) M) (\ (w__29 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__27 w__28 w__29) (\ (w__30 :
+ pmpMatch) .
+ (case w__30 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__31 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 64 words$word) M) (\ (w__32 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 64 words$word) M) (\ (w__33 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__31 w__32 w__33) (\ (w__34 :
+ pmpMatch) .
+ (case w__34 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__35 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 64 words$word) M) (\ (w__36 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 64 words$word) M) (\ (w__37 : 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__35 w__36 w__37) (\ (w__38 :
+ pmpMatch) .
+ (case w__38 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__39 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 64 words$word) M) (\ (w__40 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 64 words$word) M) (\ (w__41 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__39 w__40 w__41) (\ (w__42 :
+ pmpMatch) .
+ (case w__42 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__43 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 64 words$word) M) (\ (w__44 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 64 words$word) M) (\ (w__45 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__43 w__44 w__45) (\ (w__46 :
+ pmpMatch) .
+ (case w__46 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__47 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 64 words$word) M) (\ (w__48 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 64 words$word) M) (\ (w__49 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__47 w__48 w__49) (\ (w__50 :
+ pmpMatch) .
+ (case w__50 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__51 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 64 words$word) M) (\ (w__52 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 64 words$word) M) (\ (w__53 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__51 w__52 w__53) (\ (w__54 :
+ pmpMatch) .
+ (case w__54 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__55 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 64 words$word) M) (\ (w__56 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 64 words$word) M) (\ (w__57 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__55 w__56 w__57) (\ (w__58 :
+ pmpMatch) .
+ (case w__58 of
+ PMP_Success => sail2_state_monad$returnS T
+ | PMP_Fail => sail2_state_monad$returnS F
+ | PMP_Continue => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__59 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 64 words$word) M) (\ (w__60 :
+ 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 64 words$word) M) (\ (w__61 :
+ 64 words$word) . sail2_state_monad$bindS
+ (pmpMatchEntry addr width acc priv w__59 w__60 w__61) (\ (w__62 :
+ pmpMatch) .
+ sail2_state_monad$returnS ((case w__62 of
+ PMP_Success => T
+ | PMP_Fail => F
+ | PMP_Continue =>
+ (case priv of
+ Machine => T
+ | _ => F
+ )
+ ))))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ ) (\ (check' : bool) .
+ sail2_state_monad$returnS (if check' then NONE
+ else
+ (case acc of
+ Read => SOME E_Load_Access_Fault
+ | Write => SOME E_SAMO_Access_Fault
+ | ReadWrite => SOME E_SAMO_Access_Fault
+ | Execute => SOME E_Fetch_Access_Fault
+ ))))))))`;
+
+
+(*val init_pmp : unit -> M unit*)
+
+val _ = Define `
+ ((init_pmp:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__0 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp0cfg_ref ((update_Pmpcfg_ent_A w__0 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp1cfg_ref)) (\ (w__1 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp1cfg_ref ((update_Pmpcfg_ent_A w__1 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp2cfg_ref)) (\ (w__2 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp2cfg_ref ((update_Pmpcfg_ent_A w__2 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp3cfg_ref)) (\ (w__3 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp3cfg_ref ((update_Pmpcfg_ent_A w__3 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp4cfg_ref)) (\ (w__4 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp4cfg_ref ((update_Pmpcfg_ent_A w__4 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp5cfg_ref)) (\ (w__5 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp5cfg_ref ((update_Pmpcfg_ent_A w__5 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp6cfg_ref)) (\ (w__6 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp6cfg_ref ((update_Pmpcfg_ent_A w__6 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp7cfg_ref)) (\ (w__7 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp7cfg_ref ((update_Pmpcfg_ent_A w__7 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp8cfg_ref)) (\ (w__8 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp8cfg_ref ((update_Pmpcfg_ent_A w__8 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp9cfg_ref)) (\ (w__9 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmp9cfg_ref ((update_Pmpcfg_ent_A w__9 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp10cfg_ref)) (\ (w__10 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp10cfg_ref
+ ((update_Pmpcfg_ent_A w__10 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp11cfg_ref)) (\ (w__11 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp11cfg_ref
+ ((update_Pmpcfg_ent_A w__11 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp12cfg_ref)) (\ (w__12 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp12cfg_ref
+ ((update_Pmpcfg_ent_A w__12 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp13cfg_ref)) (\ (w__13 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp13cfg_ref
+ ((update_Pmpcfg_ent_A w__13 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp14cfg_ref)) (\ (w__14 : Pmpcfg_ent) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ pmp14cfg_ref
+ ((update_Pmpcfg_ent_A w__14 ((pmpAddrMatchType_to_bits OFF : 2 words$word)))))
+ (sail2_state_monad$read_regS pmp15cfg_ref)) (\ (w__15 : Pmpcfg_ent) .
+ sail2_state_monad$write_regS
+ pmp15cfg_ref
+ ((update_Pmpcfg_ent_A w__15 ((pmpAddrMatchType_to_bits OFF : 2 words$word))))))))))))))))))))))`;
+
+
+(*val ext_init_regs : unit -> M unit*)
+
+val _ = Define `
+ ((ext_init_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`;
+
+
+(*
+This function is called after above when running rvfi and allows the model
+to be initialised differently (e.g. CHERI cap regs are initialised
+to omnipotent instead of null).
+ *)
+(*val ext_rvfi_init : unit -> M unit*)
+
+val _ = Define `
+ ((ext_rvfi_init:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`;
+
+
+(*val ext_fetch_check_pc : mword ty64 -> mword ty64 -> Ext_FetchAddr_Check unit*)
+
+val _ = Define `
+ ((ext_fetch_check_pc:(64)words$word ->(64)words$word ->(unit)Ext_FetchAddr_Check) (start_pc : xlenbits) (pc : xlenbits)= (Ext_FetchAddr_OK pc))`;
+
+
+(*val ext_handle_fetch_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_fetch_check_error:unit -> unit) err= () )`;
+
+
+(*val ext_control_check_addr : mword ty64 -> Ext_ControlAddr_Check unit*)
+
+val _ = Define `
+ ((ext_control_check_addr:(64)words$word ->(unit)Ext_ControlAddr_Check) pc= (Ext_ControlAddr_OK pc))`;
+
+
+(*val ext_control_check_pc : mword ty64 -> Ext_ControlAddr_Check unit*)
+
+val _ = Define `
+ ((ext_control_check_pc:(64)words$word ->(unit)Ext_ControlAddr_Check) pc= (Ext_ControlAddr_OK pc))`;
+
+
+(*val ext_handle_control_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_control_check_error:unit -> unit) err= () )`;
+
+
+(*val ext_data_get_addr : mword ty5 -> mword ty64 -> AccessType -> word_width -> M (Ext_DataAddr_Check unit)*)
+
+val _ = Define `
+ ((ext_data_get_addr:(5)words$word ->(64)words$word -> AccessType -> word_width ->(regstate)sail2_state_monad$sequential_state ->((((unit)Ext_DataAddr_Check),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (base : regidx) (offset : xlenbits) (acc : AccessType) (width : word_width)= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno base)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let addr = ((add_vec w__0 offset : 64 words$word)) in
+ sail2_state_monad$returnS (Ext_DataAddr_OK addr))))`;
+
+
+(*val ext_handle_data_check_error : unit -> unit*)
+
+val _ = Define `
+ ((ext_handle_data_check_error:unit -> unit) err= () )`;
+
+
+(*val csr_name : mword ty12 -> string*)
+
+val _ = Define `
+ ((csr_name:(12)words$word -> string) csr=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "ustatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "uie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "utvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "uscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "uepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "ucause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "utval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "uip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "fflags"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "frm"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "fcsr"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "cycle"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "time"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "instret"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "cycleh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "timeh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "instreth"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "sstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "sedeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "sideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "sie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "stvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ "scounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "sscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "sepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "scause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "stval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "sip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "satp"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ "mvendorid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ "marchid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ "mimpid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ "mhartid"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "misa"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "medeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "mideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "mie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ "mtvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ "mcounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ "mepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "mcause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ "mtval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ "mip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "pmpcfg0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ "pmpaddr0"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mcycle"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "minstret"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "mcycleh"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ "minstreth"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ "tselect"
+ else "UNKNOWN"))`;
+
+
+(*val csr_name_map_forwards : mword ty12 -> M string*)
+
+val _ = Define `
+ ((csr_name_map_forwards:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "ustatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "utvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "uepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "ucause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "utval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "uip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "fflags"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "frm"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "fcsr"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "cycle"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "time"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "instret"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "cycleh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "timeh"
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "instreth"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sedeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "sideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "stvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "scounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "sepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "scause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "stval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "sip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "satp"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mvendorid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "marchid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mimpid"
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mhartid"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mstatus"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "misa"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "medeleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mideleg"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mie"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mtvec"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcounteren"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mscratch"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mepc"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcause"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "mtval"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mip"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg1"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg2"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpcfg3"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr0"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr1"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr2"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr3"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr4"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr5"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr6"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr7"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr8"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr9"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr10"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr11"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr12"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr13"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr14"
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "pmpaddr15"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcycle"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "minstret"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "mcycleh"
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "minstreth"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "tselect"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata1"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata2"
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS "tdata3"
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_name_map_backwards : string -> M (mword ty12)*)
+
+val _ = Define `
+ ((csr_name_map_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((12)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "ustatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "uie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "utvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "uscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "uepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "ucause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "utval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "uip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "fflags"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "frm"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "fcsr"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "cycle"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "time"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "instret"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "cycleh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "timeh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "instreth"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "sstatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "sedeleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "sideleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "sie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "stvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "scounteren"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "sscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "sepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "scause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "stval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "sip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "satp"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "mvendorid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "marchid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mimpid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mhartid"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "mstatus"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "misa"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "medeleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mideleg"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mie"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "mtvec"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "mcounteren"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "mscratch"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "mepc"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "mcause"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mtval"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "mip"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg0"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpcfg2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpcfg3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr0"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr4"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr5"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr6"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr7"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr8"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr9"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr10"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr11"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr12"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr13"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)
+ else if (((p0_ = "pmpaddr14"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)
+ else if (((p0_ = "pmpaddr15"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)
+ else if (((p0_ = "mcycle"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "minstret"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "mcycleh"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "minstreth"))) then
+ sail2_state_monad$returnS (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "tselect"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)
+ else if (((p0_ = "tdata1"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)
+ else if (((p0_ = "tdata2"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)
+ else if (((p0_ = "tdata3"))) then
+ sail2_state_monad$returnS (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_name_map_forwards_matches : mword ty12 -> bool*)
+
+val _ = Define `
+ ((csr_name_map_forwards_matches:(12)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ T
+ else F))`;
+
+
+(*val csr_name_map_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((csr_name_map_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "ustatus"))) then T
+ else if (((p0_ = "uie"))) then T
+ else if (((p0_ = "utvec"))) then T
+ else if (((p0_ = "uscratch"))) then T
+ else if (((p0_ = "uepc"))) then T
+ else if (((p0_ = "ucause"))) then T
+ else if (((p0_ = "utval"))) then T
+ else if (((p0_ = "uip"))) then T
+ else if (((p0_ = "fflags"))) then T
+ else if (((p0_ = "frm"))) then T
+ else if (((p0_ = "fcsr"))) then T
+ else if (((p0_ = "cycle"))) then T
+ else if (((p0_ = "time"))) then T
+ else if (((p0_ = "instret"))) then T
+ else if (((p0_ = "cycleh"))) then T
+ else if (((p0_ = "timeh"))) then T
+ else if (((p0_ = "instreth"))) then T
+ else if (((p0_ = "sstatus"))) then T
+ else if (((p0_ = "sedeleg"))) then T
+ else if (((p0_ = "sideleg"))) then T
+ else if (((p0_ = "sie"))) then T
+ else if (((p0_ = "stvec"))) then T
+ else if (((p0_ = "scounteren"))) then T
+ else if (((p0_ = "sscratch"))) then T
+ else if (((p0_ = "sepc"))) then T
+ else if (((p0_ = "scause"))) then T
+ else if (((p0_ = "stval"))) then T
+ else if (((p0_ = "sip"))) then T
+ else if (((p0_ = "satp"))) then T
+ else if (((p0_ = "mvendorid"))) then T
+ else if (((p0_ = "marchid"))) then T
+ else if (((p0_ = "mimpid"))) then T
+ else if (((p0_ = "mhartid"))) then T
+ else if (((p0_ = "mstatus"))) then T
+ else if (((p0_ = "misa"))) then T
+ else if (((p0_ = "medeleg"))) then T
+ else if (((p0_ = "mideleg"))) then T
+ else if (((p0_ = "mie"))) then T
+ else if (((p0_ = "mtvec"))) then T
+ else if (((p0_ = "mcounteren"))) then T
+ else if (((p0_ = "mscratch"))) then T
+ else if (((p0_ = "mepc"))) then T
+ else if (((p0_ = "mcause"))) then T
+ else if (((p0_ = "mtval"))) then T
+ else if (((p0_ = "mip"))) then T
+ else if (((p0_ = "pmpcfg0"))) then T
+ else if (((p0_ = "pmpcfg1"))) then T
+ else if (((p0_ = "pmpcfg2"))) then T
+ else if (((p0_ = "pmpcfg3"))) then T
+ else if (((p0_ = "pmpaddr0"))) then T
+ else if (((p0_ = "pmpaddr1"))) then T
+ else if (((p0_ = "pmpaddr2"))) then T
+ else if (((p0_ = "pmpaddr3"))) then T
+ else if (((p0_ = "pmpaddr4"))) then T
+ else if (((p0_ = "pmpaddr5"))) then T
+ else if (((p0_ = "pmpaddr6"))) then T
+ else if (((p0_ = "pmpaddr7"))) then T
+ else if (((p0_ = "pmpaddr8"))) then T
+ else if (((p0_ = "pmpaddr9"))) then T
+ else if (((p0_ = "pmpaddr10"))) then T
+ else if (((p0_ = "pmpaddr11"))) then T
+ else if (((p0_ = "pmpaddr12"))) then T
+ else if (((p0_ = "pmpaddr13"))) then T
+ else if (((p0_ = "pmpaddr14"))) then T
+ else if (((p0_ = "pmpaddr15"))) then T
+ else if (((p0_ = "mcycle"))) then T
+ else if (((p0_ = "minstret"))) then T
+ else if (((p0_ = "mcycleh"))) then T
+ else if (((p0_ = "minstreth"))) then T
+ else if (((p0_ = "tselect"))) then T
+ else if (((p0_ = "tdata1"))) then T
+ else if (((p0_ = "tdata2"))) then T
+ else if (((p0_ = "tdata3"))) then T
+ else F))`;
+
+
+(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*)
+
+(*val _s488_ : string -> maybe string*)
+
+val _ = Define `
+ ((s488_:string ->(string)option) s489_0=
+ (let s490_0 = s489_0 in
+ if ((string_startswith s490_0 "tdata3")) then
+ (case ((string_drop s490_0 ((string_length "tdata3")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s484_ : string -> maybe string*)
+
+val _ = Define `
+ ((s484_:string ->(string)option) s485_0=
+ (let s486_0 = s485_0 in
+ if ((string_startswith s486_0 "tdata2")) then
+ (case ((string_drop s486_0 ((string_length "tdata2")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s480_ : string -> maybe string*)
+
+val _ = Define `
+ ((s480_:string ->(string)option) s481_0=
+ (let s482_0 = s481_0 in
+ if ((string_startswith s482_0 "tdata1")) then
+ (case ((string_drop s482_0 ((string_length "tdata1")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s476_ : string -> maybe string*)
+
+val _ = Define `
+ ((s476_:string ->(string)option) s477_0=
+ (let s478_0 = s477_0 in
+ if ((string_startswith s478_0 "tselect")) then
+ (case ((string_drop s478_0 ((string_length "tselect")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s472_ : string -> maybe string*)
+
+val _ = Define `
+ ((s472_:string ->(string)option) s473_0=
+ (let s474_0 = s473_0 in
+ if ((string_startswith s474_0 "minstreth")) then
+ (case ((string_drop s474_0 ((string_length "minstreth")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s468_ : string -> maybe string*)
+
+val _ = Define `
+ ((s468_:string ->(string)option) s469_0=
+ (let s470_0 = s469_0 in
+ if ((string_startswith s470_0 "mcycleh")) then
+ (case ((string_drop s470_0 ((string_length "mcycleh")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s464_ : string -> maybe string*)
+
+val _ = Define `
+ ((s464_:string ->(string)option) s465_0=
+ (let s466_0 = s465_0 in
+ if ((string_startswith s466_0 "minstret")) then
+ (case ((string_drop s466_0 ((string_length "minstret")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s460_ : string -> maybe string*)
+
+val _ = Define `
+ ((s460_:string ->(string)option) s461_0=
+ (let s462_0 = s461_0 in
+ if ((string_startswith s462_0 "mcycle")) then
+ (case ((string_drop s462_0 ((string_length "mcycle")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s456_ : string -> maybe string*)
+
+val _ = Define `
+ ((s456_:string ->(string)option) s457_0=
+ (let s458_0 = s457_0 in
+ if ((string_startswith s458_0 "pmpaddr15")) then
+ (case ((string_drop s458_0 ((string_length "pmpaddr15")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s452_ : string -> maybe string*)
+
+val _ = Define `
+ ((s452_:string ->(string)option) s453_0=
+ (let s454_0 = s453_0 in
+ if ((string_startswith s454_0 "pmpaddr14")) then
+ (case ((string_drop s454_0 ((string_length "pmpaddr14")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s448_ : string -> maybe string*)
+
+val _ = Define `
+ ((s448_:string ->(string)option) s449_0=
+ (let s450_0 = s449_0 in
+ if ((string_startswith s450_0 "pmpaddr13")) then
+ (case ((string_drop s450_0 ((string_length "pmpaddr13")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s444_ : string -> maybe string*)
+
+val _ = Define `
+ ((s444_:string ->(string)option) s445_0=
+ (let s446_0 = s445_0 in
+ if ((string_startswith s446_0 "pmpaddr12")) then
+ (case ((string_drop s446_0 ((string_length "pmpaddr12")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s440_ : string -> maybe string*)
+
+val _ = Define `
+ ((s440_:string ->(string)option) s441_0=
+ (let s442_0 = s441_0 in
+ if ((string_startswith s442_0 "pmpaddr11")) then
+ (case ((string_drop s442_0 ((string_length "pmpaddr11")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s436_ : string -> maybe string*)
+
+val _ = Define `
+ ((s436_:string ->(string)option) s437_0=
+ (let s438_0 = s437_0 in
+ if ((string_startswith s438_0 "pmpaddr10")) then
+ (case ((string_drop s438_0 ((string_length "pmpaddr10")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s432_ : string -> maybe string*)
+
+val _ = Define `
+ ((s432_:string ->(string)option) s433_0=
+ (let s434_0 = s433_0 in
+ if ((string_startswith s434_0 "pmpaddr9")) then
+ (case ((string_drop s434_0 ((string_length "pmpaddr9")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s428_ : string -> maybe string*)
+
+val _ = Define `
+ ((s428_:string ->(string)option) s429_0=
+ (let s430_0 = s429_0 in
+ if ((string_startswith s430_0 "pmpaddr8")) then
+ (case ((string_drop s430_0 ((string_length "pmpaddr8")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s424_ : string -> maybe string*)
+
+val _ = Define `
+ ((s424_:string ->(string)option) s425_0=
+ (let s426_0 = s425_0 in
+ if ((string_startswith s426_0 "pmpaddr7")) then
+ (case ((string_drop s426_0 ((string_length "pmpaddr7")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s420_ : string -> maybe string*)
+
+val _ = Define `
+ ((s420_:string ->(string)option) s421_0=
+ (let s422_0 = s421_0 in
+ if ((string_startswith s422_0 "pmpaddr6")) then
+ (case ((string_drop s422_0 ((string_length "pmpaddr6")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s416_ : string -> maybe string*)
+
+val _ = Define `
+ ((s416_:string ->(string)option) s417_0=
+ (let s418_0 = s417_0 in
+ if ((string_startswith s418_0 "pmpaddr5")) then
+ (case ((string_drop s418_0 ((string_length "pmpaddr5")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s412_ : string -> maybe string*)
+
+val _ = Define `
+ ((s412_:string ->(string)option) s413_0=
+ (let s414_0 = s413_0 in
+ if ((string_startswith s414_0 "pmpaddr4")) then
+ (case ((string_drop s414_0 ((string_length "pmpaddr4")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s408_ : string -> maybe string*)
+
+val _ = Define `
+ ((s408_:string ->(string)option) s409_0=
+ (let s410_0 = s409_0 in
+ if ((string_startswith s410_0 "pmpaddr3")) then
+ (case ((string_drop s410_0 ((string_length "pmpaddr3")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s404_ : string -> maybe string*)
+
+val _ = Define `
+ ((s404_:string ->(string)option) s405_0=
+ (let s406_0 = s405_0 in
+ if ((string_startswith s406_0 "pmpaddr2")) then
+ (case ((string_drop s406_0 ((string_length "pmpaddr2")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s400_ : string -> maybe string*)
+
+val _ = Define `
+ ((s400_:string ->(string)option) s401_0=
+ (let s402_0 = s401_0 in
+ if ((string_startswith s402_0 "pmpaddr1")) then
+ (case ((string_drop s402_0 ((string_length "pmpaddr1")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s396_ : string -> maybe string*)
+
+val _ = Define `
+ ((s396_:string ->(string)option) s397_0=
+ (let s398_0 = s397_0 in
+ if ((string_startswith s398_0 "pmpaddr0")) then
+ (case ((string_drop s398_0 ((string_length "pmpaddr0")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s392_ : string -> maybe string*)
+
+val _ = Define `
+ ((s392_:string ->(string)option) s393_0=
+ (let s394_0 = s393_0 in
+ if ((string_startswith s394_0 "pmpcfg3")) then
+ (case ((string_drop s394_0 ((string_length "pmpcfg3")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s388_ : string -> maybe string*)
+
+val _ = Define `
+ ((s388_:string ->(string)option) s389_0=
+ (let s390_0 = s389_0 in
+ if ((string_startswith s390_0 "pmpcfg2")) then
+ (case ((string_drop s390_0 ((string_length "pmpcfg2")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s384_ : string -> maybe string*)
+
+val _ = Define `
+ ((s384_:string ->(string)option) s385_0=
+ (let s386_0 = s385_0 in
+ if ((string_startswith s386_0 "pmpcfg1")) then
+ (case ((string_drop s386_0 ((string_length "pmpcfg1")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s380_ : string -> maybe string*)
+
+val _ = Define `
+ ((s380_:string ->(string)option) s381_0=
+ (let s382_0 = s381_0 in
+ if ((string_startswith s382_0 "pmpcfg0")) then
+ (case ((string_drop s382_0 ((string_length "pmpcfg0")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s376_ : string -> maybe string*)
+
+val _ = Define `
+ ((s376_:string ->(string)option) s377_0=
+ (let s378_0 = s377_0 in
+ if ((string_startswith s378_0 "mip")) then
+ (case ((string_drop s378_0 ((string_length "mip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s372_ : string -> maybe string*)
+
+val _ = Define `
+ ((s372_:string ->(string)option) s373_0=
+ (let s374_0 = s373_0 in
+ if ((string_startswith s374_0 "mtval")) then
+ (case ((string_drop s374_0 ((string_length "mtval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s368_ : string -> maybe string*)
+
+val _ = Define `
+ ((s368_:string ->(string)option) s369_0=
+ (let s370_0 = s369_0 in
+ if ((string_startswith s370_0 "mcause")) then
+ (case ((string_drop s370_0 ((string_length "mcause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s364_ : string -> maybe string*)
+
+val _ = Define `
+ ((s364_:string ->(string)option) s365_0=
+ (let s366_0 = s365_0 in
+ if ((string_startswith s366_0 "mepc")) then
+ (case ((string_drop s366_0 ((string_length "mepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s360_ : string -> maybe string*)
+
+val _ = Define `
+ ((s360_:string ->(string)option) s361_0=
+ (let s362_0 = s361_0 in
+ if ((string_startswith s362_0 "mscratch")) then
+ (case ((string_drop s362_0 ((string_length "mscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s356_ : string -> maybe string*)
+
+val _ = Define `
+ ((s356_:string ->(string)option) s357_0=
+ (let s358_0 = s357_0 in
+ if ((string_startswith s358_0 "mcounteren")) then
+ (case ((string_drop s358_0 ((string_length "mcounteren")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s352_ : string -> maybe string*)
+
+val _ = Define `
+ ((s352_:string ->(string)option) s353_0=
+ (let s354_0 = s353_0 in
+ if ((string_startswith s354_0 "mtvec")) then
+ (case ((string_drop s354_0 ((string_length "mtvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s348_ : string -> maybe string*)
+
+val _ = Define `
+ ((s348_:string ->(string)option) s349_0=
+ (let s350_0 = s349_0 in
+ if ((string_startswith s350_0 "mie")) then
+ (case ((string_drop s350_0 ((string_length "mie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s344_ : string -> maybe string*)
+
+val _ = Define `
+ ((s344_:string ->(string)option) s345_0=
+ (let s346_0 = s345_0 in
+ if ((string_startswith s346_0 "mideleg")) then
+ (case ((string_drop s346_0 ((string_length "mideleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s340_ : string -> maybe string*)
+
+val _ = Define `
+ ((s340_:string ->(string)option) s341_0=
+ (let s342_0 = s341_0 in
+ if ((string_startswith s342_0 "medeleg")) then
+ (case ((string_drop s342_0 ((string_length "medeleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s336_ : string -> maybe string*)
+
+val _ = Define `
+ ((s336_:string ->(string)option) s337_0=
+ (let s338_0 = s337_0 in
+ if ((string_startswith s338_0 "misa")) then
+ (case ((string_drop s338_0 ((string_length "misa")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s332_ : string -> maybe string*)
+
+val _ = Define `
+ ((s332_:string ->(string)option) s333_0=
+ (let s334_0 = s333_0 in
+ if ((string_startswith s334_0 "mstatus")) then
+ (case ((string_drop s334_0 ((string_length "mstatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s328_ : string -> maybe string*)
+
+val _ = Define `
+ ((s328_:string ->(string)option) s329_0=
+ (let s330_0 = s329_0 in
+ if ((string_startswith s330_0 "mhartid")) then
+ (case ((string_drop s330_0 ((string_length "mhartid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s324_ : string -> maybe string*)
+
+val _ = Define `
+ ((s324_:string ->(string)option) s325_0=
+ (let s326_0 = s325_0 in
+ if ((string_startswith s326_0 "mimpid")) then
+ (case ((string_drop s326_0 ((string_length "mimpid")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s320_ : string -> maybe string*)
+
+val _ = Define `
+ ((s320_:string ->(string)option) s321_0=
+ (let s322_0 = s321_0 in
+ if ((string_startswith s322_0 "marchid")) then
+ (case ((string_drop s322_0 ((string_length "marchid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s316_ : string -> maybe string*)
+
+val _ = Define `
+ ((s316_:string ->(string)option) s317_0=
+ (let s318_0 = s317_0 in
+ if ((string_startswith s318_0 "mvendorid")) then
+ (case ((string_drop s318_0 ((string_length "mvendorid")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s312_ : string -> maybe string*)
+
+val _ = Define `
+ ((s312_:string ->(string)option) s313_0=
+ (let s314_0 = s313_0 in
+ if ((string_startswith s314_0 "satp")) then
+ (case ((string_drop s314_0 ((string_length "satp")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s308_ : string -> maybe string*)
+
+val _ = Define `
+ ((s308_:string ->(string)option) s309_0=
+ (let s310_0 = s309_0 in
+ if ((string_startswith s310_0 "sip")) then
+ (case ((string_drop s310_0 ((string_length "sip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s304_ : string -> maybe string*)
+
+val _ = Define `
+ ((s304_:string ->(string)option) s305_0=
+ (let s306_0 = s305_0 in
+ if ((string_startswith s306_0 "stval")) then
+ (case ((string_drop s306_0 ((string_length "stval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s300_ : string -> maybe string*)
+
+val _ = Define `
+ ((s300_:string ->(string)option) s301_0=
+ (let s302_0 = s301_0 in
+ if ((string_startswith s302_0 "scause")) then
+ (case ((string_drop s302_0 ((string_length "scause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s296_ : string -> maybe string*)
+
+val _ = Define `
+ ((s296_:string ->(string)option) s297_0=
+ (let s298_0 = s297_0 in
+ if ((string_startswith s298_0 "sepc")) then
+ (case ((string_drop s298_0 ((string_length "sepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s292_ : string -> maybe string*)
+
+val _ = Define `
+ ((s292_:string ->(string)option) s293_0=
+ (let s294_0 = s293_0 in
+ if ((string_startswith s294_0 "sscratch")) then
+ (case ((string_drop s294_0 ((string_length "sscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s288_ : string -> maybe string*)
+
+val _ = Define `
+ ((s288_:string ->(string)option) s289_0=
+ (let s290_0 = s289_0 in
+ if ((string_startswith s290_0 "scounteren")) then
+ (case ((string_drop s290_0 ((string_length "scounteren")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s284_ : string -> maybe string*)
+
+val _ = Define `
+ ((s284_:string ->(string)option) s285_0=
+ (let s286_0 = s285_0 in
+ if ((string_startswith s286_0 "stvec")) then
+ (case ((string_drop s286_0 ((string_length "stvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s280_ : string -> maybe string*)
+
+val _ = Define `
+ ((s280_:string ->(string)option) s281_0=
+ (let s282_0 = s281_0 in
+ if ((string_startswith s282_0 "sie")) then
+ (case ((string_drop s282_0 ((string_length "sie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s276_ : string -> maybe string*)
+
+val _ = Define `
+ ((s276_:string ->(string)option) s277_0=
+ (let s278_0 = s277_0 in
+ if ((string_startswith s278_0 "sideleg")) then
+ (case ((string_drop s278_0 ((string_length "sideleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s272_ : string -> maybe string*)
+
+val _ = Define `
+ ((s272_:string ->(string)option) s273_0=
+ (let s274_0 = s273_0 in
+ if ((string_startswith s274_0 "sedeleg")) then
+ (case ((string_drop s274_0 ((string_length "sedeleg")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s268_ : string -> maybe string*)
+
+val _ = Define `
+ ((s268_:string ->(string)option) s269_0=
+ (let s270_0 = s269_0 in
+ if ((string_startswith s270_0 "sstatus")) then
+ (case ((string_drop s270_0 ((string_length "sstatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s264_ : string -> maybe string*)
+
+val _ = Define `
+ ((s264_:string ->(string)option) s265_0=
+ (let s266_0 = s265_0 in
+ if ((string_startswith s266_0 "instreth")) then
+ (case ((string_drop s266_0 ((string_length "instreth")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s260_ : string -> maybe string*)
+
+val _ = Define `
+ ((s260_:string ->(string)option) s261_0=
+ (let s262_0 = s261_0 in
+ if ((string_startswith s262_0 "timeh")) then
+ (case ((string_drop s262_0 ((string_length "timeh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s256_ : string -> maybe string*)
+
+val _ = Define `
+ ((s256_:string ->(string)option) s257_0=
+ (let s258_0 = s257_0 in
+ if ((string_startswith s258_0 "cycleh")) then
+ (case ((string_drop s258_0 ((string_length "cycleh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s252_ : string -> maybe string*)
+
+val _ = Define `
+ ((s252_:string ->(string)option) s253_0=
+ (let s254_0 = s253_0 in
+ if ((string_startswith s254_0 "instret")) then
+ (case ((string_drop s254_0 ((string_length "instret")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s248_ : string -> maybe string*)
+
+val _ = Define `
+ ((s248_:string ->(string)option) s249_0=
+ (let s250_0 = s249_0 in
+ if ((string_startswith s250_0 "time")) then
+ (case ((string_drop s250_0 ((string_length "time")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s244_ : string -> maybe string*)
+
+val _ = Define `
+ ((s244_:string ->(string)option) s245_0=
+ (let s246_0 = s245_0 in
+ if ((string_startswith s246_0 "cycle")) then
+ (case ((string_drop s246_0 ((string_length "cycle")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s240_ : string -> maybe string*)
+
+val _ = Define `
+ ((s240_:string ->(string)option) s241_0=
+ (let s242_0 = s241_0 in
+ if ((string_startswith s242_0 "fcsr")) then
+ (case ((string_drop s242_0 ((string_length "fcsr")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s236_ : string -> maybe string*)
+
+val _ = Define `
+ ((s236_:string ->(string)option) s237_0=
+ (let s238_0 = s237_0 in
+ if ((string_startswith s238_0 "frm")) then
+ (case ((string_drop s238_0 ((string_length "frm")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s232_ : string -> maybe string*)
+
+val _ = Define `
+ ((s232_:string ->(string)option) s233_0=
+ (let s234_0 = s233_0 in
+ if ((string_startswith s234_0 "fflags")) then
+ (case ((string_drop s234_0 ((string_length "fflags")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s228_ : string -> maybe string*)
+
+val _ = Define `
+ ((s228_:string ->(string)option) s229_0=
+ (let s230_0 = s229_0 in
+ if ((string_startswith s230_0 "uip")) then
+ (case ((string_drop s230_0 ((string_length "uip")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s224_ : string -> maybe string*)
+
+val _ = Define `
+ ((s224_:string ->(string)option) s225_0=
+ (let s226_0 = s225_0 in
+ if ((string_startswith s226_0 "utval")) then
+ (case ((string_drop s226_0 ((string_length "utval")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s220_ : string -> maybe string*)
+
+val _ = Define `
+ ((s220_:string ->(string)option) s221_0=
+ (let s222_0 = s221_0 in
+ if ((string_startswith s222_0 "ucause")) then
+ (case ((string_drop s222_0 ((string_length "ucause")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s216_ : string -> maybe string*)
+
+val _ = Define `
+ ((s216_:string ->(string)option) s217_0=
+ (let s218_0 = s217_0 in
+ if ((string_startswith s218_0 "uepc")) then
+ (case ((string_drop s218_0 ((string_length "uepc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s212_ : string -> maybe string*)
+
+val _ = Define `
+ ((s212_:string ->(string)option) s213_0=
+ (let s214_0 = s213_0 in
+ if ((string_startswith s214_0 "uscratch")) then
+ (case ((string_drop s214_0 ((string_length "uscratch")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s208_ : string -> maybe string*)
+
+val _ = Define `
+ ((s208_:string ->(string)option) s209_0=
+ (let s210_0 = s209_0 in
+ if ((string_startswith s210_0 "utvec")) then
+ (case ((string_drop s210_0 ((string_length "utvec")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s204_ : string -> maybe string*)
+
+val _ = Define `
+ ((s204_:string ->(string)option) s205_0=
+ (let s206_0 = s205_0 in
+ if ((string_startswith s206_0 "uie")) then
+ (case ((string_drop s206_0 ((string_length "uie")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s200_ : string -> maybe string*)
+
+val _ = Define `
+ ((s200_:string ->(string)option) s201_0=
+ (let s202_0 = s201_0 in
+ if ((string_startswith s202_0 "ustatus")) then
+ (case ((string_drop s202_0 ((string_length "ustatus")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((csr_name_map_matches_prefix:string ->((12)words$word#int)option) arg_=
+ (let s203_0 = arg_ in
+ if ((case ((s200_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s200_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s204_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s204_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s208_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s208_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s212_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s212_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s216_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s216_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s220_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s220_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s224_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s224_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s228_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s228_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s232_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s232_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s236_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s236_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s240_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s240_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s244_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s244_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s248_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s248_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s252_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s252_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s256_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s256_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s260_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s260_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s264_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s264_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s268_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s268_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s272_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s272_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s276_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s276_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s280_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s280_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s284_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s284_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s288_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s288_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s292_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s292_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s296_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s296_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s300_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s300_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s304_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s304_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s308_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s308_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s312_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s312_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s316_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s316_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s320_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s320_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s324_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s324_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s328_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s328_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s332_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s332_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s336_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s336_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s340_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s340_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s344_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s344_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s348_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s348_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s352_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s352_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s356_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s356_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s360_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s360_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s364_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s364_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s368_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s368_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s372_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s372_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s376_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s376_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s380_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s380_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s384_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s384_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s388_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s388_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s392_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s392_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s396_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s396_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s400_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s400_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s404_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s404_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s408_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s408_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s412_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s412_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s416_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s416_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s420_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s420_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s424_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s424_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s428_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s428_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s432_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s432_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s436_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s436_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s440_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s440_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s444_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s444_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s448_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s448_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s452_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s452_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s456_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s456_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s460_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s460_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s464_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s464_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s468_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s468_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s472_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s472_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s476_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s476_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s480_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s480_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s484_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s484_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s488_ s203_0)) of SOME (s_) => T | _ => F )) then
+ (case s488_ s203_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val Mk_Ustatus : mword ty64 -> Ustatus*)
+
+val _ = Define `
+ ((Mk_Ustatus:(64)words$word -> Ustatus) v=
+ (<| Ustatus_Ustatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Ustatus_bits : Ustatus -> mword ty64*)
+
+val _ = Define `
+ ((get_Ustatus_bits:Ustatus ->(64)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Ustatus_bits : register_ref regstate register_value Ustatus -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Ustatus_bits:((regstate),(register_value),(Ustatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Ustatus_bits : Ustatus -> mword ty64 -> Ustatus*)
+
+val _ = Define `
+ ((update_Ustatus_bits:Ustatus ->(64)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Ustatus_UPIE:Ustatus ->(1)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Ustatus_UPIE:((regstate),(register_value),(Ustatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Ustatus_UPIE:Ustatus ->(1)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Ustatus_UIE:Ustatus ->(1)words$word) v= ((subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Ustatus_UIE:((regstate),(register_value),(Ustatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec r.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Ustatus_UIE:Ustatus ->(1)words$word -> Ustatus) v x=
+ ((v with<|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec v.Ustatus_Ustatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val lower_sstatus : Sstatus -> Ustatus*)
+
+val _ = Define `
+ ((lower_sstatus:Sstatus -> Ustatus) s=
+ (let u = (Mk_Ustatus ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let u = (update_Ustatus_UPIE u ((get_Sstatus_UPIE s : 1 words$word))) in
+ update_Ustatus_UIE u ((get_Sstatus_UIE s : 1 words$word))))`;
+
+
+(*val lift_ustatus : Sstatus -> Ustatus -> Sstatus*)
+
+val _ = Define `
+ ((lift_ustatus:Sstatus -> Ustatus -> Sstatus) (s : Sstatus) (u : Ustatus)=
+ (let s = (update_Sstatus_UPIE s ((get_Ustatus_UPIE u : 1 words$word))) in
+ update_Sstatus_UIE s ((get_Ustatus_UIE u : 1 words$word))))`;
+
+
+(*val legalize_ustatus : Mstatus -> mword ty64 -> M Mstatus*)
+
+val _ = Define `
+ ((legalize_ustatus:Mstatus ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Mstatus),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Mstatus) (v : xlenbits)=
+ (let u = (Mk_Ustatus v) in
+ let s = (lower_mstatus m) in
+ let s = (lift_ustatus s u) in
+ lift_sstatus m s))`;
+
+
+(*val Mk_Uinterrupts : mword ty64 -> Uinterrupts*)
+
+val _ = Define `
+ ((Mk_Uinterrupts:(64)words$word -> Uinterrupts) v=
+ (<| Uinterrupts_Uinterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_Uinterrupts_bits : Uinterrupts -> mword ty64*)
+
+val _ = Define `
+ ((get_Uinterrupts_bits:Uinterrupts ->(64)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_Uinterrupts_bits : register_ref regstate register_value Uinterrupts -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_Uinterrupts_bits:((regstate),(register_value),(Uinterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_Uinterrupts_bits : Uinterrupts -> mword ty64 -> Uinterrupts*)
+
+val _ = Define `
+ ((update_Uinterrupts_bits:Uinterrupts ->(64)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_UEI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_UEI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_UEI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_UTI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_UTI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_UTI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_Uinterrupts_USI:Uinterrupts ->(1)words$word) v=
+ ((subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Uinterrupts_USI:((regstate),(register_value),(Uinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec r.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_Uinterrupts_USI:Uinterrupts ->(1)words$word -> Uinterrupts) v x=
+ ((v with<|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec v.Uinterrupts_Uinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val lower_sip : Sinterrupts -> Sinterrupts -> Uinterrupts*)
+
+val _ = Define `
+ ((lower_sip:Sinterrupts -> Sinterrupts -> Uinterrupts) (s : Sinterrupts) (d : Sinterrupts)=
+ (let (u : Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s : 1 words$word)) ((get_Sinterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s : 1 words$word)) ((get_Sinterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s : 1 words$word)) ((get_Sinterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lower_sie : Sinterrupts -> Sinterrupts -> Uinterrupts*)
+
+val _ = Define `
+ ((lower_sie:Sinterrupts -> Sinterrupts -> Uinterrupts) (s : Sinterrupts) (d : Sinterrupts)=
+ (let (u : Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in
+ let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s : 1 words$word)) ((get_Sinterrupts_UEI d : 1 words$word))
+ : 1 words$word))) in
+ let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s : 1 words$word)) ((get_Sinterrupts_UTI d : 1 words$word))
+ : 1 words$word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s : 1 words$word)) ((get_Sinterrupts_USI d : 1 words$word))
+ : 1 words$word))))`;
+
+
+(*val lift_uip : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lift_uip:Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts) (o1 : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)=
+ (let (s : Sinterrupts) = o1 in
+ if (((((get_Sinterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u : 1 words$word))
+ else s))`;
+
+
+(*val legalize_uip : Sinterrupts -> Sinterrupts -> mword ty64 -> Sinterrupts*)
+
+val _ = Define `
+ ((legalize_uip:Sinterrupts -> Sinterrupts ->(64)words$word -> Sinterrupts) (s : Sinterrupts) (d : Sinterrupts) (v : xlenbits)=
+ (lift_uip s d ((Mk_Uinterrupts v))))`;
+
+
+(*val lift_uie : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts*)
+
+val _ = Define `
+ ((lift_uie:Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts) (o1 : Sinterrupts) (d : Sinterrupts) (u : Uinterrupts)=
+ (let (s : Sinterrupts) = o1 in
+ let s =
+ (if (((((get_Sinterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_UEI s ((get_Uinterrupts_UEI u : 1 words$word))
+ else s) in
+ let s =
+ (if (((((get_Sinterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_UTI s ((get_Uinterrupts_UTI u : 1 words$word))
+ else s) in
+ if (((((get_Sinterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u : 1 words$word))
+ else s))`;
+
+
+(*val legalize_uie : Sinterrupts -> Sinterrupts -> mword ty64 -> Sinterrupts*)
+
+val _ = Define `
+ ((legalize_uie:Sinterrupts -> Sinterrupts ->(64)words$word -> Sinterrupts) (s : Sinterrupts) (d : Sinterrupts) (v : xlenbits)=
+ (lift_uie s d ((Mk_Uinterrupts v))))`;
+
+
+(*val handle_trap_extension : Privilege -> mword ty64 -> maybe unit -> unit*)
+
+val _ = Define `
+ ((handle_trap_extension:Privilege ->(64)words$word ->(unit)option -> unit) (p : Privilege) (pc : xlenbits) (u : unit option)= () )`;
+
+
+(*val prepare_trap_vector : Privilege -> Mcause -> M (mword ty64)*)
+
+val _ = Define `
+ ((prepare_trap_vector:Privilege -> Mcause ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p : Privilege) (cause : Mcause)= (sail2_state_monad$bindS
+ (case p of
+ Machine => sail2_state_monad$read_regS mtvec_ref
+ | Supervisor => sail2_state_monad$read_regS stvec_ref
+ | User => sail2_state_monad$read_regS utvec_ref
+ ) (\ (tvec : Mtvec) .
+ (case ((tvec_addr tvec cause : ( 64 words$word)option)) of
+ SOME (epc) => sail2_state_monad$returnS epc
+ | NONE => (internal_error "Invalid tvec mode" : ( 64 words$word) M)
+ ))))`;
+
+
+(*val get_xret_target : Privilege -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_xret_target:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p=
+ ((case p of
+ Machine => (sail2_state_monad$read_regS mepc_ref : ( 64 words$word) M)
+ | Supervisor => (sail2_state_monad$read_regS sepc_ref : ( 64 words$word) M)
+ | User => (sail2_state_monad$read_regS uepc_ref : ( 64 words$word) M)
+ )))`;
+
+
+(*val set_xret_target : Privilege -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((set_xret_target:Privilege ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p value= (sail2_state_monad$bindS
+ (legalize_xepc value : ( 64 words$word) M) (\ target . sail2_state_monad$seqS
+ (case p of
+ Machine => sail2_state_monad$write_regS mepc_ref target
+ | Supervisor => sail2_state_monad$write_regS sepc_ref target
+ | User => sail2_state_monad$write_regS uepc_ref target
+ )
+ (sail2_state_monad$returnS target))))`;
+
+
+(*val prepare_xret_target : Privilege -> M (mword ty64)*)
+
+val _ = Define `
+ ((prepare_xret_target:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) p= ((get_xret_target p : ( 64 words$word) M)))`;
+
+
+(*val get_mtvec : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_mtvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 64 words$word)))))`;
+
+
+(*val get_stvec : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_stvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS stvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 64 words$word)))))`;
+
+
+(*val get_utvec : unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((get_utvec:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__0 : 64 words$word)))))`;
+
+
+(*val set_mtvec : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((set_mtvec:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS mtvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 64 words$word))))))`;
+
+
+(*val set_stvec : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((set_stvec:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS stvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS stvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS stvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 64 words$word))))))`;
+
+
+(*val set_utvec : mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((set_utvec:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utvec_ref) (\ (w__0 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS utvec_ref ((legalize_tvec w__0 value)))
+ (sail2_state_monad$read_regS utvec_ref)) (\ (w__1 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__1 : 64 words$word))))))`;
+
+
+(*val is_NExt_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((is_NExt_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : 12 bits) (p : Privilege)=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ haveUsrMode ()
+ else sail2_state_monad$returnS F))`;
+
+
+(*val read_NExt_CSR : mword ty12 -> M (maybe (mword ty64))*)
+
+val _ = Define `
+ ((read_NExt_CSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((64)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Ustatus_bits ((lower_sstatus ((lower_mstatus w__0)))) : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__1 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__2 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__3 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Uinterrupts_bits ((lower_sie ((lower_mie w__1 w__2)) w__3)) : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_utvec () : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$returnS (SOME w__4))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS uscratch_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . sail2_state_monad$returnS (SOME w__5))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target User : ( 64 words$word) M) (\ (w__6 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__7 : 64 words$word) .
+ sail2_state_monad$returnS (SOME ((and_vec w__6 w__7 : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS ucause_ref) (\ (w__8 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__8 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS utval_ref : ( 64 words$word) M) (\ (w__9 : 64 words$word) . sail2_state_monad$returnS (SOME w__9))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__10 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__11 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__12 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Uinterrupts_bits ((lower_sip ((lower_mip w__10 w__11)) w__12))
+ : 64 words$word))))))
+ else sail2_state_monad$returnS NONE))`;
+
+
+(*val write_NExt_CSR : mword ty12 -> mword ty64 -> M bool*)
+
+val _ = Define `
+ ((write_NExt_CSR:(12)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)=
+ (let b__0 = csr in sail2_state_monad$bindS
+ (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (legalize_ustatus w__0 value) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__1)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__2 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__3 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__4 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__5 : Sinterrupts) .
+ let sie = (legalize_uie ((lower_mie w__3 w__4)) w__5 value) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . sail2_state_monad$bindS
+ (lift_sie w__6 w__7 sie) (\ (w__8 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__8)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__9 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__9 : 64 words$word))))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_utvec value : ( 64 words$word) M) (\ (w__10 : 64 words$word) . sail2_state_monad$returnS (SOME w__10))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS uscratch_ref value)
+ (sail2_state_monad$read_regS uscratch_ref : ( 64 words$word) M)) (\ (w__11 : 64 words$word) . sail2_state_monad$returnS (SOME w__11))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target User value : ( 64 words$word) M) (\ (w__12 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__12))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits ucause_ref value)
+ (sail2_state_monad$read_regS ucause_ref)) (\ (w__13 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__13 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS utval_ref value)
+ (sail2_state_monad$read_regS utval_ref : ( 64 words$word) M)) (\ (w__14 : 64 words$word) . sail2_state_monad$returnS (SOME w__14))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__15 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__16 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) .
+ let sip = (legalize_uip ((lower_mip w__15 w__16)) w__17 value) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__18 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__19 : Minterrupts) . sail2_state_monad$bindS
+ (lift_sip w__18 w__19 sip) (\ (w__20 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__20)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__21 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__21 : 64 words$word))))))))))
+ else sail2_state_monad$returnS NONE) (\ (res : xlenbits option) .
+ sail2_state_monad$returnS ((case res of
+ SOME (v) =>
+ let (_ : unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr))
+ ((STRCAT " <- "
+ ((STRCAT ((string_of_bits v))
+ ((STRCAT " (input: " ((STRCAT ((string_of_bits value)) ")"))))))))))))
+ else () ) in
+ T
+ | NONE => F
+ )))))`;
+
+
+(*val ext_is_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((ext_is_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (is_NExt_CSR_defined csr p))`;
+
+
+(*val ext_read_CSR : mword ty12 -> M (maybe (mword ty64))*)
+
+val _ = Define `
+ ((ext_read_CSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((64)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr= ((read_NExt_CSR csr : ( ( 64 words$word)option) M)))`;
+
+
+(*val ext_write_CSR : mword ty12 -> mword ty64 -> M bool*)
+
+val _ = Define `
+ ((ext_write_CSR:(12)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= (write_NExt_CSR csr value))`;
+
+
+(*val csrAccess : mword ty12 -> mword ty2*)
+
+val _ = Define `
+ ((csrAccess:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)))`;
+
+
+(*val csrPriv : mword ty12 -> mword ty2*)
+
+val _ = Define `
+ ((csrPriv:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val is_CSR_defined : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((is_CSR_defined:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state_monad$returnS ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) /\ ((((( 64 : int):ii) = (( 32 : int):ii)))))))
+ else ext_is_CSR_defined csr p))`;
+
+
+(*val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool*)
+
+val _ = Define `
+ ((check_CSR_access:(2)words$word ->(2)words$word -> Privilege -> bool -> bool) csrrw csrpr p isWrite=
+ (((~ ((((((isWrite = T))) /\ (((csrrw = (vec_of_bits [B1;B1] : 2 words$word))))))))) /\ ((zopz0zKzJ_u ((privLevel_to_bits p : 2 words$word)) csrpr))))`;
+
+
+(*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ (w__2 :
+ bool) .
+ sail2_state_monad$returnS ((~ w__2)))))`;
+
+
+(*val check_Counteren : mword ty12 -> Privilege -> M bool*)
+
+val _ = Define `
+ ((check_Counteren:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)=
+ ((case (csr, p) of
+ (b__0, Supervisor) =>
+ if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__0 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__1 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__2 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))
+ else
+ sail2_state_monad$returnS ((case (b__0, Supervisor) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T
+ ))
+ | (b__3, User) =>
+ if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__6 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__7 : bool) . sail2_state_monad$returnS ((~ w__7))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__8 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_CY w__8 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__11 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__11 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__12 : bool) . sail2_state_monad$returnS ((~ w__12))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__13 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_TM w__13 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ sail2_state$and_boolS
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mcounteren_ref) (\ (w__16 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__16 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__17 : bool) . sail2_state_monad$returnS ((~ w__17))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS scounteren_ref) (\ (w__18 : Counteren) .
+ sail2_state_monad$returnS (((((get_Counteren_IR w__18 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ else
+ sail2_state_monad$returnS ((case (b__3, User) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T
+ ))
+ | (_, _) =>
+ sail2_state_monad$returnS (if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)
+ csr)) /\ ((zopz0zIzJ_u csr
+ (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then
+ F
+ else T)
+ )))`;
+
+
+(*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*)
+
+val _ = Define `
+ ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)=
+ (sail2_state$and_boolS ((is_CSR_defined csr p))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p
+ isWrite))) (sail2_state$and_boolS ((check_TVM_SATP csr p)) ((check_Counteren csr p))))))`;
+
+
+(*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*)
+
+val _ = Define `
+ ((exception_delegatee:ExceptionType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)=
+ (let idx = (num_of_ExceptionType e) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) .
+ let super = (access_vec_dec ((get_Medeleg_bits w__0 : 64 words$word)) idx) in sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$bindS
+ (if w__1 then
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool super)))
+ (sail2_state$and_boolS ((haveNExt () ))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS sedeleg_ref) (\ (w__3 : Sedeleg) .
+ sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec ((get_Sedeleg_bits w__3 : 64 words$word)) idx)))))))
+ else sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool super))) ((haveNExt () ))) (\ user . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveUsrMode () )) (sail2_state_monad$returnS user)) (\ w__9 . sail2_state_monad$bindS
+ (if w__9 then sail2_state_monad$returnS User
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveSupMode () )) (sail2_state_monad$returnS ((bit_to_bool super)))) (\ (w__11 : bool) .
+ sail2_state_monad$returnS (if w__11 then Supervisor
+ else Machine))) (\ deleg .
+ sail2_state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg : 2 words$word))
+ ((privLevel_to_bits p : 2 words$word)))) then
+ p
+ else deleg))))))))`;
+
+
+(*val findPendingInterrupt : mword ty64 -> maybe InterruptType*)
+
+val _ = Define `
+ ((findPendingInterrupt:(64)words$word ->(InterruptType)option) ip=
+ (let ip = (Mk_Minterrupts ip) in
+ if (((((get_Minterrupts_MEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then
+ SOME I_M_External
+ else if (((((get_Minterrupts_MSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_M_Software
+ else if (((((get_Minterrupts_MTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_M_Timer
+ else if (((((get_Minterrupts_SEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_External
+ else if (((((get_Minterrupts_SSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_Software
+ else if (((((get_Minterrupts_STI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_S_Timer
+ else if (((((get_Minterrupts_UEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_External
+ else if (((((get_Minterrupts_USI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_Software
+ else if (((((get_Minterrupts_UTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ SOME I_U_Timer
+ else NONE))`;
+
+
+(*val processPending : Minterrupts -> Minterrupts -> mword ty64 -> bool -> interrupt_set*)
+
+val _ = Define `
+ ((processPending:Minterrupts -> Minterrupts ->(64)words$word -> bool -> interrupt_set) (xip : Minterrupts) (xie : Minterrupts) (xideleg : xlenbits) (priv_enabled : bool)=
+ (let effective_pend =
+ ((and_vec ((get_Minterrupts_bits xip : 64 words$word))
+ ((and_vec ((get_Minterrupts_bits xie : 64 words$word)) ((not_vec xideleg : 64 words$word))
+ : 64 words$word))
+ : 64 words$word)) in
+ let effective_delg = ((and_vec ((get_Minterrupts_bits xip : 64 words$word)) xideleg : 64 words$word)) in
+ if (((priv_enabled /\ (((effective_pend <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))))))
+ then
+ Ints_Pending effective_pend
+ else if (((effective_delg <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))
+ then
+ Ints_Delegated effective_delg
+ else Ints_Empty () ))`;
+
+
+(*val getPendingSet : Privilege -> M (maybe ((mword ty64 * Privilege)))*)
+
+val _ = Define `
+ ((getPendingSet:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((((64)words$word#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv= (sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__0 "no user mode: M/U or M/S/U system required")
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__1 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__2 : Minterrupts) .
+ let effective_pending =
+ ((and_vec ((get_Minterrupts_bits w__1 : 64 words$word))
+ ((get_Minterrupts_bits w__2 : 64 words$word))
+ : 64 words$word)) in
+ if (((effective_pending = ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))
+ then
+ sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) <> ((privLevel_to_bits Machine : 2 words$word))))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_MIE w__3 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ mIE . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveSupMode () ))
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_SIE w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))))) (\ sIE . sail2_state_monad$bindS
+ (sail2_state$and_boolS ((haveNExt () ))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_UIE w__10 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ uIE . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__12 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__13 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__14 : Minterrupts) .
+ (case ((processPending w__12 w__13 ((get_Minterrupts_bits w__14 : 64 words$word)) mIE)) of
+ Ints_Empty (() ) => sail2_state_monad$returnS NONE
+ | Ints_Pending (p) =>
+ let r = (p, Machine) in
+ sail2_state_monad$returnS (SOME r)
+ | Ints_Delegated (d) => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__15 : bool) .
+ if ((~ w__15)) then
+ sail2_state_monad$returnS (if uIE then
+ let r = (d, User) in
+ SOME r
+ else NONE)
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__16 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) .
+ sail2_state_monad$returnS ((case ((processPending ((Mk_Minterrupts d)) w__16
+ ((get_Sinterrupts_bits w__17 : 64 words$word)) sIE)) of
+ Ints_Empty (() ) => NONE
+ | Ints_Pending (p) =>
+ let r = (p, Supervisor) in
+ SOME r
+ | Ints_Delegated (d) =>
+ if uIE then
+ let r = (d, User) in
+ SOME r
+ else NONE
+ )))))
+ ))))))))))))`;
+
+
+(*val dispatchInterrupt : Privilege -> M (maybe ((InterruptType * Privilege)))*)
+
+val _ = Define `
+ ((dispatchInterrupt:Privilege ->(regstate)sail2_state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv= (sail2_state_monad$bindS
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))
+ (sail2_state$and_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))
+ ( sail2_state_monad$bindS(haveNExt () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) .
+ if w__4 then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) "invalid current privilege")
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__5 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) .
+ let enabled_pending =
+ ((and_vec ((get_Minterrupts_bits w__5 : 64 words$word))
+ ((get_Minterrupts_bits w__6 : 64 words$word))
+ : 64 words$word)) in
+ sail2_state_monad$returnS ((case ((findPendingInterrupt enabled_pending)) of
+ SOME (i) =>
+ let r = (i, Machine) in
+ SOME r
+ | NONE => NONE
+ ))))
+ else sail2_state_monad$bindS
+ (getPendingSet priv : ( (( 64 words$word # Privilege))option) M) (\ (w__7 :
+ (( 64 words$word # Privilege))option) .
+ sail2_state_monad$returnS ((case w__7 of
+ NONE => NONE
+ | SOME ((ip, p)) =>
+ (case ((findPendingInterrupt ip)) of
+ NONE => NONE
+ | SOME (i) =>
+ let r = (i, p) in
+ SOME r
+ )
+ ))))))`;
+
+
+(*val tval : maybe (mword ty64) -> mword ty64*)
+
+val _ = Define `
+ ((tval:((64)words$word)option ->(64)words$word) excinfo=
+ ((case excinfo of
+ SOME (e) => e
+ | NONE => (EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)
+ )))`;
+
+
+(*val rvfi_trap : unit -> unit*)
+
+val _ = Define `
+ ((rvfi_trap:unit -> unit) () = () )`;
+
+
+(*val trap_handler : Privilege -> bool -> mword ty8 -> mword ty64 -> maybe (mword ty64) -> maybe unit -> M (mword ty64)*)
+
+val _ = Define `
+ ((trap_handler:Privilege -> bool ->(8)words$word ->(64)words$word ->(xlenbits)option ->(ext_exception)option ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info :
+ xlenbits option) (ext : ext_exception option)=
+ (let (_ : unit) = (rvfi_trap () ) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "handling "
+ ((STRCAT (if intr then "int#" else "exc#")
+ ((STRCAT ((string_of_bits c))
+ ((STRCAT " at priv "
+ ((STRCAT ((privLevel_to_str del_priv))
+ ((STRCAT " with tval "
+ ((string_of_bits ((tval info : 64 words$word))))))))))))))))
+ else () ) in
+ let (_ : unit) = (cancel_reservation () ) in
+ (case del_priv of
+ Machine => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word)))
+ (set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word)))
+ (set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word)))
+ (sail2_state_monad$write_regS mtval_ref ((tval info : 64 words$word))))
+ (sail2_state_monad$write_regS mepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__2 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mcause_ref)) (\ (w__3 : Mcause) .
+ (prepare_trap_vector del_priv w__3 : ( 64 words$word) M)))))
+ | Supervisor => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__5 "no supervisor mode present for delegation")
+ (set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))))
+ (set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word)))
+ (set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . sail2_state_monad$bindS
+ (case w__7 of
+ User => sail2_state_monad$returnS ((bool_to_bits F : 1 words$word))
+ | Supervisor => sail2_state_monad$returnS ((bool_to_bits T : 1 words$word))
+ | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) M)
+ ) (\ (w__9 : 1 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SPP mstatus_ref w__9)
+ (sail2_state_monad$write_regS stval_ref ((tval info : 64 words$word))))
+ (sail2_state_monad$write_regS sepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__10 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS scause_ref)) (\ (w__11 : Mcause) .
+ (prepare_trap_vector del_priv w__11 : ( 64 words$word) M)))))))
+ | User => sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__13 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS w__13 "no user mode present for delegation")
+ (set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr : 1 words$word))))
+ (set_Mcause_Cause ucause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__14 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_UPIE mstatus_ref ((get_Mstatus_UIE w__14 : 1 words$word)))
+ (set_Mstatus_UIE mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$write_regS utval_ref ((tval info : 64 words$word))))
+ (sail2_state_monad$write_regS uepc_ref pc))
+ (sail2_state_monad$write_regS cur_privilege_ref del_priv))
+ (let (_ : unit) = (handle_trap_extension del_priv pc ext) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__15 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS ucause_ref)) (\ (w__16 : Mcause) .
+ (prepare_trap_vector del_priv w__16 : ( 64 words$word) M)))))
+ )))`;
+
+
+(*val exception_handler : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*)
+
+val _ = Define `
+ ((exception_handler:Privilege -> ctl_result ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)=
+ ((case (cur_priv, ctl) of
+ (_, CTL_TRAP (e)) => sail2_state_monad$bindS
+ (exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv .
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "trapping from "
+ ((STRCAT ((privLevel_to_str cur_priv))
+ ((STRCAT " to "
+ ((STRCAT ((privLevel_to_str del_priv))
+ ((STRCAT " to handle "
+ ((exceptionType_to_str e.sync_exception_trap))))))))))))
+ else () ) in
+ (trap_handler del_priv F ((exceptionType_to_bits e.sync_exception_trap : 8 words$word)) pc
+ e.sync_exception_excinfo e.sync_exception_ext
+ : ( 64 words$word) M))
+ | (_, CTL_MRET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word)))
+ (set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS
+ (privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))) (\ (w__3 : Privilege) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS cur_privilege_ref w__3)
+ (haveUsrMode () )) (\ (w__4 : bool) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_MPP mstatus_ref
+ ((privLevel_to_bits (if w__4 then User else Machine) : 2 words$word)))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__5 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__6 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__6)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target Machine : ( 64 words$word) M) (\ (w__7 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__8 : 64 words$word) .
+ sail2_state_monad$returnS ((and_vec w__7 w__8 : 64 words$word))))))))))
+ | (_, CTL_SRET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__9 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__9 : 1 words$word)))
+ (set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__10 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ cur_privilege_ref
+ (if (((((get_Mstatus_SPP w__10 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))
+ then
+ Supervisor
+ else User))
+ (set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__11 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__11 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__12 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__12)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target Supervisor : ( 64 words$word) M) (\ (w__13 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__14 : 64 words$word) .
+ sail2_state_monad$returnS ((and_vec w__13 w__14 : 64 words$word))))))))
+ | (_, CTL_URET (() )) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Mstatus_UIE mstatus_ref ((get_Mstatus_UPIE w__15 : 1 words$word)))
+ (set_Mstatus_UPIE mstatus_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$write_regS cur_privilege_ref User))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__16 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((string_of_bits ((get_Mstatus_bits w__16 : 64 words$word)))))))))
+ else sail2_state_monad$returnS () ))
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__17 : Privilege) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "ret-ing from "
+ ((STRCAT ((privLevel_to_str prev_priv))
+ ((STRCAT " to " ((privLevel_to_str w__17)))))))))))
+ else sail2_state_monad$returnS () ))
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (prepare_xret_target User : ( 64 words$word) M) (\ (w__18 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__19 : 64 words$word) .
+ sail2_state_monad$returnS ((and_vec w__18 w__19 : 64 words$word)))))))
+ )))`;
+
+
+(*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*)
+
+val _ = Define `
+ ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)=
+ (let (t : sync_exception) =
+ (<| sync_exception_trap := e;
+ sync_exception_excinfo := (SOME addr);
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ set_next_pc w__2)))))`;
+
+
+(*val handle_interrupt : InterruptType -> Privilege -> M unit*)
+
+val _ = Define `
+ ((handle_interrupt:InterruptType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS
+ (trap_handler del_priv T ((interruptType_to_bits i : 8 words$word)) w__0 NONE NONE
+ : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ set_next_pc w__1))))`;
+
+
+(*val init_sys : unit -> M unit*)
+
+val _ = Define `
+ ((init_sys:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS cur_privilege_ref Machine)
+ (sail2_state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Misa_MXL misa_ref ((arch_to_bits RV64 : 2 words$word))))
+ (set_Misa_A misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_C misa_ref ((bool_to_bits ((sys_enable_rvc () )) : 1 words$word))))
+ (set_Misa_I misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_M misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_U misa_ref ((bool_to_bits T : 1 words$word))))
+ (set_Misa_S misa_ref ((bool_to_bits T : 1 words$word))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref ((set_mstatus_SXL w__0 ((get_Misa_MXL w__1 : 2 words$word)))))
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__3 : Misa) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref ((set_mstatus_UXL w__2 ((get_Misa_MXL w__3 : 2 words$word)))))
+ (set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word))))
+ (set_Minterrupts_bits mip_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Minterrupts_bits mie_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Medeleg_bits medeleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Mtvec_bits mtvec_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Mcause_bits mcause_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mepc_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mtval_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mscratch_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mcycle_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS mtime_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (set_Counteren_bits mcounteren_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))))
+ (sail2_state_monad$write_regS minstret_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ (sail2_state_monad$write_regS minstret_written_ref F))
+ (init_pmp () ))
+ (if ((get_config_print_reg () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "CSR mstatus <- "
+ ((STRCAT ((string_of_bits ((get_Mstatus_bits w__4 : 64 words$word))))
+ ((STRCAT " (input: "
+ ((STRCAT
+ ((string_of_bits
+ ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))
+ ")")))))))))))
+ else sail2_state_monad$returnS () )))))))`;
+
+
+(*val elf_tohost : unit -> ii*)
+
+(*val elf_entry : unit -> ii*)
+
+
+
+(*val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))*)
+
+val _ = Define `
+ ((phys_mem_segments:unit ->((64)words$word#(64)words$word)list) () =
+ (((plat_rom_base () : 64 words$word), (plat_rom_size () : 64 words$word)) ::
+ (((plat_ram_base () : 64 words$word), (plat_ram_size () : 64 words$word)) :: [])))`;
+
+
+(*val within_phys_mem : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_phys_mem:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (let addr_int = (lem$w2ui addr) in
+ let ram_base_int = (lem$w2ui ((plat_ram_base () : 64 words$word))) in
+ let rom_base_int = (lem$w2ui ((plat_rom_base () : 64 words$word))) in
+ let ram_size_int = (lem$w2ui ((plat_ram_size () : 64 words$word))) in
+ let rom_size_int = (lem$w2ui ((plat_rom_size () : 64 words$word))) in
+ if (((((ram_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <= ((ram_base_int + ram_size_int)))))))
+ then
+ T
+ else if (((((rom_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <=
+ ((rom_base_int + rom_size_int))))))) then
+ T
+ else
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT "within_phys_mem: "
+ ((STRCAT ((string_of_bits addr)) " not within phys-mem:"))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_rom_base: " ((string_of_bits ((plat_rom_base () : 64 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_rom_size: " ((string_of_bits ((plat_rom_size () : 64 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_ram_base: " ((string_of_bits ((plat_ram_base () : 64 words$word))))))) in
+ let (_ : unit) =
+ (print_dbg
+ ((STRCAT " plat_ram_size: " ((string_of_bits ((plat_ram_size () : 64 words$word))))))) in
+ F))`;
+
+
+(*val within_clint : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_clint:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (let addr_int = (lem$w2ui addr) in
+ let clint_base_int = (lem$w2ui ((plat_clint_base () : 64 words$word))) in
+ let clint_size_int = (lem$w2ui ((plat_clint_size () : 64 words$word))) in
+ (((clint_base_int <= addr_int)) /\ ((((addr_int + ((id width)))) <= ((clint_base_int + clint_size_int)))))))`;
+
+
+(*val within_htif_writable : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_htif_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ ((((((plat_htif_tohost () : 64 words$word)) = addr))) \/ ((((((((add_vec_int ((plat_htif_tohost () : 64 words$word)) (( 4 : int):ii) : 64 words$word)) = addr))) /\ (((width = (( 4 : int):ii)))))))))`;
+
+
+(*val within_htif_readable : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_htif_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ ((((((plat_htif_tohost () : 64 words$word)) = addr))) \/ ((((((((add_vec_int ((plat_htif_tohost () : 64 words$word)) (( 4 : int):ii) : 64 words$word)) = addr))) /\ (((width = (( 4 : int):ii)))))))))`;
+
+
+val _ = Define `
+((MSIP_BASE:(64)words$word)=
+ ((EXTZ (( 64 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 20 words$word)
+ : 64 words$word)))`;
+
+
+val _ = Define `
+((MTIMECMP_BASE:(64)words$word)=
+ ((EXTZ (( 64 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 20 words$word)
+ : 64 words$word)))`;
+
+
+val _ = Define `
+((MTIMECMP_BASE_HI:(64)words$word)=
+ ((EXTZ (( 64 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 20 words$word)
+ : 64 words$word)))`;
+
+
+val _ = Define `
+((MTIME_BASE:(64)words$word)=
+ ((EXTZ (( 64 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0] : 20 words$word)
+ : 64 words$word)))`;
+
+
+val _ = Define `
+((MTIME_BASE_HI:(64)words$word)=
+ ((EXTZ (( 64 : int):ii)
+ (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0] : 20 words$word)
+ : 64 words$word)))`;
+
+
+(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((clint_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width=
+ (let addr = ((sub_vec addr ((plat_clint_base () : 64 words$word)) : 64 words$word)) in
+ if ((((((addr = MSIP_BASE))) /\ ((((((((id width)) = (( 8 : int):ii)))) \/ (((((id width)) = (( 4 : int):ii)))))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits ((get_Minterrupts_MSI w__0 : 1 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__1 : Minterrupts) .
+ sail2_state_monad$returnS (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 : 1 words$word))
+ (((( 8 : int):ii) * ((id width))))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits
+ ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__3 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint<8>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__4)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__5 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__5 (( 64 : int):ii) : 64 words$word)) : 'int8_times_n words$word))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint-hi<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> "
+ ((string_of_bits
+ ((subrange_vec_dec w__6 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__7 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__7 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__8)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__9 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__9 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__10)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__11 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__11 (( 64 : int):ii) : 64 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((addr = MTIME_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__12 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__12)))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__13 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__13 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint[" ((STRCAT ((string_of_bits addr)) "] -> <not-mapped>"))))
+ else () ) in
+ sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val clint_dispatch : unit -> M unit*)
+
+val _ = Define `
+ ((clint_dispatch:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT "clint::tick mtime <- " ((string_of_bits w__0)))))))
+ else sail2_state_monad$returnS () )
+ (set_Minterrupts_MTI mip_ref ((bool_to_bits F : 1 words$word))))
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ if ((zopz0zIzJ_u w__1 w__2)) then sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT " clint timer pending at mtime " ((string_of_bits w__3)))))))
+ else sail2_state_monad$returnS () )
+ (set_Minterrupts_MTI mip_ref ((bool_to_bits T : 1 words$word)))
+ else sail2_state_monad$returnS () ))))`;
+
+
+(*val clint_store : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((clint_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+ (let addr = ((sub_vec addr ((plat_clint_base () : 64 words$word)) : 64 words$word)) in
+ if ((((((addr = MSIP_BASE))) /\ ((((((((id width)) = (( 8 : int):ii)))) \/ (((((id width)) = (( 4 : int):ii)))))))))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- "
+ ((STRCAT ((string_of_bits data))
+ ((STRCAT " (mip.MSI <- "
+ ((STRCAT
+ ((string_of_bits
+ ((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word))))
+ ")"))))))))))))
+ else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (set_Minterrupts_MSI mip_ref
+ ((bool_to_bits
+ (((((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word))))
+ : 1 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 8 : int):ii))))))) then
+ let (data : 64 words$word) = ((words$w2w data : 64 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<8>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtimecmp_ref ((zero_extend data (( 64 : int):ii) : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T))
+ else if ((((((addr = MTIMECMP_BASE))) /\ (((((id width)) = (( 4 : int):ii))))))) then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) ((zero_extend data (( 32 : int):ii) : 32 words$word))
+ : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T)))
+ else if ((((((addr = MTIMECMP_BASE_HI))) /\ (((((id width)) = (( 4 : int):ii))))))) then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint<4>["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))
+ else () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__1 (( 63 : int):ii) (( 32 : int):ii) ((zero_extend data (( 32 : int):ii) : 32 words$word))
+ : 64 words$word)))
+ (clint_dispatch () )) (sail2_state_monad$returnS (MemValue T)))
+ else
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "clint["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (<unmapped>)"))))))))
+ else () ) in
+ sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val tick_clock : unit -> M unit*)
+
+val _ = Define `
+ ((tick_clock:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii) : 64 words$word)))
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtime_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))) (clint_dispatch () )))))`;
+
+
+(*val Mk_htif_cmd : mword ty64 -> htif_cmd*)
+
+val _ = Define `
+ ((Mk_htif_cmd:(64)words$word -> htif_cmd) v=
+ (<| htif_cmd_htif_cmd_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*)
+
+val _ = Define `
+ ((get_htif_cmd_bits:htif_cmd ->(64)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_bits:((regstate),(register_value),(htif_cmd))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_bits:htif_cmd ->(64)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_device : htif_cmd -> mword ty8*)
+
+val _ = Define `
+ ((get_htif_cmd_device:htif_cmd ->(8)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_device:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_device:htif_cmd ->(8)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*)
+
+val _ = Define `
+ ((get_htif_cmd_cmd:htif_cmd ->(8)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_cmd:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_cmd:htif_cmd ->(8)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*)
+
+val _ = Define `
+ ((get_htif_cmd_payload:htif_cmd ->(48)words$word) v=
+ ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))`;
+
+
+(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*)
+
+val _ = Define `
+ ((set_htif_cmd_payload:((regstate),(register_value),(htif_cmd))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*)
+
+val _ = Define `
+ ((update_htif_cmd_payload:htif_cmd ->(48)words$word -> htif_cmd) v x=
+ ((v with<|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val htif_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((htif_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "htif["
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits w__0)))))))))))
+ else sail2_state_monad$returnS () )
+ (if ((((((width = (( 8 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 64 words$word)))))))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w ((zero_extend w__1 (( 64 : int):ii) : 64 words$word)) : 'int8_times_n words$word))))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 64 words$word))))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((add_vec_int ((plat_htif_tohost () : 64 words$word)) (( 4 : int):ii) : 64 words$word))))))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$returnS (MemValue ((words$w2w
+ ((zero_extend ((subrange_vec_dec w__3 (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))
+ (( 32 : int):ii)
+ : 32 words$word))
+ : 'int8_times_n words$word))))
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault))))`;
+
+
+(*val htif_store : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((htif_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data=
+ (let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif["
+ ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))
+ else () ) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if (((width = (( 8 : int):ii)))) then
+ let (data : 64 words$word) = ((words$w2w data : 64 words$word)) in
+ sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) data : 64 words$word))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((plat_htif_tohost () : 64 words$word))))))))
+ then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$write_regS htif_tohost_ref ((update_subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) data : 64 words$word)))
+ else if ((((((width = (( 4 : int):ii)))) /\ (((addr = ((add_vec_int ((plat_htif_tohost () : 64 words$word)) (( 4 : int):ii) : 64 words$word))))))))
+ then
+ let (data : 32 words$word) = ((words$w2w data : 32 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$write_regS htif_tohost_ref ((update_subrange_vec_dec w__1 (( 63 : int):ii) (( 32 : int):ii) data : 64 words$word)))
+ else sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) data : 64 words$word)))
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M)) (\ (w__2 : 64 words$word) .
+ let cmd = (Mk_htif_cmd w__2) in
+ let b__0 = ((get_htif_cmd_device cmd : 8 words$word)) in sail2_state_monad$seqS
+ (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif-syscall-proxy cmd: "
+ ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))
+ else () ) in
+ if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 0 : int):ii)))
+ : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$seqS
+ (sail2_state_monad$write_regS htif_done_ref T)
+ (sail2_state_monad$write_regS
+ htif_exit_code_ref
+ ((shiftr ((zero_extend ((get_htif_cmd_payload cmd : 48 words$word)) (( 64 : int):ii) : 64 words$word))
+ (( 1 : int):ii)
+ : 64 words$word)))
+ else sail2_state_monad$returnS ()
+ else
+ sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then
+ let (_ : unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ ((STRCAT "htif-term cmd: "
+ ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))
+ else () ) in
+ let b__2 = ((get_htif_cmd_cmd cmd : 8 words$word)) in
+ if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then ()
+ else if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then
+ plat_term_write
+ ((subrange_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 7 : int):ii) (( 0 : int):ii)
+ : 8 words$word))
+ else print_endline ((STRCAT "Unknown term cmd: " ((string_of_bits b__2))))
+ else print_endline ((STRCAT "htif-???? cmd: " ((string_of_bits data))))))
+ (sail2_state_monad$returnS (MemValue T)))))`;
+
+
+(*val htif_tick : unit -> M unit*)
+
+val _ = Define `
+ ((htif_tick:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS
+ (if ((get_config_print_platform () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((print_dbg ((STRCAT "htif::tick " ((string_of_bits w__0)))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`;
+
+
+(*val within_mmio_readable : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_mmio_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((within_clint addr width)) \/ (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= ((id width)))))))))`;
+
+
+(*val within_mmio_writable : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((within_mmio_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((within_clint addr width)) \/ (((((within_htif_writable addr width)) /\ ((((id width)) <= (( 8 : int):ii))))))))`;
+
+
+(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mmio_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int)=
+ (if ((within_clint addr width)) then (clint_load addr width )
+ else if (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= ((id width))))))) then
+ (htif_load addr width )
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val mmio_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mmio_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) data=
+ (if ((within_clint addr width)) then clint_store addr width data
+ else if (((((within_htif_writable addr width)) /\ ((((id width)) <= (( 8 : int):ii)))))) then
+ htif_store addr width data
+ else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val init_platform : unit -> M unit*)
+
+val _ = Define `
+ ((init_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))
+ (sail2_state_monad$write_regS htif_done_ref F))
+ (sail2_state_monad$write_regS htif_exit_code_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`;
+
+
+(*val tick_platform : unit -> M unit*)
+
+val _ = Define `
+ ((tick_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (htif_tick () ))`;
+
+
+(*val handle_illegal : unit -> M unit*)
+
+val _ = Define `
+ ((handle_illegal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (if ((plat_mtval_has_illegal_inst_bits () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS instbits_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$returnS (SOME w__0))
+ else sail2_state_monad$returnS NONE) (\ info .
+ let (t : sync_exception) =
+ (<| sync_exception_trap := E_Illegal_Instr;
+ sync_exception_excinfo := info;
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_TRAP t) w__2 : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ set_next_pc w__3))))))`;
+
+
+(*val platform_wfi : unit -> M unit*)
+
+val _ = Define `
+ ((platform_wfi:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+ (let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ if ((zopz0zI_u w__0 w__1)) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtime_ref w__2)
+ (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__3 : 64 words$word) .
+ sail2_state_monad$write_regS mcycle_ref w__3))
+ else sail2_state_monad$returnS () ))))`;
+
+
+(*val is_aligned_addr : mword ty64 -> integer -> bool*)
+
+val _ = Define `
+ ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)=
+ (((((lem$w2ui addr)) % width)) = (( 0 : int):ii)))`;
+
+
+(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((phys_mem_read:AccessType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)= (sail2_state_monad$bindS
+ (case (aq, rl, res) of
+ (F, F, F) => sail2_state_monad$bindS
+ (read_ram Read_plain addr width : ( 'int8_times_n words$word) M) (\ (w__0 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__0))
+ | (T, F, F) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__1 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__1))
+ | (T, T, F) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_strong_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__2 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__2))
+ | (F, F, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved addr width : ( 'int8_times_n words$word) M) (\ (w__3 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__3))
+ | (T, F, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__4 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__4))
+ | (T, T, T) => sail2_state_monad$bindS
+ (read_ram Read_RISCV_reserved_strong_acquire addr width : ( 'int8_times_n words$word) M) (\ (w__5 :
+ 'int8_times_n words$word) .
+ sail2_state_monad$returnS (SOME w__5))
+ | (F, T, F) => sail2_state_monad$returnS NONE
+ | (F, T, T) => sail2_state_monad$returnS NONE
+ ) (\ w__6 .
+ let result = w__6 in
+ sail2_state_monad$returnS ((case (t, result) of
+ (Execute, NONE) => MemException E_Fetch_Access_Fault
+ | (Read, NONE) => MemException E_Load_Access_Fault
+ | (_, NONE) => MemException E_SAMO_Access_Fault
+ | (_, SOME (v)) =>
+ let (_ : unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ ((STRCAT "mem["
+ ((STRCAT ((accessType_to_str t))
+ ((STRCAT ","
+ ((STRCAT ((string_of_bits addr))
+ ((STRCAT "] -> " ((string_of_bits v))))))))))))
+ else () ) in
+ MemValue v
+ )))))`;
+
+
+(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((checked_mem_read:AccessType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)=
+ (if ((within_mmio_readable addr width)) then (mmio_read addr width )
+ else if ((within_phys_mem addr width)) then (phys_mem_read t addr width aq rl res )
+ else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`;
+
+
+(*val pmp_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((pmp_mem_read:AccessType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : AccessType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res :
+ bool)=
+ (if ((~ ((plat_enable_pmp () )))) then (checked_mem_read t addr width aq rl res )
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . sail2_state_monad$bindS
+ (effectivePrivilege w__1 w__2) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (pmpCheck addr width t w__3) (\ (w__4 : ExceptionType option) .
+ (case w__4 of
+ NONE => (checked_mem_read t addr width aq rl res )
+ | SOME (e) => sail2_state_monad$returnS (MemException e)
+ )))))))`;
+
+
+(*val rvfi_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> MemoryOpResult (mword 'int8_times_n) -> unit*)
+
+val _ = Define `
+ ((rvfi_read:(64)words$word -> int ->('int8_times_n words$word)MemoryOpResult -> unit) addr width value= () )`;
+
+
+(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mem_read:AccessType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ addr width aq rl res= (sail2_state_monad$bindS
+ (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_Load_Addr_Align)
+ else
+ (case (aq, rl, res) of
+ (F, T, F) => sail2_state_monad$throwS (Error_not_implemented "load.rl")
+ | (F, T, T) => sail2_state_monad$throwS (Error_not_implemented "lr.rl")
+ | (_, _, _) => (pmp_mem_read typ addr width aq rl res )
+ )) (\ result .
+ let (_ : unit) = (rvfi_read addr width result) in
+ sail2_state_monad$returnS result)))`;
+
+
+(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl con=
+ (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (F, F, F) => sail2_state_monad$seqS (write_ram_ea Write_plain addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, T, F) => sail2_state_monad$seqS (write_ram_ea Write_RISCV_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, F, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (F, T, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+ | (T, T, F) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+ | (T, T, T) => sail2_state_monad$seqS
+ (write_ram_ea Write_RISCV_conditional_strong_release addr width) (sail2_state_monad$returnS (MemValue () ))
+ )))`;
+
+
+(*val rvfi_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> unit*)
+
+val _ = Define `
+ ((rvfi_write:(64)words$word -> int -> 'int8_times_n words$word -> unit) addr width value= () )`;
+
+
+(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((phys_mem_write:write_kind ->(64)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (let (_ : unit) = (rvfi_write addr width data) in sail2_state_monad$bindS
+ (write_ram wk addr width data meta) (\ (w__0 : bool) .
+ let result = (MemValue w__0) in
+ let (_ : unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ ((STRCAT "mem["
+ ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))
+ else () ) in
+ sail2_state_monad$returnS result)))`;
+
+
+(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((checked_mem_write:write_kind ->(64)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (if ((within_mmio_writable addr width)) then mmio_write addr width data
+ else if ((within_phys_mem addr width)) then phys_mem_write wk addr width data meta
+ else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`;
+
+
+(*val pmp_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((pmp_mem_write:write_kind ->(64)words$word -> int -> 'int8_times_n words$word -> unit ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (wk : write_kind) (addr : xlenbits) (width : int) data (meta : mem_meta)=
+ (if ((~ ((plat_enable_pmp () )))) then checked_mem_write wk addr width data meta
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . sail2_state_monad$bindS
+ (effectivePrivilege w__1 w__2) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (pmpCheck addr width Write w__3) (\ (w__4 : ExceptionType option) .
+ (case w__4 of
+ NONE => checked_mem_write wk addr width data meta
+ | SOME (e) => sail2_state_monad$returnS (MemException e)
+ )))))))`;
+
+
+(*val mem_write_value_meta : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> unit -> bool -> bool -> bool -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mem_write_value_meta:(64)words$word -> int -> 'int8_times_n words$word -> unit -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value meta aq rl con=
+ (let (_ : unit) = (rvfi_write addr width value) in
+ if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+ sail2_state_monad$returnS (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (F, F, F) => pmp_mem_write Write_plain addr width value meta
+ | (F, T, F) => pmp_mem_write Write_RISCV_release addr width value meta
+ | (F, F, T) => pmp_mem_write Write_RISCV_conditional addr width value meta
+ | (F, T, T) => pmp_mem_write Write_RISCV_conditional_release addr width value meta
+ | (T, T, F) => pmp_mem_write Write_RISCV_strong_release addr width value meta
+ | (T, T, T) =>
+ pmp_mem_write Write_RISCV_conditional_strong_release addr width value meta
+ | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq")
+ | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq")
+ )))`;
+
+
+(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult bool)*)
+
+val _ = Define `
+ ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((bool)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value aq rl con=
+ (mem_write_value_meta addr width value default_meta aq rl con))`;
+
+
+val _ = Define `
+ ((PAGESIZE_BITS:int)= ((( 12 : int):ii)))`;
+
+
+(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((Mk_PTE_Bits:(8)words$word -> PTE_Bits) v=
+ (<| PTE_Bits_PTE_Bits_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) |>))`;
+
+
+(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*)
+
+val _ = Define `
+ ((get_PTE_Bits_bits:PTE_Bits ->(8)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_PTE_Bits_bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits_bits:PTE_Bits ->(8)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) v x=
+ ((v with<|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word))
+ : 8 words$word))|>)))`;
+
+
+(*val isPTEPtr : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isPTEPtr:(8)words$word -> bool) p=
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`;
+
+
+(*val isInvalidPTE : mword ty8 -> bool*)
+
+val _ = Define `
+ ((isInvalidPTE:(8)words$word -> bool) p=
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_V a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`;
+
+
+(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*)
+
+val _ = Define `
+ ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p :
+ PTE_Bits)=
+ ((case (ac, priv) of
+ (Read, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))
+ | (Write, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (ReadWrite, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))))))
+ | (Execute, User) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (Read, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))
+ | (Write, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (ReadWrite, Supervisor) =>
+ sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))))))
+ | (Execute, Supervisor) =>
+ sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))
+ | (_, Machine) => internal_error "m-mode mem perm check"
+ )))`;
+
+
+(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)=
+ (let update_d =
+ (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in
+ let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in
+ if (((update_d \/ update_a))) then
+ let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in
+ let np = (if update_d then update_PTE_Bits_D np ((bool_to_bits T : 1 words$word)) else np) in
+ SOME np
+ else NONE))`;
+
+
+(*val PTW_Error_of_num : integer -> PTW_Error*)
+
+val _ = Define `
+ ((PTW_Error_of_num:int -> PTW_Error) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = (( 0 : int):ii)))) then PTW_Access
+ else if (((p0_ = (( 1 : int):ii)))) then PTW_Invalid_PTE
+ else if (((p0_ = (( 2 : int):ii)))) then PTW_No_Permission
+ else if (((p0_ = (( 3 : int):ii)))) then PTW_Misaligned
+ else PTW_PTE_Update))`;
+
+
+(*val num_of_PTW_Error : PTW_Error -> integer*)
+
+val _ = Define `
+ ((num_of_PTW_Error:PTW_Error -> int) arg_=
+ ((case arg_ of
+ PTW_Access => (( 0 : int):ii)
+ | PTW_Invalid_PTE => (( 1 : int):ii)
+ | PTW_No_Permission => (( 2 : int):ii)
+ | PTW_Misaligned => (( 3 : int):ii)
+ | PTW_PTE_Update => (( 4 : int):ii)
+ )))`;
+
+
+(*val ptw_error_to_str : PTW_Error -> string*)
+
+val _ = Define `
+ ((ptw_error_to_str:PTW_Error -> string) e=
+ ((case e of
+ PTW_Access => "mem-access-error"
+ | PTW_Invalid_PTE => "invalid-pte"
+ | PTW_No_Permission => "no-permission"
+ | PTW_Misaligned => "misaligned-superpage"
+ | PTW_PTE_Update => "pte-update-needed"
+ )))`;
+
+
+(*val translationException : AccessType -> PTW_Error -> ExceptionType*)
+
+val _ = Define `
+ ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)=
+ ((case (a, f) of
+ (ReadWrite, PTW_Access) => E_SAMO_Access_Fault
+ | (ReadWrite, _) => E_SAMO_Page_Fault
+ | (Read, PTW_Access) => E_Load_Access_Fault
+ | (Read, _) => E_Load_Page_Fault
+ | (Write, PTW_Access) => E_SAMO_Access_Fault
+ | (Write, _) => E_SAMO_Page_Fault
+ | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+ | (Fetch, _) => E_Fetch_Page_Fault
+ )))`;
+
+
+(*val curAsid32 : mword ty32 -> mword ty9*)
+
+val _ = Define `
+ ((curAsid32:(32)words$word ->(9)words$word) satp1=
+ (let s = (Mk_Satp32 satp1) in
+ (get_Satp32_Asid s : 9 words$word)))`;
+
+
+(*val curPTB32 : mword ty32 -> mword ty34*)
+
+val _ = Define `
+ ((curPTB32:(32)words$word ->(34)words$word) satp1=
+ (let (s : Satp32) = (Mk_Satp32 satp1) in
+ (shiftl ((EXTZ (( 34 : int):ii) ((get_Satp32_PPN s : 22 words$word)) : 34 words$word)) PAGESIZE_BITS
+ : 34 words$word)))`;
+
+
+val _ = Define `
+ ((SV32_LEVEL_BITS:int)= ((( 10 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV32_LEVELS:int)= ((( 2 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE32_LOG_SIZE:int)= ((( 2 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE32_SIZE:int)= ((( 4 : int):ii)))`;
+
+
+(*val Mk_SV32_Vaddr : mword ty32 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV32_Vaddr:(32)words$word -> SV32_Vaddr) v=
+ (<| SV32_Vaddr_SV32_Vaddr_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_bits:SV32_Vaddr ->(32)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_bits : register_ref regstate register_value SV32_Vaddr -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_bits:((regstate),(register_value),(SV32_Vaddr))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_bits:SV32_Vaddr ->(32)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_VPNi:SV32_Vaddr ->(20)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_VPNi : register_ref regstate register_value SV32_Vaddr -> mword ty20 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_VPNi:((regstate),(register_value),(SV32_Vaddr))register_ref ->(20)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 19 : int):ii) (( 0 : int):ii) : 20 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_VPNi:SV32_Vaddr ->(20)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 31 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 19 : int):ii) (( 0 : int):ii) : 20 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27 -> SV48_Vaddr*)
+
+(*val _get_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27*)
+
+(*val _set_SV48_Vaddr_VPNi : register_ref regstate register_value SV48_Vaddr -> mword ty27 -> M unit*)
+
+(*val _get_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV32_Vaddr_PgOfs:SV32_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV32_Vaddr_PgOfs : register_ref regstate register_value SV32_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Vaddr_PgOfs:((regstate),(register_value),(SV32_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12 -> SV32_Vaddr*)
+
+val _ = Define `
+ ((update_SV32_Vaddr_PgOfs:SV32_Vaddr ->(12)words$word -> SV32_Vaddr) v x=
+ ((v with<|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Vaddr_SV32_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12 -> SV48_Paddr*)
+
+(*val _get_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12*)
+
+(*val _set_SV48_Paddr_PgOfs : register_ref regstate register_value SV48_Paddr -> mword ty12 -> M unit*)
+
+(*val Mk_SV32_Paddr : mword ty34 -> SV32_Paddr*)
+
+val _ = Define `
+ ((Mk_SV32_Paddr:(34)words$word -> SV32_Paddr) v=
+ (<| SV32_Paddr_SV32_Paddr_chunk_0 := ((subrange_vec_dec v (( 33 : int):ii) (( 0 : int):ii) : 34 words$word)) |>))`;
+
+
+(*val _get_SV32_Paddr_bits : SV32_Paddr -> mword ty34*)
+
+val _ = Define `
+ ((get_SV32_Paddr_bits:SV32_Paddr ->(34)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii) : 34 words$word)))`;
+
+
+(*val _set_SV32_Paddr_bits : register_ref regstate register_value SV32_Paddr -> mword ty34 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_bits:((regstate),(register_value),(SV32_Paddr))register_ref ->(34)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 33 : int):ii) (( 0 : int):ii) : 34 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_bits : SV32_Paddr -> mword ty34 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_bits:SV32_Paddr ->(34)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 33 : int):ii) (( 0 : int):ii) : 34 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val _get_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22*)
+
+val _ = Define `
+ ((get_SV32_Paddr_PPNi:SV32_Paddr ->(22)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii) : 22 words$word)))`;
+
+
+(*val _set_SV32_Paddr_PPNi : register_ref regstate register_value SV32_Paddr -> mword ty22 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_PPNi:((regstate),(register_value),(SV32_Paddr))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_PPNi:SV32_Paddr ->(22)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 33 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_PPNi : SV48_PTE -> mword ty44 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_PPNi : SV48_PTE -> mword ty44*)
+
+(*val _set_SV48_PTE_PPNi : register_ref regstate register_value SV48_PTE -> mword ty44 -> M unit*)
+
+(*val _get_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV32_Paddr_PgOfs:SV32_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV32_Paddr_PgOfs : register_ref regstate register_value SV32_Paddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_Paddr_PgOfs:((regstate),(register_value),(SV32_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 34 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12 -> SV32_Paddr*)
+
+val _ = Define `
+ ((update_SV32_Paddr_PgOfs:SV32_Paddr ->(12)words$word -> SV32_Paddr) v x=
+ ((v with<|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_Paddr_SV32_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 34 words$word))|>)))`;
+
+
+(*val Mk_SV32_PTE : mword ty32 -> SV32_PTE*)
+
+val _ = Define `
+ ((Mk_SV32_PTE:(32)words$word -> SV32_PTE) v=
+ (<| SV32_PTE_SV32_PTE_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`;
+
+
+(*val _get_SV32_PTE_bits : SV32_PTE -> mword ty32*)
+
+val _ = Define `
+ ((get_SV32_PTE_bits:SV32_PTE ->(32)words$word) v=
+ ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`;
+
+
+(*val _set_SV32_PTE_bits : register_ref regstate register_value SV32_PTE -> mword ty32 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_bits:((regstate),(register_value),(SV32_PTE))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_bits : SV32_PTE -> mword ty32 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_bits:SV32_PTE ->(32)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_PTE_PPNi : SV32_PTE -> mword ty22*)
+
+val _ = Define `
+ ((get_SV32_PTE_PPNi:SV32_PTE ->(22)words$word) v=
+ ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii) : 22 words$word)))`;
+
+
+(*val _set_SV32_PTE_PPNi : register_ref regstate register_value SV32_PTE -> mword ty22 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_PPNi:((regstate),(register_value),(SV32_PTE))register_ref ->(22)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_PPNi : SV32_PTE -> mword ty22 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_PPNi:SV32_PTE ->(22)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 31 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 21 : int):ii) (( 0 : int):ii) : 22 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _get_SV32_PTE_RSW : SV32_PTE -> mword ty2*)
+
+val _ = Define `
+ ((get_SV32_PTE_RSW:SV32_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_SV32_PTE_RSW : register_ref regstate register_value SV32_PTE -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_RSW:((regstate),(register_value),(SV32_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_RSW : SV32_PTE -> mword ty2 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_RSW:SV32_PTE ->(2)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_RSW : SV48_PTE -> mword ty2 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_RSW : SV48_PTE -> mword ty2*)
+
+(*val _set_SV48_PTE_RSW : register_ref regstate register_value SV48_PTE -> mword ty2 -> M unit*)
+
+(*val _get_SV32_PTE_BITS : SV32_PTE -> mword ty8*)
+
+val _ = Define `
+ ((get_SV32_PTE_BITS:SV32_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_SV32_PTE_BITS : register_ref regstate register_value SV32_PTE -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_SV32_PTE_BITS:((regstate),(register_value),(SV32_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 32 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV32_PTE_BITS : SV32_PTE -> mword ty8 -> SV32_PTE*)
+
+val _ = Define `
+ ((update_SV32_PTE_BITS:SV32_PTE ->(8)words$word -> SV32_PTE) v x=
+ ((v with<|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV32_PTE_SV32_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 32 words$word))|>)))`;
+
+
+(*val _update_SV48_PTE_BITS : SV48_PTE -> mword ty8 -> SV48_PTE*)
+
+(*val _get_SV48_PTE_BITS : SV48_PTE -> mword ty8*)
+
+(*val _set_SV48_PTE_BITS : register_ref regstate register_value SV48_PTE -> mword ty8 -> M unit*)
+
+(*val curAsid64 : mword ty64 -> mword ty16*)
+
+val _ = Define `
+ ((curAsid64:(64)words$word ->(16)words$word) satp1=
+ (let s = (Mk_Satp64 satp1) in
+ (get_Satp64_Asid s : 16 words$word)))`;
+
+
+(*val curPTB64 : mword ty64 -> mword ty56*)
+
+val _ = Define `
+ ((curPTB64:(64)words$word ->(56)words$word) satp1=
+ (let s = (Mk_Satp64 satp1) in
+ (shiftl ((EXTZ (( 56 : int):ii) ((get_Satp64_PPN s : 44 words$word)) : 56 words$word)) PAGESIZE_BITS
+ : 56 words$word)))`;
+
+
+val _ = Define `
+ ((SV39_LEVEL_BITS:int)= ((( 9 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV39_LEVELS:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_LOG_SIZE:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE39_SIZE:int)= ((( 8 : int):ii)))`;
+
+
+(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV39_Vaddr:(39)words$word -> SV39_Vaddr) v=
+ (<| SV39_Vaddr_SV39_Vaddr_chunk_0 := ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) |>))`;
+
+
+(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_bits:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 39 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) v x=
+ ((v with<|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 39 words$word))|>)))`;
+
+
+(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((Mk_SV39_Paddr:(56)words$word -> SV39_Paddr) v=
+ (<| SV39_Paddr_SV39_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) |>))`;
+
+
+(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*)
+
+val _ = Define `
+ ((get_SV39_Paddr_bits:SV39_Paddr ->(56)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)))`;
+
+
+(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_bits:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_bits:SV39_Paddr ->(56)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) v x=
+ ((v with<|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*)
+
+val _ = Define `
+ ((Mk_SV39_PTE:(64)words$word -> SV39_PTE) v=
+ (<| SV39_PTE_SV39_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*)
+
+val _ = Define `
+ ((get_SV39_PTE_bits:SV39_PTE ->(64)words$word) v=
+ ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_bits:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_bits:SV39_PTE ->(64)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*)
+
+val _ = Define `
+ ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) v=
+ ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*)
+
+val _ = Define `
+ ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*)
+
+val _ = Define `
+ ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) v x=
+ ((v with<|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((SV48_LEVEL_BITS:int)= ((( 9 : int):ii)))`;
+
+
+val _ = Define `
+ ((SV48_LEVELS:int)= ((( 4 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE48_LOG_SIZE:int)= ((( 3 : int):ii)))`;
+
+
+val _ = Define `
+ ((PTE48_SIZE:int)= ((( 8 : int):ii)))`;
+
+
+(*val Mk_SV48_Vaddr : mword ty48 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((Mk_SV48_Vaddr:(48)words$word -> SV48_Vaddr) v=
+ (<| SV48_Vaddr_SV48_Vaddr_chunk_0 := ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) |>))`;
+
+
+(*val _get_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48*)
+
+val _ = Define `
+ ((get_SV48_Vaddr_bits:SV48_Vaddr ->(48)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))`;
+
+
+(*val _set_SV48_Vaddr_bits : register_ref regstate register_value SV48_Vaddr -> mword ty48 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Vaddr_bits:((regstate),(register_value),(SV48_Vaddr))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((update_SV48_Vaddr_bits:SV48_Vaddr ->(48)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 47 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii) : 48 words$word))
+ : 48 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_Vaddr_VPNi:SV48_Vaddr ->(27)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_Vaddr_VPNi:((regstate),(register_value),(SV48_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_Vaddr_VPNi:SV48_Vaddr ->(27)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word))
+ : 48 words$word))|>)))`;
+
+
+(*val _get_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12*)
+
+val _ = Define `
+ ((get_SV48_Vaddr_PgOfs:SV48_Vaddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+(*val _set_SV48_Vaddr_PgOfs : register_ref regstate register_value SV48_Vaddr -> mword ty12 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Vaddr_PgOfs:((regstate),(register_value),(SV48_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 48 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12 -> SV48_Vaddr*)
+
+val _ = Define `
+ ((update_SV48_Vaddr_PgOfs:SV48_Vaddr ->(12)words$word -> SV48_Vaddr) v x=
+ ((v with<|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Vaddr_SV48_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 48 words$word))|>)))`;
+
+
+(*val Mk_SV48_Paddr : mword ty56 -> SV48_Paddr*)
+
+val _ = Define `
+ ((Mk_SV48_Paddr:(56)words$word -> SV48_Paddr) v=
+ (<| SV48_Paddr_SV48_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) |>))`;
+
+
+(*val _get_SV48_Paddr_bits : SV48_Paddr -> mword ty56*)
+
+val _ = Define `
+ ((get_SV48_Paddr_bits:SV48_Paddr ->(56)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)))`;
+
+
+(*val _set_SV48_Paddr_bits : register_ref regstate register_value SV48_Paddr -> mword ty56 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Paddr_bits:((regstate),(register_value),(SV48_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Paddr_bits : SV48_Paddr -> mword ty56 -> SV48_Paddr*)
+
+val _ = Define `
+ ((update_SV48_Paddr_bits:SV48_Paddr ->(56)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii) : 56 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val _get_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44*)
+
+val _ = Define `
+ ((get_SV48_Paddr_PPNi:SV48_Paddr ->(44)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`;
+
+
+(*val _set_SV48_Paddr_PPNi : register_ref regstate register_value SV48_Paddr -> mword ty44 -> M unit*)
+
+val _ = Define `
+ ((set_SV48_Paddr_PPNi:((regstate),(register_value),(SV48_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+(*val _update_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44 -> SV48_Paddr*)
+
+val _ = Define `
+ ((update_SV48_Paddr_PPNi:SV48_Paddr ->(44)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 56 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_Paddr_PgOfs:SV48_Paddr ->(12)words$word) v=
+ ((subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_Paddr_PgOfs:((regstate),(register_value),(SV48_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_Paddr_PgOfs:SV48_Paddr ->(12)words$word -> SV48_Paddr) v x=
+ ((v with<|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_Paddr_SV48_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word))
+ : 56 words$word))|>)))`;
+
+
+(*val Mk_SV48_PTE : mword ty64 -> SV48_PTE*)
+
+val _ = Define `
+ ((Mk_SV48_PTE:(64)words$word -> SV48_PTE) v=
+ (<| SV48_PTE_SV48_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_bits:SV48_PTE ->(64)words$word) v=
+ ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_bits:((regstate),(register_value),(SV48_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_bits:SV48_PTE ->(64)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_PPNi:SV48_PTE ->(44)words$word) v=
+ ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_PPNi:((regstate),(register_value),(SV48_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_PPNi:SV48_PTE ->(44)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii)
+ ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_RSW:SV48_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_RSW:((regstate),(register_value),(SV48_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_RSW:SV48_PTE ->(2)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii)
+ ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word))
+ : 64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((get_SV48_PTE_BITS:SV48_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV48_PTE_BITS:((regstate),(register_value),(SV48_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS r_ref) (\ r .
+ let r =
+ ((r with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec r.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)) in
+ sail2_state_monad$write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((update_SV48_PTE_BITS:SV48_PTE ->(8)words$word -> SV48_PTE) v x=
+ ((v with<|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec v.SV48_PTE_SV48_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii)
+ ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))
+ : 64 words$word))|>)))`;
+
+
+(*val make_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'palen, Size 'ptelen, Size 'valen => mword 'asidlen -> bool -> mword 'valen -> mword 'palen -> mword 'ptelen -> ii -> mword 'palen -> ii -> M (TLB_Entry 'asidlen 'valen 'palen 'ptelen)*)
+
+val _ = Define `
+ ((make_TLB_Entry:'asidlen words$word -> bool -> 'valen words$word -> 'palen words$word -> 'ptelen words$word -> int -> 'palen words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('asidlen,'valen,'palen,'ptelen)TLB_Entry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr levelBitSize=
+ (let (shift : ii) = (PAGESIZE_BITS + ((level * levelBitSize))) in
+ let vAddrMask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec vAddr
+ ((xor_vec vAddr
+ ((EXTZ ((int_of_num (words$word_len vAddr))) (vec_of_bits [B1] : 1 words$word) : 'valen words$word))
+ : 'valen words$word))
+ : 'valen words$word)) shift
+ : 'valen words$word)) (( 1 : int):ii)
+ : 'valen words$word)) in
+ let vMatchMask = ((not_vec vAddrMask : 'valen words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS (<| TLB_Entry_asid := asid;
+ TLB_Entry_global := global;
+ TLB_Entry_pte := pte;
+ TLB_Entry_pteAddr := pteAddr;
+ TLB_Entry_vAddrMask := vAddrMask;
+ TLB_Entry_vMatchMask := vMatchMask;
+ TLB_Entry_vAddr := ((and_vec vAddr vMatchMask : 'valen words$word));
+ TLB_Entry_pAddr :=
+ ((shiftl ((shiftr pAddr shift : 'palen words$word)) shift : 'palen words$word));
+ TLB_Entry_age := w__0 |>))))`;
+
+
+(*val match_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> mword 'asidlen -> mword 'valen -> bool*)
+
+val _ = Define `
+ ((match_TLB_Entry:('asidlen,'valen,'palen,'ptelen)TLB_Entry -> 'asidlen words$word -> 'valen words$word -> bool) ent asid vaddr=
+ ((((ent.TLB_Entry_global \/ (((ent.TLB_Entry_asid = asid)))))) /\ (((ent.TLB_Entry_vAddr = ((and_vec ent.TLB_Entry_vMatchMask vaddr : 'valen words$word)))))))`;
+
+
+(*val flush_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> maybe (mword 'asidlen) -> maybe (mword 'valen) -> bool*)
+
+val _ = Define `
+ ((flush_TLB_Entry:('asidlen,'valen,'palen,'ptelen)TLB_Entry ->('asidlen words$word)option ->('valen words$word)option -> bool) e asid addr=
+ ((case (asid, addr) of
+ (NONE, NONE) => T
+ | (NONE, SOME (a)) =>
+ (e.TLB_Entry_vAddr = ((and_vec e.TLB_Entry_vMatchMask a : 'valen words$word)))
+ | (SOME (i), NONE) => ((((e.TLB_Entry_asid = i))) /\ ((~ e.TLB_Entry_global)))
+ | (SOME (i), SOME (a)) =>
+ ((((e.TLB_Entry_asid = i))) /\ ((((((e.TLB_Entry_vAddr = ((and_vec a e.TLB_Entry_vMatchMask : 'valen words$word))))) /\ ((~ e.TLB_Entry_global))))))
+ )))`;
+
+
+(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M (PTW_Result (mword ty56) SV39_PTE)*)
+
+ val walk39_defn = Hol_defn "walk39" `
+ ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->((((((56)words$word),(SV39_PTE))PTW_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global=
+ (let va = (Mk_SV39_Vaddr vaddr) in
+ let (pt_ofs : paddr64) =
+ ((shiftl
+ ((EXTZ (( 56 : int):ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV39_Vaddr_VPNi va : 27 words$word))
+ ((level * SV39_LEVEL_BITS))
+ : 27 words$word)) ((SV39_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii)
+ : 9 words$word))
+ : 56 words$word)) PTE39_LOG_SIZE
+ : 56 words$word)) in
+ let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in sail2_state_monad$bindS
+ (mem_read ac ((EXTZ (( 64 : int):ii) pte_addr : 64 words$word)) (( 8 : int):ii) F F F
+ : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => sail2_state_monad$returnS (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ let pte = (Mk_SV39_PTE v) in
+ let pbits = ((get_SV39_PTE_BITS pte : 8 words$word)) in
+ let pattr = (Mk_PTE_Bits pbits) in
+ let is_global =
+ (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in
+ if ((isInvalidPTE pbits)) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 : int):ii)))) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk39 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 56 : int):ii) ((get_SV39_PTE_PPNi pte : 44 words$word)) : 56 words$word))
+ PAGESIZE_BITS
+ : 56 words$word)) ((level - (( 1 : int):ii))) is_global
+ : ( (( 56 words$word), SV39_PTE)PTW_Result) M)
+ else sail2_state_monad$bindS
+ (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) .
+ sail2_state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 : int):ii))) then
+ let mask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV39_PTE_PPNi pte : 44 words$word))
+ ((xor_vec ((get_SV39_PTE_PPNi pte : 44 words$word))
+ ((EXTZ (( 44 : int):ii) (vec_of_bits [B1] : 1 words$word) : 44 words$word))
+ : 44 words$word))
+ : 44 words$word)) ((level * SV39_LEVEL_BITS))
+ : 44 words$word)) (( 1 : int):ii)
+ : 44 words$word)) in
+ if (((((and_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) mask : 44 words$word)) <> ((EXTZ (( 44 : int):ii) (vec_of_bits [B0] : 1 words$word) : 44 words$word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ let ppn =
+ ((or_vec ((get_SV39_PTE_PPNi pte : 44 words$word))
+ ((and_vec
+ ((EXTZ (( 44 : int):ii) ((get_SV39_Vaddr_VPNi va : 27 words$word)) : 44 words$word))
+ mask
+ : 44 words$word))
+ : 44 words$word)) in
+ PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va : 12 words$word))
+ : 56 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)
+ else
+ PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte : 44 words$word))
+ ((get_SV39_Vaddr_PgOfs va : 12 words$word))
+ : 56 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ ))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn;
+
+(*val lookup_TLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB_Entry ty16 ty39 ty56 ty64)))*)
+
+val _ = Define `
+ ((lookup_TLB39:(16)words$word ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->((((int#((16),(39),(56),(64))TLB_Entry)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vaddr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 : ( (16, 39, 56, 64)TLB_Entry)option) .
+ sail2_state_monad$returnS ((case w__0 of
+ NONE => NONE
+ | SOME (e) => if ((match_TLB_Entry e asid vaddr)) then SOME ((( 0 : int):ii), e) else NONE
+ )))))`;
+
+
+(*val add_to_TLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((add_to_TLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (sail2_state_monad$bindS
+ (make_TLB_Entry asid global vAddr pAddr ((get_SV39_PTE_bits pte : 64 words$word)) level pteAddr
+ SV39_LEVEL_BITS) (\ (ent : TLB39_Entry) .
+ sail2_state_monad$write_regS tlb39_ref (SOME ent))))`;
+
+
+(*val write_TLB39 : ii -> TLB_Entry ty16 ty39 ty56 ty64 -> M unit*)
+
+val _ = Define `
+ ((write_TLB39:int ->((16),(39),(56),(64))TLB_Entry ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)= (sail2_state_monad$write_regS tlb39_ref (SOME ent)))`;
+
+
+(*val flush_TLB39 : maybe (mword ty16) -> maybe (mword ty39) -> M unit*)
+
+val _ = Define `
+ ((flush_TLB39:((16)words$word)option ->((39)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid addr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 : ( (16, 39, 56, 64)TLB_Entry)option) .
+ (case w__0 of
+ NONE => sail2_state_monad$returnS ()
+ | SOME (e) => if ((flush_TLB_Entry e asid addr)) then sail2_state_monad$write_regS tlb39_ref NONE else sail2_state_monad$returnS ()
+ ))))`;
+
+
+(*val translate39 : mword ty16 -> mword ty56 -> mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty56) PTW_Error)*)
+
+val _ = Define `
+ ((translate39:(16)words$word ->(56)words$word ->(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->((((((56)words$word),(PTW_Error))TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid ptb vAddr ac priv mxr do_sum level= (sail2_state_monad$bindS
+ (lookup_TLB39 asid vAddr) (\ (w__0 : ((ii # (16, 39, 56, 64) TLB_Entry))option) .
+ (case w__0 of
+ SOME ((idx, ent)) =>
+ let pte = (Mk_SV39_PTE ent.TLB_Entry_pte) in
+ let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word))) in sail2_state_monad$bindS
+ (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) .
+ if ((~ w__1)) then sail2_state_monad$returnS (TR_Failure PTW_No_Permission)
+ else
+ (case ((update_PTE_Bits pteBits ac)) of
+ NONE =>
+ sail2_state_monad$returnS (TR_Address ((or_vec ent.TLB_Entry_pAddr
+ ((EXTZ (( 56 : int):ii)
+ ((and_vec vAddr ent.TLB_Entry_vAddrMask : 39 words$word))
+ : 56 words$word))
+ : 56 words$word)))
+ | SOME (pbits) =>
+ if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR_Failure PTW_PTE_Update)
+ else
+ let n_pte = (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in
+ let (n_ent : TLB39_Entry) = ent in
+ let n_ent = ((n_ent with<| TLB_Entry_pte := ((get_SV39_PTE_bits n_pte : 64 words$word))|>)) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (write_TLB39 idx n_ent)
+ (mem_write_value ((EXTZ (( 64 : int):ii) ent.TLB_Entry_pteAddr : 64 words$word)) (( 8 : int):ii)
+ ((get_SV39_PTE_bits n_pte : 64 words$word)) F F F)) (\ (w__2 : bool
+ MemoryOpResult) . sail2_state_monad$seqS
+ (case w__2 of
+ MemValue (_) => sail2_state_monad$returnS ()
+ | MemException (e) => internal_error "invalid physical address in TLB"
+ )
+ (sail2_state_monad$returnS (TR_Address ((or_vec ent.TLB_Entry_pAddr
+ ((EXTZ (( 56 : int):ii)
+ ((and_vec vAddr ent.TLB_Entry_vAddrMask : 39 words$word))
+ : 56 words$word))
+ : 56 words$word)))))
+ ))
+ | NONE => sail2_state_monad$bindS
+ (walk39 vAddr ac priv mxr do_sum ptb level F : ( (( 56 words$word), SV39_PTE)PTW_Result) M) (\ (w__6 : (( 56 words$word), SV39_PTE)
+ PTW_Result) .
+ (case w__6 of
+ PTW_Failure (f) => sail2_state_monad$returnS (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word)))) ac)) of
+ NONE => sail2_state_monad$seqS
+ (add_to_TLB39 asid vAddr pAddr pte pteAddr level global) (sail2_state_monad$returnS (TR_Address pAddr))
+ | SOME (pbits) =>
+ if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR_Failure PTW_PTE_Update)
+ else
+ let (w_pte : SV39_PTE) =
+ (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in sail2_state_monad$bindS
+ (mem_write_value ((EXTZ (( 64 : int):ii) pteAddr : 64 words$word)) (( 8 : int):ii)
+ ((get_SV39_PTE_bits w_pte : 64 words$word)) F F F) (\ (w__7 : bool
+ MemoryOpResult) .
+ (case w__7 of
+ MemValue (_) => sail2_state_monad$seqS
+ (add_to_TLB39 asid vAddr pAddr w_pte pteAddr level global)
+ (sail2_state_monad$returnS (TR_Address pAddr))
+ | MemException (e) => sail2_state_monad$returnS (TR_Failure PTW_Access)
+ ))
+ )
+ ))
+ ))))`;
+
+
+(*val init_vmem_sv39 : unit -> M unit*)
+
+val _ = Define `
+ ((init_vmem_sv39:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS tlb39_ref NONE))`;
+
+
+(*val walk48 : mword ty48 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M (PTW_Result (mword ty56) SV48_PTE)*)
+
+ val walk48_defn = Hol_defn "walk48" `
+ ((walk48:(48)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->((((((56)words$word),(SV48_PTE))PTW_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global=
+ (let va = (Mk_SV48_Vaddr vaddr) in
+ let (pt_ofs : paddr64) =
+ ((shiftl
+ ((EXTZ (( 56 : int):ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV48_Vaddr_VPNi va : 27 words$word))
+ ((level * SV48_LEVEL_BITS))
+ : 27 words$word)) ((SV48_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii)
+ : 9 words$word))
+ : 56 words$word)) PTE48_LOG_SIZE
+ : 56 words$word)) in
+ let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in sail2_state_monad$bindS
+ (mem_read ac ((EXTZ (( 64 : int):ii) pte_addr : 64 words$word)) (( 8 : int):ii) F F F
+ : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => sail2_state_monad$returnS (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ let pte = (Mk_SV48_PTE v) in
+ let pbits = ((get_SV48_PTE_BITS pte : 8 words$word)) in
+ let pattr = (Mk_PTE_Bits pbits) in
+ let is_global =
+ (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in
+ if ((isInvalidPTE pbits)) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 : int):ii)))) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk48 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 56 : int):ii) ((get_SV48_PTE_PPNi pte : 44 words$word)) : 56 words$word))
+ PAGESIZE_BITS
+ : 56 words$word)) ((level - (( 1 : int):ii))) is_global
+ : ( (( 56 words$word), SV48_PTE)PTW_Result) M)
+ else sail2_state_monad$bindS
+ (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) .
+ sail2_state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 : int):ii))) then
+ let mask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV48_PTE_PPNi pte : 44 words$word))
+ ((xor_vec ((get_SV48_PTE_PPNi pte : 44 words$word))
+ ((EXTZ (( 44 : int):ii) (vec_of_bits [B1] : 1 words$word) : 44 words$word))
+ : 44 words$word))
+ : 44 words$word)) ((level * SV48_LEVEL_BITS))
+ : 44 words$word)) (( 1 : int):ii)
+ : 44 words$word)) in
+ if (((((and_vec ((get_SV48_PTE_PPNi pte : 44 words$word)) mask : 44 words$word)) <> ((EXTZ (( 44 : int):ii) (vec_of_bits [B0] : 1 words$word) : 44 words$word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ let ppn =
+ ((or_vec ((get_SV48_PTE_PPNi pte : 44 words$word))
+ ((and_vec
+ ((EXTZ (( 44 : int):ii) ((get_SV48_Vaddr_VPNi va : 27 words$word)) : 44 words$word))
+ mask
+ : 44 words$word))
+ : 44 words$word)) in
+ PTW_Success ((concat_vec ppn ((get_SV48_Vaddr_PgOfs va : 12 words$word))
+ : 56 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)
+ else
+ PTW_Success ((concat_vec ((get_SV48_PTE_PPNi pte : 44 words$word))
+ ((get_SV48_Vaddr_PgOfs va : 12 words$word))
+ : 56 words$word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ ))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk48_defn;
+
+(*val lookup_TLB48 : mword ty16 -> mword ty48 -> M (maybe ((ii * TLB_Entry ty16 ty48 ty56 ty64)))*)
+
+val _ = Define `
+ ((lookup_TLB48:(16)words$word ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->((((int#((16),(48),(56),(64))TLB_Entry)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vaddr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb48_ref) (\ (w__0 : ( (16, 48, 56, 64)TLB_Entry)option) .
+ sail2_state_monad$returnS ((case w__0 of
+ NONE => NONE
+ | SOME (e) => if ((match_TLB_Entry e asid vaddr)) then SOME ((( 0 : int):ii), e) else NONE
+ )))))`;
+
+
+(*val add_to_TLB48 : mword ty16 -> mword ty48 -> mword ty56 -> SV48_PTE -> mword ty56 -> ii -> bool -> M unit*)
+
+val _ = Define `
+ ((add_to_TLB48:(16)words$word ->(48)words$word ->(56)words$word -> SV48_PTE ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (sail2_state_monad$bindS
+ (make_TLB_Entry asid global vAddr pAddr ((get_SV48_PTE_bits pte : 64 words$word)) level pteAddr
+ SV48_LEVEL_BITS) (\ (ent : TLB48_Entry) .
+ sail2_state_monad$write_regS tlb48_ref (SOME ent))))`;
+
+
+(*val write_TLB48 : ii -> TLB_Entry ty16 ty48 ty56 ty64 -> M unit*)
+
+val _ = Define `
+ ((write_TLB48:int ->((16),(48),(56),(64))TLB_Entry ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (idx : ii) (ent : TLB48_Entry)= (sail2_state_monad$write_regS tlb48_ref (SOME ent)))`;
+
+
+(*val flush_TLB48 : maybe (mword ty16) -> maybe (mword ty48) -> M unit*)
+
+val _ = Define `
+ ((flush_TLB48:((16)words$word)option ->((48)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid addr= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tlb48_ref) (\ (w__0 : ( (16, 48, 56, 64)TLB_Entry)option) .
+ (case w__0 of
+ NONE => sail2_state_monad$returnS ()
+ | SOME (e) => if ((flush_TLB_Entry e asid addr)) then sail2_state_monad$write_regS tlb48_ref NONE else sail2_state_monad$returnS ()
+ ))))`;
+
+
+(*val translate48 : mword ty16 -> mword ty56 -> mword ty48 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty56) PTW_Error)*)
+
+val _ = Define `
+ ((translate48:(16)words$word ->(56)words$word ->(48)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->((((((56)words$word),(PTW_Error))TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid ptb vAddr ac priv mxr do_sum level= (sail2_state_monad$bindS
+ (walk48 vAddr ac priv mxr do_sum ptb level F : ( (( 56 words$word), SV48_PTE)PTW_Result) M) (\ (w__0 : (( 56 words$word), SV48_PTE)
+ PTW_Result) .
+ (case w__0 of
+ PTW_Failure (f) => sail2_state_monad$returnS (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV48_PTE_BITS pte : 8 words$word)))) ac)) of
+ NONE => sail2_state_monad$seqS
+ (add_to_TLB48 asid vAddr pAddr pte pteAddr level global) (sail2_state_monad$returnS (TR_Address pAddr))
+ | SOME (pbits) =>
+ if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR_Failure PTW_PTE_Update)
+ else
+ let (w_pte : SV48_PTE) =
+ (update_SV48_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in sail2_state_monad$bindS
+ (mem_write_value ((EXTZ (( 64 : int):ii) pteAddr : 64 words$word)) (( 8 : int):ii)
+ ((get_SV48_PTE_bits w_pte : 64 words$word)) F F F) (\ (w__1 : bool
+ MemoryOpResult) .
+ (case w__1 of
+ MemValue (_) => sail2_state_monad$seqS
+ (add_to_TLB48 asid vAddr pAddr w_pte pteAddr level global) (sail2_state_monad$returnS (TR_Address pAddr))
+ | MemException (e) => sail2_state_monad$returnS (TR_Failure PTW_Access)
+ ))
+ )
+ ))))`;
+
+
+(*val init_vmem_sv48 : unit -> M unit*)
+
+val _ = Define `
+ ((init_vmem_sv48:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS tlb48_ref NONE))`;
+
+
+(*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*)
+
+val _ = Define `
+ ((legalize_satp:Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : Architecture) (o1 : xlenbits) (v : xlenbits)=
+ ((legalize_satp64 a o1 v : 64 words$word)))`;
+
+
+(*val translationMode : Privilege -> M SATPMode*)
+
+val _ = Define `
+ ((translationMode:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((SATPMode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv=
+ (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ then
+ sail2_state_monad$returnS Sbare
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) .
+ let arch = (architecture ((get_mstatus_SXL w__0 : 2 words$word))) in
+ (case arch of
+ SOME (RV64) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let (mbits : satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1)) : 4 words$word)) in
+ (case ((satp64Mode_of_bits RV64 mbits)) of
+ SOME (m) => sail2_state_monad$returnS m
+ | NONE => internal_error "invalid RV64 translation mode in satp"
+ ))
+ | SOME (RV32) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) .
+ let s = (Mk_Satp32 ((subrange_vec_dec w__4 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in
+ sail2_state_monad$returnS (if (((((get_Satp32_Mode s : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))
+ then
+ Sbare
+ else Sv32))
+ | _ => internal_error "unsupported address translation arch"
+ ))))`;
+
+
+(*val translateAddr : mword ty64 -> AccessType -> M (TR_Result (mword ty64) ExceptionType)*)
+
+val _ = Define `
+ ((translateAddr:(64)words$word -> AccessType ->(regstate)sail2_state_monad$sequential_state ->((((((64)words$word),(ExceptionType))TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac= (sail2_state_monad$bindS
+ (case ac of
+ Execute => sail2_state_monad$read_regS cur_privilege_ref
+ | _ => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . effectivePrivilege w__1 w__2))
+ ) (\ (effPriv : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ let (mxr : bool) =
+ (((get_Mstatus_MXR w__4 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) .
+ let (do_sum : bool) =
+ (((get_Mstatus_SUM w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS
+ (translationMode effPriv) (\ (mode : SATPMode) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) .
+ let asid = ((curAsid64 w__6 : 16 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__7 : 64 words$word) .
+ let ptb = ((curPTB64 w__7 : 56 words$word)) in
+ (case mode of
+ Sbare => sail2_state_monad$returnS (TR_Address vAddr)
+ | Sv39 => sail2_state_monad$bindS
+ (translate39 asid ptb ((subrange_vec_dec vAddr (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) ac effPriv mxr
+ do_sum ((SV39_LEVELS - (( 1 : int):ii)))
+ : ( (( 56 words$word), PTW_Error)TR_Result) M) (\ (w__8 : (( 56 words$word), PTW_Error) TR_Result) .
+ sail2_state_monad$returnS ((case w__8 of
+ TR_Address (pa) => TR_Address ((EXTZ (( 64 : int):ii) pa : 64 words$word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | Sv48 => sail2_state_monad$bindS
+ (translate48 asid ptb ((subrange_vec_dec vAddr (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) ac effPriv mxr
+ do_sum ((SV48_LEVELS - (( 1 : int):ii)))
+ : ( (( 56 words$word), PTW_Error)TR_Result) M) (\ (w__9 : (( 56 words$word), PTW_Error) TR_Result) .
+ sail2_state_monad$returnS ((case w__9 of
+ TR_Address (pa) => TR_Address ((EXTZ (( 64 : int):ii) pa : 64 words$word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | _ =>
+ (internal_error "unsupported address translation scheme"
+ : ( (( 64 words$word), ExceptionType)TR_Result) M)
+ )))))))))`;
+
+
+(*val flush_TLB : maybe (mword ty64) -> maybe (mword ty64) -> M unit*)
+
+val _ = Define `
+ ((flush_TLB:((64)words$word)option ->((64)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid_xlen addr_xlen=
+ (let ((addr39 : vaddr39 option), (addr48 : vaddr48 option)) =
+ ((case addr_xlen of
+ NONE => (NONE, NONE)
+ | SOME (a) =>
+ (SOME ((subrange_vec_dec a (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)),
+ SOME ((subrange_vec_dec a (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))
+ )) in
+ let (asid : asid64 option) =
+ ((case asid_xlen of
+ NONE => NONE
+ | SOME (a) => SOME ((subrange_vec_dec a (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))
+ )) in sail2_state_monad$seqS
+ (flush_TLB39 asid addr39) (flush_TLB48 asid addr48)))`;
+
+
+(*val init_vmem : unit -> M unit*)
+
+val _ = Define `
+ ((init_vmem:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (init_vmem_sv39 () ) (init_vmem_sv48 () )))`;
+
+
+(*val execute : ast -> M Retired*)
+
+(*val encdec_uop_forwards : uop -> mword ty7*)
+
+val _ = Define `
+ ((encdec_uop_forwards:uop ->(7)words$word) arg_=
+ ((case arg_ of
+ RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)
+ | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)
+ )))`;
+
+
+(*val encdec_uop_backwards : mword ty7 -> M uop*)
+
+val _ = Define `
+ ((encdec_uop_backwards:(7)words$word ->(regstate)sail2_state_monad$sequential_state ->(((uop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then sail2_state_monad$returnS RISCV_LUI
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then sail2_state_monad$returnS RISCV_AUIPC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_uop_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((encdec_uop_forwards_matches:uop -> bool) arg_=
+ ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val encdec_uop_backwards_matches : mword ty7 -> bool*)
+
+val _ = Define `
+ ((encdec_uop_backwards_matches:(7)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then T
+ else F))`;
+
+
+(*val utype_mnemonic_forwards : uop -> string*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards:uop -> string) arg_= ((case arg_ of RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" )))`;
+
+
+(*val utype_mnemonic_backwards : string -> M uop*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((uop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "lui"))) then sail2_state_monad$returnS RISCV_LUI
+ else if (((p0_ = "auipc"))) then sail2_state_monad$returnS RISCV_AUIPC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val utype_mnemonic_forwards_matches : uop -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_forwards_matches:uop -> bool) arg_=
+ ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`;
+
+
+(*val utype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((utype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "lui"))) then T
+ else if (((p0_ = "auipc"))) then T
+ else F))`;
+
+
+(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*)
+
+(*val _s496_ : string -> maybe string*)
+
+val _ = Define `
+ ((s496_:string ->(string)option) s497_0=
+ (let s498_0 = s497_0 in
+ if ((string_startswith s498_0 "auipc")) then
+ (case ((string_drop s498_0 ((string_length "auipc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s492_ : string -> maybe string*)
+
+val _ = Define `
+ ((s492_:string ->(string)option) s493_0=
+ (let s494_0 = s493_0 in
+ if ((string_startswith s494_0 "lui")) then
+ (case ((string_drop s494_0 ((string_length "lui")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((utype_mnemonic_matches_prefix:string ->(uop#int)option) arg_=
+ (let s495_0 = arg_ in
+ if ((case ((s492_ s495_0)) of SOME (s_) => T | _ => F )) then
+ (case s492_ s495_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_LUI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s496_ s495_0)) of SOME (s_) => T | _ => F )) then
+ (case s496_ s495_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_AUIPC, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_bop_forwards : bop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_bop_forwards:bop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_BEQ => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | RISCV_BNE => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | RISCV_BLT => (vec_of_bits [B1;B0;B0] : 3 words$word)
+ | RISCV_BGE => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : 3 words$word)
+ | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_bop_backwards : mword ty3 -> M bop*)
+
+val _ = Define `
+ ((encdec_bop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BEQ
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BNE
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BLT
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BGE
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BLTU
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_BGEU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_bop_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((encdec_bop_forwards_matches:bop -> bool) arg_=
+ ((case arg_ of
+ RISCV_BEQ => T
+ | RISCV_BNE => T
+ | RISCV_BLT => T
+ | RISCV_BGE => T
+ | RISCV_BLTU => T
+ | RISCV_BGEU => T
+ )))`;
+
+
+(*val encdec_bop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_bop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val btype_mnemonic_forwards : bop -> string*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards:bop -> string) arg_=
+ ((case arg_ of
+ RISCV_BEQ => "beq"
+ | RISCV_BNE => "bne"
+ | RISCV_BLT => "blt"
+ | RISCV_BGE => "bge"
+ | RISCV_BLTU => "bltu"
+ | RISCV_BGEU => "bgeu"
+ )))`;
+
+
+(*val btype_mnemonic_backwards : string -> M bop*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "beq"))) then sail2_state_monad$returnS RISCV_BEQ
+ else if (((p0_ = "bne"))) then sail2_state_monad$returnS RISCV_BNE
+ else if (((p0_ = "blt"))) then sail2_state_monad$returnS RISCV_BLT
+ else if (((p0_ = "bge"))) then sail2_state_monad$returnS RISCV_BGE
+ else if (((p0_ = "bltu"))) then sail2_state_monad$returnS RISCV_BLTU
+ else if (((p0_ = "bgeu"))) then sail2_state_monad$returnS RISCV_BGEU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val btype_mnemonic_forwards_matches : bop -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_forwards_matches:bop -> bool) arg_=
+ ((case arg_ of
+ RISCV_BEQ => T
+ | RISCV_BNE => T
+ | RISCV_BLT => T
+ | RISCV_BGE => T
+ | RISCV_BLTU => T
+ | RISCV_BGEU => T
+ )))`;
+
+
+(*val btype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((btype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "beq"))) then T
+ else if (((p0_ = "bne"))) then T
+ else if (((p0_ = "blt"))) then T
+ else if (((p0_ = "bge"))) then T
+ else if (((p0_ = "bltu"))) then T
+ else if (((p0_ = "bgeu"))) then T
+ else F))`;
+
+
+(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*)
+
+(*val _s520_ : string -> maybe string*)
+
+val _ = Define `
+ ((s520_:string ->(string)option) s521_0=
+ (let s522_0 = s521_0 in
+ if ((string_startswith s522_0 "bgeu")) then
+ (case ((string_drop s522_0 ((string_length "bgeu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s516_ : string -> maybe string*)
+
+val _ = Define `
+ ((s516_:string ->(string)option) s517_0=
+ (let s518_0 = s517_0 in
+ if ((string_startswith s518_0 "bltu")) then
+ (case ((string_drop s518_0 ((string_length "bltu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s512_ : string -> maybe string*)
+
+val _ = Define `
+ ((s512_:string ->(string)option) s513_0=
+ (let s514_0 = s513_0 in
+ if ((string_startswith s514_0 "bge")) then
+ (case ((string_drop s514_0 ((string_length "bge")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s508_ : string -> maybe string*)
+
+val _ = Define `
+ ((s508_:string ->(string)option) s509_0=
+ (let s510_0 = s509_0 in
+ if ((string_startswith s510_0 "blt")) then
+ (case ((string_drop s510_0 ((string_length "blt")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s504_ : string -> maybe string*)
+
+val _ = Define `
+ ((s504_:string ->(string)option) s505_0=
+ (let s506_0 = s505_0 in
+ if ((string_startswith s506_0 "bne")) then
+ (case ((string_drop s506_0 ((string_length "bne")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s500_ : string -> maybe string*)
+
+val _ = Define `
+ ((s500_:string ->(string)option) s501_0=
+ (let s502_0 = s501_0 in
+ if ((string_startswith s502_0 "beq")) then
+ (case ((string_drop s502_0 ((string_length "beq")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((btype_mnemonic_matches_prefix:string ->(bop#int)option) arg_=
+ (let s503_0 = arg_ in
+ if ((case ((s500_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s500_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BEQ, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s504_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s504_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BNE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s508_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s508_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BLT, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s512_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s512_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BGE, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s516_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s516_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BLTU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s520_ s503_0)) of SOME (s_) => T | _ => F )) then
+ (case s520_ s503_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_BGEU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_iop_forwards : iop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_iop_forwards:iop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_ADDI => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : 3 words$word)
+ | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : 3 words$word)
+ | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : 3 words$word)
+ | RISCV_ORI => (vec_of_bits [B1;B1;B0] : 3 words$word)
+ | RISCV_XORI => (vec_of_bits [B1;B0;B0] : 3 words$word)
+ )))`;
+
+
+(*val encdec_iop_backwards : mword ty3 -> M iop*)
+
+val _ = Define `
+ ((encdec_iop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((iop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ADDI
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLTI
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLTIU
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ANDI
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_ORI
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS RISCV_XORI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_iop_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((encdec_iop_forwards_matches:iop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDI => T
+ | RISCV_SLTI => T
+ | RISCV_SLTIU => T
+ | RISCV_ANDI => T
+ | RISCV_ORI => T
+ | RISCV_XORI => T
+ )))`;
+
+
+(*val encdec_iop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_iop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val itype_mnemonic_forwards : iop -> string*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards:iop -> string) arg_=
+ ((case arg_ of
+ RISCV_ADDI => "addi"
+ | RISCV_SLTI => "slti"
+ | RISCV_SLTIU => "sltiu"
+ | RISCV_XORI => "xori"
+ | RISCV_ORI => "ori"
+ | RISCV_ANDI => "andi"
+ )))`;
+
+
+(*val itype_mnemonic_backwards : string -> M iop*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((iop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addi"))) then sail2_state_monad$returnS RISCV_ADDI
+ else if (((p0_ = "slti"))) then sail2_state_monad$returnS RISCV_SLTI
+ else if (((p0_ = "sltiu"))) then sail2_state_monad$returnS RISCV_SLTIU
+ else if (((p0_ = "xori"))) then sail2_state_monad$returnS RISCV_XORI
+ else if (((p0_ = "ori"))) then sail2_state_monad$returnS RISCV_ORI
+ else if (((p0_ = "andi"))) then sail2_state_monad$returnS RISCV_ANDI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val itype_mnemonic_forwards_matches : iop -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_forwards_matches:iop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDI => T
+ | RISCV_SLTI => T
+ | RISCV_SLTIU => T
+ | RISCV_XORI => T
+ | RISCV_ORI => T
+ | RISCV_ANDI => T
+ )))`;
+
+
+(*val itype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((itype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addi"))) then T
+ else if (((p0_ = "slti"))) then T
+ else if (((p0_ = "sltiu"))) then T
+ else if (((p0_ = "xori"))) then T
+ else if (((p0_ = "ori"))) then T
+ else if (((p0_ = "andi"))) then T
+ else F))`;
+
+
+(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*)
+
+(*val _s544_ : string -> maybe string*)
+
+val _ = Define `
+ ((s544_:string ->(string)option) s545_0=
+ (let s546_0 = s545_0 in
+ if ((string_startswith s546_0 "andi")) then
+ (case ((string_drop s546_0 ((string_length "andi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s540_ : string -> maybe string*)
+
+val _ = Define `
+ ((s540_:string ->(string)option) s541_0=
+ (let s542_0 = s541_0 in
+ if ((string_startswith s542_0 "ori")) then
+ (case ((string_drop s542_0 ((string_length "ori")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s536_ : string -> maybe string*)
+
+val _ = Define `
+ ((s536_:string ->(string)option) s537_0=
+ (let s538_0 = s537_0 in
+ if ((string_startswith s538_0 "xori")) then
+ (case ((string_drop s538_0 ((string_length "xori")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s532_ : string -> maybe string*)
+
+val _ = Define `
+ ((s532_:string ->(string)option) s533_0=
+ (let s534_0 = s533_0 in
+ if ((string_startswith s534_0 "sltiu")) then
+ (case ((string_drop s534_0 ((string_length "sltiu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s528_ : string -> maybe string*)
+
+val _ = Define `
+ ((s528_:string ->(string)option) s529_0=
+ (let s530_0 = s529_0 in
+ if ((string_startswith s530_0 "slti")) then
+ (case ((string_drop s530_0 ((string_length "slti")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s524_ : string -> maybe string*)
+
+val _ = Define `
+ ((s524_:string ->(string)option) s525_0=
+ (let s526_0 = s525_0 in
+ if ((string_startswith s526_0 "addi")) then
+ (case ((string_drop s526_0 ((string_length "addi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((itype_mnemonic_matches_prefix:string ->(iop#int)option) arg_=
+ (let s527_0 = arg_ in
+ if ((case ((s524_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s524_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADDI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s528_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s528_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s532_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s532_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTIU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s536_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s536_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_XORI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s540_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s540_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ORI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s544_ s527_0)) of SOME (s_) => T | _ => F )) then
+ (case s544_ s527_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ANDI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_sop_forwards : sop -> mword ty3*)
+
+val _ = Define `
+ ((encdec_sop_forwards:sop ->(3)words$word) arg_=
+ ((case arg_ of
+ RISCV_SLLI => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_sop_backwards : mword ty3 -> M sop*)
+
+val _ = Define `
+ ((encdec_sop_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_sop_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((encdec_sop_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val encdec_sop_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_sop_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val shiftiop_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards:sop -> string) arg_=
+ ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftiop_mnemonic_backwards : string -> M sop*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((p0_ = "srli"))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((p0_ = "srai"))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftiop_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftiop_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftiop_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then T
+ else if (((p0_ = "srli"))) then T
+ else if (((p0_ = "srai"))) then T
+ else F))`;
+
+
+(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+(*val _s556_ : string -> maybe string*)
+
+val _ = Define `
+ ((s556_:string ->(string)option) s557_0=
+ (let s558_0 = s557_0 in
+ if ((string_startswith s558_0 "srai")) then
+ (case ((string_drop s558_0 ((string_length "srai")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s552_ : string -> maybe string*)
+
+val _ = Define `
+ ((s552_:string ->(string)option) s553_0=
+ (let s554_0 = s553_0 in
+ if ((string_startswith s554_0 "srli")) then
+ (case ((string_drop s554_0 ((string_length "srli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s548_ : string -> maybe string*)
+
+val _ = Define `
+ ((s548_:string ->(string)option) s549_0=
+ (let s550_0 = s549_0 in
+ if ((string_startswith s550_0 "slli")) then
+ (case ((string_drop s550_0 ((string_length "slli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftiop_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+ (let s551_0 = arg_ in
+ if ((case ((s548_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s548_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s552_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s552_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s556_ s551_0)) of SOME (s_) => T | _ => F )) then
+ (case s556_ s551_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val rtype_mnemonic_forwards : rop -> string*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards:rop -> string) arg_=
+ ((case arg_ of
+ RISCV_ADD => "add"
+ | RISCV_SLT => "slt"
+ | RISCV_SLTU => "sltu"
+ | RISCV_AND => "and"
+ | RISCV_OR => "or"
+ | RISCV_XOR => "xor"
+ | RISCV_SLL => "sll"
+ | RISCV_SRL => "srl"
+ | RISCV_SUB => "sub"
+ | RISCV_SRA => "sra"
+ )))`;
+
+
+(*val rtype_mnemonic_backwards : string -> M rop*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((rop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "add"))) then sail2_state_monad$returnS RISCV_ADD
+ else if (((p0_ = "slt"))) then sail2_state_monad$returnS RISCV_SLT
+ else if (((p0_ = "sltu"))) then sail2_state_monad$returnS RISCV_SLTU
+ else if (((p0_ = "and"))) then sail2_state_monad$returnS RISCV_AND
+ else if (((p0_ = "or"))) then sail2_state_monad$returnS RISCV_OR
+ else if (((p0_ = "xor"))) then sail2_state_monad$returnS RISCV_XOR
+ else if (((p0_ = "sll"))) then sail2_state_monad$returnS RISCV_SLL
+ else if (((p0_ = "srl"))) then sail2_state_monad$returnS RISCV_SRL
+ else if (((p0_ = "sub"))) then sail2_state_monad$returnS RISCV_SUB
+ else if (((p0_ = "sra"))) then sail2_state_monad$returnS RISCV_SRA
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val rtype_mnemonic_forwards_matches : rop -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_forwards_matches:rop -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADD => T
+ | RISCV_SLT => T
+ | RISCV_SLTU => T
+ | RISCV_AND => T
+ | RISCV_OR => T
+ | RISCV_XOR => T
+ | RISCV_SLL => T
+ | RISCV_SRL => T
+ | RISCV_SUB => T
+ | RISCV_SRA => T
+ )))`;
+
+
+(*val rtype_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((rtype_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "add"))) then T
+ else if (((p0_ = "slt"))) then T
+ else if (((p0_ = "sltu"))) then T
+ else if (((p0_ = "and"))) then T
+ else if (((p0_ = "or"))) then T
+ else if (((p0_ = "xor"))) then T
+ else if (((p0_ = "sll"))) then T
+ else if (((p0_ = "srl"))) then T
+ else if (((p0_ = "sub"))) then T
+ else if (((p0_ = "sra"))) then T
+ else F))`;
+
+
+(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*)
+
+(*val _s596_ : string -> maybe string*)
+
+val _ = Define `
+ ((s596_:string ->(string)option) s597_0=
+ (let s598_0 = s597_0 in
+ if ((string_startswith s598_0 "sra")) then
+ (case ((string_drop s598_0 ((string_length "sra")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s592_ : string -> maybe string*)
+
+val _ = Define `
+ ((s592_:string ->(string)option) s593_0=
+ (let s594_0 = s593_0 in
+ if ((string_startswith s594_0 "sub")) then
+ (case ((string_drop s594_0 ((string_length "sub")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s588_ : string -> maybe string*)
+
+val _ = Define `
+ ((s588_:string ->(string)option) s589_0=
+ (let s590_0 = s589_0 in
+ if ((string_startswith s590_0 "srl")) then
+ (case ((string_drop s590_0 ((string_length "srl")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s584_ : string -> maybe string*)
+
+val _ = Define `
+ ((s584_:string ->(string)option) s585_0=
+ (let s586_0 = s585_0 in
+ if ((string_startswith s586_0 "sll")) then
+ (case ((string_drop s586_0 ((string_length "sll")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s580_ : string -> maybe string*)
+
+val _ = Define `
+ ((s580_:string ->(string)option) s581_0=
+ (let s582_0 = s581_0 in
+ if ((string_startswith s582_0 "xor")) then
+ (case ((string_drop s582_0 ((string_length "xor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s576_ : string -> maybe string*)
+
+val _ = Define `
+ ((s576_:string ->(string)option) s577_0=
+ (let s578_0 = s577_0 in
+ if ((string_startswith s578_0 "or")) then
+ (case ((string_drop s578_0 ((string_length "or")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s572_ : string -> maybe string*)
+
+val _ = Define `
+ ((s572_:string ->(string)option) s573_0=
+ (let s574_0 = s573_0 in
+ if ((string_startswith s574_0 "and")) then
+ (case ((string_drop s574_0 ((string_length "and")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s568_ : string -> maybe string*)
+
+val _ = Define `
+ ((s568_:string ->(string)option) s569_0=
+ (let s570_0 = s569_0 in
+ if ((string_startswith s570_0 "sltu")) then
+ (case ((string_drop s570_0 ((string_length "sltu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s564_ : string -> maybe string*)
+
+val _ = Define `
+ ((s564_:string ->(string)option) s565_0=
+ (let s566_0 = s565_0 in
+ if ((string_startswith s566_0 "slt")) then
+ (case ((string_drop s566_0 ((string_length "slt")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s560_ : string -> maybe string*)
+
+val _ = Define `
+ ((s560_:string ->(string)option) s561_0=
+ (let s562_0 = s561_0 in
+ if ((string_startswith s562_0 "add")) then
+ (case ((string_drop s562_0 ((string_length "add")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((rtype_mnemonic_matches_prefix:string ->(rop#int)option) arg_=
+ (let s563_0 = arg_ in
+ if ((case ((s560_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s560_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s564_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s564_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLT, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s568_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s568_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLTU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s572_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s572_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_AND, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s576_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s576_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_OR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s580_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s580_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_XOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s584_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s584_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLL, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s588_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s588_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRL, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s592_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s592_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SUB, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s596_ s563_0)) of SOME (s_) => T | _ => F )) then
+ (case s596_ s563_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRA, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val extend_value : forall 'int8_times_n. Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*)
+
+val _ = Define `
+ ((extend_value:bool ->('int8_times_n words$word)MemoryOpResult ->((64)words$word)MemoryOpResult) is_unsigned value=
+ ((case value of
+ MemValue (v) =>
+ MemValue (if is_unsigned then (EXTZ (( 64 : int):ii) v : 64 words$word)
+ else (EXTS (( 64 : int):ii) v : 64 words$word))
+ | MemException (e) => MemException e
+ )))`;
+
+
+(*val process_load : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired*)
+
+val _ = Define `
+ ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+ ((case ((extend_value is_unsigned value : ( 64 words$word) MemoryOpResult)) of
+ MemValue (result) => sail2_state_monad$seqS (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))`;
+
+
+(*val check_misaligned : mword ty64 -> word_width -> bool*)
+
+val _ = Define `
+ ((check_misaligned:(64)words$word -> word_width -> bool) (vaddr : xlenbits) (width : word_width)=
+ (if ((plat_enable_misaligned_access () )) then F
+ else
+ (case width of
+ BYTE => F
+ | HALF => (((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T)
+ | WORD =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T))) \/ (((((bit_to_bool ((access_vec_dec vaddr (( 1 : int):ii))))) = T))))
+ | DOUBLE =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 : int):ii))))) = T))) \/ ((((((((bit_to_bool ((access_vec_dec vaddr (( 1 : int):ii))))) = T))) \/ (((((bit_to_bool ((access_vec_dec vaddr (( 2 : int):ii))))) = T)))))))
+ )))`;
+
+
+(*val maybe_aq_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_aq_forwards:bool -> string) arg_= ((case arg_ of T => ".aq" | F => "" )))`;
+
+
+(*val maybe_aq_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".aq"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_aq_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_aq_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_aq_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_aq_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".aq"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s604_ : string -> maybe string*)
+
+val _ = Define `
+ ((s604_:string ->(string)option) s605_0=
+ (let s606_0 = s605_0 in
+ if ((string_startswith s606_0 "")) then
+ (case ((string_drop s606_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s600_ : string -> maybe string*)
+
+val _ = Define `
+ ((s600_:string ->(string)option) s601_0=
+ (let s602_0 = s601_0 in
+ if ((string_startswith s602_0 ".aq")) then
+ (case ((string_drop s602_0 ((string_length ".aq")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_aq_matches_prefix:string ->(bool#int)option) arg_=
+ (let s603_0 = arg_ in
+ if ((case ((s600_ s603_0)) of SOME (s_) => T | _ => F )) then
+ (case s600_ s603_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s604_ s603_0)) of SOME (s_) => T | _ => F )) then
+ (case s604_ s603_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_rl_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_rl_forwards:bool -> string) arg_= ((case arg_ of T => ".rl" | F => "" )))`;
+
+
+(*val maybe_rl_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".rl"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_rl_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_rl_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_rl_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_rl_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = ".rl"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s612_ : string -> maybe string*)
+
+val _ = Define `
+ ((s612_:string ->(string)option) s613_0=
+ (let s614_0 = s613_0 in
+ if ((string_startswith s614_0 "")) then
+ (case ((string_drop s614_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s608_ : string -> maybe string*)
+
+val _ = Define `
+ ((s608_:string ->(string)option) s609_0=
+ (let s610_0 = s609_0 in
+ if ((string_startswith s610_0 ".rl")) then
+ (case ((string_drop s610_0 ((string_length ".rl")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_rl_matches_prefix:string ->(bool#int)option) arg_=
+ (let s611_0 = arg_ in
+ if ((case ((s608_ s611_0)) of SOME (s_) => T | _ => F )) then
+ (case s608_ s611_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s612_ s611_0)) of SOME (s_) => T | _ => F )) then
+ (case s612_ s611_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_u_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_u_forwards:bool -> string) arg_= ((case arg_ of T => "u" | F => "" )))`;
+
+
+(*val maybe_u_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_u_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_u_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_u_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_u_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_u_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s620_ : string -> maybe string*)
+
+val _ = Define `
+ ((s620_:string ->(string)option) s621_0=
+ (let s622_0 = s621_0 in
+ if ((string_startswith s622_0 "")) then
+ (case ((string_drop s622_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s616_ : string -> maybe string*)
+
+val _ = Define `
+ ((s616_:string ->(string)option) s617_0=
+ (let s618_0 = s617_0 in
+ if ((string_startswith s618_0 "u")) then
+ (case ((string_drop s618_0 ((string_length "u")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_u_matches_prefix:string ->(bool#int)option) arg_=
+ (let s619_0 = arg_ in
+ if ((case ((s616_ s619_0)) of SOME (s_) => T | _ => F )) then
+ (case s616_ s619_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s620_ s619_0)) of SOME (s_) => T | _ => F )) then
+ (case s620_ s619_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val shiftw_mnemonic_forwards : sop -> string*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards:sop -> string) arg_=
+ ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`;
+
+
+(*val shiftw_mnemonic_backwards : string -> M sop*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then sail2_state_monad$returnS RISCV_SLLI
+ else if (((p0_ = "srli"))) then sail2_state_monad$returnS RISCV_SRLI
+ else if (((p0_ = "srai"))) then sail2_state_monad$returnS RISCV_SRAI
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftw_mnemonic_forwards_matches : sop -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_forwards_matches:sop -> bool) arg_=
+ ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`;
+
+
+(*val shiftw_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftw_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slli"))) then T
+ else if (((p0_ = "srli"))) then T
+ else if (((p0_ = "srai"))) then T
+ else F))`;
+
+
+(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*)
+
+(*val _s632_ : string -> maybe string*)
+
+val _ = Define `
+ ((s632_:string ->(string)option) s633_0=
+ (let s634_0 = s633_0 in
+ if ((string_startswith s634_0 "srai")) then
+ (case ((string_drop s634_0 ((string_length "srai")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s628_ : string -> maybe string*)
+
+val _ = Define `
+ ((s628_:string ->(string)option) s629_0=
+ (let s630_0 = s629_0 in
+ if ((string_startswith s630_0 "srli")) then
+ (case ((string_drop s630_0 ((string_length "srli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s624_ : string -> maybe string*)
+
+val _ = Define `
+ ((s624_:string ->(string)option) s625_0=
+ (let s626_0 = s625_0 in
+ if ((string_startswith s626_0 "slli")) then
+ (case ((string_drop s626_0 ((string_length "slli")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftw_mnemonic_matches_prefix:string ->(sop#int)option) arg_=
+ (let s627_0 = arg_ in
+ if ((case ((s624_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s624_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s628_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s628_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s632_ s627_0)) of SOME (s_) => T | _ => F )) then
+ (case s632_ s627_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val rtypew_mnemonic_forwards : ropw -> string*)
+
+val _ = Define `
+ ((rtypew_mnemonic_forwards:ropw -> string) arg_=
+ ((case arg_ of
+ RISCV_ADDW => "addw"
+ | RISCV_SUBW => "subw"
+ | RISCV_SLLW => "sllw"
+ | RISCV_SRLW => "srlw"
+ | RISCV_SRAW => "sraw"
+ )))`;
+
+
+(*val rtypew_mnemonic_backwards : string -> M ropw*)
+
+val _ = Define `
+ ((rtypew_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((ropw),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addw"))) then sail2_state_monad$returnS RISCV_ADDW
+ else if (((p0_ = "subw"))) then sail2_state_monad$returnS RISCV_SUBW
+ else if (((p0_ = "sllw"))) then sail2_state_monad$returnS RISCV_SLLW
+ else if (((p0_ = "srlw"))) then sail2_state_monad$returnS RISCV_SRLW
+ else if (((p0_ = "sraw"))) then sail2_state_monad$returnS RISCV_SRAW
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val rtypew_mnemonic_forwards_matches : ropw -> bool*)
+
+val _ = Define `
+ ((rtypew_mnemonic_forwards_matches:ropw -> bool) arg_=
+ ((case arg_ of
+ RISCV_ADDW => T
+ | RISCV_SUBW => T
+ | RISCV_SLLW => T
+ | RISCV_SRLW => T
+ | RISCV_SRAW => T
+ )))`;
+
+
+(*val rtypew_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((rtypew_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "addw"))) then T
+ else if (((p0_ = "subw"))) then T
+ else if (((p0_ = "sllw"))) then T
+ else if (((p0_ = "srlw"))) then T
+ else if (((p0_ = "sraw"))) then T
+ else F))`;
+
+
+(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*)
+
+(*val _s652_ : string -> maybe string*)
+
+val _ = Define `
+ ((s652_:string ->(string)option) s653_0=
+ (let s654_0 = s653_0 in
+ if ((string_startswith s654_0 "sraw")) then
+ (case ((string_drop s654_0 ((string_length "sraw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s648_ : string -> maybe string*)
+
+val _ = Define `
+ ((s648_:string ->(string)option) s649_0=
+ (let s650_0 = s649_0 in
+ if ((string_startswith s650_0 "srlw")) then
+ (case ((string_drop s650_0 ((string_length "srlw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s644_ : string -> maybe string*)
+
+val _ = Define `
+ ((s644_:string ->(string)option) s645_0=
+ (let s646_0 = s645_0 in
+ if ((string_startswith s646_0 "sllw")) then
+ (case ((string_drop s646_0 ((string_length "sllw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s640_ : string -> maybe string*)
+
+val _ = Define `
+ ((s640_:string ->(string)option) s641_0=
+ (let s642_0 = s641_0 in
+ if ((string_startswith s642_0 "subw")) then
+ (case ((string_drop s642_0 ((string_length "subw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s636_ : string -> maybe string*)
+
+val _ = Define `
+ ((s636_:string ->(string)option) s637_0=
+ (let s638_0 = s637_0 in
+ if ((string_startswith s638_0 "addw")) then
+ (case ((string_drop s638_0 ((string_length "addw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((rtypew_mnemonic_matches_prefix:string ->(ropw#int)option) arg_=
+ (let s639_0 = arg_ in
+ if ((case ((s636_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s636_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_ADDW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s640_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s640_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SUBW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s644_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s644_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s648_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s648_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s652_ s639_0)) of SOME (s_) => T | _ => F )) then
+ (case s652_ s639_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val shiftiwop_mnemonic_forwards : sopw -> string*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_forwards:sopw -> string) arg_=
+ ((case arg_ of RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" )))`;
+
+
+(*val shiftiwop_mnemonic_backwards : string -> M sopw*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((sopw),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slliw"))) then sail2_state_monad$returnS RISCV_SLLIW
+ else if (((p0_ = "srliw"))) then sail2_state_monad$returnS RISCV_SRLIW
+ else if (((p0_ = "sraiw"))) then sail2_state_monad$returnS RISCV_SRAIW
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val shiftiwop_mnemonic_forwards_matches : sopw -> bool*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_forwards_matches:sopw -> bool) arg_=
+ ((case arg_ of RISCV_SLLIW => T | RISCV_SRLIW => T | RISCV_SRAIW => T )))`;
+
+
+(*val shiftiwop_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((shiftiwop_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "slliw"))) then T
+ else if (((p0_ = "srliw"))) then T
+ else if (((p0_ = "sraiw"))) then T
+ else F))`;
+
+
+(*val shiftiwop_mnemonic_matches_prefix : string -> maybe ((sopw * ii))*)
+
+(*val _s664_ : string -> maybe string*)
+
+val _ = Define `
+ ((s664_:string ->(string)option) s665_0=
+ (let s666_0 = s665_0 in
+ if ((string_startswith s666_0 "sraiw")) then
+ (case ((string_drop s666_0 ((string_length "sraiw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s660_ : string -> maybe string*)
+
+val _ = Define `
+ ((s660_:string ->(string)option) s661_0=
+ (let s662_0 = s661_0 in
+ if ((string_startswith s662_0 "srliw")) then
+ (case ((string_drop s662_0 ((string_length "srliw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s656_ : string -> maybe string*)
+
+val _ = Define `
+ ((s656_:string ->(string)option) s657_0=
+ (let s658_0 = s657_0 in
+ if ((string_startswith s658_0 "slliw")) then
+ (case ((string_drop s658_0 ((string_length "slliw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((shiftiwop_mnemonic_matches_prefix:string ->(sopw#int)option) arg_=
+ (let s659_0 = arg_ in
+ if ((case ((s656_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s656_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SLLIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s660_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s660_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRLIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s664_ s659_0)) of SOME (s_) => T | _ => F )) then
+ (case s664_ s659_0 of
+ (SOME (s_)) =>
+ SOME (RISCV_SRAIW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_r_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_r_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "r"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_r_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_r_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "r"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_r_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_r_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_r_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "r"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s672_ : string -> maybe string*)
+
+val _ = Define `
+ ((s672_:string ->(string)option) s673_0=
+ (let s674_0 = s673_0 in
+ if ((string_startswith s674_0 "")) then
+ (case ((string_drop s674_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s668_ : string -> maybe string*)
+
+val _ = Define `
+ ((s668_:string ->(string)option) s669_0=
+ (let s670_0 = s669_0 in
+ if ((string_startswith s670_0 "r")) then
+ (case ((string_drop s670_0 ((string_length "r")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_r_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s671_0 = arg_ in
+ if ((case ((s668_ s671_0)) of SOME (s_) => T | _ => F )) then
+ (case s668_ s671_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s672_ s671_0)) of SOME (s_) => T | _ => F )) then
+ (case s672_ s671_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_w_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_w_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "w"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_w_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_w_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "w"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_w_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_w_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_w_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "w"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s680_ : string -> maybe string*)
+
+val _ = Define `
+ ((s680_:string ->(string)option) s681_0=
+ (let s682_0 = s681_0 in
+ if ((string_startswith s682_0 "")) then
+ (case ((string_drop s682_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s676_ : string -> maybe string*)
+
+val _ = Define `
+ ((s676_:string ->(string)option) s677_0=
+ (let s678_0 = s677_0 in
+ if ((string_startswith s678_0 "w")) then
+ (case ((string_drop s678_0 ((string_length "w")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_w_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s679_0 = arg_ in
+ if ((case ((s676_ s679_0)) of SOME (s_) => T | _ => F )) then
+ (case s676_ s679_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s680_ s679_0)) of SOME (s_) => T | _ => F )) then
+ (case s680_ s679_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_i_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_i_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "i"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_i_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_i_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_i_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_i_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_i_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s688_ : string -> maybe string*)
+
+val _ = Define `
+ ((s688_:string ->(string)option) s689_0=
+ (let s690_0 = s689_0 in
+ if ((string_startswith s690_0 "")) then
+ (case ((string_drop s690_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s684_ : string -> maybe string*)
+
+val _ = Define `
+ ((s684_:string ->(string)option) s685_0=
+ (let s686_0 = s685_0 in
+ if ((string_startswith s686_0 "i")) then
+ (case ((string_drop s686_0 ((string_length "i")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_i_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s687_0 = arg_ in
+ if ((case ((s684_ s687_0)) of SOME (s_) => T | _ => F )) then
+ (case s684_ s687_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s688_ s687_0)) of SOME (s_) => T | _ => F )) then
+ (case s688_ s687_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val bit_maybe_o_forwards : mword ty1 -> M string*)
+
+val _ = Define `
+ ((bit_maybe_o_forwards:(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$returnS "o"
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS ""
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_o_backwards : string -> M (mword ty1)*)
+
+val _ = Define `
+ ((bit_maybe_o_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "o"))) then sail2_state_monad$returnS (vec_of_bits [B1] : 1 words$word)
+ else if (((p0_ = ""))) then sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*)
+
+val _ = Define `
+ ((bit_maybe_o_forwards_matches:(1)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B1] : 1 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then T
+ else F))`;
+
+
+(*val bit_maybe_o_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((bit_maybe_o_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "o"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*)
+
+(*val _s696_ : string -> maybe string*)
+
+val _ = Define `
+ ((s696_:string ->(string)option) s697_0=
+ (let s698_0 = s697_0 in
+ if ((string_startswith s698_0 "")) then
+ (case ((string_drop s698_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s692_ : string -> maybe string*)
+
+val _ = Define `
+ ((s692_:string ->(string)option) s693_0=
+ (let s694_0 = s693_0 in
+ if ((string_startswith s694_0 "o")) then
+ (case ((string_drop s694_0 ((string_length "o")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((bit_maybe_o_matches_prefix:string ->((1)words$word#int)option) arg_=
+ (let s695_0 = arg_ in
+ if ((case ((s692_ s695_0)) of SOME (s_) => T | _ => F )) then
+ (case s692_ s695_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B1] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s696_ s695_0)) of SOME (s_) => T | _ => F )) then
+ (case s696_ s695_0 of
+ (SOME (s_)) =>
+ SOME
+ ((vec_of_bits [B0] : 1 words$word), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val fence_bits_forwards : mword ty4 -> M string*)
+
+val _ = Define `
+ ((fence_bits_forwards:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ v__0 =>
+ let (i : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (w : 1 bits) = ((subrange_vec_dec v__0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ let (r : 1 bits) = ((subrange_vec_dec v__0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (o1 : 1 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bit_maybe_i_forwards i) (\ (w__0 : string) . sail2_state_monad$bindS
+ (bit_maybe_o_forwards o1) (\ (w__1 : string) . sail2_state_monad$bindS
+ (bit_maybe_r_forwards r) (\ (w__2 : string) . sail2_state_monad$bindS
+ (bit_maybe_w_forwards w) (\ (w__3 : string) .
+ sail2_state_monad$returnS ((string_append w__0
+ ((string_append w__1 ((string_append w__2 ((string_append w__3 ""))))))))))))
+ )))`;
+
+
+(*val fence_bits_backwards : string -> M (mword ty4)*)
+
+(*val _s700_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))*)
+
+val _ = Define `
+ ((s700_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word)option) s701_0=
+ ((case s701_0 of
+ s702_0 =>
+ (case ((bit_maybe_i_matches_prefix s702_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s703_0)) =>
+ (case ((string_drop s702_0 s703_0)) of
+ s704_0 =>
+ (case ((bit_maybe_o_matches_prefix s704_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s705_0)) =>
+ (case ((string_drop s704_0 s705_0)) of
+ s706_0 =>
+ (case ((bit_maybe_r_matches_prefix s706_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s707_0)) =>
+ (case ((string_drop s706_0 s707_0)) of
+ s708_0 =>
+ (case ((bit_maybe_w_matches_prefix s708_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s709_0)) =>
+ let p0_ = (string_drop s708_0 s709_0) in
+ if (((p0_ = ""))) then SOME (i, o1, r, w) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_backwards:string ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s710_0 = arg_ in
+ if ((case ((s700_ s710_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word))option)) of
+ SOME ((i, o1, r, w)) => T
+ | _ => F
+ )) then (case
+ (s700_ s710_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word)) option) of
+ (SOME ((i, o1, r, w))) =>
+ sail2_state_monad$returnS
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w : 2 words$word)) : 3 words$word))
+ : 4 words$word))
+ )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val fence_bits_forwards_matches : mword ty4 -> bool*)
+
+val _ = Define `
+ ((fence_bits_forwards_matches:(4)words$word -> bool) arg_=
+ ((case arg_ of v__1 => T )))`;
+
+
+(*val fence_bits_backwards_matches : string -> bool*)
+
+(*val _s711_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))*)
+
+val _ = Define `
+ ((s711_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word)option) s712_0=
+ ((case s712_0 of
+ s713_0 =>
+ (case ((bit_maybe_i_matches_prefix s713_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s714_0)) =>
+ (case ((string_drop s713_0 s714_0)) of
+ s715_0 =>
+ (case ((bit_maybe_o_matches_prefix s715_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s716_0)) =>
+ (case ((string_drop s715_0 s716_0)) of
+ s717_0 =>
+ (case ((bit_maybe_r_matches_prefix s717_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s718_0)) =>
+ (case ((string_drop s717_0 s718_0)) of
+ s719_0 =>
+ (case ((bit_maybe_w_matches_prefix s719_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s720_0)) =>
+ let p0_ = (string_drop s719_0 s720_0) in
+ if (((p0_ = ""))) then SOME (i, o1, r, w) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_backwards_matches:string -> bool) arg_=
+ (let s721_0 = arg_ in
+ if ((case ((s711_ s721_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word))option)) of
+ SOME ((i, o1, r, w)) => T
+ | _ => F
+ )) then (case
+ (s711_ s721_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word)) option) of
+ (SOME ((i, o1, r, w))) =>
+ T
+ )
+ else F))`;
+
+
+(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*)
+
+(*val _s722_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1 * string))*)
+
+val _ = Define `
+ ((s722_:string ->((1)words$word#(1)words$word#(1)words$word#(1)words$word#string)option) s723_0=
+ ((case s723_0 of
+ s724_0 =>
+ (case ((bit_maybe_i_matches_prefix s724_0 : (( 1 words$word # ii)) option)) of
+ SOME ((i, s725_0)) =>
+ (case ((string_drop s724_0 s725_0)) of
+ s726_0 =>
+ (case ((bit_maybe_o_matches_prefix s726_0 : (( 1 words$word # ii)) option)) of
+ SOME ((o1, s727_0)) =>
+ (case ((string_drop s726_0 s727_0)) of
+ s728_0 =>
+ (case ((bit_maybe_r_matches_prefix s728_0 : (( 1 words$word # ii)) option)) of
+ SOME ((r, s729_0)) =>
+ (case ((string_drop s728_0 s729_0)) of
+ s730_0 =>
+ (case ((bit_maybe_w_matches_prefix s730_0 : (( 1 words$word # ii)) option)) of
+ SOME ((w, s731_0)) =>
+ (case ((string_drop s730_0 s731_0)) of s_ => SOME (i, o1, r, w, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((fence_bits_matches_prefix:string ->((4)words$word#int)option) arg_=
+ (let s732_0 = arg_ in
+ if ((case ((s722_ s732_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word # string))option)) of
+ SOME ((i, o1, r, w, s_)) => T
+ | _ => F
+ )) then (case
+ (s722_ s732_0 : (( 1 words$word # 1 words$word # 1 words$word # 1 words$word # string)) option) of
+ (SOME ((i, o1, r, w, s_))) =>
+ SOME
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w : 2 words$word)) : 3 words$word)) : 4 words$word),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val aqrl_str : bool -> bool -> string*)
+
+val _ = Define `
+ ((aqrl_str:bool -> bool -> string) (aq : bool) (rl : bool)=
+ ((case (aq, rl) of
+ (F, F) => ""
+ | (F, T) => ".rl"
+ | (T, F) => ".aq"
+ | (T, T) => ".aqrl"
+ )))`;
+
+
+(*val lrsc_width_str : word_width -> string*)
+
+val _ = Define `
+ ((lrsc_width_str:word_width -> string) width=
+ ((case width of BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" )))`;
+
+
+(*val process_loadres : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired*)
+
+val _ = Define `
+ ((process_loadres:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned=
+ ((case ((extend_value is_unsigned value : ( 64 words$word) MemoryOpResult)) of
+ MemValue (result) =>
+ let (_ : unit) = (load_reservation addr) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))`;
+
+
+(*val encdec_amoop_forwards : amoop -> mword ty5*)
+
+val _ = Define `
+ ((encdec_amoop_forwards:amoop ->(5)words$word) arg_=
+ ((case arg_ of
+ AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)
+ | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)
+ | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)
+ | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)
+ | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)
+ | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)
+ | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)
+ | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)
+ )))`;
+
+
+(*val encdec_amoop_backwards : mword ty5 -> M amoop*)
+
+val _ = Define `
+ ((encdec_amoop_backwards:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((amoop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))
+ then
+ sail2_state_monad$returnS AMOSWAP
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOADD
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOXOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOAND
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMIN
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMAX
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMINU
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ sail2_state_monad$returnS AMOMAXU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_amoop_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_forwards_matches:amoop -> bool) arg_=
+ ((case arg_ of
+ AMOSWAP => T
+ | AMOADD => T
+ | AMOXOR => T
+ | AMOAND => T
+ | AMOOR => T
+ | AMOMIN => T
+ | AMOMAX => T
+ | AMOMINU => T
+ | AMOMAXU => T
+ )))`;
+
+
+(*val encdec_amoop_backwards_matches : mword ty5 -> bool*)
+
+val _ = Define `
+ ((encdec_amoop_backwards_matches:(5)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))
+ then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then
+ T
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then
+ T
+ else F))`;
+
+
+(*val amo_mnemonic_forwards : amoop -> string*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards:amoop -> string) arg_=
+ ((case arg_ of
+ AMOSWAP => "amoswap"
+ | AMOADD => "amoadd"
+ | AMOXOR => "amoxor"
+ | AMOAND => "amoand"
+ | AMOOR => "amoor"
+ | AMOMIN => "amomin"
+ | AMOMAX => "amomax"
+ | AMOMINU => "amominu"
+ | AMOMAXU => "amomaxu"
+ )))`;
+
+
+(*val amo_mnemonic_backwards : string -> M amoop*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((amoop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "amoswap"))) then sail2_state_monad$returnS AMOSWAP
+ else if (((p0_ = "amoadd"))) then sail2_state_monad$returnS AMOADD
+ else if (((p0_ = "amoxor"))) then sail2_state_monad$returnS AMOXOR
+ else if (((p0_ = "amoand"))) then sail2_state_monad$returnS AMOAND
+ else if (((p0_ = "amoor"))) then sail2_state_monad$returnS AMOOR
+ else if (((p0_ = "amomin"))) then sail2_state_monad$returnS AMOMIN
+ else if (((p0_ = "amomax"))) then sail2_state_monad$returnS AMOMAX
+ else if (((p0_ = "amominu"))) then sail2_state_monad$returnS AMOMINU
+ else if (((p0_ = "amomaxu"))) then sail2_state_monad$returnS AMOMAXU
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val amo_mnemonic_forwards_matches : amoop -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_forwards_matches:amoop -> bool) arg_=
+ ((case arg_ of
+ AMOSWAP => T
+ | AMOADD => T
+ | AMOXOR => T
+ | AMOAND => T
+ | AMOOR => T
+ | AMOMIN => T
+ | AMOMAX => T
+ | AMOMINU => T
+ | AMOMAXU => T
+ )))`;
+
+
+(*val amo_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((amo_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "amoswap"))) then T
+ else if (((p0_ = "amoadd"))) then T
+ else if (((p0_ = "amoxor"))) then T
+ else if (((p0_ = "amoand"))) then T
+ else if (((p0_ = "amoor"))) then T
+ else if (((p0_ = "amomin"))) then T
+ else if (((p0_ = "amomax"))) then T
+ else if (((p0_ = "amominu"))) then T
+ else if (((p0_ = "amomaxu"))) then T
+ else F))`;
+
+
+(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*)
+
+(*val _s765_ : string -> maybe string*)
+
+val _ = Define `
+ ((s765_:string ->(string)option) s766_0=
+ (let s767_0 = s766_0 in
+ if ((string_startswith s767_0 "amomaxu")) then
+ (case ((string_drop s767_0 ((string_length "amomaxu")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s761_ : string -> maybe string*)
+
+val _ = Define `
+ ((s761_:string ->(string)option) s762_0=
+ (let s763_0 = s762_0 in
+ if ((string_startswith s763_0 "amominu")) then
+ (case ((string_drop s763_0 ((string_length "amominu")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s757_ : string -> maybe string*)
+
+val _ = Define `
+ ((s757_:string ->(string)option) s758_0=
+ (let s759_0 = s758_0 in
+ if ((string_startswith s759_0 "amomax")) then
+ (case ((string_drop s759_0 ((string_length "amomax")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s753_ : string -> maybe string*)
+
+val _ = Define `
+ ((s753_:string ->(string)option) s754_0=
+ (let s755_0 = s754_0 in
+ if ((string_startswith s755_0 "amomin")) then
+ (case ((string_drop s755_0 ((string_length "amomin")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s749_ : string -> maybe string*)
+
+val _ = Define `
+ ((s749_:string ->(string)option) s750_0=
+ (let s751_0 = s750_0 in
+ if ((string_startswith s751_0 "amoor")) then
+ (case ((string_drop s751_0 ((string_length "amoor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s745_ : string -> maybe string*)
+
+val _ = Define `
+ ((s745_:string ->(string)option) s746_0=
+ (let s747_0 = s746_0 in
+ if ((string_startswith s747_0 "amoand")) then
+ (case ((string_drop s747_0 ((string_length "amoand")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s741_ : string -> maybe string*)
+
+val _ = Define `
+ ((s741_:string ->(string)option) s742_0=
+ (let s743_0 = s742_0 in
+ if ((string_startswith s743_0 "amoxor")) then
+ (case ((string_drop s743_0 ((string_length "amoxor")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s737_ : string -> maybe string*)
+
+val _ = Define `
+ ((s737_:string ->(string)option) s738_0=
+ (let s739_0 = s738_0 in
+ if ((string_startswith s739_0 "amoadd")) then
+ (case ((string_drop s739_0 ((string_length "amoadd")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s733_ : string -> maybe string*)
+
+val _ = Define `
+ ((s733_:string ->(string)option) s734_0=
+ (let s735_0 = s734_0 in
+ if ((string_startswith s735_0 "amoswap")) then
+ (case ((string_drop s735_0 ((string_length "amoswap")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((amo_mnemonic_matches_prefix:string ->(amoop#int)option) arg_=
+ (let s736_0 = arg_ in
+ if ((case ((s733_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s733_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOSWAP, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s737_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s737_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOADD, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s741_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s741_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOXOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s745_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s745_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOAND, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s749_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s749_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOOR, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s753_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s753_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMIN, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s757_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s757_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMAX, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s761_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s761_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMINU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s765_ s736_0)) of SOME (s_) => T | _ => F )) then
+ (case s765_ s736_0 of
+ (SOME (s_)) =>
+ SOME (AMOMAXU, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_mul_op_forwards : (bool * bool * bool) -> mword ty3*)
+
+val _ = Define `
+ ((encdec_mul_op_forwards:bool#bool#bool ->(3)words$word) arg_=
+ ((case arg_ of
+ (F, T, T) => (vec_of_bits [B0;B0;B0] : 3 words$word)
+ | (T, T, T) => (vec_of_bits [B0;B0;B1] : 3 words$word)
+ | (T, T, F) => (vec_of_bits [B0;B1;B0] : 3 words$word)
+ | (T, F, F) => (vec_of_bits [B0;B1;B1] : 3 words$word)
+ )))`;
+
+
+(*val encdec_mul_op_backwards : mword ty3 -> M (bool * bool * bool)*)
+
+val _ = Define `
+ ((encdec_mul_op_backwards:(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$returnS (F, T, T)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$returnS (T, T, T)
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$returnS (T, T, F)
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$returnS (T, F, F)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_mul_op_forwards_matches : (bool * bool * bool) -> bool*)
+
+val _ = Define `
+ ((encdec_mul_op_forwards_matches:bool#bool#bool -> bool) arg_=
+ ((case arg_ of
+ (F, T, T) => T
+ | (T, T, T) => T
+ | (T, T, F) => T
+ | (T, F, F) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*)
+
+val _ = Define `
+ ((encdec_mul_op_backwards_matches:(3)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T
+ else F))`;
+
+
+(*val mul_mnemonic_forwards : (bool * bool * bool) -> string*)
+
+val _ = Define `
+ ((mul_mnemonic_forwards:bool#bool#bool -> string) arg_=
+ ((case arg_ of
+ (F, T, T) => "mul"
+ | (T, T, T) => "mulh"
+ | (T, T, F) => "mulhsu"
+ | (T, F, F) => "mulhu"
+ )))`;
+
+
+(*val mul_mnemonic_backwards : string -> M (bool * bool * bool)*)
+
+val _ = Define `
+ ((mul_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "mul"))) then sail2_state_monad$returnS (F, T, T)
+ else if (((p0_ = "mulh"))) then sail2_state_monad$returnS (T, T, T)
+ else if (((p0_ = "mulhsu"))) then sail2_state_monad$returnS (T, T, F)
+ else if (((p0_ = "mulhu"))) then sail2_state_monad$returnS (T, F, F)
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val mul_mnemonic_forwards_matches : (bool * bool * bool) -> bool*)
+
+val _ = Define `
+ ((mul_mnemonic_forwards_matches:bool#bool#bool -> bool) arg_=
+ ((case arg_ of
+ (F, T, T) => T
+ | (T, T, T) => T
+ | (T, T, F) => T
+ | (T, F, F) => T
+ | _ => F
+ )))`;
+
+
+(*val mul_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((mul_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "mul"))) then T
+ else if (((p0_ = "mulh"))) then T
+ else if (((p0_ = "mulhsu"))) then T
+ else if (((p0_ = "mulhu"))) then T
+ else F))`;
+
+
+(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*)
+
+(*val _s781_ : string -> maybe string*)
+
+val _ = Define `
+ ((s781_:string ->(string)option) s782_0=
+ (let s783_0 = s782_0 in
+ if ((string_startswith s783_0 "mulhu")) then
+ (case ((string_drop s783_0 ((string_length "mulhu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s777_ : string -> maybe string*)
+
+val _ = Define `
+ ((s777_:string ->(string)option) s778_0=
+ (let s779_0 = s778_0 in
+ if ((string_startswith s779_0 "mulhsu")) then
+ (case ((string_drop s779_0 ((string_length "mulhsu")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s773_ : string -> maybe string*)
+
+val _ = Define `
+ ((s773_:string ->(string)option) s774_0=
+ (let s775_0 = s774_0 in
+ if ((string_startswith s775_0 "mulh")) then
+ (case ((string_drop s775_0 ((string_length "mulh")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s769_ : string -> maybe string*)
+
+val _ = Define `
+ ((s769_:string ->(string)option) s770_0=
+ (let s771_0 = s770_0 in
+ if ((string_startswith s771_0 "mul")) then
+ (case ((string_drop s771_0 ((string_length "mul")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((mul_mnemonic_matches_prefix:string ->((bool#bool#bool)#int)option) arg_=
+ (let s772_0 = arg_ in
+ if ((case ((s769_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s769_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((F, T, T), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s773_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s773_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, T, T), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s777_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s777_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, T, F), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s781_ s772_0)) of SOME (s_) => T | _ => F )) then
+ (case s781_ s772_0 of
+ (SOME (s_)) =>
+ SOME ((T, F, F), ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val maybe_not_u_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_not_u_forwards:bool -> string) arg_= ((case arg_ of F => "u" | T => "" )))`;
+
+
+(*val maybe_not_u_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_not_u_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then sail2_state_monad$returnS F
+ else if (((p0_ = ""))) then sail2_state_monad$returnS T
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_not_u_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_not_u_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of F => T | T => T )))`;
+
+
+(*val maybe_not_u_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_not_u_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "u"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s789_ : string -> maybe string*)
+
+val _ = Define `
+ ((s789_:string ->(string)option) s790_0=
+ (let s791_0 = s790_0 in
+ if ((string_startswith s791_0 "")) then
+ (case ((string_drop s791_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s785_ : string -> maybe string*)
+
+val _ = Define `
+ ((s785_:string ->(string)option) s786_0=
+ (let s787_0 = s786_0 in
+ if ((string_startswith s787_0 "u")) then
+ (case ((string_drop s787_0 ((string_length "u")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_not_u_matches_prefix:string ->(bool#int)option) arg_=
+ (let s788_0 = arg_ in
+ if ((case ((s785_ s788_0)) of SOME (s_) => T | _ => F )) then
+ (case s785_ s788_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s789_ s788_0)) of SOME (s_) => T | _ => F )) then
+ (case s789_ s788_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_csrop_forwards : csrop -> mword ty2*)
+
+val _ = Define `
+ ((encdec_csrop_forwards:csrop ->(2)words$word) arg_=
+ ((case arg_ of
+ CSRRW => (vec_of_bits [B0;B1] : 2 words$word)
+ | CSRRS => (vec_of_bits [B1;B0] : 2 words$word)
+ | CSRRC => (vec_of_bits [B1;B1] : 2 words$word)
+ )))`;
+
+
+(*val encdec_csrop_backwards : mword ty2 -> M csrop*)
+
+val _ = Define `
+ ((encdec_csrop_backwards:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((csrop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS CSRRW
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS CSRRS
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS CSRRC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val encdec_csrop_forwards_matches : csrop -> bool*)
+
+val _ = Define `
+ ((encdec_csrop_forwards_matches:csrop -> bool) arg_=
+ ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`;
+
+
+(*val encdec_csrop_backwards_matches : mword ty2 -> bool*)
+
+val _ = Define `
+ ((encdec_csrop_backwards_matches:(2)words$word -> bool) arg_=
+ (let b__0 = arg_ in
+ if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then T
+ else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then T
+ else F))`;
+
+
+(*val readCSR : mword ty12 -> M (mword ty64)*)
+
+val _ = Define `
+ ((readCSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr= (sail2_state_monad$bindS
+ (case (csr, (( 64 : int):ii)) of
+ (b__0, g__15) =>
+ if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mvendorid_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) .
+ sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) w__0 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS marchid_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mimpid_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mhartid_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ sail2_state_monad$returnS ((get_Mstatus_bits w__4 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__5 : Misa) . sail2_state_monad$returnS ((get_Misa_bits w__5 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) .
+ sail2_state_monad$returnS ((get_Medeleg_bits w__6 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__7 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__8 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ (get_mtvec () : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__10 : Counteren) .
+ sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__10 : 32 words$word)) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mscratch_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target Machine : ( 64 words$word) M) (\ (w__12 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__13 : 64 words$word) .
+ sail2_state_monad$returnS ((and_vec w__12 w__13 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcause_ref) (\ (w__14 : Mcause) .
+ sail2_state_monad$returnS ((get_Mcause_bits w__14 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS mtval_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__16 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Minterrupts_bits w__16 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (pmpReadCfgReg (( 0 : int):ii) : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then
+ (pmpReadCfgReg (( 2 : int):ii) : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__35 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__35 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__36 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__36 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS tselect_ref : ( 64 words$word) M) (\ (w__37 : 64 words$word) .
+ sail2_state_monad$returnS ((not_vec w__37 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__38 : Mstatus) .
+ sail2_state_monad$returnS ((get_Sstatus_bits ((lower_mstatus w__38)) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sedeleg_ref) (\ (w__39 : Sedeleg) .
+ sail2_state_monad$returnS ((get_Sedeleg_bits w__39 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sideleg_ref) (\ (w__40 : Sinterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits w__40 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__41 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__42 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mie w__41 w__42)) : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then
+ (get_stvec () : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scounteren_ref) (\ (w__44 : Counteren) .
+ sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__44 : 32 words$word)) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS sscratch_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (get_xret_target Supervisor : ( 64 words$word) M) (\ (w__46 : 64 words$word) . sail2_state_monad$bindS
+ (pc_alignment_mask () : ( 64 words$word) M) (\ (w__47 : 64 words$word) .
+ sail2_state_monad$returnS ((and_vec w__46 w__47 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scause_ref) (\ (w__48 : Mcause) .
+ sail2_state_monad$returnS ((get_Mcause_bits w__48 : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then
+ (sail2_state_monad$read_regS stval_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__50 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__51 : Minterrupts) .
+ sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mip w__50 w__51)) : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M)
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__53 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__53 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__54 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__54 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)))
+ else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__55 : 64 words$word) .
+ sail2_state_monad$returnS ((subrange_vec_dec w__55 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)))
+ else sail2_state_monad$bindS
+ (ext_read_CSR csr : ( ( 64 words$word)option) M) (\ (w__56 : ( 64 words$word)option) .
+ sail2_state_monad$returnS ((case w__56 of
+ SOME (res) => res
+ | NONE =>
+ let (_ : unit) = (print_bits0 "unhandled read to CSR " csr) in
+ (EXTZ (( 64 : int):ii) (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 64 words$word)
+ )))
+ ) (\ (res : xlenbits) .
+ let (_ : unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr)) ((STRCAT " -> " ((string_of_bits res))))))))
+ else () ) in
+ sail2_state_monad$returnS res)))`;
+
+
+(*val writeCSR : mword ty12 -> mword ty64 -> M unit*)
+
+val _ = Define `
+ ((writeCSR:(12)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= (sail2_state_monad$bindS
+ (case (csr, (( 64 : int):ii)) of
+ (b__0, g__14) =>
+ if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . sail2_state_monad$bindS
+ (legalize_mstatus w__0 value) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__1)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__2 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS misa_ref) (\ (w__3 : Misa) . sail2_state_monad$bindS
+ (legalize_misa w__3 value) (\ (w__4 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS misa_ref w__4)
+ (sail2_state_monad$read_regS misa_ref)) (\ (w__5 : Misa) .
+ sail2_state_monad$returnS (SOME ((get_Misa_bits w__5 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS medeleg_ref ((legalize_medeleg w__6 value)))
+ (sail2_state_monad$read_regS medeleg_ref)) (\ (w__7 : Medeleg) .
+ sail2_state_monad$returnS (SOME ((get_Medeleg_bits w__7 : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__8 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mideleg_ref ((legalize_mideleg w__8 value)))
+ (sail2_state_monad$read_regS mideleg_ref)) (\ (w__9 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__9 : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__10 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_mie w__10 value) (\ (w__11 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__11)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__12 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__12 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_mtvec value : ( 64 words$word) M) (\ (w__13 : 64 words$word) . sail2_state_monad$returnS (SOME w__13))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcounteren_ref) (\ (w__14 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mcounteren_ref ((legalize_mcounteren w__14 value)))
+ (sail2_state_monad$read_regS mcounteren_ref)) (\ (w__15 : Counteren) .
+ sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__15 : 32 words$word)) : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mscratch_ref value)
+ (sail2_state_monad$read_regS mscratch_ref : ( 64 words$word) M)) (\ (w__16 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__16))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target Machine value : ( 64 words$word) M) (\ (w__17 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__17))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits mcause_ref value)
+ (sail2_state_monad$read_regS mcause_ref)) (\ (w__18 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__18 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mtval_ref value)
+ (sail2_state_monad$read_regS mtval_ref : ( 64 words$word) M)) (\ (w__19 : 64 words$word) . sail2_state_monad$returnS (SOME w__19))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__20 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_mip w__20 value) (\ (w__21 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__21)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__22 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__22 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 0 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$seqS
+ (pmpWriteCfgReg (( 2 : int):ii) value) (sail2_state_monad$returnS (SOME value))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp0cfg_ref) (\ (w__23 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M) (\ (w__24 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr0_ref ((pmpWriteAddr w__23 w__24 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M)) (\ (w__25 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__25))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp1cfg_ref) (\ (w__26 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 64 words$word) M) (\ (w__27 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr1_ref ((pmpWriteAddr w__26 w__27 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr1_ref : ( 64 words$word) M)) (\ (w__28 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__28))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp2cfg_ref) (\ (w__29 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 64 words$word) M) (\ (w__30 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr2_ref ((pmpWriteAddr w__29 w__30 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr2_ref : ( 64 words$word) M)) (\ (w__31 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__31))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp3cfg_ref) (\ (w__32 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 64 words$word) M) (\ (w__33 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr3_ref ((pmpWriteAddr w__32 w__33 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr3_ref : ( 64 words$word) M)) (\ (w__34 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__34))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp4cfg_ref) (\ (w__35 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 64 words$word) M) (\ (w__36 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr4_ref ((pmpWriteAddr w__35 w__36 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr4_ref : ( 64 words$word) M)) (\ (w__37 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__37))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp5cfg_ref) (\ (w__38 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 64 words$word) M) (\ (w__39 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr5_ref ((pmpWriteAddr w__38 w__39 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr5_ref : ( 64 words$word) M)) (\ (w__40 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__40))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp6cfg_ref) (\ (w__41 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 64 words$word) M) (\ (w__42 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr6_ref ((pmpWriteAddr w__41 w__42 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr6_ref : ( 64 words$word) M)) (\ (w__43 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__43))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp7cfg_ref) (\ (w__44 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 64 words$word) M) (\ (w__45 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr7_ref ((pmpWriteAddr w__44 w__45 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr7_ref : ( 64 words$word) M)) (\ (w__46 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__46))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp8cfg_ref) (\ (w__47 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 64 words$word) M) (\ (w__48 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr8_ref ((pmpWriteAddr w__47 w__48 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr8_ref : ( 64 words$word) M)) (\ (w__49 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__49))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp9cfg_ref) (\ (w__50 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 64 words$word) M) (\ (w__51 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr9_ref ((pmpWriteAddr w__50 w__51 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr9_ref : ( 64 words$word) M)) (\ (w__52 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__52))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp10cfg_ref) (\ (w__53 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 64 words$word) M) (\ (w__54 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr10_ref ((pmpWriteAddr w__53 w__54 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr10_ref : ( 64 words$word) M)) (\ (w__55 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__55))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp11cfg_ref) (\ (w__56 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 64 words$word) M) (\ (w__57 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr11_ref ((pmpWriteAddr w__56 w__57 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr11_ref : ( 64 words$word) M)) (\ (w__58 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__58))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp12cfg_ref) (\ (w__59 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 64 words$word) M) (\ (w__60 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr12_ref ((pmpWriteAddr w__59 w__60 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr12_ref : ( 64 words$word) M)) (\ (w__61 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__61))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp13cfg_ref) (\ (w__62 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 64 words$word) M) (\ (w__63 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr13_ref ((pmpWriteAddr w__62 w__63 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr13_ref : ( 64 words$word) M)) (\ (w__64 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__64))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp14cfg_ref) (\ (w__65 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 64 words$word) M) (\ (w__66 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr14_ref ((pmpWriteAddr w__65 w__66 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr14_ref : ( 64 words$word) M)) (\ (w__67 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__67))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmp15cfg_ref) (\ (w__68 : Pmpcfg_ent) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 64 words$word) M) (\ (w__69 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS pmpaddr15_ref ((pmpWriteAddr w__68 w__69 value : 64 words$word)))
+ (sail2_state_monad$read_regS pmpaddr15_ref : ( 64 words$word) M)) (\ (w__70 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__70))))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__71 : 64 words$word) . sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ mcycle_ref
+ ((update_subrange_vec_dec w__71 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$returnS (SOME value)))
+ else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__72 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS
+ minstret_ref
+ ((update_subrange_vec_dec w__72 (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) value : 64 words$word)))
+ (sail2_state_monad$write_regS minstret_written_ref T)) (sail2_state_monad$returnS (SOME value)))
+ else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS tselect_ref value)
+ (sail2_state_monad$read_regS tselect_ref : ( 64 words$word) M)) (\ (w__73 : 64 words$word) . sail2_state_monad$returnS (SOME w__73))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__74 : Mstatus) . sail2_state_monad$bindS
+ (legalize_sstatus w__74 value) (\ (w__75 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mstatus_ref w__75)
+ (sail2_state_monad$read_regS mstatus_ref)) (\ (w__76 : Mstatus) .
+ sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__76 : 64 words$word))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS sedeleg_ref) (\ (w__77 : Sedeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__77 value)))
+ (sail2_state_monad$read_regS sedeleg_ref)) (\ (w__78 : Sedeleg) .
+ sail2_state_monad$returnS (SOME ((get_Sedeleg_bits w__78 : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Sinterrupts_bits sideleg_ref value)
+ (sail2_state_monad$read_regS sideleg_ref)) (\ (w__79 : Sinterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Sinterrupts_bits w__79 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mie_ref) (\ (w__80 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__81 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_sie w__80 w__81 value) (\ (w__82 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mie_ref w__82)
+ (sail2_state_monad$read_regS mie_ref)) (\ (w__83 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__83 : 64 words$word)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_stvec value : ( 64 words$word) M) (\ (w__84 : 64 words$word) . sail2_state_monad$returnS (SOME w__84))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS scounteren_ref) (\ (w__85 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS scounteren_ref ((legalize_scounteren w__85 value)))
+ (sail2_state_monad$read_regS scounteren_ref)) (\ (w__86 : Counteren) .
+ sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__86 : 32 words$word)) : 64 words$word)))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS sscratch_ref value)
+ (sail2_state_monad$read_regS sscratch_ref : ( 64 words$word) M)) (\ (w__87 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__87))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS
+ (set_xret_target Supervisor value : ( 64 words$word) M) (\ (w__88 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__88))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (set_Mcause_bits scause_ref value)
+ (sail2_state_monad$read_regS scause_ref)) (\ (w__89 : Mcause) .
+ sail2_state_monad$returnS (SOME ((get_Mcause_bits w__89 : 64 words$word))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS stval_ref value)
+ (sail2_state_monad$read_regS stval_ref : ( 64 words$word) M)) (\ (w__90 : 64 words$word) . sail2_state_monad$returnS (SOME w__90))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mip_ref) (\ (w__91 : Minterrupts) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mideleg_ref) (\ (w__92 : Minterrupts) . sail2_state_monad$bindS
+ (legalize_sip w__91 w__92 value) (\ (w__93 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS mip_ref w__93)
+ (sail2_state_monad$read_regS mip_ref)) (\ (w__94 : Minterrupts) .
+ sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__94 : 64 words$word)))))))
+ else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS
+ (cur_Architecture () ) (\ (w__95 : Architecture) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__96 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS satp_ref ((legalize_satp w__95 w__96 value : 64 words$word)))
+ (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M)) (\ (w__97 : 64 words$word) . sail2_state_monad$returnS (SOME w__97))))
+ else sail2_state_monad$returnS NONE
+ ) (\ (res : xlenbits option) .
+ (case res of
+ SOME (v) =>
+ sail2_state_monad$returnS (if ((get_config_print_reg () )) then
+ print_dbg
+ ((STRCAT "CSR "
+ ((STRCAT ((csr_name csr))
+ ((STRCAT " <- "
+ ((STRCAT ((string_of_bits v))
+ ((STRCAT " (input: "
+ ((STRCAT ((string_of_bits value)) ")"))))))))))))
+ else () )
+ | NONE => sail2_state_monad$bindS
+ (ext_write_CSR csr value) (\ (w__143 : bool) .
+ sail2_state_monad$returnS (if w__143 then ()
+ else print_bits0 "unhandled write to CSR " csr))
+ ))))`;
+
+
+(*val maybe_i_forwards : bool -> string*)
+
+val _ = Define `
+ ((maybe_i_forwards:bool -> string) arg_= ((case arg_ of T => "i" | F => "" )))`;
+
+
+(*val maybe_i_backwards : string -> M bool*)
+
+val _ = Define `
+ ((maybe_i_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then sail2_state_monad$returnS T
+ else if (((p0_ = ""))) then sail2_state_monad$returnS F
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val maybe_i_forwards_matches : bool -> bool*)
+
+val _ = Define `
+ ((maybe_i_forwards_matches:bool -> bool) arg_=
+ ((case arg_ of T => T | F => T )))`;
+
+
+(*val maybe_i_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((maybe_i_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "i"))) then T
+ else if (((p0_ = ""))) then T
+ else F))`;
+
+
+(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*)
+
+(*val _s797_ : string -> maybe string*)
+
+val _ = Define `
+ ((s797_:string ->(string)option) s798_0=
+ (let s799_0 = s798_0 in
+ if ((string_startswith s799_0 "")) then
+ (case ((string_drop s799_0 ((string_length "")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s793_ : string -> maybe string*)
+
+val _ = Define `
+ ((s793_:string ->(string)option) s794_0=
+ (let s795_0 = s794_0 in
+ if ((string_startswith s795_0 "i")) then
+ (case ((string_drop s795_0 ((string_length "i")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((maybe_i_matches_prefix:string ->(bool#int)option) arg_=
+ (let s796_0 = arg_ in
+ if ((case ((s793_ s796_0)) of SOME (s_) => T | _ => F )) then
+ (case s793_ s796_0 of
+ (SOME (s_)) =>
+ SOME (T, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s797_ s796_0)) of SOME (s_) => T | _ => F )) then
+ (case s797_ s796_0 of
+ (SOME (s_)) =>
+ SOME (F, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val csr_mnemonic_forwards : csrop -> string*)
+
+val _ = Define `
+ ((csr_mnemonic_forwards:csrop -> string) arg_=
+ ((case arg_ of CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" )))`;
+
+
+(*val csr_mnemonic_backwards : string -> M csrop*)
+
+val _ = Define `
+ ((csr_mnemonic_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((csrop),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "csrrw"))) then sail2_state_monad$returnS CSRRW
+ else if (((p0_ = "csrrs"))) then sail2_state_monad$returnS CSRRS
+ else if (((p0_ = "csrrc"))) then sail2_state_monad$returnS CSRRC
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val csr_mnemonic_forwards_matches : csrop -> bool*)
+
+val _ = Define `
+ ((csr_mnemonic_forwards_matches:csrop -> bool) arg_=
+ ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`;
+
+
+(*val csr_mnemonic_backwards_matches : string -> bool*)
+
+val _ = Define `
+ ((csr_mnemonic_backwards_matches:string -> bool) arg_=
+ (let p0_ = arg_ in
+ if (((p0_ = "csrrw"))) then T
+ else if (((p0_ = "csrrs"))) then T
+ else if (((p0_ = "csrrc"))) then T
+ else F))`;
+
+
+(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*)
+
+(*val _s809_ : string -> maybe string*)
+
+val _ = Define `
+ ((s809_:string ->(string)option) s810_0=
+ (let s811_0 = s810_0 in
+ if ((string_startswith s811_0 "csrrc")) then
+ (case ((string_drop s811_0 ((string_length "csrrc")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s805_ : string -> maybe string*)
+
+val _ = Define `
+ ((s805_:string ->(string)option) s806_0=
+ (let s807_0 = s806_0 in
+ if ((string_startswith s807_0 "csrrs")) then
+ (case ((string_drop s807_0 ((string_length "csrrs")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s801_ : string -> maybe string*)
+
+val _ = Define `
+ ((s801_:string ->(string)option) s802_0=
+ (let s803_0 = s802_0 in
+ if ((string_startswith s803_0 "csrrw")) then
+ (case ((string_drop s803_0 ((string_length "csrrw")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((csr_mnemonic_matches_prefix:string ->(csrop#int)option) arg_=
+ (let s804_0 = arg_ in
+ if ((case ((s801_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s801_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRW, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s805_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s805_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRS, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s809_ s804_0)) of SOME (s_) => T | _ => F )) then
+ (case s809_ s804_0 of
+ (SOME (s_)) =>
+ SOME (CSRRC, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+(*val encdec_forwards : ast -> M (mword ty32)*)
+
+val _ = Define `
+ ((encdec_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rd ((encdec_uop_forwards op : 7 words$word)) : 12 words$word))
+ : 32 words$word))
+ | RISCV_JAL ((v__2, rd)) =>
+ if (((((subrange_vec_dec v__2 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__2 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_8 : 1 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__2 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__2 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in
+ let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm_19
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9
+ ((concat_vec imm_8
+ ((concat_vec imm_7_0
+ ((concat_vec rd (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 20 words$word))
+ : 21 words$word))
+ : 25 words$word))
+ : 31 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RISCV_JALR ((imm, rs1, rd)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | BTYPE ((v__4, rs2, rs1, op)) =>
+ if (((((subrange_vec_dec v__4 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__4 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__4 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__4 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in
+ let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__4 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in
+ let (imm5_0 : 1 bits) = ((subrange_vec_dec v__4 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm7_6
+ ((concat_vec imm7_5_0
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec ((encdec_bop_forwards op : 3 words$word))
+ ((concat_vec imm5_4_1
+ ((concat_vec imm5_0
+ (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)
+ : 8 words$word))
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 31 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | ITYPE ((imm, rs1, rd, op)) =>
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((encdec_iop_forwards op : 3 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 26 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, F, F)) =>
+ if (((((((word_width_bytes size1)) < (( 8 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 8 : int):ii))))))))) then
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_unsigned : 1 words$word))
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | STORE ((v__6, rs2, rs1, size1, F, F)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__6 (( 11 : int):ii) (( 5 : int):ii) : 7 words$word)) in
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__6 (( 11 : int):ii) (( 5 : int):ii) : 7 words$word)) in
+ let (imm5 : 5 bits) = ((subrange_vec_dec v__6 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec imm7
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec imm5
+ (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | FENCE ((pred, succ)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 24 words$word))
+ : 28 words$word))
+ : 32 words$word))
+ | FENCE_TSO ((pred, succ)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0;B0] : 4 words$word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 24 words$word))
+ : 28 words$word))
+ : 32 words$word))
+ | FENCEI (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | ECALL (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | MRET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | SRET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | EBREAK (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | WFI (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | SFENCE_VMA ((rs1, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | LOADRES ((aq, rl, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | AMO ((op, aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then
+ sail2_state_monad$returnS ((concat_vec ((encdec_amoop_forwards op : 5 words$word))
+ ((concat_vec ((bool_bits_forwards aq : 1 words$word))
+ ((concat_vec ((bool_bits_forwards rl : 1 words$word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec ((size_bits_forwards size1 : 2 words$word))
+ ((concat_vec rd
+ (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 26 words$word))
+ : 27 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec
+ ((encdec_mul_op_forwards (high, signed1, signed2) : 3 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | DIV0 ((rs2, rs1, rd, s)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | REM ((rs2, rs1, rd, s)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec ((bool_not_bits_forwards s : 1 words$word))
+ ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 13 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ sail2_state_monad$returnS ((concat_vec csr
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_imm : 1 words$word))
+ ((concat_vec ((encdec_csrop_forwards op : 2 words$word))
+ ((concat_vec rd (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 14 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 32 words$word))
+ | URET (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)
+ : 12 words$word))
+ : 15 words$word))
+ : 20 words$word))
+ : 25 words$word))
+ : 32 words$word))
+ | ILLEGAL (s) => sail2_state_monad$returnS s
+ | _ => sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val encdec_backwards : mword ty32 -> M ast*)
+
+val _ = Define `
+ ((encdec_backwards:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let v__7 = arg_ in
+ let (mappingpatterns_23_0 : 7 words$word) = ((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_uop_backwards_matches mappingpatterns_23_0)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_23_0)) then sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_23_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__1 : bool) .
+ if w__1 then
+ let (imm : 20 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 20 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in
+ let (mappingpatterns_23_0 : 7 words$word) = ((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_23_0) (\ op . sail2_state_monad$returnS (UTYPE (imm, rd, op)))
+ else if (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm_8 : 1 bits) = ((subrange_vec_dec v__7 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in
+ let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in
+ let (imm_19 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__7 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in
+ let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 21 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (RISCV_JAL ((concat_vec imm_19
+ ((concat_vec imm_7_0
+ ((concat_vec imm_8
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9 (vec_of_bits [B0] : 1 words$word)
+ : 5 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 20 words$word))
+ : 21 words$word),
+ rd))
+ else if ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ sail2_state_monad$returnS (RISCV_JALR (imm, rs1, rd))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_24_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_bop_backwards_matches mappingpatterns_24_0)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_24_0)) then sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_24_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__4 : bool) .
+ if w__4 then
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (imm7_6 : 1 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in
+ let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__7 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in
+ let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in
+ let (imm5_0 : 1 bits) = ((subrange_vec_dec v__7 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_24_0 : 3 words$word) = ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_24_0) (\ op .
+ sail2_state_monad$returnS (BTYPE ((concat_vec imm7_6
+ ((concat_vec imm5_0
+ ((concat_vec imm7_5_0
+ ((concat_vec imm5_4_1 (vec_of_bits [B0] : 1 words$word) : 5 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word),
+ rs2,
+ rs1,
+ op)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_25_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_iop_backwards_matches mappingpatterns_25_0)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_25_0)) then sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_25_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__7 : bool) .
+ if w__7 then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_25_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_25_0) (\ op . sail2_state_monad$returnS (ITYPE (imm, rs1, rd, op)))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SLLI))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SRLI))
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 6 words$word) = ((subrange_vec_dec v__7 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, RISCV_SRAI))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_ADD))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLT))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLTU))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_AND))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_OR))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_XOR))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SLL))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SRL))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SUB))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, RISCV_SRA))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_27_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_26_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_27_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_27_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_27_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_26_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_26_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_26_0) (\ is_unsigned .
+ sail2_state_monad$returnS (((((((word_width_bytes size1)) < (( 8 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 8 : int):ii))))))))))
+ else sail2_state_monad$returnS F)) (\ (w__9 : bool) .
+ sail2_state_monad$returnS w__9))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__12 : bool) .
+ if w__12 then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_27_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_26_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_27_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_26_0) (\ is_unsigned .
+ sail2_state_monad$returnS (LOAD (imm, rs1, rd, is_unsigned, size1, F, F))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_28_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_28_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_28_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_28_0) (\ size1 .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__15 :
+ bool) .
+ if w__15 then
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (imm7 : 7 bits) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in
+ let (imm5 : 5 bits) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_28_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_28_0) (\ size1 .
+ sail2_state_monad$returnS (STORE ((concat_vec imm7 imm5 : 12 words$word), rs2, rs1, size1, F, F)))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm : 12 words$word) = ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ sail2_state_monad$returnS (ADDIW (imm, rs1, rd))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SLLI))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SRLI))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, RISCV_SRAI))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_ADDW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SUBW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SLLW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SRLW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, RISCV_SRAW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SLLIW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SRLIW))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ let (shamt : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, RISCV_SRAIW))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__7 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ let (succ : 4 words$word) = ((subrange_vec_dec v__7 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in
+ let (pred : 4 words$word) = ((subrange_vec_dec v__7 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (FENCE (pred, succ))
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__7 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ let (succ : 4 words$word) = ((subrange_vec_dec v__7 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in
+ let (pred : 4 words$word) = ((subrange_vec_dec v__7 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS (FENCE_TSO (pred, succ))
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (FENCEI () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (ECALL () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (MRET () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (SRET () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (EBREAK () )
+ else if (((v__7 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS (WFI () )
+ else if ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__7 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word)))))))
+ then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (SFENCE_VMA (rs1, rs2))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_31_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_30_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_29_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_31_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_31_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_31_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_30_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_30_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_30_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_29_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_29_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_29_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__17 : bool) .
+ sail2_state_monad$returnS w__17))
+ else sail2_state_monad$returnS F)) (\ (w__19 : bool) .
+ sail2_state_monad$returnS w__19))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))))) (\ (w__22 :
+ bool) .
+ if w__22 then
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_31_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_30_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_29_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_31_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_30_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_29_0) (\ aq .
+ sail2_state_monad$returnS (LOADRES (aq, rl, rs1, size1, rd)))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_34_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_33_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_32_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_34_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_34_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_34_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_33_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_33_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_33_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_32_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_32_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_32_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__24 : bool) .
+ sail2_state_monad$returnS w__24))
+ else sail2_state_monad$returnS F)) (\ (w__26 : bool) .
+ sail2_state_monad$returnS w__26))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))))) (\ (w__29 :
+ bool) .
+ if w__29 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_34_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_33_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_32_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_34_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_33_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_32_0) (\ aq .
+ sail2_state_monad$returnS (STORECON (aq, rl, rs2, rs1, size1, rd)))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_38_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_37_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_36_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_38_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_38_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_38_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_37_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_37_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_37_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_36_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_36_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_36_0) (\ aq . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_amoop_backwards_matches mappingpatterns_35_0)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_35_0)) then sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_35_0) (\ op .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__31 : bool) .
+ sail2_state_monad$returnS w__31))
+ else sail2_state_monad$returnS F)) (\ (w__33 : bool) .
+ sail2_state_monad$returnS w__33))
+ else sail2_state_monad$returnS F)) (\ (w__35 : bool) .
+ sail2_state_monad$returnS w__35))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))) (\ (w__38 :
+ bool) .
+ if w__38 then
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_38_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_37_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_36_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_35_0 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_38_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_37_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_36_0) (\ aq . sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_35_0) (\ op .
+ sail2_state_monad$returnS (AMO (op, aq, rl, rs2, rs1, size1, rd))))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_39_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_mul_op_backwards_matches mappingpatterns_39_0)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_39_0)) then sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_39_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__41 :
+ bool) .
+ if w__41 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_39_0 : 3 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_39_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS (MUL (rs2, rs1, rd, high, signed1, signed2)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_40_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_40_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_40_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_40_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__44 :
+ bool) .
+ if w__44 then
+ let (rs2 : 5 words$word) = ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) = ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_40_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_40_0) (\ s .
+ sail2_state_monad$returnS (DIV0 (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_41_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_41_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_41_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_41_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__47 :
+ bool) .
+ if w__47 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_41_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_41_0) (\ s .
+ sail2_state_monad$returnS (REM (rs2, rs1, rd, s)))
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))))
+ then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) = ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS (MULW (rs2, rs1, rd))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_42_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_42_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_42_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_42_0) (\ s .
+ sail2_state_monad$returnS ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__50 :
+ bool) .
+ if w__50 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_42_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_42_0) (\ s .
+ sail2_state_monad$returnS (DIVW (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_43_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_43_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_43_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_43_0) (\ s .
+ sail2_state_monad$returnS ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__7 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__7 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__53 :
+ bool) .
+ if w__53 then
+ let (rs2 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_43_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_43_0) (\ s .
+ sail2_state_monad$returnS (REMW (rs2, rs1, rd, s)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_45_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_44_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_csrop_backwards_matches mappingpatterns_45_0)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_45_0)) then sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_45_0) (\ op . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_44_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_44_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_44_0) (\ is_imm .
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__55 : bool) .
+ sail2_state_monad$returnS w__55))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__7 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__58 :
+ bool) .
+ if w__58 then
+ let (csr : 12 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (rs1 : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in
+ let (rd : 5 words$word) =
+ ((subrange_vec_dec v__7 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (csr : 12 words$word) =
+ ((subrange_vec_dec v__7 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in
+ let (mappingpatterns_45_0 : 2 words$word) =
+ ((subrange_vec_dec v__7 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_44_0 : 1 words$word) =
+ ((subrange_vec_dec v__7 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_45_0) (\ op . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_44_0) (\ is_imm .
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, is_imm, op))))
+ else
+ sail2_state_monad$returnS (if (((v__7 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+ B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ URET ()
+ else ILLEGAL v__7)))))))))))))))))`;
+
+
+(*val encdec_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((encdec_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => T
+ | RISCV_JAL ((v__220, rd)) =>
+ if (((((subrange_vec_dec v__220 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ T
+ else F
+ | RISCV_JALR ((imm, rs1, rd)) => T
+ | BTYPE ((v__222, rs2, rs1, op)) =>
+ if (((((subrange_vec_dec v__222 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then
+ T
+ else F
+ | ITYPE ((imm, rs1, rd, op)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI)) => T
+ | SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_ADD)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLT)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLTU)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_AND)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_OR)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_XOR)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SLL)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SRL)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SUB)) => T
+ | RTYPE ((rs2, rs1, rd, RISCV_SRA)) => T
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, F, F)) =>
+ if (((((((word_width_bytes size1)) < (( 8 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 8 : int):ii))))))))) then
+ T
+ else F
+ | STORE ((v__224, rs2, rs1, size1, F, F)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then T else F
+ | ADDIW ((imm, rs1, rd)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SLLI)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRLI)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, RISCV_SRAI)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_ADDW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SUBW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SLLW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRLW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, RISCV_SRAW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | FENCE ((pred, succ)) => T
+ | FENCE_TSO ((pred, succ)) => T
+ | FENCEI (() ) => T
+ | ECALL (() ) => T
+ | MRET (() ) => T
+ | SRET (() ) => T
+ | EBREAK (() ) => T
+ | WFI (() ) => T
+ | SFENCE_VMA ((rs1, rs2)) => T
+ | LOADRES ((aq, rl, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then T else F
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then T else F
+ | AMO ((op, aq, rl, rs2, rs1, size1, rd)) =>
+ if ((((word_width_bytes size1)) <= (( 8 : int):ii))) then T else F
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => T
+ | DIV0 ((rs2, rs1, rd, s)) => T
+ | REM ((rs2, rs1, rd, s)) => T
+ | MULW ((rs2, rs1, rd)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | DIVW ((rs2, rs1, rd, s)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | REMW ((rs2, rs1, rd, s)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | CSR ((csr, rs1, rd, is_imm, op)) => T
+ | URET (() ) => T
+ | ILLEGAL (s) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_backwards_matches : mword ty32 -> M bool*)
+
+val _ = Define `
+ ((encdec_backwards_matches:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let v__225 = arg_ in
+ let (mappingpatterns_0_0 : 7 words$word) = ((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_uop_backwards_matches mappingpatterns_0_0)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_0_0)) then sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_0_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__1 : bool) .
+ if w__1 then
+ let (mappingpatterns_0_0 : 7 words$word) = ((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in sail2_state_monad$bindS
+ (encdec_uop_backwards mappingpatterns_0_0) (\ op . sail2_state_monad$returnS T)
+ else if (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_1_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_bop_backwards_matches mappingpatterns_1_0)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_1_0)) then sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_1_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__4 : bool) .
+ if w__4 then
+ let (mappingpatterns_1_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_bop_backwards mappingpatterns_1_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_2_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_iop_backwards_matches mappingpatterns_2_0)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_2_0)) then sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_2_0) (\ op . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__7 : bool) .
+ if w__7 then
+ let (mappingpatterns_2_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_iop_backwards mappingpatterns_2_0) (\ op . sail2_state_monad$returnS T)
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((let (shamt : 6 words$word) = ((subrange_vec_dec v__225 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in
+ (((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((((bit_to_bool ((access_vec_dec shamt (( 5 : int):ii))))) = F))))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_4_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_3_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_4_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_4_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_4_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_3_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_3_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_3_0) (\ is_unsigned .
+ sail2_state_monad$returnS (((((((word_width_bytes size1)) < (( 8 : int):ii))) \/ (((((~ is_unsigned)) /\ ((((word_width_bytes size1)) <= (( 8 : int):ii))))))))))
+ else sail2_state_monad$returnS F)) (\ (w__9 : bool) .
+ sail2_state_monad$returnS w__9))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__12 : bool) .
+ if w__12 then
+ let (mappingpatterns_4_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_3_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_4_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_3_0) (\ is_unsigned . sail2_state_monad$returnS T))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_5_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_5_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_5_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_5_0) (\ size1 .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__15 :
+ bool) .
+ if w__15 then
+ let (mappingpatterns_5_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_5_0) (\ size1 . sail2_state_monad$returnS T)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__225 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__225 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 20 words$word))))))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+ B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if (((v__225 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+ B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ sail2_state_monad$returnS T
+ else if ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__225 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word)))))))
+ then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_8_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_7_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_6_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_8_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_8_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_8_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_7_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_7_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_7_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_6_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_6_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_6_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__17 : bool) .
+ sail2_state_monad$returnS w__17))
+ else sail2_state_monad$returnS F)) (\ (w__19 : bool) .
+ sail2_state_monad$returnS w__19))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))))) (\ (w__22 :
+ bool) .
+ if w__22 then
+ let (mappingpatterns_8_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_7_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_6_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_8_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_7_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_6_0) (\ aq . sail2_state_monad$returnS T)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_9_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_11_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_10_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_11_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_11_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_11_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_10_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_10_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_10_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_9_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_9_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_9_0) (\ aq .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__24 : bool) .
+ sail2_state_monad$returnS w__24))
+ else sail2_state_monad$returnS F)) (\ (w__26 : bool) .
+ sail2_state_monad$returnS w__26))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))))) (\ (w__29 :
+ bool) .
+ if w__29 then
+ let (mappingpatterns_9_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_11_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_10_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_11_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_10_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_9_0) (\ aq . sail2_state_monad$returnS T)))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_15_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_14_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_13_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((size_bits_backwards_matches mappingpatterns_15_0)))
+ (if ((size_bits_backwards_matches mappingpatterns_15_0)) then sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_15_0) (\ size1 . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_14_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_14_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_14_0) (\ rl . sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_13_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_13_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_13_0) (\ aq . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_amoop_backwards_matches mappingpatterns_12_0)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_12_0)) then sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_12_0) (\ op .
+ sail2_state_monad$returnS ((((word_width_bytes size1)) <= (( 8 : int):ii))))
+ else sail2_state_monad$returnS F)) (\ (w__31 : bool) .
+ sail2_state_monad$returnS w__31))
+ else sail2_state_monad$returnS F)) (\ (w__33 : bool) .
+ sail2_state_monad$returnS w__33))
+ else sail2_state_monad$returnS F)) (\ (w__35 : bool) .
+ sail2_state_monad$returnS w__35))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))) (\ (w__38 :
+ bool) .
+ if w__38 then
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in
+ let (mappingpatterns_15_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_14_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_13_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in
+ let (mappingpatterns_12_0 : 5 words$word) =
+ ((subrange_vec_dec v__225 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in sail2_state_monad$bindS
+ (size_bits_backwards mappingpatterns_15_0) (\ size1 . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_14_0) (\ rl . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_13_0) (\ aq . sail2_state_monad$bindS
+ (encdec_amoop_backwards mappingpatterns_12_0) (\ op . sail2_state_monad$returnS T))))
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_16_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((encdec_mul_op_backwards_matches mappingpatterns_16_0)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_16_0)) then sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_16_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))))) (\ (w__41 :
+ bool) .
+ if w__41 then
+ let (mappingpatterns_16_0 : 3 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in sail2_state_monad$bindS
+ (encdec_mul_op_backwards mappingpatterns_16_0) (\ varstup . let (high, signed1, signed2) = varstup in
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_17_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_17_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_17_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_17_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__44 :
+ bool) .
+ if w__44 then
+ let (mappingpatterns_17_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_17_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_18_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_18_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_18_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_18_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__47 :
+ bool) .
+ if w__47 then
+ let (mappingpatterns_18_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_18_0) (\ s . sail2_state_monad$returnS T)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 12 : int):ii)
+ : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))))
+ then
+ sail2_state_monad$returnS T
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_19_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_19_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_19_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_19_0) (\ s .
+ sail2_state_monad$returnS ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__50 :
+ bool) .
+ if w__50 then
+ let (mappingpatterns_19_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_19_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_20_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_not_bits_backwards_matches mappingpatterns_20_0)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_20_0)) then sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_20_0) (\ s .
+ sail2_state_monad$returnS ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS ((((((((subrange_vec_dec v__225 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__225 (( 14 : int):ii) (( 13 : int):ii)
+ : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii)
+ : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))))) (\ (w__53 :
+ bool) .
+ if w__53 then
+ let (mappingpatterns_20_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (bool_not_bits_backwards mappingpatterns_20_0) (\ s . sail2_state_monad$returnS T)
+ else sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (let (mappingpatterns_22_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_21_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in
+ sail2_state$and_boolS
+ (sail2_state_monad$returnS ((encdec_csrop_backwards_matches mappingpatterns_22_0)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_22_0)) then sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_22_0) (\ op . sail2_state_monad$bindS
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS ((bool_bits_backwards_matches mappingpatterns_21_0)))
+ (if ((bool_bits_backwards_matches mappingpatterns_21_0)) then sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_21_0) (\ is_imm .
+ sail2_state_monad$returnS T)
+ else sail2_state_monad$returnS F)) (\ (w__55 : bool) .
+ sail2_state_monad$returnS w__55))
+ else sail2_state_monad$returnS F))
+ (sail2_state_monad$returnS (((((subrange_vec_dec v__225 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) (\ (w__58 :
+ bool) .
+ if w__58 then
+ let (mappingpatterns_22_0 : 2 words$word) =
+ ((subrange_vec_dec v__225 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in
+ let (mappingpatterns_21_0 : 1 words$word) =
+ ((subrange_vec_dec v__225 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in sail2_state_monad$bindS
+ (encdec_csrop_backwards mappingpatterns_22_0) (\ op . sail2_state_monad$bindS
+ (bool_bits_backwards mappingpatterns_21_0) (\ is_imm .
+ sail2_state_monad$returnS T))
+ else
+ sail2_state_monad$returnS (if (((v__225 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;
+ B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;
+ B1;B1;B0;B0;B1;B1]
+ : 32 words$word)))) then
+ T
+ else T)))))))))))))))))`;
+
+
+(*val encdec_compressed_forwards : ast -> M (mword ty16)*)
+
+val _ = Define `
+ ((encdec_compressed_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ C_NOP (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B0;B1] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_ADDI4SPN ((rd, v__438)) =>
+ if (let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__438 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__438 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__438 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) then
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__438 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__438 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__438 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__438 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nz54
+ ((concat_vec nz96
+ ((concat_vec nz2
+ ((concat_vec nz3
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 11 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LW ((v__439, rs1, rd)) =>
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__439 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__439 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__439 (( 3 : int):ii) (( 1 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__439 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_LD ((v__440, rs1, rd)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__440 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__440 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__440 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rd (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SW ((v__441, rs1, rs2)) =>
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__441 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__441 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__441 (( 3 : int):ii) (( 1 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__441 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rs2 (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SD ((v__442, rs1, rs2)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__442 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__442 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__442 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B0;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDI ((v__443, rsd)) =>
+ if (let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__443 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) then
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__443 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__443 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nzi5
+ ((concat_vec rsd
+ ((concat_vec nzi40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JAL (v__444) =>
+ if ((((( 64 : int):ii) = (( 32 : int):ii)))) then
+ let (i11 : 1 bits) = ((subrange_vec_dec v__444 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i98 : 2 bits) = ((subrange_vec_dec v__444 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__444 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__444 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__444 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__444 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__444 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__444 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__444 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 8 words$word))
+ : 9 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDIW ((v__445, rsd)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))))
+ then
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__445 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__445 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__445 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word)
+ ((concat_vec imm5
+ ((concat_vec rsd
+ ((concat_vec imm40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LI ((v__446, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__446 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__446 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__446 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec imm5
+ ((concat_vec rd
+ ((concat_vec imm40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDI16SP (v__447) =>
+ if (let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__447 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__447 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__447 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__447 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__447 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__447 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__447 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__447 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__447 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec nzi9
+ ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)
+ ((concat_vec nzi4
+ ((concat_vec nzi6
+ ((concat_vec nzi87
+ ((concat_vec nzi5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LUI ((v__448, rd)) =>
+ if (let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__448 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) then
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__448 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__448 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec imm17
+ ((concat_vec rd
+ ((concat_vec imm1612 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SRLI ((v__449, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__449 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__449 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__449 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SRAI ((v__450, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__450 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__450 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__450 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ANDI ((v__451, rsd)) =>
+ let (i5 : 1 bits) = ((subrange_vec_dec v__451 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__451 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i40 : 5 bits) = ((subrange_vec_dec v__451 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec i5
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec i40 (vec_of_bits [B0;B1] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SUB ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_XOR ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_OR ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_AND ((rsd, rs2)) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B1;B1] : 2 words$word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0;B1] : 2 words$word)
+ ((concat_vec rs2 (vec_of_bits [B0;B1] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_J (v__452) =>
+ let (i11 : 1 bits) = ((subrange_vec_dec v__452 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i98 : 2 bits) = ((subrange_vec_dec v__452 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__452 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__452 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__452 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__452 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__452 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__452 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__452 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word)
+ : 3 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 8 words$word))
+ : 9 words$word))
+ : 11 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_BEQZ ((v__453, rs)) =>
+ let (i8 : 1 bits) = ((subrange_vec_dec v__453 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__453 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__453 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__453 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__453 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__453 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word) : 3 words$word))
+ : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_BNEZ ((v__454, rs)) =>
+ let (i8 : 1 bits) = ((subrange_vec_dec v__454 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__454 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__454 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__454 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__454 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__454 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0;B1] : 2 words$word) : 3 words$word))
+ : 5 words$word))
+ : 7 words$word))
+ : 10 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SLLI ((v__455, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__455 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word)))))))))))))
+ then
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__455 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__455 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word)
+ ((concat_vec nzui5
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LWSP ((v__456, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__456 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__456 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__456 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in
+ let (ui42 : 3 bits) = ((subrange_vec_dec v__456 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui42
+ ((concat_vec ui76 (vec_of_bits [B1;B0] : 2 words$word) : 4 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_LDSP ((v__457, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))))
+ then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__457 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__457 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__457 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (ui43 : 2 bits) = ((subrange_vec_dec v__457 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui43
+ ((concat_vec ui86 (vec_of_bits [B1;B0] : 2 words$word) : 5 words$word))
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_SWSP ((v__458, rs2)) =>
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__458 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__458 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) in
+ let (ui52 : 4 bits) = ((subrange_vec_dec v__458 (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word)
+ ((concat_vec ui52
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 9 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_SDSP ((v__459, rs2)) =>
+ if ((((( 64 : int):ii) = (( 64 : int):ii)))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__459 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__459 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__459 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word)
+ ((concat_vec ui53
+ ((concat_vec ui86
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 10 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B0] : 1 words$word)
+ ((concat_vec rd
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_EBREAK (() ) =>
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)
+ (vec_of_bits [B1;B0] : 2 words$word)
+ : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$returnS ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word)
+ ((concat_vec (vec_of_bits [B1] : 1 words$word)
+ ((concat_vec rsd
+ ((concat_vec rs2 (vec_of_bits [B1;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word))
+ : 13 words$word))
+ : 16 words$word))
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ | C_ILLEGAL (s) => sail2_state_monad$returnS s
+ | _ => sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )
+ )))`;
+
+
+(*val encdec_compressed_backwards : mword ty16 -> ast*)
+
+val _ = Define `
+ ((encdec_compressed_backwards:(16)words$word -> ast) arg_=
+ (let v__460 = arg_ in
+ if (((v__460 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))
+ then
+ C_NOP ()
+ else if ((((let (nz96 : 4 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ C_ADDI4SPN (rd,
+ (concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word))
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_LW ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word), rs1, rd)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rd : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_LD ((concat_vec ui76 ui53 : 5 words$word), rs1, rd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ let (ui6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (ui2 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (rs1 : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ C_SW ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word), rs1, rs2)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs2 : 3 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (rs1 : 3 bits) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ C_SD ((concat_vec ui76 ui53 : 5 words$word), rs1, rs2)
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADDI ((concat_vec nzi5 nzi40 : 6 words$word), rsd)
+ else if (((((((( 64 : int):ii) = (( 32 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (i98 : 2 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__460 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in
+ C_JAL ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 9 words$word))
+ : 10 words$word))
+ : 11 words$word))
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADDIW ((concat_vec imm5 imm40 : 6 words$word), rsd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_LI ((concat_vec imm5 imm40 : 6 words$word), rd)
+ else if ((((let (nzi9 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regidx_to_regno ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ C_ADDI16SP ((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word))
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_LUI ((concat_vec imm17 imm1612 : 6 words$word), rd)
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SRLI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SRAI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ANDI ((concat_vec i5 i40 : 6 words$word), rsd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_SUB (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_XOR (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_OR (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_AND (rsd, rs2)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_SUBW (rsd, rs2)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ let (rsd : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (rs2 : cregidx) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ C_ADDW (rsd, rs2)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (i98 : 2 bits) = ((subrange_vec_dec v__460 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in
+ let (i7 : 1 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ let (i6 : 1 bits) = ((subrange_vec_dec v__460 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i4 : 1 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in
+ let (i31 : 3 bits) = ((subrange_vec_dec v__460 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in
+ let (i11 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i10 : 1 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in
+ C_J ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word))
+ : 6 words$word))
+ : 7 words$word))
+ : 9 words$word))
+ : 10 words$word))
+ : 11 words$word))
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (rs : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ C_BEQZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word))
+ : 7 words$word))
+ : 8 words$word),
+ rs)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ let (rs : cregidx) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (i8 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (i76 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (i5 : 1 bits) = ((subrange_vec_dec v__460 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (i43 : 2 bits) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in
+ let (i21 : 2 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ C_BNEZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word))
+ : 7 words$word))
+ : 8 words$word),
+ rs)
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word))))))))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SLLI ((concat_vec nzui5 nzui40 : 6 words$word), rsd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (ui42 : 3 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 4 : int):ii) : 3 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_LWSP ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word), rd)
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__460 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in
+ let (ui5 : 1 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (ui43 : 2 bits) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_LDSP ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word), rd)
+ else if ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ let (ui76 : 2 bits) = ((subrange_vec_dec v__460 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in
+ let (ui52 : 4 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SWSP ((concat_vec ui76 ui52 : 6 words$word), rs2)
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (ui86 : 3 bits) = ((subrange_vec_dec v__460 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in
+ let (ui53 : 3 bits) = ((subrange_vec_dec v__460 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_SDSP ((concat_vec ui86 ui53 : 6 words$word), rs2)
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_JR rs1
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ let (rs1 : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_JALR rs1
+ else if ((((let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ C_MV (rd, rs2)
+ else if (((v__460 = (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 16 words$word)))) then
+ C_EBREAK ()
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__460 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__460 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ let (rsd : regidx) = ((subrange_vec_dec v__460 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__460 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ C_ADD (rsd, rs2)
+ else C_ILLEGAL v__460))`;
+
+
+(*val encdec_compressed_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((encdec_compressed_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ C_NOP (() ) => T
+ | C_ADDI4SPN ((rd, v__596)) =>
+ if (let (nz96 : 4 bits) = ((subrange_vec_dec v__596 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz96 : 4 bits) = ((subrange_vec_dec v__596 (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__596 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__596 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__596 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) then
+ T
+ else F
+ | C_LW ((v__597, rs1, rd)) => T
+ | C_LD ((v__598, rs1, rd)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_SW ((v__599, rs1, rs2)) => T
+ | C_SD ((v__600, rs1, rs2)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_ADDI ((v__601, rsd)) =>
+ if (let (nzi5 : 1 bits) = ((subrange_vec_dec v__601 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__601 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__601 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) then
+ T
+ else F
+ | C_JAL (v__602) => if ((((( 64 : int):ii) = (( 32 : int):ii)))) then T else F
+ | C_ADDIW ((v__603, rsd)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))))
+ then
+ T
+ else F
+ | C_LI ((v__604, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_ADDI16SP (v__605) =>
+ if (let (nzi9 : 1 bits) = ((subrange_vec_dec v__605 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi9 : 1 bits) = ((subrange_vec_dec v__605 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__605 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__605 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__605 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__605 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_LUI ((v__606, rd)) =>
+ if (let (imm17 : 1 bits) = ((subrange_vec_dec v__606 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__606 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__606 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) then
+ T
+ else F
+ | C_SRLI ((v__607, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__607 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__607 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__607 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_SRAI ((v__608, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__608 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__608 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__608 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) then
+ T
+ else F
+ | C_ANDI ((v__609, rsd)) => T
+ | C_SUB ((rsd, rs2)) => T
+ | C_XOR ((rsd, rs2)) => T
+ | C_OR ((rsd, rs2)) => T
+ | C_AND ((rsd, rs2)) => T
+ | C_SUBW ((rsd, rs2)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_ADDW ((rsd, rs2)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_J (v__610) => T
+ | C_BEQZ ((v__611, rs)) => T
+ | C_BNEZ ((v__612, rs)) => T
+ | C_SLLI ((v__613, rsd)) =>
+ if (let (nzui5 : 1 bits) = ((subrange_vec_dec v__613 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__613 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__613 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word)))))))))))))
+ then
+ T
+ else F
+ | C_LWSP ((v__614, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_LDSP ((v__615, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))))
+ then
+ T
+ else F
+ | C_SWSP ((v__616, rs2)) => T
+ | C_SDSP ((v__617, rs2)) => if ((((( 64 : int):ii) = (( 64 : int):ii)))) then T else F
+ | C_JR (rs1) => if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T
+ else F
+ | C_EBREAK (() ) => T
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T
+ else F
+ | C_ILLEGAL (s) => T
+ | _ => F
+ )))`;
+
+
+(*val encdec_compressed_backwards_matches : mword ty16 -> bool*)
+
+val _ = Define `
+ ((encdec_compressed_backwards_matches:(16)words$word -> bool) arg_=
+ (let v__618 = arg_ in
+ if (((v__618 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))
+ then
+ T
+ else if ((((let (nz96 : 4 bits) = ((subrange_vec_dec v__618 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in
+ let (nz54 : 2 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in
+ let (nz3 : 1 bits) = ((subrange_vec_dec v__618 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nz2 : 1 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word))
+ : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzi5 nzi40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 32 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (nzi9 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzi87 : 2 bits) = ((subrange_vec_dec v__618 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in
+ let (nzi6 : 1 bits) = ((subrange_vec_dec v__618 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in
+ let (nzi5 : 1 bits) = ((subrange_vec_dec v__618 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in
+ let (nzi4 : 1 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word))
+ : 5 words$word))
+ : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regidx_to_regno ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regidx_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (imm17 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (imm1612 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((((concat_vec imm17 imm1612 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ (((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__618 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (nzui5 : 1 bits) = ((subrange_vec_dec v__618 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in
+ let (nzui40 : 5 bits) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((concat_vec nzui5 nzui40 : 6 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((((( 64 : int):ii) = (( 64 : int):ii)))) \/ (((nzui5 = ((bool_to_bits F : 1 words$word))))))))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ T
+ else if (((((((( 64 : int):ii) = (( 64 : int):ii)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ T
+ else if ((((let (rs1 : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))))))))) then
+ T
+ else if ((((let (rs2 : regidx) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ let (rd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else if (((v__618 = (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 16 words$word)))) then
+ T
+ else if ((((let (rsd : regidx) = ((subrange_vec_dec v__618 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in
+ let (rs2 : regidx) = ((subrange_vec_dec v__618 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))) /\ ((((((((subrange_vec_dec v__618 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__618 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then
+ T
+ else T))`;
+
+
+(*val execute_WFI : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_WFI:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .
+ (case w__0 of
+ Machine => sail2_state_monad$seqS (platform_wfi () ) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) .
+ if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS
+ (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$seqS (platform_wfi () ) (sail2_state_monad$returnS RETIRE_SUCCESS))
+ | User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ ))))`;
+
+
+(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M Retired*)
+
+val _ = Define `
+ ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd op=
+ (let (off : xlenbits) =
+ ((EXTS (( 64 : int):ii)
+ ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+ : 32 words$word))
+ : 64 words$word)) in sail2_state_monad$bindS
+ (case op of
+ RISCV_LUI => sail2_state_monad$returnS off
+ | RISCV_AUIPC => sail2_state_monad$bindS
+ (get_arch_pc () : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS ((add_vec w__0 off : 64 words$word)))
+ ) (\ (ret : xlenbits) . sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ret) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_URET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_URET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (haveUsrMode () ) (\ (w__0 : bool) . sail2_state_monad$seqS
+ (if ((~ w__0)) then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_URET () ) w__2 : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ set_next_pc w__3))))
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (sail2_state_monad$bindS
+ (speculate_conditional_success () ) (\ (w__0 : bool) .
+ if (((w__0 = F))) then sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTZ (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)
+ else sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__1 : bool) .
+ if w__1 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 64 : int):ii) : 64 words$word)) Write width) (\ (w__2 : unit
+ Ext_DataAddr_Check) .
+ (case w__2 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ let (aligned : bool) =
+ ((case width of
+ BYTE => T
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))
+ )) in
+ if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else if (((((match_reservation vaddr)) = F))) then sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTZ (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Write : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__3 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__3 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__10) => mem_write_ea addr (( 4 : int):ii) aq rl T
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then mem_write_ea addr (( 8 : int):ii) aq rl T
+ else internal_error "STORECON expected word or double"
+ | _ => internal_error "STORECON expected word or double"
+ ) (\ (eares : unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . sail2_state_monad$bindS
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__9) =>
+ mem_write_value addr (( 4 : int):ii)
+ ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq rl T
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then mem_write_value addr (( 8 : int):ii) rs2_val aq rl T
+ else internal_error "STORECON expected word or double"
+ | _ => internal_error "STORECON expected word or double"
+ ) (\ (res : bool MemoryOpResult) .
+ (case res of
+ MemValue (T) => sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemValue (F) => sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTZ (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)))
+ (let (_ : unit) = (cancel_reservation () ) in
+ sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))
+ ))
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))))`;
+
+
+(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 width aq rl=
+ (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS
+ (ext_data_get_addr rs1 offset Write width) (\ (w__0 : unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+ (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Write : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__1 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case width of
+ BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F
+ | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F
+ | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F
+ | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F
+ ) (\ (eares : unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . sail2_state_monad$bindS
+ (case (width, (( 64 : int): ii)) of
+ (BYTE, g__3) =>
+ mem_write_value addr (( 1 : int): ii)
+ ((subrange_vec_dec rs2_val (( 7 : int): ii) (( 0 : int): ii) : 8 words$word))
+ aq rl F
+ | (HALF, g__4) =>
+ mem_write_value addr (( 2 : int): ii)
+ ((subrange_vec_dec rs2_val (( 15 : int): ii) (( 0 : int): ii) : 16 words$word))
+ aq rl F
+ | (WORD, g__5) =>
+ mem_write_value addr (( 4 : int): ii)
+ ((subrange_vec_dec rs2_val (( 31 : int): ii) (( 0 : int): ii) : 32 words$word))
+ aq rl F
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int): ii)))) then
+ mem_write_value addr (( 8 : int): ii) rs2_val aq rl F else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at model/riscv_insts_base.sail 394:47 - 399:15")
+ (sail2_state_monad$exitS () )
+ ) (\ (res : bool MemoryOpResult) .
+ (case res of
+ MemValue (T) => sail2_state_monad$returnS RETIRE_SUCCESS
+ | MemValue (F) => internal_error "store got false from mem_write_value"
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ )))
+ ))
+ ))
+ ))))`;
+
+
+(*val execute_SRET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_SRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS
+ (case w__0 of
+ User => handle_illegal ()
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state$or_boolS ( sail2_state_monad$bindS(haveSupMode () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))
+ ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) .
+ sail2_state_monad$returnS (((((get_Mstatus_TSR w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) (\ (w__3 :
+ bool) .
+ if w__3 then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__4 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__4 (CTL_SRET () ) w__5 : ( 64 words$word) M) (\ (w__6 : 64 words$word) .
+ set_next_pc w__6))))
+ | Machine => sail2_state_monad$bindS
+ (haveSupMode () ) (\ (w__7 : bool) .
+ if ((~ w__7)) then handle_illegal ()
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__8 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__8 (CTL_SRET () ) w__9 : ( 64 words$word) M) (\ (w__10 : 64 words$word) .
+ set_next_pc w__10))))
+ )
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word)
+ | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SHIFTIWOP : mword ty5 -> mword ty5 -> mword ty5 -> sopw -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTIWOP:(5)words$word ->(5)words$word ->(5)words$word -> sopw ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val .
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_SLLIW =>
+ (shift_bits_left ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ | RISCV_SRLIW =>
+ (shift_bits_right ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ | RISCV_SRAIW =>
+ (shift_right_arith32 ((subrange_vec_dec rs1_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) shamt
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M Retired*)
+
+val _ = Define `
+ ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val .
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt : 64 words$word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt : 64 words$word)
+ | RISCV_SRAI => (shift_right_arith64 rs1_val shamt : 64 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs1 rs2= (sail2_state_monad$bindS
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__0))) (\ (addr : xlenbits option) . sail2_state_monad$bindS
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE
+ else sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ sail2_state_monad$returnS (SOME w__1))) (\ (asid : xlenbits option) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) .
+ (case w__2 of
+ User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ | Supervisor => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) .
+ let p__7 =
+ (architecture ((get_mstatus_SXL w__3 : 2 words$word)), (get_Mstatus_TVM w__4 : 1 words$word)) in
+ (case p__7 of
+ (SOME (g__6), v_0) =>
+ if (((v_0 = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS
+ (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else if (((v_0 = ((bool_to_bits F : 1 words$word))))) then sail2_state_monad$seqS
+ (flush_TLB asid addr) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ else
+ (case (SOME g__6, v_0) of
+ (_, _) => internal_error "unimplemented sfence architecture"
+ )
+ | (_, _) => internal_error "unimplemented sfence architecture"
+ )))
+ | Machine => sail2_state_monad$seqS (flush_TLB asid addr) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ ))))))`;
+
+
+(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M Retired*)
+
+val _ = Define `
+ ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (result : 32 bits) =
+ ((case op of
+ RISCV_ADDW => (add_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SUBW => (sub_vec rs1_val rs2_val : 32 words$word)
+ | RISCV_SLLW =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRLW =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ | RISCV_SRAW =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word))
+ : 32 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M Retired*)
+
+val _ = Define `
+ ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val .
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_ADD => (add_vec rs1_val rs2_val : 64 words$word)
+ | RISCV_SLT =>
+ (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) : 1 words$word)) : 64 words$word)
+ | RISCV_SLTU =>
+ (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) : 1 words$word)) : 64 words$word)
+ | RISCV_AND => (and_vec rs1_val rs2_val : 64 words$word)
+ | RISCV_OR => (or_vec rs1_val rs2_val : 64 words$word)
+ | RISCV_XOR => (xor_vec rs1_val rs2_val : 64 words$word)
+ | RISCV_SLL =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word))
+ : 64 words$word)
+ | RISCV_SRL =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word))
+ : 64 words$word)
+ | RISCV_SUB => (sub_vec rs1_val rs2_val : 64 words$word)
+ | RISCV_SRA =>
+ (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word))
+ : 64 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in
+ (case ((ext_control_check_addr t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (addr) =>
+ let target = ((update_vec_dec addr (( 0 : int):ii) B0 : 64 words$word)) in sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (get_next_pc () : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) w__3) (set_next_pc target)) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ ))))`;
+
+
+(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd= (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (target) => sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (get_next_pc () : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) w__3) (set_next_pc target)) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ ))))`;
+
+
+(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r : 32 words$word)) : 64 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((to_bits (( 64 : int):ii) r : 64 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (integer_word$w2i rs1_val) in
+ let (rs2_int : ii) = (integer_word$w2i rs2_val) in
+ let result32 =
+ ((subrange_vec_dec ((to_bits (( 64 : int):ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):ii)
+ (( 0 : int):ii)
+ : 32 words$word)) in
+ let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32 : 64 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let result_wide =
+ ((to_bits (((( 2 : int):ii) * (( 64 : int):ii))) ((rs1_int * rs2_int)) : 128 words$word)) in
+ let result =
+ (if high then
+ (subrange_vec_dec result_wide (((((( 2 : int):ii) * (( 64 : int):ii))) - (( 1 : int):ii)))
+ (( 64 : int):ii)
+ : 64 words$word)
+ else (subrange_vec_dec result_wide (((( 64 : int):ii) - (( 1 : int):ii))) (( 0 : int):ii) : 64 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_MRET : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_MRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS
+ (if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))
+ then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_MRET () ) w__2 : ( 64 words$word) M) (\ (w__3 : 64 words$word) .
+ set_next_pc w__3)))
+ else handle_illegal () )
+ (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs1 width rd= (sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 64 : int):ii) : 64 words$word)) Read width) (\ (w__1 : unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ let (aligned : bool) =
+ ((case width of
+ BYTE => T
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))
+ )) in
+ if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Read : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__2 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) =>
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__8) => sail2_state_monad$bindS
+ (mem_read Read addr (( 4 : int):ii) aq rl T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__3 : ( 32 words$word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__3 F)
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS
+ (mem_read Read addr (( 8 : int):ii) aq rl T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__5 F)
+ else internal_error "LOADRES expected WORD or DOUBLE"
+ | _ => internal_error "LOADRES expected WORD or DOUBLE"
+ )
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl=
+ (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS
+ (ext_data_get_addr rs1 offset Read width) (\ (w__0 : unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then sail2_state_monad$seqS
+ (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (translateAddr vaddr Read : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__1 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) =>
+ (case (width, (( 64 : int): ii)) of
+ (BYTE, g__0) => sail2_state_monad$bindS
+ (mem_read Read addr (( 1 : int): ii) aq rl F : ( ( 8 words$word) MemoryOpResult) M)
+ (\ (w__2 : ( 8 words$word) MemoryOpResult) .
+ process_load rd vaddr w__2 is_unsigned)
+ | (HALF, g__1) => sail2_state_monad$bindS
+ (mem_read Read addr (( 2 : int): ii) aq rl F : ( ( 16 words$word) MemoryOpResult) M)
+ (\ (w__4 : ( 16 words$word) MemoryOpResult) .
+ process_load rd vaddr w__4 is_unsigned)
+ | (WORD, g__2) => sail2_state_monad$bindS
+ (mem_read Read addr (( 4 : int): ii) aq rl F : ( ( 32 words$word) MemoryOpResult) M)
+ (\ (w__6 : ( 32 words$word) MemoryOpResult) .
+ process_load rd vaddr w__6 is_unsigned)
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS
+ (mem_read Read addr (( 8 : int): ii) aq rl F : ( ( 64 words$word) MemoryOpResult) M)
+ (\ (w__8 : ( 64 words$word) MemoryOpResult) .
+ process_load rd vaddr w__8 is_unsigned) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at model/riscv_insts_base.sail 329:10 - 338:11")
+ (sail2_state_monad$exitS () )
+ )
+ ))
+ ))))`;
+
+
+(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M Retired*)
+
+val _ = Define `
+ ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val .
+ let (immext : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in
+ let (result : xlenbits) =
+ ((case op of
+ RISCV_ADDI => (add_vec rs1_val immext : 64 words$word)
+ | RISCV_SLTI =>
+ (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) : 1 words$word)) : 64 words$word)
+ | RISCV_SLTIU =>
+ (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) : 1 words$word)) : 64 words$word)
+ | RISCV_ANDI => (and_vec rs1_val immext : 64 words$word)
+ | RISCV_ORI => (or_vec rs1_val immext : 64 words$word)
+ | RISCV_XORI => (xor_vec rs1_val immext : 64 words$word)
+ )) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) result) (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+(*val execute_ILLEGAL : mword ty32 -> M Retired*)
+
+val _ = Define `
+ ((execute_ILLEGAL:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))`;
+
+
+(*val execute_FENCE_TSO : mword ty4 -> mword ty4 -> M Retired*)
+
+val _ = Define `
+ ((execute_FENCE_TSO:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ= (sail2_state_monad$seqS
+ (case (pred, succ) of
+ (v__794, v__795) =>
+ if ((((((((subrange_vec_dec v__794 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__795 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_tso
+ else
+ sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__794 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__795 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ ()
+ else
+ let (_ : unit) = (print_endline "FIXME: unsupported fence") in
+ () )
+ )
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))`;
+
+
+(*val execute_FENCEI : unit -> Retired*)
+
+val _ = Define `
+ ((execute_FENCEI:unit -> Retired) () = RETIRE_SUCCESS)`;
+
+
+(*val execute_FENCE : mword ty4 -> mword ty4 -> M Retired*)
+
+val _ = Define `
+ ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ= (sail2_state_monad$seqS
+ (case (pred, succ) of
+ (v__754, v__755) =>
+ if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_rw_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ barrier Barrier_RISCV_r_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ barrier Barrier_RISCV_w_r
+ else
+ sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__754 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__755 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ ()
+ else
+ let (_ : unit) = (print_endline "FIXME: unsupported fence") in
+ () )
+ )
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))`;
+
+
+(*val execute_ECALL : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_ECALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) .
+ let (t : sync_exception) =
+ (<| sync_exception_trap :=
+ ((case w__0 of
+ User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ ));
+ sync_exception_excinfo := NONE;
+ sync_exception_ext := NONE |>) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS
+ (exception_handler w__1 (CTL_TRAP t) w__2 : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$seqS
+ (set_next_pc w__3) (sail2_state_monad$returnS RETIRE_FAIL)))))))`;
+
+
+(*val execute_EBREAK : unit -> M Retired*)
+
+val _ = Define `
+ ((execute_EBREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$seqS
+ (handle_mem_exception w__0 E_Breakpoint) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let rs1_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ let rs2_val = ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in
+ let (q' : ii) =
+ (if (((s /\ ((q > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then
+ (( 0 : int):ii) - ((pow0 (( 2 : int):ii) (( 31 : int):ii)))
+ else q) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q' : 32 words$word)) : 64 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired*)
+
+val _ = Define `
+ ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS
+ (haveMulDiv () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val .
+ let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+ let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+ let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in
+ let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd)) ((to_bits (( 64 : int):ii) q' : 64 words$word))) (sail2_state_monad$returnS RETIRE_SUCCESS)))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_C_NOP : unit -> Retired*)
+
+val _ = Define `
+ ((execute_C_NOP:unit -> Retired) () = RETIRE_SUCCESS)`;
+
+
+(*val execute_C_ILLEGAL : mword ty16 -> M Retired*)
+
+val _ = Define `
+ ((execute_C_ILLEGAL:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)))`;
+
+
+(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M Retired*)
+
+val _ = Define `
+ ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr rs1 rd is_imm op= (sail2_state_monad$bindS
+ (if is_imm then sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) rs1 : 64 words$word))
+ else (rX ((regidx_to_regno rs1)) : ( 64 words$word) M)) (\ (rs1_val : xlenbits) .
+ let (isWrite : bool) =
+ ((case op of
+ CSRRW => T
+ | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii))
+ )) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS
+ (check_CSR csr w__1 isWrite) (\ (w__2 : bool) .
+ if ((~ w__2)) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$bindS
+ (readCSR csr : ( 64 words$word) M) (\ csr_val . sail2_state_monad$seqS (sail2_state_monad$seqS
+ (if isWrite then
+ let (new_val : xlenbits) =
+ ((case op of
+ CSRRW => rs1_val
+ | CSRRS => (or_vec csr_val rs1_val : 64 words$word)
+ | CSRRC => (and_vec csr_val ((not_vec rs1_val : 64 words$word)) : 64 words$word)
+ )) in
+ writeCSR csr new_val
+ else sail2_state_monad$returnS () )
+ (wX ((regidx_to_regno rd)) csr_val)) (sail2_state_monad$returnS RETIRE_SUCCESS)))))))`;
+
+
+(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M Retired*)
+
+val _ = Define `
+ ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 op= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val .
+ let (taken : bool) =
+ ((case op of
+ RISCV_BEQ => (rs1_val = rs2_val)
+ | RISCV_BNE => (rs1_val <> rs2_val)
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ )) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let (t : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in
+ if taken then
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_control_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_ControlAddr_OK (target) => sail2_state_monad$bindS
+ (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec target (( 1 : int):ii))))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : bool) .
+ if w__2 then sail2_state_monad$seqS (handle_mem_exception target E_Fetch_Addr_Align) (sail2_state_monad$returnS RETIRE_FAIL)
+ else sail2_state_monad$seqS (set_next_pc target) (sail2_state_monad$returnS RETIRE_SUCCESS))
+ )
+ else sail2_state_monad$returnS RETIRE_SUCCESS)))))`;
+
+
+(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (sail2_state_monad$bindS
+ (haveAtomics () ) (\ (w__0 : bool) .
+ if w__0 then sail2_state_monad$bindS
+ (ext_data_get_addr rs1 ((zeros_implicit (( 64 : int):ii) : 64 words$word)) ReadWrite width) (\ (w__1 : unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ let (_ : unit) = (ext_handle_data_check_error e) in
+ sail2_state_monad$returnS RETIRE_FAIL
+ | Ext_DataAddr_OK (vaddr) => sail2_state_monad$bindS
+ (translateAddr vaddr ReadWrite : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__2 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | TR_Address (addr) => sail2_state_monad$bindS
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__13) => mem_write_ea addr (( 4 : int):ii) (((aq /\ rl))) rl T
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then mem_write_ea addr (( 8 : int):ii) (((aq /\ rl))) rl T
+ else internal_error "AMO expected WORD or DOUBLE"
+ | _ => internal_error "AMO expected WORD or DOUBLE"
+ ) (\ (eares : unit MemoryOpResult) . sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs2)) : ( 64 words$word) M) (\ (rs2_val : xlenbits) .
+ (case eares of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (_) => sail2_state_monad$bindS
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__12) => sail2_state_monad$bindS
+ (mem_read ReadWrite addr (( 4 : int):ii) aq (((aq /\ rl))) T
+ : ( ( 32 words$word)MemoryOpResult) M) (\ (w__8 : ( 32 words$word) MemoryOpResult) .
+ sail2_state_monad$returnS ((extend_value F w__8 : ( 64 words$word) MemoryOpResult)))
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS
+ (mem_read ReadWrite addr (( 8 : int):ii) aq (((aq /\ rl))) T
+ : ( ( 64 words$word)MemoryOpResult) M) (\ (w__9 : ( 64 words$word) MemoryOpResult) .
+ sail2_state_monad$returnS ((extend_value F w__9 : ( 64 words$word) MemoryOpResult)))
+ else
+ (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)MemoryOpResult) M)
+ | _ =>
+ (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)MemoryOpResult) M)
+ ) (\ (rval : xlenbits MemoryOpResult) .
+ (case rval of
+ MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ | MemValue (loaded) =>
+ let (result : xlenbits) =
+ ((case op of
+ AMOSWAP => rs2_val
+ | AMOADD => (add_vec rs2_val loaded : 64 words$word)
+ | AMOXOR => (xor_vec rs2_val loaded : 64 words$word)
+ | AMOAND => (and_vec rs2_val loaded : 64 words$word)
+ | AMOOR => (or_vec rs2_val loaded : 64 words$word)
+ | AMOMIN =>
+ (to_bits (( 64 : int):ii) ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word)
+ | AMOMAX =>
+ (to_bits (( 64 : int):ii) ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word)
+ | AMOMINU =>
+ (to_bits (( 64 : int):ii) ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word)
+ | AMOMAXU =>
+ (to_bits (( 64 : int):ii) ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word)
+ )) in sail2_state_monad$bindS
+ (case (width, (( 64 : int):ii)) of
+ (WORD, g__11) =>
+ mem_write_value addr (( 4 : int):ii)
+ ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) (((aq /\ rl))) rl
+ T
+ | (DOUBLE, p0_) =>
+ if (((p0_ = (( 64 : int):ii)))) then
+ mem_write_value addr (( 8 : int):ii) result (((aq /\ rl))) rl T
+ else internal_error "AMO expected WORD or DOUBLE"
+ | _ => internal_error "AMO expected WORD or DOUBLE"
+ ) (\ (wval : bool MemoryOpResult) .
+ (case wval of
+ MemValue (T) => sail2_state_monad$seqS (wX ((regidx_to_regno rd)) loaded) (sail2_state_monad$returnS RETIRE_SUCCESS)
+ | MemValue (F) => internal_error "AMO got false from mem_write_value"
+ | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS RETIRE_FAIL)
+ ))
+ ))
+ )))
+ ))
+ ))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS RETIRE_FAIL))))`;
+
+
+(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M Retired*)
+
+val _ = Define `
+ ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS
+ (rX ((regidx_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm : 64 words$word)) w__0 : 64 words$word)) in sail2_state_monad$seqS
+ (wX ((regidx_to_regno rd))
+ ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))
+ (sail2_state_monad$returnS RETIRE_SUCCESS))))`;
+
+
+ val execute_defn = Hol_defn "execute" `
+ ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((Retired),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var=
+ ((case merge_var of
+ C_ADDI4SPN ((rdc, nzimm)) =>
+ let (imm : 12 bits) =
+ ((concat_vec (vec_of_bits [B0;B0] : 2 words$word)
+ ((concat_vec nzimm (vec_of_bits [B0;B0] : 2 words$word) : 10 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ execute (ITYPE (imm, sp, rd, RISCV_ADDI))
+ | C_LW ((uimm, rsc, rdc)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ let rs = ((creg2reg_idx rsc : 5 words$word)) in
+ execute (LOAD (imm, rs, rd, F, WORD, F, F))
+ | C_LD ((uimm, rsc, rdc)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word))
+ : 12 words$word)) in
+ let rd = ((creg2reg_idx rdc : 5 words$word)) in
+ let rs = ((creg2reg_idx rsc : 5 words$word)) in
+ execute (LOAD (imm, rs, rd, F, DOUBLE, F, F))
+ | C_SW ((uimm, rsc1, rsc2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word))
+ : 12 words$word)) in
+ let rs1 = ((creg2reg_idx rsc1 : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rsc2 : 5 words$word)) in
+ execute (STORE (imm, rs2, rs1, WORD, F, F))
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word))
+ : 12 words$word)) in
+ let rs1 = ((creg2reg_idx rsc1 : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rsc2 : 5 words$word)) in
+ execute (STORE (imm, rs2, rs1, DOUBLE, F, F))
+ | C_ADDI ((nzi, rsd)) =>
+ let (imm : 12 bits) = ((EXTS (( 12 : int):ii) nzi : 12 words$word)) in
+ execute (ITYPE (imm, rsd, rsd, RISCV_ADDI))
+ | C_JAL (imm) =>
+ execute
+ (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))
+ : 21 words$word),
+ ra))
+ | C_ADDIW ((imm, rsd)) => execute (ADDIW ((EXTS (( 12 : int):ii) imm : 12 words$word), rsd, rsd))
+ | C_LI ((imm, rd)) =>
+ let (imm : 12 bits) = ((EXTS (( 12 : int):ii) imm : 12 words$word)) in
+ execute (ITYPE (imm, zreg, rd, RISCV_ADDI))
+ | C_ADDI16SP (imm) =>
+ let (imm : 12 bits) =
+ ((EXTS (( 12 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 10 words$word))
+ : 12 words$word)) in
+ execute (ITYPE (imm, sp, sp, RISCV_ADDI))
+ | C_LUI ((imm, rd)) =>
+ let (res : 20 bits) = ((EXTS (( 20 : int):ii) imm : 20 words$word)) in
+ execute (UTYPE (res, rd, RISCV_LUI))
+ | C_SRLI ((shamt, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))
+ | C_SRAI ((shamt, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))
+ | C_ANDI ((imm, rsd)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ execute (ITYPE ((EXTS (( 12 : int):ii) imm : 12 words$word), rsd, rsd, RISCV_ANDI))
+ | C_SUB ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_SUB))
+ | C_XOR ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_XOR))
+ | C_OR ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_OR))
+ | C_AND ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_AND))
+ | C_SUBW ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_SUBW))
+ | C_ADDW ((rsd, rs2)) =>
+ let rsd = ((creg2reg_idx rsd : 5 words$word)) in
+ let rs2 = ((creg2reg_idx rs2 : 5 words$word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_ADDW))
+ | C_J (imm) =>
+ execute
+ (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))
+ : 21 words$word),
+ zreg))
+ | C_BEQZ ((imm, rs)) =>
+ execute
+ (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word))
+ : 13 words$word),
+ zreg,
+ (creg2reg_idx rs : 5 words$word),
+ RISCV_BEQ))
+ | C_BNEZ ((imm, rs)) =>
+ execute
+ (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word))
+ : 13 words$word),
+ zreg,
+ (creg2reg_idx rs : 5 words$word),
+ RISCV_BNE))
+ | C_SLLI ((shamt, rsd)) => execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI))
+ | C_LWSP ((uimm, rd)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word))
+ : 12 words$word)) in
+ execute (LOAD (imm, sp, rd, F, WORD, F, F))
+ | C_LDSP ((uimm, rd)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word))
+ : 12 words$word)) in
+ execute (LOAD (imm, sp, rd, F, DOUBLE, F, F))
+ | C_SWSP ((uimm, rs2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word))
+ : 12 words$word)) in
+ execute (STORE (imm, rs2, sp, WORD, F, F))
+ | C_SDSP ((uimm, rs2)) =>
+ let (imm : 12 bits) =
+ ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word))
+ : 12 words$word)) in
+ execute (STORE (imm, rs2, sp, DOUBLE, F, F))
+ | C_JR (rs1) =>
+ execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word), rs1, zreg))
+ | C_JALR (rs1) =>
+ execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word), rs1, ra))
+ | C_MV ((rd, rs2)) => execute (RTYPE (rs2, zreg, rd, RISCV_ADD))
+ | C_EBREAK (() ) => execute (EBREAK () )
+ | C_ADD ((rsd, rs2)) => execute (RTYPE (rs2, rsd, rsd, RISCV_ADD))
+ | UTYPE ((imm, rd, op)) => execute_UTYPE imm rd op
+ | RISCV_JAL ((imm, rd)) => execute_RISCV_JAL imm rd
+ | BTYPE ((imm, rs2, rs1, op)) => execute_BTYPE imm rs2 rs1 op
+ | ITYPE ((imm, rs1, rd, op)) => execute_ITYPE imm rs1 rd op
+ | SHIFTIOP ((shamt, rs1, rd, op)) => execute_SHIFTIOP shamt rs1 rd op
+ | RTYPE ((rs2, rs1, rd, op)) => execute_RTYPE rs2 rs1 rd op
+ | LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl)) =>
+ execute_LOAD imm rs1 rd is_unsigned width aq rl
+ | STORE ((imm, rs2, rs1, width, aq, rl)) => execute_STORE imm rs2 rs1 width aq rl
+ | ADDIW ((imm, rs1, rd)) => execute_ADDIW imm rs1 rd
+ | SHIFTW ((shamt, rs1, rd, op)) => execute_SHIFTW shamt rs1 rd op
+ | RTYPEW ((rs2, rs1, rd, op)) => execute_RTYPEW rs2 rs1 rd op
+ | SHIFTIWOP ((shamt, rs1, rd, op)) => execute_SHIFTIWOP shamt rs1 rd op
+ | FENCE ((pred, succ)) => execute_FENCE pred succ
+ | FENCE_TSO ((pred, succ)) => execute_FENCE_TSO pred succ
+ | FENCEI (arg0) => sail2_state_monad$returnS ((execute_FENCEI arg0))
+ | ECALL (arg0) => execute_ECALL arg0
+ | MRET (arg0) => execute_MRET arg0
+ | SRET (arg0) => execute_SRET arg0
+ | EBREAK (arg0) => execute_EBREAK arg0
+ | WFI (arg0) => execute_WFI arg0
+ | SFENCE_VMA ((rs1, rs2)) => execute_SFENCE_VMA rs1 rs2
+ | LOADRES ((aq, rl, rs1, width, rd)) => execute_LOADRES aq rl rs1 width rd
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) => execute_STORECON aq rl rs2 rs1 width rd
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => execute_AMO op aq rl rs2 rs1 width rd
+ | C_NOP (arg0) => sail2_state_monad$returnS ((execute_C_NOP arg0))
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => execute_MUL rs2 rs1 rd high signed1 signed2
+ | DIV0 ((rs2, rs1, rd, s)) => execute_DIV rs2 rs1 rd s
+ | REM ((rs2, rs1, rd, s)) => execute_REM rs2 rs1 rd s
+ | MULW ((rs2, rs1, rd)) => execute_MULW rs2 rs1 rd
+ | DIVW ((rs2, rs1, rd, s)) => execute_DIVW rs2 rs1 rd s
+ | REMW ((rs2, rs1, rd, s)) => execute_REMW rs2 rs1 rd s
+ | CSR ((csr, rs1, rd, is_imm, op)) => execute_CSR csr rs1 rd is_imm op
+ | URET (arg0) => execute_URET arg0
+ | RISCV_JALR ((imm, rs1, rd)) => execute_RISCV_JALR imm rs1 rd
+ | ILLEGAL (s) => execute_ILLEGAL s
+ | C_ILLEGAL (s) => execute_C_ILLEGAL s
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn;
+
+(*val assembly_forwards : ast -> M string*)
+
+val _ = Define `
+ ((assembly_forwards:ast ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__0 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((utype_mnemonic_forwards op))
+ ((string_append
+ ((spc_forwards () ))
+ ((string_append w__0
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm))
+ "")))))))))))
+ | RISCV_JAL ((imm, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__1 : string) .
+ sail2_state_monad$returnS
+ ((string_append "jal"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__1
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | RISCV_JALR ((imm, rs1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__2 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__3 : string) .
+ sail2_state_monad$returnS
+ ((
+ string_append
+ "jalr"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__2
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__3
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | BTYPE ((imm, rs2, rs1, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__4 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__5 : string) .
+ sail2_state_monad$returnS
+ ((
+ string_append
+ (
+ (
+ btype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__4
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__5
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | ITYPE ((imm, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__6 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__7 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ (
+ (
+ itype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__6
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__7
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ | SHIFTIOP ((shamt, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__8 : string) . sail2_state_monad$bindS
+ (
+ reg_name_forwards
+ rs1)
+ (
+ \ (w__9 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ shiftiop_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__8
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__9
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ | RTYPE ((rs2, rs1, rd, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__10 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__11 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__12 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ rtype_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__10
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__11
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__12
+ "")))))))))))))))))
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl)) => sail2_state_monad$bindS
+ (reg_name_forwards
+ rd)
+ (\ (w__13 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__14 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "l"
+ (
+ (
+ string_append
+ (
+ (
+ size_mnemonic_forwards
+ size1))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_u_forwards
+ is_unsigned))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__13
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ "("
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__14
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ ")"
+ ""))))))))))))))))))))))))))))))))
+ | STORE ((imm, rs2, rs1, size1, aq, rl)) => sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__15 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__16 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "s"
+ ((string_append
+ ((size_mnemonic_forwards
+ size1))
+ ((string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__15
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ imm))
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ "("
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__16
+ (
+ (
+ string_append
+ (
+ (
+ opt_spc_forwards
+ () ))
+ (
+ (
+ string_append
+ ")"
+ ""))))))))))))))))))))))))))))))
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__17 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__18 : string) .
+ sail2_state_monad$returnS
+ ((string_append "addiw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__17
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__18
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__21 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__22 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((shiftw_mnemonic_forwards op))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__21
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__22
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__25 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__26 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__27 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((rtypew_mnemonic_forwards
+ op))
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__25
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__26
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__27
+ "")))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__30 : string) . sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__31 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((shiftiwop_mnemonic_forwards op))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__30
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__31
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ shamt))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | FENCE ((pred, succ)) => sail2_state_monad$bindS
+ (fence_bits_forwards pred)
+ (\ (w__34 : string) . sail2_state_monad$bindS
+ (fence_bits_forwards
+ succ)
+ (\ (w__35 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "fence"
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__34
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__35
+ ""))))))))))))
+ | FENCE_TSO ((pred, succ)) => sail2_state_monad$bindS
+ (fence_bits_forwards pred)
+ (\ (w__36 : string) . sail2_state_monad$bindS
+ (fence_bits_forwards
+ succ)
+ (\ (w__37 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "fence.tso"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__36
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__37
+ ""))))))))))))
+ | FENCEI (() ) => sail2_state_monad$returnS "fence.i"
+ | ECALL (() ) => sail2_state_monad$returnS "ecall"
+ | MRET (() ) => sail2_state_monad$returnS "mret"
+ | SRET (() ) => sail2_state_monad$returnS "sret"
+ | EBREAK (() ) => sail2_state_monad$returnS "ebreak"
+ | WFI (() ) => sail2_state_monad$returnS "wfi"
+ | SFENCE_VMA ((rs1, rs2)) => sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__38 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__39 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "sfence.vma"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__38
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__39
+ ""))))))))))))
+ | LOADRES ((aq, rl, rs1, size1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__40 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__41 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "lr."
+ ((string_append
+ ((size_mnemonic_forwards
+ size1))
+ ((string_append
+ ((maybe_aq_forwards
+ aq))
+ ((string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__40
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__41
+ ""))))))))))))))))))
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__42 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__43 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__44 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "sc."
+ ((string_append
+ (
+ (
+ size_mnemonic_forwards
+ size1))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__42
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__43
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__44
+ "")))))))))))))))))))))))
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__45 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__46 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__47 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ ((amo_mnemonic_forwards
+ op))
+ ((string_append
+ "."
+ (
+ (
+ string_append
+ (
+ (
+ size_mnemonic_forwards
+ width))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_aq_forwards
+ aq))
+ (
+ (
+ string_append
+ (
+ (
+ maybe_rl_forwards
+ rl))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__45
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__46
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__47
+ "")))))))))))))))))))))))))
+ | C_NOP (() ) => sail2_state_monad$returnS "c.nop"
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if (((nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rdc)
+ (\ (w__48 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addi4spn"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__48
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec nzimm
+ (vec_of_bits [B0;B0] : 2 words$word)
+ : 10 words$word)))) ""))))))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LW ((uimm, rsc, rdc)) => sail2_state_monad$bindS
+ (creg_name_forwards rdc)
+ (\ (w__51 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rsc)
+ (\ (w__52 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.lw"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__51
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__52
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ (
+ (
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0] : 2 words$word)
+ : 7 words$word))))
+ ""))))))))))))))))
+ | C_LD ((uimm, rsc, rdc)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rdc)
+ (\ (w__53 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rsc)
+ (\ (w__54 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.ld"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__53
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__54
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0;B0] : 3 words$word)
+ : 8 words$word))))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SW ((uimm, rsc1, rsc2)) => sail2_state_monad$bindS
+ (creg_name_forwards rsc1)
+ (\ (w__57 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rsc2)
+ (\ (w__58 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.sw"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__57
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__58
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ (
+ (
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0] : 2 words$word)
+ : 7 words$word))))
+ ""))))))))))))))))
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsc1)
+ (\ (w__59 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rsc2)
+ (\ (w__60 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.sd"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__59
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__60
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((
+ concat_vec
+ uimm
+ (
+ vec_of_bits
+ [B0;B0;B0] : 3 words$word)
+ : 8 words$word))))
+ ""))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDI ((nzi, rsd)) =>
+ if ((((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__63 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addi"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__63
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits nzi)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JAL (imm) =>
+ if ((((( 64 : int): ii) = (( 32 : int): ii)))) then
+ sail2_state_monad$returnS
+ ((string_append "c.jal"
+ ((string_append ((spc_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word))))
+ "")))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDIW ((imm, rsd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__68 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addiw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__68
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LI ((imm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__71 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.li"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__71
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDI16SP (imm) =>
+ if (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$returnS
+ ((string_append "c.addi16sp"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LUI ((imm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\
+ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__76 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.lui"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__76
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SRLI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__79 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.srli"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__79
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SRAI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__82 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.srai"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__82
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ANDI ((imm, rsd)) => sail2_state_monad$bindS
+ (creg_name_forwards rsd)
+ (\ (w__85 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.andi"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__85
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_SUB ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__86 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__87 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.sub"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__86
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__87
+ ""))))))))))))
+ | C_XOR ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__88 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__89 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.xor"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__88
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__89
+ ""))))))))))))
+ | C_OR ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__90 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__91 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.or"
+ ((string_append
+ ((spc_forwards
+ () ))
+ ((string_append
+ w__90
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__91
+ ""))))))))))))
+ | C_AND ((rsd, rs2)) => sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__92 : string) . sail2_state_monad$bindS
+ (creg_name_forwards
+ rs2)
+ (\ (w__93 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "c.and"
+ ((string_append
+ ((
+ spc_forwards
+ () ))
+ ((
+ string_append
+ w__92
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__93
+ ""))))))))))))
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__94 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rs2)
+ (\ (w__95 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.subw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__94
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__95 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (creg_name_forwards rsd)
+ (\ (w__98 : string) . sail2_state_monad$bindS
+ (creg_name_forwards rs2)
+ (\ (w__99 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.addw"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__98
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__99 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_J (imm) =>
+ sail2_state_monad$returnS
+ ((string_append "c.j"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ""))))))
+ | C_BEQZ ((imm, rs)) => sail2_state_monad$bindS (creg_name_forwards rs)
+ (\ (w__102 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.beqz"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__102
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_BNEZ ((imm, rs)) => sail2_state_monad$bindS (creg_name_forwards rs)
+ (\ (w__103 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.bnez"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__103
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ imm)) "")))))))))))
+ | C_SLLI ((shamt, rsd)) =>
+ if ((((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__104 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.slli"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__104
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LWSP ((uimm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__107 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.lwsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__107
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_LDSP ((uimm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((( 64 : int): ii) = (( 64 : int): ii))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__110 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.ldsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__110
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_SWSP ((uimm, rd)) => sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__113 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.swsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__113
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ uimm)) "")))))))))))
+ | C_SDSP ((uimm, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rs2)
+ (\ (w__114 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.sdsp"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__114
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) "")))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__117 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.jr"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__117 ""))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then
+ sail2_state_monad$bindS (reg_name_forwards rs1)
+ (\ (w__120 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.jalr"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__120 ""))))))) else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__123 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__124 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.mv"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__123
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__124 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | C_EBREAK (() ) => sail2_state_monad$returnS "c.ebreak"
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ sail2_state_monad$bindS (reg_name_forwards rsd)
+ (\ (w__127 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs2)
+ (\ (w__128 : string) .
+ sail2_state_monad$returnS
+ ((string_append "c.add"
+ ((string_append ((spc_forwards () ))
+ ((string_append w__127
+ ((string_append
+ ((sep_forwards () ))
+ ((string_append w__128 ""))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => sail2_state_monad$bindS
+ (reg_name_forwards
+ rd)
+ (\ (w__131 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__132 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__133 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ (
+ (
+ mul_mnemonic_forwards
+ (high, signed1, signed2)))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__131
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__132
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__133
+ "")))))))))))))))))
+ | DIV0 ((rs2, rs1, rd, s)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__134 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__135 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__136 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "div"
+ (
+ (
+ string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__134
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__135
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__136
+ "")))))))))))))))))))
+ | REM ((rs2, rs1, rd, s)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__137 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__138 : string) .
+ sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__139 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ "rem"
+ (
+ (
+ string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__137
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__138
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__139
+ "")))))))))))))))))))
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__140 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__141 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__142 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "mulw"
+ ((string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__140
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__141
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__142
+ "")))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__145 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__146 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__147 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "div"
+ ((string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ "w"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__145
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__146
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__147
+ "")))))))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then
+ sail2_state_monad$bindS (reg_name_forwards rd)
+ (\ (w__150 : string) . sail2_state_monad$bindS
+ (reg_name_forwards rs1)
+ (\ (w__151 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs2)
+ (\ (w__152 : string) .
+ sail2_state_monad$returnS
+ ((string_append
+ "rem"
+ ((string_append
+ (
+ (
+ maybe_not_u_forwards
+ s))
+ (
+ (
+ string_append
+ "w"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__150
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__151
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__152
+ "")))))))))))))))))))))
+ else
+ sail2_state_monad$seqS
+ (sail2_state_monad$assert_expS F
+ "Pattern match failure at unknown location")
+ (sail2_state_monad$exitS () )
+ | CSR ((csr, rs1, rd, T, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__155 : string) . sail2_state_monad$bindS
+ (csr_name_map_forwards
+ csr)
+ (\ (w__156 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ csr_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ "i"
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__155
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ (
+ (
+ decimal_string_of_bits
+ rs1))
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__156
+ ""))))))))))))))))))
+ | CSR ((csr, rs1, rd, F, op)) => sail2_state_monad$bindS
+ (reg_name_forwards rd)
+ (\ (w__157 : string) . sail2_state_monad$bindS
+ (reg_name_forwards
+ rs1)
+ (\ (w__158 : string) .
+ sail2_state_monad$bindS
+ (
+ csr_name_map_forwards
+ csr)
+ (
+ \ (w__159 : string) .
+ sail2_state_monad$returnS
+ (
+ (
+ string_append
+ (
+ (
+ csr_mnemonic_forwards
+ op))
+ (
+ (
+ string_append
+ (
+ (
+ spc_forwards
+ () ))
+ (
+ (
+ string_append
+ w__157
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__158
+ (
+ (
+ string_append
+ (
+ (
+ sep_forwards
+ () ))
+ (
+ (
+ string_append
+ w__159
+ "")))))))))))))))))
+ | URET (() ) => sail2_state_monad$returnS "uret"
+ | ILLEGAL (s) =>
+ sail2_state_monad$returnS
+ ((string_append "illegal"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) ""))))))
+ | C_ILLEGAL (s) =>
+ sail2_state_monad$returnS
+ ((string_append "c.illegal"
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) ""))))))
+ )))`;
+
+
+(*val assembly_backwards : string -> M ast*)
+
+(*val _s1677_ : string -> maybe (mword ty16)*)
+
+val _ = Define `
+ ((s1677_:string ->((16)words$word)option) s1678_0=
+ (let s1679_0 = s1678_0 in
+ if ((string_startswith s1679_0 "c.illegal")) then
+ (case ((string_drop s1679_0 ((string_length "c.illegal")))) of
+ s1680_0 =>
+ (case ((spc_matches_prefix0 s1680_0)) of
+ SOME ((() , s1681_0)) =>
+ (case ((string_drop s1680_0 s1681_0)) of
+ s1682_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1682_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s1683_0)) =>
+ let p0_ = (string_drop s1682_0 s1683_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1669_ : string -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((s1669_:string ->((32)words$word)option) s1670_0=
+ (let s1671_0 = s1670_0 in
+ if ((string_startswith s1671_0 "illegal")) then
+ (case ((string_drop s1671_0 ((string_length "illegal")))) of
+ s1672_0 =>
+ (case ((spc_matches_prefix0 s1672_0)) of
+ SOME ((() , s1673_0)) =>
+ (case ((string_drop s1672_0 s1673_0)) of
+ s1674_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1674_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s1675_0)) =>
+ let p0_ = (string_drop s1674_0 s1675_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1652_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1652_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s1653_0=
+ ((case s1653_0 of
+ s1654_0 =>
+ (case ((csr_mnemonic_matches_prefix s1654_0)) of
+ SOME ((op, s1655_0)) =>
+ (case ((string_drop s1654_0 s1655_0)) of
+ s1656_0 =>
+ (case ((spc_matches_prefix0 s1656_0)) of
+ SOME ((() , s1657_0)) =>
+ (case ((string_drop s1656_0 s1657_0)) of
+ s1658_0 =>
+ (case ((reg_name_matches_prefix s1658_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1659_0)) =>
+ (case ((string_drop s1658_0 s1659_0)) of
+ s1660_0 =>
+ (case ((sep_matches_prefix s1660_0)) of
+ SOME ((() , s1661_0)) =>
+ (case ((string_drop s1660_0 s1661_0)) of
+ s1662_0 =>
+ (case ((reg_name_matches_prefix s1662_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1663_0)) =>
+ (case ((string_drop s1662_0 s1663_0)) of
+ s1664_0 =>
+ (case ((sep_matches_prefix s1664_0)) of
+ SOME ((() , s1665_0)) =>
+ (case ((string_drop s1664_0 s1665_0)) of
+ s1666_0 =>
+ (case ((csr_name_map_matches_prefix s1666_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s1667_0)) =>
+ let p0_ = (string_drop s1666_0 s1667_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1634_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1634_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s1635_0=
+ ((case s1635_0 of
+ s1636_0 =>
+ (case ((csr_mnemonic_matches_prefix s1636_0)) of
+ SOME ((op, s1637_0)) =>
+ let s1638_0 = (string_drop s1636_0 s1637_0) in
+ if ((string_startswith s1638_0 "i")) then
+ (case ((string_drop s1638_0 ((string_length "i")))) of
+ s1639_0 =>
+ (case ((spc_matches_prefix0 s1639_0)) of
+ SOME ((() , s1640_0)) =>
+ (case ((string_drop s1639_0 s1640_0)) of
+ s1641_0 =>
+ (case ((reg_name_matches_prefix s1641_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1642_0)) =>
+ (case ((string_drop s1641_0 s1642_0)) of
+ s1643_0 =>
+ (case ((sep_matches_prefix s1643_0)) of
+ SOME ((() , s1644_0)) =>
+ (case ((string_drop s1643_0 s1644_0)) of
+ s1645_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1645_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1646_0)) =>
+ (case ((string_drop s1645_0 s1646_0)) of
+ s1647_0 =>
+ (case ((sep_matches_prefix s1647_0)) of
+ SOME ((() , s1648_0)) =>
+ (case ((string_drop s1647_0 s1648_0)) of
+ s1649_0 =>
+ (case ((csr_name_map_matches_prefix s1649_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s1650_0)) =>
+ let p0_ = (string_drop s1649_0 s1650_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1615_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1615_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1616_0=
+ (let s1617_0 = s1616_0 in
+ if ((string_startswith s1617_0 "rem")) then
+ (case ((string_drop s1617_0 ((string_length "rem")))) of
+ s1618_0 =>
+ (case ((maybe_not_u_matches_prefix s1618_0)) of
+ SOME ((s, s1619_0)) =>
+ let s1620_0 = (string_drop s1618_0 s1619_0) in
+ if ((string_startswith s1620_0 "w")) then
+ (case ((string_drop s1620_0 ((string_length "w")))) of
+ s1621_0 =>
+ (case ((spc_matches_prefix0 s1621_0)) of
+ SOME ((() , s1622_0)) =>
+ (case ((string_drop s1621_0 s1622_0)) of
+ s1623_0 =>
+ (case ((reg_name_matches_prefix s1623_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1624_0)) =>
+ (case ((string_drop s1623_0 s1624_0)) of
+ s1625_0 =>
+ (case ((sep_matches_prefix s1625_0)) of
+ SOME ((() , s1626_0)) =>
+ (case ((string_drop s1625_0 s1626_0)) of
+ s1627_0 =>
+ (case ((reg_name_matches_prefix s1627_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1628_0)) =>
+ (case ((string_drop s1627_0 s1628_0)) of
+ s1629_0 =>
+ (case ((sep_matches_prefix s1629_0)) of
+ SOME ((() , s1630_0)) =>
+ (case ((string_drop s1629_0 s1630_0)) of
+ s1631_0 =>
+ (case ((reg_name_matches_prefix s1631_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1632_0)) =>
+ let p0_ = (string_drop s1631_0 s1632_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1596_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1596_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1597_0=
+ (let s1598_0 = s1597_0 in
+ if ((string_startswith s1598_0 "div")) then
+ (case ((string_drop s1598_0 ((string_length "div")))) of
+ s1599_0 =>
+ (case ((maybe_not_u_matches_prefix s1599_0)) of
+ SOME ((s, s1600_0)) =>
+ let s1601_0 = (string_drop s1599_0 s1600_0) in
+ if ((string_startswith s1601_0 "w")) then
+ (case ((string_drop s1601_0 ((string_length "w")))) of
+ s1602_0 =>
+ (case ((spc_matches_prefix0 s1602_0)) of
+ SOME ((() , s1603_0)) =>
+ (case ((string_drop s1602_0 s1603_0)) of
+ s1604_0 =>
+ (case ((reg_name_matches_prefix s1604_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1605_0)) =>
+ (case ((string_drop s1604_0 s1605_0)) of
+ s1606_0 =>
+ (case ((sep_matches_prefix s1606_0)) of
+ SOME ((() , s1607_0)) =>
+ (case ((string_drop s1606_0 s1607_0)) of
+ s1608_0 =>
+ (case ((reg_name_matches_prefix s1608_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1609_0)) =>
+ (case ((string_drop s1608_0 s1609_0)) of
+ s1610_0 =>
+ (case ((sep_matches_prefix s1610_0)) of
+ SOME ((() , s1611_0)) =>
+ (case ((string_drop s1610_0 s1611_0)) of
+ s1612_0 =>
+ (case ((reg_name_matches_prefix s1612_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1613_0)) =>
+ let p0_ = (string_drop s1612_0 s1613_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1580_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1580_:string ->((5)words$word#(5)words$word#(5)words$word)option) s1581_0=
+ (let s1582_0 = s1581_0 in
+ if ((string_startswith s1582_0 "mulw")) then
+ (case ((string_drop s1582_0 ((string_length "mulw")))) of
+ s1583_0 =>
+ (case ((spc_matches_prefix0 s1583_0)) of
+ SOME ((() , s1584_0)) =>
+ (case ((string_drop s1583_0 s1584_0)) of
+ s1585_0 =>
+ (case ((reg_name_matches_prefix s1585_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1586_0)) =>
+ (case ((string_drop s1585_0 s1586_0)) of
+ s1587_0 =>
+ (case ((sep_matches_prefix s1587_0)) of
+ SOME ((() , s1588_0)) =>
+ (case ((string_drop s1587_0 s1588_0)) of
+ s1589_0 =>
+ (case ((reg_name_matches_prefix s1589_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1590_0)) =>
+ (case ((string_drop s1589_0 s1590_0)) of
+ s1591_0 =>
+ (case ((sep_matches_prefix s1591_0)) of
+ SOME ((() , s1592_0)) =>
+ (case ((string_drop s1591_0 s1592_0)) of
+ s1593_0 =>
+ (case ((reg_name_matches_prefix s1593_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1594_0)) =>
+ let p0_ = (string_drop s1593_0 s1594_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1562_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1562_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1563_0=
+ (let s1564_0 = s1563_0 in
+ if ((string_startswith s1564_0 "rem")) then
+ (case ((string_drop s1564_0 ((string_length "rem")))) of
+ s1565_0 =>
+ (case ((maybe_not_u_matches_prefix s1565_0)) of
+ SOME ((s, s1566_0)) =>
+ (case ((string_drop s1565_0 s1566_0)) of
+ s1567_0 =>
+ (case ((spc_matches_prefix0 s1567_0)) of
+ SOME ((() , s1568_0)) =>
+ (case ((string_drop s1567_0 s1568_0)) of
+ s1569_0 =>
+ (case ((reg_name_matches_prefix s1569_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1570_0)) =>
+ (case ((string_drop s1569_0 s1570_0)) of
+ s1571_0 =>
+ (case ((sep_matches_prefix s1571_0)) of
+ SOME ((() , s1572_0)) =>
+ (case ((string_drop s1571_0 s1572_0)) of
+ s1573_0 =>
+ (case ((reg_name_matches_prefix s1573_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1574_0)) =>
+ (case ((string_drop s1573_0 s1574_0)) of
+ s1575_0 =>
+ (case ((sep_matches_prefix s1575_0)) of
+ SOME ((() , s1576_0)) =>
+ (case ((string_drop s1575_0 s1576_0)) of
+ s1577_0 =>
+ (case ((reg_name_matches_prefix s1577_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1578_0)) =>
+ let p0_ = (string_drop s1577_0 s1578_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1544_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1544_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s1545_0=
+ (let s1546_0 = s1545_0 in
+ if ((string_startswith s1546_0 "div")) then
+ (case ((string_drop s1546_0 ((string_length "div")))) of
+ s1547_0 =>
+ (case ((maybe_not_u_matches_prefix s1547_0)) of
+ SOME ((s, s1548_0)) =>
+ (case ((string_drop s1547_0 s1548_0)) of
+ s1549_0 =>
+ (case ((spc_matches_prefix0 s1549_0)) of
+ SOME ((() , s1550_0)) =>
+ (case ((string_drop s1549_0 s1550_0)) of
+ s1551_0 =>
+ (case ((reg_name_matches_prefix s1551_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1552_0)) =>
+ (case ((string_drop s1551_0 s1552_0)) of
+ s1553_0 =>
+ (case ((sep_matches_prefix s1553_0)) of
+ SOME ((() , s1554_0)) =>
+ (case ((string_drop s1553_0 s1554_0)) of
+ s1555_0 =>
+ (case ((reg_name_matches_prefix s1555_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1556_0)) =>
+ (case ((string_drop s1555_0 s1556_0)) of
+ s1557_0 =>
+ (case ((sep_matches_prefix s1557_0)) of
+ SOME ((() , s1558_0)) =>
+ (case ((string_drop s1557_0 s1558_0)) of
+ s1559_0 =>
+ (case ((reg_name_matches_prefix s1559_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1560_0)) =>
+ let p0_ = (string_drop s1559_0 s1560_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1527_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1527_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1528_0=
+ ((case s1528_0 of
+ s1529_0 =>
+ (case ((mul_mnemonic_matches_prefix s1529_0)) of
+ SOME (((high, signed1, signed2), s1530_0)) =>
+ (case ((string_drop s1529_0 s1530_0)) of
+ s1531_0 =>
+ (case ((spc_matches_prefix0 s1531_0)) of
+ SOME ((() , s1532_0)) =>
+ (case ((string_drop s1531_0 s1532_0)) of
+ s1533_0 =>
+ (case ((reg_name_matches_prefix s1533_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1534_0)) =>
+ (case ((string_drop s1533_0 s1534_0)) of
+ s1535_0 =>
+ (case ((sep_matches_prefix s1535_0)) of
+ SOME ((() , s1536_0)) =>
+ (case ((string_drop s1535_0 s1536_0)) of
+ s1537_0 =>
+ (case ((reg_name_matches_prefix s1537_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1538_0)) =>
+ (case ((string_drop s1537_0 s1538_0)) of
+ s1539_0 =>
+ (case ((sep_matches_prefix s1539_0)) of
+ SOME ((() , s1540_0)) =>
+ (case ((string_drop s1539_0 s1540_0)) of
+ s1541_0 =>
+ (case ((reg_name_matches_prefix s1541_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1542_0)) =>
+ let p0_ = (string_drop s1541_0 s1542_0) in
+ if (((p0_ = ""))) then SOME (high, signed1, signed2, rd, rs1, rs2) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1515_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1515_:string ->((5)words$word#(5)words$word)option) s1516_0=
+ (let s1517_0 = s1516_0 in
+ if ((string_startswith s1517_0 "c.add")) then
+ (case ((string_drop s1517_0 ((string_length "c.add")))) of
+ s1518_0 =>
+ (case ((spc_matches_prefix0 s1518_0)) of
+ SOME ((() , s1519_0)) =>
+ (case ((string_drop s1518_0 s1519_0)) of
+ s1520_0 =>
+ (case ((reg_name_matches_prefix s1520_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1521_0)) =>
+ (case ((string_drop s1520_0 s1521_0)) of
+ s1522_0 =>
+ (case ((sep_matches_prefix s1522_0)) of
+ SOME ((() , s1523_0)) =>
+ (case ((string_drop s1522_0 s1523_0)) of
+ s1524_0 =>
+ (case ((reg_name_matches_prefix s1524_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1525_0)) =>
+ let p0_ = (string_drop s1524_0 s1525_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1503_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1503_:string ->((5)words$word#(5)words$word)option) s1504_0=
+ (let s1505_0 = s1504_0 in
+ if ((string_startswith s1505_0 "c.mv")) then
+ (case ((string_drop s1505_0 ((string_length "c.mv")))) of
+ s1506_0 =>
+ (case ((spc_matches_prefix0 s1506_0)) of
+ SOME ((() , s1507_0)) =>
+ (case ((string_drop s1506_0 s1507_0)) of
+ s1508_0 =>
+ (case ((reg_name_matches_prefix s1508_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1509_0)) =>
+ (case ((string_drop s1508_0 s1509_0)) of
+ s1510_0 =>
+ (case ((sep_matches_prefix s1510_0)) of
+ SOME ((() , s1511_0)) =>
+ (case ((string_drop s1510_0 s1511_0)) of
+ s1512_0 =>
+ (case ((reg_name_matches_prefix s1512_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1513_0)) =>
+ let p0_ = (string_drop s1512_0 s1513_0) in
+ if (((p0_ = ""))) then SOME (rd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1495_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s1495_:string ->((5)words$word)option) s1496_0=
+ (let s1497_0 = s1496_0 in
+ if ((string_startswith s1497_0 "c.jalr")) then
+ (case ((string_drop s1497_0 ((string_length "c.jalr")))) of
+ s1498_0 =>
+ (case ((spc_matches_prefix0 s1498_0)) of
+ SOME ((() , s1499_0)) =>
+ (case ((string_drop s1498_0 s1499_0)) of
+ s1500_0 =>
+ (case ((reg_name_matches_prefix s1500_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1501_0)) =>
+ let p0_ = (string_drop s1500_0 s1501_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1487_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s1487_:string ->((5)words$word)option) s1488_0=
+ (let s1489_0 = s1488_0 in
+ if ((string_startswith s1489_0 "c.jr")) then
+ (case ((string_drop s1489_0 ((string_length "c.jr")))) of
+ s1490_0 =>
+ (case ((spc_matches_prefix0 s1490_0)) of
+ SOME ((() , s1491_0)) =>
+ (case ((string_drop s1490_0 s1491_0)) of
+ s1492_0 =>
+ (case ((reg_name_matches_prefix s1492_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1493_0)) =>
+ let p0_ = (string_drop s1492_0 s1493_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1475_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1475_:string ->((5)words$word#(6)words$word)option) s1476_0=
+ (let s1477_0 = s1476_0 in
+ if ((string_startswith s1477_0 "c.sdsp")) then
+ (case ((string_drop s1477_0 ((string_length "c.sdsp")))) of
+ s1478_0 =>
+ (case ((spc_matches_prefix0 s1478_0)) of
+ SOME ((() , s1479_0)) =>
+ (case ((string_drop s1478_0 s1479_0)) of
+ s1480_0 =>
+ (case ((reg_name_matches_prefix s1480_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1481_0)) =>
+ (case ((string_drop s1480_0 s1481_0)) of
+ s1482_0 =>
+ (case ((sep_matches_prefix s1482_0)) of
+ SOME ((() , s1483_0)) =>
+ (case ((string_drop s1482_0 s1483_0)) of
+ s1484_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1484_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1485_0)) =>
+ let p0_ = (string_drop s1484_0 s1485_0) in
+ if (((p0_ = ""))) then SOME (rs2, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1463_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1463_:string ->((5)words$word#(6)words$word)option) s1464_0=
+ (let s1465_0 = s1464_0 in
+ if ((string_startswith s1465_0 "c.swsp")) then
+ (case ((string_drop s1465_0 ((string_length "c.swsp")))) of
+ s1466_0 =>
+ (case ((spc_matches_prefix0 s1466_0)) of
+ SOME ((() , s1467_0)) =>
+ (case ((string_drop s1466_0 s1467_0)) of
+ s1468_0 =>
+ (case ((reg_name_matches_prefix s1468_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1469_0)) =>
+ (case ((string_drop s1468_0 s1469_0)) of
+ s1470_0 =>
+ (case ((sep_matches_prefix s1470_0)) of
+ SOME ((() , s1471_0)) =>
+ (case ((string_drop s1470_0 s1471_0)) of
+ s1472_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1472_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1473_0)) =>
+ let p0_ = (string_drop s1472_0 s1473_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1451_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1451_:string ->((5)words$word#(6)words$word)option) s1452_0=
+ (let s1453_0 = s1452_0 in
+ if ((string_startswith s1453_0 "c.ldsp")) then
+ (case ((string_drop s1453_0 ((string_length "c.ldsp")))) of
+ s1454_0 =>
+ (case ((spc_matches_prefix0 s1454_0)) of
+ SOME ((() , s1455_0)) =>
+ (case ((string_drop s1454_0 s1455_0)) of
+ s1456_0 =>
+ (case ((reg_name_matches_prefix s1456_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1457_0)) =>
+ (case ((string_drop s1456_0 s1457_0)) of
+ s1458_0 =>
+ (case ((sep_matches_prefix s1458_0)) of
+ SOME ((() , s1459_0)) =>
+ (case ((string_drop s1458_0 s1459_0)) of
+ s1460_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1460_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1461_0)) =>
+ let p0_ = (string_drop s1460_0 s1461_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1439_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1439_:string ->((5)words$word#(6)words$word)option) s1440_0=
+ (let s1441_0 = s1440_0 in
+ if ((string_startswith s1441_0 "c.lwsp")) then
+ (case ((string_drop s1441_0 ((string_length "c.lwsp")))) of
+ s1442_0 =>
+ (case ((spc_matches_prefix0 s1442_0)) of
+ SOME ((() , s1443_0)) =>
+ (case ((string_drop s1442_0 s1443_0)) of
+ s1444_0 =>
+ (case ((reg_name_matches_prefix s1444_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1445_0)) =>
+ (case ((string_drop s1444_0 s1445_0)) of
+ s1446_0 =>
+ (case ((sep_matches_prefix s1446_0)) of
+ SOME ((() , s1447_0)) =>
+ (case ((string_drop s1446_0 s1447_0)) of
+ s1448_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1448_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s1449_0)) =>
+ let p0_ = (string_drop s1448_0 s1449_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1427_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1427_:string ->((5)words$word#(6)words$word)option) s1428_0=
+ (let s1429_0 = s1428_0 in
+ if ((string_startswith s1429_0 "c.slli")) then
+ (case ((string_drop s1429_0 ((string_length "c.slli")))) of
+ s1430_0 =>
+ (case ((spc_matches_prefix0 s1430_0)) of
+ SOME ((() , s1431_0)) =>
+ (case ((string_drop s1430_0 s1431_0)) of
+ s1432_0 =>
+ (case ((reg_name_matches_prefix s1432_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1433_0)) =>
+ (case ((string_drop s1432_0 s1433_0)) of
+ s1434_0 =>
+ (case ((sep_matches_prefix s1434_0)) of
+ SOME ((() , s1435_0)) =>
+ (case ((string_drop s1434_0 s1435_0)) of
+ s1436_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1436_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1437_0)) =>
+ let p0_ = (string_drop s1436_0 s1437_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1415_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1415_:string ->((3)words$word#(8)words$word)option) s1416_0=
+ (let s1417_0 = s1416_0 in
+ if ((string_startswith s1417_0 "c.bnez")) then
+ (case ((string_drop s1417_0 ((string_length "c.bnez")))) of
+ s1418_0 =>
+ (case ((spc_matches_prefix0 s1418_0)) of
+ SOME ((() , s1419_0)) =>
+ (case ((string_drop s1418_0 s1419_0)) of
+ s1420_0 =>
+ (case ((creg_name_matches_prefix s1420_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s1421_0)) =>
+ (case ((string_drop s1420_0 s1421_0)) of
+ s1422_0 =>
+ (case ((sep_matches_prefix s1422_0)) of
+ SOME ((() , s1423_0)) =>
+ (case ((string_drop s1422_0 s1423_0)) of
+ s1424_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1424_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s1425_0)) =>
+ let p0_ = (string_drop s1424_0 s1425_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1403_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1403_:string ->((3)words$word#(8)words$word)option) s1404_0=
+ (let s1405_0 = s1404_0 in
+ if ((string_startswith s1405_0 "c.beqz")) then
+ (case ((string_drop s1405_0 ((string_length "c.beqz")))) of
+ s1406_0 =>
+ (case ((spc_matches_prefix0 s1406_0)) of
+ SOME ((() , s1407_0)) =>
+ (case ((string_drop s1406_0 s1407_0)) of
+ s1408_0 =>
+ (case ((creg_name_matches_prefix s1408_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s1409_0)) =>
+ (case ((string_drop s1408_0 s1409_0)) of
+ s1410_0 =>
+ (case ((sep_matches_prefix s1410_0)) of
+ SOME ((() , s1411_0)) =>
+ (case ((string_drop s1410_0 s1411_0)) of
+ s1412_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1412_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s1413_0)) =>
+ let p0_ = (string_drop s1412_0 s1413_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1395_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s1395_:string ->((11)words$word)option) s1396_0=
+ (let s1397_0 = s1396_0 in
+ if ((string_startswith s1397_0 "c.j")) then
+ (case ((string_drop s1397_0 ((string_length "c.j")))) of
+ s1398_0 =>
+ (case ((spc_matches_prefix0 s1398_0)) of
+ SOME ((() , s1399_0)) =>
+ (case ((string_drop s1398_0 s1399_0)) of
+ s1400_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1400_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s1401_0)) =>
+ let p0_ = (string_drop s1400_0 s1401_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1383_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1383_:string ->((3)words$word#(3)words$word)option) s1384_0=
+ (let s1385_0 = s1384_0 in
+ if ((string_startswith s1385_0 "c.addw")) then
+ (case ((string_drop s1385_0 ((string_length "c.addw")))) of
+ s1386_0 =>
+ (case ((spc_matches_prefix0 s1386_0)) of
+ SOME ((() , s1387_0)) =>
+ (case ((string_drop s1386_0 s1387_0)) of
+ s1388_0 =>
+ (case ((creg_name_matches_prefix s1388_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1389_0)) =>
+ (case ((string_drop s1388_0 s1389_0)) of
+ s1390_0 =>
+ (case ((sep_matches_prefix s1390_0)) of
+ SOME ((() , s1391_0)) =>
+ (case ((string_drop s1390_0 s1391_0)) of
+ s1392_0 =>
+ (case ((creg_name_matches_prefix s1392_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1393_0)) =>
+ let p0_ = (string_drop s1392_0 s1393_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1371_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1371_:string ->((3)words$word#(3)words$word)option) s1372_0=
+ (let s1373_0 = s1372_0 in
+ if ((string_startswith s1373_0 "c.subw")) then
+ (case ((string_drop s1373_0 ((string_length "c.subw")))) of
+ s1374_0 =>
+ (case ((spc_matches_prefix0 s1374_0)) of
+ SOME ((() , s1375_0)) =>
+ (case ((string_drop s1374_0 s1375_0)) of
+ s1376_0 =>
+ (case ((creg_name_matches_prefix s1376_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1377_0)) =>
+ (case ((string_drop s1376_0 s1377_0)) of
+ s1378_0 =>
+ (case ((sep_matches_prefix s1378_0)) of
+ SOME ((() , s1379_0)) =>
+ (case ((string_drop s1378_0 s1379_0)) of
+ s1380_0 =>
+ (case ((creg_name_matches_prefix s1380_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1381_0)) =>
+ let p0_ = (string_drop s1380_0 s1381_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1359_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1359_:string ->((3)words$word#(3)words$word)option) s1360_0=
+ (let s1361_0 = s1360_0 in
+ if ((string_startswith s1361_0 "c.and")) then
+ (case ((string_drop s1361_0 ((string_length "c.and")))) of
+ s1362_0 =>
+ (case ((spc_matches_prefix0 s1362_0)) of
+ SOME ((() , s1363_0)) =>
+ (case ((string_drop s1362_0 s1363_0)) of
+ s1364_0 =>
+ (case ((creg_name_matches_prefix s1364_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1365_0)) =>
+ (case ((string_drop s1364_0 s1365_0)) of
+ s1366_0 =>
+ (case ((sep_matches_prefix s1366_0)) of
+ SOME ((() , s1367_0)) =>
+ (case ((string_drop s1366_0 s1367_0)) of
+ s1368_0 =>
+ (case ((creg_name_matches_prefix s1368_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1369_0)) =>
+ let p0_ = (string_drop s1368_0 s1369_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1347_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1347_:string ->((3)words$word#(3)words$word)option) s1348_0=
+ (let s1349_0 = s1348_0 in
+ if ((string_startswith s1349_0 "c.or")) then
+ (case ((string_drop s1349_0 ((string_length "c.or")))) of
+ s1350_0 =>
+ (case ((spc_matches_prefix0 s1350_0)) of
+ SOME ((() , s1351_0)) =>
+ (case ((string_drop s1350_0 s1351_0)) of
+ s1352_0 =>
+ (case ((creg_name_matches_prefix s1352_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1353_0)) =>
+ (case ((string_drop s1352_0 s1353_0)) of
+ s1354_0 =>
+ (case ((sep_matches_prefix s1354_0)) of
+ SOME ((() , s1355_0)) =>
+ (case ((string_drop s1354_0 s1355_0)) of
+ s1356_0 =>
+ (case ((creg_name_matches_prefix s1356_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1357_0)) =>
+ let p0_ = (string_drop s1356_0 s1357_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1335_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1335_:string ->((3)words$word#(3)words$word)option) s1336_0=
+ (let s1337_0 = s1336_0 in
+ if ((string_startswith s1337_0 "c.xor")) then
+ (case ((string_drop s1337_0 ((string_length "c.xor")))) of
+ s1338_0 =>
+ (case ((spc_matches_prefix0 s1338_0)) of
+ SOME ((() , s1339_0)) =>
+ (case ((string_drop s1338_0 s1339_0)) of
+ s1340_0 =>
+ (case ((creg_name_matches_prefix s1340_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1341_0)) =>
+ (case ((string_drop s1340_0 s1341_0)) of
+ s1342_0 =>
+ (case ((sep_matches_prefix s1342_0)) of
+ SOME ((() , s1343_0)) =>
+ (case ((string_drop s1342_0 s1343_0)) of
+ s1344_0 =>
+ (case ((creg_name_matches_prefix s1344_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1345_0)) =>
+ let p0_ = (string_drop s1344_0 s1345_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1323_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s1323_:string ->((3)words$word#(3)words$word)option) s1324_0=
+ (let s1325_0 = s1324_0 in
+ if ((string_startswith s1325_0 "c.sub")) then
+ (case ((string_drop s1325_0 ((string_length "c.sub")))) of
+ s1326_0 =>
+ (case ((spc_matches_prefix0 s1326_0)) of
+ SOME ((() , s1327_0)) =>
+ (case ((string_drop s1326_0 s1327_0)) of
+ s1328_0 =>
+ (case ((creg_name_matches_prefix s1328_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1329_0)) =>
+ (case ((string_drop s1328_0 s1329_0)) of
+ s1330_0 =>
+ (case ((sep_matches_prefix s1330_0)) of
+ SOME ((() , s1331_0)) =>
+ (case ((string_drop s1330_0 s1331_0)) of
+ s1332_0 =>
+ (case ((creg_name_matches_prefix s1332_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s1333_0)) =>
+ let p0_ = (string_drop s1332_0 s1333_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1311_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1311_:string ->((3)words$word#(6)words$word)option) s1312_0=
+ (let s1313_0 = s1312_0 in
+ if ((string_startswith s1313_0 "c.andi")) then
+ (case ((string_drop s1313_0 ((string_length "c.andi")))) of
+ s1314_0 =>
+ (case ((spc_matches_prefix0 s1314_0)) of
+ SOME ((() , s1315_0)) =>
+ (case ((string_drop s1314_0 s1315_0)) of
+ s1316_0 =>
+ (case ((creg_name_matches_prefix s1316_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1317_0)) =>
+ (case ((string_drop s1316_0 s1317_0)) of
+ s1318_0 =>
+ (case ((sep_matches_prefix s1318_0)) of
+ SOME ((() , s1319_0)) =>
+ (case ((string_drop s1318_0 s1319_0)) of
+ s1320_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1320_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1321_0)) =>
+ let p0_ = (string_drop s1320_0 s1321_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1299_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1299_:string ->((3)words$word#(6)words$word)option) s1300_0=
+ (let s1301_0 = s1300_0 in
+ if ((string_startswith s1301_0 "c.srai")) then
+ (case ((string_drop s1301_0 ((string_length "c.srai")))) of
+ s1302_0 =>
+ (case ((spc_matches_prefix0 s1302_0)) of
+ SOME ((() , s1303_0)) =>
+ (case ((string_drop s1302_0 s1303_0)) of
+ s1304_0 =>
+ (case ((creg_name_matches_prefix s1304_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1305_0)) =>
+ (case ((string_drop s1304_0 s1305_0)) of
+ s1306_0 =>
+ (case ((sep_matches_prefix s1306_0)) of
+ SOME ((() , s1307_0)) =>
+ (case ((string_drop s1306_0 s1307_0)) of
+ s1308_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1308_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1309_0)) =>
+ let p0_ = (string_drop s1308_0 s1309_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1287_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s1287_:string ->((3)words$word#(6)words$word)option) s1288_0=
+ (let s1289_0 = s1288_0 in
+ if ((string_startswith s1289_0 "c.srli")) then
+ (case ((string_drop s1289_0 ((string_length "c.srli")))) of
+ s1290_0 =>
+ (case ((spc_matches_prefix0 s1290_0)) of
+ SOME ((() , s1291_0)) =>
+ (case ((string_drop s1290_0 s1291_0)) of
+ s1292_0 =>
+ (case ((creg_name_matches_prefix s1292_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s1293_0)) =>
+ (case ((string_drop s1292_0 s1293_0)) of
+ s1294_0 =>
+ (case ((sep_matches_prefix s1294_0)) of
+ SOME ((() , s1295_0)) =>
+ (case ((string_drop s1294_0 s1295_0)) of
+ s1296_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1296_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1297_0)) =>
+ let p0_ = (string_drop s1296_0 s1297_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1275_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1275_:string ->((5)words$word#(6)words$word)option) s1276_0=
+ (let s1277_0 = s1276_0 in
+ if ((string_startswith s1277_0 "c.lui")) then
+ (case ((string_drop s1277_0 ((string_length "c.lui")))) of
+ s1278_0 =>
+ (case ((spc_matches_prefix0 s1278_0)) of
+ SOME ((() , s1279_0)) =>
+ (case ((string_drop s1278_0 s1279_0)) of
+ s1280_0 =>
+ (case ((reg_name_matches_prefix s1280_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1281_0)) =>
+ (case ((string_drop s1280_0 s1281_0)) of
+ s1282_0 =>
+ (case ((sep_matches_prefix s1282_0)) of
+ SOME ((() , s1283_0)) =>
+ (case ((string_drop s1282_0 s1283_0)) of
+ s1284_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1284_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1285_0)) =>
+ let p0_ = (string_drop s1284_0 s1285_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1267_ : string -> maybe (mword ty6)*)
+
+val _ = Define `
+ ((s1267_:string ->((6)words$word)option) s1268_0=
+ (let s1269_0 = s1268_0 in
+ if ((string_startswith s1269_0 "c.addi16sp")) then
+ (case ((string_drop s1269_0 ((string_length "c.addi16sp")))) of
+ s1270_0 =>
+ (case ((spc_matches_prefix0 s1270_0)) of
+ SOME ((() , s1271_0)) =>
+ (case ((string_drop s1270_0 s1271_0)) of
+ s1272_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1272_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1273_0)) =>
+ let p0_ = (string_drop s1272_0 s1273_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1255_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1255_:string ->((5)words$word#(6)words$word)option) s1256_0=
+ (let s1257_0 = s1256_0 in
+ if ((string_startswith s1257_0 "c.li")) then
+ (case ((string_drop s1257_0 ((string_length "c.li")))) of
+ s1258_0 =>
+ (case ((spc_matches_prefix0 s1258_0)) of
+ SOME ((() , s1259_0)) =>
+ (case ((string_drop s1258_0 s1259_0)) of
+ s1260_0 =>
+ (case ((reg_name_matches_prefix s1260_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1261_0)) =>
+ (case ((string_drop s1260_0 s1261_0)) of
+ s1262_0 =>
+ (case ((sep_matches_prefix s1262_0)) of
+ SOME ((() , s1263_0)) =>
+ (case ((string_drop s1262_0 s1263_0)) of
+ s1264_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1264_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1265_0)) =>
+ let p0_ = (string_drop s1264_0 s1265_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1243_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1243_:string ->((5)words$word#(6)words$word)option) s1244_0=
+ (let s1245_0 = s1244_0 in
+ if ((string_startswith s1245_0 "c.addiw")) then
+ (case ((string_drop s1245_0 ((string_length "c.addiw")))) of
+ s1246_0 =>
+ (case ((spc_matches_prefix0 s1246_0)) of
+ SOME ((() , s1247_0)) =>
+ (case ((string_drop s1246_0 s1247_0)) of
+ s1248_0 =>
+ (case ((reg_name_matches_prefix s1248_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1249_0)) =>
+ (case ((string_drop s1248_0 s1249_0)) of
+ s1250_0 =>
+ (case ((sep_matches_prefix s1250_0)) of
+ SOME ((() , s1251_0)) =>
+ (case ((string_drop s1250_0 s1251_0)) of
+ s1252_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1252_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s1253_0)) =>
+ let p0_ = (string_drop s1252_0 s1253_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1235_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s1235_:string ->((11)words$word)option) s1236_0=
+ (let s1237_0 = s1236_0 in
+ if ((string_startswith s1237_0 "c.jal")) then
+ (case ((string_drop s1237_0 ((string_length "c.jal")))) of
+ s1238_0 =>
+ (case ((spc_matches_prefix0 s1238_0)) of
+ SOME ((() , s1239_0)) =>
+ (case ((string_drop s1238_0 s1239_0)) of
+ s1240_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1240_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__802, s1241_0)) =>
+ if (((((subrange_vec_dec v__802 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__802 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__802 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let p0_ = (string_drop s1240_0 s1241_0) in
+ if (((p0_ = ""))) then SOME imm else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1223_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1223_:string ->((5)words$word#(6)words$word)option) s1224_0=
+ (let s1225_0 = s1224_0 in
+ if ((string_startswith s1225_0 "c.addi")) then
+ (case ((string_drop s1225_0 ((string_length "c.addi")))) of
+ s1226_0 =>
+ (case ((spc_matches_prefix0 s1226_0)) of
+ SOME ((() , s1227_0)) =>
+ (case ((string_drop s1226_0 s1227_0)) of
+ s1228_0 =>
+ (case ((reg_name_matches_prefix s1228_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s1229_0)) =>
+ (case ((string_drop s1228_0 s1229_0)) of
+ s1230_0 =>
+ (case ((sep_matches_prefix s1230_0)) of
+ SOME ((() , s1231_0)) =>
+ (case ((string_drop s1230_0 s1231_0)) of
+ s1232_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1232_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s1233_0)) =>
+ let p0_ = (string_drop s1232_0 s1233_0) in
+ if (((p0_ = ""))) then SOME (rsd, nzi) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1207_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1207_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1208_0=
+ (let s1209_0 = s1208_0 in
+ if ((string_startswith s1209_0 "c.sd")) then
+ (case ((string_drop s1209_0 ((string_length "c.sd")))) of
+ s1210_0 =>
+ (case ((spc_matches_prefix0 s1210_0)) of
+ SOME ((() , s1211_0)) =>
+ (case ((string_drop s1210_0 s1211_0)) of
+ s1212_0 =>
+ (case ((creg_name_matches_prefix s1212_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s1213_0)) =>
+ (case ((string_drop s1212_0 s1213_0)) of
+ s1214_0 =>
+ (case ((sep_matches_prefix s1214_0)) of
+ SOME ((() , s1215_0)) =>
+ (case ((string_drop s1214_0 s1215_0)) of
+ s1216_0 =>
+ (case ((creg_name_matches_prefix s1216_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s1217_0)) =>
+ (case ((string_drop s1216_0 s1217_0)) of
+ s1218_0 =>
+ (case ((sep_matches_prefix s1218_0)) of
+ SOME ((() , s1219_0)) =>
+ (case ((string_drop s1218_0 s1219_0)) of
+ s1220_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1220_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__804, s1221_0)) =>
+ if (((((subrange_vec_dec v__804 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__804 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__804 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1220_0 s1221_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1191_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1191_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1192_0=
+ (let s1193_0 = s1192_0 in
+ if ((string_startswith s1193_0 "c.sw")) then
+ (case ((string_drop s1193_0 ((string_length "c.sw")))) of
+ s1194_0 =>
+ (case ((spc_matches_prefix0 s1194_0)) of
+ SOME ((() , s1195_0)) =>
+ (case ((string_drop s1194_0 s1195_0)) of
+ s1196_0 =>
+ (case ((creg_name_matches_prefix s1196_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s1197_0)) =>
+ (case ((string_drop s1196_0 s1197_0)) of
+ s1198_0 =>
+ (case ((sep_matches_prefix s1198_0)) of
+ SOME ((() , s1199_0)) =>
+ (case ((string_drop s1198_0 s1199_0)) of
+ s1200_0 =>
+ (case ((creg_name_matches_prefix s1200_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s1201_0)) =>
+ (case ((string_drop s1200_0 s1201_0)) of
+ s1202_0 =>
+ (case ((sep_matches_prefix s1202_0)) of
+ SOME ((() , s1203_0)) =>
+ (case ((string_drop s1202_0 s1203_0)) of
+ s1204_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1204_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__806, s1205_0)) =>
+ if (((((subrange_vec_dec v__806 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__806 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__806 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1204_0 s1205_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1175_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1175_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1176_0=
+ (let s1177_0 = s1176_0 in
+ if ((string_startswith s1177_0 "c.ld")) then
+ (case ((string_drop s1177_0 ((string_length "c.ld")))) of
+ s1178_0 =>
+ (case ((spc_matches_prefix0 s1178_0)) of
+ SOME ((() , s1179_0)) =>
+ (case ((string_drop s1178_0 s1179_0)) of
+ s1180_0 =>
+ (case ((creg_name_matches_prefix s1180_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1181_0)) =>
+ (case ((string_drop s1180_0 s1181_0)) of
+ s1182_0 =>
+ (case ((sep_matches_prefix s1182_0)) of
+ SOME ((() , s1183_0)) =>
+ (case ((string_drop s1182_0 s1183_0)) of
+ s1184_0 =>
+ (case ((creg_name_matches_prefix s1184_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s1185_0)) =>
+ (case ((string_drop s1184_0 s1185_0)) of
+ s1186_0 =>
+ (case ((sep_matches_prefix s1186_0)) of
+ SOME ((() , s1187_0)) =>
+ (case ((string_drop s1186_0 s1187_0)) of
+ s1188_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1188_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__808, s1189_0)) =>
+ if (((((subrange_vec_dec v__808 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__808 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__808 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1188_0 s1189_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1159_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s1159_:string ->((3)words$word#(3)words$word#(5)words$word)option) s1160_0=
+ (let s1161_0 = s1160_0 in
+ if ((string_startswith s1161_0 "c.lw")) then
+ (case ((string_drop s1161_0 ((string_length "c.lw")))) of
+ s1162_0 =>
+ (case ((spc_matches_prefix0 s1162_0)) of
+ SOME ((() , s1163_0)) =>
+ (case ((string_drop s1162_0 s1163_0)) of
+ s1164_0 =>
+ (case ((creg_name_matches_prefix s1164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1165_0)) =>
+ (case ((string_drop s1164_0 s1165_0)) of
+ s1166_0 =>
+ (case ((sep_matches_prefix s1166_0)) of
+ SOME ((() , s1167_0)) =>
+ (case ((string_drop s1166_0 s1167_0)) of
+ s1168_0 =>
+ (case ((creg_name_matches_prefix s1168_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s1169_0)) =>
+ (case ((string_drop s1168_0 s1169_0)) of
+ s1170_0 =>
+ (case ((sep_matches_prefix s1170_0)) of
+ SOME ((() , s1171_0)) =>
+ (case ((string_drop s1170_0 s1171_0)) of
+ s1172_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1172_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__810, s1173_0)) =>
+ if (((((subrange_vec_dec v__810 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__810 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__810 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s1172_0 s1173_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1147_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s1147_:string ->((3)words$word#(8)words$word)option) s1148_0=
+ (let s1149_0 = s1148_0 in
+ if ((string_startswith s1149_0 "c.addi4spn")) then
+ (case ((string_drop s1149_0 ((string_length "c.addi4spn")))) of
+ s1150_0 =>
+ (case ((spc_matches_prefix0 s1150_0)) of
+ SOME ((() , s1151_0)) =>
+ (case ((string_drop s1150_0 s1151_0)) of
+ s1152_0 =>
+ (case ((creg_name_matches_prefix s1152_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s1153_0)) =>
+ (case ((string_drop s1152_0 s1153_0)) of
+ s1154_0 =>
+ (case ((sep_matches_prefix s1154_0)) of
+ SOME ((() , s1155_0)) =>
+ (case ((string_drop s1154_0 s1155_0)) of
+ s1156_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1156_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__812, s1157_0)) =>
+ if (((((subrange_vec_dec v__812 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__812 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__812 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let p0_ = (string_drop s1156_0 s1157_0) in
+ if (((p0_ = ""))) then SOME (rdc, nzimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1123_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1123_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1124_0=
+ ((case s1124_0 of
+ s1125_0 =>
+ (case ((amo_mnemonic_matches_prefix s1125_0)) of
+ SOME ((op, s1126_0)) =>
+ let s1127_0 = (string_drop s1125_0 s1126_0) in
+ if ((string_startswith s1127_0 ".")) then
+ (case ((string_drop s1127_0 ((string_length ".")))) of
+ s1128_0 =>
+ (case ((size_mnemonic_matches_prefix s1128_0)) of
+ SOME ((width, s1129_0)) =>
+ (case ((string_drop s1128_0 s1129_0)) of
+ s1130_0 =>
+ (case ((maybe_aq_matches_prefix s1130_0)) of
+ SOME ((aq, s1131_0)) =>
+ (case ((string_drop s1130_0 s1131_0)) of
+ s1132_0 =>
+ (case ((maybe_rl_matches_prefix s1132_0)) of
+ SOME ((rl, s1133_0)) =>
+ (case ((string_drop s1132_0 s1133_0)) of
+ s1134_0 =>
+ (case ((spc_matches_prefix0 s1134_0)) of
+ SOME ((() , s1135_0)) =>
+ (case ((string_drop s1134_0 s1135_0)) of
+ s1136_0 =>
+ (case ((reg_name_matches_prefix s1136_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1137_0)) =>
+ (case ((string_drop s1136_0 s1137_0)) of
+ s1138_0 =>
+ (case ((sep_matches_prefix s1138_0)) of
+ SOME ((() , s1139_0)) =>
+ (case ((string_drop s1138_0 s1139_0)) of
+ s1140_0 =>
+ (case ((reg_name_matches_prefix s1140_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1141_0)) =>
+ (case ((string_drop s1140_0 s1141_0)) of
+ s1142_0 =>
+ (case ((sep_matches_prefix s1142_0)) of
+ SOME ((() , s1143_0)) =>
+ (case ((string_drop s1142_0 s1143_0)) of
+ s1144_0 =>
+ (case ((reg_name_matches_prefix s1144_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1145_0)) =>
+ let p0_ = (string_drop s1144_0 s1145_0) in
+ if (((p0_ = ""))) then SOME (op, width, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1101_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1101_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1102_0=
+ (let s1103_0 = s1102_0 in
+ if ((string_startswith s1103_0 "sc.")) then
+ (case ((string_drop s1103_0 ((string_length "sc.")))) of
+ s1104_0 =>
+ (case ((size_mnemonic_matches_prefix s1104_0)) of
+ SOME ((size1, s1105_0)) =>
+ (case ((string_drop s1104_0 s1105_0)) of
+ s1106_0 =>
+ (case ((maybe_aq_matches_prefix s1106_0)) of
+ SOME ((aq, s1107_0)) =>
+ (case ((string_drop s1106_0 s1107_0)) of
+ s1108_0 =>
+ (case ((maybe_rl_matches_prefix s1108_0)) of
+ SOME ((rl, s1109_0)) =>
+ (case ((string_drop s1108_0 s1109_0)) of
+ s1110_0 =>
+ (case ((spc_matches_prefix0 s1110_0)) of
+ SOME ((() , s1111_0)) =>
+ (case ((string_drop s1110_0 s1111_0)) of
+ s1112_0 =>
+ (case ((reg_name_matches_prefix s1112_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1113_0)) =>
+ (case ((string_drop s1112_0 s1113_0)) of
+ s1114_0 =>
+ (case ((sep_matches_prefix s1114_0)) of
+ SOME ((() , s1115_0)) =>
+ (case ((string_drop s1114_0 s1115_0)) of
+ s1116_0 =>
+ (case ((reg_name_matches_prefix s1116_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1117_0)) =>
+ (case ((string_drop s1116_0 s1117_0)) of
+ s1118_0 =>
+ (case ((sep_matches_prefix s1118_0)) of
+ SOME ((() , s1119_0)) =>
+ (case ((string_drop s1118_0 s1119_0)) of
+ s1120_0 =>
+ (case ((reg_name_matches_prefix s1120_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1121_0)) =>
+ let p0_ = (string_drop s1120_0 s1121_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1083_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1083_:string ->(word_width#bool#bool#(5)words$word#(5)words$word)option) s1084_0=
+ (let s1085_0 = s1084_0 in
+ if ((string_startswith s1085_0 "lr.")) then
+ (case ((string_drop s1085_0 ((string_length "lr.")))) of
+ s1086_0 =>
+ (case ((size_mnemonic_matches_prefix s1086_0)) of
+ SOME ((size1, s1087_0)) =>
+ (case ((string_drop s1086_0 s1087_0)) of
+ s1088_0 =>
+ (case ((maybe_aq_matches_prefix s1088_0)) of
+ SOME ((aq, s1089_0)) =>
+ (case ((string_drop s1088_0 s1089_0)) of
+ s1090_0 =>
+ (case ((maybe_rl_matches_prefix s1090_0)) of
+ SOME ((rl, s1091_0)) =>
+ (case ((string_drop s1090_0 s1091_0)) of
+ s1092_0 =>
+ (case ((spc_matches_prefix0 s1092_0)) of
+ SOME ((() , s1093_0)) =>
+ (case ((string_drop s1092_0 s1093_0)) of
+ s1094_0 =>
+ (case ((reg_name_matches_prefix s1094_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1095_0)) =>
+ (case ((string_drop s1094_0 s1095_0)) of
+ s1096_0 =>
+ (case ((sep_matches_prefix s1096_0)) of
+ SOME ((() , s1097_0)) =>
+ (case ((string_drop s1096_0 s1097_0)) of
+ s1098_0 =>
+ (case ((reg_name_matches_prefix s1098_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1099_0)) =>
+ let p0_ = (string_drop s1098_0 s1099_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1071_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1071_:string ->((5)words$word#(5)words$word)option) s1072_0=
+ (let s1073_0 = s1072_0 in
+ if ((string_startswith s1073_0 "sfence.vma")) then
+ (case ((string_drop s1073_0 ((string_length "sfence.vma")))) of
+ s1074_0 =>
+ (case ((spc_matches_prefix0 s1074_0)) of
+ SOME ((() , s1075_0)) =>
+ (case ((string_drop s1074_0 s1075_0)) of
+ s1076_0 =>
+ (case ((reg_name_matches_prefix s1076_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1077_0)) =>
+ (case ((string_drop s1076_0 s1077_0)) of
+ s1078_0 =>
+ (case ((sep_matches_prefix s1078_0)) of
+ SOME ((() , s1079_0)) =>
+ (case ((string_drop s1078_0 s1079_0)) of
+ s1080_0 =>
+ (case ((reg_name_matches_prefix s1080_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1081_0)) =>
+ let p0_ = (string_drop s1080_0 s1081_0) in
+ if (((p0_ = ""))) then SOME (rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1059_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1059_:string ->((4)words$word#(4)words$word)option) s1060_0=
+ (let s1061_0 = s1060_0 in
+ if ((string_startswith s1061_0 "fence.tso")) then
+ (case ((string_drop s1061_0 ((string_length "fence.tso")))) of
+ s1062_0 =>
+ (case ((spc_matches_prefix0 s1062_0)) of
+ SOME ((() , s1063_0)) =>
+ (case ((string_drop s1062_0 s1063_0)) of
+ s1064_0 =>
+ (case ((fence_bits_matches_prefix s1064_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1065_0)) =>
+ (case ((string_drop s1064_0 s1065_0)) of
+ s1066_0 =>
+ (case ((sep_matches_prefix s1066_0)) of
+ SOME ((() , s1067_0)) =>
+ (case ((string_drop s1066_0 s1067_0)) of
+ s1068_0 =>
+ (case ((fence_bits_matches_prefix s1068_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1069_0)) =>
+ let p0_ = (string_drop s1068_0 s1069_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1047_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1047_:string ->((4)words$word#(4)words$word)option) s1048_0=
+ (let s1049_0 = s1048_0 in
+ if ((string_startswith s1049_0 "fence")) then
+ (case ((string_drop s1049_0 ((string_length "fence")))) of
+ s1050_0 =>
+ (case ((spc_matches_prefix0 s1050_0)) of
+ SOME ((() , s1051_0)) =>
+ (case ((string_drop s1050_0 s1051_0)) of
+ s1052_0 =>
+ (case ((fence_bits_matches_prefix s1052_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1053_0)) =>
+ (case ((string_drop s1052_0 s1053_0)) of
+ s1054_0 =>
+ (case ((sep_matches_prefix s1054_0)) of
+ SOME ((() , s1055_0)) =>
+ (case ((string_drop s1054_0 s1055_0)) of
+ s1056_0 =>
+ (case ((fence_bits_matches_prefix s1056_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1057_0)) =>
+ let p0_ = (string_drop s1056_0 s1057_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1030_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1030_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word)option) s1031_0=
+ ((case s1031_0 of
+ s1032_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s1032_0)) of
+ SOME ((op, s1033_0)) =>
+ (case ((string_drop s1032_0 s1033_0)) of
+ s1034_0 =>
+ (case ((spc_matches_prefix0 s1034_0)) of
+ SOME ((() , s1035_0)) =>
+ (case ((string_drop s1034_0 s1035_0)) of
+ s1036_0 =>
+ (case ((reg_name_matches_prefix s1036_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1037_0)) =>
+ (case ((string_drop s1036_0 s1037_0)) of
+ s1038_0 =>
+ (case ((sep_matches_prefix s1038_0)) of
+ SOME ((() , s1039_0)) =>
+ (case ((string_drop s1038_0 s1039_0)) of
+ s1040_0 =>
+ (case ((reg_name_matches_prefix s1040_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1041_0)) =>
+ (case ((string_drop s1040_0 s1041_0)) of
+ s1042_0 =>
+ (case ((sep_matches_prefix s1042_0)) of
+ SOME ((() , s1043_0)) =>
+ (case ((string_drop s1042_0 s1043_0)) of
+ s1044_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1044_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1045_0)) =>
+ let p0_ = (string_drop s1044_0 s1045_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1013_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1013_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word)option) s1014_0=
+ ((case s1014_0 of
+ s1015_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s1015_0)) of
+ SOME ((op, s1016_0)) =>
+ (case ((string_drop s1015_0 s1016_0)) of
+ s1017_0 =>
+ (case ((spc_matches_prefix0 s1017_0)) of
+ SOME ((() , s1018_0)) =>
+ (case ((string_drop s1017_0 s1018_0)) of
+ s1019_0 =>
+ (case ((reg_name_matches_prefix s1019_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1020_0)) =>
+ (case ((string_drop s1019_0 s1020_0)) of
+ s1021_0 =>
+ (case ((sep_matches_prefix s1021_0)) of
+ SOME ((() , s1022_0)) =>
+ (case ((string_drop s1021_0 s1022_0)) of
+ s1023_0 =>
+ (case ((reg_name_matches_prefix s1023_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1024_0)) =>
+ (case ((string_drop s1023_0 s1024_0)) of
+ s1025_0 =>
+ (case ((sep_matches_prefix s1025_0)) of
+ SOME ((() , s1026_0)) =>
+ (case ((string_drop s1025_0 s1026_0)) of
+ s1027_0 =>
+ (case ((reg_name_matches_prefix s1027_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1028_0)) =>
+ let p0_ = (string_drop s1027_0 s1028_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s996_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s996_:string ->(sop#(5)words$word#(5)words$word#(5)words$word)option) s997_0=
+ ((case s997_0 of
+ s998_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s998_0)) of
+ SOME ((op, s999_0)) =>
+ (case ((string_drop s998_0 s999_0)) of
+ s1000_0 =>
+ (case ((spc_matches_prefix0 s1000_0)) of
+ SOME ((() , s1001_0)) =>
+ (case ((string_drop s1000_0 s1001_0)) of
+ s1002_0 =>
+ (case ((reg_name_matches_prefix s1002_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1003_0)) =>
+ (case ((string_drop s1002_0 s1003_0)) of
+ s1004_0 =>
+ (case ((sep_matches_prefix s1004_0)) of
+ SOME ((() , s1005_0)) =>
+ (case ((string_drop s1004_0 s1005_0)) of
+ s1006_0 =>
+ (case ((reg_name_matches_prefix s1006_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1007_0)) =>
+ (case ((string_drop s1006_0 s1007_0)) of
+ s1008_0 =>
+ (case ((sep_matches_prefix s1008_0)) of
+ SOME ((() , s1009_0)) =>
+ (case ((string_drop s1008_0 s1009_0)) of
+ s1010_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1010_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1011_0)) =>
+ let p0_ = (string_drop s1010_0 s1011_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s980_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s980_:string ->((5)words$word#(5)words$word#(12)words$word)option) s981_0=
+ (let s982_0 = s981_0 in
+ if ((string_startswith s982_0 "addiw")) then
+ (case ((string_drop s982_0 ((string_length "addiw")))) of
+ s983_0 =>
+ (case ((spc_matches_prefix0 s983_0)) of
+ SOME ((() , s984_0)) =>
+ (case ((string_drop s983_0 s984_0)) of
+ s985_0 =>
+ (case ((reg_name_matches_prefix s985_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s986_0)) =>
+ (case ((string_drop s985_0 s986_0)) of
+ s987_0 =>
+ (case ((sep_matches_prefix s987_0)) of
+ SOME ((() , s988_0)) =>
+ (case ((string_drop s987_0 s988_0)) of
+ s989_0 =>
+ (case ((reg_name_matches_prefix s989_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s990_0)) =>
+ (case ((string_drop s989_0 s990_0)) of
+ s991_0 =>
+ (case ((sep_matches_prefix s991_0)) of
+ SOME ((() , s992_0)) =>
+ (case ((string_drop s991_0 s992_0)) of
+ s993_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s993_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s994_0)) =>
+ let p0_ = (string_drop s993_0 s994_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s952_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s952_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s953_0=
+ (let s954_0 = s953_0 in
+ if ((string_startswith s954_0 "s")) then
+ (case ((string_drop s954_0 ((string_length "s")))) of
+ s955_0 =>
+ (case ((size_mnemonic_matches_prefix s955_0)) of
+ SOME ((size1, s956_0)) =>
+ (case ((string_drop s955_0 s956_0)) of
+ s957_0 =>
+ (case ((maybe_aq_matches_prefix s957_0)) of
+ SOME ((aq, s958_0)) =>
+ (case ((string_drop s957_0 s958_0)) of
+ s959_0 =>
+ (case ((maybe_rl_matches_prefix s959_0)) of
+ SOME ((rl, s960_0)) =>
+ (case ((string_drop s959_0 s960_0)) of
+ s961_0 =>
+ (case ((spc_matches_prefix0 s961_0)) of
+ SOME ((() , s962_0)) =>
+ (case ((string_drop s961_0 s962_0)) of
+ s963_0 =>
+ (case ((reg_name_matches_prefix s963_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s964_0)) =>
+ (case ((string_drop s963_0 s964_0)) of
+ s965_0 =>
+ (case ((sep_matches_prefix s965_0)) of
+ SOME ((() , s966_0)) =>
+ (case ((string_drop s965_0 s966_0)) of
+ s967_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s967_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s968_0)) =>
+ (case ((string_drop s967_0 s968_0)) of
+ s969_0 =>
+ (case ((opt_spc_matches_prefix0 s969_0)) of
+ SOME ((() , s970_0)) =>
+ let s971_0 = (string_drop s969_0 s970_0) in
+ if ((string_startswith s971_0 "(")) then
+ (case ((string_drop s971_0 ((string_length "(")))) of
+ s972_0 =>
+ (case ((opt_spc_matches_prefix0 s972_0)) of
+ SOME ((() , s973_0)) =>
+ (case ((string_drop s972_0 s973_0)) of
+ s974_0 =>
+ (case ((reg_name_matches_prefix s974_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s975_0)) =>
+ (case ((string_drop s974_0 s975_0)) of
+ s976_0 =>
+ (case ((opt_spc_matches_prefix0 s976_0)) of
+ SOME ((() , s977_0)) =>
+ let s978_0 = (string_drop s976_0 s977_0) in
+ if ((string_startswith s978_0 ")")) then
+ let p0_ = (string_drop s978_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rs2, imm, rs1) else NONE
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s922_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s922_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s923_0=
+ (let s924_0 = s923_0 in
+ if ((string_startswith s924_0 "l")) then
+ (case ((string_drop s924_0 ((string_length "l")))) of
+ s925_0 =>
+ (case ((size_mnemonic_matches_prefix s925_0)) of
+ SOME ((size1, s926_0)) =>
+ (case ((string_drop s925_0 s926_0)) of
+ s927_0 =>
+ (case ((maybe_u_matches_prefix s927_0)) of
+ SOME ((is_unsigned, s928_0)) =>
+ (case ((string_drop s927_0 s928_0)) of
+ s929_0 =>
+ (case ((maybe_aq_matches_prefix s929_0)) of
+ SOME ((aq, s930_0)) =>
+ (case ((string_drop s929_0 s930_0)) of
+ s931_0 =>
+ (case ((maybe_rl_matches_prefix s931_0)) of
+ SOME ((rl, s932_0)) =>
+ (case ((string_drop s931_0 s932_0)) of
+ s933_0 =>
+ (case ((spc_matches_prefix0 s933_0)) of
+ SOME ((() , s934_0)) =>
+ (case ((string_drop s933_0 s934_0)) of
+ s935_0 =>
+ (case ((reg_name_matches_prefix s935_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s936_0)) =>
+ (case ((string_drop s935_0 s936_0)) of
+ s937_0 =>
+ (case ((sep_matches_prefix s937_0)) of
+ SOME ((() , s938_0)) =>
+ (case ((string_drop s937_0 s938_0)) of
+ s939_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s939_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s940_0)) =>
+ (case ((string_drop s939_0 s940_0)) of
+ s941_0 =>
+ (case ((opt_spc_matches_prefix0 s941_0)) of
+ SOME ((() , s942_0)) =>
+ let s943_0 = (string_drop s941_0 s942_0) in
+ if ((string_startswith s943_0 "(")) then
+ (case ((string_drop s943_0 ((string_length "(")))) of
+ s944_0 =>
+ (case ((opt_spc_matches_prefix0 s944_0)) of
+ SOME ((() , s945_0)) =>
+ (case ((string_drop s944_0 s945_0)) of
+ s946_0 =>
+ (case ((reg_name_matches_prefix s946_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s947_0)) =>
+ (case ((string_drop s946_0 s947_0)) of
+ s948_0 =>
+ (case ((opt_spc_matches_prefix0 s948_0)) of
+ SOME ((() , s949_0)) =>
+ let s950_0 = (string_drop s948_0 s949_0) in
+ if ((string_startswith s950_0 ")")) then
+ let p0_ = (string_drop s950_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, is_unsigned, aq, rl, rd, imm, rs1)
+ else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s905_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s905_:string ->(rop#(5)words$word#(5)words$word#(5)words$word)option) s906_0=
+ ((case s906_0 of
+ s907_0 =>
+ (case ((rtype_mnemonic_matches_prefix s907_0)) of
+ SOME ((op, s908_0)) =>
+ (case ((string_drop s907_0 s908_0)) of
+ s909_0 =>
+ (case ((spc_matches_prefix0 s909_0)) of
+ SOME ((() , s910_0)) =>
+ (case ((string_drop s909_0 s910_0)) of
+ s911_0 =>
+ (case ((reg_name_matches_prefix s911_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s912_0)) =>
+ (case ((string_drop s911_0 s912_0)) of
+ s913_0 =>
+ (case ((sep_matches_prefix s913_0)) of
+ SOME ((() , s914_0)) =>
+ (case ((string_drop s913_0 s914_0)) of
+ s915_0 =>
+ (case ((reg_name_matches_prefix s915_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s916_0)) =>
+ (case ((string_drop s915_0 s916_0)) of
+ s917_0 =>
+ (case ((sep_matches_prefix s917_0)) of
+ SOME ((() , s918_0)) =>
+ (case ((string_drop s917_0 s918_0)) of
+ s919_0 =>
+ (case ((reg_name_matches_prefix s919_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s920_0)) =>
+ let p0_ = (string_drop s919_0 s920_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s888_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s888_:string ->(sop#(5)words$word#(5)words$word#(6)words$word)option) s889_0=
+ ((case s889_0 of
+ s890_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s890_0)) of
+ SOME ((op, s891_0)) =>
+ (case ((string_drop s890_0 s891_0)) of
+ s892_0 =>
+ (case ((spc_matches_prefix0 s892_0)) of
+ SOME ((() , s893_0)) =>
+ (case ((string_drop s892_0 s893_0)) of
+ s894_0 =>
+ (case ((reg_name_matches_prefix s894_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s895_0)) =>
+ (case ((string_drop s894_0 s895_0)) of
+ s896_0 =>
+ (case ((sep_matches_prefix s896_0)) of
+ SOME ((() , s897_0)) =>
+ (case ((string_drop s896_0 s897_0)) of
+ s898_0 =>
+ (case ((reg_name_matches_prefix s898_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s899_0)) =>
+ (case ((string_drop s898_0 s899_0)) of
+ s900_0 =>
+ (case ((sep_matches_prefix s900_0)) of
+ SOME ((() , s901_0)) =>
+ (case ((string_drop s900_0 s901_0)) of
+ s902_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s902_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s903_0)) =>
+ let p0_ = (string_drop s902_0 s903_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s871_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s871_:string ->(iop#(5)words$word#(5)words$word#(12)words$word)option) s872_0=
+ ((case s872_0 of
+ s873_0 =>
+ (case ((itype_mnemonic_matches_prefix s873_0)) of
+ SOME ((op, s874_0)) =>
+ (case ((string_drop s873_0 s874_0)) of
+ s875_0 =>
+ (case ((spc_matches_prefix0 s875_0)) of
+ SOME ((() , s876_0)) =>
+ (case ((string_drop s875_0 s876_0)) of
+ s877_0 =>
+ (case ((reg_name_matches_prefix s877_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s878_0)) =>
+ (case ((string_drop s877_0 s878_0)) of
+ s879_0 =>
+ (case ((sep_matches_prefix s879_0)) of
+ SOME ((() , s880_0)) =>
+ (case ((string_drop s879_0 s880_0)) of
+ s881_0 =>
+ (case ((reg_name_matches_prefix s881_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s882_0)) =>
+ (case ((string_drop s881_0 s882_0)) of
+ s883_0 =>
+ (case ((sep_matches_prefix s883_0)) of
+ SOME ((() , s884_0)) =>
+ (case ((string_drop s883_0 s884_0)) of
+ s885_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s885_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s886_0)) =>
+ let p0_ = (string_drop s885_0 s886_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s854_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))*)
+
+val _ = Define `
+ ((s854_:string ->(bop#(5)words$word#(5)words$word#(13)words$word)option) s855_0=
+ ((case s855_0 of
+ s856_0 =>
+ (case ((btype_mnemonic_matches_prefix s856_0)) of
+ SOME ((op, s857_0)) =>
+ (case ((string_drop s856_0 s857_0)) of
+ s858_0 =>
+ (case ((spc_matches_prefix0 s858_0)) of
+ SOME ((() , s859_0)) =>
+ (case ((string_drop s858_0 s859_0)) of
+ s860_0 =>
+ (case ((reg_name_matches_prefix s860_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s861_0)) =>
+ (case ((string_drop s860_0 s861_0)) of
+ s862_0 =>
+ (case ((sep_matches_prefix s862_0)) of
+ SOME ((() , s863_0)) =>
+ (case ((string_drop s862_0 s863_0)) of
+ s864_0 =>
+ (case ((reg_name_matches_prefix s864_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s865_0)) =>
+ (case ((string_drop s864_0 s865_0)) of
+ s866_0 =>
+ (case ((sep_matches_prefix s866_0)) of
+ SOME ((() , s867_0)) =>
+ (case ((string_drop s866_0 s867_0)) of
+ s868_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s868_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s869_0)) =>
+ let p0_ = (string_drop s868_0 s869_0) in
+ if (((p0_ = ""))) then SOME (op, rs1, rs2, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s838_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s838_:string ->((5)words$word#(5)words$word#(12)words$word)option) s839_0=
+ (let s840_0 = s839_0 in
+ if ((string_startswith s840_0 "jalr")) then
+ (case ((string_drop s840_0 ((string_length "jalr")))) of
+ s841_0 =>
+ (case ((spc_matches_prefix0 s841_0)) of
+ SOME ((() , s842_0)) =>
+ (case ((string_drop s841_0 s842_0)) of
+ s843_0 =>
+ (case ((reg_name_matches_prefix s843_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s844_0)) =>
+ (case ((string_drop s843_0 s844_0)) of
+ s845_0 =>
+ (case ((sep_matches_prefix s845_0)) of
+ SOME ((() , s846_0)) =>
+ (case ((string_drop s845_0 s846_0)) of
+ s847_0 =>
+ (case ((reg_name_matches_prefix s847_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s848_0)) =>
+ (case ((string_drop s847_0 s848_0)) of
+ s849_0 =>
+ (case ((sep_matches_prefix s849_0)) of
+ SOME ((() , s850_0)) =>
+ (case ((string_drop s849_0 s850_0)) of
+ s851_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s851_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s852_0)) =>
+ let p0_ = (string_drop s851_0 s852_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s826_ : string -> maybe ((mword ty5 * mword ty21))*)
+
+val _ = Define `
+ ((s826_:string ->((5)words$word#(21)words$word)option) s827_0=
+ (let s828_0 = s827_0 in
+ if ((string_startswith s828_0 "jal")) then
+ (case ((string_drop s828_0 ((string_length "jal")))) of
+ s829_0 =>
+ (case ((spc_matches_prefix0 s829_0)) of
+ SOME ((() , s830_0)) =>
+ (case ((string_drop s829_0 s830_0)) of
+ s831_0 =>
+ (case ((reg_name_matches_prefix s831_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s832_0)) =>
+ (case ((string_drop s831_0 s832_0)) of
+ s833_0 =>
+ (case ((sep_matches_prefix s833_0)) of
+ SOME ((() , s834_0)) =>
+ (case ((string_drop s833_0 s834_0)) of
+ s835_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s835_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s836_0)) =>
+ let p0_ = (string_drop s835_0 s836_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s813_ : string -> maybe ((uop * mword ty5 * mword ty20))*)
+
+val _ = Define `
+ ((s813_:string ->(uop#(5)words$word#(20)words$word)option) s814_0=
+ ((case s814_0 of
+ s815_0 =>
+ (case ((utype_mnemonic_matches_prefix s815_0)) of
+ SOME ((op, s816_0)) =>
+ (case ((string_drop s815_0 s816_0)) of
+ s817_0 =>
+ (case ((spc_matches_prefix0 s817_0)) of
+ SOME ((() , s818_0)) =>
+ (case ((string_drop s817_0 s818_0)) of
+ s819_0 =>
+ (case ((reg_name_matches_prefix s819_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s820_0)) =>
+ (case ((string_drop s819_0 s820_0)) of
+ s821_0 =>
+ (case ((sep_matches_prefix s821_0)) of
+ SOME ((() , s822_0)) =>
+ (case ((string_drop s821_0 s822_0)) of
+ s823_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s823_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s824_0)) =>
+ let p0_ = (string_drop s823_0 s824_0) in
+ if (((p0_ = ""))) then SOME (op, rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_backwards:string ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg_=
+ (let s825_0 = arg_ in
+ if ((case ((s813_ s825_0 : ((uop # 5 words$word # 20 words$word))option)) of
+ SOME ((op, rd, imm)) => T
+ | _ => F
+ )) then (case (s813_ s825_0 : (( uop # 5 words$word # 20 words$word)) option) of
+ (SOME ((op, rd, imm))) =>
+ sail2_state_monad$returnS (UTYPE (imm, rd, op))
+ )
+ else if ((case ((s826_ s825_0 : (( 5 words$word # 21 words$word))option)) of
+ SOME ((rd, imm)) => T
+ | _ => F
+ )) then (case (s826_ s825_0 : (( 5 words$word # 21 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (RISCV_JAL (imm, rd))
+ )
+ else if ((case ((s838_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => T
+ | _ => F
+ )) then (case (s838_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ sail2_state_monad$returnS (RISCV_JALR (imm, rs1, rd))
+ )
+ else if ((case ((s854_ s825_0 : ((bop # 5 words$word # 5 words$word # 13 words$word))option)) of
+ SOME ((op, rs1, rs2, imm)) => T
+ | _ => F
+ )) then (case
+ (s854_ s825_0 : (( bop # 5 words$word # 5 words$word # 13 words$word)) option) of
+ (SOME ((op, rs1, rs2, imm))) =>
+ sail2_state_monad$returnS (BTYPE (imm, rs2, rs1, op))
+ )
+ else if ((case ((s871_ s825_0 : ((iop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, imm)) => T
+ | _ => F
+ )) then (case
+ (s871_ s825_0 : (( iop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, imm))) =>
+ sail2_state_monad$returnS (ITYPE (imm, rs1, rd, op))
+ )
+ else if ((case ((s888_ s825_0 : ((sop # 5 words$word # 5 words$word # 6 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => T
+ | _ => F
+ )) then (case
+ (s888_ s825_0 : (( sop # 5 words$word # 5 words$word # 6 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTIOP (shamt, rs1, rd, op))
+ )
+ else if ((case ((s905_ s825_0 : ((rop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s905_ s825_0 : (( rop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (RTYPE (rs2, rs1, rd, op))
+ )
+ else if ((case ((s922_ s825_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s922_ s825_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ sail2_state_monad$returnS (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl))
+ )
+ else if ((case ((s952_ s825_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s952_ s825_0 : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1))) =>
+ sail2_state_monad$returnS (STORE (imm, rs2, rs1, size1, aq, rl))
+ )
+ else if ((case ((s980_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s980_ s825_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ sail2_state_monad$returnS (ADDIW (imm, rs1, rd))
+ )
+ else if ((case ((s996_ s825_0 : ((sop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s996_ s825_0 : (( sop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTW (shamt, rs1, rd, op))
+ )
+ else if ((case ((s1013_ s825_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1013_ s825_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (RTYPEW (rs2, rs1, rd, op))
+ )
+ else if ((case ((s1030_ s825_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1030_ s825_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ sail2_state_monad$returnS (SHIFTIWOP (shamt, rs1, rd, op))
+ )
+ else if ((case ((s1047_ s825_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1047_ s825_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ sail2_state_monad$returnS (FENCE (pred, succ))
+ )
+ else if ((case ((s1059_ s825_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1059_ s825_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ sail2_state_monad$returnS (FENCE_TSO (pred, succ))
+ )
+ else if (((s825_0 = "fence.i"))) then sail2_state_monad$returnS (FENCEI () )
+ else if (((s825_0 = "ecall"))) then sail2_state_monad$returnS (ECALL () )
+ else if (((s825_0 = "mret"))) then sail2_state_monad$returnS (MRET () )
+ else if (((s825_0 = "sret"))) then sail2_state_monad$returnS (SRET () )
+ else if (((s825_0 = "ebreak"))) then sail2_state_monad$returnS (EBREAK () )
+ else if (((s825_0 = "wfi"))) then sail2_state_monad$returnS (WFI () )
+ else if ((case ((s1071_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rs1, rs2)) => T
+ | _ => F
+ )) then (case (s1071_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rs1, rs2))) =>
+ sail2_state_monad$returnS (SFENCE_VMA (rs1, rs2))
+ )
+ else if ((case ((s1083_ s825_0 : ((word_width # bool # bool # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1083_ s825_0 : (( word_width # bool # bool # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1))) =>
+ sail2_state_monad$returnS (LOADRES (aq, rl, rs1, size1, rd))
+ )
+ else if ((case ((s1101_ s825_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1101_ s825_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (STORECON (aq, rl, rs2, rs1, size1, rd))
+ )
+ else if ((case ((s1123_ s825_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1123_ s825_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (AMO (op, aq, rl, rs2, rs1, width, rd))
+ )
+ else if (((s825_0 = "c.nop"))) then sail2_state_monad$returnS (C_NOP () )
+ else if ((case ((s1147_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rdc, nzimm)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s1147_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rdc, nzimm))) =>
+ sail2_state_monad$returnS (C_ADDI4SPN (rdc, nzimm))
+ )
+ else if ((case ((s1159_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => T
+ | _ => F
+ )) then (case (s1159_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ sail2_state_monad$returnS (C_LW (uimm, rsc, rdc))
+ )
+ else if ((case ((s1175_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1175_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ sail2_state_monad$returnS (C_LD (uimm, rsc, rdc))
+ )
+ else if ((case ((s1191_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => T
+ | _ => F
+ )) then (case
+ (s1191_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ sail2_state_monad$returnS (C_SW (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1207_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1207_ s825_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ sail2_state_monad$returnS (C_SD (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1223_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, nzi)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1223_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, nzi))) =>
+ sail2_state_monad$returnS (C_ADDI (nzi, rsd))
+ )
+ else if ((case ((s1235_ s825_0 : ( 11 words$word)option)) of
+ SOME (imm) => ((( 64 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s1235_ s825_0 : ( 11 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_JAL imm)
+ )
+ else if ((case ((s1243_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1243_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ sail2_state_monad$returnS (C_ADDIW (imm, rsd))
+ )
+ else if ((case ((s1255_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1255_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (C_LI (imm, rd))
+ )
+ else if ((case ((s1267_ s825_0 : ( 6 words$word)option)) of
+ SOME (imm) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1267_ s825_0 : ( 6 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_ADDI16SP imm)
+ )
+ else if ((case ((s1275_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s1275_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ sail2_state_monad$returnS (C_LUI (imm, rd))
+ )
+ else if ((case ((s1287_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1287_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SRLI (shamt, rsd))
+ )
+ else if ((case ((s1299_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s1299_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SRAI (shamt, rsd))
+ )
+ else if ((case ((s1311_ s825_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => T
+ | _ => F
+ )) then (case (s1311_ s825_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ sail2_state_monad$returnS (C_ANDI (imm, rsd))
+ )
+ else if ((case ((s1323_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1323_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_SUB (rsd, rs2))
+ )
+ else if ((case ((s1335_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1335_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_XOR (rsd, rs2))
+ )
+ else if ((case ((s1347_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1347_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_OR (rsd, rs2))
+ )
+ else if ((case ((s1359_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s1359_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_AND (rsd, rs2))
+ )
+ else if ((case ((s1371_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1371_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_SUBW (rsd, rs2))
+ )
+ else if ((case ((s1383_ s825_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1383_ s825_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_ADDW (rsd, rs2))
+ )
+ else if ((case ((s1395_ s825_0 : ( 11 words$word)option)) of
+ SOME (imm) => T
+ | _ => F
+ )) then (case (s1395_ s825_0 : ( 11 words$word) option) of
+ (SOME (imm)) =>
+ sail2_state_monad$returnS (C_J imm)
+ )
+ else if ((case ((s1403_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s1403_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ sail2_state_monad$returnS (C_BEQZ (imm, rs))
+ )
+ else if ((case ((s1415_ s825_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s1415_ s825_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ sail2_state_monad$returnS (C_BNEZ (imm, rs))
+ )
+ else if ((case ((s1427_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1427_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ sail2_state_monad$returnS (C_SLLI (shamt, rsd))
+ )
+ else if ((case ((s1439_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1439_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_LWSP (uimm, rd))
+ )
+ else if ((case ((s1451_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s1451_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_LDSP (uimm, rd))
+ )
+ else if ((case ((s1463_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => T
+ | _ => F
+ )) then (case (s1463_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ sail2_state_monad$returnS (C_SWSP (uimm, rd))
+ )
+ else if ((case ((s1475_ s825_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rs2, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1475_ s825_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rs2, uimm))) =>
+ sail2_state_monad$returnS (C_SDSP (uimm, rs2))
+ )
+ else if ((case ((s1487_ s825_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1487_ s825_0 : ( 5 words$word) option) of
+ (SOME (rs1)) =>
+ sail2_state_monad$returnS (C_JR rs1)
+ )
+ else if ((case ((s1495_ s825_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s1495_ s825_0 : ( 5 words$word) option) of
+ (SOME (rs1)) =>
+ sail2_state_monad$returnS (C_JALR rs1)
+ )
+ else if ((case ((s1503_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1503_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs2))) =>
+ sail2_state_monad$returnS (C_MV (rd, rs2))
+ )
+ else if (((s825_0 = "c.ebreak"))) then sail2_state_monad$returnS (C_EBREAK () )
+ else if ((case ((s1515_ s825_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s1515_ s825_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ sail2_state_monad$returnS (C_ADD (rsd, rs2))
+ )
+ else if ((case ((s1527_ s825_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1527_ s825_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (MUL (rs2, rs1, rd, high, signed1, signed2))
+ )
+ else if ((case ((s1544_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1544_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (DIV0 (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1562_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1562_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (REM (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1580_ s825_0 : (( 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1580_ s825_0 : (( 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (MULW (rs2, rs1, rd))
+ )
+ else if ((case ((s1596_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1596_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (DIVW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1615_ s825_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1615_ s825_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ sail2_state_monad$returnS (REMW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1634_ s825_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s1634_ s825_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, T, op))
+ )
+ else if ((case ((s1652_ s825_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s1652_ s825_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ sail2_state_monad$returnS (CSR (csr, rs1, rd, F, op))
+ )
+ else if (((s825_0 = "uret"))) then sail2_state_monad$returnS (URET () )
+ else if ((case ((s1669_ s825_0 : ( 32 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s1669_ s825_0 : ( 32 words$word) option) of
+ (SOME (s)) =>
+ sail2_state_monad$returnS (ILLEGAL s)
+ )
+ else if ((case ((s1677_ s825_0 : ( 16 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s1677_ s825_0 : ( 16 words$word) option) of
+ (SOME (s)) =>
+ sail2_state_monad$returnS (C_ILLEGAL s)
+ )
+ else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "Pattern match failure at unknown location") (sail2_state_monad$exitS () )))`;
+
+
+(*val assembly_forwards_matches : ast -> bool*)
+
+val _ = Define `
+ ((assembly_forwards_matches:ast -> bool) arg_=
+ ((case arg_ of
+ UTYPE ((imm, rd, op)) => T
+ | RISCV_JAL ((imm, rd)) => T
+ | RISCV_JALR ((imm, rs1, rd)) => T
+ | BTYPE ((imm, rs2, rs1, op)) => T
+ | ITYPE ((imm, rs1, rd, op)) => T
+ | SHIFTIOP ((shamt, rs1, rd, op)) => T
+ | RTYPE ((rs2, rs1, rd, op)) => T
+ | LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl)) => T
+ | STORE ((imm, rs2, rs1, size1, aq, rl)) => T
+ | ADDIW ((imm, rs1, rd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | SHIFTW ((shamt, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | SHIFTIWOP ((shamt, rs1, rd, op)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | FENCE ((pred, succ)) => T
+ | FENCE_TSO ((pred, succ)) => T
+ | FENCEI (() ) => T
+ | ECALL (() ) => T
+ | MRET (() ) => T
+ | SRET (() ) => T
+ | EBREAK (() ) => T
+ | WFI (() ) => T
+ | SFENCE_VMA ((rs1, rs2)) => T
+ | LOADRES ((aq, rl, rs1, size1, rd)) => T
+ | STORECON ((aq, rl, rs2, rs1, size1, rd)) => T
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) => T
+ | C_NOP (() ) => T
+ | C_ADDI4SPN ((rdc, nzimm)) =>
+ if (((nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then
+ T else F
+ | C_LW ((uimm, rsc, rdc)) => T
+ | C_LD ((uimm, rsc, rdc)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_SW ((uimm, rsc1, rsc2)) => T
+ | C_SD ((uimm, rsc1, rsc2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_ADDI ((nzi, rsd)) =>
+ if ((((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_JAL (imm) =>
+ if ((((( 64 : int): ii) = (( 32 : int): ii)))) then T else F
+ | C_ADDIW ((imm, rsd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_LI ((imm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_ADDI16SP (imm) =>
+ if (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_LUI ((imm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\
+ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then
+ T else F
+ | C_SRLI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_SRAI ((shamt, rsd)) =>
+ if (((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then
+ T else F
+ | C_ANDI ((imm, rsd)) => T
+ | C_SUB ((rsd, rs2)) => T
+ | C_XOR ((rsd, rs2)) => T
+ | C_OR ((rsd, rs2)) => T
+ | C_AND ((rsd, rs2)) => T
+ | C_SUBW ((rsd, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_ADDW ((rsd, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_J (imm) => T
+ | C_BEQZ ((imm, rs)) => T
+ | C_BNEZ ((imm, rs)) => T
+ | C_SLLI ((shamt, rsd)) =>
+ if ((((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\
+ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_LWSP ((uimm, rd)) =>
+ if (((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_LDSP ((uimm, rd)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ ((((( 64 : int): ii) = (( 64 : int): ii))))))) then T else
+ F
+ | C_SWSP ((uimm, rd)) => T
+ | C_SDSP ((uimm, rs2)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | C_JR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_JALR (rs1) =>
+ if (((((regidx_to_regno rs1)) <> ((regidx_to_regno zreg))))) then T else F
+ | C_MV ((rd, rs2)) =>
+ if ((((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | C_EBREAK (() ) => T
+ | C_ADD ((rsd, rs2)) =>
+ if ((((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\
+ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg)))))))) then
+ T else F
+ | MUL ((rs2, rs1, rd, high, signed1, signed2)) => T
+ | DIV0 ((rs2, rs1, rd, s)) => T
+ | REM ((rs2, rs1, rd, s)) => T
+ | MULW ((rs2, rs1, rd)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | DIVW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | REMW ((rs2, rs1, rd, s)) =>
+ if ((((( 64 : int): ii) = (( 64 : int): ii)))) then T else F
+ | CSR ((csr, rs1, rd, T, op)) => T
+ | CSR ((csr, rs1, rd, F, op)) => T
+ | URET (() ) => T
+ | ILLEGAL (s) => T
+ | C_ILLEGAL (s) => T
+ )))`;
+
+
+(*val assembly_backwards_matches : string -> bool*)
+
+(*val _s2549_ : string -> maybe (mword ty16)*)
+
+val _ = Define `
+ ((s2549_:string ->((16)words$word)option) s2550_0=
+ (let s2551_0 = s2550_0 in
+ if ((string_startswith s2551_0 "c.illegal")) then
+ (case ((string_drop s2551_0 ((string_length "c.illegal")))) of
+ s2552_0 =>
+ (case ((spc_matches_prefix0 s2552_0)) of
+ SOME ((() , s2553_0)) =>
+ (case ((string_drop s2552_0 s2553_0)) of
+ s2554_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2554_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s2555_0)) =>
+ let p0_ = (string_drop s2554_0 s2555_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2541_ : string -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((s2541_:string ->((32)words$word)option) s2542_0=
+ (let s2543_0 = s2542_0 in
+ if ((string_startswith s2543_0 "illegal")) then
+ (case ((string_drop s2543_0 ((string_length "illegal")))) of
+ s2544_0 =>
+ (case ((spc_matches_prefix0 s2544_0)) of
+ SOME ((() , s2545_0)) =>
+ (case ((string_drop s2544_0 s2545_0)) of
+ s2546_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2546_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s2547_0)) =>
+ let p0_ = (string_drop s2546_0 s2547_0) in
+ if (((p0_ = ""))) then SOME s else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2524_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s2524_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s2525_0=
+ ((case s2525_0 of
+ s2526_0 =>
+ (case ((csr_mnemonic_matches_prefix s2526_0)) of
+ SOME ((op, s2527_0)) =>
+ (case ((string_drop s2526_0 s2527_0)) of
+ s2528_0 =>
+ (case ((spc_matches_prefix0 s2528_0)) of
+ SOME ((() , s2529_0)) =>
+ (case ((string_drop s2528_0 s2529_0)) of
+ s2530_0 =>
+ (case ((reg_name_matches_prefix s2530_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2531_0)) =>
+ (case ((string_drop s2530_0 s2531_0)) of
+ s2532_0 =>
+ (case ((sep_matches_prefix s2532_0)) of
+ SOME ((() , s2533_0)) =>
+ (case ((string_drop s2532_0 s2533_0)) of
+ s2534_0 =>
+ (case ((reg_name_matches_prefix s2534_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2535_0)) =>
+ (case ((string_drop s2534_0 s2535_0)) of
+ s2536_0 =>
+ (case ((sep_matches_prefix s2536_0)) of
+ SOME ((() , s2537_0)) =>
+ (case ((string_drop s2536_0 s2537_0)) of
+ s2538_0 =>
+ (case ((csr_name_map_matches_prefix s2538_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s2539_0)) =>
+ let p0_ = (string_drop s2538_0 s2539_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2506_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s2506_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word)option) s2507_0=
+ ((case s2507_0 of
+ s2508_0 =>
+ (case ((csr_mnemonic_matches_prefix s2508_0)) of
+ SOME ((op, s2509_0)) =>
+ let s2510_0 = (string_drop s2508_0 s2509_0) in
+ if ((string_startswith s2510_0 "i")) then
+ (case ((string_drop s2510_0 ((string_length "i")))) of
+ s2511_0 =>
+ (case ((spc_matches_prefix0 s2511_0)) of
+ SOME ((() , s2512_0)) =>
+ (case ((string_drop s2511_0 s2512_0)) of
+ s2513_0 =>
+ (case ((reg_name_matches_prefix s2513_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2514_0)) =>
+ (case ((string_drop s2513_0 s2514_0)) of
+ s2515_0 =>
+ (case ((sep_matches_prefix s2515_0)) of
+ SOME ((() , s2516_0)) =>
+ (case ((string_drop s2515_0 s2516_0)) of
+ s2517_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2517_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2518_0)) =>
+ (case ((string_drop s2517_0 s2518_0)) of
+ s2519_0 =>
+ (case ((sep_matches_prefix s2519_0)) of
+ SOME ((() , s2520_0)) =>
+ (case ((string_drop s2519_0 s2520_0)) of
+ s2521_0 =>
+ (case ((csr_name_map_matches_prefix s2521_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s2522_0)) =>
+ let p0_ = (string_drop s2521_0 s2522_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, csr) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2487_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2487_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2488_0=
+ (let s2489_0 = s2488_0 in
+ if ((string_startswith s2489_0 "rem")) then
+ (case ((string_drop s2489_0 ((string_length "rem")))) of
+ s2490_0 =>
+ (case ((maybe_not_u_matches_prefix s2490_0)) of
+ SOME ((s, s2491_0)) =>
+ let s2492_0 = (string_drop s2490_0 s2491_0) in
+ if ((string_startswith s2492_0 "w")) then
+ (case ((string_drop s2492_0 ((string_length "w")))) of
+ s2493_0 =>
+ (case ((spc_matches_prefix0 s2493_0)) of
+ SOME ((() , s2494_0)) =>
+ (case ((string_drop s2493_0 s2494_0)) of
+ s2495_0 =>
+ (case ((reg_name_matches_prefix s2495_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2496_0)) =>
+ (case ((string_drop s2495_0 s2496_0)) of
+ s2497_0 =>
+ (case ((sep_matches_prefix s2497_0)) of
+ SOME ((() , s2498_0)) =>
+ (case ((string_drop s2497_0 s2498_0)) of
+ s2499_0 =>
+ (case ((reg_name_matches_prefix s2499_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2500_0)) =>
+ (case ((string_drop s2499_0 s2500_0)) of
+ s2501_0 =>
+ (case ((sep_matches_prefix s2501_0)) of
+ SOME ((() , s2502_0)) =>
+ (case ((string_drop s2501_0 s2502_0)) of
+ s2503_0 =>
+ (case ((reg_name_matches_prefix s2503_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2504_0)) =>
+ let p0_ = (string_drop s2503_0 s2504_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2468_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2468_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2469_0=
+ (let s2470_0 = s2469_0 in
+ if ((string_startswith s2470_0 "div")) then
+ (case ((string_drop s2470_0 ((string_length "div")))) of
+ s2471_0 =>
+ (case ((maybe_not_u_matches_prefix s2471_0)) of
+ SOME ((s, s2472_0)) =>
+ let s2473_0 = (string_drop s2471_0 s2472_0) in
+ if ((string_startswith s2473_0 "w")) then
+ (case ((string_drop s2473_0 ((string_length "w")))) of
+ s2474_0 =>
+ (case ((spc_matches_prefix0 s2474_0)) of
+ SOME ((() , s2475_0)) =>
+ (case ((string_drop s2474_0 s2475_0)) of
+ s2476_0 =>
+ (case ((reg_name_matches_prefix s2476_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2477_0)) =>
+ (case ((string_drop s2476_0 s2477_0)) of
+ s2478_0 =>
+ (case ((sep_matches_prefix s2478_0)) of
+ SOME ((() , s2479_0)) =>
+ (case ((string_drop s2478_0 s2479_0)) of
+ s2480_0 =>
+ (case ((reg_name_matches_prefix s2480_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2481_0)) =>
+ (case ((string_drop s2480_0 s2481_0)) of
+ s2482_0 =>
+ (case ((sep_matches_prefix s2482_0)) of
+ SOME ((() , s2483_0)) =>
+ (case ((string_drop s2482_0 s2483_0)) of
+ s2484_0 =>
+ (case ((reg_name_matches_prefix s2484_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2485_0)) =>
+ let p0_ = (string_drop s2484_0 s2485_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2452_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2452_:string ->((5)words$word#(5)words$word#(5)words$word)option) s2453_0=
+ (let s2454_0 = s2453_0 in
+ if ((string_startswith s2454_0 "mulw")) then
+ (case ((string_drop s2454_0 ((string_length "mulw")))) of
+ s2455_0 =>
+ (case ((spc_matches_prefix0 s2455_0)) of
+ SOME ((() , s2456_0)) =>
+ (case ((string_drop s2455_0 s2456_0)) of
+ s2457_0 =>
+ (case ((reg_name_matches_prefix s2457_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2458_0)) =>
+ (case ((string_drop s2457_0 s2458_0)) of
+ s2459_0 =>
+ (case ((sep_matches_prefix s2459_0)) of
+ SOME ((() , s2460_0)) =>
+ (case ((string_drop s2459_0 s2460_0)) of
+ s2461_0 =>
+ (case ((reg_name_matches_prefix s2461_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2462_0)) =>
+ (case ((string_drop s2461_0 s2462_0)) of
+ s2463_0 =>
+ (case ((sep_matches_prefix s2463_0)) of
+ SOME ((() , s2464_0)) =>
+ (case ((string_drop s2463_0 s2464_0)) of
+ s2465_0 =>
+ (case ((reg_name_matches_prefix s2465_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2466_0)) =>
+ let p0_ = (string_drop s2465_0 s2466_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2434_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2434_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2435_0=
+ (let s2436_0 = s2435_0 in
+ if ((string_startswith s2436_0 "rem")) then
+ (case ((string_drop s2436_0 ((string_length "rem")))) of
+ s2437_0 =>
+ (case ((maybe_not_u_matches_prefix s2437_0)) of
+ SOME ((s, s2438_0)) =>
+ (case ((string_drop s2437_0 s2438_0)) of
+ s2439_0 =>
+ (case ((spc_matches_prefix0 s2439_0)) of
+ SOME ((() , s2440_0)) =>
+ (case ((string_drop s2439_0 s2440_0)) of
+ s2441_0 =>
+ (case ((reg_name_matches_prefix s2441_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2442_0)) =>
+ (case ((string_drop s2441_0 s2442_0)) of
+ s2443_0 =>
+ (case ((sep_matches_prefix s2443_0)) of
+ SOME ((() , s2444_0)) =>
+ (case ((string_drop s2443_0 s2444_0)) of
+ s2445_0 =>
+ (case ((reg_name_matches_prefix s2445_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2446_0)) =>
+ (case ((string_drop s2445_0 s2446_0)) of
+ s2447_0 =>
+ (case ((sep_matches_prefix s2447_0)) of
+ SOME ((() , s2448_0)) =>
+ (case ((string_drop s2447_0 s2448_0)) of
+ s2449_0 =>
+ (case ((reg_name_matches_prefix s2449_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2450_0)) =>
+ let p0_ = (string_drop s2449_0 s2450_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2416_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2416_:string ->(bool#(5)words$word#(5)words$word#(5)words$word)option) s2417_0=
+ (let s2418_0 = s2417_0 in
+ if ((string_startswith s2418_0 "div")) then
+ (case ((string_drop s2418_0 ((string_length "div")))) of
+ s2419_0 =>
+ (case ((maybe_not_u_matches_prefix s2419_0)) of
+ SOME ((s, s2420_0)) =>
+ (case ((string_drop s2419_0 s2420_0)) of
+ s2421_0 =>
+ (case ((spc_matches_prefix0 s2421_0)) of
+ SOME ((() , s2422_0)) =>
+ (case ((string_drop s2421_0 s2422_0)) of
+ s2423_0 =>
+ (case ((reg_name_matches_prefix s2423_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2424_0)) =>
+ (case ((string_drop s2423_0 s2424_0)) of
+ s2425_0 =>
+ (case ((sep_matches_prefix s2425_0)) of
+ SOME ((() , s2426_0)) =>
+ (case ((string_drop s2425_0 s2426_0)) of
+ s2427_0 =>
+ (case ((reg_name_matches_prefix s2427_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2428_0)) =>
+ (case ((string_drop s2427_0 s2428_0)) of
+ s2429_0 =>
+ (case ((sep_matches_prefix s2429_0)) of
+ SOME ((() , s2430_0)) =>
+ (case ((string_drop s2429_0 s2430_0)) of
+ s2431_0 =>
+ (case ((reg_name_matches_prefix s2431_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2432_0)) =>
+ let p0_ = (string_drop s2431_0 s2432_0) in
+ if (((p0_ = ""))) then SOME (s, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2399_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2399_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s2400_0=
+ ((case s2400_0 of
+ s2401_0 =>
+ (case ((mul_mnemonic_matches_prefix s2401_0)) of
+ SOME (((high, signed1, signed2), s2402_0)) =>
+ (case ((string_drop s2401_0 s2402_0)) of
+ s2403_0 =>
+ (case ((spc_matches_prefix0 s2403_0)) of
+ SOME ((() , s2404_0)) =>
+ (case ((string_drop s2403_0 s2404_0)) of
+ s2405_0 =>
+ (case ((reg_name_matches_prefix s2405_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2406_0)) =>
+ (case ((string_drop s2405_0 s2406_0)) of
+ s2407_0 =>
+ (case ((sep_matches_prefix s2407_0)) of
+ SOME ((() , s2408_0)) =>
+ (case ((string_drop s2407_0 s2408_0)) of
+ s2409_0 =>
+ (case ((reg_name_matches_prefix s2409_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2410_0)) =>
+ (case ((string_drop s2409_0 s2410_0)) of
+ s2411_0 =>
+ (case ((sep_matches_prefix s2411_0)) of
+ SOME ((() , s2412_0)) =>
+ (case ((string_drop s2411_0 s2412_0)) of
+ s2413_0 =>
+ (case ((reg_name_matches_prefix s2413_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2414_0)) =>
+ let p0_ = (string_drop s2413_0 s2414_0) in
+ if (((p0_ = ""))) then SOME (high, signed1, signed2, rd, rs1, rs2) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2387_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2387_:string ->((5)words$word#(5)words$word)option) s2388_0=
+ (let s2389_0 = s2388_0 in
+ if ((string_startswith s2389_0 "c.add")) then
+ (case ((string_drop s2389_0 ((string_length "c.add")))) of
+ s2390_0 =>
+ (case ((spc_matches_prefix0 s2390_0)) of
+ SOME ((() , s2391_0)) =>
+ (case ((string_drop s2390_0 s2391_0)) of
+ s2392_0 =>
+ (case ((reg_name_matches_prefix s2392_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2393_0)) =>
+ (case ((string_drop s2392_0 s2393_0)) of
+ s2394_0 =>
+ (case ((sep_matches_prefix s2394_0)) of
+ SOME ((() , s2395_0)) =>
+ (case ((string_drop s2394_0 s2395_0)) of
+ s2396_0 =>
+ (case ((reg_name_matches_prefix s2396_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2397_0)) =>
+ let p0_ = (string_drop s2396_0 s2397_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2375_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s2375_:string ->((5)words$word#(5)words$word)option) s2376_0=
+ (let s2377_0 = s2376_0 in
+ if ((string_startswith s2377_0 "c.mv")) then
+ (case ((string_drop s2377_0 ((string_length "c.mv")))) of
+ s2378_0 =>
+ (case ((spc_matches_prefix0 s2378_0)) of
+ SOME ((() , s2379_0)) =>
+ (case ((string_drop s2378_0 s2379_0)) of
+ s2380_0 =>
+ (case ((reg_name_matches_prefix s2380_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2381_0)) =>
+ (case ((string_drop s2380_0 s2381_0)) of
+ s2382_0 =>
+ (case ((sep_matches_prefix s2382_0)) of
+ SOME ((() , s2383_0)) =>
+ (case ((string_drop s2382_0 s2383_0)) of
+ s2384_0 =>
+ (case ((reg_name_matches_prefix s2384_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2385_0)) =>
+ let p0_ = (string_drop s2384_0 s2385_0) in
+ if (((p0_ = ""))) then SOME (rd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2367_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s2367_:string ->((5)words$word)option) s2368_0=
+ (let s2369_0 = s2368_0 in
+ if ((string_startswith s2369_0 "c.jalr")) then
+ (case ((string_drop s2369_0 ((string_length "c.jalr")))) of
+ s2370_0 =>
+ (case ((spc_matches_prefix0 s2370_0)) of
+ SOME ((() , s2371_0)) =>
+ (case ((string_drop s2370_0 s2371_0)) of
+ s2372_0 =>
+ (case ((reg_name_matches_prefix s2372_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2373_0)) =>
+ let p0_ = (string_drop s2372_0 s2373_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2359_ : string -> maybe (mword ty5)*)
+
+val _ = Define `
+ ((s2359_:string ->((5)words$word)option) s2360_0=
+ (let s2361_0 = s2360_0 in
+ if ((string_startswith s2361_0 "c.jr")) then
+ (case ((string_drop s2361_0 ((string_length "c.jr")))) of
+ s2362_0 =>
+ (case ((spc_matches_prefix0 s2362_0)) of
+ SOME ((() , s2363_0)) =>
+ (case ((string_drop s2362_0 s2363_0)) of
+ s2364_0 =>
+ (case ((reg_name_matches_prefix s2364_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2365_0)) =>
+ let p0_ = (string_drop s2364_0 s2365_0) in
+ if (((p0_ = ""))) then SOME rs1 else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2347_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2347_:string ->((5)words$word#(6)words$word)option) s2348_0=
+ (let s2349_0 = s2348_0 in
+ if ((string_startswith s2349_0 "c.sdsp")) then
+ (case ((string_drop s2349_0 ((string_length "c.sdsp")))) of
+ s2350_0 =>
+ (case ((spc_matches_prefix0 s2350_0)) of
+ SOME ((() , s2351_0)) =>
+ (case ((string_drop s2350_0 s2351_0)) of
+ s2352_0 =>
+ (case ((reg_name_matches_prefix s2352_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2353_0)) =>
+ (case ((string_drop s2352_0 s2353_0)) of
+ s2354_0 =>
+ (case ((sep_matches_prefix s2354_0)) of
+ SOME ((() , s2355_0)) =>
+ (case ((string_drop s2354_0 s2355_0)) of
+ s2356_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2356_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2357_0)) =>
+ let p0_ = (string_drop s2356_0 s2357_0) in
+ if (((p0_ = ""))) then SOME (rs2, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2335_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2335_:string ->((5)words$word#(6)words$word)option) s2336_0=
+ (let s2337_0 = s2336_0 in
+ if ((string_startswith s2337_0 "c.swsp")) then
+ (case ((string_drop s2337_0 ((string_length "c.swsp")))) of
+ s2338_0 =>
+ (case ((spc_matches_prefix0 s2338_0)) of
+ SOME ((() , s2339_0)) =>
+ (case ((string_drop s2338_0 s2339_0)) of
+ s2340_0 =>
+ (case ((reg_name_matches_prefix s2340_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2341_0)) =>
+ (case ((string_drop s2340_0 s2341_0)) of
+ s2342_0 =>
+ (case ((sep_matches_prefix s2342_0)) of
+ SOME ((() , s2343_0)) =>
+ (case ((string_drop s2342_0 s2343_0)) of
+ s2344_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2344_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2345_0)) =>
+ let p0_ = (string_drop s2344_0 s2345_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2323_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2323_:string ->((5)words$word#(6)words$word)option) s2324_0=
+ (let s2325_0 = s2324_0 in
+ if ((string_startswith s2325_0 "c.ldsp")) then
+ (case ((string_drop s2325_0 ((string_length "c.ldsp")))) of
+ s2326_0 =>
+ (case ((spc_matches_prefix0 s2326_0)) of
+ SOME ((() , s2327_0)) =>
+ (case ((string_drop s2326_0 s2327_0)) of
+ s2328_0 =>
+ (case ((reg_name_matches_prefix s2328_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2329_0)) =>
+ (case ((string_drop s2328_0 s2329_0)) of
+ s2330_0 =>
+ (case ((sep_matches_prefix s2330_0)) of
+ SOME ((() , s2331_0)) =>
+ (case ((string_drop s2330_0 s2331_0)) of
+ s2332_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2332_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2333_0)) =>
+ let p0_ = (string_drop s2332_0 s2333_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2311_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2311_:string ->((5)words$word#(6)words$word)option) s2312_0=
+ (let s2313_0 = s2312_0 in
+ if ((string_startswith s2313_0 "c.lwsp")) then
+ (case ((string_drop s2313_0 ((string_length "c.lwsp")))) of
+ s2314_0 =>
+ (case ((spc_matches_prefix0 s2314_0)) of
+ SOME ((() , s2315_0)) =>
+ (case ((string_drop s2314_0 s2315_0)) of
+ s2316_0 =>
+ (case ((reg_name_matches_prefix s2316_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2317_0)) =>
+ (case ((string_drop s2316_0 s2317_0)) of
+ s2318_0 =>
+ (case ((sep_matches_prefix s2318_0)) of
+ SOME ((() , s2319_0)) =>
+ (case ((string_drop s2318_0 s2319_0)) of
+ s2320_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2320_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s2321_0)) =>
+ let p0_ = (string_drop s2320_0 s2321_0) in
+ if (((p0_ = ""))) then SOME (rd, uimm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2299_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2299_:string ->((5)words$word#(6)words$word)option) s2300_0=
+ (let s2301_0 = s2300_0 in
+ if ((string_startswith s2301_0 "c.slli")) then
+ (case ((string_drop s2301_0 ((string_length "c.slli")))) of
+ s2302_0 =>
+ (case ((spc_matches_prefix0 s2302_0)) of
+ SOME ((() , s2303_0)) =>
+ (case ((string_drop s2302_0 s2303_0)) of
+ s2304_0 =>
+ (case ((reg_name_matches_prefix s2304_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2305_0)) =>
+ (case ((string_drop s2304_0 s2305_0)) of
+ s2306_0 =>
+ (case ((sep_matches_prefix s2306_0)) of
+ SOME ((() , s2307_0)) =>
+ (case ((string_drop s2306_0 s2307_0)) of
+ s2308_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2308_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2309_0)) =>
+ let p0_ = (string_drop s2308_0 s2309_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2287_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2287_:string ->((3)words$word#(8)words$word)option) s2288_0=
+ (let s2289_0 = s2288_0 in
+ if ((string_startswith s2289_0 "c.bnez")) then
+ (case ((string_drop s2289_0 ((string_length "c.bnez")))) of
+ s2290_0 =>
+ (case ((spc_matches_prefix0 s2290_0)) of
+ SOME ((() , s2291_0)) =>
+ (case ((string_drop s2290_0 s2291_0)) of
+ s2292_0 =>
+ (case ((creg_name_matches_prefix s2292_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s2293_0)) =>
+ (case ((string_drop s2292_0 s2293_0)) of
+ s2294_0 =>
+ (case ((sep_matches_prefix s2294_0)) of
+ SOME ((() , s2295_0)) =>
+ (case ((string_drop s2294_0 s2295_0)) of
+ s2296_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2296_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s2297_0)) =>
+ let p0_ = (string_drop s2296_0 s2297_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2275_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2275_:string ->((3)words$word#(8)words$word)option) s2276_0=
+ (let s2277_0 = s2276_0 in
+ if ((string_startswith s2277_0 "c.beqz")) then
+ (case ((string_drop s2277_0 ((string_length "c.beqz")))) of
+ s2278_0 =>
+ (case ((spc_matches_prefix0 s2278_0)) of
+ SOME ((() , s2279_0)) =>
+ (case ((string_drop s2278_0 s2279_0)) of
+ s2280_0 =>
+ (case ((creg_name_matches_prefix s2280_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s2281_0)) =>
+ (case ((string_drop s2280_0 s2281_0)) of
+ s2282_0 =>
+ (case ((sep_matches_prefix s2282_0)) of
+ SOME ((() , s2283_0)) =>
+ (case ((string_drop s2282_0 s2283_0)) of
+ s2284_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2284_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s2285_0)) =>
+ let p0_ = (string_drop s2284_0 s2285_0) in
+ if (((p0_ = ""))) then SOME (rs, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2267_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s2267_:string ->((11)words$word)option) s2268_0=
+ (let s2269_0 = s2268_0 in
+ if ((string_startswith s2269_0 "c.j")) then
+ (case ((string_drop s2269_0 ((string_length "c.j")))) of
+ s2270_0 =>
+ (case ((spc_matches_prefix0 s2270_0)) of
+ SOME ((() , s2271_0)) =>
+ (case ((string_drop s2270_0 s2271_0)) of
+ s2272_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2272_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s2273_0)) =>
+ let p0_ = (string_drop s2272_0 s2273_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2255_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2255_:string ->((3)words$word#(3)words$word)option) s2256_0=
+ (let s2257_0 = s2256_0 in
+ if ((string_startswith s2257_0 "c.addw")) then
+ (case ((string_drop s2257_0 ((string_length "c.addw")))) of
+ s2258_0 =>
+ (case ((spc_matches_prefix0 s2258_0)) of
+ SOME ((() , s2259_0)) =>
+ (case ((string_drop s2258_0 s2259_0)) of
+ s2260_0 =>
+ (case ((creg_name_matches_prefix s2260_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2261_0)) =>
+ (case ((string_drop s2260_0 s2261_0)) of
+ s2262_0 =>
+ (case ((sep_matches_prefix s2262_0)) of
+ SOME ((() , s2263_0)) =>
+ (case ((string_drop s2262_0 s2263_0)) of
+ s2264_0 =>
+ (case ((creg_name_matches_prefix s2264_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2265_0)) =>
+ let p0_ = (string_drop s2264_0 s2265_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2243_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2243_:string ->((3)words$word#(3)words$word)option) s2244_0=
+ (let s2245_0 = s2244_0 in
+ if ((string_startswith s2245_0 "c.subw")) then
+ (case ((string_drop s2245_0 ((string_length "c.subw")))) of
+ s2246_0 =>
+ (case ((spc_matches_prefix0 s2246_0)) of
+ SOME ((() , s2247_0)) =>
+ (case ((string_drop s2246_0 s2247_0)) of
+ s2248_0 =>
+ (case ((creg_name_matches_prefix s2248_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2249_0)) =>
+ (case ((string_drop s2248_0 s2249_0)) of
+ s2250_0 =>
+ (case ((sep_matches_prefix s2250_0)) of
+ SOME ((() , s2251_0)) =>
+ (case ((string_drop s2250_0 s2251_0)) of
+ s2252_0 =>
+ (case ((creg_name_matches_prefix s2252_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2253_0)) =>
+ let p0_ = (string_drop s2252_0 s2253_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2231_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2231_:string ->((3)words$word#(3)words$word)option) s2232_0=
+ (let s2233_0 = s2232_0 in
+ if ((string_startswith s2233_0 "c.and")) then
+ (case ((string_drop s2233_0 ((string_length "c.and")))) of
+ s2234_0 =>
+ (case ((spc_matches_prefix0 s2234_0)) of
+ SOME ((() , s2235_0)) =>
+ (case ((string_drop s2234_0 s2235_0)) of
+ s2236_0 =>
+ (case ((creg_name_matches_prefix s2236_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2237_0)) =>
+ (case ((string_drop s2236_0 s2237_0)) of
+ s2238_0 =>
+ (case ((sep_matches_prefix s2238_0)) of
+ SOME ((() , s2239_0)) =>
+ (case ((string_drop s2238_0 s2239_0)) of
+ s2240_0 =>
+ (case ((creg_name_matches_prefix s2240_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2241_0)) =>
+ let p0_ = (string_drop s2240_0 s2241_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2219_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2219_:string ->((3)words$word#(3)words$word)option) s2220_0=
+ (let s2221_0 = s2220_0 in
+ if ((string_startswith s2221_0 "c.or")) then
+ (case ((string_drop s2221_0 ((string_length "c.or")))) of
+ s2222_0 =>
+ (case ((spc_matches_prefix0 s2222_0)) of
+ SOME ((() , s2223_0)) =>
+ (case ((string_drop s2222_0 s2223_0)) of
+ s2224_0 =>
+ (case ((creg_name_matches_prefix s2224_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2225_0)) =>
+ (case ((string_drop s2224_0 s2225_0)) of
+ s2226_0 =>
+ (case ((sep_matches_prefix s2226_0)) of
+ SOME ((() , s2227_0)) =>
+ (case ((string_drop s2226_0 s2227_0)) of
+ s2228_0 =>
+ (case ((creg_name_matches_prefix s2228_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2229_0)) =>
+ let p0_ = (string_drop s2228_0 s2229_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2207_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2207_:string ->((3)words$word#(3)words$word)option) s2208_0=
+ (let s2209_0 = s2208_0 in
+ if ((string_startswith s2209_0 "c.xor")) then
+ (case ((string_drop s2209_0 ((string_length "c.xor")))) of
+ s2210_0 =>
+ (case ((spc_matches_prefix0 s2210_0)) of
+ SOME ((() , s2211_0)) =>
+ (case ((string_drop s2210_0 s2211_0)) of
+ s2212_0 =>
+ (case ((creg_name_matches_prefix s2212_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2213_0)) =>
+ (case ((string_drop s2212_0 s2213_0)) of
+ s2214_0 =>
+ (case ((sep_matches_prefix s2214_0)) of
+ SOME ((() , s2215_0)) =>
+ (case ((string_drop s2214_0 s2215_0)) of
+ s2216_0 =>
+ (case ((creg_name_matches_prefix s2216_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2217_0)) =>
+ let p0_ = (string_drop s2216_0 s2217_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2195_ : string -> maybe ((mword ty3 * mword ty3))*)
+
+val _ = Define `
+ ((s2195_:string ->((3)words$word#(3)words$word)option) s2196_0=
+ (let s2197_0 = s2196_0 in
+ if ((string_startswith s2197_0 "c.sub")) then
+ (case ((string_drop s2197_0 ((string_length "c.sub")))) of
+ s2198_0 =>
+ (case ((spc_matches_prefix0 s2198_0)) of
+ SOME ((() , s2199_0)) =>
+ (case ((string_drop s2198_0 s2199_0)) of
+ s2200_0 =>
+ (case ((creg_name_matches_prefix s2200_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2201_0)) =>
+ (case ((string_drop s2200_0 s2201_0)) of
+ s2202_0 =>
+ (case ((sep_matches_prefix s2202_0)) of
+ SOME ((() , s2203_0)) =>
+ (case ((string_drop s2202_0 s2203_0)) of
+ s2204_0 =>
+ (case ((creg_name_matches_prefix s2204_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s2205_0)) =>
+ let p0_ = (string_drop s2204_0 s2205_0) in
+ if (((p0_ = ""))) then SOME (rsd, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2183_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2183_:string ->((3)words$word#(6)words$word)option) s2184_0=
+ (let s2185_0 = s2184_0 in
+ if ((string_startswith s2185_0 "c.andi")) then
+ (case ((string_drop s2185_0 ((string_length "c.andi")))) of
+ s2186_0 =>
+ (case ((spc_matches_prefix0 s2186_0)) of
+ SOME ((() , s2187_0)) =>
+ (case ((string_drop s2186_0 s2187_0)) of
+ s2188_0 =>
+ (case ((creg_name_matches_prefix s2188_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2189_0)) =>
+ (case ((string_drop s2188_0 s2189_0)) of
+ s2190_0 =>
+ (case ((sep_matches_prefix s2190_0)) of
+ SOME ((() , s2191_0)) =>
+ (case ((string_drop s2190_0 s2191_0)) of
+ s2192_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2192_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2193_0)) =>
+ let p0_ = (string_drop s2192_0 s2193_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2171_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2171_:string ->((3)words$word#(6)words$word)option) s2172_0=
+ (let s2173_0 = s2172_0 in
+ if ((string_startswith s2173_0 "c.srai")) then
+ (case ((string_drop s2173_0 ((string_length "c.srai")))) of
+ s2174_0 =>
+ (case ((spc_matches_prefix0 s2174_0)) of
+ SOME ((() , s2175_0)) =>
+ (case ((string_drop s2174_0 s2175_0)) of
+ s2176_0 =>
+ (case ((creg_name_matches_prefix s2176_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2177_0)) =>
+ (case ((string_drop s2176_0 s2177_0)) of
+ s2178_0 =>
+ (case ((sep_matches_prefix s2178_0)) of
+ SOME ((() , s2179_0)) =>
+ (case ((string_drop s2178_0 s2179_0)) of
+ s2180_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2180_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2181_0)) =>
+ let p0_ = (string_drop s2180_0 s2181_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2159_ : string -> maybe ((mword ty3 * mword ty6))*)
+
+val _ = Define `
+ ((s2159_:string ->((3)words$word#(6)words$word)option) s2160_0=
+ (let s2161_0 = s2160_0 in
+ if ((string_startswith s2161_0 "c.srli")) then
+ (case ((string_drop s2161_0 ((string_length "c.srli")))) of
+ s2162_0 =>
+ (case ((spc_matches_prefix0 s2162_0)) of
+ SOME ((() , s2163_0)) =>
+ (case ((string_drop s2162_0 s2163_0)) of
+ s2164_0 =>
+ (case ((creg_name_matches_prefix s2164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s2165_0)) =>
+ (case ((string_drop s2164_0 s2165_0)) of
+ s2166_0 =>
+ (case ((sep_matches_prefix s2166_0)) of
+ SOME ((() , s2167_0)) =>
+ (case ((string_drop s2166_0 s2167_0)) of
+ s2168_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2168_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2169_0)) =>
+ let p0_ = (string_drop s2168_0 s2169_0) in
+ if (((p0_ = ""))) then SOME (rsd, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2147_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2147_:string ->((5)words$word#(6)words$word)option) s2148_0=
+ (let s2149_0 = s2148_0 in
+ if ((string_startswith s2149_0 "c.lui")) then
+ (case ((string_drop s2149_0 ((string_length "c.lui")))) of
+ s2150_0 =>
+ (case ((spc_matches_prefix0 s2150_0)) of
+ SOME ((() , s2151_0)) =>
+ (case ((string_drop s2150_0 s2151_0)) of
+ s2152_0 =>
+ (case ((reg_name_matches_prefix s2152_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2153_0)) =>
+ (case ((string_drop s2152_0 s2153_0)) of
+ s2154_0 =>
+ (case ((sep_matches_prefix s2154_0)) of
+ SOME ((() , s2155_0)) =>
+ (case ((string_drop s2154_0 s2155_0)) of
+ s2156_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2156_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2157_0)) =>
+ let p0_ = (string_drop s2156_0 s2157_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2139_ : string -> maybe (mword ty6)*)
+
+val _ = Define `
+ ((s2139_:string ->((6)words$word)option) s2140_0=
+ (let s2141_0 = s2140_0 in
+ if ((string_startswith s2141_0 "c.addi16sp")) then
+ (case ((string_drop s2141_0 ((string_length "c.addi16sp")))) of
+ s2142_0 =>
+ (case ((spc_matches_prefix0 s2142_0)) of
+ SOME ((() , s2143_0)) =>
+ (case ((string_drop s2142_0 s2143_0)) of
+ s2144_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2144_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2145_0)) =>
+ let p0_ = (string_drop s2144_0 s2145_0) in
+ if (((p0_ = ""))) then SOME imm else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2127_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2127_:string ->((5)words$word#(6)words$word)option) s2128_0=
+ (let s2129_0 = s2128_0 in
+ if ((string_startswith s2129_0 "c.li")) then
+ (case ((string_drop s2129_0 ((string_length "c.li")))) of
+ s2130_0 =>
+ (case ((spc_matches_prefix0 s2130_0)) of
+ SOME ((() , s2131_0)) =>
+ (case ((string_drop s2130_0 s2131_0)) of
+ s2132_0 =>
+ (case ((reg_name_matches_prefix s2132_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2133_0)) =>
+ (case ((string_drop s2132_0 s2133_0)) of
+ s2134_0 =>
+ (case ((sep_matches_prefix s2134_0)) of
+ SOME ((() , s2135_0)) =>
+ (case ((string_drop s2134_0 s2135_0)) of
+ s2136_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2136_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2137_0)) =>
+ let p0_ = (string_drop s2136_0 s2137_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2115_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2115_:string ->((5)words$word#(6)words$word)option) s2116_0=
+ (let s2117_0 = s2116_0 in
+ if ((string_startswith s2117_0 "c.addiw")) then
+ (case ((string_drop s2117_0 ((string_length "c.addiw")))) of
+ s2118_0 =>
+ (case ((spc_matches_prefix0 s2118_0)) of
+ SOME ((() , s2119_0)) =>
+ (case ((string_drop s2118_0 s2119_0)) of
+ s2120_0 =>
+ (case ((reg_name_matches_prefix s2120_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2121_0)) =>
+ (case ((string_drop s2120_0 s2121_0)) of
+ s2122_0 =>
+ (case ((sep_matches_prefix s2122_0)) of
+ SOME ((() , s2123_0)) =>
+ (case ((string_drop s2122_0 s2123_0)) of
+ s2124_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2124_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s2125_0)) =>
+ let p0_ = (string_drop s2124_0 s2125_0) in
+ if (((p0_ = ""))) then SOME (rsd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2107_ : string -> maybe (mword ty11)*)
+
+val _ = Define `
+ ((s2107_:string ->((11)words$word)option) s2108_0=
+ (let s2109_0 = s2108_0 in
+ if ((string_startswith s2109_0 "c.jal")) then
+ (case ((string_drop s2109_0 ((string_length "c.jal")))) of
+ s2110_0 =>
+ (case ((spc_matches_prefix0 s2110_0)) of
+ SOME ((() , s2111_0)) =>
+ (case ((string_drop s2110_0 s2111_0)) of
+ s2112_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2112_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__814, s2113_0)) =>
+ if (((((subrange_vec_dec v__814 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__814 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__814 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let p0_ = (string_drop s2112_0 s2113_0) in
+ if (((p0_ = ""))) then SOME imm else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2095_ : string -> maybe ((mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s2095_:string ->((5)words$word#(6)words$word)option) s2096_0=
+ (let s2097_0 = s2096_0 in
+ if ((string_startswith s2097_0 "c.addi")) then
+ (case ((string_drop s2097_0 ((string_length "c.addi")))) of
+ s2098_0 =>
+ (case ((spc_matches_prefix0 s2098_0)) of
+ SOME ((() , s2099_0)) =>
+ (case ((string_drop s2098_0 s2099_0)) of
+ s2100_0 =>
+ (case ((reg_name_matches_prefix s2100_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s2101_0)) =>
+ (case ((string_drop s2100_0 s2101_0)) of
+ s2102_0 =>
+ (case ((sep_matches_prefix s2102_0)) of
+ SOME ((() , s2103_0)) =>
+ (case ((string_drop s2102_0 s2103_0)) of
+ s2104_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2104_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s2105_0)) =>
+ let p0_ = (string_drop s2104_0 s2105_0) in
+ if (((p0_ = ""))) then SOME (rsd, nzi) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2079_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2079_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2080_0=
+ (let s2081_0 = s2080_0 in
+ if ((string_startswith s2081_0 "c.sd")) then
+ (case ((string_drop s2081_0 ((string_length "c.sd")))) of
+ s2082_0 =>
+ (case ((spc_matches_prefix0 s2082_0)) of
+ SOME ((() , s2083_0)) =>
+ (case ((string_drop s2082_0 s2083_0)) of
+ s2084_0 =>
+ (case ((creg_name_matches_prefix s2084_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2085_0)) =>
+ (case ((string_drop s2084_0 s2085_0)) of
+ s2086_0 =>
+ (case ((sep_matches_prefix s2086_0)) of
+ SOME ((() , s2087_0)) =>
+ (case ((string_drop s2086_0 s2087_0)) of
+ s2088_0 =>
+ (case ((creg_name_matches_prefix s2088_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2089_0)) =>
+ (case ((string_drop s2088_0 s2089_0)) of
+ s2090_0 =>
+ (case ((sep_matches_prefix s2090_0)) of
+ SOME ((() , s2091_0)) =>
+ (case ((string_drop s2090_0 s2091_0)) of
+ s2092_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2092_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__816, s2093_0)) =>
+ if (((((subrange_vec_dec v__816 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__816 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__816 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2092_0 s2093_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2063_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2063_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2064_0=
+ (let s2065_0 = s2064_0 in
+ if ((string_startswith s2065_0 "c.sw")) then
+ (case ((string_drop s2065_0 ((string_length "c.sw")))) of
+ s2066_0 =>
+ (case ((spc_matches_prefix0 s2066_0)) of
+ SOME ((() , s2067_0)) =>
+ (case ((string_drop s2066_0 s2067_0)) of
+ s2068_0 =>
+ (case ((creg_name_matches_prefix s2068_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2069_0)) =>
+ (case ((string_drop s2068_0 s2069_0)) of
+ s2070_0 =>
+ (case ((sep_matches_prefix s2070_0)) of
+ SOME ((() , s2071_0)) =>
+ (case ((string_drop s2070_0 s2071_0)) of
+ s2072_0 =>
+ (case ((creg_name_matches_prefix s2072_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2073_0)) =>
+ (case ((string_drop s2072_0 s2073_0)) of
+ s2074_0 =>
+ (case ((sep_matches_prefix s2074_0)) of
+ SOME ((() , s2075_0)) =>
+ (case ((string_drop s2074_0 s2075_0)) of
+ s2076_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2076_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__818, s2077_0)) =>
+ if (((((subrange_vec_dec v__818 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__818 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__818 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2076_0 s2077_0) in
+ if (((p0_ = ""))) then SOME (rsc1, rsc2, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2047_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2047_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2048_0=
+ (let s2049_0 = s2048_0 in
+ if ((string_startswith s2049_0 "c.ld")) then
+ (case ((string_drop s2049_0 ((string_length "c.ld")))) of
+ s2050_0 =>
+ (case ((spc_matches_prefix0 s2050_0)) of
+ SOME ((() , s2051_0)) =>
+ (case ((string_drop s2050_0 s2051_0)) of
+ s2052_0 =>
+ (case ((creg_name_matches_prefix s2052_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2053_0)) =>
+ (case ((string_drop s2052_0 s2053_0)) of
+ s2054_0 =>
+ (case ((sep_matches_prefix s2054_0)) of
+ SOME ((() , s2055_0)) =>
+ (case ((string_drop s2054_0 s2055_0)) of
+ s2056_0 =>
+ (case ((creg_name_matches_prefix s2056_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2057_0)) =>
+ (case ((string_drop s2056_0 s2057_0)) of
+ s2058_0 =>
+ (case ((sep_matches_prefix s2058_0)) of
+ SOME ((() , s2059_0)) =>
+ (case ((string_drop s2058_0 s2059_0)) of
+ s2060_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2060_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__820, s2061_0)) =>
+ if (((((subrange_vec_dec v__820 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__820 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__820 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2060_0 s2061_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2031_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))*)
+
+val _ = Define `
+ ((s2031_:string ->((3)words$word#(3)words$word#(5)words$word)option) s2032_0=
+ (let s2033_0 = s2032_0 in
+ if ((string_startswith s2033_0 "c.lw")) then
+ (case ((string_drop s2033_0 ((string_length "c.lw")))) of
+ s2034_0 =>
+ (case ((spc_matches_prefix0 s2034_0)) of
+ SOME ((() , s2035_0)) =>
+ (case ((string_drop s2034_0 s2035_0)) of
+ s2036_0 =>
+ (case ((creg_name_matches_prefix s2036_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2037_0)) =>
+ (case ((string_drop s2036_0 s2037_0)) of
+ s2038_0 =>
+ (case ((sep_matches_prefix s2038_0)) of
+ SOME ((() , s2039_0)) =>
+ (case ((string_drop s2038_0 s2039_0)) of
+ s2040_0 =>
+ (case ((creg_name_matches_prefix s2040_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2041_0)) =>
+ (case ((string_drop s2040_0 s2041_0)) of
+ s2042_0 =>
+ (case ((sep_matches_prefix s2042_0)) of
+ SOME ((() , s2043_0)) =>
+ (case ((string_drop s2042_0 s2043_0)) of
+ s2044_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2044_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__822, s2045_0)) =>
+ if (((((subrange_vec_dec v__822 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__822 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__822 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let p0_ = (string_drop s2044_0 s2045_0) in
+ if (((p0_ = ""))) then SOME (rdc, rsc, uimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2019_ : string -> maybe ((mword ty3 * mword ty8))*)
+
+val _ = Define `
+ ((s2019_:string ->((3)words$word#(8)words$word)option) s2020_0=
+ (let s2021_0 = s2020_0 in
+ if ((string_startswith s2021_0 "c.addi4spn")) then
+ (case ((string_drop s2021_0 ((string_length "c.addi4spn")))) of
+ s2022_0 =>
+ (case ((spc_matches_prefix0 s2022_0)) of
+ SOME ((() , s2023_0)) =>
+ (case ((string_drop s2022_0 s2023_0)) of
+ s2024_0 =>
+ (case ((creg_name_matches_prefix s2024_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2025_0)) =>
+ (case ((string_drop s2024_0 s2025_0)) of
+ s2026_0 =>
+ (case ((sep_matches_prefix s2026_0)) of
+ SOME ((() , s2027_0)) =>
+ (case ((string_drop s2026_0 s2027_0)) of
+ s2028_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2028_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__824, s2029_0)) =>
+ if (((((subrange_vec_dec v__824 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__824 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__824 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let p0_ = (string_drop s2028_0 s2029_0) in
+ if (((p0_ = ""))) then SOME (rdc, nzimm) else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1995_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1995_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1996_0=
+ ((case s1996_0 of
+ s1997_0 =>
+ (case ((amo_mnemonic_matches_prefix s1997_0)) of
+ SOME ((op, s1998_0)) =>
+ let s1999_0 = (string_drop s1997_0 s1998_0) in
+ if ((string_startswith s1999_0 ".")) then
+ (case ((string_drop s1999_0 ((string_length ".")))) of
+ s2000_0 =>
+ (case ((size_mnemonic_matches_prefix s2000_0)) of
+ SOME ((width, s2001_0)) =>
+ (case ((string_drop s2000_0 s2001_0)) of
+ s2002_0 =>
+ (case ((maybe_aq_matches_prefix s2002_0)) of
+ SOME ((aq, s2003_0)) =>
+ (case ((string_drop s2002_0 s2003_0)) of
+ s2004_0 =>
+ (case ((maybe_rl_matches_prefix s2004_0)) of
+ SOME ((rl, s2005_0)) =>
+ (case ((string_drop s2004_0 s2005_0)) of
+ s2006_0 =>
+ (case ((spc_matches_prefix0 s2006_0)) of
+ SOME ((() , s2007_0)) =>
+ (case ((string_drop s2006_0 s2007_0)) of
+ s2008_0 =>
+ (case ((reg_name_matches_prefix s2008_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2009_0)) =>
+ (case ((string_drop s2008_0 s2009_0)) of
+ s2010_0 =>
+ (case ((sep_matches_prefix s2010_0)) of
+ SOME ((() , s2011_0)) =>
+ (case ((string_drop s2010_0 s2011_0)) of
+ s2012_0 =>
+ (case ((reg_name_matches_prefix s2012_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2013_0)) =>
+ (case ((string_drop s2012_0 s2013_0)) of
+ s2014_0 =>
+ (case ((sep_matches_prefix s2014_0)) of
+ SOME ((() , s2015_0)) =>
+ (case ((string_drop s2014_0 s2015_0)) of
+ s2016_0 =>
+ (case ((reg_name_matches_prefix s2016_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2017_0)) =>
+ let p0_ = (string_drop s2016_0 s2017_0) in
+ if (((p0_ = ""))) then SOME (op, width, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1973_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1973_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word)option) s1974_0=
+ (let s1975_0 = s1974_0 in
+ if ((string_startswith s1975_0 "sc.")) then
+ (case ((string_drop s1975_0 ((string_length "sc.")))) of
+ s1976_0 =>
+ (case ((size_mnemonic_matches_prefix s1976_0)) of
+ SOME ((size1, s1977_0)) =>
+ (case ((string_drop s1976_0 s1977_0)) of
+ s1978_0 =>
+ (case ((maybe_aq_matches_prefix s1978_0)) of
+ SOME ((aq, s1979_0)) =>
+ (case ((string_drop s1978_0 s1979_0)) of
+ s1980_0 =>
+ (case ((maybe_rl_matches_prefix s1980_0)) of
+ SOME ((rl, s1981_0)) =>
+ (case ((string_drop s1980_0 s1981_0)) of
+ s1982_0 =>
+ (case ((spc_matches_prefix0 s1982_0)) of
+ SOME ((() , s1983_0)) =>
+ (case ((string_drop s1982_0 s1983_0)) of
+ s1984_0 =>
+ (case ((reg_name_matches_prefix s1984_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1985_0)) =>
+ (case ((string_drop s1984_0 s1985_0)) of
+ s1986_0 =>
+ (case ((sep_matches_prefix s1986_0)) of
+ SOME ((() , s1987_0)) =>
+ (case ((string_drop s1986_0 s1987_0)) of
+ s1988_0 =>
+ (case ((reg_name_matches_prefix s1988_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1989_0)) =>
+ (case ((string_drop s1988_0 s1989_0)) of
+ s1990_0 =>
+ (case ((sep_matches_prefix s1990_0)) of
+ SOME ((() , s1991_0)) =>
+ (case ((string_drop s1990_0 s1991_0)) of
+ s1992_0 =>
+ (case ((reg_name_matches_prefix s1992_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1993_0)) =>
+ let p0_ = (string_drop s1992_0 s1993_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1955_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1955_:string ->(word_width#bool#bool#(5)words$word#(5)words$word)option) s1956_0=
+ (let s1957_0 = s1956_0 in
+ if ((string_startswith s1957_0 "lr.")) then
+ (case ((string_drop s1957_0 ((string_length "lr.")))) of
+ s1958_0 =>
+ (case ((size_mnemonic_matches_prefix s1958_0)) of
+ SOME ((size1, s1959_0)) =>
+ (case ((string_drop s1958_0 s1959_0)) of
+ s1960_0 =>
+ (case ((maybe_aq_matches_prefix s1960_0)) of
+ SOME ((aq, s1961_0)) =>
+ (case ((string_drop s1960_0 s1961_0)) of
+ s1962_0 =>
+ (case ((maybe_rl_matches_prefix s1962_0)) of
+ SOME ((rl, s1963_0)) =>
+ (case ((string_drop s1962_0 s1963_0)) of
+ s1964_0 =>
+ (case ((spc_matches_prefix0 s1964_0)) of
+ SOME ((() , s1965_0)) =>
+ (case ((string_drop s1964_0 s1965_0)) of
+ s1966_0 =>
+ (case ((reg_name_matches_prefix s1966_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1967_0)) =>
+ (case ((string_drop s1966_0 s1967_0)) of
+ s1968_0 =>
+ (case ((sep_matches_prefix s1968_0)) of
+ SOME ((() , s1969_0)) =>
+ (case ((string_drop s1968_0 s1969_0)) of
+ s1970_0 =>
+ (case ((reg_name_matches_prefix s1970_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1971_0)) =>
+ let p0_ = (string_drop s1970_0 s1971_0) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rd, rs1) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1943_ : string -> maybe ((mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1943_:string ->((5)words$word#(5)words$word)option) s1944_0=
+ (let s1945_0 = s1944_0 in
+ if ((string_startswith s1945_0 "sfence.vma")) then
+ (case ((string_drop s1945_0 ((string_length "sfence.vma")))) of
+ s1946_0 =>
+ (case ((spc_matches_prefix0 s1946_0)) of
+ SOME ((() , s1947_0)) =>
+ (case ((string_drop s1946_0 s1947_0)) of
+ s1948_0 =>
+ (case ((reg_name_matches_prefix s1948_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1949_0)) =>
+ (case ((string_drop s1948_0 s1949_0)) of
+ s1950_0 =>
+ (case ((sep_matches_prefix s1950_0)) of
+ SOME ((() , s1951_0)) =>
+ (case ((string_drop s1950_0 s1951_0)) of
+ s1952_0 =>
+ (case ((reg_name_matches_prefix s1952_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1953_0)) =>
+ let p0_ = (string_drop s1952_0 s1953_0) in
+ if (((p0_ = ""))) then SOME (rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1931_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1931_:string ->((4)words$word#(4)words$word)option) s1932_0=
+ (let s1933_0 = s1932_0 in
+ if ((string_startswith s1933_0 "fence.tso")) then
+ (case ((string_drop s1933_0 ((string_length "fence.tso")))) of
+ s1934_0 =>
+ (case ((spc_matches_prefix0 s1934_0)) of
+ SOME ((() , s1935_0)) =>
+ (case ((string_drop s1934_0 s1935_0)) of
+ s1936_0 =>
+ (case ((fence_bits_matches_prefix s1936_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1937_0)) =>
+ (case ((string_drop s1936_0 s1937_0)) of
+ s1938_0 =>
+ (case ((sep_matches_prefix s1938_0)) of
+ SOME ((() , s1939_0)) =>
+ (case ((string_drop s1938_0 s1939_0)) of
+ s1940_0 =>
+ (case ((fence_bits_matches_prefix s1940_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1941_0)) =>
+ let p0_ = (string_drop s1940_0 s1941_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1919_ : string -> maybe ((mword ty4 * mword ty4))*)
+
+val _ = Define `
+ ((s1919_:string ->((4)words$word#(4)words$word)option) s1920_0=
+ (let s1921_0 = s1920_0 in
+ if ((string_startswith s1921_0 "fence")) then
+ (case ((string_drop s1921_0 ((string_length "fence")))) of
+ s1922_0 =>
+ (case ((spc_matches_prefix0 s1922_0)) of
+ SOME ((() , s1923_0)) =>
+ (case ((string_drop s1922_0 s1923_0)) of
+ s1924_0 =>
+ (case ((fence_bits_matches_prefix s1924_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s1925_0)) =>
+ (case ((string_drop s1924_0 s1925_0)) of
+ s1926_0 =>
+ (case ((sep_matches_prefix s1926_0)) of
+ SOME ((() , s1927_0)) =>
+ (case ((string_drop s1926_0 s1927_0)) of
+ s1928_0 =>
+ (case ((fence_bits_matches_prefix s1928_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s1929_0)) =>
+ let p0_ = (string_drop s1928_0 s1929_0) in
+ if (((p0_ = ""))) then SOME (pred, succ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1902_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1902_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word)option) s1903_0=
+ ((case s1903_0 of
+ s1904_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s1904_0)) of
+ SOME ((op, s1905_0)) =>
+ (case ((string_drop s1904_0 s1905_0)) of
+ s1906_0 =>
+ (case ((spc_matches_prefix0 s1906_0)) of
+ SOME ((() , s1907_0)) =>
+ (case ((string_drop s1906_0 s1907_0)) of
+ s1908_0 =>
+ (case ((reg_name_matches_prefix s1908_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1909_0)) =>
+ (case ((string_drop s1908_0 s1909_0)) of
+ s1910_0 =>
+ (case ((sep_matches_prefix s1910_0)) of
+ SOME ((() , s1911_0)) =>
+ (case ((string_drop s1910_0 s1911_0)) of
+ s1912_0 =>
+ (case ((reg_name_matches_prefix s1912_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1913_0)) =>
+ (case ((string_drop s1912_0 s1913_0)) of
+ s1914_0 =>
+ (case ((sep_matches_prefix s1914_0)) of
+ SOME ((() , s1915_0)) =>
+ (case ((string_drop s1914_0 s1915_0)) of
+ s1916_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1916_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1917_0)) =>
+ let p0_ = (string_drop s1916_0 s1917_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1885_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1885_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word)option) s1886_0=
+ ((case s1886_0 of
+ s1887_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s1887_0)) of
+ SOME ((op, s1888_0)) =>
+ (case ((string_drop s1887_0 s1888_0)) of
+ s1889_0 =>
+ (case ((spc_matches_prefix0 s1889_0)) of
+ SOME ((() , s1890_0)) =>
+ (case ((string_drop s1889_0 s1890_0)) of
+ s1891_0 =>
+ (case ((reg_name_matches_prefix s1891_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1892_0)) =>
+ (case ((string_drop s1891_0 s1892_0)) of
+ s1893_0 =>
+ (case ((sep_matches_prefix s1893_0)) of
+ SOME ((() , s1894_0)) =>
+ (case ((string_drop s1893_0 s1894_0)) of
+ s1895_0 =>
+ (case ((reg_name_matches_prefix s1895_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1896_0)) =>
+ (case ((string_drop s1895_0 s1896_0)) of
+ s1897_0 =>
+ (case ((sep_matches_prefix s1897_0)) of
+ SOME ((() , s1898_0)) =>
+ (case ((string_drop s1897_0 s1898_0)) of
+ s1899_0 =>
+ (case ((reg_name_matches_prefix s1899_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1900_0)) =>
+ let p0_ = (string_drop s1899_0 s1900_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1868_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1868_:string ->(sop#(5)words$word#(5)words$word#(5)words$word)option) s1869_0=
+ ((case s1869_0 of
+ s1870_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s1870_0)) of
+ SOME ((op, s1871_0)) =>
+ (case ((string_drop s1870_0 s1871_0)) of
+ s1872_0 =>
+ (case ((spc_matches_prefix0 s1872_0)) of
+ SOME ((() , s1873_0)) =>
+ (case ((string_drop s1872_0 s1873_0)) of
+ s1874_0 =>
+ (case ((reg_name_matches_prefix s1874_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1875_0)) =>
+ (case ((string_drop s1874_0 s1875_0)) of
+ s1876_0 =>
+ (case ((sep_matches_prefix s1876_0)) of
+ SOME ((() , s1877_0)) =>
+ (case ((string_drop s1876_0 s1877_0)) of
+ s1878_0 =>
+ (case ((reg_name_matches_prefix s1878_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1879_0)) =>
+ (case ((string_drop s1878_0 s1879_0)) of
+ s1880_0 =>
+ (case ((sep_matches_prefix s1880_0)) of
+ SOME ((() , s1881_0)) =>
+ (case ((string_drop s1880_0 s1881_0)) of
+ s1882_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1882_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s1883_0)) =>
+ let p0_ = (string_drop s1882_0 s1883_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1852_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1852_:string ->((5)words$word#(5)words$word#(12)words$word)option) s1853_0=
+ (let s1854_0 = s1853_0 in
+ if ((string_startswith s1854_0 "addiw")) then
+ (case ((string_drop s1854_0 ((string_length "addiw")))) of
+ s1855_0 =>
+ (case ((spc_matches_prefix0 s1855_0)) of
+ SOME ((() , s1856_0)) =>
+ (case ((string_drop s1855_0 s1856_0)) of
+ s1857_0 =>
+ (case ((reg_name_matches_prefix s1857_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1858_0)) =>
+ (case ((string_drop s1857_0 s1858_0)) of
+ s1859_0 =>
+ (case ((sep_matches_prefix s1859_0)) of
+ SOME ((() , s1860_0)) =>
+ (case ((string_drop s1859_0 s1860_0)) of
+ s1861_0 =>
+ (case ((reg_name_matches_prefix s1861_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1862_0)) =>
+ (case ((string_drop s1861_0 s1862_0)) of
+ s1863_0 =>
+ (case ((sep_matches_prefix s1863_0)) of
+ SOME ((() , s1864_0)) =>
+ (case ((string_drop s1863_0 s1864_0)) of
+ s1865_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1865_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1866_0)) =>
+ let p0_ = (string_drop s1865_0 s1866_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1824_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s1824_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s1825_0=
+ (let s1826_0 = s1825_0 in
+ if ((string_startswith s1826_0 "s")) then
+ (case ((string_drop s1826_0 ((string_length "s")))) of
+ s1827_0 =>
+ (case ((size_mnemonic_matches_prefix s1827_0)) of
+ SOME ((size1, s1828_0)) =>
+ (case ((string_drop s1827_0 s1828_0)) of
+ s1829_0 =>
+ (case ((maybe_aq_matches_prefix s1829_0)) of
+ SOME ((aq, s1830_0)) =>
+ (case ((string_drop s1829_0 s1830_0)) of
+ s1831_0 =>
+ (case ((maybe_rl_matches_prefix s1831_0)) of
+ SOME ((rl, s1832_0)) =>
+ (case ((string_drop s1831_0 s1832_0)) of
+ s1833_0 =>
+ (case ((spc_matches_prefix0 s1833_0)) of
+ SOME ((() , s1834_0)) =>
+ (case ((string_drop s1833_0 s1834_0)) of
+ s1835_0 =>
+ (case ((reg_name_matches_prefix s1835_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1836_0)) =>
+ (case ((string_drop s1835_0 s1836_0)) of
+ s1837_0 =>
+ (case ((sep_matches_prefix s1837_0)) of
+ SOME ((() , s1838_0)) =>
+ (case ((string_drop s1837_0 s1838_0)) of
+ s1839_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1839_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1840_0)) =>
+ (case ((string_drop s1839_0 s1840_0)) of
+ s1841_0 =>
+ (case ((opt_spc_matches_prefix0 s1841_0)) of
+ SOME ((() , s1842_0)) =>
+ let s1843_0 = (string_drop s1841_0 s1842_0) in
+ if ((string_startswith s1843_0 "(")) then
+ (case ((string_drop s1843_0 ((string_length "(")))) of
+ s1844_0 =>
+ (case ((opt_spc_matches_prefix0 s1844_0)) of
+ SOME ((() , s1845_0)) =>
+ (case ((string_drop s1844_0 s1845_0)) of
+ s1846_0 =>
+ (case ((reg_name_matches_prefix s1846_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1847_0)) =>
+ (case ((string_drop s1846_0 s1847_0)) of
+ s1848_0 =>
+ (case ((opt_spc_matches_prefix0 s1848_0)) of
+ SOME ((() , s1849_0)) =>
+ let s1850_0 = (string_drop s1848_0 s1849_0) in
+ if ((string_startswith s1850_0 ")")) then
+ let p0_ = (string_drop s1850_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, aq, rl, rs2, imm, rs1) else NONE
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1794_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))*)
+
+val _ = Define `
+ ((s1794_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word)option) s1795_0=
+ (let s1796_0 = s1795_0 in
+ if ((string_startswith s1796_0 "l")) then
+ (case ((string_drop s1796_0 ((string_length "l")))) of
+ s1797_0 =>
+ (case ((size_mnemonic_matches_prefix s1797_0)) of
+ SOME ((size1, s1798_0)) =>
+ (case ((string_drop s1797_0 s1798_0)) of
+ s1799_0 =>
+ (case ((maybe_u_matches_prefix s1799_0)) of
+ SOME ((is_unsigned, s1800_0)) =>
+ (case ((string_drop s1799_0 s1800_0)) of
+ s1801_0 =>
+ (case ((maybe_aq_matches_prefix s1801_0)) of
+ SOME ((aq, s1802_0)) =>
+ (case ((string_drop s1801_0 s1802_0)) of
+ s1803_0 =>
+ (case ((maybe_rl_matches_prefix s1803_0)) of
+ SOME ((rl, s1804_0)) =>
+ (case ((string_drop s1803_0 s1804_0)) of
+ s1805_0 =>
+ (case ((spc_matches_prefix0 s1805_0)) of
+ SOME ((() , s1806_0)) =>
+ (case ((string_drop s1805_0 s1806_0)) of
+ s1807_0 =>
+ (case ((reg_name_matches_prefix s1807_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1808_0)) =>
+ (case ((string_drop s1807_0 s1808_0)) of
+ s1809_0 =>
+ (case ((sep_matches_prefix s1809_0)) of
+ SOME ((() , s1810_0)) =>
+ (case ((string_drop s1809_0 s1810_0)) of
+ s1811_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1811_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1812_0)) =>
+ (case ((string_drop s1811_0 s1812_0)) of
+ s1813_0 =>
+ (case ((opt_spc_matches_prefix0 s1813_0)) of
+ SOME ((() , s1814_0)) =>
+ let s1815_0 = (string_drop s1813_0 s1814_0) in
+ if ((string_startswith s1815_0 "(")) then
+ (case ((string_drop s1815_0 ((string_length "(")))) of
+ s1816_0 =>
+ (case ((opt_spc_matches_prefix0 s1816_0)) of
+ SOME ((() , s1817_0)) =>
+ (case ((string_drop s1816_0 s1817_0)) of
+ s1818_0 =>
+ (case ((reg_name_matches_prefix s1818_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1819_0)) =>
+ (case ((string_drop s1818_0 s1819_0)) of
+ s1820_0 =>
+ (case ((opt_spc_matches_prefix0 s1820_0)) of
+ SOME ((() , s1821_0)) =>
+ let s1822_0 = (string_drop s1820_0 s1821_0) in
+ if ((string_startswith s1822_0 ")")) then
+ let p0_ = (string_drop s1822_0 ((string_length ")"))) in
+ if (((p0_ = ""))) then SOME (size1, is_unsigned, aq, rl, rd, imm, rs1)
+ else NONE else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1777_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))*)
+
+val _ = Define `
+ ((s1777_:string ->(rop#(5)words$word#(5)words$word#(5)words$word)option) s1778_0=
+ ((case s1778_0 of
+ s1779_0 =>
+ (case ((rtype_mnemonic_matches_prefix s1779_0)) of
+ SOME ((op, s1780_0)) =>
+ (case ((string_drop s1779_0 s1780_0)) of
+ s1781_0 =>
+ (case ((spc_matches_prefix0 s1781_0)) of
+ SOME ((() , s1782_0)) =>
+ (case ((string_drop s1781_0 s1782_0)) of
+ s1783_0 =>
+ (case ((reg_name_matches_prefix s1783_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1784_0)) =>
+ (case ((string_drop s1783_0 s1784_0)) of
+ s1785_0 =>
+ (case ((sep_matches_prefix s1785_0)) of
+ SOME ((() , s1786_0)) =>
+ (case ((string_drop s1785_0 s1786_0)) of
+ s1787_0 =>
+ (case ((reg_name_matches_prefix s1787_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1788_0)) =>
+ (case ((string_drop s1787_0 s1788_0)) of
+ s1789_0 =>
+ (case ((sep_matches_prefix s1789_0)) of
+ SOME ((() , s1790_0)) =>
+ (case ((string_drop s1789_0 s1790_0)) of
+ s1791_0 =>
+ (case ((reg_name_matches_prefix s1791_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1792_0)) =>
+ let p0_ = (string_drop s1791_0 s1792_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, rs2) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1760_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))*)
+
+val _ = Define `
+ ((s1760_:string ->(sop#(5)words$word#(5)words$word#(6)words$word)option) s1761_0=
+ ((case s1761_0 of
+ s1762_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s1762_0)) of
+ SOME ((op, s1763_0)) =>
+ (case ((string_drop s1762_0 s1763_0)) of
+ s1764_0 =>
+ (case ((spc_matches_prefix0 s1764_0)) of
+ SOME ((() , s1765_0)) =>
+ (case ((string_drop s1764_0 s1765_0)) of
+ s1766_0 =>
+ (case ((reg_name_matches_prefix s1766_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1767_0)) =>
+ (case ((string_drop s1766_0 s1767_0)) of
+ s1768_0 =>
+ (case ((sep_matches_prefix s1768_0)) of
+ SOME ((() , s1769_0)) =>
+ (case ((string_drop s1768_0 s1769_0)) of
+ s1770_0 =>
+ (case ((reg_name_matches_prefix s1770_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1771_0)) =>
+ (case ((string_drop s1770_0 s1771_0)) of
+ s1772_0 =>
+ (case ((sep_matches_prefix s1772_0)) of
+ SOME ((() , s1773_0)) =>
+ (case ((string_drop s1772_0 s1773_0)) of
+ s1774_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1774_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s1775_0)) =>
+ let p0_ = (string_drop s1774_0 s1775_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, shamt) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1743_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1743_:string ->(iop#(5)words$word#(5)words$word#(12)words$word)option) s1744_0=
+ ((case s1744_0 of
+ s1745_0 =>
+ (case ((itype_mnemonic_matches_prefix s1745_0)) of
+ SOME ((op, s1746_0)) =>
+ (case ((string_drop s1745_0 s1746_0)) of
+ s1747_0 =>
+ (case ((spc_matches_prefix0 s1747_0)) of
+ SOME ((() , s1748_0)) =>
+ (case ((string_drop s1747_0 s1748_0)) of
+ s1749_0 =>
+ (case ((reg_name_matches_prefix s1749_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1750_0)) =>
+ (case ((string_drop s1749_0 s1750_0)) of
+ s1751_0 =>
+ (case ((sep_matches_prefix s1751_0)) of
+ SOME ((() , s1752_0)) =>
+ (case ((string_drop s1751_0 s1752_0)) of
+ s1753_0 =>
+ (case ((reg_name_matches_prefix s1753_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1754_0)) =>
+ (case ((string_drop s1753_0 s1754_0)) of
+ s1755_0 =>
+ (case ((sep_matches_prefix s1755_0)) of
+ SOME ((() , s1756_0)) =>
+ (case ((string_drop s1755_0 s1756_0)) of
+ s1757_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1757_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1758_0)) =>
+ let p0_ = (string_drop s1757_0 s1758_0) in
+ if (((p0_ = ""))) then SOME (op, rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1726_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))*)
+
+val _ = Define `
+ ((s1726_:string ->(bop#(5)words$word#(5)words$word#(13)words$word)option) s1727_0=
+ ((case s1727_0 of
+ s1728_0 =>
+ (case ((btype_mnemonic_matches_prefix s1728_0)) of
+ SOME ((op, s1729_0)) =>
+ (case ((string_drop s1728_0 s1729_0)) of
+ s1730_0 =>
+ (case ((spc_matches_prefix0 s1730_0)) of
+ SOME ((() , s1731_0)) =>
+ (case ((string_drop s1730_0 s1731_0)) of
+ s1732_0 =>
+ (case ((reg_name_matches_prefix s1732_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1733_0)) =>
+ (case ((string_drop s1732_0 s1733_0)) of
+ s1734_0 =>
+ (case ((sep_matches_prefix s1734_0)) of
+ SOME ((() , s1735_0)) =>
+ (case ((string_drop s1734_0 s1735_0)) of
+ s1736_0 =>
+ (case ((reg_name_matches_prefix s1736_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s1737_0)) =>
+ (case ((string_drop s1736_0 s1737_0)) of
+ s1738_0 =>
+ (case ((sep_matches_prefix s1738_0)) of
+ SOME ((() , s1739_0)) =>
+ (case ((string_drop s1738_0 s1739_0)) of
+ s1740_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1740_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s1741_0)) =>
+ let p0_ = (string_drop s1740_0 s1741_0) in
+ if (((p0_ = ""))) then SOME (op, rs1, rs2, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s1710_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))*)
+
+val _ = Define `
+ ((s1710_:string ->((5)words$word#(5)words$word#(12)words$word)option) s1711_0=
+ (let s1712_0 = s1711_0 in
+ if ((string_startswith s1712_0 "jalr")) then
+ (case ((string_drop s1712_0 ((string_length "jalr")))) of
+ s1713_0 =>
+ (case ((spc_matches_prefix0 s1713_0)) of
+ SOME ((() , s1714_0)) =>
+ (case ((string_drop s1713_0 s1714_0)) of
+ s1715_0 =>
+ (case ((reg_name_matches_prefix s1715_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1716_0)) =>
+ (case ((string_drop s1715_0 s1716_0)) of
+ s1717_0 =>
+ (case ((sep_matches_prefix s1717_0)) of
+ SOME ((() , s1718_0)) =>
+ (case ((string_drop s1717_0 s1718_0)) of
+ s1719_0 =>
+ (case ((reg_name_matches_prefix s1719_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s1720_0)) =>
+ (case ((string_drop s1719_0 s1720_0)) of
+ s1721_0 =>
+ (case ((sep_matches_prefix s1721_0)) of
+ SOME ((() , s1722_0)) =>
+ (case ((string_drop s1721_0 s1722_0)) of
+ s1723_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1723_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s1724_0)) =>
+ let p0_ = (string_drop s1723_0 s1724_0) in
+ if (((p0_ = ""))) then SOME (rd, rs1, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1698_ : string -> maybe ((mword ty5 * mword ty21))*)
+
+val _ = Define `
+ ((s1698_:string ->((5)words$word#(21)words$word)option) s1699_0=
+ (let s1700_0 = s1699_0 in
+ if ((string_startswith s1700_0 "jal")) then
+ (case ((string_drop s1700_0 ((string_length "jal")))) of
+ s1701_0 =>
+ (case ((spc_matches_prefix0 s1701_0)) of
+ SOME ((() , s1702_0)) =>
+ (case ((string_drop s1701_0 s1702_0)) of
+ s1703_0 =>
+ (case ((reg_name_matches_prefix s1703_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1704_0)) =>
+ (case ((string_drop s1703_0 s1704_0)) of
+ s1705_0 =>
+ (case ((sep_matches_prefix s1705_0)) of
+ SOME ((() , s1706_0)) =>
+ (case ((string_drop s1705_0 s1706_0)) of
+ s1707_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s1707_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s1708_0)) =>
+ let p0_ = (string_drop s1707_0 s1708_0) in
+ if (((p0_ = ""))) then SOME (rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s1685_ : string -> maybe ((uop * mword ty5 * mword ty20))*)
+
+val _ = Define `
+ ((s1685_:string ->(uop#(5)words$word#(20)words$word)option) s1686_0=
+ ((case s1686_0 of
+ s1687_0 =>
+ (case ((utype_mnemonic_matches_prefix s1687_0)) of
+ SOME ((op, s1688_0)) =>
+ (case ((string_drop s1687_0 s1688_0)) of
+ s1689_0 =>
+ (case ((spc_matches_prefix0 s1689_0)) of
+ SOME ((() , s1690_0)) =>
+ (case ((string_drop s1689_0 s1690_0)) of
+ s1691_0 =>
+ (case ((reg_name_matches_prefix s1691_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s1692_0)) =>
+ (case ((string_drop s1691_0 s1692_0)) of
+ s1693_0 =>
+ (case ((sep_matches_prefix s1693_0)) of
+ SOME ((() , s1694_0)) =>
+ (case ((string_drop s1693_0 s1694_0)) of
+ s1695_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s1695_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s1696_0)) =>
+ let p0_ = (string_drop s1695_0 s1696_0) in
+ if (((p0_ = ""))) then SOME (op, rd, imm) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_backwards_matches:string -> bool) arg_=
+ (let s1697_0 = arg_ in
+ if ((case ((s1685_ s1697_0 : ((uop # 5 words$word # 20 words$word))option)) of
+ SOME ((op, rd, imm)) => T
+ | _ => F
+ )) then (case (s1685_ s1697_0 : (( uop # 5 words$word # 20 words$word)) option) of
+ (SOME ((op, rd, imm))) =>
+ T
+ )
+ else if ((case ((s1698_ s1697_0 : (( 5 words$word # 21 words$word))option)) of
+ SOME ((rd, imm)) => T
+ | _ => F
+ )) then (case (s1698_ s1697_0 : (( 5 words$word # 21 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s1710_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => T
+ | _ => F
+ )) then (case (s1710_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1726_ s1697_0 : ((bop # 5 words$word # 5 words$word # 13 words$word))option)) of
+ SOME ((op, rs1, rs2, imm)) => T
+ | _ => F
+ )) then (case
+ (s1726_ s1697_0 : (( bop # 5 words$word # 5 words$word # 13 words$word)) option) of
+ (SOME ((op, rs1, rs2, imm))) =>
+ T
+ )
+ else if ((case ((s1743_ s1697_0 : ((iop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, imm)) => T
+ | _ => F
+ )) then (case
+ (s1743_ s1697_0 : (( iop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1760_ s1697_0 : ((sop # 5 words$word # 5 words$word # 6 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => T
+ | _ => F
+ )) then (case
+ (s1760_ s1697_0 : (( sop # 5 words$word # 5 words$word # 6 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1777_ s1697_0 : ((rop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1777_ s1697_0 : (( rop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1794_ s1697_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1794_ s1697_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ T
+ )
+ else if ((case ((s1824_ s1697_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1824_ s1697_0 : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1))) =>
+ T
+ )
+ else if ((case ((s1852_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((rd, rs1, imm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s1852_ s1697_0 : (( 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((rd, rs1, imm))) =>
+ T
+ )
+ else if ((case ((s1868_ s1697_0 : ((sop # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1868_ s1697_0 : (( sop # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1885_ s1697_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1885_ s1697_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1902_ s1697_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, rd, rs1, shamt)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s1902_ s1697_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, rd, rs1, shamt))) =>
+ T
+ )
+ else if ((case ((s1919_ s1697_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1919_ s1697_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ T
+ )
+ else if ((case ((s1931_ s1697_0 : (( 4 words$word # 4 words$word))option)) of
+ SOME ((pred, succ)) => T
+ | _ => F
+ )) then (case (s1931_ s1697_0 : (( 4 words$word # 4 words$word)) option) of
+ (SOME ((pred, succ))) =>
+ T
+ )
+ else if (((s1697_0 = "fence.i"))) then T
+ else if (((s1697_0 = "ecall"))) then T
+ else if (((s1697_0 = "mret"))) then T
+ else if (((s1697_0 = "sret"))) then T
+ else if (((s1697_0 = "ebreak"))) then T
+ else if (((s1697_0 = "wfi"))) then T
+ else if ((case ((s1943_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rs1, rs2)) => T
+ | _ => F
+ )) then (case (s1943_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1955_ s1697_0 : ((word_width # bool # bool # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1)) => T
+ | _ => F
+ )) then (case
+ (s1955_ s1697_0 : (( word_width # bool # bool # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1))) =>
+ T
+ )
+ else if ((case ((s1973_ s1697_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1973_ s1697_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s1995_ s1697_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s1995_ s1697_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2))) =>
+ T
+ )
+ else if (((s1697_0 = "c.nop"))) then T
+ else if ((case ((s2019_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rdc, nzimm)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s2019_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rdc, nzimm))) =>
+ T
+ )
+ else if ((case ((s2031_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => T
+ | _ => F
+ )) then (case
+ (s2031_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ T
+ )
+ else if ((case ((s2047_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rdc, rsc, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2047_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rdc, rsc, uimm))) =>
+ T
+ )
+ else if ((case ((s2063_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => T
+ | _ => F
+ )) then (case
+ (s2063_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ T
+ )
+ else if ((case ((s2079_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word))option)) of
+ SOME ((rsc1, rsc2, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2079_ s1697_0 : (( 3 words$word # 3 words$word # 5 words$word)) option) of
+ (SOME ((rsc1, rsc2, uimm))) =>
+ T
+ )
+ else if ((case ((s2095_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, nzi)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2095_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, nzi))) =>
+ T
+ )
+ else if ((case ((s2107_ s1697_0 : ( 11 words$word)option)) of
+ SOME (imm) => ((( 64 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s2107_ s1697_0 : ( 11 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2115_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2115_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ T
+ )
+ else if ((case ((s2127_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2127_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s2139_ s1697_0 : ( 6 words$word)option)) of
+ SOME (imm) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2139_ s1697_0 : ( 6 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2147_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s2147_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, imm))) =>
+ T
+ )
+ else if ((case ((s2159_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2159_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2171_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s2171_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2183_ s1697_0 : (( 3 words$word # 6 words$word))option)) of
+ SOME ((rsd, imm)) => T
+ | _ => F
+ )) then (case (s2183_ s1697_0 : (( 3 words$word # 6 words$word)) option) of
+ (SOME ((rsd, imm))) =>
+ T
+ )
+ else if ((case ((s2195_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2195_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2207_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2207_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2219_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2219_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2231_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => T
+ | _ => F
+ )) then (case (s2231_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2243_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2243_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2255_ s1697_0 : (( 3 words$word # 3 words$word))option)) of
+ SOME ((rsd, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2255_ s1697_0 : (( 3 words$word # 3 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2267_ s1697_0 : ( 11 words$word)option)) of
+ SOME (imm) => T
+ | _ => F
+ )) then (case (s2267_ s1697_0 : ( 11 words$word) option) of (SOME (imm)) => T )
+ else if ((case ((s2275_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s2275_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ T
+ )
+ else if ((case ((s2287_ s1697_0 : (( 3 words$word # 8 words$word))option)) of
+ SOME ((rs, imm)) => T
+ | _ => F
+ )) then (case (s2287_ s1697_0 : (( 3 words$word # 8 words$word)) option) of
+ (SOME ((rs, imm))) =>
+ T
+ )
+ else if ((case ((s2299_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rsd, shamt)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2299_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rsd, shamt))) =>
+ T
+ )
+ else if ((case ((s2311_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2311_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2323_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s2323_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2335_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rd, uimm)) => T
+ | _ => F
+ )) then (case (s2335_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rd, uimm))) =>
+ T
+ )
+ else if ((case ((s2347_ s1697_0 : (( 5 words$word # 6 words$word))option)) of
+ SOME ((rs2, uimm)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2347_ s1697_0 : (( 5 words$word # 6 words$word)) option) of
+ (SOME ((rs2, uimm))) =>
+ T
+ )
+ else if ((case ((s2359_ s1697_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2359_ s1697_0 : ( 5 words$word) option) of (SOME (rs1)) => T )
+ else if ((case ((s2367_ s1697_0 : ( 5 words$word)option)) of
+ SOME (rs1) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s2367_ s1697_0 : ( 5 words$word) option) of (SOME (rs1)) => T )
+ else if ((case ((s2375_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2375_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs2))) =>
+ T
+ )
+ else if (((s1697_0 = "c.ebreak"))) then T
+ else if ((case ((s2387_ s1697_0 : (( 5 words$word # 5 words$word))option)) of
+ SOME ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2387_ s1697_0 : (( 5 words$word # 5 words$word)) option) of
+ (SOME ((rsd, rs2))) =>
+ T
+ )
+ else if ((case ((s2399_ s1697_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2399_ s1697_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2416_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2416_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2434_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => T
+ | _ => F
+ )) then (case
+ (s2434_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2452_ s1697_0 : (( 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s2452_ s1697_0 : (( 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2468_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2468_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2487_ s1697_0 : ((bool # 5 words$word # 5 words$word # 5 words$word))option)) of
+ SOME ((s, rd, rs1, rs2)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2487_ s1697_0 : (( bool # 5 words$word # 5 words$word # 5 words$word)) option) of
+ (SOME ((s, rd, rs1, rs2))) =>
+ T
+ )
+ else if ((case ((s2506_ s1697_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s2506_ s1697_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ T
+ )
+ else if ((case ((s2524_ s1697_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word))option)) of
+ SOME ((op, rd, rs1, csr)) => T
+ | _ => F
+ )) then (case
+ (s2524_ s1697_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word)) option) of
+ (SOME ((op, rd, rs1, csr))) =>
+ T
+ )
+ else if (((s1697_0 = "uret"))) then T
+ else if ((case ((s2541_ s1697_0 : ( 32 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s2541_ s1697_0 : ( 32 words$word) option) of (SOME (s)) => T )
+ else if ((case ((s2549_ s1697_0 : ( 16 words$word)option)) of SOME (s) => T | _ => F ))
+ then (case (s2549_ s1697_0 : ( 16 words$word) option) of (SOME (s)) => T )
+ else F))`;
+
+
+(*val assembly_matches_prefix : string -> maybe ((ast * ii))*)
+
+(*val _s3457_ : string -> maybe ((mword ty16 * string))*)
+
+val _ = Define `
+ ((s3457_:string ->((16)words$word#string)option) s3458_0=
+ (let s3459_0 = s3458_0 in
+ if ((string_startswith s3459_0 "c.illegal")) then
+ (case ((string_drop s3459_0 ((string_length "c.illegal")))) of
+ s3460_0 =>
+ (case ((spc_matches_prefix0 s3460_0)) of
+ SOME ((() , s3461_0)) =>
+ (case ((string_drop s3460_0 s3461_0)) of
+ s3462_0 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3462_0 : (( 16 words$word # ii)) option)) of
+ SOME ((s, s3463_0)) =>
+ (case ((string_drop s3462_0 s3463_0)) of s_ => SOME (s, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3449_ : string -> maybe ((mword ty32 * string))*)
+
+val _ = Define `
+ ((s3449_:string ->((32)words$word#string)option) s3450_0=
+ (let s3451_0 = s3450_0 in
+ if ((string_startswith s3451_0 "illegal")) then
+ (case ((string_drop s3451_0 ((string_length "illegal")))) of
+ s3452_0 =>
+ (case ((spc_matches_prefix0 s3452_0)) of
+ SOME ((() , s3453_0)) =>
+ (case ((string_drop s3452_0 s3453_0)) of
+ s3454_0 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3454_0 : (( 32 words$word # ii)) option)) of
+ SOME ((s, s3455_0)) =>
+ (case ((string_drop s3454_0 s3455_0)) of s_ => SOME (s, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3445_ : string -> maybe string*)
+
+val _ = Define `
+ ((s3445_:string ->(string)option) s3446_0=
+ (let s3447_0 = s3446_0 in
+ if ((string_startswith s3447_0 "uret")) then
+ (case ((string_drop s3447_0 ((string_length "uret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s3428_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s3428_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word#string)option) s3429_0=
+ ((case s3429_0 of
+ s3430_0 =>
+ (case ((csr_mnemonic_matches_prefix s3430_0)) of
+ SOME ((op, s3431_0)) =>
+ (case ((string_drop s3430_0 s3431_0)) of
+ s3432_0 =>
+ (case ((spc_matches_prefix0 s3432_0)) of
+ SOME ((() , s3433_0)) =>
+ (case ((string_drop s3432_0 s3433_0)) of
+ s3434_0 =>
+ (case ((reg_name_matches_prefix s3434_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3435_0)) =>
+ (case ((string_drop s3434_0 s3435_0)) of
+ s3436_0 =>
+ (case ((sep_matches_prefix s3436_0)) of
+ SOME ((() , s3437_0)) =>
+ (case ((string_drop s3436_0 s3437_0)) of
+ s3438_0 =>
+ (case ((reg_name_matches_prefix s3438_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3439_0)) =>
+ (case ((string_drop s3438_0 s3439_0)) of
+ s3440_0 =>
+ (case ((sep_matches_prefix s3440_0)) of
+ SOME ((() , s3441_0)) =>
+ (case ((string_drop s3440_0 s3441_0)) of
+ s3442_0 =>
+ (case ((csr_name_map_matches_prefix s3442_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s3443_0)) =>
+ (case ((string_drop s3442_0 s3443_0)) of
+ s_ => SOME (op, rd, rs1, csr, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3410_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s3410_:string ->(csrop#(5)words$word#(5)words$word#(12)words$word#string)option) s3411_0=
+ ((case s3411_0 of
+ s3412_0 =>
+ (case ((csr_mnemonic_matches_prefix s3412_0)) of
+ SOME ((op, s3413_0)) =>
+ let s3414_0 = (string_drop s3412_0 s3413_0) in
+ if ((string_startswith s3414_0 "i")) then
+ (case ((string_drop s3414_0 ((string_length "i")))) of
+ s3415_0 =>
+ (case ((spc_matches_prefix0 s3415_0)) of
+ SOME ((() , s3416_0)) =>
+ (case ((string_drop s3415_0 s3416_0)) of
+ s3417_0 =>
+ (case ((reg_name_matches_prefix s3417_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3418_0)) =>
+ (case ((string_drop s3417_0 s3418_0)) of
+ s3419_0 =>
+ (case ((sep_matches_prefix s3419_0)) of
+ SOME ((() , s3420_0)) =>
+ (case ((string_drop s3419_0 s3420_0)) of
+ s3421_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s3421_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3422_0)) =>
+ (case ((string_drop s3421_0 s3422_0)) of
+ s3423_0 =>
+ (case ((sep_matches_prefix s3423_0)) of
+ SOME ((() , s3424_0)) =>
+ (case ((string_drop s3423_0 s3424_0)) of
+ s3425_0 =>
+ (case ((csr_name_map_matches_prefix s3425_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((csr, s3426_0)) =>
+ (case ((string_drop s3425_0 s3426_0)) of
+ s_ => SOME (op, rd, rs1, csr, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3391_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3391_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3392_0=
+ (let s3393_0 = s3392_0 in
+ if ((string_startswith s3393_0 "rem")) then
+ (case ((string_drop s3393_0 ((string_length "rem")))) of
+ s3394_0 =>
+ (case ((maybe_not_u_matches_prefix s3394_0)) of
+ SOME ((s, s3395_0)) =>
+ let s3396_0 = (string_drop s3394_0 s3395_0) in
+ if ((string_startswith s3396_0 "w")) then
+ (case ((string_drop s3396_0 ((string_length "w")))) of
+ s3397_0 =>
+ (case ((spc_matches_prefix0 s3397_0)) of
+ SOME ((() , s3398_0)) =>
+ (case ((string_drop s3397_0 s3398_0)) of
+ s3399_0 =>
+ (case ((reg_name_matches_prefix s3399_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3400_0)) =>
+ (case ((string_drop s3399_0 s3400_0)) of
+ s3401_0 =>
+ (case ((sep_matches_prefix s3401_0)) of
+ SOME ((() , s3402_0)) =>
+ (case ((string_drop s3401_0 s3402_0)) of
+ s3403_0 =>
+ (case ((reg_name_matches_prefix s3403_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3404_0)) =>
+ (case ((string_drop s3403_0 s3404_0)) of
+ s3405_0 =>
+ (case ((sep_matches_prefix s3405_0)) of
+ SOME ((() , s3406_0)) =>
+ (case ((string_drop s3405_0 s3406_0)) of
+ s3407_0 =>
+ (case ((reg_name_matches_prefix s3407_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3408_0)) =>
+ (case ((string_drop s3407_0 s3408_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3372_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3372_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3373_0=
+ (let s3374_0 = s3373_0 in
+ if ((string_startswith s3374_0 "div")) then
+ (case ((string_drop s3374_0 ((string_length "div")))) of
+ s3375_0 =>
+ (case ((maybe_not_u_matches_prefix s3375_0)) of
+ SOME ((s, s3376_0)) =>
+ let s3377_0 = (string_drop s3375_0 s3376_0) in
+ if ((string_startswith s3377_0 "w")) then
+ (case ((string_drop s3377_0 ((string_length "w")))) of
+ s3378_0 =>
+ (case ((spc_matches_prefix0 s3378_0)) of
+ SOME ((() , s3379_0)) =>
+ (case ((string_drop s3378_0 s3379_0)) of
+ s3380_0 =>
+ (case ((reg_name_matches_prefix s3380_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3381_0)) =>
+ (case ((string_drop s3380_0 s3381_0)) of
+ s3382_0 =>
+ (case ((sep_matches_prefix s3382_0)) of
+ SOME ((() , s3383_0)) =>
+ (case ((string_drop s3382_0 s3383_0)) of
+ s3384_0 =>
+ (case ((reg_name_matches_prefix s3384_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3385_0)) =>
+ (case ((string_drop s3384_0 s3385_0)) of
+ s3386_0 =>
+ (case ((sep_matches_prefix s3386_0)) of
+ SOME ((() , s3387_0)) =>
+ (case ((string_drop s3386_0 s3387_0)) of
+ s3388_0 =>
+ (case ((reg_name_matches_prefix s3388_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3389_0)) =>
+ (case ((string_drop s3388_0 s3389_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3356_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3356_:string ->((5)words$word#(5)words$word#(5)words$word#string)option) s3357_0=
+ (let s3358_0 = s3357_0 in
+ if ((string_startswith s3358_0 "mulw")) then
+ (case ((string_drop s3358_0 ((string_length "mulw")))) of
+ s3359_0 =>
+ (case ((spc_matches_prefix0 s3359_0)) of
+ SOME ((() , s3360_0)) =>
+ (case ((string_drop s3359_0 s3360_0)) of
+ s3361_0 =>
+ (case ((reg_name_matches_prefix s3361_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3362_0)) =>
+ (case ((string_drop s3361_0 s3362_0)) of
+ s3363_0 =>
+ (case ((sep_matches_prefix s3363_0)) of
+ SOME ((() , s3364_0)) =>
+ (case ((string_drop s3363_0 s3364_0)) of
+ s3365_0 =>
+ (case ((reg_name_matches_prefix s3365_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3366_0)) =>
+ (case ((string_drop s3365_0 s3366_0)) of
+ s3367_0 =>
+ (case ((sep_matches_prefix s3367_0)) of
+ SOME ((() , s3368_0)) =>
+ (case ((string_drop s3367_0 s3368_0)) of
+ s3369_0 =>
+ (case ((reg_name_matches_prefix s3369_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3370_0)) =>
+ (case ((string_drop s3369_0 s3370_0)) of s_ => SOME (rd, rs1, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3338_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3338_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3339_0=
+ (let s3340_0 = s3339_0 in
+ if ((string_startswith s3340_0 "rem")) then
+ (case ((string_drop s3340_0 ((string_length "rem")))) of
+ s3341_0 =>
+ (case ((maybe_not_u_matches_prefix s3341_0)) of
+ SOME ((s, s3342_0)) =>
+ (case ((string_drop s3341_0 s3342_0)) of
+ s3343_0 =>
+ (case ((spc_matches_prefix0 s3343_0)) of
+ SOME ((() , s3344_0)) =>
+ (case ((string_drop s3343_0 s3344_0)) of
+ s3345_0 =>
+ (case ((reg_name_matches_prefix s3345_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3346_0)) =>
+ (case ((string_drop s3345_0 s3346_0)) of
+ s3347_0 =>
+ (case ((sep_matches_prefix s3347_0)) of
+ SOME ((() , s3348_0)) =>
+ (case ((string_drop s3347_0 s3348_0)) of
+ s3349_0 =>
+ (case ((reg_name_matches_prefix s3349_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3350_0)) =>
+ (case ((string_drop s3349_0 s3350_0)) of
+ s3351_0 =>
+ (case ((sep_matches_prefix s3351_0)) of
+ SOME ((() , s3352_0)) =>
+ (case ((string_drop s3351_0 s3352_0)) of
+ s3353_0 =>
+ (case ((reg_name_matches_prefix s3353_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3354_0)) =>
+ (case ((string_drop s3353_0 s3354_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3320_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3320_:string ->(bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3321_0=
+ (let s3322_0 = s3321_0 in
+ if ((string_startswith s3322_0 "div")) then
+ (case ((string_drop s3322_0 ((string_length "div")))) of
+ s3323_0 =>
+ (case ((maybe_not_u_matches_prefix s3323_0)) of
+ SOME ((s, s3324_0)) =>
+ (case ((string_drop s3323_0 s3324_0)) of
+ s3325_0 =>
+ (case ((spc_matches_prefix0 s3325_0)) of
+ SOME ((() , s3326_0)) =>
+ (case ((string_drop s3325_0 s3326_0)) of
+ s3327_0 =>
+ (case ((reg_name_matches_prefix s3327_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3328_0)) =>
+ (case ((string_drop s3327_0 s3328_0)) of
+ s3329_0 =>
+ (case ((sep_matches_prefix s3329_0)) of
+ SOME ((() , s3330_0)) =>
+ (case ((string_drop s3329_0 s3330_0)) of
+ s3331_0 =>
+ (case ((reg_name_matches_prefix s3331_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3332_0)) =>
+ (case ((string_drop s3331_0 s3332_0)) of
+ s3333_0 =>
+ (case ((sep_matches_prefix s3333_0)) of
+ SOME ((() , s3334_0)) =>
+ (case ((string_drop s3333_0 s3334_0)) of
+ s3335_0 =>
+ (case ((reg_name_matches_prefix s3335_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3336_0)) =>
+ (case ((string_drop s3335_0 s3336_0)) of
+ s_ => SOME (s, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3303_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3303_:string ->(bool#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s3304_0=
+ ((case s3304_0 of
+ s3305_0 =>
+ (case ((mul_mnemonic_matches_prefix s3305_0)) of
+ SOME (((high, signed1, signed2), s3306_0)) =>
+ (case ((string_drop s3305_0 s3306_0)) of
+ s3307_0 =>
+ (case ((spc_matches_prefix0 s3307_0)) of
+ SOME ((() , s3308_0)) =>
+ (case ((string_drop s3307_0 s3308_0)) of
+ s3309_0 =>
+ (case ((reg_name_matches_prefix s3309_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3310_0)) =>
+ (case ((string_drop s3309_0 s3310_0)) of
+ s3311_0 =>
+ (case ((sep_matches_prefix s3311_0)) of
+ SOME ((() , s3312_0)) =>
+ (case ((string_drop s3311_0 s3312_0)) of
+ s3313_0 =>
+ (case ((reg_name_matches_prefix s3313_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3314_0)) =>
+ (case ((string_drop s3313_0 s3314_0)) of
+ s3315_0 =>
+ (case ((sep_matches_prefix s3315_0)) of
+ SOME ((() , s3316_0)) =>
+ (case ((string_drop s3315_0 s3316_0)) of
+ s3317_0 =>
+ (case ((reg_name_matches_prefix s3317_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3318_0)) =>
+ (case ((string_drop s3317_0 s3318_0)) of
+ s_ => SOME (high, signed1, signed2, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s3291_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3291_:string ->((5)words$word#(5)words$word#string)option) s3292_0=
+ (let s3293_0 = s3292_0 in
+ if ((string_startswith s3293_0 "c.add")) then
+ (case ((string_drop s3293_0 ((string_length "c.add")))) of
+ s3294_0 =>
+ (case ((spc_matches_prefix0 s3294_0)) of
+ SOME ((() , s3295_0)) =>
+ (case ((string_drop s3294_0 s3295_0)) of
+ s3296_0 =>
+ (case ((reg_name_matches_prefix s3296_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3297_0)) =>
+ (case ((string_drop s3296_0 s3297_0)) of
+ s3298_0 =>
+ (case ((sep_matches_prefix s3298_0)) of
+ SOME ((() , s3299_0)) =>
+ (case ((string_drop s3298_0 s3299_0)) of
+ s3300_0 =>
+ (case ((reg_name_matches_prefix s3300_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3301_0)) =>
+ (case ((string_drop s3300_0 s3301_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3287_ : string -> maybe string*)
+
+val _ = Define `
+ ((s3287_:string ->(string)option) s3288_0=
+ (let s3289_0 = s3288_0 in
+ if ((string_startswith s3289_0 "c.ebreak")) then
+ (case ((string_drop s3289_0 ((string_length "c.ebreak")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s3275_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s3275_:string ->((5)words$word#(5)words$word#string)option) s3276_0=
+ (let s3277_0 = s3276_0 in
+ if ((string_startswith s3277_0 "c.mv")) then
+ (case ((string_drop s3277_0 ((string_length "c.mv")))) of
+ s3278_0 =>
+ (case ((spc_matches_prefix0 s3278_0)) of
+ SOME ((() , s3279_0)) =>
+ (case ((string_drop s3278_0 s3279_0)) of
+ s3280_0 =>
+ (case ((reg_name_matches_prefix s3280_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3281_0)) =>
+ (case ((string_drop s3280_0 s3281_0)) of
+ s3282_0 =>
+ (case ((sep_matches_prefix s3282_0)) of
+ SOME ((() , s3283_0)) =>
+ (case ((string_drop s3282_0 s3283_0)) of
+ s3284_0 =>
+ (case ((reg_name_matches_prefix s3284_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3285_0)) =>
+ (case ((string_drop s3284_0 s3285_0)) of s_ => SOME (rd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3267_ : string -> maybe ((mword ty5 * string))*)
+
+val _ = Define `
+ ((s3267_:string ->((5)words$word#string)option) s3268_0=
+ (let s3269_0 = s3268_0 in
+ if ((string_startswith s3269_0 "c.jalr")) then
+ (case ((string_drop s3269_0 ((string_length "c.jalr")))) of
+ s3270_0 =>
+ (case ((spc_matches_prefix0 s3270_0)) of
+ SOME ((() , s3271_0)) =>
+ (case ((string_drop s3270_0 s3271_0)) of
+ s3272_0 =>
+ (case ((reg_name_matches_prefix s3272_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3273_0)) =>
+ (case ((string_drop s3272_0 s3273_0)) of s_ => SOME (rs1, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3259_ : string -> maybe ((mword ty5 * string))*)
+
+val _ = Define `
+ ((s3259_:string ->((5)words$word#string)option) s3260_0=
+ (let s3261_0 = s3260_0 in
+ if ((string_startswith s3261_0 "c.jr")) then
+ (case ((string_drop s3261_0 ((string_length "c.jr")))) of
+ s3262_0 =>
+ (case ((spc_matches_prefix0 s3262_0)) of
+ SOME ((() , s3263_0)) =>
+ (case ((string_drop s3262_0 s3263_0)) of
+ s3264_0 =>
+ (case ((reg_name_matches_prefix s3264_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s3265_0)) =>
+ (case ((string_drop s3264_0 s3265_0)) of s_ => SOME (rs1, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3247_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3247_:string ->((5)words$word#(6)words$word#string)option) s3248_0=
+ (let s3249_0 = s3248_0 in
+ if ((string_startswith s3249_0 "c.sdsp")) then
+ (case ((string_drop s3249_0 ((string_length "c.sdsp")))) of
+ s3250_0 =>
+ (case ((spc_matches_prefix0 s3250_0)) of
+ SOME ((() , s3251_0)) =>
+ (case ((string_drop s3250_0 s3251_0)) of
+ s3252_0 =>
+ (case ((reg_name_matches_prefix s3252_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s3253_0)) =>
+ (case ((string_drop s3252_0 s3253_0)) of
+ s3254_0 =>
+ (case ((sep_matches_prefix s3254_0)) of
+ SOME ((() , s3255_0)) =>
+ (case ((string_drop s3254_0 s3255_0)) of
+ s3256_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3256_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3257_0)) =>
+ (case ((string_drop s3256_0 s3257_0)) of s_ => SOME (rs2, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3235_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3235_:string ->((5)words$word#(6)words$word#string)option) s3236_0=
+ (let s3237_0 = s3236_0 in
+ if ((string_startswith s3237_0 "c.swsp")) then
+ (case ((string_drop s3237_0 ((string_length "c.swsp")))) of
+ s3238_0 =>
+ (case ((spc_matches_prefix0 s3238_0)) of
+ SOME ((() , s3239_0)) =>
+ (case ((string_drop s3238_0 s3239_0)) of
+ s3240_0 =>
+ (case ((reg_name_matches_prefix s3240_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3241_0)) =>
+ (case ((string_drop s3240_0 s3241_0)) of
+ s3242_0 =>
+ (case ((sep_matches_prefix s3242_0)) of
+ SOME ((() , s3243_0)) =>
+ (case ((string_drop s3242_0 s3243_0)) of
+ s3244_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3244_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3245_0)) =>
+ (case ((string_drop s3244_0 s3245_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3223_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3223_:string ->((5)words$word#(6)words$word#string)option) s3224_0=
+ (let s3225_0 = s3224_0 in
+ if ((string_startswith s3225_0 "c.ldsp")) then
+ (case ((string_drop s3225_0 ((string_length "c.ldsp")))) of
+ s3226_0 =>
+ (case ((spc_matches_prefix0 s3226_0)) of
+ SOME ((() , s3227_0)) =>
+ (case ((string_drop s3226_0 s3227_0)) of
+ s3228_0 =>
+ (case ((reg_name_matches_prefix s3228_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3229_0)) =>
+ (case ((string_drop s3228_0 s3229_0)) of
+ s3230_0 =>
+ (case ((sep_matches_prefix s3230_0)) of
+ SOME ((() , s3231_0)) =>
+ (case ((string_drop s3230_0 s3231_0)) of
+ s3232_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3232_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3233_0)) =>
+ (case ((string_drop s3232_0 s3233_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3211_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3211_:string ->((5)words$word#(6)words$word#string)option) s3212_0=
+ (let s3213_0 = s3212_0 in
+ if ((string_startswith s3213_0 "c.lwsp")) then
+ (case ((string_drop s3213_0 ((string_length "c.lwsp")))) of
+ s3214_0 =>
+ (case ((spc_matches_prefix0 s3214_0)) of
+ SOME ((() , s3215_0)) =>
+ (case ((string_drop s3214_0 s3215_0)) of
+ s3216_0 =>
+ (case ((reg_name_matches_prefix s3216_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3217_0)) =>
+ (case ((string_drop s3216_0 s3217_0)) of
+ s3218_0 =>
+ (case ((sep_matches_prefix s3218_0)) of
+ SOME ((() , s3219_0)) =>
+ (case ((string_drop s3218_0 s3219_0)) of
+ s3220_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3220_0 : (( 6 words$word # ii)) option)) of
+ SOME ((uimm, s3221_0)) =>
+ (case ((string_drop s3220_0 s3221_0)) of s_ => SOME (rd, uimm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3199_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3199_:string ->((5)words$word#(6)words$word#string)option) s3200_0=
+ (let s3201_0 = s3200_0 in
+ if ((string_startswith s3201_0 "c.slli")) then
+ (case ((string_drop s3201_0 ((string_length "c.slli")))) of
+ s3202_0 =>
+ (case ((spc_matches_prefix0 s3202_0)) of
+ SOME ((() , s3203_0)) =>
+ (case ((string_drop s3202_0 s3203_0)) of
+ s3204_0 =>
+ (case ((reg_name_matches_prefix s3204_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3205_0)) =>
+ (case ((string_drop s3204_0 s3205_0)) of
+ s3206_0 =>
+ (case ((sep_matches_prefix s3206_0)) of
+ SOME ((() , s3207_0)) =>
+ (case ((string_drop s3206_0 s3207_0)) of
+ s3208_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3208_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3209_0)) =>
+ (case ((string_drop s3208_0 s3209_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3187_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s3187_:string ->((3)words$word#(8)words$word#string)option) s3188_0=
+ (let s3189_0 = s3188_0 in
+ if ((string_startswith s3189_0 "c.bnez")) then
+ (case ((string_drop s3189_0 ((string_length "c.bnez")))) of
+ s3190_0 =>
+ (case ((spc_matches_prefix0 s3190_0)) of
+ SOME ((() , s3191_0)) =>
+ (case ((string_drop s3190_0 s3191_0)) of
+ s3192_0 =>
+ (case ((creg_name_matches_prefix s3192_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s3193_0)) =>
+ (case ((string_drop s3192_0 s3193_0)) of
+ s3194_0 =>
+ (case ((sep_matches_prefix s3194_0)) of
+ SOME ((() , s3195_0)) =>
+ (case ((string_drop s3194_0 s3195_0)) of
+ s3196_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3196_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s3197_0)) =>
+ (case ((string_drop s3196_0 s3197_0)) of s_ => SOME (rs, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3175_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s3175_:string ->((3)words$word#(8)words$word#string)option) s3176_0=
+ (let s3177_0 = s3176_0 in
+ if ((string_startswith s3177_0 "c.beqz")) then
+ (case ((string_drop s3177_0 ((string_length "c.beqz")))) of
+ s3178_0 =>
+ (case ((spc_matches_prefix0 s3178_0)) of
+ SOME ((() , s3179_0)) =>
+ (case ((string_drop s3178_0 s3179_0)) of
+ s3180_0 =>
+ (case ((creg_name_matches_prefix s3180_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs, s3181_0)) =>
+ (case ((string_drop s3180_0 s3181_0)) of
+ s3182_0 =>
+ (case ((sep_matches_prefix s3182_0)) of
+ SOME ((() , s3183_0)) =>
+ (case ((string_drop s3182_0 s3183_0)) of
+ s3184_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3184_0 : (( 8 words$word # ii)) option)) of
+ SOME ((imm, s3185_0)) =>
+ (case ((string_drop s3184_0 s3185_0)) of s_ => SOME (rs, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3167_ : string -> maybe ((mword ty11 * string))*)
+
+val _ = Define `
+ ((s3167_:string ->((11)words$word#string)option) s3168_0=
+ (let s3169_0 = s3168_0 in
+ if ((string_startswith s3169_0 "c.j")) then
+ (case ((string_drop s3169_0 ((string_length "c.j")))) of
+ s3170_0 =>
+ (case ((spc_matches_prefix0 s3170_0)) of
+ SOME ((() , s3171_0)) =>
+ (case ((string_drop s3170_0 s3171_0)) of
+ s3172_0 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3172_0 : (( 11 words$word # ii)) option)) of
+ SOME ((imm, s3173_0)) =>
+ (case ((string_drop s3172_0 s3173_0)) of s_ => SOME (imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3155_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3155_:string ->((3)words$word#(3)words$word#string)option) s3156_0=
+ (let s3157_0 = s3156_0 in
+ if ((string_startswith s3157_0 "c.addw")) then
+ (case ((string_drop s3157_0 ((string_length "c.addw")))) of
+ s3158_0 =>
+ (case ((spc_matches_prefix0 s3158_0)) of
+ SOME ((() , s3159_0)) =>
+ (case ((string_drop s3158_0 s3159_0)) of
+ s3160_0 =>
+ (case ((creg_name_matches_prefix s3160_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3161_0)) =>
+ (case ((string_drop s3160_0 s3161_0)) of
+ s3162_0 =>
+ (case ((sep_matches_prefix s3162_0)) of
+ SOME ((() , s3163_0)) =>
+ (case ((string_drop s3162_0 s3163_0)) of
+ s3164_0 =>
+ (case ((creg_name_matches_prefix s3164_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3165_0)) =>
+ (case ((string_drop s3164_0 s3165_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3143_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3143_:string ->((3)words$word#(3)words$word#string)option) s3144_0=
+ (let s3145_0 = s3144_0 in
+ if ((string_startswith s3145_0 "c.subw")) then
+ (case ((string_drop s3145_0 ((string_length "c.subw")))) of
+ s3146_0 =>
+ (case ((spc_matches_prefix0 s3146_0)) of
+ SOME ((() , s3147_0)) =>
+ (case ((string_drop s3146_0 s3147_0)) of
+ s3148_0 =>
+ (case ((creg_name_matches_prefix s3148_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3149_0)) =>
+ (case ((string_drop s3148_0 s3149_0)) of
+ s3150_0 =>
+ (case ((sep_matches_prefix s3150_0)) of
+ SOME ((() , s3151_0)) =>
+ (case ((string_drop s3150_0 s3151_0)) of
+ s3152_0 =>
+ (case ((creg_name_matches_prefix s3152_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3153_0)) =>
+ (case ((string_drop s3152_0 s3153_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3131_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3131_:string ->((3)words$word#(3)words$word#string)option) s3132_0=
+ (let s3133_0 = s3132_0 in
+ if ((string_startswith s3133_0 "c.and")) then
+ (case ((string_drop s3133_0 ((string_length "c.and")))) of
+ s3134_0 =>
+ (case ((spc_matches_prefix0 s3134_0)) of
+ SOME ((() , s3135_0)) =>
+ (case ((string_drop s3134_0 s3135_0)) of
+ s3136_0 =>
+ (case ((creg_name_matches_prefix s3136_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3137_0)) =>
+ (case ((string_drop s3136_0 s3137_0)) of
+ s3138_0 =>
+ (case ((sep_matches_prefix s3138_0)) of
+ SOME ((() , s3139_0)) =>
+ (case ((string_drop s3138_0 s3139_0)) of
+ s3140_0 =>
+ (case ((creg_name_matches_prefix s3140_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3141_0)) =>
+ (case ((string_drop s3140_0 s3141_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3119_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3119_:string ->((3)words$word#(3)words$word#string)option) s3120_0=
+ (let s3121_0 = s3120_0 in
+ if ((string_startswith s3121_0 "c.or")) then
+ (case ((string_drop s3121_0 ((string_length "c.or")))) of
+ s3122_0 =>
+ (case ((spc_matches_prefix0 s3122_0)) of
+ SOME ((() , s3123_0)) =>
+ (case ((string_drop s3122_0 s3123_0)) of
+ s3124_0 =>
+ (case ((creg_name_matches_prefix s3124_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3125_0)) =>
+ (case ((string_drop s3124_0 s3125_0)) of
+ s3126_0 =>
+ (case ((sep_matches_prefix s3126_0)) of
+ SOME ((() , s3127_0)) =>
+ (case ((string_drop s3126_0 s3127_0)) of
+ s3128_0 =>
+ (case ((creg_name_matches_prefix s3128_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3129_0)) =>
+ (case ((string_drop s3128_0 s3129_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3107_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3107_:string ->((3)words$word#(3)words$word#string)option) s3108_0=
+ (let s3109_0 = s3108_0 in
+ if ((string_startswith s3109_0 "c.xor")) then
+ (case ((string_drop s3109_0 ((string_length "c.xor")))) of
+ s3110_0 =>
+ (case ((spc_matches_prefix0 s3110_0)) of
+ SOME ((() , s3111_0)) =>
+ (case ((string_drop s3110_0 s3111_0)) of
+ s3112_0 =>
+ (case ((creg_name_matches_prefix s3112_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3113_0)) =>
+ (case ((string_drop s3112_0 s3113_0)) of
+ s3114_0 =>
+ (case ((sep_matches_prefix s3114_0)) of
+ SOME ((() , s3115_0)) =>
+ (case ((string_drop s3114_0 s3115_0)) of
+ s3116_0 =>
+ (case ((creg_name_matches_prefix s3116_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3117_0)) =>
+ (case ((string_drop s3116_0 s3117_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3095_ : string -> maybe ((mword ty3 * mword ty3 * string))*)
+
+val _ = Define `
+ ((s3095_:string ->((3)words$word#(3)words$word#string)option) s3096_0=
+ (let s3097_0 = s3096_0 in
+ if ((string_startswith s3097_0 "c.sub")) then
+ (case ((string_drop s3097_0 ((string_length "c.sub")))) of
+ s3098_0 =>
+ (case ((spc_matches_prefix0 s3098_0)) of
+ SOME ((() , s3099_0)) =>
+ (case ((string_drop s3098_0 s3099_0)) of
+ s3100_0 =>
+ (case ((creg_name_matches_prefix s3100_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3101_0)) =>
+ (case ((string_drop s3100_0 s3101_0)) of
+ s3102_0 =>
+ (case ((sep_matches_prefix s3102_0)) of
+ SOME ((() , s3103_0)) =>
+ (case ((string_drop s3102_0 s3103_0)) of
+ s3104_0 =>
+ (case ((creg_name_matches_prefix s3104_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rs2, s3105_0)) =>
+ (case ((string_drop s3104_0 s3105_0)) of s_ => SOME (rsd, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3083_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3083_:string ->((3)words$word#(6)words$word#string)option) s3084_0=
+ (let s3085_0 = s3084_0 in
+ if ((string_startswith s3085_0 "c.andi")) then
+ (case ((string_drop s3085_0 ((string_length "c.andi")))) of
+ s3086_0 =>
+ (case ((spc_matches_prefix0 s3086_0)) of
+ SOME ((() , s3087_0)) =>
+ (case ((string_drop s3086_0 s3087_0)) of
+ s3088_0 =>
+ (case ((creg_name_matches_prefix s3088_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3089_0)) =>
+ (case ((string_drop s3088_0 s3089_0)) of
+ s3090_0 =>
+ (case ((sep_matches_prefix s3090_0)) of
+ SOME ((() , s3091_0)) =>
+ (case ((string_drop s3090_0 s3091_0)) of
+ s3092_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3092_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3093_0)) =>
+ (case ((string_drop s3092_0 s3093_0)) of s_ => SOME (rsd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3071_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3071_:string ->((3)words$word#(6)words$word#string)option) s3072_0=
+ (let s3073_0 = s3072_0 in
+ if ((string_startswith s3073_0 "c.srai")) then
+ (case ((string_drop s3073_0 ((string_length "c.srai")))) of
+ s3074_0 =>
+ (case ((spc_matches_prefix0 s3074_0)) of
+ SOME ((() , s3075_0)) =>
+ (case ((string_drop s3074_0 s3075_0)) of
+ s3076_0 =>
+ (case ((creg_name_matches_prefix s3076_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3077_0)) =>
+ (case ((string_drop s3076_0 s3077_0)) of
+ s3078_0 =>
+ (case ((sep_matches_prefix s3078_0)) of
+ SOME ((() , s3079_0)) =>
+ (case ((string_drop s3078_0 s3079_0)) of
+ s3080_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3080_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3081_0)) =>
+ (case ((string_drop s3080_0 s3081_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3059_ : string -> maybe ((mword ty3 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3059_:string ->((3)words$word#(6)words$word#string)option) s3060_0=
+ (let s3061_0 = s3060_0 in
+ if ((string_startswith s3061_0 "c.srli")) then
+ (case ((string_drop s3061_0 ((string_length "c.srli")))) of
+ s3062_0 =>
+ (case ((spc_matches_prefix0 s3062_0)) of
+ SOME ((() , s3063_0)) =>
+ (case ((string_drop s3062_0 s3063_0)) of
+ s3064_0 =>
+ (case ((creg_name_matches_prefix s3064_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsd, s3065_0)) =>
+ (case ((string_drop s3064_0 s3065_0)) of
+ s3066_0 =>
+ (case ((sep_matches_prefix s3066_0)) of
+ SOME ((() , s3067_0)) =>
+ (case ((string_drop s3066_0 s3067_0)) of
+ s3068_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3068_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s3069_0)) =>
+ (case ((string_drop s3068_0 s3069_0)) of s_ => SOME (rsd, shamt, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3047_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3047_:string ->((5)words$word#(6)words$word#string)option) s3048_0=
+ (let s3049_0 = s3048_0 in
+ if ((string_startswith s3049_0 "c.lui")) then
+ (case ((string_drop s3049_0 ((string_length "c.lui")))) of
+ s3050_0 =>
+ (case ((spc_matches_prefix0 s3050_0)) of
+ SOME ((() , s3051_0)) =>
+ (case ((string_drop s3050_0 s3051_0)) of
+ s3052_0 =>
+ (case ((reg_name_matches_prefix s3052_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3053_0)) =>
+ (case ((string_drop s3052_0 s3053_0)) of
+ s3054_0 =>
+ (case ((sep_matches_prefix s3054_0)) of
+ SOME ((() , s3055_0)) =>
+ (case ((string_drop s3054_0 s3055_0)) of
+ s3056_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3056_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3057_0)) =>
+ (case ((string_drop s3056_0 s3057_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3039_ : string -> maybe ((mword ty6 * string))*)
+
+val _ = Define `
+ ((s3039_:string ->((6)words$word#string)option) s3040_0=
+ (let s3041_0 = s3040_0 in
+ if ((string_startswith s3041_0 "c.addi16sp")) then
+ (case ((string_drop s3041_0 ((string_length "c.addi16sp")))) of
+ s3042_0 =>
+ (case ((spc_matches_prefix0 s3042_0)) of
+ SOME ((() , s3043_0)) =>
+ (case ((string_drop s3042_0 s3043_0)) of
+ s3044_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3044_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3045_0)) =>
+ (case ((string_drop s3044_0 s3045_0)) of s_ => SOME (imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3027_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3027_:string ->((5)words$word#(6)words$word#string)option) s3028_0=
+ (let s3029_0 = s3028_0 in
+ if ((string_startswith s3029_0 "c.li")) then
+ (case ((string_drop s3029_0 ((string_length "c.li")))) of
+ s3030_0 =>
+ (case ((spc_matches_prefix0 s3030_0)) of
+ SOME ((() , s3031_0)) =>
+ (case ((string_drop s3030_0 s3031_0)) of
+ s3032_0 =>
+ (case ((reg_name_matches_prefix s3032_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s3033_0)) =>
+ (case ((string_drop s3032_0 s3033_0)) of
+ s3034_0 =>
+ (case ((sep_matches_prefix s3034_0)) of
+ SOME ((() , s3035_0)) =>
+ (case ((string_drop s3034_0 s3035_0)) of
+ s3036_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3036_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3037_0)) =>
+ (case ((string_drop s3036_0 s3037_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3015_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s3015_:string ->((5)words$word#(6)words$word#string)option) s3016_0=
+ (let s3017_0 = s3016_0 in
+ if ((string_startswith s3017_0 "c.addiw")) then
+ (case ((string_drop s3017_0 ((string_length "c.addiw")))) of
+ s3018_0 =>
+ (case ((spc_matches_prefix0 s3018_0)) of
+ SOME ((() , s3019_0)) =>
+ (case ((string_drop s3018_0 s3019_0)) of
+ s3020_0 =>
+ (case ((reg_name_matches_prefix s3020_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3021_0)) =>
+ (case ((string_drop s3020_0 s3021_0)) of
+ s3022_0 =>
+ (case ((sep_matches_prefix s3022_0)) of
+ SOME ((() , s3023_0)) =>
+ (case ((string_drop s3022_0 s3023_0)) of
+ s3024_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3024_0 : (( 6 words$word # ii)) option)) of
+ SOME ((imm, s3025_0)) =>
+ (case ((string_drop s3024_0 s3025_0)) of s_ => SOME (rsd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s3007_ : string -> maybe ((mword ty11 * string))*)
+
+val _ = Define `
+ ((s3007_:string ->((11)words$word#string)option) s3008_0=
+ (let s3009_0 = s3008_0 in
+ if ((string_startswith s3009_0 "c.jal")) then
+ (case ((string_drop s3009_0 ((string_length "c.jal")))) of
+ s3010_0 =>
+ (case ((spc_matches_prefix0 s3010_0)) of
+ SOME ((() , s3011_0)) =>
+ (case ((string_drop s3010_0 s3011_0)) of
+ s3012_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3012_0 : (( 12 words$word # ii)) option)) of
+ SOME ((v__826, s3013_0)) =>
+ if (((((subrange_vec_dec v__826 (( 0 : int): ii) (( 0 : int): ii) : 1 words$word))
+ = (vec_of_bits [B0] : 1 words$word)))) then
+ let (imm : 11 words$word) = ((subrange_vec_dec v__826 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ let (imm : 11 words$word) = ((subrange_vec_dec v__826 (( 11 : int): ii)
+ (( 1 : int): ii) : 11 words$word)) in
+ (case ((string_drop s3012_0 s3013_0)) of s_ => SOME (imm, s_) ) else
+ NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2995_ : string -> maybe ((mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s2995_:string ->((5)words$word#(6)words$word#string)option) s2996_0=
+ (let s2997_0 = s2996_0 in
+ if ((string_startswith s2997_0 "c.addi")) then
+ (case ((string_drop s2997_0 ((string_length "c.addi")))) of
+ s2998_0 =>
+ (case ((spc_matches_prefix0 s2998_0)) of
+ SOME ((() , s2999_0)) =>
+ (case ((string_drop s2998_0 s2999_0)) of
+ s3000_0 =>
+ (case ((reg_name_matches_prefix s3000_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rsd, s3001_0)) =>
+ (case ((string_drop s3000_0 s3001_0)) of
+ s3002_0 =>
+ (case ((sep_matches_prefix s3002_0)) of
+ SOME ((() , s3003_0)) =>
+ (case ((string_drop s3002_0 s3003_0)) of
+ s3004_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s3004_0 : (( 6 words$word # ii)) option)) of
+ SOME ((nzi, s3005_0)) =>
+ (case ((string_drop s3004_0 s3005_0)) of s_ => SOME (rsd, nzi, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2979_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2979_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2980_0=
+ (let s2981_0 = s2980_0 in
+ if ((string_startswith s2981_0 "c.sd")) then
+ (case ((string_drop s2981_0 ((string_length "c.sd")))) of
+ s2982_0 =>
+ (case ((spc_matches_prefix0 s2982_0)) of
+ SOME ((() , s2983_0)) =>
+ (case ((string_drop s2982_0 s2983_0)) of
+ s2984_0 =>
+ (case ((creg_name_matches_prefix s2984_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2985_0)) =>
+ (case ((string_drop s2984_0 s2985_0)) of
+ s2986_0 =>
+ (case ((sep_matches_prefix s2986_0)) of
+ SOME ((() , s2987_0)) =>
+ (case ((string_drop s2986_0 s2987_0)) of
+ s2988_0 =>
+ (case ((creg_name_matches_prefix s2988_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2989_0)) =>
+ (case ((string_drop s2988_0 s2989_0)) of
+ s2990_0 =>
+ (case ((sep_matches_prefix s2990_0)) of
+ SOME ((() , s2991_0)) =>
+ (case ((string_drop s2990_0 s2991_0)) of
+ s2992_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2992_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__828, s2993_0)) =>
+ if (((((subrange_vec_dec v__828 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__828 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__828 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2992_0 s2993_0)) of
+ s_ => SOME (rsc1, rsc2, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2963_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2963_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2964_0=
+ (let s2965_0 = s2964_0 in
+ if ((string_startswith s2965_0 "c.sw")) then
+ (case ((string_drop s2965_0 ((string_length "c.sw")))) of
+ s2966_0 =>
+ (case ((spc_matches_prefix0 s2966_0)) of
+ SOME ((() , s2967_0)) =>
+ (case ((string_drop s2966_0 s2967_0)) of
+ s2968_0 =>
+ (case ((creg_name_matches_prefix s2968_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc1, s2969_0)) =>
+ (case ((string_drop s2968_0 s2969_0)) of
+ s2970_0 =>
+ (case ((sep_matches_prefix s2970_0)) of
+ SOME ((() , s2971_0)) =>
+ (case ((string_drop s2970_0 s2971_0)) of
+ s2972_0 =>
+ (case ((creg_name_matches_prefix s2972_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc2, s2973_0)) =>
+ (case ((string_drop s2972_0 s2973_0)) of
+ s2974_0 =>
+ (case ((sep_matches_prefix s2974_0)) of
+ SOME ((() , s2975_0)) =>
+ (case ((string_drop s2974_0 s2975_0)) of
+ s2976_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2976_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__830, s2977_0)) =>
+ if (((((subrange_vec_dec v__830 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__830 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__830 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2976_0 s2977_0)) of
+ s_ => SOME (rsc1, rsc2, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2947_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2947_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2948_0=
+ (let s2949_0 = s2948_0 in
+ if ((string_startswith s2949_0 "c.ld")) then
+ (case ((string_drop s2949_0 ((string_length "c.ld")))) of
+ s2950_0 =>
+ (case ((spc_matches_prefix0 s2950_0)) of
+ SOME ((() , s2951_0)) =>
+ (case ((string_drop s2950_0 s2951_0)) of
+ s2952_0 =>
+ (case ((creg_name_matches_prefix s2952_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2953_0)) =>
+ (case ((string_drop s2952_0 s2953_0)) of
+ s2954_0 =>
+ (case ((sep_matches_prefix s2954_0)) of
+ SOME ((() , s2955_0)) =>
+ (case ((string_drop s2954_0 s2955_0)) of
+ s2956_0 =>
+ (case ((creg_name_matches_prefix s2956_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2957_0)) =>
+ (case ((string_drop s2956_0 s2957_0)) of
+ s2958_0 =>
+ (case ((sep_matches_prefix s2958_0)) of
+ SOME ((() , s2959_0)) =>
+ (case ((string_drop s2958_0 s2959_0)) of
+ s2960_0 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2960_0
+ : (( 8 words$word # ii)) option)) of
+ SOME ((v__832, s2961_0)) =>
+ if (((((subrange_vec_dec v__832 (( 2 : int): ii) (( 0 : int): ii) : 3 words$word))
+ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__832 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__832 (( 7 : int): ii) (( 3 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2960_0 s2961_0)) of
+ s_ => SOME (rdc, rsc, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2931_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2931_:string ->((3)words$word#(3)words$word#(5)words$word#string)option) s2932_0=
+ (let s2933_0 = s2932_0 in
+ if ((string_startswith s2933_0 "c.lw")) then
+ (case ((string_drop s2933_0 ((string_length "c.lw")))) of
+ s2934_0 =>
+ (case ((spc_matches_prefix0 s2934_0)) of
+ SOME ((() , s2935_0)) =>
+ (case ((string_drop s2934_0 s2935_0)) of
+ s2936_0 =>
+ (case ((creg_name_matches_prefix s2936_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2937_0)) =>
+ (case ((string_drop s2936_0 s2937_0)) of
+ s2938_0 =>
+ (case ((sep_matches_prefix s2938_0)) of
+ SOME ((() , s2939_0)) =>
+ (case ((string_drop s2938_0 s2939_0)) of
+ s2940_0 =>
+ (case ((creg_name_matches_prefix s2940_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rsc, s2941_0)) =>
+ (case ((string_drop s2940_0 s2941_0)) of
+ s2942_0 =>
+ (case ((sep_matches_prefix s2942_0)) of
+ SOME ((() , s2943_0)) =>
+ (case ((string_drop s2942_0 s2943_0)) of
+ s2944_0 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2944_0
+ : (( 7 words$word # ii)) option)) of
+ SOME ((v__834, s2945_0)) =>
+ if (((((subrange_vec_dec v__834 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__834 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ let (uimm : 5 words$word) =
+ ((subrange_vec_dec v__834 (( 6 : int): ii) (( 2 : int): ii) : 5 words$word)) in
+ (case ((string_drop s2944_0 s2945_0)) of
+ s_ => SOME (rdc, rsc, uimm, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2919_ : string -> maybe ((mword ty3 * mword ty8 * string))*)
+
+val _ = Define `
+ ((s2919_:string ->((3)words$word#(8)words$word#string)option) s2920_0=
+ (let s2921_0 = s2920_0 in
+ if ((string_startswith s2921_0 "c.addi4spn")) then
+ (case ((string_drop s2921_0 ((string_length "c.addi4spn")))) of
+ s2922_0 =>
+ (case ((spc_matches_prefix0 s2922_0)) of
+ SOME ((() , s2923_0)) =>
+ (case ((string_drop s2922_0 s2923_0)) of
+ s2924_0 =>
+ (case ((creg_name_matches_prefix s2924_0 : (( 3 words$word # ii)) option)) of
+ SOME ((rdc, s2925_0)) =>
+ (case ((string_drop s2924_0 s2925_0)) of
+ s2926_0 =>
+ (case ((sep_matches_prefix s2926_0)) of
+ SOME ((() , s2927_0)) =>
+ (case ((string_drop s2926_0 s2927_0)) of
+ s2928_0 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2928_0 : (( 10 words$word # ii)) option)) of
+ SOME ((v__836, s2929_0)) =>
+ if (((((subrange_vec_dec v__836 (( 1 : int): ii) (( 0 : int): ii) : 2 words$word))
+ = (vec_of_bits [B0;B0] : 2 words$word)))) then
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__836 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ let (nzimm : 8 words$word) =
+ ((subrange_vec_dec v__836 (( 9 : int): ii) (( 2 : int): ii) : 8 words$word)) in
+ (case ((string_drop s2928_0 s2929_0)) of s_ => SOME (rdc, nzimm, s_) )
+ else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2915_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2915_:string ->(string)option) s2916_0=
+ (let s2917_0 = s2916_0 in
+ if ((string_startswith s2917_0 "c.nop")) then
+ (case ((string_drop s2917_0 ((string_length "c.nop")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2891_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2891_:string ->(amoop#word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s2892_0=
+ ((case s2892_0 of
+ s2893_0 =>
+ (case ((amo_mnemonic_matches_prefix s2893_0)) of
+ SOME ((op, s2894_0)) =>
+ let s2895_0 = (string_drop s2893_0 s2894_0) in
+ if ((string_startswith s2895_0 ".")) then
+ (case ((string_drop s2895_0 ((string_length ".")))) of
+ s2896_0 =>
+ (case ((size_mnemonic_matches_prefix s2896_0)) of
+ SOME ((width, s2897_0)) =>
+ (case ((string_drop s2896_0 s2897_0)) of
+ s2898_0 =>
+ (case ((maybe_aq_matches_prefix s2898_0)) of
+ SOME ((aq, s2899_0)) =>
+ (case ((string_drop s2898_0 s2899_0)) of
+ s2900_0 =>
+ (case ((maybe_rl_matches_prefix s2900_0)) of
+ SOME ((rl, s2901_0)) =>
+ (case ((string_drop s2900_0 s2901_0)) of
+ s2902_0 =>
+ (case ((spc_matches_prefix0 s2902_0)) of
+ SOME ((() , s2903_0)) =>
+ (case ((string_drop s2902_0 s2903_0)) of
+ s2904_0 =>
+ (case ((reg_name_matches_prefix s2904_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2905_0)) =>
+ (case ((string_drop s2904_0 s2905_0)) of
+ s2906_0 =>
+ (case ((sep_matches_prefix s2906_0)) of
+ SOME ((() , s2907_0)) =>
+ (case ((string_drop s2906_0 s2907_0)) of
+ s2908_0 =>
+ (case ((reg_name_matches_prefix s2908_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2909_0)) =>
+ (case ((string_drop s2908_0 s2909_0)) of
+ s2910_0 =>
+ (case ((sep_matches_prefix s2910_0)) of
+ SOME ((() , s2911_0)) =>
+ (case ((string_drop s2910_0 s2911_0)) of
+ s2912_0 =>
+ (case ((reg_name_matches_prefix s2912_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2913_0)) =>
+ (case ((string_drop s2912_0 s2913_0)) of
+ s_ =>
+ SOME (op, width, aq, rl, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2869_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2869_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#(5)words$word#string)option) s2870_0=
+ (let s2871_0 = s2870_0 in
+ if ((string_startswith s2871_0 "sc.")) then
+ (case ((string_drop s2871_0 ((string_length "sc.")))) of
+ s2872_0 =>
+ (case ((size_mnemonic_matches_prefix s2872_0)) of
+ SOME ((size1, s2873_0)) =>
+ (case ((string_drop s2872_0 s2873_0)) of
+ s2874_0 =>
+ (case ((maybe_aq_matches_prefix s2874_0)) of
+ SOME ((aq, s2875_0)) =>
+ (case ((string_drop s2874_0 s2875_0)) of
+ s2876_0 =>
+ (case ((maybe_rl_matches_prefix s2876_0)) of
+ SOME ((rl, s2877_0)) =>
+ (case ((string_drop s2876_0 s2877_0)) of
+ s2878_0 =>
+ (case ((spc_matches_prefix0 s2878_0)) of
+ SOME ((() , s2879_0)) =>
+ (case ((string_drop s2878_0 s2879_0)) of
+ s2880_0 =>
+ (case ((reg_name_matches_prefix s2880_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2881_0)) =>
+ (case ((string_drop s2880_0 s2881_0)) of
+ s2882_0 =>
+ (case ((sep_matches_prefix s2882_0)) of
+ SOME ((() , s2883_0)) =>
+ (case ((string_drop s2882_0 s2883_0)) of
+ s2884_0 =>
+ (case ((reg_name_matches_prefix s2884_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2885_0)) =>
+ (case ((string_drop s2884_0 s2885_0)) of
+ s2886_0 =>
+ (case ((sep_matches_prefix s2886_0)) of
+ SOME ((() , s2887_0)) =>
+ (case ((string_drop s2886_0 s2887_0)) of
+ s2888_0 =>
+ (case ((reg_name_matches_prefix s2888_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2889_0)) =>
+ (case ((string_drop s2888_0 s2889_0)) of
+ s_ =>
+ SOME (size1, aq, rl, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2851_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2851_:string ->(word_width#bool#bool#(5)words$word#(5)words$word#string)option) s2852_0=
+ (let s2853_0 = s2852_0 in
+ if ((string_startswith s2853_0 "lr.")) then
+ (case ((string_drop s2853_0 ((string_length "lr.")))) of
+ s2854_0 =>
+ (case ((size_mnemonic_matches_prefix s2854_0)) of
+ SOME ((size1, s2855_0)) =>
+ (case ((string_drop s2854_0 s2855_0)) of
+ s2856_0 =>
+ (case ((maybe_aq_matches_prefix s2856_0)) of
+ SOME ((aq, s2857_0)) =>
+ (case ((string_drop s2856_0 s2857_0)) of
+ s2858_0 =>
+ (case ((maybe_rl_matches_prefix s2858_0)) of
+ SOME ((rl, s2859_0)) =>
+ (case ((string_drop s2858_0 s2859_0)) of
+ s2860_0 =>
+ (case ((spc_matches_prefix0 s2860_0)) of
+ SOME ((() , s2861_0)) =>
+ (case ((string_drop s2860_0 s2861_0)) of
+ s2862_0 =>
+ (case ((reg_name_matches_prefix s2862_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2863_0)) =>
+ (case ((string_drop s2862_0 s2863_0)) of
+ s2864_0 =>
+ (case ((sep_matches_prefix s2864_0)) of
+ SOME ((() , s2865_0)) =>
+ (case ((string_drop s2864_0 s2865_0)) of
+ s2866_0 =>
+ (case ((reg_name_matches_prefix s2866_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2867_0)) =>
+ (case ((string_drop s2866_0 s2867_0)) of
+ s_ => SOME (size1, aq, rl, rd, rs1, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2839_ : string -> maybe ((mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2839_:string ->((5)words$word#(5)words$word#string)option) s2840_0=
+ (let s2841_0 = s2840_0 in
+ if ((string_startswith s2841_0 "sfence.vma")) then
+ (case ((string_drop s2841_0 ((string_length "sfence.vma")))) of
+ s2842_0 =>
+ (case ((spc_matches_prefix0 s2842_0)) of
+ SOME ((() , s2843_0)) =>
+ (case ((string_drop s2842_0 s2843_0)) of
+ s2844_0 =>
+ (case ((reg_name_matches_prefix s2844_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2845_0)) =>
+ (case ((string_drop s2844_0 s2845_0)) of
+ s2846_0 =>
+ (case ((sep_matches_prefix s2846_0)) of
+ SOME ((() , s2847_0)) =>
+ (case ((string_drop s2846_0 s2847_0)) of
+ s2848_0 =>
+ (case ((reg_name_matches_prefix s2848_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2849_0)) =>
+ (case ((string_drop s2848_0 s2849_0)) of s_ => SOME (rs1, rs2, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2835_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2835_:string ->(string)option) s2836_0=
+ (let s2837_0 = s2836_0 in
+ if ((string_startswith s2837_0 "wfi")) then
+ (case ((string_drop s2837_0 ((string_length "wfi")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2831_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2831_:string ->(string)option) s2832_0=
+ (let s2833_0 = s2832_0 in
+ if ((string_startswith s2833_0 "ebreak")) then
+ (case ((string_drop s2833_0 ((string_length "ebreak")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s2827_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2827_:string ->(string)option) s2828_0=
+ (let s2829_0 = s2828_0 in
+ if ((string_startswith s2829_0 "sret")) then
+ (case ((string_drop s2829_0 ((string_length "sret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2823_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2823_:string ->(string)option) s2824_0=
+ (let s2825_0 = s2824_0 in
+ if ((string_startswith s2825_0 "mret")) then
+ (case ((string_drop s2825_0 ((string_length "mret")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2819_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2819_:string ->(string)option) s2820_0=
+ (let s2821_0 = s2820_0 in
+ if ((string_startswith s2821_0 "ecall")) then
+ (case ((string_drop s2821_0 ((string_length "ecall")))) of s_ => SOME s_ )
+ else NONE))`;
+
+
+(*val _s2815_ : string -> maybe string*)
+
+val _ = Define `
+ ((s2815_:string ->(string)option) s2816_0=
+ (let s2817_0 = s2816_0 in
+ if ((string_startswith s2817_0 "fence.i")) then
+ (case ((string_drop s2817_0 ((string_length "fence.i")))) of
+ s_ => SOME s_
+ )
+ else NONE))`;
+
+
+(*val _s2803_ : string -> maybe ((mword ty4 * mword ty4 * string))*)
+
+val _ = Define `
+ ((s2803_:string ->((4)words$word#(4)words$word#string)option) s2804_0=
+ (let s2805_0 = s2804_0 in
+ if ((string_startswith s2805_0 "fence.tso")) then
+ (case ((string_drop s2805_0 ((string_length "fence.tso")))) of
+ s2806_0 =>
+ (case ((spc_matches_prefix0 s2806_0)) of
+ SOME ((() , s2807_0)) =>
+ (case ((string_drop s2806_0 s2807_0)) of
+ s2808_0 =>
+ (case ((fence_bits_matches_prefix s2808_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s2809_0)) =>
+ (case ((string_drop s2808_0 s2809_0)) of
+ s2810_0 =>
+ (case ((sep_matches_prefix s2810_0)) of
+ SOME ((() , s2811_0)) =>
+ (case ((string_drop s2810_0 s2811_0)) of
+ s2812_0 =>
+ (case ((fence_bits_matches_prefix s2812_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s2813_0)) =>
+ (case ((string_drop s2812_0 s2813_0)) of s_ => SOME (pred, succ, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2791_ : string -> maybe ((mword ty4 * mword ty4 * string))*)
+
+val _ = Define `
+ ((s2791_:string ->((4)words$word#(4)words$word#string)option) s2792_0=
+ (let s2793_0 = s2792_0 in
+ if ((string_startswith s2793_0 "fence")) then
+ (case ((string_drop s2793_0 ((string_length "fence")))) of
+ s2794_0 =>
+ (case ((spc_matches_prefix0 s2794_0)) of
+ SOME ((() , s2795_0)) =>
+ (case ((string_drop s2794_0 s2795_0)) of
+ s2796_0 =>
+ (case ((fence_bits_matches_prefix s2796_0 : (( 4 words$word # ii)) option)) of
+ SOME ((pred, s2797_0)) =>
+ (case ((string_drop s2796_0 s2797_0)) of
+ s2798_0 =>
+ (case ((sep_matches_prefix s2798_0)) of
+ SOME ((() , s2799_0)) =>
+ (case ((string_drop s2798_0 s2799_0)) of
+ s2800_0 =>
+ (case ((fence_bits_matches_prefix s2800_0 : (( 4 words$word # ii)) option)) of
+ SOME ((succ, s2801_0)) =>
+ (case ((string_drop s2800_0 s2801_0)) of s_ => SOME (pred, succ, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2774_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2774_:string ->(sopw#(5)words$word#(5)words$word#(5)words$word#string)option) s2775_0=
+ ((case s2775_0 of
+ s2776_0 =>
+ (case ((shiftiwop_mnemonic_matches_prefix s2776_0)) of
+ SOME ((op, s2777_0)) =>
+ (case ((string_drop s2776_0 s2777_0)) of
+ s2778_0 =>
+ (case ((spc_matches_prefix0 s2778_0)) of
+ SOME ((() , s2779_0)) =>
+ (case ((string_drop s2778_0 s2779_0)) of
+ s2780_0 =>
+ (case ((reg_name_matches_prefix s2780_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2781_0)) =>
+ (case ((string_drop s2780_0 s2781_0)) of
+ s2782_0 =>
+ (case ((sep_matches_prefix s2782_0)) of
+ SOME ((() , s2783_0)) =>
+ (case ((string_drop s2782_0 s2783_0)) of
+ s2784_0 =>
+ (case ((reg_name_matches_prefix s2784_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2785_0)) =>
+ (case ((string_drop s2784_0 s2785_0)) of
+ s2786_0 =>
+ (case ((sep_matches_prefix s2786_0)) of
+ SOME ((() , s2787_0)) =>
+ (case ((string_drop s2786_0 s2787_0)) of
+ s2788_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2788_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s2789_0)) =>
+ (case ((string_drop s2788_0 s2789_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2757_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2757_:string ->(ropw#(5)words$word#(5)words$word#(5)words$word#string)option) s2758_0=
+ ((case s2758_0 of
+ s2759_0 =>
+ (case ((rtypew_mnemonic_matches_prefix s2759_0)) of
+ SOME ((op, s2760_0)) =>
+ (case ((string_drop s2759_0 s2760_0)) of
+ s2761_0 =>
+ (case ((spc_matches_prefix0 s2761_0)) of
+ SOME ((() , s2762_0)) =>
+ (case ((string_drop s2761_0 s2762_0)) of
+ s2763_0 =>
+ (case ((reg_name_matches_prefix s2763_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2764_0)) =>
+ (case ((string_drop s2763_0 s2764_0)) of
+ s2765_0 =>
+ (case ((sep_matches_prefix s2765_0)) of
+ SOME ((() , s2766_0)) =>
+ (case ((string_drop s2765_0 s2766_0)) of
+ s2767_0 =>
+ (case ((reg_name_matches_prefix s2767_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2768_0)) =>
+ (case ((string_drop s2767_0 s2768_0)) of
+ s2769_0 =>
+ (case ((sep_matches_prefix s2769_0)) of
+ SOME ((() , s2770_0)) =>
+ (case ((string_drop s2769_0 s2770_0)) of
+ s2771_0 =>
+ (case ((reg_name_matches_prefix s2771_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2772_0)) =>
+ (case ((string_drop s2771_0 s2772_0)) of
+ s_ => SOME (op, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2740_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2740_:string ->(sop#(5)words$word#(5)words$word#(5)words$word#string)option) s2741_0=
+ ((case s2741_0 of
+ s2742_0 =>
+ (case ((shiftw_mnemonic_matches_prefix s2742_0)) of
+ SOME ((op, s2743_0)) =>
+ (case ((string_drop s2742_0 s2743_0)) of
+ s2744_0 =>
+ (case ((spc_matches_prefix0 s2744_0)) of
+ SOME ((() , s2745_0)) =>
+ (case ((string_drop s2744_0 s2745_0)) of
+ s2746_0 =>
+ (case ((reg_name_matches_prefix s2746_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2747_0)) =>
+ (case ((string_drop s2746_0 s2747_0)) of
+ s2748_0 =>
+ (case ((sep_matches_prefix s2748_0)) of
+ SOME ((() , s2749_0)) =>
+ (case ((string_drop s2748_0 s2749_0)) of
+ s2750_0 =>
+ (case ((reg_name_matches_prefix s2750_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2751_0)) =>
+ (case ((string_drop s2750_0 s2751_0)) of
+ s2752_0 =>
+ (case ((sep_matches_prefix s2752_0)) of
+ SOME ((() , s2753_0)) =>
+ (case ((string_drop s2752_0 s2753_0)) of
+ s2754_0 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2754_0 : (( 5 words$word # ii)) option)) of
+ SOME ((shamt, s2755_0)) =>
+ (case ((string_drop s2754_0 s2755_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2724_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2724_:string ->((5)words$word#(5)words$word#(12)words$word#string)option) s2725_0=
+ (let s2726_0 = s2725_0 in
+ if ((string_startswith s2726_0 "addiw")) then
+ (case ((string_drop s2726_0 ((string_length "addiw")))) of
+ s2727_0 =>
+ (case ((spc_matches_prefix0 s2727_0)) of
+ SOME ((() , s2728_0)) =>
+ (case ((string_drop s2727_0 s2728_0)) of
+ s2729_0 =>
+ (case ((reg_name_matches_prefix s2729_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2730_0)) =>
+ (case ((string_drop s2729_0 s2730_0)) of
+ s2731_0 =>
+ (case ((sep_matches_prefix s2731_0)) of
+ SOME ((() , s2732_0)) =>
+ (case ((string_drop s2731_0 s2732_0)) of
+ s2733_0 =>
+ (case ((reg_name_matches_prefix s2733_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2734_0)) =>
+ (case ((string_drop s2733_0 s2734_0)) of
+ s2735_0 =>
+ (case ((sep_matches_prefix s2735_0)) of
+ SOME ((() , s2736_0)) =>
+ (case ((string_drop s2735_0 s2736_0)) of
+ s2737_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2737_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2738_0)) =>
+ (case ((string_drop s2737_0 s2738_0)) of s_ => SOME (rd, rs1, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2696_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2696_:string ->(word_width#bool#bool#(5)words$word#(12)words$word#(5)words$word#string)option) s2697_0=
+ (let s2698_0 = s2697_0 in
+ if ((string_startswith s2698_0 "s")) then
+ (case ((string_drop s2698_0 ((string_length "s")))) of
+ s2699_0 =>
+ (case ((size_mnemonic_matches_prefix s2699_0)) of
+ SOME ((size1, s2700_0)) =>
+ (case ((string_drop s2699_0 s2700_0)) of
+ s2701_0 =>
+ (case ((maybe_aq_matches_prefix s2701_0)) of
+ SOME ((aq, s2702_0)) =>
+ (case ((string_drop s2701_0 s2702_0)) of
+ s2703_0 =>
+ (case ((maybe_rl_matches_prefix s2703_0)) of
+ SOME ((rl, s2704_0)) =>
+ (case ((string_drop s2703_0 s2704_0)) of
+ s2705_0 =>
+ (case ((spc_matches_prefix0 s2705_0)) of
+ SOME ((() , s2706_0)) =>
+ (case ((string_drop s2705_0 s2706_0)) of
+ s2707_0 =>
+ (case ((reg_name_matches_prefix s2707_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2708_0)) =>
+ (case ((string_drop s2707_0 s2708_0)) of
+ s2709_0 =>
+ (case ((sep_matches_prefix s2709_0)) of
+ SOME ((() , s2710_0)) =>
+ (case ((string_drop s2709_0 s2710_0)) of
+ s2711_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2711_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2712_0)) =>
+ (case ((string_drop s2711_0 s2712_0)) of
+ s2713_0 =>
+ (case ((opt_spc_matches_prefix0 s2713_0)) of
+ SOME ((() , s2714_0)) =>
+ let s2715_0 = (string_drop s2713_0 s2714_0) in
+ if ((string_startswith s2715_0 "(")) then
+ (case ((string_drop s2715_0 ((string_length "(")))) of
+ s2716_0 =>
+ (case ((opt_spc_matches_prefix0 s2716_0)) of
+ SOME ((() , s2717_0)) =>
+ (case ((string_drop s2716_0 s2717_0)) of
+ s2718_0 =>
+ (case ((reg_name_matches_prefix s2718_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2719_0)) =>
+ (case ((string_drop s2718_0 s2719_0)) of
+ s2720_0 =>
+ (case ((opt_spc_matches_prefix0 s2720_0)) of
+ SOME ((() , s2721_0)) =>
+ let s2722_0 = (string_drop s2720_0 s2721_0) in
+ if ((string_startswith s2722_0 ")")) then
+ (case ((string_drop s2722_0 ((string_length ")")))) of
+ s_ =>
+ SOME (size1, aq, rl, rs2, imm, rs1, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2666_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2666_:string ->(word_width#bool#bool#bool#(5)words$word#(12)words$word#(5)words$word#string)option) s2667_0=
+ (let s2668_0 = s2667_0 in
+ if ((string_startswith s2668_0 "l")) then
+ (case ((string_drop s2668_0 ((string_length "l")))) of
+ s2669_0 =>
+ (case ((size_mnemonic_matches_prefix s2669_0)) of
+ SOME ((size1, s2670_0)) =>
+ (case ((string_drop s2669_0 s2670_0)) of
+ s2671_0 =>
+ (case ((maybe_u_matches_prefix s2671_0)) of
+ SOME ((is_unsigned, s2672_0)) =>
+ (case ((string_drop s2671_0 s2672_0)) of
+ s2673_0 =>
+ (case ((maybe_aq_matches_prefix s2673_0)) of
+ SOME ((aq, s2674_0)) =>
+ (case ((string_drop s2673_0 s2674_0)) of
+ s2675_0 =>
+ (case ((maybe_rl_matches_prefix s2675_0)) of
+ SOME ((rl, s2676_0)) =>
+ (case ((string_drop s2675_0 s2676_0)) of
+ s2677_0 =>
+ (case ((spc_matches_prefix0 s2677_0)) of
+ SOME ((() , s2678_0)) =>
+ (case ((string_drop s2677_0 s2678_0)) of
+ s2679_0 =>
+ (case ((reg_name_matches_prefix s2679_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2680_0)) =>
+ (case ((string_drop s2679_0 s2680_0)) of
+ s2681_0 =>
+ (case ((sep_matches_prefix s2681_0)) of
+ SOME ((() , s2682_0)) =>
+ (case ((string_drop s2681_0 s2682_0)) of
+ s2683_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2683_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2684_0)) =>
+ (case ((string_drop s2683_0 s2684_0)) of
+ s2685_0 =>
+ (case ((opt_spc_matches_prefix0 s2685_0)) of
+ SOME ((() , s2686_0)) =>
+ let s2687_0 = (string_drop s2685_0 s2686_0) in
+ if ((string_startswith s2687_0 "(")) then
+ (case ((string_drop s2687_0 ((string_length "(")))) of
+ s2688_0 =>
+ (case ((opt_spc_matches_prefix0 s2688_0)) of
+ SOME ((() , s2689_0)) =>
+ (case ((string_drop s2688_0 s2689_0)) of
+ s2690_0 =>
+ (case ((reg_name_matches_prefix s2690_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2691_0)) =>
+ (case ((string_drop s2690_0 s2691_0)) of
+ s2692_0 =>
+ (case ((opt_spc_matches_prefix0 s2692_0)) of
+ SOME ((() , s2693_0)) =>
+ let s2694_0 = (string_drop s2692_0 s2693_0) in
+ if ((string_startswith s2694_0 ")")) then
+ (case ((string_drop s2694_0 ((string_length ")")))) of
+ s_ =>
+ SOME (size1, is_unsigned, aq, rl, rd, imm, rs1, s_)
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ ) else NONE
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2649_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5 * string))*)
+
+val _ = Define `
+ ((s2649_:string ->(rop#(5)words$word#(5)words$word#(5)words$word#string)option) s2650_0=
+ ((case s2650_0 of
+ s2651_0 =>
+ (case ((rtype_mnemonic_matches_prefix s2651_0)) of
+ SOME ((op, s2652_0)) =>
+ (case ((string_drop s2651_0 s2652_0)) of
+ s2653_0 =>
+ (case ((spc_matches_prefix0 s2653_0)) of
+ SOME ((() , s2654_0)) =>
+ (case ((string_drop s2653_0 s2654_0)) of
+ s2655_0 =>
+ (case ((reg_name_matches_prefix s2655_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2656_0)) =>
+ (case ((string_drop s2655_0 s2656_0)) of
+ s2657_0 =>
+ (case ((sep_matches_prefix s2657_0)) of
+ SOME ((() , s2658_0)) =>
+ (case ((string_drop s2657_0 s2658_0)) of
+ s2659_0 =>
+ (case ((reg_name_matches_prefix s2659_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2660_0)) =>
+ (case ((string_drop s2659_0 s2660_0)) of
+ s2661_0 =>
+ (case ((sep_matches_prefix s2661_0)) of
+ SOME ((() , s2662_0)) =>
+ (case ((string_drop s2661_0 s2662_0)) of
+ s2663_0 =>
+ (case ((reg_name_matches_prefix s2663_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2664_0)) =>
+ (case ((string_drop s2663_0 s2664_0)) of
+ s_ => SOME (op, rd, rs1, rs2, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2632_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6 * string))*)
+
+val _ = Define `
+ ((s2632_:string ->(sop#(5)words$word#(5)words$word#(6)words$word#string)option) s2633_0=
+ ((case s2633_0 of
+ s2634_0 =>
+ (case ((shiftiop_mnemonic_matches_prefix s2634_0)) of
+ SOME ((op, s2635_0)) =>
+ (case ((string_drop s2634_0 s2635_0)) of
+ s2636_0 =>
+ (case ((spc_matches_prefix0 s2636_0)) of
+ SOME ((() , s2637_0)) =>
+ (case ((string_drop s2636_0 s2637_0)) of
+ s2638_0 =>
+ (case ((reg_name_matches_prefix s2638_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2639_0)) =>
+ (case ((string_drop s2638_0 s2639_0)) of
+ s2640_0 =>
+ (case ((sep_matches_prefix s2640_0)) of
+ SOME ((() , s2641_0)) =>
+ (case ((string_drop s2640_0 s2641_0)) of
+ s2642_0 =>
+ (case ((reg_name_matches_prefix s2642_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2643_0)) =>
+ (case ((string_drop s2642_0 s2643_0)) of
+ s2644_0 =>
+ (case ((sep_matches_prefix s2644_0)) of
+ SOME ((() , s2645_0)) =>
+ (case ((string_drop s2644_0 s2645_0)) of
+ s2646_0 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2646_0 : (( 6 words$word # ii)) option)) of
+ SOME ((shamt, s2647_0)) =>
+ (case ((string_drop s2646_0 s2647_0)) of
+ s_ => SOME (op, rd, rs1, shamt, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2615_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2615_:string ->(iop#(5)words$word#(5)words$word#(12)words$word#string)option) s2616_0=
+ ((case s2616_0 of
+ s2617_0 =>
+ (case ((itype_mnemonic_matches_prefix s2617_0)) of
+ SOME ((op, s2618_0)) =>
+ (case ((string_drop s2617_0 s2618_0)) of
+ s2619_0 =>
+ (case ((spc_matches_prefix0 s2619_0)) of
+ SOME ((() , s2620_0)) =>
+ (case ((string_drop s2619_0 s2620_0)) of
+ s2621_0 =>
+ (case ((reg_name_matches_prefix s2621_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2622_0)) =>
+ (case ((string_drop s2621_0 s2622_0)) of
+ s2623_0 =>
+ (case ((sep_matches_prefix s2623_0)) of
+ SOME ((() , s2624_0)) =>
+ (case ((string_drop s2623_0 s2624_0)) of
+ s2625_0 =>
+ (case ((reg_name_matches_prefix s2625_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2626_0)) =>
+ (case ((string_drop s2625_0 s2626_0)) of
+ s2627_0 =>
+ (case ((sep_matches_prefix s2627_0)) of
+ SOME ((() , s2628_0)) =>
+ (case ((string_drop s2627_0 s2628_0)) of
+ s2629_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2629_0 : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2630_0)) =>
+ (case ((string_drop s2629_0 s2630_0)) of
+ s_ => SOME (op, rd, rs1, imm, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2598_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13 * string))*)
+
+val _ = Define `
+ ((s2598_:string ->(bop#(5)words$word#(5)words$word#(13)words$word#string)option) s2599_0=
+ ((case s2599_0 of
+ s2600_0 =>
+ (case ((btype_mnemonic_matches_prefix s2600_0)) of
+ SOME ((op, s2601_0)) =>
+ (case ((string_drop s2600_0 s2601_0)) of
+ s2602_0 =>
+ (case ((spc_matches_prefix0 s2602_0)) of
+ SOME ((() , s2603_0)) =>
+ (case ((string_drop s2602_0 s2603_0)) of
+ s2604_0 =>
+ (case ((reg_name_matches_prefix s2604_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2605_0)) =>
+ (case ((string_drop s2604_0 s2605_0)) of
+ s2606_0 =>
+ (case ((sep_matches_prefix s2606_0)) of
+ SOME ((() , s2607_0)) =>
+ (case ((string_drop s2606_0 s2607_0)) of
+ s2608_0 =>
+ (case ((reg_name_matches_prefix s2608_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs2, s2609_0)) =>
+ (case ((string_drop s2608_0 s2609_0)) of
+ s2610_0 =>
+ (case ((sep_matches_prefix s2610_0)) of
+ SOME ((() , s2611_0)) =>
+ (case ((string_drop s2610_0 s2611_0)) of
+ s2612_0 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2612_0 : (( 13 words$word # ii)) option)) of
+ SOME ((imm, s2613_0)) =>
+ (case ((string_drop s2612_0 s2613_0)) of
+ s_ => SOME (op, rs1, rs2, imm, s_)
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+(*val _s2582_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))*)
+
+val _ = Define `
+ ((s2582_:string ->((5)words$word#(5)words$word#(12)words$word#string)option) s2583_0=
+ (let s2584_0 = s2583_0 in
+ if ((string_startswith s2584_0 "jalr")) then
+ (case ((string_drop s2584_0 ((string_length "jalr")))) of
+ s2585_0 =>
+ (case ((spc_matches_prefix0 s2585_0)) of
+ SOME ((() , s2586_0)) =>
+ (case ((string_drop s2585_0 s2586_0)) of
+ s2587_0 =>
+ (case ((reg_name_matches_prefix s2587_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2588_0)) =>
+ (case ((string_drop s2587_0 s2588_0)) of
+ s2589_0 =>
+ (case ((sep_matches_prefix s2589_0)) of
+ SOME ((() , s2590_0)) =>
+ (case ((string_drop s2589_0 s2590_0)) of
+ s2591_0 =>
+ (case ((reg_name_matches_prefix s2591_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rs1, s2592_0)) =>
+ (case ((string_drop s2591_0 s2592_0)) of
+ s2593_0 =>
+ (case ((sep_matches_prefix s2593_0)) of
+ SOME ((() , s2594_0)) =>
+ (case ((string_drop s2593_0 s2594_0)) of
+ s2595_0 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2595_0
+ : (( 12 words$word # ii)) option)) of
+ SOME ((imm, s2596_0)) =>
+ (case ((string_drop s2595_0 s2596_0)) of s_ => SOME (rd, rs1, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2570_ : string -> maybe ((mword ty5 * mword ty21 * string))*)
+
+val _ = Define `
+ ((s2570_:string ->((5)words$word#(21)words$word#string)option) s2571_0=
+ (let s2572_0 = s2571_0 in
+ if ((string_startswith s2572_0 "jal")) then
+ (case ((string_drop s2572_0 ((string_length "jal")))) of
+ s2573_0 =>
+ (case ((spc_matches_prefix0 s2573_0)) of
+ SOME ((() , s2574_0)) =>
+ (case ((string_drop s2573_0 s2574_0)) of
+ s2575_0 =>
+ (case ((reg_name_matches_prefix s2575_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2576_0)) =>
+ (case ((string_drop s2575_0 s2576_0)) of
+ s2577_0 =>
+ (case ((sep_matches_prefix s2577_0)) of
+ SOME ((() , s2578_0)) =>
+ (case ((string_drop s2577_0 s2578_0)) of
+ s2579_0 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s2579_0 : (( 21 words$word # ii)) option)) of
+ SOME ((imm, s2580_0)) =>
+ (case ((string_drop s2579_0 s2580_0)) of s_ => SOME (rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ else NONE))`;
+
+
+(*val _s2557_ : string -> maybe ((uop * mword ty5 * mword ty20 * string))*)
+
+val _ = Define `
+ ((s2557_:string ->(uop#(5)words$word#(20)words$word#string)option) s2558_0=
+ ((case s2558_0 of
+ s2559_0 =>
+ (case ((utype_mnemonic_matches_prefix s2559_0)) of
+ SOME ((op, s2560_0)) =>
+ (case ((string_drop s2559_0 s2560_0)) of
+ s2561_0 =>
+ (case ((spc_matches_prefix0 s2561_0)) of
+ SOME ((() , s2562_0)) =>
+ (case ((string_drop s2561_0 s2562_0)) of
+ s2563_0 =>
+ (case ((reg_name_matches_prefix s2563_0 : (( 5 words$word # ii)) option)) of
+ SOME ((rd, s2564_0)) =>
+ (case ((string_drop s2563_0 s2564_0)) of
+ s2565_0 =>
+ (case ((sep_matches_prefix s2565_0)) of
+ SOME ((() , s2566_0)) =>
+ (case ((string_drop s2565_0 s2566_0)) of
+ s2567_0 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s2567_0 : (( 20 words$word # ii)) option)) of
+ SOME ((imm, s2568_0)) =>
+ (case ((string_drop s2567_0 s2568_0)) of s_ => SOME (op, rd, imm, s_) )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )
+ | _ => NONE
+ )
+ )))`;
+
+
+val _ = Define `
+ ((assembly_matches_prefix:string ->(ast#int)option) arg_=
+ (let s2569_0 = arg_ in
+ if ((case ((s2557_ s2569_0 : ((uop # 5 words$word # 20 words$word # string))option)) of
+ SOME ((op, rd, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2557_ s2569_0 : (( uop # 5 words$word # 20 words$word # string)) option) of
+ (SOME ((op, rd, imm, s_))) =>
+ SOME (UTYPE (imm, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2570_ s2569_0 : (( 5 words$word # 21 words$word # string))option)) of
+ SOME ((rd, imm, s_)) => T
+ | _ => F
+ )) then (case (s2570_ s2569_0 : (( 5 words$word # 21 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (RISCV_JAL (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2582_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((rd, rs1, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2582_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((rd, rs1, imm, s_))) =>
+ SOME
+ (RISCV_JALR (imm, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2598_ s2569_0 : ((bop # 5 words$word # 5 words$word # 13 words$word # string))option)) of
+ SOME ((op, rs1, rs2, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2598_ s2569_0 : (( bop # 5 words$word # 5 words$word # 13 words$word # string)) option) of
+ (SOME ((op, rs1, rs2, imm, s_))) =>
+ SOME
+ (BTYPE (imm, rs2, rs1, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2615_ s2569_0 : ((iop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, imm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2615_ s2569_0 : (( iop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, imm, s_))) =>
+ SOME
+ (ITYPE (imm, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2632_ s2569_0 : ((sop # 5 words$word # 5 words$word # 6 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => T
+ | _ => F
+ )) then (case
+ (s2632_ s2569_0 : (( sop # 5 words$word # 5 words$word # 6 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTIOP (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2649_ s2569_0 : ((rop # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2649_ s2569_0 : (( rop # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, rs2, s_))) =>
+ SOME
+ (RTYPE (rs2, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2666_ s2569_0
+ : ((word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word # string))option)) of
+ SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2666_ s2569_0
+ : (( word_width # bool # bool # bool # 5 words$word # 12 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, is_unsigned, aq, rl, rd, imm, rs1, s_))) =>
+ SOME
+ (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2696_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rs2, imm, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2696_ s2569_0
+ : (( word_width # bool # bool # 5 words$word # 12 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rs2, imm, rs1, s_))) =>
+ SOME
+ (STORE (imm, rs2, rs1, size1, aq, rl),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2724_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((rd, rs1, imm, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2724_ s2569_0 : (( 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((rd, rs1, imm, s_))) =>
+ SOME (ADDIW (imm, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2740_ s2569_0 : ((sop # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2740_ s2569_0 : (( sop # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTW (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2757_ s2569_0 : ((ropw # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2757_ s2569_0 : (( ropw # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, rs2, s_))) =>
+ SOME
+ (RTYPEW (rs2, rs1, rd, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2774_ s2569_0 : ((sopw # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, rd, rs1, shamt, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2774_ s2569_0 : (( sopw # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, rd, rs1, shamt, s_))) =>
+ SOME
+ (SHIFTIWOP (shamt, rs1, rd, op), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2791_ s2569_0 : (( 4 words$word # 4 words$word # string))option)) of
+ SOME ((pred, succ, s_)) => T
+ | _ => F
+ )) then (case (s2791_ s2569_0 : (( 4 words$word # 4 words$word # string)) option) of
+ (SOME ((pred, succ, s_))) =>
+ SOME (FENCE (pred, succ), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2803_ s2569_0 : (( 4 words$word # 4 words$word # string))option)) of
+ SOME ((pred, succ, s_)) => T
+ | _ => F
+ )) then (case (s2803_ s2569_0 : (( 4 words$word # 4 words$word # string)) option) of
+ (SOME ((pred, succ, s_))) =>
+ SOME (FENCE_TSO (pred, succ), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2815_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2815_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (FENCEI () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2819_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2819_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (ECALL () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2823_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2823_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (MRET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2827_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2827_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (SRET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2831_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2831_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (EBREAK () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2835_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2835_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (WFI () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2839_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case (s2839_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rs1, rs2, s_))) =>
+ SOME (SFENCE_VMA (rs1, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2851_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rd, rs1, s_)) => T
+ | _ => F
+ )) then (case
+ (s2851_ s2569_0 : (( word_width # bool # bool # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, s_))) =>
+ SOME
+ (LOADRES (aq, rl, rs1, size1, rd), ((string_length arg_)) -
+ ((string_length s_)))
+ )
+ else if ((case ((s2869_ s2569_0
+ : ((word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((size1, aq, rl, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2869_ s2569_0
+ : (( word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((size1, aq, rl, rd, rs1, rs2, s_))) =>
+ SOME
+ (STORECON (aq, rl, rs2, rs1, size1, rd),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2891_ s2569_0
+ : ((amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((op, width, aq, rl, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s2891_ s2569_0
+ : (( amoop # word_width # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((op, width, aq, rl, rd, rs1, rs2, s_))) =>
+ SOME
+ (AMO (op, aq, rl, rs2, rs1, width, rd),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2915_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s2915_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (C_NOP () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2919_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rdc, nzimm, s_)) => (nzimm <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))
+ | _ => F
+ )) then (case (s2919_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rdc, nzimm, s_))) =>
+ SOME
+ (C_ADDI4SPN (rdc, nzimm), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2931_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rdc, rsc, uimm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2931_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rdc, rsc, uimm, s_))) =>
+ SOME (C_LW (uimm, rsc, rdc), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2947_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rdc, rsc, uimm, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2947_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rdc, rsc, uimm, s_))) =>
+ SOME (C_LD (uimm, rsc, rdc), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2963_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rsc1, rsc2, uimm, s_)) => T
+ | _ => F
+ )) then (case
+ (s2963_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rsc1, rsc2, uimm, s_))) =>
+ SOME
+ (C_SW (uimm, rsc1, rsc2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2979_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string))option)) of
+ SOME ((rsc1, rsc2, uimm, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s2979_ s2569_0 : (( 3 words$word # 3 words$word # 5 words$word # string)) option) of
+ (SOME ((rsc1, rsc2, uimm, s_))) =>
+ SOME
+ (C_SD (uimm, rsc1, rsc2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s2995_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, nzi, s_)) =>
+ ((((nzi <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s2995_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, nzi, s_))) =>
+ SOME (C_ADDI (nzi, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3007_ s2569_0 : (( 11 words$word # string))option)) of
+ SOME ((imm, s_)) => ((( 64 : int):ii) = (( 32 : int):ii))
+ | _ => F
+ )) then (case (s3007_ s2569_0 : (( 11 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_JAL imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3015_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, imm, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3015_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, imm, s_))) =>
+ SOME (C_ADDIW (imm, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3027_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, imm, s_)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3027_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (C_LI (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3039_ s2569_0 : (( 6 words$word # string))option)) of
+ SOME ((imm, s_)) => (imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3039_ s2569_0 : (( 6 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_ADDI16SP imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3047_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, imm, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((((((regidx_to_regno rd)) <> ((regidx_to_regno sp))))) /\ (((imm <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))))
+ | _ => F
+ )) then (case (s3047_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, imm, s_))) =>
+ SOME (C_LUI (imm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3059_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3059_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SRLI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3071_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) => (shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))
+ | _ => F
+ )) then (case (s3071_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SRAI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3083_ s2569_0 : (( 3 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, imm, s_)) => T
+ | _ => F
+ )) then (case (s3083_ s2569_0 : (( 3 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, imm, s_))) =>
+ SOME (C_ANDI (imm, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3095_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3095_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_SUB (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3107_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3107_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_XOR (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3119_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3119_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_OR (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3131_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => T
+ | _ => F
+ )) then (case (s3131_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_AND (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3143_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3143_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_SUBW (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3155_ s2569_0 : (( 3 words$word # 3 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3155_ s2569_0 : (( 3 words$word # 3 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_ADDW (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3167_ s2569_0 : (( 11 words$word # string))option)) of
+ SOME ((imm, s_)) => T
+ | _ => F
+ )) then (case (s3167_ s2569_0 : (( 11 words$word # string)) option) of
+ (SOME ((imm, s_))) =>
+ SOME (C_J imm, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3175_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rs, imm, s_)) => T
+ | _ => F
+ )) then (case (s3175_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rs, imm, s_))) =>
+ SOME (C_BEQZ (imm, rs), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3187_ s2569_0 : (( 3 words$word # 8 words$word # string))option)) of
+ SOME ((rs, imm, s_)) => T
+ | _ => F
+ )) then (case (s3187_ s2569_0 : (( 3 words$word # 8 words$word # string)) option) of
+ (SOME ((rs, imm, s_))) =>
+ SOME (C_BNEZ (imm, rs), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3199_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rsd, shamt, s_)) =>
+ ((((shamt <> (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3199_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rsd, shamt, s_))) =>
+ SOME (C_SLLI (shamt, rsd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3211_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) => (((regidx_to_regno rd)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3211_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_LWSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3223_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ ((((( 64 : int):ii) = (( 64 : int):ii)))))
+ | _ => F
+ )) then (case (s3223_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_LDSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3235_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rd, uimm, s_)) => T
+ | _ => F
+ )) then (case (s3235_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rd, uimm, s_))) =>
+ SOME (C_SWSP (uimm, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3247_ s2569_0 : (( 5 words$word # 6 words$word # string))option)) of
+ SOME ((rs2, uimm, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case (s3247_ s2569_0 : (( 5 words$word # 6 words$word # string)) option) of
+ (SOME ((rs2, uimm, s_))) =>
+ SOME (C_SDSP (uimm, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3259_ s2569_0 : (( 5 words$word # string))option)) of
+ SOME ((rs1, s_)) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3259_ s2569_0 : (( 5 words$word # string)) option) of
+ (SOME ((rs1, s_))) =>
+ SOME (C_JR rs1, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3267_ s2569_0 : (( 5 words$word # string))option)) of
+ SOME ((rs1, s_)) => (((regidx_to_regno rs1)) <> ((regidx_to_regno zreg)))
+ | _ => F
+ )) then (case (s3267_ s2569_0 : (( 5 words$word # string)) option) of
+ (SOME ((rs1, s_))) =>
+ SOME (C_JALR rs1, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3275_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rd, rs2, s_)) =>
+ ((((((regidx_to_regno rd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3275_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rd, rs2, s_))) =>
+ SOME (C_MV (rd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3287_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s3287_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (C_EBREAK () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3291_ s2569_0 : (( 5 words$word # 5 words$word # string))option)) of
+ SOME ((rsd, rs2, s_)) =>
+ ((((((regidx_to_regno rsd)) <> ((regidx_to_regno zreg))))) /\ (((((regidx_to_regno rs2)) <> ((regidx_to_regno zreg))))))
+ | _ => F
+ )) then (case (s3291_ s2569_0 : (( 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rsd, rs2, s_))) =>
+ SOME (C_ADD (rsd, rs2), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3303_ s2569_0
+ : ((bool # bool # bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((high, signed1, signed2, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3303_ s2569_0 : (( bool # bool # bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((high, signed1, signed2, rd, rs1, rs2, s_))) =>
+ SOME
+ (MUL (rs2, rs1, rd, high, signed1, signed2),
+ ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3320_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3320_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (DIV0 (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3338_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => T
+ | _ => F
+ )) then (case
+ (s3338_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (REM (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3356_ s2569_0 : (( 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((rd, rs1, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3356_ s2569_0 : (( 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((rd, rs1, rs2, s_))) =>
+ SOME (MULW (rs2, rs1, rd), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3372_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3372_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (DIVW (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3391_ s2569_0 : ((bool # 5 words$word # 5 words$word # 5 words$word # string))option)) of
+ SOME ((s, rd, rs1, rs2, s_)) => ((( 64 : int):ii) = (( 64 : int):ii))
+ | _ => F
+ )) then (case
+ (s3391_ s2569_0 : (( bool # 5 words$word # 5 words$word # 5 words$word # string)) option) of
+ (SOME ((s, rd, rs1, rs2, s_))) =>
+ SOME (REMW (rs2, rs1, rd, s), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3410_ s2569_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, csr, s_)) => T
+ | _ => F
+ )) then (case
+ (s3410_ s2569_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, csr, s_))) =>
+ SOME
+ (CSR (csr, rs1, rd, T, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3428_ s2569_0 : ((csrop # 5 words$word # 5 words$word # 12 words$word # string))option)) of
+ SOME ((op, rd, rs1, csr, s_)) => T
+ | _ => F
+ )) then (case
+ (s3428_ s2569_0 : (( csrop # 5 words$word # 5 words$word # 12 words$word # string)) option) of
+ (SOME ((op, rd, rs1, csr, s_))) =>
+ SOME
+ (CSR (csr, rs1, rd, F, op), ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3445_ s2569_0)) of SOME (s_) => T | _ => F )) then
+ (case s3445_ s2569_0 of
+ (SOME (s_)) =>
+ SOME (URET () , ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3449_ s2569_0 : (( 32 words$word # string))option)) of
+ SOME ((s, s_)) => T
+ | _ => F
+ )) then (case (s3449_ s2569_0 : (( 32 words$word # string)) option) of
+ (SOME ((s, s_))) =>
+ SOME (ILLEGAL s, ((string_length arg_)) - ((string_length s_)))
+ )
+ else if ((case ((s3457_ s2569_0 : (( 16 words$word # string))option)) of
+ SOME ((s, s_)) => T
+ | _ => F
+ )) then (case (s3457_ s2569_0 : (( 16 words$word # string)) option) of
+ (SOME ((s, s_))) =>
+ SOME (C_ILLEGAL s, ((string_length arg_)) - ((string_length s_)))
+ )
+ else NONE))`;
+
+
+val _ = Define `
+ ((print_insn:ast ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) insn= (assembly_forwards insn))`;
+
+
+(*val decode : mword ty32 -> M ast*)
+
+val _ = Define `
+ ((decode:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bv= (encdec_backwards bv))`;
+
+
+(*val decodeCompressed : mword ty16 -> ast*)
+
+val _ = Define `
+ ((decodeCompressed:(16)words$word -> ast) bv= (encdec_compressed_backwards bv))`;
+
+
+(*val ext_init : unit -> unit*)
+
+val _ = Define `
+ ((ext_init:unit -> unit) () = () )`;
+
+
+(*val ext_fetch_hook : FetchResult -> FetchResult*)
+
+val _ = Define `
+ ((ext_fetch_hook:FetchResult -> FetchResult) f= f)`;
+
+
+(*val ext_pre_step_hook : unit -> unit*)
+
+val _ = Define `
+ ((ext_pre_step_hook:unit -> unit) () = () )`;
+
+
+(*val ext_post_step_hook : unit -> unit*)
+
+val _ = Define `
+ ((ext_post_step_hook:unit -> unit) () = () )`;
+
+
+(*val ext_post_decode_hook : ast -> M ast*)
+
+val _ = Define `
+ ((ext_post_decode_hook:ast ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= (sail2_state_monad$returnS x))`;
+
+
+(*val isRVC : mword ty16 -> bool*)
+
+val _ = Define `
+ ((isRVC:(16)words$word -> bool) h=
+ (~ (((((subrange_vec_dec h (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))`;
+
+
+(*val fetch : unit -> M FetchResult*)
+
+val _ = Define `
+ ((fetch:unit ->(regstate)sail2_state_monad$sequential_state ->(((FetchResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ (case ((ext_fetch_check_pc w__0 w__1)) of
+ Ext_FetchAddr_Error (e) => sail2_state_monad$returnS (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc) => sail2_state_monad$bindS
+ (sail2_state$or_boolS
+ (sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec use_pc (( 0 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))
+ (sail2_state$and_boolS
+ (sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec use_pc (( 1 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))
+ ( sail2_state_monad$bindS(haveRVC () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) .
+ if w__4 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) .
+ sail2_state_monad$returnS (F_Error (E_Fetch_Addr_Align, w__5)))
+ else sail2_state_monad$bindS
+ (translateAddr use_pc Execute : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__6 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__6 of
+ TR_Failure (e) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__7 : 64 words$word) .
+ sail2_state_monad$returnS (F_Error (e, w__7)))
+ | TR_Address (ppclo) => sail2_state_monad$bindS
+ (mem_read Execute ppclo (( 2 : int):ii) F F F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__8 : ( 16 words$word)
+ MemoryOpResult) .
+ (case w__8 of
+ MemException (e) => sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : 64 words$word) .
+ sail2_state_monad$returnS (F_Error (E_Fetch_Access_Fault, w__9)))
+ | MemValue (ilo) =>
+ if ((isRVC ilo)) then sail2_state_monad$returnS (F_RVC ilo)
+ else sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) .
+ let (PC_hi : xlenbits) = ((add_vec_int w__10 (( 2 : int):ii) : 64 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) .
+ (case ((ext_fetch_check_pc w__11 PC_hi)) of
+ Ext_FetchAddr_Error (e) => sail2_state_monad$returnS (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc_hi) => sail2_state_monad$bindS
+ (translateAddr use_pc_hi Execute : ( (( 64 words$word), ExceptionType)TR_Result) M) (\ (w__12 : (( 64 words$word), ExceptionType)
+ TR_Result) .
+ (case w__12 of
+ TR_Failure (e) => sail2_state_monad$returnS (F_Error (e, PC_hi))
+ | TR_Address (ppchi) => sail2_state_monad$bindS
+ (mem_read Execute ppchi (( 2 : int):ii) F F F
+ : ( ( 16 words$word)MemoryOpResult) M) (\ (w__13 : ( 16 words$word)
+ MemoryOpResult) .
+ sail2_state_monad$returnS ((case w__13 of
+ MemException (e) => F_Error (E_Fetch_Access_Fault, PC_hi)
+ | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word))
+ )))
+ ))
+ )))
+ ))
+ )))
+ )))))`;
+
+
+(*val step : ii -> M bool*)
+
+val _ = Define `
+ ((step:int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) step_no=
+ (let (_ : unit) = (ext_pre_step_hook () ) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS minstret_written_ref F)
+ (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__0 : Privilege) . sail2_state_monad$bindS
+ (dispatchInterrupt w__0) (\ (w__1 : ((InterruptType # Privilege))option) . sail2_state_monad$bindS
+ (case w__1 of
+ SOME ((intr, priv)) =>
+ let (_ : unit) =
+ (if ((get_config_print_instr () )) then
+ print_bits0 "Handling interrupt: " ((interruptType_to_bits intr : 8 words$word))
+ else () ) in sail2_state_monad$seqS
+ (handle_interrupt intr priv) (sail2_state_monad$returnS (RETIRE_FAIL, F))
+ | NONE => sail2_state_monad$bindS
+ (fetch () ) (\ (w__2 : FetchResult) .
+ let (f : FetchResult) = (ext_fetch_hook w__2) in
+ (case f of
+ F_Ext_Error (e) =>
+ let (_ : unit) = (ext_handle_fetch_check_error e) in
+ sail2_state_monad$returnS (RETIRE_FAIL, F)
+ | F_Error ((e, addr)) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS (RETIRE_FAIL, F))
+ | F_RVC (h) =>
+ let ast = (decodeCompressed h) in sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_instr () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__3 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS
+ (print_insn ast) (\ (w__5 : string) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "["
+ ((STRCAT ((stringFromInteger step_no))
+ ((STRCAT "] ["
+ ((STRCAT ((privLevel_to_str w__3))
+ ((STRCAT "]: "
+ ((STRCAT ((string_of_bits w__4))
+ ((STRCAT " ("
+ ((STRCAT ((string_of_bits h))
+ ((STRCAT ") " w__5)))))))))))))))))))))))
+ else sail2_state_monad$returnS () )
+ (haveRVC () )) (\ (w__6 : bool) .
+ if w__6 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__7 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__7 (( 2 : int):ii) : 64 words$word)))
+ (ext_post_decode_hook ast)) (\ (w__8 : ast) . sail2_state_monad$bindS
+ (execute w__8) (\ (w__9 : Retired) . sail2_state_monad$returnS (w__9, T))))
+ else sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS (RETIRE_FAIL, T)))
+ | F_Base (w) => sail2_state_monad$bindS
+ (decode w) (\ ast . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (if ((get_config_print_instr () )) then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__11 : Privilege) . sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__12 : 64 words$word) . sail2_state_monad$bindS
+ (print_insn ast) (\ (w__13 : string) .
+ sail2_state_monad$returnS ((print_dbg
+ ((STRCAT "["
+ ((STRCAT ((stringFromInteger step_no))
+ ((STRCAT "] ["
+ ((STRCAT ((privLevel_to_str w__11))
+ ((STRCAT "]: "
+ ((STRCAT ((string_of_bits w__12))
+ ((STRCAT " ("
+ ((STRCAT ((string_of_bits w))
+ ((STRCAT ") " w__13)))))))))))))))))))))))
+ else sail2_state_monad$returnS () )
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__14 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS
+ (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__14 (( 4 : int):ii) : 64 words$word)))
+ (ext_post_decode_hook ast)) (\ (w__15 : ast) . sail2_state_monad$bindS
+ (execute w__15) (\ (w__16 : Retired) . sail2_state_monad$returnS (w__16, T)))))
+ ))
+ ) (\ varstup . let ((retired : Retired), (stepped : bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS
+ (tick_pc () )
+ (case retired of RETIRE_SUCCESS => retire_instruction () | RETIRE_FAIL => sail2_state_monad$returnS () ))
+ (let (_ : unit) = (ext_post_step_hook () ) in
+ sail2_state_monad$returnS stepped))))))`;
+
+
+(*val loop : unit -> M unit*)
+
+val _ = Define `
+ ((loop:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () =
+ (let insns_per_tick = (plat_insns_per_tick () ) in
+ let (i : ii) = ((( 0 : int):ii)) in
+ let (step_no : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS
+ (sail2_state$whileS (i, step_no)
+ (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_done_ref) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))
+ (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS
+ (step step_no) (\ stepped .
+ let (step_no : ii) = (if stepped then step_no + (( 1 : int):ii) else step_no) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_done_ref) (\ (w__1 : bool) . sail2_state_monad$bindS
+ (if w__1 then sail2_state_monad$bindS
+ (sail2_state_monad$read_regS htif_exit_code_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) .
+ let exit_val = (lem$w2ui w__2) in
+ sail2_state_monad$returnS (let _ =
+ (if (((exit_val = (( 0 : int):ii)))) then print_endline "SUCCESS"
+ else print_int "FAILURE: " exit_val) in
+ i))
+ else
+ let i = (i + (( 1 : int):ii)) in
+ if (((i = insns_per_tick))) then sail2_state_monad$seqS (sail2_state_monad$seqS (tick_clock () ) (tick_platform () )) (sail2_state_monad$returnS (( 0 : int):ii))
+ else sail2_state_monad$returnS i) (\ (i : ii) .
+ sail2_state_monad$returnS (i, step_no)))))) (\ varstup . let ((i : ii), (step_no : ii)) = varstup in
+ sail2_state_monad$returnS () )))`;
+
+
+(*val init_model : unit -> M unit*)
+
+val _ = Define `
+ ((init_model:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS
+ (init_platform () )
+ (init_sys () ))
+ (init_vmem () ))
+ (let (_ : unit) = (ext_init () ) in
+ ext_init_regs () )))`;
+
+
+val _ = Define `
+((GPRstr:(string)list)=
+ (["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";
+ "x15";"x14";"x13";"x12";"x11";"x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]))`;
+
+
+val _ = Define `
+ ((CIA_fp:regfp)= (RFull "CIA"))`;
+
+
+val _ = Define `
+ ((NIA_fp:regfp)= (RFull "NIA"))`;
+
+
+(*val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)*)
+
+val _ = Define `
+ ((initial_analysis:ast ->(regstate)sail2_state_monad$sequential_state ->((((regfp)list#(regfp)list#(regfp)list#(niafp)list#diafp#instruction_kind),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) instr=
+ (let iR = ([]) in
+ let oR = ([]) in
+ let aR = ([]) in
+ let ik = (IK_simple () ) in
+ let Nias = ([NIAFP_successor () ]) in
+ let Dia = (DIAFP_none () ) in sail2_state_monad$bindS
+ (case instr of
+ EBREAK (() ) => sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | UTYPE ((imm, rd, op)) =>
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | RISCV_JAL ((imm, rd)) =>
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) .
+ let (Nias : niafp list) = ([NIAFP_concrete_address ((add_vec w__0 offset : 64 words$word))]) in
+ let (ik : instruction_kind) = (IK_branch () ) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | RISCV_JALR ((imm, rs, rd)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in
+ let (Nias : niafp list) = ([NIAFP_indirect_address () ]) in
+ let (ik : instruction_kind) = (IK_branch () ) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | BTYPE ((imm, rs2, rs1, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let ik = (IK_branch () ) in
+ let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS
+ (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) .
+ let (Nias : niafp list) =
+ ([NIAFP_concrete_address ((add_vec w__1 offset : 64 words$word));NIAFP_successor () ]) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | ITYPE ((imm, rs, rd, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | SHIFTIOP ((imm, rs, rd, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | RTYPE ((rs2, rs1, rd, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | CSR ((csr, rs1, rd, is_imm, op)) =>
+ let (isWrite : bool) =
+ ((case op of
+ CSRRW => T
+ | _ => if is_imm then (((lem$w2ui rs1)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii))
+ )) in
+ let (iR : regfp list) = ((RFull ((csr_name csr))) :: iR) in
+ let (iR : regfp list) =
+ (if ((~ is_imm)) then (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR
+ else iR) in
+ let (oR : regfp list) = (if isWrite then (RFull ((csr_name csr))) :: oR else oR) in
+ let (oR : regfp list) = ((RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | LOAD ((imm, rs, rd, unsign, width, aq, rl)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ let aR = iR in sail2_state_monad$bindS
+ (case (aq, rl) of
+ (F, F) => sail2_state_monad$returnS (IK_mem_read Read_plain)
+ | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_acquire)
+ | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_strong_acquire)
+ | _ => internal_error "LOAD type not implemented in initial_analysis"
+ ) (\ (w__3 : instruction_kind) .
+ let (ik : instruction_kind) = w__3 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | STORE ((imm, rs2, rs1, width, aq, rl)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (aR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: aR) in sail2_state_monad$bindS
+ (case (aq, rl) of
+ (F, F) => sail2_state_monad$returnS (IK_mem_write Write_plain)
+ | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_release)
+ | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_strong_release)
+ | _ => internal_error "STORE type not implemented in initial_analysis"
+ ) (\ (w__5 : instruction_kind) .
+ let (ik : instruction_kind) = w__5 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | ADDIW ((imm, rs, rd)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | SHIFTW ((imm, rs, rd, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | RTYPEW ((rs2, rs1, rd, op)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | FENCE ((pred, succ)) => sail2_state_monad$bindS
+ (case (pred, succ) of
+ (v__838, v__839) =>
+ if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__839 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_simple () )
+ else internal_error "barrier type not implemented in initial_analysis"
+ ) (\ (w__17 : instruction_kind) .
+ let (ik : instruction_kind) = w__17 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | FENCE_TSO ((pred, succ)) => sail2_state_monad$bindS
+ (case (pred, succ) of
+ (v__878, v__879) =>
+ if ((((((((subrange_vec_dec v__878 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__879 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then
+ sail2_state_monad$returnS (IK_barrier Barrier_RISCV_tso)
+ else internal_error "barrier type not implemented in initial_analysis"
+ ) (\ (w__20 : instruction_kind) .
+ let (ik : instruction_kind) = w__20 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | FENCEI (() ) =>
+ let (ik : instruction_kind) = (IK_simple () ) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | LOADRES ((aq, rl, rs1, width, rd)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ let aR = iR in sail2_state_monad$bindS
+ (case (aq, rl) of
+ (F, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved)
+ | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_acquire)
+ | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_strong_acquire)
+ | (F, T) => internal_error "LOADRES type not implemented in initial_analysis"
+ ) (\ (w__22 : instruction_kind) .
+ let (ik : instruction_kind) = w__22 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (aR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: aR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in sail2_state_monad$bindS
+ (case (aq, rl) of
+ (F, F) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional)
+ | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_release)
+ | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_strong_release)
+ | (T, F) => internal_error "STORECON type not implemented in initial_analysis"
+ ) (\ (w__24 : instruction_kind) .
+ let (ik : instruction_kind) = w__24 in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR))
+ | AMO ((op, aq, rl, rs2, rs1, width, rd)) =>
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) :: iR) in
+ let (iR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: iR) in
+ let (aR : regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 : int):ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) :: aR) in
+ let (oR : regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 : int):ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) :: oR) in
+ let (ik : instruction_kind) =
+ ((case (aq, rl) of
+ (F, F) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional)
+ | (F, T) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release)
+ | (T, F) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional)
+ | (T, T) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional_release)
+ )) in
+ sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ | _ => sail2_state_monad$returnS (Nias, aR, iR, ik, oR)
+ ) (\ varstup . let ((Nias : niafp list), (aR : regfp list), (iR : regfp list), (ik :
+ instruction_kind), (oR : regfp list)) = varstup in
+ sail2_state_monad$returnS (iR, oR, aR, Nias, Dia, ik))))`;
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV64/riscv_extrasScript.sml b/prover_snapshots/hol4/RV64/riscv_extrasScript.sml
new file mode 100644
index 0000000..c6d4fe2
--- /dev/null
+++ b/prover_snapshots/hol4/RV64/riscv_extrasScript.sml
@@ -0,0 +1,276 @@
+(*Generated by Lem from handwritten_support/riscv_extras.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_extras"
+
+(*open import Pervasives*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+val _ = type_abbrev((* 'a *) "bitvector" , ``: 'a words$word``);
+
+val _ = Define `
+ ((MEM_fence_rw_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_r))`;
+
+val _ = Define `
+ ((MEM_fence_rw_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_rw))`;
+
+val _ = Define `
+ ((MEM_fence_rw_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_r))`;
+
+val _ = Define `
+ ((MEM_fence_r_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_r))`;
+
+val _ = Define `
+ ((MEM_fence_tso:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_tso))`;
+
+val _ = Define `
+ ((MEM_fence_i:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_i))`;
+
+
+(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*)
+
+val _ = Define `
+ ((MEMea:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$returnS () ))`;
+
+val _ = Define `
+ ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1=
+ (sail2_state_monad$returnS () ))`;
+
+
+(*val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*)
+
+val _ = Define `
+ ((MEMr:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserved_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addrsize addr size1))`;
+
+
+(*val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+(*val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e*)
+
+val _ = Define `
+ ((MEMw:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_strong_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addrsize addr size1))`;
+
+val _ = Define `
+ ((MEMw_conditional_strong_release:int -> int -> 'a words$word -> 'a words$word -> 'b words$word ->('rv,(bool),'e)sail2_state_monad$monadS) addrsize size1 hexRAM addr= (sail2_state_monad$write_memS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addrsize addr size1))`;
+
+
+(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((load_reservation:'a words$word -> unit) addr= () )`;
+
+
+val _ = Define `
+ ((speculate_conditional_success:unit -> 'a sail2_state_monad$sequential_state ->(((bool),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$excl_resultS () ))`;
+
+
+val _ = Define `
+ ((match_reservation:'a -> bool) _= T)`;
+
+val _ = Define `
+ ((cancel_reservation:unit -> unit) () = () )`;
+
+
+(*val sys_enable_writable_misa : unit -> bool*)
+val _ = Define `
+ ((sys_enable_writable_misa:unit -> bool) () = T)`;
+
+
+(*val sys_enable_rvc : unit -> bool*)
+val _ = Define `
+ ((sys_enable_rvc:unit -> bool) () = T)`;
+
+
+(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_ram_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_ram_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_rom_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_rom_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_clint_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_enable_dirty_update : unit -> bool*)
+val _ = Define `
+ ((plat_enable_dirty_update:unit -> bool) () = F)`;
+
+
+(*val plat_enable_misaligned_access : unit -> bool*)
+val _ = Define `
+ ((plat_enable_misaligned_access:unit -> bool) () = F)`;
+
+
+(*val plat_enable_pmp : unit -> bool*)
+val _ = Define `
+ ((plat_enable_pmp:unit -> bool) () = F)`;
+
+
+(*val plat_mtval_has_illegal_inst_bits : unit -> bool*)
+val _ = Define `
+ ((plat_mtval_has_illegal_inst_bits:unit -> bool) () = F)`;
+
+
+(*val plat_insns_per_tick : unit -> integer*)
+val _ = Define `
+ ((plat_insns_per_tick:unit -> int) () = (( 1 : int)))`;
+
+
+(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_htif_tohost:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*)
+val _ = Define `
+ ((plat_term_write:'a words$word -> unit) _= () )`;
+
+
+(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*)
+val _ = Define `
+ ((plat_term_read:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`;
+
+
+(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_right:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftr v (lem$w2ui m)))`;
+
+(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_left:'a words$word -> 'b words$word -> 'a words$word) v m= (shiftl v (lem$w2ui m)))`;
+
+
+(*val print_string : string -> string -> unit*)
+val _ = Define `
+ ((print_string:string -> string -> unit) msg s= () )`;
+ (* print_endline (msg ^ s) *)
+
+(*val prerr_string : string -> string -> unit*)
+val _ = Define `
+ ((prerr_string:string -> string -> unit) msg s= (prerr_endline ( STRCAT msg s)))`;
+
+
+(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((prerr_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`;
+
+
+(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((print_bits0:string -> 'a words$word -> unit) msg bs= () )`;
+ (* print_endline (msg ^ (show_bitlist (bits_of bs))) *)
+
+(*val print_dbg : string -> unit*)
+val _ = Define `
+ ((print_dbg:string -> unit) msg= () )`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/RV64/riscv_typesScript.sml b/prover_snapshots/hol4/RV64/riscv_typesScript.sml
new file mode 100644
index 0000000..2af410b
--- /dev/null
+++ b/prover_snapshots/hol4/RV64/riscv_typesScript.sml
@@ -0,0 +1,2236 @@
+(*Generated by Lem from generated_definitions/lem/RV64/riscv_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_types"
+
+(*Generated by Sail from riscv.*)
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_string*)
+(*open import Sail2_operators_mwords*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+
+val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``);
+
+val _ = Hol_datatype `
+ regfp =
+ RFull of (string)
+ | RSlice of ((string # ii # ii))
+ | RSliceBit of ((string # ii))
+ | RField of ((string # string))`;
+
+
+
+
+val _ = type_abbrev( "regfps" , ``: regfp list``);
+
+val _ = Hol_datatype `
+ niafp =
+ NIAFP_successor of (unit)
+ | NIAFP_concrete_address of ( 64 bits)
+ | NIAFP_indirect_address of (unit)`;
+
+
+
+
+val _ = type_abbrev( "niafps" , ``: niafp list``);
+
+val _ = Hol_datatype `
+ diafp = DIAFP_none of (unit) | DIAFP_concrete of ( 64 bits) | DIAFP_reg of (regfp)`;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+val _ = type_abbrev( "xlenbits" , ``: 64 bits``);
+
+val _ = type_abbrev( "mem_meta" , ``: unit``);
+
+
+
+val _ = type_abbrev( "half" , ``: 16 bits``);
+
+val _ = type_abbrev( "word" , ``: 32 bits``);
+
+val _ = type_abbrev( "regidx" , ``: 5 bits``);
+
+val _ = type_abbrev( "cregidx" , ``: 3 bits``);
+
+val _ = type_abbrev( "csreg" , ``: 12 bits``);
+
+val _ = type_abbrev((* 'n *) "regno" , ``: int``);
+
+val _ = type_abbrev( "opcode" , ``: 7 bits``);
+
+val _ = type_abbrev( "imm12" , ``: 12 bits``);
+
+val _ = type_abbrev( "imm20" , ``: 20 bits``);
+
+val _ = type_abbrev( "amo" , ``: 1 bits``);
+
+val _ = Hol_datatype `
+ Architecture = RV32 | RV64 | RV128`;
+
+
+
+
+val _ = type_abbrev( "arch_xlen" , ``: 2 bits``);
+
+val _ = type_abbrev( "priv_level" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ Privilege = User | Supervisor | Machine`;
+
+
+
+
+val _ = Hol_datatype `
+ amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU`;
+
+
+
+
+val _ = Hol_datatype `
+ bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU`;
+
+
+
+
+val _ = Hol_datatype `
+ csrop = CSRRW | CSRRS | CSRRC`;
+
+
+
+
+val _ = Hol_datatype `
+ iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI`;
+
+
+
+
+val _ = Hol_datatype `
+ rop =
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND`;
+
+
+
+
+val _ = Hol_datatype `
+ ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW`;
+
+
+
+
+val _ = Hol_datatype `
+ sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI`;
+
+
+
+
+val _ = Hol_datatype `
+ sopw = RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW`;
+
+
+
+
+val _ = Hol_datatype `
+ uop = RISCV_LUI | RISCV_AUIPC`;
+
+
+
+
+val _ = Hol_datatype `
+ word_width = BYTE | HALF | WORD | DOUBLE`;
+
+
+
+
+val _ = Hol_datatype `
+ ast =
+ UTYPE of (( 20 bits # regidx # uop))
+ | RISCV_JAL of (( 21 bits # regidx))
+ | RISCV_JALR of (( 12 bits # regidx # regidx))
+ | BTYPE of (( 13 bits # regidx # regidx # bop))
+ | ITYPE of (( 12 bits # regidx # regidx # iop))
+ | SHIFTIOP of (( 6 bits # regidx # regidx # sop))
+ | RTYPE of ((regidx # regidx # regidx # rop))
+ | LOAD of (( 12 bits # regidx # regidx # bool # word_width # bool # bool))
+ | STORE of (( 12 bits # regidx # regidx # word_width # bool # bool))
+ | ADDIW of (( 12 bits # regidx # regidx))
+ | SHIFTW of (( 5 bits # regidx # regidx # sop))
+ | RTYPEW of ((regidx # regidx # regidx # ropw))
+ | SHIFTIWOP of (( 5 bits # regidx # regidx # sopw))
+ | FENCE of (( 4 bits # 4 bits))
+ | FENCE_TSO of (( 4 bits # 4 bits))
+ | FENCEI of (unit)
+ | ECALL of (unit)
+ | MRET of (unit)
+ | SRET of (unit)
+ | EBREAK of (unit)
+ | WFI of (unit)
+ | SFENCE_VMA of ((regidx # regidx))
+ | LOADRES of ((bool # bool # regidx # word_width # regidx))
+ | STORECON of ((bool # bool # regidx # regidx # word_width # regidx))
+ | AMO of ((amoop # bool # bool # regidx # regidx # word_width # regidx))
+ | C_NOP of (unit)
+ | C_ADDI4SPN of ((cregidx # 8 bits))
+ | C_LW of (( 5 bits # cregidx # cregidx))
+ | C_LD of (( 5 bits # cregidx # cregidx))
+ | C_SW of (( 5 bits # cregidx # cregidx))
+ | C_SD of (( 5 bits # cregidx # cregidx))
+ | C_ADDI of (( 6 bits # regidx))
+ | C_JAL of ( 11 bits)
+ | C_ADDIW of (( 6 bits # regidx))
+ | C_LI of (( 6 bits # regidx))
+ | C_ADDI16SP of ( 6 bits)
+ | C_LUI of (( 6 bits # regidx))
+ | C_SRLI of (( 6 bits # cregidx))
+ | C_SRAI of (( 6 bits # cregidx))
+ | C_ANDI of (( 6 bits # cregidx))
+ | C_SUB of ((cregidx # cregidx))
+ | C_XOR of ((cregidx # cregidx))
+ | C_OR of ((cregidx # cregidx))
+ | C_AND of ((cregidx # cregidx))
+ | C_SUBW of ((cregidx # cregidx))
+ | C_ADDW of ((cregidx # cregidx))
+ | C_J of ( 11 bits)
+ | C_BEQZ of (( 8 bits # cregidx))
+ | C_BNEZ of (( 8 bits # cregidx))
+ | C_SLLI of (( 6 bits # regidx))
+ | C_LWSP of (( 6 bits # regidx))
+ | C_LDSP of (( 6 bits # regidx))
+ | C_SWSP of (( 6 bits # regidx))
+ | C_SDSP of (( 6 bits # regidx))
+ | C_JR of (regidx)
+ | C_JALR of (regidx)
+ | C_MV of ((regidx # regidx))
+ | C_EBREAK of (unit)
+ | C_ADD of ((regidx # regidx))
+ | MUL of ((regidx # regidx # regidx # bool # bool # bool))
+ | DIV0 of ((regidx # regidx # regidx # bool))
+ | REM of ((regidx # regidx # regidx # bool))
+ | MULW of ((regidx # regidx # regidx))
+ | DIVW of ((regidx # regidx # regidx # bool))
+ | REMW of ((regidx # regidx # regidx # bool))
+ | CSR of (( 12 bits # regidx # regidx # bool # csrop))
+ | URET of (unit)
+ | ILLEGAL of (word)
+ | C_ILLEGAL of (half)`;
+
+
+
+
+val _ = Hol_datatype `
+ Retired = RETIRE_SUCCESS | RETIRE_FAIL`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessType = Read | Write | ReadWrite | Execute`;
+
+
+
+
+val _ = type_abbrev( "exc_code" , ``: 8 bits``);
+
+val _ = Hol_datatype `
+ InterruptType =
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External`;
+
+
+
+
+val _ = Hol_datatype `
+ ExceptionType =
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI`;
+
+
+
+
+val _ = Hol_datatype `
+ exception = Error_not_implemented of (string) | Error_internal_error of (unit)`;
+
+
+
+
+val _ = type_abbrev( "tv_mode" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved`;
+
+
+
+
+val _ = type_abbrev( "ext_status" , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ ExtStatus = Off | Initial | Clean | Dirty`;
+
+
+
+
+val _ = type_abbrev( "satp_mode" , ``: 4 bits``);
+
+val _ = Hol_datatype `
+ SATPMode = Sbare | Sv32 | Sv39 | Sv48`;
+
+
+
+
+val _ = type_abbrev( "csrRW" , ``: 2 bits``);
+
+val _ = type_abbrev( "regtype" , ``: xlenbits``);
+
+val _ = Hol_datatype `
+ Misa = <| Misa_Misa_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_PTE = <| SV48_PTE_SV48_PTE_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ PTE_Bits = <| PTE_Bits_PTE_Bits_chunk_0 : 8 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Pmpcfg_ent = <| Pmpcfg_ent_Pmpcfg_ent_chunk_0 : 8 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mstatus = <| Mstatus_Mstatus_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sstatus = <| Sstatus_Sstatus_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Ustatus = <| Ustatus_Ustatus_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Minterrupts = <| Minterrupts_Minterrupts_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sinterrupts = <| Sinterrupts_Sinterrupts_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Uinterrupts = <| Uinterrupts_Uinterrupts_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Medeleg = <| Medeleg_Medeleg_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Sedeleg = <| Sedeleg_Sedeleg_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mtvec = <| Mtvec_Mtvec_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Satp32 = <| Satp32_Satp32_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Mcause = <| Mcause_Mcause_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Counteren = <| Counteren_Counteren_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ Satp64 = <| Satp64_Satp64_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ PmpAddrMatchType = OFF | TOR | NA4 | NAPOT`;
+
+
+
+
+val _ = type_abbrev( "pmp_addr_range" , ``: ((xlenbits # xlenbits))option``);
+
+val _ = Hol_datatype `
+ pmpAddrMatch = PMP_NoMatch | PMP_PartialMatch | PMP_Match`;
+
+
+
+
+val _ = Hol_datatype `
+ pmpMatch = PMP_Success | PMP_Continue | PMP_Fail`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_FetchAddr_Check = Ext_FetchAddr_OK of (xlenbits) | Ext_FetchAddr_Error of ('a)`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_ControlAddr_Check = Ext_ControlAddr_OK of (xlenbits) | Ext_ControlAddr_Error of ('a)`;
+
+
+
+
+val _ = Hol_datatype `
+ Ext_DataAddr_Check = Ext_DataAddr_OK of (xlenbits) | Ext_DataAddr_Error of ('a)`;
+
+
+
+
+val _ = type_abbrev( "ext_fetch_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_control_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_data_addr_error" , ``: unit``);
+
+val _ = type_abbrev( "ext_exception" , ``: unit``);
+
+val _ = Hol_datatype `
+ sync_exception =
+ <| sync_exception_trap : ExceptionType;
+ sync_exception_excinfo : xlenbits option;
+ sync_exception_ext : ext_exception option |>`;
+
+
+
+val _ = Hol_datatype `
+ interrupt_set =
+ Ints_Pending of (xlenbits) | Ints_Delegated of (xlenbits) | Ints_Empty of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ ctl_result =
+ CTL_TRAP of (sync_exception) | CTL_SRET of (unit) | CTL_MRET of (unit) | CTL_URET of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ MemoryOpResult = MemValue of ('a) | MemException of (ExceptionType)`;
+
+
+
+
+val _ = Hol_datatype `
+ htif_cmd = <| htif_cmd_htif_cmd_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = type_abbrev( "pteAttribs" , ``: 8 bits``);
+
+val _ = Hol_datatype `
+ PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update`;
+
+
+
+
+val _ = type_abbrev( "vaddr32" , ``: 32 bits``);
+
+val _ = type_abbrev( "paddr32" , ``: 34 bits``);
+
+val _ = type_abbrev( "pte32" , ``: 32 bits``);
+
+val _ = type_abbrev( "asid32" , ``: 9 bits``);
+
+val _ = Hol_datatype `
+ SV32_Vaddr = <| SV32_Vaddr_SV32_Vaddr_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_Vaddr = <| SV48_Vaddr_SV48_Vaddr_chunk_0 : 48 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV48_Paddr = <| SV48_Paddr_SV48_Paddr_chunk_0 : 56 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV32_Paddr = <| SV32_Paddr_SV32_Paddr_chunk_0 : 34 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV32_PTE = <| SV32_PTE_SV32_PTE_chunk_0 : 32 words$word |>`;
+
+
+
+val _ = type_abbrev( "paddr64" , ``: 56 bits``);
+
+val _ = type_abbrev( "pte64" , ``: 64 bits``);
+
+val _ = type_abbrev( "asid64" , ``: 16 bits``);
+
+val _ = type_abbrev( "vaddr39" , ``: 39 bits``);
+
+val _ = Hol_datatype `
+ SV39_Vaddr = <| SV39_Vaddr_SV39_Vaddr_chunk_0 : 39 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV39_Paddr = <| SV39_Paddr_SV39_Paddr_chunk_0 : 56 words$word |>`;
+
+
+
+val _ = Hol_datatype `
+ SV39_PTE = <| SV39_PTE_SV39_PTE_chunk_0 : 64 words$word |>`;
+
+
+
+val _ = type_abbrev( "vaddr48" , ``: 48 bits``);
+
+val _ = type_abbrev( "pte48" , ``: 64 bits``);
+
+val _ = Hol_datatype `
+ PTW_Result =
+ PTW_Success of (('paddr # 'pte # 'paddr # ii # bool)) | PTW_Failure of (PTW_Error)`;
+
+
+
+
+val _ = Hol_datatype `
+ TR_Result = TR_Address of ('a_paddr) | TR_Failure of ('b_failure)`;
+
+
+
+
+val _ = Hol_datatype `
+(* ( 'a_asidlen, 'b_valen, 'c_palen, 'd_ptelen) *) TLB_Entry =
+ <| TLB_Entry_asid :'a_asidlen bits;
+ TLB_Entry_global : bool;
+ TLB_Entry_vAddr :'b_valen bits;
+ TLB_Entry_pAddr :'c_palen bits;
+ TLB_Entry_vMatchMask :'b_valen bits;
+ TLB_Entry_vAddrMask :'b_valen bits;
+ TLB_Entry_pte :'d_ptelen bits;
+ TLB_Entry_pteAddr :'c_palen bits;
+ TLB_Entry_age : 64 bits |>`;
+
+
+
+val _ = type_abbrev( "TLB39_Entry" , ``: (16, 39, 56, 64) TLB_Entry``);
+
+val _ = type_abbrev( "TLB48_Entry" , ``: (16, 48, 56, 64) TLB_Entry``);
+
+val _ = Hol_datatype `
+ FetchResult =
+ F_Ext_Error of (ext_fetch_addr_error)
+ | F_Base of (word)
+ | F_RVC of (half)
+ | F_Error of ((ExceptionType # xlenbits))`;
+
+
+
+
+val _ = Hol_datatype `
+ register_value =
+ Regval_vector of ((ii # bool # register_value list))
+ | Regval_list of ( register_value list)
+ | Regval_option of ( register_value option)
+ | Regval_Counteren of (Counteren)
+ | Regval_Mcause of (Mcause)
+ | Regval_Medeleg of (Medeleg)
+ | Regval_Minterrupts of (Minterrupts)
+ | Regval_Misa of (Misa)
+ | Regval_Mstatus of (Mstatus)
+ | Regval_Mtvec of (Mtvec)
+ | Regval_Pmpcfg_ent of (Pmpcfg_ent)
+ | Regval_Privilege of (Privilege)
+ | Regval_Sedeleg of (Sedeleg)
+ | Regval_Sinterrupts of (Sinterrupts)
+ | Regval_TLB_Entry_16_39_56_64 of ( (16, 39, 56, 64)TLB_Entry)
+ | Regval_TLB_Entry_16_48_56_64 of ( (16, 48, 56, 64)TLB_Entry)
+ | Regval_bool of (bool)
+ | Regval_vector_32_dec_bit of ( 32 words$word)
+ | Regval_vector_64_dec_bit of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate =
+ <| satp : 64 words$word;
+ tlb48 : ( (16, 48, 56, 64)TLB_Entry)option;
+ tlb39 : ( (16, 39, 56, 64)TLB_Entry)option;
+ htif_exit_code : 64 words$word;
+ htif_done : bool;
+ htif_tohost : 64 words$word;
+ mtimecmp : 64 words$word;
+ utval : 64 words$word;
+ ucause : Mcause;
+ uepc : 64 words$word;
+ uscratch : 64 words$word;
+ utvec : Mtvec;
+ pmpaddr15 : 64 words$word;
+ pmpaddr14 : 64 words$word;
+ pmpaddr13 : 64 words$word;
+ pmpaddr12 : 64 words$word;
+ pmpaddr11 : 64 words$word;
+ pmpaddr10 : 64 words$word;
+ pmpaddr9 : 64 words$word;
+ pmpaddr8 : 64 words$word;
+ pmpaddr7 : 64 words$word;
+ pmpaddr6 : 64 words$word;
+ pmpaddr5 : 64 words$word;
+ pmpaddr4 : 64 words$word;
+ pmpaddr3 : 64 words$word;
+ pmpaddr2 : 64 words$word;
+ pmpaddr1 : 64 words$word;
+ pmpaddr0 : 64 words$word;
+ pmp15cfg : Pmpcfg_ent;
+ pmp14cfg : Pmpcfg_ent;
+ pmp13cfg : Pmpcfg_ent;
+ pmp12cfg : Pmpcfg_ent;
+ pmp11cfg : Pmpcfg_ent;
+ pmp10cfg : Pmpcfg_ent;
+ pmp9cfg : Pmpcfg_ent;
+ pmp8cfg : Pmpcfg_ent;
+ pmp7cfg : Pmpcfg_ent;
+ pmp6cfg : Pmpcfg_ent;
+ pmp5cfg : Pmpcfg_ent;
+ pmp4cfg : Pmpcfg_ent;
+ pmp3cfg : Pmpcfg_ent;
+ pmp2cfg : Pmpcfg_ent;
+ pmp1cfg : Pmpcfg_ent;
+ pmp0cfg : Pmpcfg_ent;
+ tselect : 64 words$word;
+ stval : 64 words$word;
+ scause : Mcause;
+ sepc : 64 words$word;
+ sscratch : 64 words$word;
+ stvec : Mtvec;
+ sideleg : Sinterrupts;
+ sedeleg : Sedeleg;
+ mhartid : 64 words$word;
+ marchid : 64 words$word;
+ mimpid : 64 words$word;
+ mvendorid : 32 words$word;
+ minstret_written : bool;
+ minstret : 64 words$word;
+ mtime : 64 words$word;
+ mcycle : 64 words$word;
+ scounteren : Counteren;
+ mcounteren : Counteren;
+ mscratch : 64 words$word;
+ mtval : 64 words$word;
+ mepc : 64 words$word;
+ mcause : Mcause;
+ mtvec : Mtvec;
+ medeleg : Medeleg;
+ mideleg : Minterrupts;
+ mie : Minterrupts;
+ mip : Minterrupts;
+ mstatus : Mstatus;
+ misa : Misa;
+ cur_inst : 64 words$word;
+ cur_privilege : Privilege;
+ x31 : 64 words$word;
+ x30 : 64 words$word;
+ x29 : 64 words$word;
+ x28 : 64 words$word;
+ x27 : 64 words$word;
+ x26 : 64 words$word;
+ x25 : 64 words$word;
+ x24 : 64 words$word;
+ x23 : 64 words$word;
+ x22 : 64 words$word;
+ x21 : 64 words$word;
+ x20 : 64 words$word;
+ x19 : 64 words$word;
+ x18 : 64 words$word;
+ x17 : 64 words$word;
+ x16 : 64 words$word;
+ x15 : 64 words$word;
+ x14 : 64 words$word;
+ x13 : 64 words$word;
+ x12 : 64 words$word;
+ x11 : 64 words$word;
+ x10 : 64 words$word;
+ x9 : 64 words$word;
+ x8 : 64 words$word;
+ x7 : 64 words$word;
+ x6 : 64 words$word;
+ x5 : 64 words$word;
+ x4 : 64 words$word;
+ x3 : 64 words$word;
+ x2 : 64 words$word;
+ x1 : 64 words$word;
+ Xs : ( 64 words$word) list;
+ instbits : 64 words$word;
+ nextPC : 64 words$word;
+ PC : 64 words$word |>`;
+
+
+
+
+
+(*val Counteren_of_regval : register_value -> maybe Counteren*)
+
+val _ = Define `
+ ((Counteren_of_regval:register_value ->(Counteren)option) merge_var=
+ ((case merge_var of Regval_Counteren (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Counteren : Counteren -> register_value*)
+
+val _ = Define `
+ ((regval_of_Counteren:Counteren -> register_value) v= (Regval_Counteren v))`;
+
+
+(*val Mcause_of_regval : register_value -> maybe Mcause*)
+
+val _ = Define `
+ ((Mcause_of_regval:register_value ->(Mcause)option) merge_var=
+ ((case merge_var of Regval_Mcause (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mcause : Mcause -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mcause:Mcause -> register_value) v= (Regval_Mcause v))`;
+
+
+(*val Medeleg_of_regval : register_value -> maybe Medeleg*)
+
+val _ = Define `
+ ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var=
+ ((case merge_var of Regval_Medeleg (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Medeleg : Medeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Medeleg:Medeleg -> register_value) v= (Regval_Medeleg v))`;
+
+
+(*val Minterrupts_of_regval : register_value -> maybe Minterrupts*)
+
+val _ = Define `
+ ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var=
+ ((case merge_var of Regval_Minterrupts (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Minterrupts : Minterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Minterrupts:Minterrupts -> register_value) v= (Regval_Minterrupts v))`;
+
+
+(*val Misa_of_regval : register_value -> maybe Misa*)
+
+val _ = Define `
+ ((Misa_of_regval:register_value ->(Misa)option) merge_var= ((case merge_var of Regval_Misa (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Misa : Misa -> register_value*)
+
+val _ = Define `
+ ((regval_of_Misa:Misa -> register_value) v= (Regval_Misa v))`;
+
+
+(*val Mstatus_of_regval : register_value -> maybe Mstatus*)
+
+val _ = Define `
+ ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var=
+ ((case merge_var of Regval_Mstatus (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mstatus : Mstatus -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mstatus:Mstatus -> register_value) v= (Regval_Mstatus v))`;
+
+
+(*val Mtvec_of_regval : register_value -> maybe Mtvec*)
+
+val _ = Define `
+ ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= ((case merge_var of Regval_Mtvec (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Mtvec : Mtvec -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mtvec:Mtvec -> register_value) v= (Regval_Mtvec v))`;
+
+
+(*val Pmpcfg_ent_of_regval : register_value -> maybe Pmpcfg_ent*)
+
+val _ = Define `
+ ((Pmpcfg_ent_of_regval:register_value ->(Pmpcfg_ent)option) merge_var=
+ ((case merge_var of Regval_Pmpcfg_ent (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Pmpcfg_ent : Pmpcfg_ent -> register_value*)
+
+val _ = Define `
+ ((regval_of_Pmpcfg_ent:Pmpcfg_ent -> register_value) v= (Regval_Pmpcfg_ent v))`;
+
+
+(*val Privilege_of_regval : register_value -> maybe Privilege*)
+
+val _ = Define `
+ ((Privilege_of_regval:register_value ->(Privilege)option) merge_var=
+ ((case merge_var of Regval_Privilege (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Privilege : Privilege -> register_value*)
+
+val _ = Define `
+ ((regval_of_Privilege:Privilege -> register_value) v= (Regval_Privilege v))`;
+
+
+(*val Sedeleg_of_regval : register_value -> maybe Sedeleg*)
+
+val _ = Define `
+ ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var=
+ ((case merge_var of Regval_Sedeleg (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Sedeleg : Sedeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sedeleg:Sedeleg -> register_value) v= (Regval_Sedeleg v))`;
+
+
+(*val Sinterrupts_of_regval : register_value -> maybe Sinterrupts*)
+
+val _ = Define `
+ ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var=
+ ((case merge_var of Regval_Sinterrupts (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_Sinterrupts : Sinterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sinterrupts:Sinterrupts -> register_value) v= (Regval_Sinterrupts v))`;
+
+
+(*val TLB_Entry_16_39_56_64_of_regval : register_value -> maybe (TLB_Entry ty16 ty39 ty56 ty64)*)
+
+val _ = Define `
+ ((TLB_Entry_16_39_56_64_of_regval:register_value ->(((16),(39),(56),(64))TLB_Entry)option) merge_var=
+ ((case merge_var of Regval_TLB_Entry_16_39_56_64 (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_TLB_Entry_16_39_56_64 : TLB_Entry ty16 ty39 ty56 ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLB_Entry_16_39_56_64:((16),(39),(56),(64))TLB_Entry -> register_value) v= (Regval_TLB_Entry_16_39_56_64 v))`;
+
+
+(*val TLB_Entry_16_48_56_64_of_regval : register_value -> maybe (TLB_Entry ty16 ty48 ty56 ty64)*)
+
+val _ = Define `
+ ((TLB_Entry_16_48_56_64_of_regval:register_value ->(((16),(48),(56),(64))TLB_Entry)option) merge_var=
+ ((case merge_var of Regval_TLB_Entry_16_48_56_64 (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_TLB_Entry_16_48_56_64 : TLB_Entry ty16 ty48 ty56 ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLB_Entry_16_48_56_64:((16),(48),(56),(64))TLB_Entry -> register_value) v= (Regval_TLB_Entry_16_48_56_64 v))`;
+
+
+(*val bool_of_regval : register_value -> maybe bool*)
+
+val _ = Define `
+ ((bool_of_regval:register_value ->(bool)option) merge_var= ((case merge_var of Regval_bool (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_bool : bool -> register_value*)
+
+val _ = Define `
+ ((regval_of_bool:bool -> register_value) v= (Regval_bool v))`;
+
+
+(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*)
+
+val _ = Define `
+ ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=
+ ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=
+ ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | _ => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1=
+ (\x . (case x of
+ Regval_vector (_, _, v) => just_list (MAP of_regval1 v)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1=
+ (\x . (case x of
+ Regval_list v => just_list (MAP of_regval1 v)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1=
+ (\x . (case x of
+ Regval_option v => SOME (OPTION_BIND v of_regval1)
+ | _ => NONE
+ )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`;
+
+
+
+val _ = Define `
+ ((satp_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "satp";
+ read_from := (\ s . s.satp);
+ write_to := (\ v s . (( s with<| satp := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((tlb48_ref:((regstate),(register_value),((((16),(48),(56),(64))TLB_Entry)option))register_ref)= (<|
+ name := "tlb48";
+ read_from := (\ s . s.tlb48);
+ write_to := (\ v s . (( s with<| tlb48 := v |>)));
+ of_regval := (\ v . option_of_regval (\ v . TLB_Entry_16_48_56_64_of_regval v) v);
+ regval_of := (\ v . regval_of_option (\ v . regval_of_TLB_Entry_16_48_56_64 v) v) |>))`;
+
+
+val _ = Define `
+ ((tlb39_ref:((regstate),(register_value),((((16),(39),(56),(64))TLB_Entry)option))register_ref)= (<|
+ name := "tlb39";
+ read_from := (\ s . s.tlb39);
+ write_to := (\ v s . (( s with<| tlb39 := v |>)));
+ of_regval := (\ v . option_of_regval (\ v . TLB_Entry_16_39_56_64_of_regval v) v);
+ regval_of := (\ v . regval_of_option (\ v . regval_of_TLB_Entry_16_39_56_64 v) v) |>))`;
+
+
+val _ = Define `
+ ((htif_exit_code_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "htif_exit_code";
+ read_from := (\ s . s.htif_exit_code);
+ write_to := (\ v s . (( s with<| htif_exit_code := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((htif_done_ref:((regstate),(register_value),(bool))register_ref)= (<|
+ name := "htif_done";
+ read_from := (\ s . s.htif_done);
+ write_to := (\ v s . (( s with<| htif_done := v |>)));
+ of_regval := (\ v . bool_of_regval v);
+ regval_of := (\ v . regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((htif_tohost_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "htif_tohost";
+ read_from := (\ s . s.htif_tohost);
+ write_to := (\ v s . (( s with<| htif_tohost := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtimecmp_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mtimecmp";
+ read_from := (\ s . s.mtimecmp);
+ write_to := (\ v s . (( s with<| mtimecmp := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((utval_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "utval";
+ read_from := (\ s . s.utval);
+ write_to := (\ v s . (( s with<| utval := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((ucause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "ucause";
+ read_from := (\ s . s.ucause);
+ write_to := (\ v s . (( s with<| ucause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((uepc_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "uepc";
+ read_from := (\ s . s.uepc);
+ write_to := (\ v s . (( s with<| uepc := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((uscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "uscratch";
+ read_from := (\ s . s.uscratch);
+ write_to := (\ v s . (( s with<| uscratch := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((utvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "utvec";
+ read_from := (\ s . s.utvec);
+ write_to := (\ v s . (( s with<| utvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr15_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr15";
+ read_from := (\ s . s.pmpaddr15);
+ write_to := (\ v s . (( s with<| pmpaddr15 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr14_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr14";
+ read_from := (\ s . s.pmpaddr14);
+ write_to := (\ v s . (( s with<| pmpaddr14 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr13_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr13";
+ read_from := (\ s . s.pmpaddr13);
+ write_to := (\ v s . (( s with<| pmpaddr13 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr12_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr12";
+ read_from := (\ s . s.pmpaddr12);
+ write_to := (\ v s . (( s with<| pmpaddr12 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr11_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr11";
+ read_from := (\ s . s.pmpaddr11);
+ write_to := (\ v s . (( s with<| pmpaddr11 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr10_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr10";
+ read_from := (\ s . s.pmpaddr10);
+ write_to := (\ v s . (( s with<| pmpaddr10 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr9_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr9";
+ read_from := (\ s . s.pmpaddr9);
+ write_to := (\ v s . (( s with<| pmpaddr9 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr8_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr8";
+ read_from := (\ s . s.pmpaddr8);
+ write_to := (\ v s . (( s with<| pmpaddr8 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr7_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr7";
+ read_from := (\ s . s.pmpaddr7);
+ write_to := (\ v s . (( s with<| pmpaddr7 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr6_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr6";
+ read_from := (\ s . s.pmpaddr6);
+ write_to := (\ v s . (( s with<| pmpaddr6 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr5_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr5";
+ read_from := (\ s . s.pmpaddr5);
+ write_to := (\ v s . (( s with<| pmpaddr5 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr4_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr4";
+ read_from := (\ s . s.pmpaddr4);
+ write_to := (\ v s . (( s with<| pmpaddr4 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr3";
+ read_from := (\ s . s.pmpaddr3);
+ write_to := (\ v s . (( s with<| pmpaddr3 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr2";
+ read_from := (\ s . s.pmpaddr2);
+ write_to := (\ v s . (( s with<| pmpaddr2 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr1";
+ read_from := (\ s . s.pmpaddr1);
+ write_to := (\ v s . (( s with<| pmpaddr1 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr0_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "pmpaddr0";
+ read_from := (\ s . s.pmpaddr0);
+ write_to := (\ v s . (( s with<| pmpaddr0 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmp15cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp15cfg";
+ read_from := (\ s . s.pmp15cfg);
+ write_to := (\ v s . (( s with<| pmp15cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp14cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp14cfg";
+ read_from := (\ s . s.pmp14cfg);
+ write_to := (\ v s . (( s with<| pmp14cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp13cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp13cfg";
+ read_from := (\ s . s.pmp13cfg);
+ write_to := (\ v s . (( s with<| pmp13cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp12cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp12cfg";
+ read_from := (\ s . s.pmp12cfg);
+ write_to := (\ v s . (( s with<| pmp12cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp11cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp11cfg";
+ read_from := (\ s . s.pmp11cfg);
+ write_to := (\ v s . (( s with<| pmp11cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp10cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp10cfg";
+ read_from := (\ s . s.pmp10cfg);
+ write_to := (\ v s . (( s with<| pmp10cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp9cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp9cfg";
+ read_from := (\ s . s.pmp9cfg);
+ write_to := (\ v s . (( s with<| pmp9cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp8cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp8cfg";
+ read_from := (\ s . s.pmp8cfg);
+ write_to := (\ v s . (( s with<| pmp8cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp7cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp7cfg";
+ read_from := (\ s . s.pmp7cfg);
+ write_to := (\ v s . (( s with<| pmp7cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp6cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp6cfg";
+ read_from := (\ s . s.pmp6cfg);
+ write_to := (\ v s . (( s with<| pmp6cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp5cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp5cfg";
+ read_from := (\ s . s.pmp5cfg);
+ write_to := (\ v s . (( s with<| pmp5cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp4cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp4cfg";
+ read_from := (\ s . s.pmp4cfg);
+ write_to := (\ v s . (( s with<| pmp4cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp3cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp3cfg";
+ read_from := (\ s . s.pmp3cfg);
+ write_to := (\ v s . (( s with<| pmp3cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp2cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp2cfg";
+ read_from := (\ s . s.pmp2cfg);
+ write_to := (\ v s . (( s with<| pmp2cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp1cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp1cfg";
+ read_from := (\ s . s.pmp1cfg);
+ write_to := (\ v s . (( s with<| pmp1cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((pmp0cfg_ref:((regstate),(register_value),(Pmpcfg_ent))register_ref)= (<|
+ name := "pmp0cfg";
+ read_from := (\ s . s.pmp0cfg);
+ write_to := (\ v s . (( s with<| pmp0cfg := v |>)));
+ of_regval := (\ v . Pmpcfg_ent_of_regval v);
+ regval_of := (\ v . regval_of_Pmpcfg_ent v) |>))`;
+
+
+val _ = Define `
+ ((tselect_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "tselect";
+ read_from := (\ s . s.tselect);
+ write_to := (\ v s . (( s with<| tselect := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((stval_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "stval";
+ read_from := (\ s . s.stval);
+ write_to := (\ v s . (( s with<| stval := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((scause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "scause";
+ read_from := (\ s . s.scause);
+ write_to := (\ v s . (( s with<| scause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((sepc_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "sepc";
+ read_from := (\ s . s.sepc);
+ write_to := (\ v s . (( s with<| sepc := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((sscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "sscratch";
+ read_from := (\ s . s.sscratch);
+ write_to := (\ v s . (( s with<| sscratch := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((stvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "stvec";
+ read_from := (\ s . s.stvec);
+ write_to := (\ v s . (( s with<| stvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((sideleg_ref:((regstate),(register_value),(Sinterrupts))register_ref)= (<|
+ name := "sideleg";
+ read_from := (\ s . s.sideleg);
+ write_to := (\ v s . (( s with<| sideleg := v |>)));
+ of_regval := (\ v . Sinterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Sinterrupts v) |>))`;
+
+
+val _ = Define `
+ ((sedeleg_ref:((regstate),(register_value),(Sedeleg))register_ref)= (<|
+ name := "sedeleg";
+ read_from := (\ s . s.sedeleg);
+ write_to := (\ v s . (( s with<| sedeleg := v |>)));
+ of_regval := (\ v . Sedeleg_of_regval v);
+ regval_of := (\ v . regval_of_Sedeleg v) |>))`;
+
+
+val _ = Define `
+ ((mhartid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mhartid";
+ read_from := (\ s . s.mhartid);
+ write_to := (\ v s . (( s with<| mhartid := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((marchid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "marchid";
+ read_from := (\ s . s.marchid);
+ write_to := (\ v s . (( s with<| marchid := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mimpid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mimpid";
+ read_from := (\ s . s.mimpid);
+ write_to := (\ v s . (( s with<| mimpid := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mvendorid_ref:((regstate),(register_value),((32)words$word))register_ref)= (<|
+ name := "mvendorid";
+ read_from := (\ s . s.mvendorid);
+ write_to := (\ v s . (( s with<| mvendorid := v |>)));
+ of_regval := (\ v . vector_32_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((minstret_written_ref:((regstate),(register_value),(bool))register_ref)= (<|
+ name := "minstret_written";
+ read_from := (\ s . s.minstret_written);
+ write_to := (\ v s . (( s with<| minstret_written := v |>)));
+ of_regval := (\ v . bool_of_regval v);
+ regval_of := (\ v . regval_of_bool v) |>))`;
+
+
+val _ = Define `
+ ((minstret_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "minstret";
+ read_from := (\ s . s.minstret);
+ write_to := (\ v s . (( s with<| minstret := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtime_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mtime";
+ read_from := (\ s . s.mtime);
+ write_to := (\ v s . (( s with<| mtime := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcycle_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mcycle";
+ read_from := (\ s . s.mcycle);
+ write_to := (\ v s . (( s with<| mcycle := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((scounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<|
+ name := "scounteren";
+ read_from := (\ s . s.scounteren);
+ write_to := (\ v s . (( s with<| scounteren := v |>)));
+ of_regval := (\ v . Counteren_of_regval v);
+ regval_of := (\ v . regval_of_Counteren v) |>))`;
+
+
+val _ = Define `
+ ((mcounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<|
+ name := "mcounteren";
+ read_from := (\ s . s.mcounteren);
+ write_to := (\ v s . (( s with<| mcounteren := v |>)));
+ of_regval := (\ v . Counteren_of_regval v);
+ regval_of := (\ v . regval_of_Counteren v) |>))`;
+
+
+val _ = Define `
+ ((mscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mscratch";
+ read_from := (\ s . s.mscratch);
+ write_to := (\ v s . (( s with<| mscratch := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtval_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mtval";
+ read_from := (\ s . s.mtval);
+ write_to := (\ v s . (( s with<| mtval := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mepc_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "mepc";
+ read_from := (\ s . s.mepc);
+ write_to := (\ v s . (( s with<| mepc := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcause_ref:((regstate),(register_value),(Mcause))register_ref)= (<|
+ name := "mcause";
+ read_from := (\ s . s.mcause);
+ write_to := (\ v s . (( s with<| mcause := v |>)));
+ of_regval := (\ v . Mcause_of_regval v);
+ regval_of := (\ v . regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((mtvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<|
+ name := "mtvec";
+ read_from := (\ s . s.mtvec);
+ write_to := (\ v s . (( s with<| mtvec := v |>)));
+ of_regval := (\ v . Mtvec_of_regval v);
+ regval_of := (\ v . regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((medeleg_ref:((regstate),(register_value),(Medeleg))register_ref)= (<|
+ name := "medeleg";
+ read_from := (\ s . s.medeleg);
+ write_to := (\ v s . (( s with<| medeleg := v |>)));
+ of_regval := (\ v . Medeleg_of_regval v);
+ regval_of := (\ v . regval_of_Medeleg v) |>))`;
+
+
+val _ = Define `
+ ((mideleg_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mideleg";
+ read_from := (\ s . s.mideleg);
+ write_to := (\ v s . (( s with<| mideleg := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mie_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mie";
+ read_from := (\ s . s.mie);
+ write_to := (\ v s . (( s with<| mie := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mip_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<|
+ name := "mip";
+ read_from := (\ s . s.mip);
+ write_to := (\ v s . (( s with<| mip := v |>)));
+ of_regval := (\ v . Minterrupts_of_regval v);
+ regval_of := (\ v . regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mstatus_ref:((regstate),(register_value),(Mstatus))register_ref)= (<|
+ name := "mstatus";
+ read_from := (\ s . s.mstatus);
+ write_to := (\ v s . (( s with<| mstatus := v |>)));
+ of_regval := (\ v . Mstatus_of_regval v);
+ regval_of := (\ v . regval_of_Mstatus v) |>))`;
+
+
+val _ = Define `
+ ((misa_ref:((regstate),(register_value),(Misa))register_ref)= (<|
+ name := "misa";
+ read_from := (\ s . s.misa);
+ write_to := (\ v s . (( s with<| misa := v |>)));
+ of_regval := (\ v . Misa_of_regval v);
+ regval_of := (\ v . regval_of_Misa v) |>))`;
+
+
+val _ = Define `
+ ((cur_inst_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "cur_inst";
+ read_from := (\ s . s.cur_inst);
+ write_to := (\ v s . (( s with<| cur_inst := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((cur_privilege_ref:((regstate),(register_value),(Privilege))register_ref)= (<|
+ name := "cur_privilege";
+ read_from := (\ s . s.cur_privilege);
+ write_to := (\ v s . (( s with<| cur_privilege := v |>)));
+ of_regval := (\ v . Privilege_of_regval v);
+ regval_of := (\ v . regval_of_Privilege v) |>))`;
+
+
+val _ = Define `
+ ((x31_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x31";
+ read_from := (\ s . s.x31);
+ write_to := (\ v s . (( s with<| x31 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x30_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x30";
+ read_from := (\ s . s.x30);
+ write_to := (\ v s . (( s with<| x30 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x29_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x29";
+ read_from := (\ s . s.x29);
+ write_to := (\ v s . (( s with<| x29 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x28_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x28";
+ read_from := (\ s . s.x28);
+ write_to := (\ v s . (( s with<| x28 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x27_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x27";
+ read_from := (\ s . s.x27);
+ write_to := (\ v s . (( s with<| x27 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x26_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x26";
+ read_from := (\ s . s.x26);
+ write_to := (\ v s . (( s with<| x26 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x25_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x25";
+ read_from := (\ s . s.x25);
+ write_to := (\ v s . (( s with<| x25 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x24_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x24";
+ read_from := (\ s . s.x24);
+ write_to := (\ v s . (( s with<| x24 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x23_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x23";
+ read_from := (\ s . s.x23);
+ write_to := (\ v s . (( s with<| x23 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x22_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x22";
+ read_from := (\ s . s.x22);
+ write_to := (\ v s . (( s with<| x22 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x21_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x21";
+ read_from := (\ s . s.x21);
+ write_to := (\ v s . (( s with<| x21 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x20_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x20";
+ read_from := (\ s . s.x20);
+ write_to := (\ v s . (( s with<| x20 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x19_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x19";
+ read_from := (\ s . s.x19);
+ write_to := (\ v s . (( s with<| x19 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x18_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x18";
+ read_from := (\ s . s.x18);
+ write_to := (\ v s . (( s with<| x18 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x17_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x17";
+ read_from := (\ s . s.x17);
+ write_to := (\ v s . (( s with<| x17 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x16_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x16";
+ read_from := (\ s . s.x16);
+ write_to := (\ v s . (( s with<| x16 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x15_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x15";
+ read_from := (\ s . s.x15);
+ write_to := (\ v s . (( s with<| x15 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x14_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x14";
+ read_from := (\ s . s.x14);
+ write_to := (\ v s . (( s with<| x14 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x13_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x13";
+ read_from := (\ s . s.x13);
+ write_to := (\ v s . (( s with<| x13 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x12_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x12";
+ read_from := (\ s . s.x12);
+ write_to := (\ v s . (( s with<| x12 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x11_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x11";
+ read_from := (\ s . s.x11);
+ write_to := (\ v s . (( s with<| x11 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x10_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x10";
+ read_from := (\ s . s.x10);
+ write_to := (\ v s . (( s with<| x10 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x9_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x9";
+ read_from := (\ s . s.x9);
+ write_to := (\ v s . (( s with<| x9 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x8_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x8";
+ read_from := (\ s . s.x8);
+ write_to := (\ v s . (( s with<| x8 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x7_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x7";
+ read_from := (\ s . s.x7);
+ write_to := (\ v s . (( s with<| x7 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x6_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x6";
+ read_from := (\ s . s.x6);
+ write_to := (\ v s . (( s with<| x6 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x5_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x5";
+ read_from := (\ s . s.x5);
+ write_to := (\ v s . (( s with<| x5 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x4_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x4";
+ read_from := (\ s . s.x4);
+ write_to := (\ v s . (( s with<| x4 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x3";
+ read_from := (\ s . s.x3);
+ write_to := (\ v s . (( s with<| x3 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x2";
+ read_from := (\ s . s.x2);
+ write_to := (\ v s . (( s with<| x2 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((x1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "x1";
+ read_from := (\ s . s.x1);
+ write_to := (\ v s . (( s with<| x1 := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((Xs_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<|
+ name := "Xs";
+ read_from := (\ s . s.Xs);
+ write_to := (\ v s . (( s with<| Xs := v |>)));
+ of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v);
+ regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((instbits_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "instbits";
+ read_from := (\ s . s.instbits);
+ write_to := (\ v s . (( s with<| instbits := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((nextPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "nextPC";
+ read_from := (\ s . s.nextPC);
+ write_to := (\ v s . (( s with<| nextPC := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<|
+ name := "PC";
+ read_from := (\ s . s.PC);
+ write_to := (\ v s . (( s with<| PC := v |>)));
+ of_regval := (\ v . vector_64_dec_bit_of_regval v);
+ regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`;
+
+
+(*val get_regval : string -> regstate -> maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=
+ (if reg_name = "satp" then SOME (satp_ref.regval_of (satp_ref.read_from s)) else
+ if reg_name = "tlb48" then SOME (tlb48_ref.regval_of (tlb48_ref.read_from s)) else
+ if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else
+ if reg_name = "htif_exit_code" then SOME (htif_exit_code_ref.regval_of (htif_exit_code_ref.read_from s)) else
+ if reg_name = "htif_done" then SOME (htif_done_ref.regval_of (htif_done_ref.read_from s)) else
+ if reg_name = "htif_tohost" then SOME (htif_tohost_ref.regval_of (htif_tohost_ref.read_from s)) else
+ if reg_name = "mtimecmp" then SOME (mtimecmp_ref.regval_of (mtimecmp_ref.read_from s)) else
+ if reg_name = "utval" then SOME (utval_ref.regval_of (utval_ref.read_from s)) else
+ if reg_name = "ucause" then SOME (ucause_ref.regval_of (ucause_ref.read_from s)) else
+ if reg_name = "uepc" then SOME (uepc_ref.regval_of (uepc_ref.read_from s)) else
+ if reg_name = "uscratch" then SOME (uscratch_ref.regval_of (uscratch_ref.read_from s)) else
+ if reg_name = "utvec" then SOME (utvec_ref.regval_of (utvec_ref.read_from s)) else
+ if reg_name = "pmpaddr15" then SOME (pmpaddr15_ref.regval_of (pmpaddr15_ref.read_from s)) else
+ if reg_name = "pmpaddr14" then SOME (pmpaddr14_ref.regval_of (pmpaddr14_ref.read_from s)) else
+ if reg_name = "pmpaddr13" then SOME (pmpaddr13_ref.regval_of (pmpaddr13_ref.read_from s)) else
+ if reg_name = "pmpaddr12" then SOME (pmpaddr12_ref.regval_of (pmpaddr12_ref.read_from s)) else
+ if reg_name = "pmpaddr11" then SOME (pmpaddr11_ref.regval_of (pmpaddr11_ref.read_from s)) else
+ if reg_name = "pmpaddr10" then SOME (pmpaddr10_ref.regval_of (pmpaddr10_ref.read_from s)) else
+ if reg_name = "pmpaddr9" then SOME (pmpaddr9_ref.regval_of (pmpaddr9_ref.read_from s)) else
+ if reg_name = "pmpaddr8" then SOME (pmpaddr8_ref.regval_of (pmpaddr8_ref.read_from s)) else
+ if reg_name = "pmpaddr7" then SOME (pmpaddr7_ref.regval_of (pmpaddr7_ref.read_from s)) else
+ if reg_name = "pmpaddr6" then SOME (pmpaddr6_ref.regval_of (pmpaddr6_ref.read_from s)) else
+ if reg_name = "pmpaddr5" then SOME (pmpaddr5_ref.regval_of (pmpaddr5_ref.read_from s)) else
+ if reg_name = "pmpaddr4" then SOME (pmpaddr4_ref.regval_of (pmpaddr4_ref.read_from s)) else
+ if reg_name = "pmpaddr3" then SOME (pmpaddr3_ref.regval_of (pmpaddr3_ref.read_from s)) else
+ if reg_name = "pmpaddr2" then SOME (pmpaddr2_ref.regval_of (pmpaddr2_ref.read_from s)) else
+ if reg_name = "pmpaddr1" then SOME (pmpaddr1_ref.regval_of (pmpaddr1_ref.read_from s)) else
+ if reg_name = "pmpaddr0" then SOME (pmpaddr0_ref.regval_of (pmpaddr0_ref.read_from s)) else
+ if reg_name = "pmp15cfg" then SOME (pmp15cfg_ref.regval_of (pmp15cfg_ref.read_from s)) else
+ if reg_name = "pmp14cfg" then SOME (pmp14cfg_ref.regval_of (pmp14cfg_ref.read_from s)) else
+ if reg_name = "pmp13cfg" then SOME (pmp13cfg_ref.regval_of (pmp13cfg_ref.read_from s)) else
+ if reg_name = "pmp12cfg" then SOME (pmp12cfg_ref.regval_of (pmp12cfg_ref.read_from s)) else
+ if reg_name = "pmp11cfg" then SOME (pmp11cfg_ref.regval_of (pmp11cfg_ref.read_from s)) else
+ if reg_name = "pmp10cfg" then SOME (pmp10cfg_ref.regval_of (pmp10cfg_ref.read_from s)) else
+ if reg_name = "pmp9cfg" then SOME (pmp9cfg_ref.regval_of (pmp9cfg_ref.read_from s)) else
+ if reg_name = "pmp8cfg" then SOME (pmp8cfg_ref.regval_of (pmp8cfg_ref.read_from s)) else
+ if reg_name = "pmp7cfg" then SOME (pmp7cfg_ref.regval_of (pmp7cfg_ref.read_from s)) else
+ if reg_name = "pmp6cfg" then SOME (pmp6cfg_ref.regval_of (pmp6cfg_ref.read_from s)) else
+ if reg_name = "pmp5cfg" then SOME (pmp5cfg_ref.regval_of (pmp5cfg_ref.read_from s)) else
+ if reg_name = "pmp4cfg" then SOME (pmp4cfg_ref.regval_of (pmp4cfg_ref.read_from s)) else
+ if reg_name = "pmp3cfg" then SOME (pmp3cfg_ref.regval_of (pmp3cfg_ref.read_from s)) else
+ if reg_name = "pmp2cfg" then SOME (pmp2cfg_ref.regval_of (pmp2cfg_ref.read_from s)) else
+ if reg_name = "pmp1cfg" then SOME (pmp1cfg_ref.regval_of (pmp1cfg_ref.read_from s)) else
+ if reg_name = "pmp0cfg" then SOME (pmp0cfg_ref.regval_of (pmp0cfg_ref.read_from s)) else
+ if reg_name = "tselect" then SOME (tselect_ref.regval_of (tselect_ref.read_from s)) else
+ if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else
+ if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else
+ if reg_name = "sepc" then SOME (sepc_ref.regval_of (sepc_ref.read_from s)) else
+ if reg_name = "sscratch" then SOME (sscratch_ref.regval_of (sscratch_ref.read_from s)) else
+ if reg_name = "stvec" then SOME (stvec_ref.regval_of (stvec_ref.read_from s)) else
+ if reg_name = "sideleg" then SOME (sideleg_ref.regval_of (sideleg_ref.read_from s)) else
+ if reg_name = "sedeleg" then SOME (sedeleg_ref.regval_of (sedeleg_ref.read_from s)) else
+ if reg_name = "mhartid" then SOME (mhartid_ref.regval_of (mhartid_ref.read_from s)) else
+ if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else
+ if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else
+ if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else
+ if reg_name = "minstret_written" then SOME (minstret_written_ref.regval_of (minstret_written_ref.read_from s)) else
+ if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else
+ if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else
+ if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else
+ if reg_name = "scounteren" then SOME (scounteren_ref.regval_of (scounteren_ref.read_from s)) else
+ if reg_name = "mcounteren" then SOME (mcounteren_ref.regval_of (mcounteren_ref.read_from s)) else
+ if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else
+ if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else
+ if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else
+ if reg_name = "mcause" then SOME (mcause_ref.regval_of (mcause_ref.read_from s)) else
+ if reg_name = "mtvec" then SOME (mtvec_ref.regval_of (mtvec_ref.read_from s)) else
+ if reg_name = "medeleg" then SOME (medeleg_ref.regval_of (medeleg_ref.read_from s)) else
+ if reg_name = "mideleg" then SOME (mideleg_ref.regval_of (mideleg_ref.read_from s)) else
+ if reg_name = "mie" then SOME (mie_ref.regval_of (mie_ref.read_from s)) else
+ if reg_name = "mip" then SOME (mip_ref.regval_of (mip_ref.read_from s)) else
+ if reg_name = "mstatus" then SOME (mstatus_ref.regval_of (mstatus_ref.read_from s)) else
+ if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else
+ if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else
+ if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else
+ if reg_name = "x31" then SOME (x31_ref.regval_of (x31_ref.read_from s)) else
+ if reg_name = "x30" then SOME (x30_ref.regval_of (x30_ref.read_from s)) else
+ if reg_name = "x29" then SOME (x29_ref.regval_of (x29_ref.read_from s)) else
+ if reg_name = "x28" then SOME (x28_ref.regval_of (x28_ref.read_from s)) else
+ if reg_name = "x27" then SOME (x27_ref.regval_of (x27_ref.read_from s)) else
+ if reg_name = "x26" then SOME (x26_ref.regval_of (x26_ref.read_from s)) else
+ if reg_name = "x25" then SOME (x25_ref.regval_of (x25_ref.read_from s)) else
+ if reg_name = "x24" then SOME (x24_ref.regval_of (x24_ref.read_from s)) else
+ if reg_name = "x23" then SOME (x23_ref.regval_of (x23_ref.read_from s)) else
+ if reg_name = "x22" then SOME (x22_ref.regval_of (x22_ref.read_from s)) else
+ if reg_name = "x21" then SOME (x21_ref.regval_of (x21_ref.read_from s)) else
+ if reg_name = "x20" then SOME (x20_ref.regval_of (x20_ref.read_from s)) else
+ if reg_name = "x19" then SOME (x19_ref.regval_of (x19_ref.read_from s)) else
+ if reg_name = "x18" then SOME (x18_ref.regval_of (x18_ref.read_from s)) else
+ if reg_name = "x17" then SOME (x17_ref.regval_of (x17_ref.read_from s)) else
+ if reg_name = "x16" then SOME (x16_ref.regval_of (x16_ref.read_from s)) else
+ if reg_name = "x15" then SOME (x15_ref.regval_of (x15_ref.read_from s)) else
+ if reg_name = "x14" then SOME (x14_ref.regval_of (x14_ref.read_from s)) else
+ if reg_name = "x13" then SOME (x13_ref.regval_of (x13_ref.read_from s)) else
+ if reg_name = "x12" then SOME (x12_ref.regval_of (x12_ref.read_from s)) else
+ if reg_name = "x11" then SOME (x11_ref.regval_of (x11_ref.read_from s)) else
+ if reg_name = "x10" then SOME (x10_ref.regval_of (x10_ref.read_from s)) else
+ if reg_name = "x9" then SOME (x9_ref.regval_of (x9_ref.read_from s)) else
+ if reg_name = "x8" then SOME (x8_ref.regval_of (x8_ref.read_from s)) else
+ if reg_name = "x7" then SOME (x7_ref.regval_of (x7_ref.read_from s)) else
+ if reg_name = "x6" then SOME (x6_ref.regval_of (x6_ref.read_from s)) else
+ if reg_name = "x5" then SOME (x5_ref.regval_of (x5_ref.read_from s)) else
+ if reg_name = "x4" then SOME (x4_ref.regval_of (x4_ref.read_from s)) else
+ if reg_name = "x3" then SOME (x3_ref.regval_of (x3_ref.read_from s)) else
+ if reg_name = "x2" then SOME (x2_ref.regval_of (x2_ref.read_from s)) else
+ if reg_name = "x1" then SOME (x1_ref.regval_of (x1_ref.read_from s)) else
+ if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else
+ if reg_name = "instbits" then SOME (instbits_ref.regval_of (instbits_ref.read_from s)) else
+ if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
+ if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+ NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=
+ (if reg_name = "satp" then OPTION_MAP (\ v . satp_ref.write_to v s) (satp_ref.of_regval v) else
+ if reg_name = "tlb48" then OPTION_MAP (\ v . tlb48_ref.write_to v s) (tlb48_ref.of_regval v) else
+ if reg_name = "tlb39" then OPTION_MAP (\ v . tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else
+ if reg_name = "htif_exit_code" then OPTION_MAP (\ v . htif_exit_code_ref.write_to v s) (htif_exit_code_ref.of_regval v) else
+ if reg_name = "htif_done" then OPTION_MAP (\ v . htif_done_ref.write_to v s) (htif_done_ref.of_regval v) else
+ if reg_name = "htif_tohost" then OPTION_MAP (\ v . htif_tohost_ref.write_to v s) (htif_tohost_ref.of_regval v) else
+ if reg_name = "mtimecmp" then OPTION_MAP (\ v . mtimecmp_ref.write_to v s) (mtimecmp_ref.of_regval v) else
+ if reg_name = "utval" then OPTION_MAP (\ v . utval_ref.write_to v s) (utval_ref.of_regval v) else
+ if reg_name = "ucause" then OPTION_MAP (\ v . ucause_ref.write_to v s) (ucause_ref.of_regval v) else
+ if reg_name = "uepc" then OPTION_MAP (\ v . uepc_ref.write_to v s) (uepc_ref.of_regval v) else
+ if reg_name = "uscratch" then OPTION_MAP (\ v . uscratch_ref.write_to v s) (uscratch_ref.of_regval v) else
+ if reg_name = "utvec" then OPTION_MAP (\ v . utvec_ref.write_to v s) (utvec_ref.of_regval v) else
+ if reg_name = "pmpaddr15" then OPTION_MAP (\ v . pmpaddr15_ref.write_to v s) (pmpaddr15_ref.of_regval v) else
+ if reg_name = "pmpaddr14" then OPTION_MAP (\ v . pmpaddr14_ref.write_to v s) (pmpaddr14_ref.of_regval v) else
+ if reg_name = "pmpaddr13" then OPTION_MAP (\ v . pmpaddr13_ref.write_to v s) (pmpaddr13_ref.of_regval v) else
+ if reg_name = "pmpaddr12" then OPTION_MAP (\ v . pmpaddr12_ref.write_to v s) (pmpaddr12_ref.of_regval v) else
+ if reg_name = "pmpaddr11" then OPTION_MAP (\ v . pmpaddr11_ref.write_to v s) (pmpaddr11_ref.of_regval v) else
+ if reg_name = "pmpaddr10" then OPTION_MAP (\ v . pmpaddr10_ref.write_to v s) (pmpaddr10_ref.of_regval v) else
+ if reg_name = "pmpaddr9" then OPTION_MAP (\ v . pmpaddr9_ref.write_to v s) (pmpaddr9_ref.of_regval v) else
+ if reg_name = "pmpaddr8" then OPTION_MAP (\ v . pmpaddr8_ref.write_to v s) (pmpaddr8_ref.of_regval v) else
+ if reg_name = "pmpaddr7" then OPTION_MAP (\ v . pmpaddr7_ref.write_to v s) (pmpaddr7_ref.of_regval v) else
+ if reg_name = "pmpaddr6" then OPTION_MAP (\ v . pmpaddr6_ref.write_to v s) (pmpaddr6_ref.of_regval v) else
+ if reg_name = "pmpaddr5" then OPTION_MAP (\ v . pmpaddr5_ref.write_to v s) (pmpaddr5_ref.of_regval v) else
+ if reg_name = "pmpaddr4" then OPTION_MAP (\ v . pmpaddr4_ref.write_to v s) (pmpaddr4_ref.of_regval v) else
+ if reg_name = "pmpaddr3" then OPTION_MAP (\ v . pmpaddr3_ref.write_to v s) (pmpaddr3_ref.of_regval v) else
+ if reg_name = "pmpaddr2" then OPTION_MAP (\ v . pmpaddr2_ref.write_to v s) (pmpaddr2_ref.of_regval v) else
+ if reg_name = "pmpaddr1" then OPTION_MAP (\ v . pmpaddr1_ref.write_to v s) (pmpaddr1_ref.of_regval v) else
+ if reg_name = "pmpaddr0" then OPTION_MAP (\ v . pmpaddr0_ref.write_to v s) (pmpaddr0_ref.of_regval v) else
+ if reg_name = "pmp15cfg" then OPTION_MAP (\ v . pmp15cfg_ref.write_to v s) (pmp15cfg_ref.of_regval v) else
+ if reg_name = "pmp14cfg" then OPTION_MAP (\ v . pmp14cfg_ref.write_to v s) (pmp14cfg_ref.of_regval v) else
+ if reg_name = "pmp13cfg" then OPTION_MAP (\ v . pmp13cfg_ref.write_to v s) (pmp13cfg_ref.of_regval v) else
+ if reg_name = "pmp12cfg" then OPTION_MAP (\ v . pmp12cfg_ref.write_to v s) (pmp12cfg_ref.of_regval v) else
+ if reg_name = "pmp11cfg" then OPTION_MAP (\ v . pmp11cfg_ref.write_to v s) (pmp11cfg_ref.of_regval v) else
+ if reg_name = "pmp10cfg" then OPTION_MAP (\ v . pmp10cfg_ref.write_to v s) (pmp10cfg_ref.of_regval v) else
+ if reg_name = "pmp9cfg" then OPTION_MAP (\ v . pmp9cfg_ref.write_to v s) (pmp9cfg_ref.of_regval v) else
+ if reg_name = "pmp8cfg" then OPTION_MAP (\ v . pmp8cfg_ref.write_to v s) (pmp8cfg_ref.of_regval v) else
+ if reg_name = "pmp7cfg" then OPTION_MAP (\ v . pmp7cfg_ref.write_to v s) (pmp7cfg_ref.of_regval v) else
+ if reg_name = "pmp6cfg" then OPTION_MAP (\ v . pmp6cfg_ref.write_to v s) (pmp6cfg_ref.of_regval v) else
+ if reg_name = "pmp5cfg" then OPTION_MAP (\ v . pmp5cfg_ref.write_to v s) (pmp5cfg_ref.of_regval v) else
+ if reg_name = "pmp4cfg" then OPTION_MAP (\ v . pmp4cfg_ref.write_to v s) (pmp4cfg_ref.of_regval v) else
+ if reg_name = "pmp3cfg" then OPTION_MAP (\ v . pmp3cfg_ref.write_to v s) (pmp3cfg_ref.of_regval v) else
+ if reg_name = "pmp2cfg" then OPTION_MAP (\ v . pmp2cfg_ref.write_to v s) (pmp2cfg_ref.of_regval v) else
+ if reg_name = "pmp1cfg" then OPTION_MAP (\ v . pmp1cfg_ref.write_to v s) (pmp1cfg_ref.of_regval v) else
+ if reg_name = "pmp0cfg" then OPTION_MAP (\ v . pmp0cfg_ref.write_to v s) (pmp0cfg_ref.of_regval v) else
+ if reg_name = "tselect" then OPTION_MAP (\ v . tselect_ref.write_to v s) (tselect_ref.of_regval v) else
+ if reg_name = "stval" then OPTION_MAP (\ v . stval_ref.write_to v s) (stval_ref.of_regval v) else
+ if reg_name = "scause" then OPTION_MAP (\ v . scause_ref.write_to v s) (scause_ref.of_regval v) else
+ if reg_name = "sepc" then OPTION_MAP (\ v . sepc_ref.write_to v s) (sepc_ref.of_regval v) else
+ if reg_name = "sscratch" then OPTION_MAP (\ v . sscratch_ref.write_to v s) (sscratch_ref.of_regval v) else
+ if reg_name = "stvec" then OPTION_MAP (\ v . stvec_ref.write_to v s) (stvec_ref.of_regval v) else
+ if reg_name = "sideleg" then OPTION_MAP (\ v . sideleg_ref.write_to v s) (sideleg_ref.of_regval v) else
+ if reg_name = "sedeleg" then OPTION_MAP (\ v . sedeleg_ref.write_to v s) (sedeleg_ref.of_regval v) else
+ if reg_name = "mhartid" then OPTION_MAP (\ v . mhartid_ref.write_to v s) (mhartid_ref.of_regval v) else
+ if reg_name = "marchid" then OPTION_MAP (\ v . marchid_ref.write_to v s) (marchid_ref.of_regval v) else
+ if reg_name = "mimpid" then OPTION_MAP (\ v . mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else
+ if reg_name = "mvendorid" then OPTION_MAP (\ v . mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else
+ if reg_name = "minstret_written" then OPTION_MAP (\ v . minstret_written_ref.write_to v s) (minstret_written_ref.of_regval v) else
+ if reg_name = "minstret" then OPTION_MAP (\ v . minstret_ref.write_to v s) (minstret_ref.of_regval v) else
+ if reg_name = "mtime" then OPTION_MAP (\ v . mtime_ref.write_to v s) (mtime_ref.of_regval v) else
+ if reg_name = "mcycle" then OPTION_MAP (\ v . mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else
+ if reg_name = "scounteren" then OPTION_MAP (\ v . scounteren_ref.write_to v s) (scounteren_ref.of_regval v) else
+ if reg_name = "mcounteren" then OPTION_MAP (\ v . mcounteren_ref.write_to v s) (mcounteren_ref.of_regval v) else
+ if reg_name = "mscratch" then OPTION_MAP (\ v . mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else
+ if reg_name = "mtval" then OPTION_MAP (\ v . mtval_ref.write_to v s) (mtval_ref.of_regval v) else
+ if reg_name = "mepc" then OPTION_MAP (\ v . mepc_ref.write_to v s) (mepc_ref.of_regval v) else
+ if reg_name = "mcause" then OPTION_MAP (\ v . mcause_ref.write_to v s) (mcause_ref.of_regval v) else
+ if reg_name = "mtvec" then OPTION_MAP (\ v . mtvec_ref.write_to v s) (mtvec_ref.of_regval v) else
+ if reg_name = "medeleg" then OPTION_MAP (\ v . medeleg_ref.write_to v s) (medeleg_ref.of_regval v) else
+ if reg_name = "mideleg" then OPTION_MAP (\ v . mideleg_ref.write_to v s) (mideleg_ref.of_regval v) else
+ if reg_name = "mie" then OPTION_MAP (\ v . mie_ref.write_to v s) (mie_ref.of_regval v) else
+ if reg_name = "mip" then OPTION_MAP (\ v . mip_ref.write_to v s) (mip_ref.of_regval v) else
+ if reg_name = "mstatus" then OPTION_MAP (\ v . mstatus_ref.write_to v s) (mstatus_ref.of_regval v) else
+ if reg_name = "misa" then OPTION_MAP (\ v . misa_ref.write_to v s) (misa_ref.of_regval v) else
+ if reg_name = "cur_inst" then OPTION_MAP (\ v . cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else
+ if reg_name = "cur_privilege" then OPTION_MAP (\ v . cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else
+ if reg_name = "x31" then OPTION_MAP (\ v . x31_ref.write_to v s) (x31_ref.of_regval v) else
+ if reg_name = "x30" then OPTION_MAP (\ v . x30_ref.write_to v s) (x30_ref.of_regval v) else
+ if reg_name = "x29" then OPTION_MAP (\ v . x29_ref.write_to v s) (x29_ref.of_regval v) else
+ if reg_name = "x28" then OPTION_MAP (\ v . x28_ref.write_to v s) (x28_ref.of_regval v) else
+ if reg_name = "x27" then OPTION_MAP (\ v . x27_ref.write_to v s) (x27_ref.of_regval v) else
+ if reg_name = "x26" then OPTION_MAP (\ v . x26_ref.write_to v s) (x26_ref.of_regval v) else
+ if reg_name = "x25" then OPTION_MAP (\ v . x25_ref.write_to v s) (x25_ref.of_regval v) else
+ if reg_name = "x24" then OPTION_MAP (\ v . x24_ref.write_to v s) (x24_ref.of_regval v) else
+ if reg_name = "x23" then OPTION_MAP (\ v . x23_ref.write_to v s) (x23_ref.of_regval v) else
+ if reg_name = "x22" then OPTION_MAP (\ v . x22_ref.write_to v s) (x22_ref.of_regval v) else
+ if reg_name = "x21" then OPTION_MAP (\ v . x21_ref.write_to v s) (x21_ref.of_regval v) else
+ if reg_name = "x20" then OPTION_MAP (\ v . x20_ref.write_to v s) (x20_ref.of_regval v) else
+ if reg_name = "x19" then OPTION_MAP (\ v . x19_ref.write_to v s) (x19_ref.of_regval v) else
+ if reg_name = "x18" then OPTION_MAP (\ v . x18_ref.write_to v s) (x18_ref.of_regval v) else
+ if reg_name = "x17" then OPTION_MAP (\ v . x17_ref.write_to v s) (x17_ref.of_regval v) else
+ if reg_name = "x16" then OPTION_MAP (\ v . x16_ref.write_to v s) (x16_ref.of_regval v) else
+ if reg_name = "x15" then OPTION_MAP (\ v . x15_ref.write_to v s) (x15_ref.of_regval v) else
+ if reg_name = "x14" then OPTION_MAP (\ v . x14_ref.write_to v s) (x14_ref.of_regval v) else
+ if reg_name = "x13" then OPTION_MAP (\ v . x13_ref.write_to v s) (x13_ref.of_regval v) else
+ if reg_name = "x12" then OPTION_MAP (\ v . x12_ref.write_to v s) (x12_ref.of_regval v) else
+ if reg_name = "x11" then OPTION_MAP (\ v . x11_ref.write_to v s) (x11_ref.of_regval v) else
+ if reg_name = "x10" then OPTION_MAP (\ v . x10_ref.write_to v s) (x10_ref.of_regval v) else
+ if reg_name = "x9" then OPTION_MAP (\ v . x9_ref.write_to v s) (x9_ref.of_regval v) else
+ if reg_name = "x8" then OPTION_MAP (\ v . x8_ref.write_to v s) (x8_ref.of_regval v) else
+ if reg_name = "x7" then OPTION_MAP (\ v . x7_ref.write_to v s) (x7_ref.of_regval v) else
+ if reg_name = "x6" then OPTION_MAP (\ v . x6_ref.write_to v s) (x6_ref.of_regval v) else
+ if reg_name = "x5" then OPTION_MAP (\ v . x5_ref.write_to v s) (x5_ref.of_regval v) else
+ if reg_name = "x4" then OPTION_MAP (\ v . x4_ref.write_to v s) (x4_ref.of_regval v) else
+ if reg_name = "x3" then OPTION_MAP (\ v . x3_ref.write_to v s) (x3_ref.of_regval v) else
+ if reg_name = "x2" then OPTION_MAP (\ v . x2_ref.write_to v s) (x2_ref.of_regval v) else
+ if reg_name = "x1" then OPTION_MAP (\ v . x1_ref.write_to v s) (x1_ref.of_regval v) else
+ if reg_name = "Xs" then OPTION_MAP (\ v . Xs_ref.write_to v s) (Xs_ref.of_regval v) else
+ if reg_name = "instbits" then OPTION_MAP (\ v . instbits_ref.write_to v s) (instbits_ref.of_regval v) else
+ if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
+ if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else
+ NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``);
+val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``);
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/build b/prover_snapshots/hol4/build
new file mode 100755
index 0000000..f4ee71d
--- /dev/null
+++ b/prover_snapshots/hol4/build
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+for d in lib/lem lib/sail RV32 RV64; do
+ (cd $d; Holmake)
+done
diff --git a/prover_snapshots/hol4/clean b/prover_snapshots/hol4/clean
new file mode 100755
index 0000000..9c0778f
--- /dev/null
+++ b/prover_snapshots/hol4/clean
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+for d in lib/lem lib/sail RV32 RV64; do
+ (cd $d; Holmake cleanAll)
+done
diff --git a/prover_snapshots/hol4/lib/lem/Holmakefile b/prover_snapshots/hol4/lib/lem/Holmakefile
new file mode 100644
index 0000000..0d07567
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/Holmakefile
@@ -0,0 +1,14 @@
+ifdef POLY
+HOLHEAP_NAME = lemheap
+EXTRA_CLEANS = $(HOLHEAP_NAME) $(HOLHEAP_NAME).o
+
+BARE_DEPS = lemLib lemTheory lem_pervasivesTheory lem_pervasives_extraTheory lem_stringTheory lem_wordTheory
+DEPS = $(patsubst %,%.uo,$(BARE_DEPS))
+
+.PHONY: all
+all: $(HOLHEAP_NAME)
+
+$(HOLHEAP_NAME): $(DEPS)
+ rm -f $(HOLHEAP_NAME)
+ $(protect $(HOLDIR)/bin/buildheap) -o $@ $(BARE_DEPS)
+endif
diff --git a/prover_snapshots/hol4/lib/lem/lemLib.sml b/prover_snapshots/hol4/lib/lem/lemLib.sml
new file mode 100644
index 0000000..93d06dc
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lemLib.sml
@@ -0,0 +1,105 @@
+(*========================================================================*)
+(* Lem *)
+(* *)
+(* Dominic Mulligan, University of Cambridge *)
+(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *)
+(* Gabriel Kerneis, University of Cambridge *)
+(* Kathy Gray, University of Cambridge *)
+(* Peter Boehm, University of Cambridge (while working on Lem) *)
+(* Peter Sewell, University of Cambridge *)
+(* Scott Owens, University of Kent *)
+(* Thomas Tuerk, University of Cambridge *)
+(* *)
+(* The Lem sources are copyright 2010-2013 *)
+(* by the UK authors above and Institut National de Recherche en *)
+(* Informatique et en Automatique (INRIA). *)
+(* *)
+(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *)
+(* are distributed under the license below. The former are distributed *)
+(* under the LGPLv2, as in the LICENSE file. *)
+(* *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in the *)
+(* documentation and/or other materials provided with the distribution. *)
+(* 3. The names of the authors may not be used to endorse or promote *)
+(* products derived from this software without specific prior written *)
+(* permission. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *)
+(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *)
+(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *)
+(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *)
+(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *)
+(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *)
+(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *)
+(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *)
+(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *)
+(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *)
+(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *)
+(*========================================================================*)
+
+
+structure lemLib =
+struct
+
+open HolKernel Parse boolLib bossLib;
+open lemTheory intReduce wordsLib;
+
+val run_interactive = ref false
+val lem_conv_eval = computeLib.EVAL_CONV
+val lem_conv_simp = SIMP_CONV (srw_ss()++permLib.PERM_ss) []
+
+
+val lem_convs = [lem_conv_eval, lem_conv_simp];
+
+
+datatype test_result =
+ Success
+ | Fail
+ | Unknown of term
+
+
+fun lem_run_single_test (t:term) conv =
+case total conv t of
+ NONE => NONE
+ | SOME thm =>
+ if (can EQT_ELIM thm) then SOME Success else
+ if (can EQF_ELIM thm) then SOME Fail else
+ NONE
+;
+
+fun lem_run_test t =
+ case Lib.get_first (lem_run_single_test t) lem_convs of
+ NONE => Unknown (rhs (concl (EVAL t)))
+ | SOME r => r
+
+
+fun lem_assertion s t =
+let
+ open PPBackEnd Parse;
+ fun terminal_print sty s = (if !run_interactive then print_with_style sty s else
+ Lib.with_flag (Parse.current_backend, PPBackEnd.vt100_terminal) (print_with_style sty) s);
+ val _ = print "Testing ";
+ val _ = terminal_print [FG LightBlue] s;
+ val _ = print ": ``";
+ val _ = print_term t;
+ val _ = print ("`` ");
+ val result = lem_run_test t;
+ val _ = case result of
+ Success => terminal_print [FG Green] "OK\n"
+ | Fail => (terminal_print [FG OrangeRed] "FAILED\n";
+ if (not (!run_interactive)) then Process.exit Process.failure else ())
+ | Unknown t => (terminal_print [FG Yellow] "evaluation failed\n")
+(* print_term t;
+ print "\n\n"*)
+in
+ ()
+end;
+
+end
diff --git a/prover_snapshots/hol4/lib/lem/lemScript.sml b/prover_snapshots/hol4/lib/lem/lemScript.sml
new file mode 100644
index 0000000..94a8682
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lemScript.sml
@@ -0,0 +1,284 @@
+(*========================================================================*)
+(* Lem *)
+(* *)
+(* Dominic Mulligan, University of Cambridge *)
+(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *)
+(* Gabriel Kerneis, University of Cambridge *)
+(* Kathy Gray, University of Cambridge *)
+(* Peter Boehm, University of Cambridge (while working on Lem) *)
+(* Peter Sewell, University of Cambridge *)
+(* Scott Owens, University of Kent *)
+(* Thomas Tuerk, University of Cambridge *)
+(* *)
+(* The Lem sources are copyright 2010-2013 *)
+(* by the UK authors above and Institut National de Recherche en *)
+(* Informatique et en Automatique (INRIA). *)
+(* *)
+(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *)
+(* are distributed under the license below. The former are distributed *)
+(* under the LGPLv2, as in the LICENSE file. *)
+(* *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in the *)
+(* documentation and/or other materials provided with the distribution. *)
+(* 3. The names of the authors may not be used to endorse or promote *)
+(* products derived from this software without specific prior written *)
+(* permission. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *)
+(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *)
+(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *)
+(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *)
+(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *)
+(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *)
+(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *)
+(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *)
+(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *)
+(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *)
+(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *)
+(*========================================================================*)
+
+open finite_mapTheory finite_mapLib
+open HolKernel Parse boolLib bossLib;
+open pred_setSimps pred_setTheory
+open finite_mapTheory
+open set_relationTheory
+open integerTheory intReduce quantHeuristicsLib;
+open wordsTheory
+
+val _ = numLib.prefer_num();
+
+(* From BasicProvers, for compatibility with older versions of HOL *)
+fun subgoal q = Q.SUBGOAL_THEN q STRIP_ASSUME_TAC
+
+val _ = new_theory "lem"
+
+val failwith_def = Define `failwith (s:'a) = (ARB:'b)`;
+
+val set_CASE_def = zDefine `
+ set_CASE s c_emp c_sing c_else =
+ (if s = {} then c_emp else (
+ if (FINITE s /\ (CARD s = 1)) then c_sing (CHOICE s) else
+ c_else))`
+
+val set_CASE_emp = prove (
+``!c_emp c_sing c_else. set_CASE {} c_emp c_sing c_else = c_emp``,
+ SIMP_TAC std_ss [set_CASE_def])
+
+
+
+val set_CASE_sing = prove (
+``!x c_emp c_sing c_else. set_CASE {x} c_emp c_sing c_else = c_sing x``,
+ SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def])
+
+
+val set_CASE_infinite = prove (``~(FINITE s) ==> (set_CASE s c_emp c_sing c_else = c_else)``,
+REPEAT STRIP_TAC THEN
+`~ (s = {})` by METIS_TAC [FINITE_EMPTY] THEN
+ASM_SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def])
+
+val set_CASE_else_two_elems = store_thm ("set_CASE_else_two_elems",
+``(x1 IN s /\ x2 IN s /\ ~(x1 = x2)) ==>
+ (set_CASE s c_emp c_sing c_else = c_else)``,
+
+REPEAT STRIP_TAC THEN
+Tactical.REVERSE (Cases_on `FINITE s`) THEN1 (
+ ASM_SIMP_TAC std_ss [set_CASE_infinite]
+) THEN
+
+`~(s = {})` by (PROVE_TAC [MEMBER_NOT_EMPTY]) THEN
+
+subgoal `2 <= CARD s` THEN1 (
+ `CARD {x1; x2} = 2` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN
+ `{x1; x2} SUBSET s` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN
+ PROVE_TAC [CARD_SUBSET]
+) THEN
+
+ASM_SIMP_TAC arith_ss [set_CASE_def]);
+
+
+val set_CASE_else_1 = prove (``~(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = c_else)``,
+REPEAT STRIP_TAC THEN
+MATCH_MP_TAC set_CASE_else_two_elems THEN
+ASM_SIMP_TAC (std_ss++PRED_SET_ss) [])
+
+
+val set_CASE_else_2 = prove (``(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = set_CASE (x2 INSERT s) c_emp c_sing c_else)``,
+SIMP_TAC (std_ss++PRED_SET_ss) [])
+
+
+val set_CASE_REWRITES = save_thm ("set_CASE_REWRITES",
+ LIST_CONJ (map GEN_ALL [set_CASE_emp, set_CASE_sing, set_CASE_else_1, set_CASE_else_2, set_CASE_infinite]));
+
+val _ = export_rewrites ["set_CASE_REWRITES"]
+
+
+val set_CASE_compute = store_thm ("set_CASE_compute", ``
+ (!c_sing c_emp c_else. set_CASE {} c_emp c_sing c_else = c_emp) /\
+ (!x c_sing c_emp c_else.
+ set_CASE {x} c_emp c_sing c_else = c_sing x) /\
+ (!x2 x1 s c_sing c_emp c_else.
+ x1 <> x2 ==>
+ (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else =
+ c_else)) /\
+ (!x2 x1 s c_sing c_emp c_else.
+ (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else =
+ if (x1 = x2) then set_CASE (x2 INSERT s) c_emp c_sing c_else else c_else))``,
+METIS_TAC[set_CASE_REWRITES]);
+
+
+val SET_FILTER_def = zDefine `
+ (SET_FILTER P s = ({e | e | (e IN s) /\ P e}))`;
+
+val SET_FILTER_REWRITES = store_thm ("SET_FILTER_REWRITES",``
+ (!P. (SET_FILTER P {} = {})) /\
+ (!P x s. P x ==> (SET_FILTER P (x INSERT s) = x INSERT (SET_FILTER P s))) /\
+ (!P x s. (~(P x) ==> (SET_FILTER P (x INSERT s) = SET_FILTER P s)))``,
+
+SIMP_TAC (std_ss++PRED_SET_ss) [SET_FILTER_def, EXTENSION] THEN
+METIS_TAC[])
+
+val _ = export_rewrites ["SET_FILTER_REWRITES"]
+
+
+val SET_FILTER_compute = store_thm ("SET_FILTER_compute",``
+ (!P. (SET_FILTER P {} = {})) /\
+ (!P x s. (SET_FILTER P (x INSERT s) = if P x then
+ x INSERT (SET_FILTER P s) else (SET_FILTER P s)))``,
+METIS_TAC [SET_FILTER_REWRITES])
+
+
+val _ = computeLib.add_persistent_funs ["set_CASE_compute", "SET_FILTER_compute"]
+
+
+val SET_SIGMA_def = zDefine
+ `SET_SIGMA P Q = { (x, y) | x IN P /\ y IN Q x }`;
+
+val SET_SIGMA_EMPTY = store_thm(
+ "SET_SIGMA_EMPTY",
+ ``!Q. SET_SIGMA {} Q = {}``,
+ SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION]);
+val _ = export_rewrites ["SET_SIGMA_EMPTY"]
+val _ = computeLib.add_persistent_funs ["SET_SIGMA_EMPTY"]
+
+val SET_SIGMA_INSERT_LEFT = store_thm(
+ "SET_SIGMA_INSERT_LEFT",
+ ``!P Q x. SET_SIGMA (x INSERT P) Q =
+ (IMAGE (\y. (x, y)) (Q x)) UNION (SET_SIGMA P Q)``,
+ SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION] THEN
+ METIS_TAC[])
+val _ = export_rewrites ["SET_SIGMA_INSERT_LEFT"]
+val _ = computeLib.add_persistent_funs ["SET_SIGMA_INSERT_LEFT"]
+
+
+val _ = computeLib.add_persistent_funs ["list.LIST_TO_SET"]
+
+
+val FMAP_TO_SET_def = zDefine
+ `FMAP_TO_SET m = IMAGE (\k. (k, FAPPLY m k)) (FDOM m)`;
+
+val FMAP_TO_SET_FEMPTY = store_thm ("FMAP_TO_SET_FEMPTY",
+ ``FMAP_TO_SET FEMPTY = {}``,
+SIMP_TAC std_ss [FMAP_TO_SET_def, FDOM_FEMPTY, IMAGE_EMPTY]);
+val _ = export_rewrites ["FMAP_TO_SET_FEMPTY"]
+val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FEMPTY"]
+
+val FMAP_TO_SET_FUPDATE = store_thm ("FMAP_TO_SET_FUPDATE",
+ ``FMAP_TO_SET (FUPDATE m (k, v)) = (k, v) INSERT (FMAP_TO_SET (m \\ k))``,
+SIMP_TAC (std_ss ++ PRED_SET_ss) [FMAP_TO_SET_def, FDOM_FUPDATE, FAPPLY_FUPDATE_THM, EXTENSION,
+ FDOM_DOMSUB, DOMSUB_FAPPLY_THM] THEN
+METIS_TAC[]);
+val _ = export_rewrites ["FMAP_TO_SET_FUPDATE"]
+val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FUPDATE"]
+
+
+val IN_FMAP_TO_SET = store_thm ("IN_FMAP_TO_SET",
+ ``((k, v) IN FMAP_TO_SET m) = (FLOOKUP m k = SOME v)``,
+SIMP_TAC (std_ss++PRED_SET_ss) [FMAP_TO_SET_def, FLOOKUP_DEF] THEN
+METIS_TAC[optionTheory.option_CLAUSES])
+
+val FUPDATE_NEQ_FEMPTY = store_thm ("FUPDATE_NEQ_FEMPTY", ``(FUPDATE m (k, v) = FEMPTY) = F``,
+ SIMP_TAC (std_ss++PRED_SET_ss) [fmap_EXT, FDOM_FUPDATE, FDOM_FEMPTY])
+val _ = export_rewrites ["FUPDATE_NEQ_FEMPTY"]
+val _ = computeLib.add_persistent_funs ["FUPDATE_NEQ_FEMPTY"]
+
+val FUPDATE_EQ_FUPDATE = store_thm ("FUPDATE_EQ_FUPDATE",
+ ``(FUPDATE m (k, v) = FUPDATE m' (k', v')) =
+ (k IN FDOM (FUPDATE m' (k', v')) /\
+ (FUPDATE m' (k', v') ' k = v) /\
+ (m \\ k = (FUPDATE m' (k', v') \\ k))) ``,
+
+ EQ_TAC THEN STRIP_TAC THEN1 (
+ POP_ASSUM (ASSUME_TAC o GSYM) THEN
+ ASM_REWRITE_TAC [] THEN
+ SIMP_TAC std_ss [FDOM_FUPDATE, IN_INSERT, FAPPLY_FUPDATE, DOMSUB_FUPDATE]
+ ) THEN
+ FULL_SIMP_TAC std_ss [fmap_EXT, EXTENSION, FDOM_DOMSUB, IN_DELETE, FDOM_FUPDATE, IN_INSERT,
+ DOMSUB_FAPPLY_THM, FAPPLY_FUPDATE_THM] THEN
+ METIS_TAC[]
+)
+
+val _ = export_rewrites ["FUPDATE_EQ_FUPDATE"]
+val _ = computeLib.add_persistent_funs ["FUPDATE_EQ_FUPDATE"]
+
+
+val FEVERY_FUPDATE_DOMSUB = store_thm ("FEVERY_FUPDATE_DOMSUB",
+ ``(FEVERY P (FUPDATE m (k, v))) = (P (k, v) /\ FEVERY P (m \\ k))``,
+SIMP_TAC std_ss [FEVERY_FUPDATE, fmap_domsub]);
+
+val _ = computeLib.add_persistent_funs ["finite_map.FRANGE_FEMPTY", "finite_map.FRANGE_FUPDATE_DOMSUB",
+ "finite_map.FEVERY_FEMPTY", "FEVERY_FUPDATE_DOMSUB"]
+
+val _ = computeLib.add_persistent_funs ["finite_map.o_f_FUPDATE", "finite_map.o_f_FEMPTY",
+ "finite_map.FCARD_FEMPTY", "finite_map.FCARD_FUPDATE"]
+
+
+
+
+
+val rcomp_empty_1 = store_thm ("rcomp_empty_1",
+ ``({} OO r) = {}``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION])
+
+val rcomp_empty_2 = store_thm ("rcomp_empty_2",
+ ``(r OO {}) = {}``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION])
+
+val rcomp_insert_compute = store_thm ("rcomp_insert_compute",
+ ``(r1 OO ((x, y) INSERT r2)) = ((r1 OO r2) UNION (IMAGE (\ xy'. (FST xy', y)) (SET_FILTER (\ xy'. SND xy' = x) r1)))``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rcomp_def, EXTENSION, SET_FILTER_def] THEN
+METIS_TAC[])
+
+val _ = computeLib.add_persistent_funs ["rcomp_insert_compute", "rcomp_empty_1", "rcomp_empty_2"]
+
+
+val rrestrict_eval = store_thm ("rrestrict_eval",
+ ``rrestrict r s = SET_FILTER (\ (x, y). x IN s /\ y IN s) r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rrestrict_def, EXTENSION, SET_FILTER_def])
+
+val domain_eval = store_thm ("domain_eval",
+ ``domain r = IMAGE FST r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [domain_def, EXTENSION])
+
+val range_eval = store_thm ("range_eval",
+ ``range r = IMAGE SND r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [range_def, EXTENSION])
+
+val _ = computeLib.add_persistent_funs ["rrestrict_eval", "domain_eval", "range_eval"]
+
+val w2int_def = Define `w2int (w : 'a word) =
+ let i1 = (w2n w) in
+ let i2 = (INT_MAX (:'a)) in
+ if i1 > i2 then (int_of_num i1 - (int_of_num (UINT_MAX (:'a)))) - 1 else int_of_num i1`
+
+val w2ui_def = Define `w2ui (w : 'a word) = int_of_num (w2n w)`
+
+val _ = Define `MAP_TO_LIST m = SET_TO_LIST (\(x, y). FAPPLY m x = y)`
+
+val _ = export_theory()
diff --git a/prover_snapshots/hol4/lib/lem/lem_assert_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_assert_extraScript.sml
new file mode 100644
index 0000000..79d5eda
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_assert_extraScript.sml
@@ -0,0 +1,46 @@
+(*Generated by Lem from assert_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open stringTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_assert_extra"
+
+
+(*open import {ocaml} `Xstring`*)
+(*open import {hol} `stringTheory` `lemTheory`*)
+(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ------------------------------------ *)
+(* failing with a proper error message *)
+(* ------------------------------------ *)
+
+(*val failwith: forall 'a. string -> 'a*)
+
+(* ------------------------------------ *)
+(* failing without an error message *)
+(* ------------------------------------ *)
+
+(*val fail : forall 'a. 'a*)
+val _ = Define `
+ ((fail:'a)= (failwith "fail"))`;
+
+
+(* ------------------------------------- *)
+(* assertions *)
+(* ------------------------------------- *)
+
+(*val ensure : bool -> string -> unit*)
+val _ = Define `
+ ((ensure:bool -> string -> unit) test msg=
+ (if test then
+ ()
+ else
+ failwith msg))`;
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_basic_classesScript.sml b/prover_snapshots/hol4/lib/lem/lem_basic_classesScript.sml
new file mode 100644
index 0000000..4788ee1
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_basic_classesScript.sml
@@ -0,0 +1,503 @@
+(*Generated by Lem from basic_classes.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory ternaryComparisonsTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_basic_classes"
+
+(******************************************************************************)
+(* Basic Type Classes *)
+(******************************************************************************)
+
+(*open import Bool*)
+
+(*open import {coq} `Coq.Strings.Ascii`*)
+(*open import {hol} `ternaryComparisonsTheory`*)
+
+(* ========================================================================== *)
+(* Equality *)
+(* ========================================================================== *)
+
+(* Lem`s default equality (=) is defined by the following type-class Eq.
+ This typeclass should define equality on an abstract datatype 'a. It should
+ always coincide with the default equality of Coq, HOL and Isabelle.
+ For OCaml, it might be different, since abstract datatypes like sets
+ might have fancy equalities. *)
+
+(*class ( Eq 'a )
+ val = [isEqual] : 'a -> 'a -> bool
+ val <> [isInequal] : 'a -> 'a -> bool
+end*)
+
+
+(* (=) should for all instances be an equivalence relation
+ The isEquivalence predicate of relations could be used here.
+ However, this would lead to a cyclic dependency. *)
+
+(* TODO: add later, once lemmata can be assigned to classes
+lemma eq_equiv: ((forall x. (x = x)) &&
+ (forall x y. (x = y) <-> (y = x)) &&
+ (forall x y z. ((x = y) && (y = z)) --> (x = z)))
+*)
+
+(* Structural equality *)
+
+(* Sometimes, it is also handy to be able to use structural equality.
+ This equality is mapped to the build-in equality of backends. This equality
+ differs significantly for each backend. For example, OCaml can`t check equality
+ of function types, whereas HOL can. When using structural equality, one should
+ know what one is doing. The only guarentee is that is behaves like
+ the native backend equality.
+
+ A lengthy name for structural equality is used to discourage its direct use.
+ It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions
+ for equality *)
+(*val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool*)
+
+(*val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool*)
+(*let unsafe_structural_inequality x y= not (unsafe_structural_equality x y)*)
+
+
+(* ========================================================================== *)
+(* Orderings *)
+(* ========================================================================== *)
+
+(* The type-class Ord represents total orders (also called linear orders) *)
+(*type ordering = LT | EQ | GT*)
+
+val _ = Define `
+ ((orderingIsLess:ordering -> bool) LESS= T)
+/\ ((orderingIsLess:ordering -> bool) _= F)`;
+
+val _ = Define `
+ ((orderingIsGreater:ordering -> bool) GREATER= T)
+/\ ((orderingIsGreater:ordering -> bool) _= F)`;
+
+val _ = Define `
+ ((orderingIsEqual:ordering -> bool) EQUAL= T)
+/\ ((orderingIsEqual:ordering -> bool) _= F)`;
+
+
+val _ = Define `
+ ((ordering_cases:ordering -> 'a -> 'a -> 'a -> 'a) r lt eq gt=
+ (if orderingIsLess r then lt else
+ if orderingIsEqual r then eq else gt))`;
+
+
+
+(*val orderingEqual : ordering -> ordering -> bool*)
+
+val _ = Hol_datatype `
+(* 'a *) Ord_class= <|
+ compare_method : 'a -> 'a -> ordering;
+ isLess_method : 'a -> 'a -> bool;
+ isLessEqual_method : 'a -> 'a -> bool;
+ isGreater_method : 'a -> 'a -> bool;
+ isGreaterEqual_method : 'a -> 'a -> bool
+|>`;
+
+
+
+(* Ocaml provides default, polymorphic compare functions. Let's use them
+ as the default. However, because used perhaps in a typeclass they must be
+ defined for all targets. So, explicitly declare them as undefined for
+ all other targets. If explictly declare undefined, the type-checker won't complain and
+ an error will only be raised when trying to actually output the function for a certain
+ target. *)
+(*val defaultCompare : forall 'a. 'a -> 'a -> ordering*)
+(*val defaultLess : forall 'a. 'a -> 'a -> bool*)
+(*val defaultLessEq : forall 'a. 'a -> 'a -> bool*)
+(*val defaultGreater : forall 'a. 'a -> 'a -> bool*)
+(*val defaultGreaterEq : forall 'a. 'a -> 'a -> bool*)
+
+
+val _ = Define `
+ ((genericCompare:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a -> 'a -> ordering) (less: 'a -> 'a -> bool) (equal: 'a -> 'a -> bool) (x : 'a) (y : 'a)=
+ (if less x y then
+ LESS
+ else if equal x y then
+ EQUAL
+ else
+ GREATER))`;
+
+
+
+(*
+(* compare should really be a total order *)
+lemma ord_OK_1: (
+ (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) &&
+ (forall x y. (compare x y = LT) <-> (compare y x = GT)))
+
+lemma ord_OK_2: (
+ (forall x y z. (x <= y) && (y <= z) --> (x <= z)) &&
+ (forall x y. (x <= y) || (y <= x))
+)
+*)
+
+(* let's derive a compare function from the Ord type-class *)
+(*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*)
+val _ = Define `
+ ((ordCompare:'a Ord_class -> 'a -> 'a -> ordering)dict_Basic_classes_Ord_a x y=
+ (if ( dict_Basic_classes_Ord_a.isLess_method x y) then LESS else
+ if (x = y) then EQUAL else GREATER))`;
+
+
+val _ = Hol_datatype `
+(* 'a *) OrdMaxMin_class= <|
+ max_method : 'a -> 'a -> 'a;
+ min_method : 'a -> 'a -> 'a
+|>`;
+
+
+(*val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((minByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y= (if (le x y) then x else y))`;
+
+
+(*val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((maxByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y= (if (le y x) then x else y))`;
+
+
+(*val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a*)
+
+(*val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_var_dict:'a Ord_class -> 'a OrdMaxMin_class)dict_Basic_classes_Ord_a= (<|
+
+ max_method := (maxByLessEqual
+ dict_Basic_classes_Ord_a.isLessEqual_method);
+
+ min_method := (minByLessEqual
+ dict_Basic_classes_Ord_a.isLessEqual_method)|>))`;
+
+
+
+(* ========================================================================== *)
+(* SetTypes *)
+(* ========================================================================== *)
+
+(* Set implementations use often an order on the elements. This allows the OCaml implementation
+ to use trees for implementing them. At least, one needs to be able to check equality on sets.
+ One could use the Ord type-class for sets. However, defining a special typeclass is cleaner
+ and allows more flexibility. One can make e.g. sure, that this type-class is ignored for
+ backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate
+ the functions "<", "<=" ... *)
+
+(*class ( SetType 'a )
+ val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering
+end*)
+
+val _ = Define `
+ ((boolCompare:bool -> bool -> ordering) T T= EQUAL)
+/\ ((boolCompare:bool -> bool -> ordering) T F= GREATER)
+/\ ((boolCompare:bool -> bool -> ordering) F T= LESS)
+/\ ((boolCompare:bool -> bool -> ordering) F F= EQUAL)`;
+
+
+(* strings *)
+
+(*val charEqual : char -> char -> bool*)
+
+(*val stringEquality : string -> string -> bool*)
+
+(* pairs *)
+
+(*val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool*)
+(*let pairEqual (a1, b1) (a2, b2)= (a1 = a2) && (b1 = b2)*)
+
+(*val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool*)
+
+(*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*)
+val _ = Define `
+ ((pairCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) -> 'a#'b -> 'a#'b -> ordering) cmpa cmpb (a1, b1) (a2, b2)=
+ ((case cmpa a1 a2 of
+ LESS => LESS
+ | GREATER => GREATER
+ | EQUAL => cmpb b1 b2
+ )))`;
+
+
+val _ = Define `
+ ((pairLess:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)= ((
+ dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLess_method x2 y2))))`;
+
+val _ = Define `
+ ((pairLessEq:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)= ((
+ dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLessEqual_method x2 y2))))`;
+
+
+val _ = Define `
+ ((pairGreater:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12= (pairLess
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`;
+
+val _ = Define `
+ ((pairGreaterEq:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12= (pairLessEq
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup2_dict:'a Ord_class -> 'b Ord_class ->('a#'b)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b= (<|
+
+ compare_method := (pairCompare
+ dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method);
+
+ isLess_method :=
+ (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+ isLessEqual_method :=
+ (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+ isGreater_method :=
+ (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b);
+
+ isGreaterEqual_method :=
+ (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b)|>))`;
+
+
+
+(* triples *)
+
+(*val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool*)
+(*let tripleEqual (x1, x2, x3) (y1, y2, y3)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))*)
+
+(*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*)
+val _ = Define `
+ ((tripleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) -> 'a#'b#'c -> 'a#'b#'c -> ordering) cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2)=
+ (pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2))))`;
+
+
+val _ = Define `
+ ((tripleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)= (pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`;
+
+val _ = Define `
+ ((tripleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)= (pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`;
+
+
+val _ = Define `
+ ((tripleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123= (tripleLess
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`;
+
+val _ = Define `
+ ((tripleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123= (tripleLessEq
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup3_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class ->('a#'b#'c)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c= (<|
+
+ compare_method := (tripleCompare
+ dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method);
+
+ isLess_method :=
+ (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c);
+
+ isLessEqual_method :=
+ (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c);
+
+ isGreater_method :=
+ (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a);
+
+ isGreaterEqual_method :=
+ (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a)|>))`;
+
+
+(* quadruples *)
+
+(*val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool*)
+(*let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))*)
+
+(*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*)
+val _ = Define `
+ ((quadrupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> ordering) cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2)=
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2)))))`;
+
+
+val _ = Define `
+ ((quadrupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)= (pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`;
+
+val _ = Define `
+ ((quadrupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)= (pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`;
+
+
+val _ = Define `
+ ((quadrupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234= (quadrupleLess
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`;
+
+val _ = Define `
+ ((quadrupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234= (quadrupleLessEq
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup4_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class ->('a#'b#'c#'d)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d= (<|
+
+ compare_method := (quadrupleCompare
+ dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method);
+
+ isLess_method :=
+ (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d);
+
+ isLessEqual_method :=
+ (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d);
+
+ isGreater_method :=
+ (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+ isGreaterEqual_method :=
+ (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`;
+
+
+(* quintuples *)
+
+(*val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool*)
+(*let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))*)
+
+(*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*)
+val _ = Define `
+ ((quintupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> ordering) cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2)=
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2))))))`;
+
+
+val _ = Define `
+ ((quintupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= (pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`;
+
+val _ = Define `
+ ((quintupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= (pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`;
+
+
+val _ = Define `
+ ((quintupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345= (quintupleLess
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`;
+
+val _ = Define `
+ ((quintupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345= (quintupleLessEq
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup5_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class ->('a#'b#'c#'d#'e)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e= (<|
+
+ compare_method := (quintupleCompare
+ dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method dict_Basic_classes_Ord_e.compare_method);
+
+ isLess_method :=
+ (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e);
+
+ isLessEqual_method :=
+ (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e);
+
+ isGreater_method :=
+ (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a);
+
+ isGreaterEqual_method :=
+ (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a)|>))`;
+
+
+(* sextuples *)
+
+(*val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool*)
+(*let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))*)
+
+(*val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) ->
+ ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*)
+val _ = Define `
+ ((sextupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) ->('f -> 'f -> ordering) -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> ordering) cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2)=
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2)))))))`;
+
+
+val _ = Define `
+ ((sextupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= (pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`;
+
+val _ = Define `
+ ((sextupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= (pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`;
+
+
+val _ = Define `
+ ((sextupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456= (sextupleLess
+ dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`;
+
+val _ = Define `
+ ((sextupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456= (sextupleLessEq
+ dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup6_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class ->('a#'b#'c#'d#'e#'f)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f= (<|
+
+ compare_method := (sextupleCompare
+ dict_Basic_classes_Ord_a.compare_method dict_Basic_classes_Ord_b.compare_method dict_Basic_classes_Ord_c.compare_method dict_Basic_classes_Ord_d.compare_method dict_Basic_classes_Ord_e.compare_method dict_Basic_classes_Ord_f.compare_method);
+
+ isLess_method :=
+ (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f);
+
+ isLessEqual_method :=
+ (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f);
+
+ isGreater_method :=
+ (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+ isGreaterEqual_method :=
+ (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_boolScript.sml b/prover_snapshots/hol4/lib/lem/lem_boolScript.sml
new file mode 100644
index 0000000..5e6aa09
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_boolScript.sml
@@ -0,0 +1,75 @@
+(*Generated by Lem from bool.lem.*)
+open HolKernel Parse boolLib bossLib;
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_bool"
+
+
+
+(* The type bool is hard-coded, so are true and false *)
+
+(* ----------------------- *)
+(* not *)
+(* ----------------------- *)
+
+(*val not : bool -> bool*)
+(*let not b= match b with
+ | true -> false
+ | false -> true
+end*)
+
+(* ----------------------- *)
+(* and *)
+(* ----------------------- *)
+
+(*val && [and] : bool -> bool -> bool*)
+(*let && b1 b2= match (b1, b2) with
+ | (true, true) -> true
+ | _ -> false
+end*)
+
+
+(* ----------------------- *)
+(* or *)
+(* ----------------------- *)
+
+(*val || [or] : bool -> bool -> bool*)
+(*let || b1 b2= match (b1, b2) with
+ | (false, false) -> false
+ | _ -> true
+end*)
+
+
+(* ----------------------- *)
+(* implication *)
+(* ----------------------- *)
+
+(*val --> [imp] : bool -> bool -> bool*)
+(*let --> b1 b2= match (b1, b2) with
+ | (true, false) -> false
+ | _ -> true
+end*)
+
+
+(* ----------------------- *)
+(* equivalence *)
+(* ----------------------- *)
+
+(*val <-> [equiv] : bool -> bool -> bool*)
+(*let <-> b1 b2= match (b1, b2) with
+ | (true, true) -> true
+ | (false, false) -> true
+ | _ -> false
+end*)
+
+
+(* ----------------------- *)
+(* xor *)
+(* ----------------------- *)
+
+(*val xor : bool -> bool -> bool*)
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_eitherScript.sml b/prover_snapshots/hol4/lib/lem/lem_eitherScript.sml
new file mode 100644
index 0000000..cad5388
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_eitherScript.sml
@@ -0,0 +1,83 @@
+(*Generated by Lem from either.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_listTheory lem_tupleTheory sumTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_either"
+
+
+
+(*open import Bool Basic_classes List Tuple*)
+(*open import {hol} `sumTheory`*)
+(*open import {ocaml} `Either`*)
+
+(*type either 'a 'b
+ = Left of 'a
+ | Right of 'b*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Equality. *)
+(* -------------------------------------------------------------------------- *)
+
+(*val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool*)
+(*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*)
+
+val _ = Define `
+ ((eitherEqualBy:('a -> 'a -> bool) ->('b -> 'b -> bool) ->('a,'b)sum ->('a,'b)sum -> bool) eql eqr (left: ('a, 'b) sum) (right: ('a, 'b) sum)=
+ ((case (left, right) of
+ (INL l, INL l') => eql l l'
+ | (INR r, INR r') => eqr r r'
+ | _ => F
+ )))`;
+
+(*let eitherEqual= eitherEqualBy (=) (=)*)
+
+val _ = Define `
+ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INL x') (INL y')= (cmpa x' y'))
+/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INR x') (INR y')= (cmpb x' y'))
+/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INL _) (INR _)= LESS)
+/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INR _) (INL _)= GREATER)`;
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* Utility functions. *)
+(* -------------------------------------------------------------------------- *)
+
+(*val isLeft : forall 'a 'b. either 'a 'b -> bool*)
+
+(*val isRight : forall 'a 'b. either 'a 'b -> bool*)
+
+
+(*val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c*)
+(*let either fa fb x= match x with
+ | Left a -> fa a
+ | Right b -> fb b
+end*)
+
+
+(*val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)*)
+ val _ = Define `
+ ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) ([])= ([], []))
+/\ ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) (x :: xs)= ((
+ let (ll, rl) = (SUM_PARTITION xs) in
+ (case x of
+ INL l => ((l::ll), rl)
+ | INR r => (ll, (r::rl))
+ )
+ )))`;
+
+
+
+(*val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a*)
+
+
+(*val rights : forall 'a 'b. list (either 'a 'b) -> list 'b*)
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_functionScript.sml b/prover_snapshots/hol4/lib/lem/lem_functionScript.sml
new file mode 100644
index 0000000..2f6f52b
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_functionScript.sml
@@ -0,0 +1,72 @@
+(*Generated by Lem from function.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_function"
+
+(******************************************************************************)
+(* A library for common operations on functions *)
+(******************************************************************************)
+
+(*open import Bool Basic_classes*)
+
+(*open import {coq} `Program.Basics`*)
+
+(* ----------------------- *)
+(* identity function *)
+(* ----------------------- *)
+
+(*val id : forall 'a. 'a -> 'a*)
+(*let id x= x*)
+
+
+(* ----------------------- *)
+(* constant function *)
+(* ----------------------- *)
+
+(*val const : forall 'a 'b. 'a -> 'b -> 'a*)
+
+
+(* ----------------------- *)
+(* function composition *)
+(* ----------------------- *)
+
+(*val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)*)
+(*let comb f g= (fun x -> f (g x))*)
+
+
+(* ----------------------- *)
+(* function application *)
+(* ----------------------- *)
+
+(*val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)*)
+(*let $ f= (fun x -> f x)*)
+
+(*val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b*)
+(*let $> x f= f x*)
+
+(* ----------------------- *)
+(* flipping argument order *)
+(* ----------------------- *)
+
+(*val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)*)
+(*let flip f= (fun x y -> f y x)*)
+
+
+(* currying / uncurrying *)
+
+(*val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c*)
+val _ = Define `
+ ((curry:('a#'b -> 'c) -> 'a -> 'b -> 'c) f= (\ a b . f (a, b)))`;
+
+
+(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*)
+val _ = Define `
+ ((uncurry:('a -> 'b -> 'c) -> 'a#'b -> 'c) f (a,b)= (f a b))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_function_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_function_extraScript.sml
new file mode 100644
index 0000000..c77c977
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_function_extraScript.sml
@@ -0,0 +1,25 @@
+(*Generated by Lem from function_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_maybeTheory lem_boolTheory lem_basic_classesTheory lem_numTheory lem_functionTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_function_extra"
+
+
+
+(*open import Maybe Bool Basic_classes Num Function*)
+
+(*open import {hol} `lemTheory`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ----------------------- *)
+(* getting a unique value *)
+(* ----------------------- *)
+
+(*val THE : forall 'a. ('a -> bool) -> maybe 'a*)
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_listScript.sml b/prover_snapshots/hol4/lib/lem/lem_listScript.sml
new file mode 100644
index 0000000..1b8f25f
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_listScript.sml
@@ -0,0 +1,776 @@
+(*Generated by Lem from list.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_functionTheory lem_tupleTheory lem_numTheory lemTheory listTheory rich_listTheory sortingTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_list"
+
+
+
+(*open import Bool Maybe Basic_classes Function Tuple Num*)
+
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+(*open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`*)
+
+(* ========================================================================== *)
+(* Basic list functions *)
+(* ========================================================================== *)
+
+(* The type of lists as well as list literals like [], [1;2], ... are hardcoded.
+ Thus, we can directly dive into derived definitions. *)
+
+
+(* ----------------------- *)
+(* cons *)
+(* ----------------------- *)
+
+(*val :: : forall 'a. 'a -> list 'a -> list 'a*)
+
+
+(* ----------------------- *)
+(* Emptyness check *)
+(* ----------------------- *)
+
+(*val null : forall 'a. list 'a -> bool*)
+(*let null l= match l with [] -> true | _ -> false end*)
+
+(* ----------------------- *)
+(* Length *)
+(* ----------------------- *)
+
+(*val length : forall 'a. list 'a -> nat*)
+(*let rec length l=
+ match l with
+ | [] -> 0
+ | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1
+ end*)
+
+(* ----------------------- *)
+(* Equality *)
+(* ----------------------- *)
+
+(*val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+
+ val _ = Define `
+ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) ([])= T)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) (_::_)= F)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (_::_) ([])= F)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x::xs) (y :: ys)= (eq x y /\ listEqualBy eq xs ys))`;
+
+
+
+(* ----------------------- *)
+(* compare *)
+(* ----------------------- *)
+
+(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> ordering*)
+(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a -> ordering*)
+
+ val _ = Define `
+ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp ([]) ([])= EQUAL)
+/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp ([]) (_::_)= LESS)
+/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp (_::_) ([])= GREATER)
+/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp (x::xs) (y::ys)= ((
+ (case cmp x y of
+ LESS => LESS
+ | GREATER => GREATER
+ | EQUAL => lexicographic_compare cmp xs ys
+ )
+ )))`;
+
+
+(*val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool*)
+(*val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+ val _ = Define `
+ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])= F)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)= T)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])= F)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)= ((less x y) \/ ((less_eq x y) /\ (lexicographic_less less less_eq xs ys))))`;
+
+
+(*val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool*)
+(*val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+ val _ = Define `
+ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])= T)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)= T)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])= F)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)= (less x y \/ (less_eq x y /\ lexicographic_less_eq less less_eq xs ys)))`;
+
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_list_dict:'a Ord_class ->('a list)Ord_class)dict_Basic_classes_Ord_a= (<|
+
+ compare_method := (lexicographic_compare
+ dict_Basic_classes_Ord_a.compare_method);
+
+ isLess_method := (lexicographic_less
+ dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method);
+
+ isLessEqual_method := (lexicographic_less_eq
+ dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method);
+
+ isGreater_method := (\ x y. (lexicographic_less
+ dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method y x));
+
+ isGreaterEqual_method := (\ x y. (lexicographic_less_eq
+ dict_Basic_classes_Ord_a.isLess_method dict_Basic_classes_Ord_a.isLessEqual_method y x))|>))`;
+
+
+
+(* ----------------------- *)
+(* Append *)
+(* ----------------------- *)
+
+(*val ++ : forall 'a. list 'a -> list 'a -> list 'a*) (* originally append *)
+(*let rec ++ xs ys= match xs with
+ | [] -> ys
+ | x :: xs' -> x :: (xs' ++ ys)
+ end*)
+
+(* ----------------------- *)
+(* snoc *)
+(* ----------------------- *)
+
+(*val snoc : forall 'a. 'a -> list 'a -> list 'a*)
+(*let snoc e l= l ++ [e]*)
+
+
+(* ----------------------- *)
+(* Reverse *)
+(* ----------------------- *)
+
+(* First lets define the function [reverse_append], which is
+ closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1].
+ This can be implemented more efficienctly than appending and is
+ used to implement reverse. *)
+
+(*val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a*) (* originally named rev_append *)
+(*let rec reverseAppend l1 l2= match l1 with
+ | [] -> l2
+ | x :: xs -> reverseAppend xs (x :: l2)
+ end*)
+
+(* Reversing a list *)
+(*val reverse : forall 'a. list 'a -> list 'a*) (* originally named rev *)
+(*let reverse l= reverseAppend l []*)
+
+(* ----------------------- *)
+(* Map *)
+(* ----------------------- *)
+
+(*val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b*)
+ val map_tr_defn = Defn.Hol_multi_defns `
+ ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f ([])= (REVERSE rev_acc))
+/\ ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f (x :: xs)= (map_tr ((f x) :: rev_acc) f xs))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) map_tr_defn;
+
+(* taken from: https://blogs.janestreet.com/optimizing-list-map/ *)
+(*val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b*)
+ val count_map_defn = Defn.Hol_multi_defns `
+ ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f ([]) ctr= ([]))
+/\ ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f (hd :: tl) ctr= (f hd ::
+ (if ctr <( 5000 : num) then count_map f tl (ctr +( 1 : num))
+ else map_tr [] f tl)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) count_map_defn;
+
+(*val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*)
+(*let map f l= count_map f l 0*)
+
+(* ----------------------- *)
+(* Reverse Map *)
+(* ----------------------- *)
+
+(*val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*)
+
+
+(* ========================================================================== *)
+(* Folding *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* fold left *)
+(* ----------------------- *)
+
+(*val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a*) (* originally foldl *)
+
+(*let rec foldl f b l= match l with
+ | [] -> b
+ | x :: xs -> foldl f (f b x) xs
+end*)
+
+
+(* ----------------------- *)
+(* fold right *)
+(* ----------------------- *)
+
+(*val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b*) (* originally foldr with different argument order *)
+(*let rec foldr f b l= match l with
+ | [] -> b
+ | x :: xs -> f x (foldr f b xs)
+end*)
+
+
+(* ----------------------- *)
+(* concatenating lists *)
+(* ----------------------- *)
+
+(*val concat : forall 'a. list (list 'a) -> list 'a*) (* before also called "flatten" *)
+(*let concat= foldr (++) []*)
+
+
+(* -------------------------- *)
+(* concatenating with mapping *)
+(* -------------------------- *)
+
+(*val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b*)
+
+
+(* ------------------------- *)
+(* universal qualification *)
+(* ------------------------- *)
+
+(*val all : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally for_all *)
+(*let all P l= foldl (fun r e -> P e && r) true l*)
+
+
+
+(* ------------------------- *)
+(* existential qualification *)
+(* ------------------------- *)
+
+(*val any : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally exist *)
+(*let any P l= foldl (fun r e -> P e || r) false l*)
+
+
+(* ------------------------- *)
+(* dest_init *)
+(* ------------------------- *)
+
+(* get the initial part and the last element of the list in a safe way *)
+
+(*val dest_init : forall 'a. list 'a -> maybe (list 'a * 'a)*)
+
+ val _ = Define `
+ ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen ([])= (REVERSE rev_init, last_elem_seen))
+/\ ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen (x::xs)= (dest_init_aux (last_elem_seen::rev_init) x xs))`;
+
+
+val _ = Define `
+ ((dest_init:'a list ->('a list#'a)option) ([])= NONE)
+/\ ((dest_init:'a list ->('a list#'a)option) (x::xs)= (SOME (dest_init_aux [] x xs)))`;
+
+
+
+(* ========================================================================== *)
+(* Indexing lists *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* index / nth with maybe *)
+(* ------------------------- *)
+
+(*val index : forall 'a. list 'a -> nat -> maybe 'a*)
+
+ val _ = Define `
+ ((list_index:'a list -> num -> 'a option) ([]) n= NONE)
+/\ ((list_index:'a list -> num -> 'a option) (x :: xs) n= (if n =( 0 : num) then SOME x else list_index xs (n -( 1 : num))))`;
+
+
+(* ------------------------- *)
+(* findIndices *)
+(* ------------------------- *)
+
+(* [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P].
+ Counting starts with 0, the result list is sorted ascendingly *)
+(*val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat*)
+
+ val _ = Define `
+ ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P ([])= ([]))
+/\ ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P (x :: xs)= (if P x then i :: find_indices_aux (i +( 1 : num)) P xs else find_indices_aux (i +( 1 : num)) P xs))`;
+
+val _ = Define `
+ ((find_indices:('a -> bool) -> 'a list ->(num)list) P l= (find_indices_aux(( 0 : num)) P l))`;
+
+
+
+
+(* ------------------------- *)
+(* findIndex *)
+(* ------------------------- *)
+
+(* findIndex returns the first index of a list that satisfies a given predicate. *)
+(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> maybe nat*)
+val _ = Define `
+ ((find_index:('a -> bool) -> 'a list ->(num)option) P l= ((case find_indices P l of
+ [] => NONE
+ | x :: _ => SOME x
+)))`;
+
+
+(* ------------------------- *)
+(* elemIndices *)
+(* ------------------------- *)
+
+(*val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat*)
+
+(* ------------------------- *)
+(* elemIndex *)
+(* ------------------------- *)
+
+(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> maybe nat*)
+
+
+(* ========================================================================== *)
+(* Creating lists *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* genlist *)
+(* ------------------------- *)
+
+(* [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] *)
+(*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*)
+
+
+(*let rec genlist f n=
+ match n with
+ | 0 -> []
+ | n' + 1 -> snoc (f n') (genlist f n')
+ end*)
+
+
+(* ------------------------- *)
+(* replicate *)
+(* ------------------------- *)
+
+(*val replicate : forall 'a. nat -> 'a -> list 'a*)
+(*let rec replicate n x=
+ match n with
+ | 0 -> []
+ | n' + 1 -> x :: replicate n' x
+ end*)
+
+
+(* ========================================================================== *)
+(* Sublists *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* splitAt *)
+(* ------------------------- *)
+
+(* [splitAt n xs] returns a tuple (xs1, xs2), with "append xs1 xs2 = xs" and
+ "length xs1 = n". If there are not enough elements
+ in [xs], the original list and the empty one are returned. *)
+(*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*)
+ val splitAtAcc_defn = Hol_defn "splitAtAcc" `
+ ((splitAtAcc:'a list -> num -> 'a list -> 'a list#'a list) revAcc n l=
+ ((case l of
+ [] => (REVERSE revAcc, [])
+ | x::xs => if n <=( 0 : num) then (REVERSE revAcc, l) else splitAtAcc (x::revAcc) (n -( 1 : num)) xs
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn splitAtAcc_defn;
+
+(*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*)
+(*let rec splitAt n l=
+ splitAtAcc [] n l*)
+
+
+(* ------------------------- *)
+(* take *)
+(* ------------------------- *)
+
+(* take n xs returns the prefix of xs of length n, or xs itself if n > length xs *)
+(*val take : forall 'a. nat -> list 'a -> list 'a*)
+(*let take n l= fst (splitAt n l)*)
+
+(* ------------------------- *)
+(* drop *)
+(* ------------------------- *)
+
+(* [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. *)
+(*val drop : forall 'a. nat -> list 'a -> list 'a*)
+(*let drop n l= snd (splitAt n l)*)
+
+(* ------------------------------------ *)
+(* splitWhile, takeWhile, and dropWhile *)
+(* ------------------------------------ *)
+
+(*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*)
+ val _ = Define `
+ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p ([]) acc=
+ (REVERSE acc, []))
+/\ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p (x::xs) acc=
+ (if p x then
+ splitWhile_tr p xs (x::acc)
+ else
+ (REVERSE acc, (x::xs))))`;
+
+
+(*val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)*)
+val _ = Define `
+ ((splitWhile:('a -> bool) -> 'a list -> 'a list#'a list) p xs= (splitWhile_tr p xs []))`;
+
+
+(* [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. *)
+(*val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+val _ = Define `
+ ((takeWhile:('a -> bool) -> 'a list -> 'a list) p l= (FST (splitWhile p l)))`;
+
+
+(* [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. *)
+(*val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+val _ = Define `
+ ((dropWhile:('a -> bool) -> 'a list -> 'a list) p l= (SND (splitWhile p l)))`;
+
+
+(* ------------------------- *)
+(* isPrefixOf *)
+(* ------------------------- *)
+
+(*val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*let rec isPrefixOf l1 l2= match (l1, l2) with
+ | ([], _) -> true
+ | (_::_, []) -> false
+ | (x::xs, y::ys) -> (x = y) && isPrefixOf xs ys
+end*)
+
+(* ------------------------- *)
+(* update *)
+(* ------------------------- *)
+(*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*)
+(*let rec update l n e=
+ match l with
+ | [] -> []
+ | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e)
+end*)
+
+
+
+(* ========================================================================== *)
+(* Searching lists *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* Membership test *)
+(* ------------------------- *)
+
+(* The membership test, one of the basic list functions, is actually tricky for
+ Lem, because it is tricky, which equality to use. From Lem`s point of
+ perspective, we want to use the equality provided by the equality type - class.
+ This allows for example to check whether a set is in a list of sets.
+
+ However, in order to use the equality type class, elem essentially becomes
+ existential quantification over lists. For types, which implement semantic
+ equality (=) with syntactic equality, this is overly complicated. In
+ our theorem prover backend, we would end up with overly complicated, harder
+ to read definitions and some of the automation would be harder to apply.
+ Moreover, nearly all the old Lem generated code would change and require
+ (hopefully minor) adaptions of proofs.
+
+ For now, we ignore this problem and just demand, that all instances of
+ the equality type class do the right thing for the theorem prover backends.
+*)
+
+(*val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool*)
+(*val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool*)
+
+val _ = Define `
+ ((elemBy:('a -> 'a -> bool) -> 'a -> 'a list -> bool) eq e l= (EXISTS (eq e) l))`;
+
+(*let elem= elemBy (=)*)
+
+(* ------------------------- *)
+(* Find *)
+(* ------------------------- *)
+(*val find : forall 'a. ('a -> bool) -> list 'a -> maybe 'a*) (* previously not of maybe type *)
+ val _ = Define `
+ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P ([])= NONE)
+/\ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P (x :: xs)= (if P x then SOME x else list_find_opt P xs))`;
+
+
+
+(* ----------------------------- *)
+(* Lookup in an associative list *)
+(* ----------------------------- *)
+(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> maybe 'b*)
+(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> maybe 'b*)
+
+(* DPM: eta-expansion for Coq backend type-inference. *)
+val _ = Define `
+ ((lookupBy:('a -> 'a -> bool) -> 'a ->('a#'b)list -> 'b option) eq k m= (OPTION_MAP (\ x . SND x) (list_find_opt (\p .
+ (case (p ) of ( (k', _) ) => eq k k' )) m)))`;
+
+
+(* ------------------------- *)
+(* filter *)
+(* ------------------------- *)
+(*val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+(*let rec filter P l= match l with
+ | [] -> []
+ | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs
+ end*)
+
+
+(* ------------------------- *)
+(* partition *)
+(* ------------------------- *)
+(*val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*)
+(*let partition P l= (filter P l, filter (fun x -> not (P x)) l)*)
+
+(*val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*)
+(*let reversePartition P l= partition P (reverse l)*)
+
+
+(* ------------------------- *)
+(* delete first element *)
+(* with certain property *)
+(* ------------------------- *)
+
+(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> maybe (list 'a)*)
+ val _ = Define `
+ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P ([])= NONE)
+/\ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P (x :: xs)= (if (P x) then SOME xs else OPTION_MAP (\ xs' . x :: xs') (list_delete_first P xs)))`;
+
+
+
+(*val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a*)
+(*val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*)
+
+val _ = Define `
+ ((list_delete:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) eq x l= (option_CASE (list_delete_first (eq x) l) l I))`;
+
+
+
+(* ========================================================================== *)
+(* Zipping and unzipping lists *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* zip *)
+(* ------------------------- *)
+
+(* zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. *)
+(*val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) (* before combine *)
+ val _ = Define `
+ ((list_combine:'a list -> 'b list ->('a#'b)list) l1 l2= ((case (l1, l2) of
+ (x :: xs, y :: ys) => (x, y) :: list_combine xs ys
+ | _ => []
+)))`;
+
+
+(* ------------------------- *)
+(* unzip *)
+(* ------------------------- *)
+
+(*val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)*)
+(*let rec unzip l= match l with
+ | [] -> ([], [])
+ | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys)
+end*)
+
+(* ------------------------- *)
+(* distinct elements *)
+(* ------------------------- *)
+
+(*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*)
+(*let rec allDistinct l=
+ match l with
+ | [] -> true
+ | (x::l') -> not (elem x l') && allDistinct l'
+ end*)
+
+(* some more useful functions *)
+(*val mapMaybe : forall 'a 'b. ('a -> maybe 'b) -> list 'a -> list 'b*)
+ val mapMaybe_defn = Defn.Hol_multi_defns `
+ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f ([])= ([]))
+/\ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f (x::xs)=
+ ((case f x of
+ NONE => mapMaybe f xs
+ | SOME y => y :: (mapMaybe f xs)
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapMaybe_defn;
+
+(*val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b*)
+ val mapiAux_defn = Defn.Hol_multi_defns `
+ ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) ([])= ([]))
+/\ ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) (x :: xs)= ((f n x) :: mapiAux f (n +( 1 : num)) xs))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapiAux_defn;
+val _ = Define `
+ ((mapi:(num -> 'a -> 'b) -> 'a list -> 'b list) f l= (mapiAux f(( 0 : num)) l))`;
+
+
+(*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*)
+val _ = Define `
+ ((deletes:'a list -> 'a list -> 'a list) xs ys=
+ (FOLDL (combin$C (list_delete (=))) xs ys))`;
+
+
+(* ========================================================================== *)
+(* Comments (not clean yet, please ignore the rest of the file) *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* skipped from Haskell Lib*)
+(* -----------------------
+
+intersperse :: a -> [a] -> [a]
+intercalate :: [a] -> [[a]] -> [a]
+transpose :: [[a]] -> [[a]]
+subsequences :: [a] -> [[a]]
+permutations :: [a] -> [[a]]
+foldl` :: (a -> b -> a) -> a -> [b] -> aSource
+foldl1` :: (a -> a -> a) -> [a] -> aSource
+
+and
+or
+sum
+product
+maximum
+minimum
+scanl
+scanr
+scanl1
+scanr1
+Accumulating maps
+
+mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+
+iterate :: (a -> a) -> a -> [a]
+repeat :: a -> [a]
+cycle :: [a] -> [a]
+unfoldr
+
+
+takeWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source
+span :: (a -> Bool) -> [a] -> ([a], [a])Source
+break :: (a -> Bool) -> [a] -> ([a], [a])Source
+break p is equivalent to span (not . p).
+stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source
+group :: Eq a => [a] -> [[a]]Source
+inits :: [a] -> [[a]]Source
+tails :: [a] -> [[a]]Source
+
+
+isPrefixOf :: Eq a => [a] -> [a] -> BoolSource
+isSuffixOf :: Eq a => [a] -> [a] -> BoolSource
+isInfixOf :: Eq a => [a] -> [a] -> BoolSource
+
+
+
+notElem :: Eq a => a -> [a] -> BoolSource
+
+zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source
+zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source
+zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source
+zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source
+zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source
+
+zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source
+zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source
+zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source
+zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source
+zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source
+zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source
+
+
+unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source
+unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source
+unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source
+unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source
+unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source
+
+
+lines :: String -> [String]Source
+words :: String -> [String]Source
+unlines :: [String] -> StringSource
+unwords :: [String] -> StringSource
+nub :: Eq a => [a] -> [a]Source
+delete :: Eq a => a -> [a] -> [a]Source
+
+(\\) :: Eq a => [a] -> [a] -> [a]Source
+union :: Eq a => [a] -> [a] -> [a]Source
+intersect :: Eq a => [a] -> [a] -> [a]Source
+sort :: Ord a => [a] -> [a]Source
+insert :: Ord a => a -> [a] -> [a]Source
+
+
+nubBy :: (a -> a -> Bool) -> [a] -> [a]Source
+deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source
+deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source
+sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source
+insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source
+maximumBy :: (a -> a -> Ordering) -> [a] -> aSource
+minimumBy :: (a -> a -> Ordering) -> [a] -> aSource
+genericLength :: Num i => [b] -> iSource
+genericTake :: Integral i => i -> [a] -> [a]Source
+genericDrop :: Integral i => i -> [a] -> [a]Source
+genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source
+genericIndex :: Integral a => [b] -> a -> bSource
+genericReplicate :: Integral i => i -> a -> [a]Source
+
+
+*)
+
+
+(* ----------------------- *)
+(* skipped from Lem Lib *)
+(* -----------------------
+
+
+val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c
+val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c
+val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a
+val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c
+
+
+(* now maybe result and called lookup *)
+val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b
+let inline {ocaml} assoc = Ocaml.List.assoc
+
+
+val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool
+val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b)
+
+
+
+val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+
+val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a
+val intersect : forall 'a. list 'a -> list 'a -> list 'a
+
+
+*)
+
+(*val catMaybes : forall 'a. list (maybe 'a) -> list 'a*)
+ val catMaybes_defn = Defn.Hol_multi_defns `
+ ((catMaybes:('a option)list -> 'a list) ([])=
+ ([]))
+/\ ((catMaybes:('a option)list -> 'a list) (NONE :: xs')=
+ (catMaybes xs'))
+/\ ((catMaybes:('a option)list -> 'a list) (SOME x :: xs')=
+ (x :: catMaybes xs'))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) catMaybes_defn;
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_list_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_list_extraScript.sml
new file mode 100644
index 0000000..123d8a7
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_list_extraScript.sml
@@ -0,0 +1,110 @@
+(*Generated by Lem from list_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_tupleTheory lem_numTheory lem_listTheory lem_assert_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_list_extra"
+
+
+
+(*open import Bool Maybe Basic_classes Tuple Num List Assert_extra*)
+
+(* ------------------------- *)
+(* head of non-empty list *)
+(* ------------------------- *)
+(*val head : forall 'a. list 'a -> 'a*)
+(*let head l= match l with | x::xs -> x | [] -> failwith "List_extra.head of empty list" end*)
+
+
+(* ------------------------- *)
+(* tail of non-empty list *)
+(* ------------------------- *)
+(*val tail : forall 'a. list 'a -> list 'a*)
+(*let tail l= match l with | x::xs -> xs | [] -> failwith "List_extra.tail of empty list" end*)
+
+
+(* ------------------------- *)
+(* last *)
+(* ------------------------- *)
+(*val last : forall 'a. list 'a -> 'a*)
+(*let rec last l= match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith "List_extra.last of empty list" end*)
+
+
+(* ------------------------- *)
+(* init *)
+(* ------------------------- *)
+
+(* All elements of a non-empty list except the last one. *)
+(*val init : forall 'a. list 'a -> list 'a*)
+(*let rec init l= match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith "List_extra.init of empty list" end*)
+
+
+(* ------------------------- *)
+(* foldl1 / foldr1 *)
+(* ------------------------- *)
+
+(* folding functions for non-empty lists,
+ which don`t take the base case *)
+(*val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*)
+val _ = Define `
+ ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)= (FOLDL f x xs))
+/\ ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])= (failwith "List_extra.foldl1 of empty list"))`;
+
+
+(*val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*)
+val _ = Define `
+ ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)= (FOLDR f x xs))
+/\ ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])= (failwith "List_extra.foldr1 of empty list"))`;
+
+
+
+(* ------------------------- *)
+(* nth element *)
+(* ------------------------- *)
+
+(* get the nth element of a list *)
+(*val nth : forall 'a. list 'a -> nat -> 'a*)
+(*let nth l n= match index l n with Just e -> e | Nothing -> failwith "List_extra.nth" end*)
+
+
+(* ------------------------- *)
+(* Find_non_pure *)
+(* ------------------------- *)
+(*val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a*)
+val _ = Define `
+ ((findNonPure:('a -> bool) -> 'a list -> 'a) P l= ((case (list_find_opt P l) of
+ SOME e => e
+ | NONE => failwith "List_extra.findNonPure"
+)))`;
+
+
+
+(* ------------------------- *)
+(* zip same length *)
+(* ------------------------- *)
+
+(*val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*)
+(*let rec zipSameLength l1 l2= match (l1, l2) with
+ | (x :: xs, y :: ys) -> (x, y) :: zipSameLength xs ys
+ | ([], []) -> []
+ | _ -> failwith "List_extra.zipSameLength of different length lists"
+
+end*)
+
+(*val unfoldr: forall 'a 'b. ('a -> maybe ('b * 'a)) -> 'a -> list 'b*)
+ val unfoldr_defn = Hol_defn "unfoldr" `
+ ((unfoldr:('a ->('b#'a)option) -> 'a -> 'b list) f x=
+ ((case f x of
+ SOME (y, x') =>
+ y :: unfoldr f x'
+ | NONE =>
+ []
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn unfoldr_defn;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_machine_wordScript.sml b/prover_snapshots/hol4/lib/lem/lem_machine_wordScript.sml
new file mode 100644
index 0000000..40bbef3
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_machine_wordScript.sml
@@ -0,0 +1,433 @@
+(*Generated by Lem from machine_word.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_numTheory lem_basic_classesTheory lem_showTheory lem_functionTheory wordsTheory wordsLib bitstringTheory integer_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_machine_word"
+
+
+
+(*open import Bool Num Basic_classes Show Function*)
+
+(*open import {isabelle} `HOL-Word.Word`*)
+(*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*)
+
+(*type mword 'a*)
+
+(*class (Size 'a)
+ val size : nat
+end*)
+
+(*val native_size : forall 'a. nat*)
+
+(*val ocaml_inject : forall 'a. nat * natural -> mword 'a*)
+
+(* A singleton type family that can be used to carry a size as the type parameter *)
+
+(*type itself 'a*)
+
+(*val the_value : forall 'a. itself 'a*)
+
+(*val size_itself : forall 'a. Size 'a => itself 'a -> nat*)
+val _ = Define `
+ ((size_itself:'a itself -> num) x= (dimindex (the_value : 'a itself)))`;
+
+
+(*******************************************************************)
+(* Fixed bitwidths extracted from Anthony's models. *)
+(* *)
+(* If you need a size N that is not included here, put the lines *)
+(* *)
+(* type tyN *)
+(* instance (Size tyN) let size = N end *)
+(* declare isabelle target_rep type tyN = `N` *)
+(* declare hol target_rep type tyN = `N` *)
+(* *)
+(* in your project, replacing N in each line. *)
+(*******************************************************************)
+
+(*type ty1*)
+(*type ty2*)
+(*type ty3*)
+(*type ty4*)
+(*type ty5*)
+(*type ty6*)
+(*type ty7*)
+(*type ty8*)
+(*type ty9*)
+(*type ty10*)
+(*type ty11*)
+(*type ty12*)
+(*type ty13*)
+(*type ty14*)
+(*type ty15*)
+(*type ty16*)
+(*type ty17*)
+(*type ty18*)
+(*type ty19*)
+(*type ty20*)
+(*type ty21*)
+(*type ty22*)
+(*type ty23*)
+(*type ty24*)
+(*type ty25*)
+(*type ty26*)
+(*type ty27*)
+(*type ty28*)
+(*type ty29*)
+(*type ty30*)
+(*type ty31*)
+(*type ty32*)
+(*type ty33*)
+(*type ty34*)
+(*type ty35*)
+(*type ty36*)
+(*type ty37*)
+(*type ty38*)
+(*type ty39*)
+(*type ty40*)
+(*type ty41*)
+(*type ty42*)
+(*type ty43*)
+(*type ty44*)
+(*type ty45*)
+(*type ty46*)
+(*type ty47*)
+(*type ty48*)
+(*type ty49*)
+(*type ty50*)
+(*type ty51*)
+(*type ty52*)
+(*type ty53*)
+(*type ty54*)
+(*type ty55*)
+(*type ty56*)
+(*type ty57*)
+(*type ty58*)
+(*type ty59*)
+(*type ty60*)
+(*type ty61*)
+(*type ty62*)
+(*type ty63*)
+(*type ty64*)
+(*type ty65*)
+(*type ty66*)
+(*type ty67*)
+(*type ty68*)
+(*type ty69*)
+(*type ty70*)
+(*type ty71*)
+(*type ty72*)
+(*type ty73*)
+(*type ty74*)
+(*type ty75*)
+(*type ty76*)
+(*type ty77*)
+(*type ty78*)
+(*type ty79*)
+(*type ty80*)
+(*type ty81*)
+(*type ty82*)
+(*type ty83*)
+(*type ty84*)
+(*type ty85*)
+(*type ty86*)
+(*type ty87*)
+(*type ty88*)
+(*type ty89*)
+(*type ty90*)
+(*type ty91*)
+(*type ty92*)
+(*type ty93*)
+(*type ty94*)
+(*type ty95*)
+(*type ty96*)
+(*type ty97*)
+(*type ty98*)
+(*type ty99*)
+(*type ty100*)
+(*type ty101*)
+(*type ty102*)
+(*type ty103*)
+(*type ty104*)
+(*type ty105*)
+(*type ty106*)
+(*type ty107*)
+(*type ty108*)
+(*type ty109*)
+(*type ty110*)
+(*type ty111*)
+(*type ty112*)
+(*type ty113*)
+(*type ty114*)
+(*type ty115*)
+(*type ty116*)
+(*type ty117*)
+(*type ty118*)
+(*type ty119*)
+(*type ty120*)
+(*type ty121*)
+(*type ty122*)
+(*type ty123*)
+(*type ty124*)
+(*type ty125*)
+(*type ty126*)
+(*type ty127*)
+(*type ty128*)
+(*type ty129*)
+(*type ty130*)
+(*type ty131*)
+(*type ty132*)
+(*type ty133*)
+(*type ty134*)
+(*type ty135*)
+(*type ty136*)
+(*type ty137*)
+(*type ty138*)
+(*type ty139*)
+(*type ty140*)
+(*type ty141*)
+(*type ty142*)
+(*type ty143*)
+(*type ty144*)
+(*type ty145*)
+(*type ty146*)
+(*type ty147*)
+(*type ty148*)
+(*type ty149*)
+(*type ty150*)
+(*type ty151*)
+(*type ty152*)
+(*type ty153*)
+(*type ty154*)
+(*type ty155*)
+(*type ty156*)
+(*type ty157*)
+(*type ty158*)
+(*type ty159*)
+(*type ty160*)
+(*type ty161*)
+(*type ty162*)
+(*type ty163*)
+(*type ty164*)
+(*type ty165*)
+(*type ty166*)
+(*type ty167*)
+(*type ty168*)
+(*type ty169*)
+(*type ty170*)
+(*type ty171*)
+(*type ty172*)
+(*type ty173*)
+(*type ty174*)
+(*type ty175*)
+(*type ty176*)
+(*type ty177*)
+(*type ty178*)
+(*type ty179*)
+(*type ty180*)
+(*type ty181*)
+(*type ty182*)
+(*type ty183*)
+(*type ty184*)
+(*type ty185*)
+(*type ty186*)
+(*type ty187*)
+(*type ty188*)
+(*type ty189*)
+(*type ty190*)
+(*type ty191*)
+(*type ty192*)
+(*type ty193*)
+(*type ty194*)
+(*type ty195*)
+(*type ty196*)
+(*type ty197*)
+(*type ty198*)
+(*type ty199*)
+(*type ty200*)
+(*type ty201*)
+(*type ty202*)
+(*type ty203*)
+(*type ty204*)
+(*type ty205*)
+(*type ty206*)
+(*type ty207*)
+(*type ty208*)
+(*type ty209*)
+(*type ty210*)
+(*type ty211*)
+(*type ty212*)
+(*type ty213*)
+(*type ty214*)
+(*type ty215*)
+(*type ty216*)
+(*type ty217*)
+(*type ty218*)
+(*type ty219*)
+(*type ty220*)
+(*type ty221*)
+(*type ty222*)
+(*type ty223*)
+(*type ty224*)
+(*type ty225*)
+(*type ty226*)
+(*type ty227*)
+(*type ty228*)
+(*type ty229*)
+(*type ty230*)
+(*type ty231*)
+(*type ty232*)
+(*type ty233*)
+(*type ty234*)
+(*type ty235*)
+(*type ty236*)
+(*type ty237*)
+(*type ty238*)
+(*type ty239*)
+(*type ty240*)
+(*type ty241*)
+(*type ty242*)
+(*type ty243*)
+(*type ty244*)
+(*type ty245*)
+(*type ty246*)
+(*type ty247*)
+(*type ty248*)
+(*type ty249*)
+(*type ty250*)
+(*type ty251*)
+(*type ty252*)
+(*type ty253*)
+(*type ty254*)
+(*type ty255*)
+(*type ty256*)
+(*type ty257*)
+
+(*val word_length : forall 'a. mword 'a -> nat*)
+
+(******************************************************************)
+(* Conversions *)
+(******************************************************************)
+
+(*val signedIntegerFromWord : forall 'a. mword 'a -> integer*)
+
+(*val unsignedIntegerFromWord : forall 'a. mword 'a -> integer*)
+
+(* Version without typeclass constraint so that we can derive operations
+ in Lem for one of the theorem provers without requiring it. *)
+(*val proverWordFromInteger : forall 'a. integer -> mword 'a*)
+
+(*val wordFromInteger : forall 'a. Size 'a => integer -> mword 'a*)
+(* The OCaml version is defined after the arithmetic operations, below. *)
+
+(*val naturalFromWord : forall 'a. mword 'a -> natural*)
+
+(*val wordFromNatural : forall 'a. Size 'a => natural -> mword 'a*)
+
+(*val wordToHex : forall 'a. mword 'a -> string*)
+
+val _ = Define `
+((instance_Show_Show_Machine_word_mword_dict:('a words$word)Show_class)= (<|
+
+ show_method := words$word_to_hex_string|>))`;
+
+
+(*val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a*)
+
+(*val bitlistFromWord : forall 'a. mword 'a -> list bool*)
+
+
+(*val size_test_fn : forall 'a. Size 'a => mword 'a -> nat*)
+val _ = Define `
+ ((size_test_fn:'a words$word -> num) _= (dimindex (the_value : 'a itself)))`;
+
+
+(******************************************************************)
+(* Comparisons *)
+(******************************************************************)
+
+(*val mwordEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val signedLess : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(* Comparison tests are below, after the definition of wordFromInteger *)
+
+(******************************************************************)
+(* Appending, splitting and probing words *)
+(******************************************************************)
+
+(*val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c*)
+
+(* Note that we assume the result type has the correct size, especially
+ for Isabelle. *)
+(*val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b*)
+
+(* Needs to be in the prover because we'd end up with unknown sizes in the
+ types in Lem.
+*)
+(*val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a*)
+
+(*val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a*)
+
+(*val getBit : forall 'a. mword 'a -> nat -> bool*)
+
+(*val msb : forall 'a. mword 'a -> bool*)
+
+(*val lsb : forall 'a. mword 'a -> bool*)
+
+(******************************************************************)
+(* Bitwise operations, shifts, etc. *)
+(******************************************************************)
+
+(*val shiftLeft : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val shiftRight : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val lAnd : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lOr : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lXor : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lNot : forall 'a. mword 'a -> mword 'a*)
+
+(*val rotateRight : forall 'a. nat -> mword 'a -> mword 'a*)
+
+(*val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a*)
+
+(*val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*)
+
+(*val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*)
+
+(* Sign extension tests are below, after the definition of wordFromInteger *)
+
+(*****************************************************************)
+(* Arithmetic *)
+(*****************************************************************)
+
+(*val plus : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val minus : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val uminus : forall 'a. mword 'a -> mword 'a*)
+
+(*val times : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+(*val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_mapScript.sml b/prover_snapshots/hol4/lib/lem/lem_mapScript.sml
new file mode 100644
index 0000000..e05af7f
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_mapScript.sml
@@ -0,0 +1,153 @@
+(*Generated by Lem from map.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_maybeTheory lem_listTheory lem_tupleTheory lem_setTheory lem_numTheory finite_mapTheory finite_mapLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_map"
+
+
+
+(*open import Bool Basic_classes Function Maybe List Tuple Set Num*)
+(*open import {hol} `finite_mapTheory` `finite_mapLib`*)
+
+(*type map 'k 'v*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* Map equality. *)
+(* -------------------------------------------------------------------------- *)
+
+(*val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool*)
+(*val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Map type class *)
+(* -------------------------------------------------------------------------- *)
+
+(*class ( MapKeyType 'a )
+ val {ocaml;coq} mapKeyCompare : 'a -> 'a -> ordering
+end*)
+
+(* -------------------------------------------------------------------------- *)
+(* Empty maps *)
+(* -------------------------------------------------------------------------- *)
+
+(*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*)
+(*val emptyBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Insertion *)
+(* -------------------------------------------------------------------------- *)
+
+(*val insert : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Singleton *)
+(* -------------------------------------------------------------------------- *)
+
+(*val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* Emptyness check *)
+(* -------------------------------------------------------------------------- *)
+
+(*val null : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* lookup *)
+(* -------------------------------------------------------------------------- *)
+
+(*val lookupBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> maybe 'v*)
+
+(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> maybe 'v*)
+
+(* -------------------------------------------------------------------------- *)
+(* findWithDefault *)
+(* -------------------------------------------------------------------------- *)
+
+(*val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v*)
+
+(* -------------------------------------------------------------------------- *)
+(* from lists *)
+(* -------------------------------------------------------------------------- *)
+
+(*val fromList : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v*)
+(*let fromList l= foldl (fun m (k,v) -> insert k v m) empty l*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* to sets / domain / range *)
+(* -------------------------------------------------------------------------- *)
+
+(*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*)
+(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> ordering) -> map 'k 'v -> set ('k * 'v)*)
+
+
+(*val domainBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v -> set 'k*)
+(*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*)
+
+
+(*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*)
+(*val rangeBy : forall 'k 'v. ('v -> 'v -> ordering) -> map 'k 'v -> set 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* member *)
+(* -------------------------------------------------------------------------- *)
+
+(*val member : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*)
+
+(*val notMember : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*)
+
+(* -------------------------------------------------------------------------- *)
+(* Quantification *)
+(* -------------------------------------------------------------------------- *)
+
+(*val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*)
+(*val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*)
+
+(*let all P m= (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Set-like operations. *)
+(* -------------------------------------------------------------------------- *)
+(*val deleteBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> map 'k 'v*)
+(*val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*)
+(*val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*)
+
+(*val union : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v*)
+
+(*val unions : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Maps (in the functor sense). *)
+(* -------------------------------------------------------------------------- *)
+
+(*val map : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w*)
+
+(*val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w*)
+
+(* -------------------------------------------------------------------------- *)
+(* Cardinality *)
+(* -------------------------------------------------------------------------- *)
+(*val size : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat*)
+
+(* instance of SetType *)
+val _ = Define `
+ ((map_setElemCompare:(('d#'c)set ->('b#'a)set -> 'e) ->('d,'c)fmap ->('b,'a)fmap -> 'e) cmp x y=
+ (cmp (FMAP_TO_SET x) (FMAP_TO_SET y)))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_map_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_map_extraScript.sml
new file mode 100644
index 0000000..7e32efb
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_map_extraScript.sml
@@ -0,0 +1,72 @@
+(*Generated by Lem from map_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_assert_extraTheory lem_maybeTheory lem_listTheory lem_numTheory lem_setTheory lem_mapTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_map_extra"
+
+
+
+(*open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map*)
+
+(* -------------------------------------------------------------------------- *)
+(* find *)
+(* -------------------------------------------------------------------------- *)
+
+(*val find : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> 'v*)
+(*let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith "Map_extra.find" end*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* from sets / domain / range *)
+(* -------------------------------------------------------------------------- *)
+
+
+(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> map 'k 'v*)
+(*let fromSet f s= Set_helpers.fold (fun k m -> Map.insert k (f k) m) s Map.empty*)
+
+(*
+assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty)
+assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)]
+*)
+
+(* -------------------------------------------------------------------------- *)
+(* fold *)
+(* -------------------------------------------------------------------------- *)
+
+(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> map 'k 'v -> 'r -> 'r*)
+val _ = Define `
+ ((fold:('k -> 'v -> 'r -> 'r) ->('k,'v)fmap -> 'r -> 'r) f m v= (ITSET (\ (k, v) r . f k v r) (FMAP_TO_SET m) v))`;
+
+
+(*
+assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9)
+assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12)
+*)
+
+(*val toList: forall 'k 'v. MapKeyType 'k => map 'k 'v -> list ('k * 'v)*)
+(* declare compile_message toList = "Map_extra.toList is only defined for the ocaml, isabelle and coq backend" *)
+
+(* more 'map' functions *)
+
+(* TODO: this function is in map_extra rather than map just for implementation reasons *)
+(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> maybe 'c) -> map 'a 'b -> map 'a 'c*)
+(* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *)
+val _ = Define `
+ ((option_map:('a -> 'b -> 'c option) ->('a,'b)fmap ->('a,'c)fmap) f m=
+ (FOLDL
+ (\ m' (k, v) .
+ (case f k v of
+ NONE => m'
+ | SOME v' =>m' |+ (k, v')
+ ))
+ FEMPTY
+ (MAP_TO_LIST m)))`;
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_maybeScript.sml b/prover_snapshots/hol4/lib/lem/lem_maybeScript.sml
new file mode 100644
index 0000000..bcf4348
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_maybeScript.sml
@@ -0,0 +1,112 @@
+(*Generated by Lem from maybe.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_maybe"
+
+
+
+(*open import Bool Basic_classes Function*)
+
+(* ========================================================================== *)
+(* Basic stuff *)
+(* ========================================================================== *)
+
+(*type maybe 'a =
+ | Nothing
+ | Just of 'a*)
+
+
+(*val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool*)
+(*val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool*)
+
+val _ = Define `
+ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE NONE= T)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE (SOME _)= F)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME _) NONE= F)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME x') (SOME y')= (eq x' y'))`;
+
+
+
+val _ = Define `
+ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp NONE NONE= EQUAL)
+/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp NONE (SOME _)= LESS)
+/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp (SOME _) NONE= GREATER)
+/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp (SOME x') (SOME y')= (cmp x' y'))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Maybe_maybe_dict:'a Ord_class ->('a option)Ord_class)dict_Basic_classes_Ord_a= (<|
+
+ compare_method := (maybeCompare
+ dict_Basic_classes_Ord_a.compare_method);
+
+ isLess_method := (\ m1 . (\ m2 . maybeCompare
+ dict_Basic_classes_Ord_a.compare_method m1 m2 = LESS));
+
+ isLessEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare
+ dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = LESS) \/ (r = EQUAL))));
+
+ isGreater_method := (\ m1 . (\ m2 . maybeCompare
+ dict_Basic_classes_Ord_a.compare_method m1 m2 = GREATER));
+
+ isGreaterEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare
+ dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = GREATER) \/ (r = EQUAL))))|>))`;
+
+
+(* ----------------------- *)
+(* maybe *)
+(* ----------------------- *)
+
+(*val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b*)
+(*let maybe d f mb= match mb with
+ | Just a -> f a
+ | Nothing -> d
+end*)
+
+(* ----------------------- *)
+(* isJust / isNothing *)
+(* ----------------------- *)
+
+(*val isJust : forall 'a. maybe 'a -> bool*)
+(*let isJust mb= match mb with
+ | Just _ -> true
+ | Nothing -> false
+end*)
+
+(*val isNothing : forall 'a. maybe 'a -> bool*)
+(*let isNothing mb= match mb with
+ | Just _ -> false
+ | Nothing -> true
+end*)
+
+(* ----------------------- *)
+(* fromMaybe *)
+(* ----------------------- *)
+
+(*val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a*)
+(*let fromMaybe d mb= match mb with
+ | Just v -> v
+ | Nothing -> d
+end*)
+
+(* ----------------------- *)
+(* map *)
+(* ----------------------- *)
+
+(*val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b*)
+(*let map f= maybe Nothing (fun v -> Just (f v))*)
+
+
+(* ----------------------- *)
+(* bind *)
+(* ----------------------- *)
+
+(*val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b*)
+(*let bind mb f= maybe Nothing f mb*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_maybe_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_maybe_extraScript.sml
new file mode 100644
index 0000000..22d7e06
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_maybe_extraScript.sml
@@ -0,0 +1,23 @@
+(*Generated by Lem from maybe_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_basic_classesTheory lem_maybeTheory lem_assert_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_maybe_extra"
+
+
+
+(*open import Basic_classes Maybe Assert_extra*)
+
+(* ----------------------- *)
+(* fromJust *)
+(* ----------------------- *)
+
+(*val fromJust : forall 'a. maybe 'a -> 'a*)
+(*let fromJust op= match op with | Just v -> v | Nothing -> failwith "fromJust of Nothing" end*)
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_numScript.sml b/prover_snapshots/hol4/lib/lem/lem_numScript.sml
new file mode 100644
index 0000000..d891079
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_numScript.sml
@@ -0,0 +1,1329 @@
+(*Generated by Lem from num.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory transcTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_num"
+
+
+
+(*open import Bool Basic_classes*)
+(*open import {isabelle} `HOL-Word.Word` `Complex_Main`*)
+(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`*)
+(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Reals.Rsqrt_def` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*)
+
+(*class inline ( Numeral 'a )
+ val fromNumeral : numeral -> 'a
+end*)
+
+(* ========================================================================== *)
+(* Syntactic type-classes for common operations *)
+(* ========================================================================== *)
+
+(* Typeclasses can be used as a mean to overload constants like "+", "-", etc *)
+
+val _ = Hol_datatype `
+(* 'a *) NumNegate_class= <|
+ numNegate_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumAbs_class= <|
+ abs_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumAdd_class= <|
+ numAdd_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumMinus_class= <|
+ numMinus_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumMult_class= <|
+ numMult_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumPow_class= <|
+ numPow_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumDivision_class= <|
+ numDivision_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumIntegerDivision_class= <|
+ div_method : 'a -> 'a -> 'a
+|>`;
+
+
+
+val _ = Hol_datatype `
+(* 'a *) NumRemainder_class= <|
+ mod_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumSucc_class= <|
+ succ_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) NumPred_class= <|
+ pred_method : 'a -> 'a
+|>`;
+
+
+
+(* ----------------------- *)
+(* natural *)
+(* ----------------------- *)
+
+(* unbounded size natural numbers *)
+(*type natural*)
+
+
+(* ----------------------- *)
+(* int *)
+(* ----------------------- *)
+
+(* bounded size integers with uncertain length *)
+
+(*type int*)
+
+
+(* ----------------------- *)
+(* integer *)
+(* ----------------------- *)
+
+(* unbounded size integers *)
+
+(*type integer*)
+
+(* ----------------------- *)
+(* bint *)
+(* ----------------------- *)
+
+(* TODO the bounded ints are only partially implemented, use with care. *)
+
+(* 32 bit integers *)
+(*type int32*)
+
+(* 64 bit integers *)
+(*type int64*)
+
+
+(* ----------------------- *)
+(* rational *)
+(* ----------------------- *)
+
+(* unbounded size and precision rational numbers *)
+
+(*type rational*) (* ???: better type for this in HOL? *)
+
+
+(* ----------------------- *)
+(* real *)
+(* ----------------------- *)
+
+(* real numbers *)
+(* Note that for OCaml, this is mapped to floats with 64 bits. *)
+
+(*type real*) (* ???: better type for this in HOL? *)
+
+
+(* ----------------------- *)
+(* double *)
+(* ----------------------- *)
+
+(* double precision floating point (64 bits) *)
+
+(*type float64*) (* ???: better type for this in HOL? *)
+
+(*type float32*) (* ???: better type for this in HOL? *)
+
+
+(* ========================================================================== *)
+(* Binding the standard operations for the number types *)
+(* ========================================================================== *)
+
+
+(* ----------------------- *)
+(* nat *)
+(* ----------------------- *)
+
+(*val natFromNumeral : numeral -> nat*)
+
+(*val natEq : nat -> nat -> bool*)
+
+(*val natLess : nat -> nat -> bool*)
+(*val natLessEqual : nat -> nat -> bool*)
+(*val natGreater : nat -> nat -> bool*)
+(*val natGreaterEqual : nat -> nat -> bool*)
+
+(*val natCompare : nat -> nat -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_nat_dict:(num)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val natAdd : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumAdd_nat_dict:(num)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val natMinus : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumMinus_nat_dict:(num)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val natSucc : nat -> nat*)
+(*let natSucc n= (Instance_Num_NumAdd_nat.+) n 1*)
+val _ = Define `
+((instance_Num_NumSucc_nat_dict:(num)NumSucc_class)= (<|
+
+ succ_method := SUC|>))`;
+
+
+(*val natPred : nat -> nat*)
+val _ = Define `
+((instance_Num_NumPred_nat_dict:(num)NumPred_class)= (<|
+
+ pred_method := PRE|>))`;
+
+
+(*val natMult : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumMult_nat_dict:(num)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+(*val natDiv : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_nat_dict:(num)NumIntegerDivision_class)= (<|
+
+ div_method := (DIV)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_nat_dict:(num)NumDivision_class)= (<|
+
+ numDivision_method := (DIV)|>))`;
+
+
+(*val natMod : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumRemainder_nat_dict:(num)NumRemainder_class)= (<|
+
+ mod_method := (MOD)|>))`;
+
+
+
+(*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*)
+ val _ = Define `
+ ((gen_pow_aux:('a -> 'a -> 'a) -> 'a -> 'a -> num -> 'a) (mul : 'a -> 'a -> 'a) (a : 'a) (b : 'a) (e : num)=
+ ((case e of
+ 0 => a (* cannot happen, call discipline guarentees e >= 1 *)
+ | (SUC 0) => mul a b
+ | ( (SUC(SUC e'))) => let e'' = (e DIV( 2 : num)) in
+ let a' = (if (e MOD( 2 : num)) =( 0 : num) then a else mul a b) in
+ gen_pow_aux mul a' (mul b b) e''
+ )))`;
+
+
+val _ = Define `
+ ((gen_pow:'a ->('a -> 'a -> 'a) -> 'a -> num -> 'a) (one1 : 'a) (mul : 'a -> 'a -> 'a) (b : 'a) (e : num) : 'a=
+ (if e <( 0 : num) then one1 else
+ if (e =( 0 : num)) then one1 else gen_pow_aux mul one1 b e))`;
+
+
+(*val natPow : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumPow_nat_dict:(num)NumPow_class)= (<|
+
+ numPow_method := ( ** )|>))`;
+
+
+(*val natMin : nat -> nat -> nat*)
+
+(*val natMax : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_nat_dict:(num)OrdMaxMin_class)= (<|
+
+ max_method := MAX;
+
+ min_method := MIN|>))`;
+
+
+
+(* ----------------------- *)
+(* natural *)
+(* ----------------------- *)
+
+(*val naturalFromNumeral : numeral -> natural*)
+
+(*val naturalEq : natural -> natural -> bool*)
+
+(*val naturalLess : natural -> natural -> bool*)
+(*val naturalLessEqual : natural -> natural -> bool*)
+(*val naturalGreater : natural -> natural -> bool*)
+(*val naturalGreaterEqual : natural -> natural -> bool*)
+
+(*val naturalCompare : natural -> natural -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_natural_dict:(num)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val naturalAdd : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_natural_dict:(num)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val naturalMinus : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_natural_dict:(num)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val naturalSucc : natural -> natural*)
+(*let naturalSucc n= (Instance_Num_NumAdd_Num_natural.+) n 1*)
+val _ = Define `
+((instance_Num_NumSucc_Num_natural_dict:(num)NumSucc_class)= (<|
+
+ succ_method := SUC|>))`;
+
+
+(*val naturalPred : natural -> natural*)
+val _ = Define `
+((instance_Num_NumPred_Num_natural_dict:(num)NumPred_class)= (<|
+
+ pred_method := PRE|>))`;
+
+
+(*val naturalMult : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_natural_dict:(num)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+
+(*val naturalPow : natural -> nat -> natural*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_natural_dict:(num)NumPow_class)= (<|
+
+ numPow_method := ( ** )|>))`;
+
+
+(*val naturalDiv : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_natural_dict:(num)NumIntegerDivision_class)= (<|
+
+ div_method := (DIV)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_natural_dict:(num)NumDivision_class)= (<|
+
+ numDivision_method := (DIV)|>))`;
+
+
+(*val naturalMod : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_natural_dict:(num)NumRemainder_class)= (<|
+
+ mod_method := (MOD)|>))`;
+
+
+(*val naturalMin : natural -> natural -> natural*)
+
+(*val naturalMax : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_natural_dict:(num)OrdMaxMin_class)= (<|
+
+ max_method := MAX;
+
+ min_method := MIN|>))`;
+
+
+
+(* ----------------------- *)
+(* int *)
+(* ----------------------- *)
+
+(*val intFromNumeral : numeral -> int*)
+
+(*val intEq : int -> int -> bool*)
+
+(*val intLess : int -> int -> bool*)
+(*val intLessEqual : int -> int -> bool*)
+(*val intGreater : int -> int -> bool*)
+(*val intGreaterEqual : int -> int -> bool*)
+
+(*val intCompare : int -> int -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int_dict:(int)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val intNegate : int -> int*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int_dict:(int)NumNegate_class)= (<|
+
+ numNegate_method := (\ i. ~ i)|>))`;
+
+
+(*val intAbs : int -> int*) (* TODO: check *)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int_dict:(int)NumAbs_class)= (<|
+
+ abs_method := ABS|>))`;
+
+
+(*val intAdd : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int_dict:(int)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val intMinus : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int_dict:(int)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val intSucc : int -> int*)
+val _ = Define `
+((instance_Num_NumSucc_Num_int_dict:(int)NumSucc_class)= (<|
+
+ succ_method := (\ n. n +( 1 : int))|>))`;
+
+
+(*val intPred : int -> int*)
+val _ = Define `
+((instance_Num_NumPred_Num_int_dict:(int)NumPred_class)= (<|
+
+ pred_method := (\ n. n -( 1 : int))|>))`;
+
+
+(*val intMult : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int_dict:(int)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+
+(*val intPow : int -> nat -> int*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_int_dict:(int)NumPow_class)= (<|
+
+ numPow_method := ( ** )|>))`;
+
+
+(*val intDiv : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int_dict:(int)NumIntegerDivision_class)= (<|
+
+ div_method := (/)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int_dict:(int)NumDivision_class)= (<|
+
+ numDivision_method := (/)|>))`;
+
+
+(*val intMod : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int_dict:(int)NumRemainder_class)= (<|
+
+ mod_method := (%)|>))`;
+
+
+(*val intMin : int -> int -> int*)
+
+(*val intMax : int -> int -> int*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int_dict:(int)OrdMaxMin_class)= (<|
+
+ max_method := int_max;
+
+ min_method := int_min|>))`;
+
+
+(* ----------------------- *)
+(* int32 *)
+(* ----------------------- *)
+(*val int32FromNumeral : numeral -> int32*)
+
+(*val int32Eq : int32 -> int32 -> bool*)
+
+(*val int32Less : int32 -> int32 -> bool*)
+(*val int32LessEqual : int32 -> int32 -> bool*)
+(*val int32Greater : int32 -> int32 -> bool*)
+(*val int32GreaterEqual : int32 -> int32 -> bool*)
+
+(*val int32Compare : int32 -> int32 -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int32_dict:(word32)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val int32Negate : int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int32_dict:(word32)NumNegate_class)= (<|
+
+ numNegate_method := (\ i. ((- i) : word32))|>))`;
+
+
+(*val int32Abs : int32 -> int32*)
+val _ = Define `
+ ((int32Abs:word32 -> word32) i= (if((n2w 0) : word32) <= i then i else ((- i) : word32)))`;
+
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int32_dict:(word32)NumAbs_class)= (<|
+
+ abs_method := int32Abs|>))`;
+
+
+
+(*val int32Add : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int32_dict:(word32)NumAdd_class)= (<|
+
+ numAdd_method := (\ i1 i2. ((word_add i1 i2) : word32))|>))`;
+
+
+(*val int32Minus : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int32_dict:(word32)NumMinus_class)= (<|
+
+ numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word32))|>))`;
+
+
+(*val int32Succ : int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumSucc_Num_int32_dict:(word32)NumSucc_class)= (<|
+
+ succ_method := (\ n. ((word_add n (((n2w 1) : word32))) : word32))|>))`;
+
+
+(*val int32Pred : int32 -> int32*)
+val _ = Define `
+((instance_Num_NumPred_Num_int32_dict:(word32)NumPred_class)= (<|
+
+ pred_method := (\ n. ((word_sub n (((n2w 1) : word32))) : word32))|>))`;
+
+
+(*val int32Mult : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int32_dict:(word32)NumMult_class)= (<|
+
+ numMult_method := (\ i1 i2. ((word_mul i1 i2) : word32))|>))`;
+
+
+
+(*val int32Pow : int32 -> nat -> int32*)
+val _ = Define `
+ ((int32Pow:word32 -> num -> word32)= (gen_pow(((n2w 1) : word32)) (\ i1 i2. ((word_mul i1 i2) : word32))))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_int32_dict:(word32)NumPow_class)= (<|
+
+ numPow_method := int32Pow|>))`;
+
+
+(*val int32Div : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int32_dict:(word32)NumIntegerDivision_class)= (<|
+
+ div_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int32_dict:(word32)NumDivision_class)= (<|
+
+ numDivision_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`;
+
+
+(*val int32Mod : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int32_dict:(word32)NumRemainder_class)= (<|
+
+ mod_method := (\ i1 i2. ((word_mod i1 i2) : word32))|>))`;
+
+
+(*val int32Min : int32 -> int32 -> int32*)
+
+(*val int32Max : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int32_dict:(word32)OrdMaxMin_class)= (<|
+
+ max_method := word_smax;
+
+ min_method := word_smin|>))`;
+
+
+
+
+(* ----------------------- *)
+(* int64 *)
+(* ----------------------- *)
+(*val int64FromNumeral : numeral -> int64*)
+
+(*val int64Eq : int64 -> int64 -> bool*)
+
+(*val int64Less : int64 -> int64 -> bool*)
+(*val int64LessEqual : int64 -> int64 -> bool*)
+(*val int64Greater : int64 -> int64 -> bool*)
+(*val int64GreaterEqual : int64 -> int64 -> bool*)
+
+(*val int64Compare : int64 -> int64 -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int64_dict:(word64)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val int64Negate : int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int64_dict:(word64)NumNegate_class)= (<|
+
+ numNegate_method := (\ i. ((- i) : word64))|>))`;
+
+
+(*val int64Abs : int64 -> int64*)
+val _ = Define `
+ ((int64Abs:word64 -> word64) i= (if((n2w 0) : word64) <= i then i else ((- i) : word64)))`;
+
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int64_dict:(word64)NumAbs_class)= (<|
+
+ abs_method := int64Abs|>))`;
+
+
+
+(*val int64Add : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int64_dict:(word64)NumAdd_class)= (<|
+
+ numAdd_method := (\ i1 i2. ((word_add i1 i2) : word64))|>))`;
+
+
+(*val int64Minus : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int64_dict:(word64)NumMinus_class)= (<|
+
+ numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word64))|>))`;
+
+
+(*val int64Succ : int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumSucc_Num_int64_dict:(word64)NumSucc_class)= (<|
+
+ succ_method := (\ n. ((word_add n (((n2w 1) : word64))) : word64))|>))`;
+
+
+(*val int64Pred : int64 -> int64*)
+val _ = Define `
+((instance_Num_NumPred_Num_int64_dict:(word64)NumPred_class)= (<|
+
+ pred_method := (\ n. ((word_sub n (((n2w 1) : word64))) : word64))|>))`;
+
+
+(*val int64Mult : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int64_dict:(word64)NumMult_class)= (<|
+
+ numMult_method := (\ i1 i2. ((word_mul i1 i2) : word64))|>))`;
+
+
+
+(*val int64Pow : int64 -> nat -> int64*)
+val _ = Define `
+ ((int64Pow:word64 -> num -> word64)= (gen_pow(((n2w 1) : word64)) (\ i1 i2. ((word_mul i1 i2) : word64))))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_int64_dict:(word64)NumPow_class)= (<|
+
+ numPow_method := int64Pow|>))`;
+
+
+(*val int64Div : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int64_dict:(word64)NumIntegerDivision_class)= (<|
+
+ div_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int64_dict:(word64)NumDivision_class)= (<|
+
+ numDivision_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`;
+
+
+(*val int64Mod : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int64_dict:(word64)NumRemainder_class)= (<|
+
+ mod_method := (\ i1 i2. ((word_mod i1 i2) : word64))|>))`;
+
+
+(*val int64Min : int64 -> int64 -> int64*)
+
+(*val int64Max : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int64_dict:(word64)OrdMaxMin_class)= (<|
+
+ max_method := word_smax;
+
+ min_method := word_smin|>))`;
+
+
+
+(* ----------------------- *)
+(* integer *)
+(* ----------------------- *)
+
+(*val integerFromNumeral : numeral -> integer*)
+
+(*val integerFromNat : nat -> integer*) (* TODO: check *)
+
+(*val integerEq : integer -> integer -> bool*)
+
+(*val integerLess : integer -> integer -> bool*)
+(*val integerLessEqual : integer -> integer -> bool*)
+(*val integerGreater : integer -> integer -> bool*)
+(*val integerGreaterEqual : integer -> integer -> bool*)
+
+(*val integerCompare : integer -> integer -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_integer_dict:(int)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val integerNegate : integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_integer_dict:(int)NumNegate_class)= (<|
+
+ numNegate_method := (\ i. ~ i)|>))`;
+
+
+(*val integerAbs : integer -> integer*) (* TODO: check *)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_integer_dict:(int)NumAbs_class)= (<|
+
+ abs_method := ABS|>))`;
+
+
+(*val integerAdd : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_integer_dict:(int)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val integerMinus : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_integer_dict:(int)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val integerSucc : integer -> integer*)
+val _ = Define `
+((instance_Num_NumSucc_Num_integer_dict:(int)NumSucc_class)= (<|
+
+ succ_method := (\ n. n +( 1 : int))|>))`;
+
+
+(*val integerPred : integer -> integer*)
+val _ = Define `
+((instance_Num_NumPred_Num_integer_dict:(int)NumPred_class)= (<|
+
+ pred_method := (\ n. n -( 1 : int))|>))`;
+
+
+(*val integerMult : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_integer_dict:(int)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+
+(*val integerPow : integer -> nat -> integer*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_integer_dict:(int)NumPow_class)= (<|
+
+ numPow_method := ( ** )|>))`;
+
+
+(*val integerDiv : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_integer_dict:(int)NumIntegerDivision_class)= (<|
+
+ div_method := (/)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_integer_dict:(int)NumDivision_class)= (<|
+
+ numDivision_method := (/)|>))`;
+
+
+(*val integerMod : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_integer_dict:(int)NumRemainder_class)= (<|
+
+ mod_method := (%)|>))`;
+
+
+(*val integerMin : integer -> integer -> integer*)
+
+(*val integerMax : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_integer_dict:(int)OrdMaxMin_class)= (<|
+
+ max_method := int_max;
+
+ min_method := int_min|>))`;
+
+
+
+
+(* ----------------------- *)
+(* rational *)
+(* ----------------------- *)
+
+(*val rationalFromNumeral : numeral -> rational*)
+
+(*val rationalFromInt : int -> rational*)
+
+(*val rationalFromInteger : integer -> rational*)
+
+(*val rationalEq : rational -> rational -> bool*)
+
+(*val rationalLess : rational -> rational -> bool*)
+(*val rationalLessEqual : rational -> rational -> bool*)
+(*val rationalGreater : rational -> rational -> bool*)
+(*val rationalGreaterEqual : rational -> rational -> bool*)
+
+(*val rationalCompare : rational -> rational -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_rational_dict:(rat)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val rationalAdd : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_rational_dict:(rat)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val rationalMinus : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_rational_dict:(rat)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val rationalNegate : rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_rational_dict:(rat)NumNegate_class)= (<|
+
+ numNegate_method := (\ n. ( 0 : rat) - n)|>))`;
+
+
+(*val rationalAbs : rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_rational_dict:(rat)NumAbs_class)= (<|
+
+ abs_method := (\ n. (if n >( 0 : rat) then n else( 0 : rat) - n))|>))`;
+
+
+(*val rationalSucc : rational -> rational*)
+val _ = Define `
+((instance_Num_NumSucc_Num_rational_dict:(rat)NumSucc_class)= (<|
+
+ succ_method := (\ n. n +( 1 : rat))|>))`;
+
+
+(*val rationalPred : rational -> rational*)
+val _ = Define `
+((instance_Num_NumPred_Num_rational_dict:(rat)NumPred_class)= (<|
+
+ pred_method := (\ n. n -( 1 : rat))|>))`;
+
+
+(*val rationalMult : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_rational_dict:(rat)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+(*val rationalDiv : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumDivision_Num_rational_dict:(rat)NumDivision_class)= (<|
+
+ numDivision_method := (/)|>))`;
+
+
+(*val rationalFromFrac : int -> int -> rational*)
+(*let rationalFromFrac n d= (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)*)
+
+(*val rationalNumerator : rational -> integer*) (* TODO: test *)
+
+(*val rationalDenominator : rational -> integer*) (* TODO: test *)
+
+(*val rationalPowInteger : rational -> integer -> rational*)
+ val rationalPowInteger_defn = Hol_defn "rationalPowInteger" `
+ ((rationalPowInteger:rat -> int -> rat) b e=
+ (if e =( 0 : int) then( 1 : rat) else
+ if e >( 0 : int) then rationalPowInteger b (e -( 1 : int)) * b else
+ rationalPowInteger b (e +( 1 : int)) / b))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn rationalPowInteger_defn;
+
+(*val rationalPowNat : rational -> nat -> rational*)
+val _ = Define `
+ ((rationalPowNat:rat -> num -> rat) r e= (rationalPowInteger r (int_of_num e)))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_rational_dict:(rat)NumPow_class)= (<|
+
+ numPow_method := rationalPowNat|>))`;
+
+
+(*val rationalMin : rational -> rational -> rational*)
+
+(*val rationalMax : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_rational_dict:(rat)OrdMaxMin_class)= (<|
+
+ max_method := (maxByLessEqual (<=));
+
+ min_method := (minByLessEqual (<=))|>))`;
+
+
+
+
+(* ----------------------- *)
+(* real *)
+(* ----------------------- *)
+
+(*val realFromNumeral : numeral -> real*)
+
+(*val realFromInteger : integer -> real*)
+
+(*val realEq : real -> real -> bool*)
+
+(*val realLess : real -> real -> bool*)
+(*val realLessEqual : real -> real -> bool*)
+(*val realGreater : real -> real -> bool*)
+(*val realGreaterEqual : real -> real -> bool*)
+
+(*val realCompare : real -> real -> ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_real_dict:(real)Ord_class)= (<|
+
+ compare_method := (genericCompare (<) (=));
+
+ isLess_method := (<);
+
+ isLessEqual_method := (<=);
+
+ isGreater_method := (>);
+
+ isGreaterEqual_method := (>=)|>))`;
+
+
+(*val realAdd : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_real_dict:(real)NumAdd_class)= (<|
+
+ numAdd_method := (+)|>))`;
+
+
+(*val realMinus : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_real_dict:(real)NumMinus_class)= (<|
+
+ numMinus_method := (-)|>))`;
+
+
+(*val realNegate : real -> real*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_real_dict:(real)NumNegate_class)= (<|
+
+ numNegate_method := (\ n. (real_of_num 0) - n)|>))`;
+
+
+(*val realAbs : real -> real*)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_real_dict:(real)NumAbs_class)= (<|
+
+ abs_method := (\ n. (if n >(real_of_num 0) then n else(real_of_num 0) - n))|>))`;
+
+
+(*val realSucc : real -> real*)
+val _ = Define `
+((instance_Num_NumSucc_Num_real_dict:(real)NumSucc_class)= (<|
+
+ succ_method := (\ n. n +(real_of_num 1))|>))`;
+
+
+(*val realPred : real -> real*)
+val _ = Define `
+((instance_Num_NumPred_Num_real_dict:(real)NumPred_class)= (<|
+
+ pred_method := (\ n. n -(real_of_num 1))|>))`;
+
+
+(*val realMult : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_real_dict:(real)NumMult_class)= (<|
+
+ numMult_method := ( * )|>))`;
+
+
+(*val realDiv : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumDivision_Num_real_dict:(real)NumDivision_class)= (<|
+
+ numDivision_method := (/)|>))`;
+
+
+(*val realFromFrac : integer -> integer -> real*)
+val _ = Define `
+ ((realFromFrac:int -> int -> real) n d= (((real_of_int n)) / ((real_of_int d))))`;
+
+
+(*val realPowInteger : real -> integer -> real*)
+ val realPowInteger_defn = Hol_defn "realPowInteger" `
+ ((realPowInteger:real -> int -> real) b e=
+ (if e =( 0 : int) then(real_of_num 1) else
+ if e >( 0 : int) then realPowInteger b (e -( 1 : int)) * b else
+ realPowInteger b (e +( 1 : int)) / b))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn realPowInteger_defn;
+
+(*val realPowNat : real -> nat -> real*)
+(*let realPowNat r e= realPowInteger r (integerFromNat e)*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_real_dict:(real)NumPow_class)= (<|
+
+ numPow_method := (pow)|>))`;
+
+
+(*val realSqrt : real -> real*)
+
+(*val realMin : real -> real -> real*)
+
+(*val realMax : real -> real -> real*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_real_dict:(real)OrdMaxMin_class)= (<|
+
+ max_method := max;
+
+ min_method := min|>))`;
+
+
+(*val realCeiling : real -> integer*)
+
+(*val realFloor : real -> integer*)
+
+
+(*val integerSqrt : integer -> integer*)
+val _ = Define `
+ ((integerSqrt:int -> int) i= (flr (sqrt ((real_of_int i)))))`;
+
+
+(* ========================================================================== *)
+(* Translation between number types *)
+(* ========================================================================== *)
+
+(******************)
+(* integerFrom... *)
+(******************)
+
+(*val integerFromInt : int -> integer*)
+
+(*val integerFromNatural : natural -> integer*)
+
+
+(*val integerFromInt32 : int32 -> integer*)
+
+
+(*val integerFromInt64 : int64 -> integer*)
+
+
+(******************)
+(* naturalFrom... *)
+(******************)
+
+(*val naturalFromNat : nat -> natural*)
+
+(*val naturalFromInteger : integer -> natural*)
+
+
+(******************)
+(* intFrom ... *)
+(******************)
+
+(*val intFromInteger : integer -> int*)
+
+(*val intFromNat : nat -> int*)
+
+
+(******************)
+(* natFrom ... *)
+(******************)
+
+(*val natFromNatural : natural -> nat*)
+
+(*val natFromInt : int -> nat*)
+
+
+(******************)
+(* int32From ... *)
+(******************)
+
+(*val int32FromNat : nat -> int32*)
+
+(*val int32FromNatural : natural -> int32*)
+
+(*val int32FromInteger : integer -> int32*)
+val _ = Define `
+ ((int32FromInteger:int -> word32) i= (
+ let abs_int32 = (((n2w (Num (ABS i))) : word32)) in
+ if (i <( 0 : int)) then (((- abs_int32) : word32)) else abs_int32
+))`;
+
+
+(*val int32FromInt : int -> int32*)
+val _ = Define `
+ ((int32FromInt:int -> word32) i= (int32FromInteger ( i)))`;
+
+
+
+(*val int32FromInt64 : int64 -> int32*)
+(*let int32FromInt64 i= int32FromInteger (integerFromInt64 i)*)
+
+
+
+
+(******************)
+(* int64From ... *)
+(******************)
+
+(*val int64FromNat : nat -> int64*)
+
+(*val int64FromNatural : natural -> int64*)
+
+(*val int64FromInteger : integer -> int64*)
+val _ = Define `
+ ((int64FromInteger:int -> word64) i= (
+ let abs_int64 = (((n2w (Num (ABS i))) : word64)) in
+ if (i <( 0 : int)) then (((- abs_int64) : word64)) else abs_int64
+))`;
+
+
+(*val int64FromInt : int -> int64*)
+val _ = Define `
+ ((int64FromInt:int -> word64) i= (int64FromInteger ( i)))`;
+
+
+
+(*val int64FromInt32 : int32 -> int64*)
+(*let int64FromInt32 i= int64FromInteger (integerFromInt32 i)*)
+
+
+(******************)
+(* what's missing *)
+(******************)
+
+(*val naturalFromInt : int -> natural*)
+(*val naturalFromInt32 : int32 -> natural*)
+(*val naturalFromInt64 : int64 -> natural*)
+
+
+(*val intFromNatural : natural -> int*)
+(*val intFromInt32 : int32 -> int*)
+(*val intFromInt64 : int64 -> int*)
+
+(*val natFromInteger : integer -> nat*)
+(*val natFromInt32 : int32 -> nat*)
+(*val natFromInt64 : int64 -> nat*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_num_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_num_extraScript.sml
new file mode 100644
index 0000000..eb97041
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_num_extraScript.sml
@@ -0,0 +1,73 @@
+(*Generated by Lem from num_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_numTheory lem_basic_classesTheory lem_assert_extraTheory lem_stringTheory ASCIInumbersTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_num_extra"
+
+(* **************************************************** *)
+(* *)
+(* A library of additional functions on numbers *)
+(* *)
+(* **************************************************** *)
+
+(*open import Basic_classes*)
+(*open import Num*)
+(*open import String*)
+(*open import Assert_extra*)
+
+(*open import {hol} `ASCIInumbersTheory`*)
+
+(*val naturalOfString : string -> natural*)
+
+(*val integerOfString : string -> integer*)
+
+(*val integerOfChar : char -> integer*)
+
+val _ = Define `
+ ((integerOfChar:char -> int)=
+ (\x . (case x of
+ #"0" =>( 0 : int)
+ | #"1" =>( 1 : int)
+ | #"2" =>( 2 : int)
+ | #"3" =>( 3 : int)
+ | #"4" =>( 4 : int)
+ | #"5" =>( 5 : int)
+ | #"6" =>( 6 : int)
+ | #"7" =>( 7 : int)
+ | #"8" =>( 8 : int)
+ | #"9" =>( 9 : int)
+ | _ => failwith "integerOfChar: unexpected character"
+ )))`;
+
+
+(*val integerOfStringHelper : list char -> integer*)
+
+ val integerOfStringHelper_defn = Defn.Hol_multi_defns `
+ ((integerOfStringHelper:(char)list -> int) (d :: ds)= (integerOfChar d + (( 10 : int) * integerOfStringHelper ds)))
+/\ ((integerOfStringHelper:(char)list -> int) ([])= (( 0 : int)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) integerOfStringHelper_defn;
+
+val _ = Define `
+ ((integerOfString:string -> int) s=
+ (list_CASE s (int_of_num (toNum s))
+ (\c s0. (case(c,s0) of
+ ( #"-",_) => ~ (int_of_num (toNum s0))
+ | (_,_) => int_of_num (toNum s)
+ ))))`;
+
+
+(* Truncation integer division (round toward zero) *)
+(*val integerDiv_t: integer -> integer -> integer*)
+
+(* Truncation modulo *)
+(*val integerRem_t: integer -> integer -> integer*)
+
+(* Flooring modulo *)
+(*val integerRem_f: integer -> integer -> integer*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_pervasivesScript.sml b/prover_snapshots/hol4/lib/lem/lem_pervasivesScript.sml
new file mode 100644
index 0000000..34c8b4a
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_pervasivesScript.sml
@@ -0,0 +1,18 @@
+(*Generated by Lem from pervasives.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_basic_classesTheory lem_boolTheory lem_tupleTheory lem_maybeTheory lem_eitherTheory lem_functionTheory lem_numTheory lem_mapTheory lem_setTheory lem_listTheory lem_stringTheory lem_wordTheory lem_showTheory lem_sortingTheory lem_relationTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_pervasives"
+
+
+
+(*include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show*)
+
+(*import Sorting Relation*)
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_pervasives_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_pervasives_extraScript.sml
new file mode 100644
index 0000000..33ccd62
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_pervasives_extraScript.sml
@@ -0,0 +1,16 @@
+(*Generated by Lem from pervasives_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_function_extraTheory lem_maybe_extraTheory lem_map_extraTheory lem_num_extraTheory lem_set_extraTheory lem_set_helpersTheory lem_list_extraTheory lem_string_extraTheory lem_assert_extraTheory lem_show_extraTheory lem_machine_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_pervasives_extra"
+
+
+
+(*include import Pervasives*)
+(*include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_relationScript.sml b/prover_snapshots/hol4/lib/lem/lem_relationScript.sml
new file mode 100644
index 0000000..7d019b2
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_relationScript.sml
@@ -0,0 +1,448 @@
+(*Generated by Lem from relation.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_tupleTheory lem_setTheory lem_numTheory set_relationTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_relation"
+
+
+
+(*open import Bool Basic_classes Tuple Set Num*)
+(*open import {hol} `set_relationTheory`*)
+
+(* ========================================================================== *)
+(* The type of relations *)
+(* ========================================================================== *)
+
+val _ = type_abbrev((* ( 'a, 'b) *) "rel_pred" , ``: 'a -> 'b -> bool``);
+val _ = type_abbrev((* ( 'a, 'b) *) "rel_set" , ``: ('a # 'b) set``);
+
+(* Binary relations are usually represented as either
+ sets of pairs (rel_set) or as curried functions (rel_pred).
+
+ The choice depends on taste and the backend. Lem should not take a
+ decision, but supports both representations. There is an abstract type
+ pred, which can be converted to both representations. The representation
+ of pred itself then depends on the backend. However, for the time beeing,
+ let's implement relations as sets to get them working more quickly. *)
+
+val _ = type_abbrev((* ( 'a, 'b) *) "rel" , ``: ('a, 'b) rel_set``);
+
+(*val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b*)
+(*val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b*)
+
+(*val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool*)
+val _ = Define `
+ ((relEq:('a#'b)set ->('a#'b)set -> bool) r1 r2= (r1 = r2))`;
+
+
+(*val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b*)
+(*val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b*)
+
+(*let relToPred r= (fun x y -> (x, y) IN relToSet r)*)
+val _ = Define `
+ ((relFromPred:'a set -> 'b set ->('a -> 'b -> bool) ->('a#'b)set) xs ys p= (SET_FILTER (\ (x,y) . p x y) (xs CROSS ys)))`;
+
+
+
+(* ========================================================================== *)
+(* Basic Operations *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* membership test *)
+(* ----------------------- *)
+
+(*val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool*)
+
+
+(* ----------------------- *)
+(* empty relation *)
+(* ----------------------- *)
+
+(*val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b*)
+
+(* ----------------------- *)
+(* Insertion *)
+(* ----------------------- *)
+
+(*val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b*)
+
+
+(* ----------------------- *)
+(* Identity relation *)
+(* ----------------------- *)
+
+(*val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a*)
+val _ = Define `
+ ((relIdOn:'a set ->('a#'a)set) s= (relFromPred s s (=)))`;
+
+
+(*val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a*)
+val _ = Define `
+ ((relId:('a#'a)set)= ({(x, x) | x | T}))`;
+
+
+(* ----------------------- *)
+(* relation union *)
+(* ----------------------- *)
+
+(*val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*)
+
+(* ----------------------- *)
+(* relation intersection *)
+(* ----------------------- *)
+
+(*val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*)
+
+(* ----------------------- *)
+(* Relation Composition *)
+(* ----------------------- *)
+
+(*val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c*)
+(*let relComp r1 r2= relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}*)
+
+(* ----------------------- *)
+(* restrict *)
+(* ----------------------- *)
+
+(*val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*)
+(*let relRestrict r s= relFromSet ({ (a, b) | forall (a IN s) (b IN s) | inRel a b r })*)
+
+
+(* ----------------------- *)
+(* Converse *)
+(* ----------------------- *)
+
+(*val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a*)
+val _ = Define `
+ ((lem_converse:('a#'b)set ->('b#'a)set) r= (IMAGE SWAP (r)))`;
+
+
+
+(* ----------------------- *)
+(* domain *)
+(* ----------------------- *)
+
+(*val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a*)
+(*let relDomain r= Set.map (fun x -> fst x) (relToSet r)*)
+
+(* ----------------------- *)
+(* range *)
+(* ----------------------- *)
+
+(*val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b*)
+(*let relRange r= Set.map (fun x -> snd x) (relToSet r)*)
+
+
+(* ----------------------- *)
+(* field / definedOn *)
+(* *)
+(* avoid the keyword field *)
+(* ----------------------- *)
+
+(*val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a*)
+
+(* ----------------------- *)
+(* relOver *)
+(* *)
+(* avoid the keyword field *)
+(* ----------------------- *)
+
+(*val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((rel_over:('a#'a)set -> 'a set -> bool) r s= ((((domain r) UNION (range r))) SUBSET s))`;
+
+
+
+(* ----------------------- *)
+(* apply a relation *)
+(* ----------------------- *)
+
+(* Given a relation r and a set s, relApply r s applies s to r, i.e.
+ it returns the set of all value reachable via r from a value in s.
+ This operation can be seen as a generalisation of function application. *)
+
+(*val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b*)
+val _ = Define `
+ ((rapply:('a#'b)set -> 'a set -> 'b set) r s=
+ ({ y | x, y | ((x, y) IN (r)) /\ (x IN s) }))`;
+
+
+
+(* ========================================================================== *)
+(* Properties *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* subrel *)
+(* ----------------------- *)
+
+(*val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool*)
+
+(* ----------------------- *)
+(* reflexivity *)
+(* ----------------------- *)
+
+(*val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_reflexive_on:('a#'a)set -> 'a set -> bool) r s= (! (e :: s). (e, e) IN r))`;
+
+
+(*val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_reflexive:('a#'a)set -> bool) r= (! e. (e, e) IN r))`;
+
+
+
+(* ----------------------- *)
+(* irreflexivity *)
+(* ----------------------- *)
+
+(*val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+(*let isIrreflexiveOn r s= (forall (e IN s). not (inRel e e r))*)
+
+(*val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_irreflexive:('a#'a)set -> bool) r= (! ((e1, e2) :: (r)). ~ (e1 = e2)))`;
+
+
+
+(* ----------------------- *)
+(* symmetry *)
+(* ----------------------- *)
+
+(*val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_symmetric_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> ((e2, e1) IN r)))`;
+
+
+(*val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_symmetric:('a#'a)set -> bool) r= (! ((e1, e2) :: r). (e2, e1) IN r))`;
+
+
+
+(* ----------------------- *)
+(* antisymmetry *)
+(* ----------------------- *)
+
+(*val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_antisymmetric_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> (((e2, e1) IN r) ==> (e1 = e2))))`;
+
+
+(*val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let isAntisymmetric r= (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))*)
+
+
+(* ----------------------- *)
+(* transitivity *)
+(* ----------------------- *)
+
+(*val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_transitive_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s) (e3 :: s). ((e1, e2) IN r) ==> (((e2, e3) IN r) ==> ((e1, e3) IN r))))`;
+
+
+(*val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let isTransitive r= (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)*)
+
+(* ----------------------- *)
+(* total *)
+(* ----------------------- *)
+
+(*val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e2, e1) IN r)))`;
+
+
+
+(*val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_total:('a#'a)set -> bool) r= (! e1 e2. ((e1, e2) IN r) \/ ((e2, e1) IN r)))`;
+
+
+(*val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_trichotomous_on:('a#'a)set -> 'a set -> bool) r s= (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`;
+
+
+(*val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_trichotomous:('a#'a)set -> bool) r= (! e1 e2. ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`;
+
+
+
+(* ----------------------- *)
+(* is_single_valued *)
+(* ----------------------- *)
+
+(*val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool*)
+val _ = Define `
+ ((lem_is_single_valued:('a#'b)set -> bool) r= (! ((e1, e2a) :: r) (e2b :: rapply r {e1}). e2a = e2b))`;
+
+
+
+(* ----------------------- *)
+(* equivalence relation *)
+(* ----------------------- *)
+
+(*val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_equivalence_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_is_symmetric_on r s /\ lem_transitive_on r s))`;
+
+
+
+(*val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_equivalence:('a#'a)set -> bool) r= (lem_is_reflexive r /\ lem_is_symmetric r /\ transitive r))`;
+
+
+
+(* ----------------------- *)
+(* well founded *)
+(* ----------------------- *)
+
+(*val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let ~{ocaml;coq} isWellFounded r= (forall P. (forall x. (forall y. inRel y x r --> P x) --> P x) --> (forall x. P x))*)
+
+
+(* ========================================================================== *)
+(* Orders *)
+(* ========================================================================== *)
+
+
+(* ----------------------- *)
+(* pre- or quasiorders *)
+(* ----------------------- *)
+
+(*val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_preorder_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_transitive_on r s))`;
+
+
+(*val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_preorder:('a#'a)set -> bool) r= (lem_is_reflexive r /\ transitive r))`;
+
+
+
+(* ----------------------- *)
+(* partial orders *)
+(* ----------------------- *)
+
+(*val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_partial_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_reflexive_on r s /\ lem_transitive_on r s /\ lem_is_antisymmetric_on r s))`;
+
+
+
+(*val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_partial_order_on:('a#'a)set -> 'a set -> bool) r s= (irreflexive r s /\ lem_transitive_on r s))`;
+
+
+
+(*val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_partial_order:('a#'a)set -> bool) r= (lem_is_irreflexive r /\ transitive r))`;
+
+
+(*val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_partial_order:('a#'a)set -> bool) r= (lem_is_reflexive r /\ transitive r /\ antisym r))`;
+
+
+(* ----------------------- *)
+(* total / linear orders *)
+(* ----------------------- *)
+
+(*val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_partial_order_on r s /\ lem_is_total_on r s))`;
+
+
+(*val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_total_order_on:('a#'a)set -> 'a set -> bool) r s= (lem_is_strict_partial_order_on r s /\ lem_is_trichotomous_on r s))`;
+
+
+(*val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_order:('a#'a)set -> bool) r= (lem_is_partial_order r /\ lem_is_total r))`;
+
+
+(*val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_total_order:('a#'a)set -> bool) r= (lem_is_strict_partial_order r /\ lem_is_trichotomous r))`;
+
+
+
+
+(* ========================================================================== *)
+(* closures *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* transitive closure *)
+(* ----------------------- *)
+
+(*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+(*val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*)
+(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> ordering) -> rel 'a 'a -> rel 'a 'a*)
+
+
+(* ----------------------- *)
+(* transitive closure step *)
+(* ----------------------- *)
+
+(*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*)
+
+val _ = Define `
+ ((tc_insert:'a -> 'a ->('a#'a)set ->('a#'a)set) x y r=
+ ((((((x,y) INSERT (r)))) UNION ((((({(x, z) | z |
+ (z IN range r) /\ ((y, z) IN r)})) UNION (({(z, y) | z |
+ (z IN domain r) /\ ((z, x) IN r)}))))))))`;
+
+
+
+(* ========================================================================== *)
+(* reflexive closure *)
+(* ========================================================================== *)
+
+(*val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*)
+val _ = Define `
+ ((reflexive_transitive_closure_on:('a#'a)set -> 'a set ->('a#'a)set) r s= (tc (((r) UNION ((relIdOn s))))))`;
+
+
+
+(*val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+val _ = Define `
+ ((reflexiveTransitiveClosure:('a#'a)set ->('a#'a)set) r= (tc (((r) UNION (relId)))))`;
+
+
+
+
+(* ========================================================================== *)
+(* inverse of closures *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* without transitve edges *)
+(* ----------------------- *)
+
+(*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+val _ = Define `
+ ((withoutTransitiveEdges:('a#'a)set ->('a#'a)set) r=
+ (let tc1 = (tc r) in
+ {(a, c) | a, c
+ | ((a, c) IN r) /\
+ (! (b :: range r).
+ ((a <> b) /\ (b <> c)) ==> ~ (((a, b) IN tc1) /\ ((b, c) IN tc1)))}))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_setScript.sml b/prover_snapshots/hol4/lib/lem/lem_setScript.sml
new file mode 100644
index 0000000..c03aec5
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_setScript.sml
@@ -0,0 +1,317 @@
+(*Generated by Lem from set.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_set_helpersTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set"
+
+(******************************************************************************)
+(* A library for sets *)
+(* *)
+(* It mainly follows the Haskell Set-library *)
+(******************************************************************************)
+
+(* Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets.
+ OCaml and Haskell both represent sets by some kind of balancing trees. This means
+ that sets are finite and an order on the element type is required.
+ Such sets are constructed by simple, executable operations like inserting or
+ deleting elements, union, intersection, filtering etc.
+
+ On the other hand, we want to use sets for specifications. This leads often
+ infinite sets, which are specificied in complicated, perhaps even undecidable
+ ways.
+
+ The set library in this file, chooses the first approach. It describes
+ *finite* sets with an underlying order. Infinite sets should in the medium
+ run be represented by a separate type. Since this would require some significant
+ changes to Lem, for the moment also infinite sets are represented using this
+ class. However, a run-time exception might occour when using these sets.
+ This problem needs adressing in the future. *)
+
+
+(* ========================================================================== *)
+(* Header *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num List Set_helpers*)
+
+(* DPM: sets currently implemented as lists due to mismatch between Coq type
+ * class hierarchy and the hierarchy implemented in Lem.
+ *)
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {hol} `lemTheory`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ----------------------- *)
+(* Equality check *)
+(* ----------------------- *)
+
+(*val setEqualBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*)
+
+(*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+
+(* ----------------------- *)
+(* Empty set *)
+(* ----------------------- *)
+
+(*val empty : forall 'a. SetType 'a => set 'a*)
+(*val emptyBy : forall 'a. ('a -> 'a -> ordering) -> set 'a*)
+
+(* ----------------------- *)
+(* any / all *)
+(* ----------------------- *)
+
+(*val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*)
+
+(*val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*)
+
+
+(* ----------------------- *)
+(* (IN) *)
+(* ----------------------- *)
+
+(*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*)
+(*val memberBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a -> bool*)
+
+(* ----------------------- *)
+(* not (IN) *)
+(* ----------------------- *)
+
+(*val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool*)
+
+
+
+(* ----------------------- *)
+(* Emptyness check *)
+(* ----------------------- *)
+
+(*val null : forall 'a. SetType 'a => set 'a -> bool*)
+
+
+(* ------------------------ *)
+(* singleton *)
+(* ------------------------ *)
+
+(*val singletonBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a*)
+(*val singleton : forall 'a. SetType 'a => 'a -> set 'a*)
+
+
+(* ----------------------- *)
+(* size *)
+(* ----------------------- *)
+
+(*val size : forall 'a. SetType 'a => set 'a -> nat*)
+
+
+(* ----------------------------*)
+(* setting up pattern matching *)
+(* --------------------------- *)
+
+(*val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b*)
+
+
+(* ------------------------ *)
+(* union *)
+(* ------------------------ *)
+
+(*val unionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*)
+(*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+
+(* ----------------------- *)
+(* insert *)
+(* ----------------------- *)
+
+(*val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a*)
+
+(* ----------------------- *)
+(* filter *)
+(* ----------------------- *)
+
+(*val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a*)
+(*let filter P s= {e | forall (e IN s) | P e}*)
+
+
+(* ----------------------- *)
+(* partition *)
+(* ----------------------- *)
+
+(*val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a*)
+val _ = Define `
+ ((SET_PARTITION:('a -> bool) -> 'a set -> 'a set#'a set) P s= (SET_FILTER P s, SET_FILTER (\ e . ~ (P e)) s))`;
+
+
+
+(* ----------------------- *)
+(* split *)
+(* ----------------------- *)
+
+(*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*)
+val _ = Define `
+ ((SET_SPLIT:'a Ord_class -> 'a -> 'a set -> 'a set#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER (
+ dict_Basic_classes_Ord_a.isGreater_method p) s, SET_FILTER (dict_Basic_classes_Ord_a.isLess_method p) s))`;
+
+
+(*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*)
+val _ = Define `
+ ((splitMember:'a Ord_class -> 'a -> 'a set -> 'a set#bool#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER (
+ dict_Basic_classes_Ord_a.isLess_method p) s, (p IN s), SET_FILTER (
+ dict_Basic_classes_Ord_a.isGreater_method p) s))`;
+
+
+(* ------------------------ *)
+(* subset and proper subset *)
+(* ------------------------ *)
+
+(*val isSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*)
+(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*)
+
+(*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+(*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+
+
+(* ------------------------ *)
+(* delete *)
+(* ------------------------ *)
+
+(*val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a*)
+(*val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a*)
+
+
+(* ------------------------ *)
+(* bigunion *)
+(* ------------------------ *)
+
+(*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*)
+(*val bigunionBy : forall 'a. ('a -> 'a -> ordering) -> set (set 'a) -> set 'a*)
+
+(*let bigunion bs= {x | forall (s IN bs) (x IN s) | true}*)
+
+(* ------------------------ *)
+(* big intersection *)
+(* ------------------------ *)
+
+(* Shaked's addition, for which he is now forever responsible as a de facto
+ * Lem maintainer...
+ *)
+(*val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a*)
+val _ = Define `
+ ((bigintersection:('a set)set -> 'a set) bs=
+ ({x | x | (x IN (BIGUNION bs)) /\ (! (s :: bs). x IN s)}))`;
+
+
+(* ------------------------ *)
+(* difference *)
+(* ------------------------ *)
+
+(*val differenceBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*)
+(*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+
+(* ------------------------ *)
+(* intersection *)
+(* ------------------------ *)
+
+(*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+(*val intersectionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*)
+
+
+(* ------------------------ *)
+(* map *)
+(* ------------------------ *)
+
+(*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *)
+(*let map f s= { f e | forall (e IN s) | true }*)
+
+(*val mapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> 'b) -> set 'a -> set 'b*)
+
+
+(* ------------------------ *)
+(* bigunionMap *)
+(* ------------------------ *)
+
+(* In order to avoid providing an comparison function for sets of sets,
+ it might be better to combine bigunion and map sometimes into a single operation. *)
+
+(*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*)
+(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> set 'b) -> set 'a -> set 'b*)
+
+(* ------------------------ *)
+(* mapMaybe and fromMaybe *)
+(* ------------------------ *)
+
+(* If the mapping function returns Just x, x is added to the result
+ set. If it returns Nothing, no element is added. *)
+
+(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> maybe 'b) -> set 'a -> set 'b*)
+val _ = Define `
+ ((setMapMaybe:('a -> 'b option) -> 'a set -> 'b set) f s=
+ (BIGUNION (IMAGE (\ x . (case f x of
+ SOME y => {y}
+ | NONE => EMPTY
+ )) s)))`;
+
+
+(*val removeMaybe : forall 'a. SetType 'a => set (maybe 'a) -> set 'a*)
+val _ = Define `
+ ((removeMaybe:('a option)set -> 'a set) s= (setMapMaybe (\ x . x) s))`;
+
+
+(* ------------------------ *)
+(* min and max *)
+(* ------------------------ *)
+
+(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*)
+(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*)
+
+(* ------------------------ *)
+(* fromList *)
+(* ------------------------ *)
+
+(*val fromList : forall 'a. SetType 'a => list 'a -> set 'a*) (* before from_list *)
+(*val fromListBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> set 'a*)
+
+
+(* ------------------------ *)
+(* Sigma *)
+(* ------------------------ *)
+
+(*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*)
+(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*)
+
+(*let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }*)
+
+
+(* ------------------------ *)
+(* cross product *)
+(* ------------------------ *)
+
+(*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*)
+(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> set 'b -> set ('a * 'b)*)
+
+(*let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*)
+
+
+(* ------------------------ *)
+(* finite *)
+(* ------------------------ *)
+
+(*val finite : forall 'a. SetType 'a => set 'a -> bool*)
+
+
+(* ----------------------------*)
+(* fixed point *)
+(* --------------------------- *)
+
+(*val leastFixedPoint : forall 'a. SetType 'a
+ => nat -> (set 'a -> set 'a) -> set 'a -> set 'a*)
+ val leastFixedPoint_defn = Defn.Hol_multi_defns `
+ ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) 0 f x= x)
+/\ ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) ((SUC bound')) f x= (let fx = (f x) in
+ if fx SUBSET x then x
+ else leastFixedPoint bound' f (fx UNION x)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) leastFixedPoint_defn;
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_set_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_set_extraScript.sml
new file mode 100644
index 0000000..1e51c14
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_set_extraScript.sml
@@ -0,0 +1,118 @@
+(*Generated by Lem from set_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_sortingTheory lem_setTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set_extra"
+
+(******************************************************************************)
+(* A library for sets *)
+(* *)
+(* It mainly follows the Haskell Set-library *)
+(******************************************************************************)
+
+(* ========================================================================== *)
+(* Header *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num List Sorting Set*)
+
+
+(* ----------------------------*)
+(* set choose (be careful !) *)
+(* --------------------------- *)
+
+(*val choose : forall 'a. SetType 'a => set 'a -> 'a*)
+
+(* ------------------------ *)
+(* chooseAndSplit *)
+(* ------------------------ *)
+(* The idea here is to provide a simple primitive that Lem code can use
+ * to perform its own custom searches within the set -- likely using a
+ * search criterion related to the element ordering, but not necessarily).
+ * For example, sometimes we don't necessarily want to search for a specific
+ * element, but want to search for elements greater than or less than some other.
+ * Someties we'd like to use "split" but don't know a good value to "split" at.
+ * This function lets the set implementation decide that value.
+ *
+ * The contract of chooseAndSplit is simply to select an element nondeterministically
+ * and return that element, together with the subsets of elements less than and
+ * greater than it. In this way, we can recursively traverse the set with any
+ * search criterion, and we avoid baking in the tree representation (although that
+ * is the obvious choice).
+ *)
+(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> maybe (set 'a * 'a * set 'a)*)
+val _ = Define `
+ ((chooseAndSplit:'a Ord_class -> 'a set ->('a set#'a#'a set)option)dict_Basic_classes_Ord_a s=
+ (if s = EMPTY then
+ NONE
+ else
+ let element1 = (CHOICE s) in
+ let (lt, gt) = (lem_set$SET_SPLIT
+ dict_Basic_classes_Ord_a element1 s) in
+ SOME (lt, element1, gt)))`;
+
+
+(* ----------------------------*)
+(* universal set *)
+(* --------------------------- *)
+
+(*val universal : forall 'a. SetType 'a => set 'a*)
+
+
+(* ----------------------------*)
+(* toList *)
+(* --------------------------- *)
+
+(*val toList : forall 'a. SetType 'a => set 'a -> list 'a*)
+
+
+(* ----------------------------*)
+(* toOrderedList *)
+(* --------------------------- *)
+
+(* "toOrderedList" returns a sorted list. Therefore the result is (given a suitable order) deterministic.
+ Therefore, it is much preferred to "toList". However, it still is only defined for finite sets. So, please
+ use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations
+ and then transforming back to sets. *)
+
+(*val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a*)
+
+(*val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a*)
+
+(* ----------------------- *)
+(* compare *)
+(* ----------------------- *)
+
+(*val setCompareBy: forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> ordering*)
+val _ = Define `
+ ((setCompareBy:('a -> 'a -> ordering) -> 'a set -> 'a set -> ordering) cmp ss ts=
+ (let ss' = (ARB (\ x y . cmp x y = LESS) ss) in
+ let ts' = (ARB (\ x y . cmp x y = LESS) ts) in
+ lexicographic_compare cmp ss' ts'))`;
+
+
+(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> ordering*)
+val _ = Define `
+ ((setCompare:'a Ord_class -> 'a set -> 'a set -> ordering)dict_Basic_classes_Ord_a= (setCompareBy
+ dict_Basic_classes_Ord_a.compare_method))`;
+
+
+(* ----------------------------*)
+(* unbounded fixed point *)
+(* --------------------------- *)
+
+(* Is NOT supported by the coq backend! *)
+(*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*)
+ val leastFixedPointUnbounded_defn = Hol_defn "leastFixedPointUnbounded" `
+ ((leastFixedPointUnbounded:('a set -> 'a set) -> 'a set -> 'a set) f x=
+ (let fx = (f x) in
+ if fx SUBSET x then x
+ else leastFixedPointUnbounded f (fx UNION x)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn leastFixedPointUnbounded_defn;
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_set_helpersScript.sml b/prover_snapshots/hol4/lib/lem/lem_set_helpersScript.sml
new file mode 100644
index 0000000..5ce9f93
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_set_helpersScript.sml
@@ -0,0 +1,47 @@
+(*Generated by Lem from set_helpers.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set_helpers"
+
+(******************************************************************************)
+(* Helper functions for sets *)
+(******************************************************************************)
+
+(* Usually there is a something.lem file containing the main definitions and a
+ something_extra.lem one containing functions that might cause problems for
+ some backends or are just seldomly used.
+
+ For sets the situation is different. folding is not well defined, since it
+ is only sensibly defined for finite sets and the traversal
+ order is underspecified. *)
+
+(* ========================================================================== *)
+(* Header *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num*)
+
+(*open import {coq} `Coq.Lists.List`*)
+
+(* ------------------------ *)
+(* fold *)
+(* ------------------------ *)
+
+(* fold is suspicious, because if given a function, for which
+ the order, in which the arguments are given, matters, its
+ results are undefined. On the other hand, it is very handy to
+ define other - non suspicious functions.
+
+ Moreover, fold is central for OCaml, since it is used to
+ compile set comprehensions *)
+
+(*val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b*)
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_showScript.sml b/prover_snapshots/hol4/lib/lem/lem_showScript.sml
new file mode 100644
index 0000000..eef2c93
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_showScript.sml
@@ -0,0 +1,85 @@
+(*Generated by Lem from show.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_show"
+
+
+
+(*open import String Maybe Num Basic_classes*)
+
+(*open import {hol} `lemTheory`*)
+
+val _ = Hol_datatype `
+(* 'a *) Show_class= <|
+ show_method: 'a -> string
+|>`;
+
+
+val _ = Define `
+((instance_Show_Show_string_dict:(string)Show_class)= (<|
+
+ show_method := (\ s. STRCAT"\"" (STRCAT s "\""))|>))`;
+
+
+(*val stringFromMaybe : forall 'a. ('a -> string) -> maybe 'a -> string*)
+val _ = Define `
+ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX (SOME x)= (STRCAT"Just (" (STRCAT(showX x) ")")))
+/\ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX NONE= "Nothing")`;
+
+
+val _ = Define `
+((instance_Show_Show_Maybe_maybe_dict:'a Show_class ->('a option)Show_class)dict_Show_Show_a= (<|
+
+ show_method := (\ x_opt. stringFromMaybe
+ dict_Show_Show_a.show_method x_opt)|>))`;
+
+
+(*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*)
+ val stringFromListAux_defn = Defn.Hol_multi_defns `
+ ((stringFromListAux:('a -> string) -> 'a list -> string) showX ([])= "")
+/\ ((stringFromListAux:('a -> string) -> 'a list -> string) showX (x::xs')=
+ ((case xs' of
+ [] => showX x
+ | _ => STRCAT(showX x) (STRCAT"; " (stringFromListAux showX xs'))
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) stringFromListAux_defn;
+
+(*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*)
+val _ = Define `
+ ((stringFromList:('a -> string) -> 'a list -> string) showX xs=
+ (STRCAT"[" (STRCAT(stringFromListAux showX xs) "]")))`;
+
+
+val _ = Define `
+((instance_Show_Show_list_dict:'a Show_class ->('a list)Show_class)dict_Show_Show_a= (<|
+
+ show_method := (\ xs. stringFromList
+ dict_Show_Show_a.show_method xs)|>))`;
+
+
+(*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*)
+val _ = Define `
+ ((stringFromPair:('a -> string) ->('b -> string) -> 'a#'b -> string) showX showY (x,y)=
+ (STRCAT"(" (STRCAT(showX x) (STRCAT", " (STRCAT(showY y) ")")))))`;
+
+
+val _ = Define `
+((instance_Show_Show_tup2_dict:'a Show_class -> 'b Show_class ->('a#'b)Show_class)dict_Show_Show_a dict_Show_Show_b= (<|
+
+ show_method := (stringFromPair
+ dict_Show_Show_a.show_method dict_Show_Show_b.show_method)|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_bool_dict:(bool)Show_class)= (<|
+
+ show_method := (\ b. if b then "true" else "false")|>))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_show_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_show_extraScript.sml
new file mode 100644
index 0000000..6be9427
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_show_extraScript.sml
@@ -0,0 +1,67 @@
+(*Generated by Lem from show_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_setTheory lem_relationTheory lem_showTheory lem_set_extraTheory lem_string_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_show_extra"
+
+
+
+(*open import String Maybe Num Basic_classes Set Relation Show*)
+(*import Set_extra String_extra*)
+
+val _ = Define `
+((instance_Show_Show_nat_dict:(num)Show_class)= (<|
+
+ show_method := num_to_dec_string|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_natural_dict:(num)Show_class)= (<|
+
+ show_method := num_to_dec_string|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_int_dict:(int)Show_class)= (<|
+
+ show_method := lem_string_extra$stringFromInt|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_integer_dict:(int)Show_class)= (<|
+
+ show_method := lem_string_extra$stringFromInteger|>))`;
+
+
+val _ = Define `
+ ((stringFromSet:('a -> string) -> 'a set -> string) showX xs=
+ (STRCAT"{" (STRCAT(lem_show$stringFromListAux showX (SET_TO_LIST xs)) "}")))`;
+
+
+(* Abbreviates the representation if the relation is transitive. *)
+val _ = Define `
+ ((stringFromRelation:('a#'a -> string) ->('a#'a)set -> string) showX rel=
+ (if transitive rel then
+ let pruned_rel = (withoutTransitiveEdges rel) in
+ if (! (e :: rel). (e IN pruned_rel)) then
+ (* The relations are the same (there are no transitive edges),
+ so we can just as well print the original one. *)
+ stringFromSet showX rel
+ else
+ STRCAT"trancl of " (stringFromSet showX pruned_rel)
+ else
+ stringFromSet showX rel))`;
+
+
+val _ = Define `
+((instance_Show_Show_set_dict:'a Show_class ->('a set)Show_class)dict_Show_Show_a= (<|
+
+ show_method := (\ xs. stringFromSet
+ dict_Show_Show_a.show_method xs)|>))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_sortingScript.sml b/prover_snapshots/hol4/lib/lem/lem_sortingScript.sml
new file mode 100644
index 0000000..74d8496
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_sortingScript.sml
@@ -0,0 +1,107 @@
+(*Generated by Lem from sorting.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_listTheory lem_numTheory sortingTheory permLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_sorting"
+
+
+
+(*open import Bool Basic_classes Maybe List Num*)
+
+(*open import {isabelle} `HOL-Library.Permutation`*)
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {hol} `sortingTheory` `permLib`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ------------------------- *)
+(* permutations *)
+(* ------------------------- *)
+
+(*val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+
+ val _ = Define `
+ ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) l2= (NULL l2))
+/\ ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x :: xs) l2= ((
+ (case list_delete_first (eq x) l2 of
+ NONE => F
+ | SOME ys => PERM_BY eq xs ys
+ )
+ )))`;
+
+
+
+
+(* ------------------------- *)
+(* isSorted *)
+(* ------------------------- *)
+
+(* isSortedBy R l
+ checks, whether the list l is sorted by ordering R.
+ R should represent an order, i.e. it should be transitive.
+ Different backends defined "isSorted" slightly differently. However,
+ the definitions coincide for transitive R. Therefore there is the
+ following restriction:
+
+ WARNING: Use isSorted and isSortedBy only with transitive relations!
+*)
+
+(*val isSorted : forall 'a. Ord 'a => list 'a -> bool*)
+(*val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool*)
+
+(* DPM: rejigged the definition with a nested match to get past Coq's termination checker. *)
+(*let rec isSortedBy cmp l= match l with
+ | [] -> true
+ | x1 :: xs ->
+ match xs with
+ | [] -> true
+ | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs)
+ end
+end*)
+
+
+(* ----------------------- *)
+(* insertion sort *)
+(* ----------------------- *)
+
+(*val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a*)
+(*val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*)
+
+(*val insertSort: forall 'a. Ord 'a => list 'a -> list 'a*)
+(*val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*)
+
+ val _ = Define `
+ ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e ([])= ([e]))
+/\ ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e (x :: xs)= (if cmp x e then x :: (INSERT_SORT_INSERT cmp e xs) else (e :: (x :: xs))))`;
+
+
+val _ = Define `
+ ((INSERT_SORT:('a -> 'a -> bool) -> 'a list -> 'a list) cmp l= (FOLDL (\ l e . INSERT_SORT_INSERT cmp e l) [] l))`;
+
+
+
+(* ----------------------- *)
+(* general sorting *)
+(* ----------------------- *)
+
+(*val sort: forall 'a. Ord 'a => list 'a -> list 'a*)
+(*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*)
+(*val sortByOrd: forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a*)
+
+(*val predicate_of_ord : forall 'a. ('a -> 'a -> ordering) -> 'a -> 'a -> bool*)
+val _ = Define `
+ ((predicate_of_ord:('a -> 'a -> ordering) -> 'a -> 'a -> bool) f x y=
+ ((case f x y of
+ LESS => T
+ | EQUAL => T
+ | GREATER => F
+ )))`;
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_stringScript.sml b/prover_snapshots/hol4/lib/lem/lem_stringScript.sml
new file mode 100644
index 0000000..f91a4cb
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_stringScript.sml
@@ -0,0 +1,74 @@
+(*Generated by Lem from string.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_listTheory lemTheory stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_string"
+
+
+
+(*open import Bool Basic_classes List*)
+(*open import {ocaml} `Xstring`*)
+(*open import {hol} `lemTheory` `stringTheory`*)
+(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*)
+
+(* ------------------------------------------- *)
+(* translations between strings and char lists *)
+(* ------------------------------------------- *)
+
+(*val toCharList : string -> list char*)
+
+(*val toString : list char -> string*)
+
+
+(* ----------------------- *)
+(* generating strings *)
+(* ----------------------- *)
+
+(*val makeString : nat -> char -> string*)
+(*let makeString len c= toString (replicate len c)*)
+
+(* ----------------------- *)
+(* length *)
+(* ----------------------- *)
+
+(*val stringLength : string -> nat*)
+
+(* ----------------------- *)
+(* string concatenation *)
+(* ----------------------- *)
+
+(*val ^ [stringAppend] : string -> string -> string*)
+
+
+(* ----------------------------*)
+(* setting up pattern matching *)
+(* --------------------------- *)
+
+(*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*)
+
+(*let string_case s c_empty c_cons=
+ match (toCharList s) with
+ | [] -> c_empty
+ | c :: cs -> c_cons c (toString cs)
+ end*)
+
+(*val empty_string : string*)
+
+(*val cons_string : char -> string -> string*)
+
+(*val concat : string -> list string -> string*)
+ val concat_defn = Defn.Hol_multi_defns `
+ ((concat:string ->(string)list -> string) sep ([])= "")
+/\ ((concat:string ->(string)list -> string) sep (s :: ss')=
+ ((case ss' of
+ [] => s
+ | _ => STRCAT s (STRCAT sep (concat sep ss'))
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) concat_defn;
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_string_extraScript.sml b/prover_snapshots/hol4/lib/lem/lem_string_extraScript.sml
new file mode 100644
index 0000000..33f71ab
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_string_extraScript.sml
@@ -0,0 +1,124 @@
+(*Generated by Lem from string_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_numTheory lem_listTheory lem_basic_classesTheory lem_stringTheory lem_list_extraTheory ASCIInumbersTheory stringLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_string_extra"
+
+(******************************************************************************)
+(* String functions *)
+(******************************************************************************)
+
+(*open import Basic_classes*)
+(*open import Num*)
+(*open import List*)
+(*open import String*)
+(*open import List_extra*)
+(*open import {hol} `stringLib`*)
+(*open import {hol} `ASCIInumbersTheory`*)
+
+
+(******************************************************************************)
+(* Character's to numbers *)
+(******************************************************************************)
+
+(*val ord : char -> nat*)
+
+(*val chr : nat -> char*)
+
+(******************************************************************************)
+(* Converting to strings *)
+(******************************************************************************)
+
+(*val stringFromNatHelper : nat -> list char -> list char*)
+ val stringFromNatHelper_defn = Hol_defn "stringFromNatHelper" `
+ ((stringFromNatHelper:num ->(char)list ->(char)list) n acc=
+ (if n =( 0 : num) then
+ acc
+ else
+ stringFromNatHelper (n DIV( 10 : num)) (CHR ((n MOD( 10 : num)) +( 48 : num)) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNatHelper_defn;
+
+(*val stringFromNat : nat -> string*)
+
+(*val stringFromNaturalHelper : natural -> list char -> list char*)
+ val stringFromNaturalHelper_defn = Hol_defn "stringFromNaturalHelper" `
+ ((stringFromNaturalHelper:num ->(char)list ->(char)list) n acc=
+ (if n =( 0:num) then
+ acc
+ else
+ stringFromNaturalHelper (n DIV( 10:num)) (CHR ((((n MOD( 10:num)) +( 48:num)):num)) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNaturalHelper_defn;
+
+(*val stringFromNatural : natural -> string*)
+
+(*val stringFromInt : int -> string*)
+val _ = Define `
+ ((stringFromInt:int -> string) i=
+ (if i <( 0 : int) then
+ STRCAT"-" (num_to_dec_string (Num (ABS i)))
+ else
+ num_to_dec_string (Num (ABS i))))`;
+
+
+(*val stringFromInteger : integer -> string*)
+val _ = Define `
+ ((stringFromInteger:int -> string) i=
+ (if i <( 0 : int) then
+ STRCAT"-" (num_to_dec_string (Num (ABS i)))
+ else
+ num_to_dec_string (Num (ABS i))))`;
+
+
+
+(******************************************************************************)
+(* List-like operations *)
+(******************************************************************************)
+
+(*val nth : string -> nat -> char*)
+(*let nth s n= List_extra.nth (toCharList s) n*)
+
+(*val stringConcat : list string -> string*)
+(*let stringConcat s=
+ List.foldr (^) "" s*)
+
+(******************************************************************************)
+(* String comparison *)
+(******************************************************************************)
+
+(*val stringCompare : string -> string -> ordering*)
+
+val _ = Define `
+ ((stringLess:string -> string -> bool) x y= (orderingIsLess (EQUAL)))`;
+
+val _ = Define `
+ ((stringLessEq:string -> string -> bool) x y= (~ (orderingIsGreater (EQUAL))))`;
+
+val _ = Define `
+ ((stringGreater:string -> string -> bool) x y= (stringLess y x))`;
+
+val _ = Define `
+ ((stringGreaterEq:string -> string -> bool) x y= (stringLessEq y x))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_string_dict:(string)Ord_class)= (<|
+
+ compare_method := (\ x y. EQUAL);
+
+ isLess_method := stringLess;
+
+ isLessEqual_method := stringLessEq;
+
+ isGreater_method := stringGreater;
+
+ isGreaterEqual_method := stringGreaterEq|>))`;
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_tupleScript.sml b/prover_snapshots/hol4/lib/lem/lem_tupleScript.sml
new file mode 100644
index 0000000..7ee21f6
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_tupleScript.sml
@@ -0,0 +1,51 @@
+(*Generated by Lem from tuple.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_tuple"
+
+
+
+(*open import Bool Basic_classes*)
+
+(* ----------------------- *)
+(* fst *)
+(* ----------------------- *)
+
+(*val fst : forall 'a 'b. 'a * 'b -> 'a*)
+(*let fst (v1, v2)= v1*)
+
+(* ----------------------- *)
+(* snd *)
+(* ----------------------- *)
+
+(*val snd : forall 'a 'b. 'a * 'b -> 'b*)
+(*let snd (v1, v2)= v2*)
+
+
+(* ----------------------- *)
+(* curry *)
+(* ----------------------- *)
+
+(*val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)*)
+
+(* ----------------------- *)
+(* uncurry *)
+(* ----------------------- *)
+
+(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*)
+
+
+(* ----------------------- *)
+(* swap *)
+(* ----------------------- *)
+
+(*val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)*)
+(*let swap (v1, v2)= (v2, v1)*)
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/lem/lem_wordScript.sml b/prover_snapshots/hol4/lib/lem/lem_wordScript.sml
new file mode 100644
index 0000000..552f031
--- /dev/null
+++ b/prover_snapshots/hol4/lib/lem/lem_wordScript.sml
@@ -0,0 +1,1021 @@
+(*Generated by Lem from word.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_listTheory wordsTheory wordsLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_word"
+
+
+
+(*open import Bool Maybe Num Basic_classes List*)
+
+(*open import {isabelle} `HOL-Word.Word`*)
+(*open import {hol} `wordsTheory` `wordsLib`*)
+
+
+(* ========================================================================== *)
+(* Define general purpose word, i.e. sequences of bits of arbitrary length *)
+(* ========================================================================== *)
+
+val _ = Hol_datatype `
+ bitSequence = BitSeq of
+ num option => (* length of the sequence, Nothing means infinite length *)
+ bool => bool (* sign of the word, used to fill up after concrete value is exhausted *)
+ list`;
+ (* the initial part of the sequence, least significant bit first *)
+
+(*val bitSeqEq : bitSequence -> bitSequence -> bool*)
+
+(*val boolListFrombitSeq : nat -> bitSequence -> list bool*)
+
+ val _ = Define `
+ ((boolListFrombitSeqAux:num -> 'a -> 'a list -> 'a list) n s bl=
+ (if n =( 0 : num) then [] else
+ (case bl of
+ [] => REPLICATE n s
+ | b :: bl' => b :: (boolListFrombitSeqAux (n -( 1 : num)) s bl')
+ )))`;
+
+
+val _ = Define `
+ ((boolListFrombitSeq:num -> bitSequence ->(bool)list) n (BitSeq _ s bl)= (boolListFrombitSeqAux n s bl))`;
+
+
+
+(*val bitSeqFromBoolList : list bool -> maybe bitSequence*)
+val _ = Define `
+ ((bitSeqFromBoolList:(bool)list ->(bitSequence)option) bl=
+ ((case dest_init bl of
+ NONE => NONE
+ | SOME (bl', s) => SOME (BitSeq (SOME (LENGTH bl)) s bl')
+ )))`;
+
+
+
+(* cleans up the representation of a bitSequence without changing its semantics *)
+(*val cleanBitSeq : bitSequence -> bitSequence*)
+val _ = Define `
+ ((cleanBitSeq:bitSequence -> bitSequence) (BitSeq len s bl)= ((case len of
+ NONE => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE bl))))
+ | SOME n => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE (TAKE (n -( 1 : num)) bl)))))
+)))`;
+
+
+
+(*val bitSeqTestBit : bitSequence -> nat -> maybe bool*)
+val _ = Define `
+ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq NONE s bl) pos= (if pos < LENGTH bl then list_index bl pos else SOME s))
+/\ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq(SOME l) s bl) pos= (if (pos >= l) then NONE else
+ if ((pos = (l -( 1 : num))) \/ (pos >= LENGTH bl)) then SOME s else
+ list_index bl pos))`;
+
+
+(*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*)
+val _ = Define `
+ ((bitSeqSetBit:bitSequence -> num -> bool -> bitSequence) (BitSeq len s bl) pos v=
+ (let bl' = (if (pos < LENGTH bl) then bl else bl ++ REPLICATE pos s) in
+ let bl'' = (LUPDATE v pos bl') in
+ let bs' = (BitSeq len s bl'') in
+ cleanBitSeq bs'))`;
+
+
+
+(*val resizeBitSeq : maybe nat -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((resizeBitSeq:(num)option -> bitSequence -> bitSequence) new_len bs=
+ ((case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ let shorten_opt = ((case (new_len, len) of
+ (NONE, _) => NONE
+ | (SOME l1, NONE) => SOME l1
+ | (SOME l1, SOME l2) =>
+ if (l1 < l2) then SOME l1 else NONE
+ )) in
+ (case shorten_opt of
+ NONE => BitSeq new_len s bl
+ | SOME l1 => (
+ let bl' = (TAKE l1 (bl ++ [s])) in
+ (case dest_init bl' of
+ NONE => (BitSeq len s bl) (* do nothing if size 0 is requested *)
+ | SOME (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'')
+ ))
+ )
+ )))`;
+
+
+(*val bitSeqNot : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqNot:bitSequence -> bitSequence) (BitSeq len s bl)= (BitSeq len (~ s) (MAP (\ x. ~ x) bl)))`;
+
+
+(*val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence*)
+
+(*val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool*)
+ val _ = Define `
+ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 ([])= ([]))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 ([])= ((binop b1 s2) :: bitSeqBinopAux binop s1 bl1' s2 []))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 (b2 :: bl2')= ((binop s1 b2) :: bitSeqBinopAux binop s1 [] s2 bl2'))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 (b2 :: bl2')= ((binop b1 b2) :: bitSeqBinopAux binop s1 bl1' s2 bl2'))`;
+
+
+val _ = Define `
+ ((bitSeqBinop:(bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2= (
+ (case cleanBitSeq bs1 of
+ (BitSeq len1 s1 bl1) =>
+ (case cleanBitSeq bs2 of
+ (BitSeq len2 s2 bl2) =>
+ let len = ((case (len1, len2) of
+ (SOME l1, SOME l2) => SOME (MAX l1 l2)
+ | _ => NONE
+ )) in
+ let s = (binop s1 s2) in
+ let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in
+ cleanBitSeq (BitSeq len s bl)
+ )
+ )
+))`;
+
+
+val _ = Define `
+ ((bitSeqAnd:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (/\)))`;
+
+val _ = Define `
+ ((bitSeqOr:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (\/)))`;
+
+val _ = Define `
+ ((bitSeqXor:bitSequence -> bitSequence -> bitSequence)= (bitSeqBinop (\ b1 b2. ~ (b1 <=> b2))))`;
+
+
+(*val bitSeqShiftLeft : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqShiftLeft:bitSequence -> num -> bitSequence) (BitSeq len s bl) n= (cleanBitSeq (BitSeq len s (REPLICATE n F ++ bl))))`;
+
+
+(*val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithmeticShiftRight:bitSequence -> num -> bitSequence) bs n=
+ ((case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ cleanBitSeq (BitSeq len s (DROP n bl))
+ )))`;
+
+
+(*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqLogicalShiftRight:bitSequence -> num -> bitSequence) bs n=
+ (if (n =( 0 : num)) then cleanBitSeq bs else
+ (case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ (case len of
+ NONE => cleanBitSeq (BitSeq len s (DROP n bl))
+ | SOME l => cleanBitSeq (BitSeq len F ((DROP n bl) ++ REPLICATE l s))
+ )
+ )))`;
+
+
+
+(* integerFromBoolList sign bl creates an integer from a list of bits
+ (least significant bit first) and an explicitly given sign bit.
+ It uses two's complement encoding. *)
+(*val integerFromBoolList : (bool * list bool) -> integer*)
+
+ val _ = Define `
+ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) (([]) : bool list)= acc)
+/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((T :: bl') : bool list)= (integerFromBoolListAux ((acc *( 2 : int)) +( 1 : int)) bl'))
+/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((F :: bl') : bool list)= (integerFromBoolListAux (acc *( 2 : int)) bl'))`;
+
+
+val _ = Define `
+ ((integerFromBoolList:bool#(bool)list -> int) (sign, bl)=
+ (if sign then
+ ~ (integerFromBoolListAux(( 0 : int)) (REVERSE (MAP (\ x. ~ x) bl)) +( 1 : int))
+ else integerFromBoolListAux(( 0 : int)) (REVERSE bl)))`;
+
+
+(* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*)
+(*val boolListFromInteger : integer -> bool * list bool*)
+
+ val _ = Define `
+ ((boolListFromNatural:(bool)list -> num ->(bool)list) acc (remainder : num)=
+ (if (remainder >( 0:num)) then
+ (boolListFromNatural (((remainder MOD( 2:num)) =( 1:num)) :: acc)
+ (remainder DIV( 2:num)))
+ else
+ REVERSE acc))`;
+
+
+val _ = Define `
+ ((boolListFromInteger:int -> bool#(bool)list) (i : int)=
+ (if (i <( 0 : int)) then
+ (T, MAP (\ x. ~ x) (boolListFromNatural [] (Num (ABS (~ (i +( 1 : int)))))))
+ else
+ (F, boolListFromNatural [] (Num (ABS i)))))`;
+
+
+
+(* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough
+ bits, truncation happens *)
+(*val bitSeqFromInteger : maybe nat -> integer -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromInteger:(num)option -> int -> bitSequence) len_opt i=
+ (let (s, bl) = (boolListFromInteger i) in
+ resizeBitSeq len_opt (BitSeq NONE s bl)))`;
+
+
+
+(*val integerFromBitSeq : bitSequence -> integer*)
+val _ = Define `
+ ((integerFromBitSeq:bitSequence -> int) bs=
+ ((case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) )))`;
+
+
+
+(* Now we can via translation to integers map arithmetic operations to bitSequences *)
+
+(*val bitSeqArithUnaryOp : (integer -> integer) -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithUnaryOp:(int -> int) -> bitSequence -> bitSequence) uop bs=
+ ((case bs of
+ (BitSeq len _ _) =>
+ bitSeqFromInteger len (uop (integerFromBitSeq bs))
+ )))`;
+
+
+(*val bitSeqArithBinOp : (integer -> integer -> integer) -> bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithBinOp:(int -> int -> int) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2=
+ ((case bs1 of
+ (BitSeq len1 _ _) =>
+ (case bs2 of
+ (BitSeq len2 _ _) =>
+ let len = ((case (len1, len2) of
+ (SOME l1, SOME l2) => SOME (MAX l1 l2)
+ | _ => NONE
+ )) in
+ bitSeqFromInteger len
+ (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))
+ )
+ )))`;
+
+
+(*val bitSeqArithBinTest : forall 'a. (integer -> integer -> 'a) -> bitSequence -> bitSequence -> 'a*)
+val _ = Define `
+ ((bitSeqArithBinTest:(int -> int -> 'a) -> bitSequence -> bitSequence -> 'a) binop bs1 bs2= (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)))`;
+
+
+
+(* now instantiate the number interface for bit-sequences *)
+
+(*val bitSeqFromNumeral : numeral -> bitSequence*)
+
+(*val bitSeqLess : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqLess:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (<) bs1 bs2))`;
+
+
+(*val bitSeqLessEqual : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqLessEqual:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (<=) bs1 bs2))`;
+
+
+(*val bitSeqGreater : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqGreater:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (>) bs1 bs2))`;
+
+
+(*val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqGreaterEqual:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (>=) bs1 bs2))`;
+
+
+(*val bitSeqCompare : bitSequence -> bitSequence -> ordering*)
+val _ = Define `
+ ((bitSeqCompare:bitSequence -> bitSequence -> ordering) bs1 bs2= (bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Word_bitSequence_dict:(bitSequence)Ord_class)= (<|
+
+ compare_method := bitSeqCompare;
+
+ isLess_method := bitSeqLess;
+
+ isLessEqual_method := bitSeqLessEqual;
+
+ isGreater_method := bitSeqGreater;
+
+ isGreaterEqual_method := bitSeqGreaterEqual|>))`;
+
+
+(* arithmetic negation, don't mix up with bitwise negation *)
+(*val bitSeqNegate : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqNegate:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ i. ~ i) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumNegate_Word_bitSequence_dict:(bitSequence)NumNegate_class)= (<|
+
+ numNegate_method := bitSeqNegate|>))`;
+
+
+
+(*val bitSeqAdd : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqAdd:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (+) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumAdd_Word_bitSequence_dict:(bitSequence)NumAdd_class)= (<|
+
+ numAdd_method := bitSeqAdd|>))`;
+
+
+(*val bitSeqMinus : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMinus:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (-) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumMinus_Word_bitSequence_dict:(bitSequence)NumMinus_class)= (<|
+
+ numMinus_method := bitSeqMinus|>))`;
+
+
+(*val bitSeqSucc : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqSucc:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ n. n +( 1 : int)) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumSucc_Word_bitSequence_dict:(bitSequence)NumSucc_class)= (<|
+
+ succ_method := bitSeqSucc|>))`;
+
+
+(*val bitSeqPred : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqPred:bitSequence -> bitSequence) bs= (bitSeqArithUnaryOp (\ n. n -( 1 : int)) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumPred_Word_bitSequence_dict:(bitSequence)NumPred_class)= (<|
+
+ pred_method := bitSeqPred|>))`;
+
+
+(*val bitSeqMult : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMult:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp ( * ) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumMult_Word_bitSequence_dict:(bitSequence)NumMult_class)= (<|
+
+ numMult_method := bitSeqMult|>))`;
+
+
+
+(*val bitSeqPow : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqPow:bitSequence -> num -> bitSequence) bs n= (bitSeqArithUnaryOp (\ i . i ** n) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Word_bitSequence_dict:(bitSequence)NumPow_class)= (<|
+
+ numPow_method := bitSeqPow|>))`;
+
+
+(*val bitSeqDiv : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqDiv:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (/) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Word_bitSequence_dict:(bitSequence)NumIntegerDivision_class)= (<|
+
+ div_method := bitSeqDiv|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Word_bitSequence_dict:(bitSequence)NumDivision_class)= (<|
+
+ numDivision_method := bitSeqDiv|>))`;
+
+
+(*val bitSeqMod : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMod:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp (%) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumRemainder_Word_bitSequence_dict:(bitSequence)NumRemainder_class)= (<|
+
+ mod_method := bitSeqMod|>))`;
+
+
+(*val bitSeqMin : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMin:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp int_min bs1 bs2))`;
+
+
+(*val bitSeqMax : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMax:bitSequence -> bitSequence -> bitSequence) bs1 bs2= (bitSeqArithBinOp int_max bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict:(bitSequence)OrdMaxMin_class)= (<|
+
+ max_method := bitSeqMax;
+
+ min_method := bitSeqMin|>))`;
+
+
+
+
+
+(* ========================================================================== *)
+(* Interface for bitoperations *)
+(* ========================================================================== *)
+
+val _ = Hol_datatype `
+(* 'a *) WordNot_class= <|
+ lnot_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) WordAnd_class= <|
+ land_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) WordOr_class= <|
+ lor_method : 'a -> 'a -> 'a
+|>`;
+
+
+
+val _ = Hol_datatype `
+(* 'a *) WordXor_class= <|
+ lxor_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) WordLsl_class= <|
+ lsl_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) WordLsr_class= <|
+ lsr_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(* 'a *) WordAsr_class= <|
+ asr_method : 'a -> num -> 'a
+|>`;
+
+
+(* ----------------------- *)
+(* bitSequence *)
+(* ----------------------- *)
+
+val _ = Define `
+((instance_Word_WordNot_Word_bitSequence_dict:(bitSequence)WordNot_class)= (<|
+
+ lnot_method := bitSeqNot|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Word_bitSequence_dict:(bitSequence)WordAnd_class)= (<|
+
+ land_method := bitSeqAnd|>))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Word_bitSequence_dict:(bitSequence)WordOr_class)= (<|
+
+ lor_method := bitSeqOr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Word_bitSequence_dict:(bitSequence)WordXor_class)= (<|
+
+ lxor_method := bitSeqXor|>))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Word_bitSequence_dict:(bitSequence)WordLsl_class)= (<|
+
+ lsl_method := bitSeqShiftLeft|>))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Word_bitSequence_dict:(bitSequence)WordLsr_class)= (<|
+
+ lsr_method := bitSeqLogicalShiftRight|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Word_bitSequence_dict:(bitSequence)WordAsr_class)= (<|
+
+ asr_method := bitSeqArithmeticShiftRight|>))`;
+
+
+
+(* ----------------------- *)
+(* int32 *)
+(* ----------------------- *)
+
+(*val int32Lnot : int32 -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordNot_Num_int32_dict:(word32)WordNot_class)= (<|
+
+ lnot_method := (\ w. (~ w))|>))`;
+
+
+
+(*val int32Lor : int32 -> int32 -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordOr_Num_int32_dict:(word32)WordOr_class)= (<|
+
+ lor_method := word_or|>))`;
+
+
+(*val int32Lxor : int32 -> int32 -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordXor_Num_int32_dict:(word32)WordXor_class)= (<|
+
+ lxor_method := word_xor|>))`;
+
+
+(*val int32Land : int32 -> int32 -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int32_dict:(word32)WordAnd_class)= (<|
+
+ land_method := word_and|>))`;
+
+
+(*val int32Lsl : int32 -> nat -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int32_dict:(word32)WordLsl_class)= (<|
+
+ lsl_method := word_lsl|>))`;
+
+
+(*val int32Lsr : int32 -> nat -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsr_Num_int32_dict:(word32)WordLsr_class)= (<|
+
+ lsr_method := word_lsr|>))`;
+
+
+
+(*val int32Asr : int32 -> nat -> int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int32_dict:(word32)WordAsr_class)= (<|
+
+ asr_method := word_asr|>))`;
+
+
+
+(* ----------------------- *)
+(* int64 *)
+(* ----------------------- *)
+
+(*val int64Lnot : int64 -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordNot_Num_int64_dict:(word64)WordNot_class)= (<|
+
+ lnot_method := (\ w. (~ w))|>))`;
+
+
+(*val int64Lor : int64 -> int64 -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordOr_Num_int64_dict:(word64)WordOr_class)= (<|
+
+ lor_method := word_or|>))`;
+
+
+(*val int64Lxor : int64 -> int64 -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordXor_Num_int64_dict:(word64)WordXor_class)= (<|
+
+ lxor_method := word_xor|>))`;
+
+
+(*val int64Land : int64 -> int64 -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int64_dict:(word64)WordAnd_class)= (<|
+
+ land_method := word_and|>))`;
+
+
+(*val int64Lsl : int64 -> nat -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int64_dict:(word64)WordLsl_class)= (<|
+
+ lsl_method := word_lsl|>))`;
+
+
+(*val int64Lsr : int64 -> nat -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsr_Num_int64_dict:(word64)WordLsr_class)= (<|
+
+ lsr_method := word_lsr|>))`;
+
+
+(*val int64Asr : int64 -> nat -> int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int64_dict:(word64)WordAsr_class)= (<|
+
+ asr_method := word_asr|>))`;
+
+
+
+(* ----------------------- *)
+(* Words via bit sequences *)
+(* ----------------------- *)
+
+(*val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLnot:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a) fromBitSeq toBitSeq x= (fromBitSeq (bitSeqNegate (toBitSeq x))))`;
+
+
+(*val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLand:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLxor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2= (fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultLsl:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqShiftLeft (toBitSeq x) n)))`;
+
+
+(*val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultLsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n)))`;
+
+
+(*val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultAsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n= (fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n)))`;
+
+
+(* ----------------------- *)
+(* integer *)
+(* ----------------------- *)
+
+(*val integerLnot : integer -> integer*)
+val _ = Define `
+ ((integerLnot:int -> int) i= (~ (i +( 1 : int))))`;
+
+
+val _ = Define `
+((instance_Word_WordNot_Num_integer_dict:(int)WordNot_class)= (<|
+
+ lnot_method := integerLnot|>))`;
+
+
+
+(*val integerLor : integer -> integer -> integer*)
+val _ = Define `
+ ((integerLor:int -> int -> int) i1 i2= (defaultLor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_integer_dict:(int)WordOr_class)= (<|
+
+ lor_method := integerLor|>))`;
+
+
+(*val integerLxor : integer -> integer -> integer*)
+val _ = Define `
+ ((integerLxor:int -> int -> int) i1 i2= (defaultLxor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_integer_dict:(int)WordXor_class)= (<|
+
+ lxor_method := integerLxor|>))`;
+
+
+(*val integerLand : integer -> integer -> integer*)
+val _ = Define `
+ ((integerLand:int -> int -> int) i1 i2= (defaultLand integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_integer_dict:(int)WordAnd_class)= (<|
+
+ land_method := integerLand|>))`;
+
+
+(*val integerLsl : integer -> nat -> integer*)
+val _ = Define `
+ ((integerLsl:int -> num -> int) i n= (defaultLsl integerFromBitSeq (bitSeqFromInteger NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_integer_dict:(int)WordLsl_class)= (<|
+
+ lsl_method := integerLsl|>))`;
+
+
+(*val integerAsr : integer -> nat -> integer*)
+val _ = Define `
+ ((integerAsr:int -> num -> int) i n= (defaultAsr integerFromBitSeq (bitSeqFromInteger NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Num_integer_dict:(int)WordLsr_class)= (<|
+
+ lsr_method := integerAsr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_integer_dict:(int)WordAsr_class)= (<|
+
+ asr_method := integerAsr|>))`;
+
+
+
+(* ----------------------- *)
+(* int *)
+(* ----------------------- *)
+
+(* sometimes it is convenient to be able to perform bit-operations on ints.
+ However, since int is not well-defined (it has different size on different systems),
+ it should be used very carefully and only for operations that don't depend on the
+ bitwidth of int *)
+
+(*val intFromBitSeq : bitSequence -> int*)
+val _ = Define `
+ ((intFromBitSeq:bitSequence -> int) bs= (I (integerFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs))))`;
+
+
+
+(*val bitSeqFromInt : int -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromInt:int -> bitSequence) i= (bitSeqFromInteger (SOME(( 31 : num))) ( i)))`;
+
+
+
+(*val intLnot : int -> int*)
+val _ = Define `
+ ((intLnot:int -> int) i= (~ (i +( 1 : int))))`;
+
+
+val _ = Define `
+((instance_Word_WordNot_Num_int_dict:(int)WordNot_class)= (<|
+
+ lnot_method := intLnot|>))`;
+
+
+(*val intLor : int -> int -> int*)
+val _ = Define `
+ ((intLor:int -> int -> int) i1 i2= (defaultLor intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_int_dict:(int)WordOr_class)= (<|
+
+ lor_method := intLor|>))`;
+
+
+(*val intLxor : int -> int -> int*)
+val _ = Define `
+ ((intLxor:int -> int -> int) i1 i2= (defaultLxor intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_int_dict:(int)WordXor_class)= (<|
+
+ lxor_method := intLxor|>))`;
+
+
+(*val intLand : int -> int -> int*)
+val _ = Define `
+ ((intLand:int -> int -> int) i1 i2= (defaultLand intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int_dict:(int)WordAnd_class)= (<|
+
+ land_method := intLand|>))`;
+
+
+(*val intLsl : int -> nat -> int*)
+val _ = Define `
+ ((intLsl:int -> num -> int) i n= (defaultLsl intFromBitSeq bitSeqFromInt i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int_dict:(int)WordLsl_class)= (<|
+
+ lsl_method := intLsl|>))`;
+
+
+(*val intAsr : int -> nat -> int*)
+val _ = Define `
+ ((intAsr:int -> num -> int) i n= (defaultAsr intFromBitSeq bitSeqFromInt i n))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int_dict:(int)WordAsr_class)= (<|
+
+ asr_method := intAsr|>))`;
+
+
+
+
+(* ----------------------- *)
+(* natural *)
+(* ----------------------- *)
+
+(* some operations work also on positive numbers *)
+
+(*val naturalFromBitSeq : bitSequence -> natural*)
+val _ = Define `
+ ((naturalFromBitSeq:bitSequence -> num) bs= (Num (ABS (integerFromBitSeq bs))))`;
+
+
+(*val bitSeqFromNatural : maybe nat -> natural -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromNatural:(num)option -> num -> bitSequence) len n= (bitSeqFromInteger len (int_of_num n)))`;
+
+
+(*val naturalLor : natural -> natural -> natural*)
+val _ = Define `
+ ((naturalLor:num -> num -> num) i1 i2= (defaultLor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_natural_dict:(num)WordOr_class)= (<|
+
+ lor_method := naturalLor|>))`;
+
+
+(*val naturalLxor : natural -> natural -> natural*)
+val _ = Define `
+ ((naturalLxor:num -> num -> num) i1 i2= (defaultLxor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_natural_dict:(num)WordXor_class)= (<|
+
+ lxor_method := naturalLxor|>))`;
+
+
+(*val naturalLand : natural -> natural -> natural*)
+val _ = Define `
+ ((naturalLand:num -> num -> num) i1 i2= (defaultLand naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_natural_dict:(num)WordAnd_class)= (<|
+
+ land_method := naturalLand|>))`;
+
+
+(*val naturalLsl : natural -> nat -> natural*)
+val _ = Define `
+ ((naturalLsl:num -> num -> num) i n= (defaultLsl naturalFromBitSeq (bitSeqFromNatural NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_natural_dict:(num)WordLsl_class)= (<|
+
+ lsl_method := naturalLsl|>))`;
+
+
+(*val naturalAsr : natural -> nat -> natural*)
+val _ = Define `
+ ((naturalAsr:num -> num -> num) i n= (defaultAsr naturalFromBitSeq (bitSeqFromNatural NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Num_natural_dict:(num)WordLsr_class)= (<|
+
+ lsr_method := naturalAsr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_natural_dict:(num)WordAsr_class)= (<|
+
+ asr_method := naturalAsr|>))`;
+
+
+
+(* ----------------------- *)
+(* nat *)
+(* ----------------------- *)
+
+(* sometimes it is convenient to be able to perform bit-operations on nats.
+ However, since nat is not well-defined (it has different size on different systems),
+ it should be used very carefully and only for operations that don't depend on the
+ bitwidth of nat *)
+
+(*val natFromBitSeq : bitSequence -> nat*)
+val _ = Define `
+ ((natFromBitSeq:bitSequence -> num) bs= (((naturalFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs)):num)))`;
+
+
+
+(*val bitSeqFromNat : nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromNat:num -> bitSequence) i= (bitSeqFromNatural (SOME(( 31 : num))) (( i:num))))`;
+
+
+
+(*val natLor : nat -> nat -> nat*)
+val _ = Define `
+ ((natLor:num -> num -> num) i1 i2= (defaultLor natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_nat_dict:(num)WordOr_class)= (<|
+
+ lor_method := natLor|>))`;
+
+
+(*val natLxor : nat -> nat -> nat*)
+val _ = Define `
+ ((natLxor:num -> num -> num) i1 i2= (defaultLxor natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_nat_dict:(num)WordXor_class)= (<|
+
+ lxor_method := natLxor|>))`;
+
+
+(*val natLand : nat -> nat -> nat*)
+val _ = Define `
+ ((natLand:num -> num -> num) i1 i2= (defaultLand natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_nat_dict:(num)WordAnd_class)= (<|
+
+ land_method := natLand|>))`;
+
+
+(*val natLsl : nat -> nat -> nat*)
+val _ = Define `
+ ((natLsl:num -> num -> num) i n= (defaultLsl natFromBitSeq bitSeqFromNat i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_nat_dict:(num)WordLsl_class)= (<|
+
+ lsl_method := natLsl|>))`;
+
+
+(*val natAsr : nat -> nat -> nat*)
+val _ = Define `
+ ((natAsr:num -> num -> num) i n= (defaultAsr natFromBitSeq bitSeqFromNat i n))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_nat_dict:(num)WordAsr_class)= (<|
+
+ asr_method := natAsr|>))`;
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/Holmakefile b/prover_snapshots/hol4/lib/sail/Holmakefile
new file mode 100644
index 0000000..344b8b7
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/Holmakefile
@@ -0,0 +1,29 @@
+LEM_SCRIPTS = sail2_instr_kindsScript.sml sail2_valuesScript.sml sail2_operatorsScript.sml \
+ sail2_operators_mwordsScript.sml sail2_operators_bitlistsScript.sml \
+ sail2_state_monadScript.sml sail2_stateScript.sml sail2_promptScript.sml sail2_prompt_monadScript.sml \
+ sail2_stringScript.sml
+
+LEM_CLEANS = $(LEM_SCRIPTS)
+
+SCRIPTS = $(LEM_SCRIPTS) \
+ sail2_valuesAuxiliaryScript.sml sail2_stateAuxiliaryScript.sml
+
+THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
+
+INCLUDES = ../lem
+
+all: $(THYS)
+.PHONY: all
+
+ifdef POLY
+HOLHEAP = sail-heap
+EXTRA_CLEANS = $(HOLHEAP) $(HOLHEAP).o
+
+BASE_HEAP = ../lem/lemheap
+
+$(HOLHEAP): $(BASE_HEAP)
+ $(protect $(HOLDIR)/bin/buildheap) -o $(HOLHEAP) -b $(BASE_HEAP)
+
+all: $(HOLHEAP)
+
+endif
diff --git a/prover_snapshots/hol4/lib/sail/sail2_instr_kindsScript.sml b/prover_snapshots/hol4/lib/sail/sail2_instr_kindsScript.sml
new file mode 100644
index 0000000..c4ba665
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_instr_kindsScript.sml
@@ -0,0 +1,543 @@
+(*Generated by Lem from ../../src/lem_interp/sail2_instr_kinds.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_instr_kinds"
+
+(*========================================================================*)
+(* Sail *)
+(* *)
+(* Copyright (c) 2013-2017 *)
+(* Kathyrn Gray *)
+(* Shaked Flur *)
+(* Stephen Kell *)
+(* Gabriel Kerneis *)
+(* Robert Norton-Wright *)
+(* Christopher Pulte *)
+(* Peter Sewell *)
+(* Alasdair Armstrong *)
+(* Brian Campbell *)
+(* Thomas Bauereiss *)
+(* Anthony Fox *)
+(* Jon French *)
+(* Dominic Mulligan *)
+(* Stephen Kell *)
+(* Mark Wassell *)
+(* *)
+(* All rights reserved. *)
+(* *)
+(* This software was developed by the University of Cambridge Computer *)
+(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *)
+(* (REMS) project, funded by EPSRC grant EP/K008528/1. *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in *)
+(* the documentation and/or other materials provided with the *)
+(* distribution. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *)
+(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *)
+(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *)
+(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *)
+(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *)
+(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *)
+(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *)
+(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *)
+(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *)
+(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *)
+(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *)
+(* SUCH DAMAGE. *)
+(*========================================================================*)
+
+(*open import Pervasives_extra*)
+
+
+val _ = Hol_datatype `
+(* 'a *) EnumerationType_class= <|
+ toNat_method : 'a -> num
+|>`;
+
+
+
+(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*)
+val _ = Define `
+ ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail2_instr_kinds_EnumerationType_a e1 e2=
+ (genericCompare (<) (=) (
+ dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e2)))`;
+
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail2_instr_kinds_EnumerationType_a= (<|
+
+ compare_method :=
+ (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a);
+
+ isLess_method := (\ r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LESS);
+
+ isLessEqual_method := (\ r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> GREATER);
+
+ isGreater_method := (\ r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GREATER);
+
+ isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`;
+
+
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+ reflected in deep_shallow_convert *)
+val _ = Hol_datatype `
+ read_kind =
+ (* common reads *)
+ Read_plain
+ (* Power reads *)
+ | Read_reserve
+ (* AArch64 reads *)
+ | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+ (* RISC-V reads *)
+ | Read_RISCV_acquire | Read_RISCV_strong_acquire
+ | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+ | Read_RISCV_reserved_strong_acquire
+ (* x86 reads *)
+ | Read_X86_locked`;
+ (* the read part of a lock'd instruction (rmw) *)
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ Read_plain => "Read_plain"
+ | Read_reserve => "Read_reserve"
+ | Read_acquire => "Read_acquire"
+ | Read_exclusive => "Read_exclusive"
+ | Read_exclusive_acquire => "Read_exclusive_acquire"
+ | Read_stream => "Read_stream"
+ | Read_RISCV_acquire => "Read_RISCV_acquire"
+ | Read_RISCV_strong_acquire => "Read_RISCV_strong_acquire"
+ | Read_RISCV_reserved => "Read_RISCV_reserved"
+ | Read_RISCV_reserved_acquire => "Read_RISCV_reserved_acquire"
+ | Read_RISCV_reserved_strong_acquire => "Read_RISCV_reserved_strong_acquire"
+ | Read_X86_locked => "Read_X86_locked"
+ ))|>))`;
+
+
+val _ = Hol_datatype `
+ write_kind =
+ (* common writes *)
+ Write_plain
+ (* Power writes *)
+ | Write_conditional
+ (* AArch64 writes *)
+ | Write_release | Write_exclusive | Write_exclusive_release
+ (* RISC-V *)
+ | Write_RISCV_release | Write_RISCV_strong_release
+ | Write_RISCV_conditional | Write_RISCV_conditional_release
+ | Write_RISCV_conditional_strong_release
+ (* x86 writes *)
+ | Write_X86_locked`;
+ (* the write part of a lock'd instruction (rmw) *)
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ Write_plain => "Write_plain"
+ | Write_conditional => "Write_conditional"
+ | Write_release => "Write_release"
+ | Write_exclusive => "Write_exclusive"
+ | Write_exclusive_release => "Write_exclusive_release"
+ | Write_RISCV_release => "Write_RISCV_release"
+ | Write_RISCV_strong_release => "Write_RISCV_strong_release"
+ | Write_RISCV_conditional => "Write_RISCV_conditional"
+ | Write_RISCV_conditional_release => "Write_RISCV_conditional_release"
+ | Write_RISCV_conditional_strong_release => "Write_RISCV_conditional_strong_release"
+ | Write_X86_locked => "Write_X86_locked"
+ ))|>))`;
+
+
+val _ = Hol_datatype `
+ barrier_kind =
+ (* Power barriers *)
+ Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+ (* AArch64 barriers *)
+ | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+ | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+ | Barrier_TM_COMMIT
+ (* MIPS barriers *)
+ | Barrier_MIPS_SYNC
+ (* RISC-V barriers *)
+ | Barrier_RISCV_rw_rw
+ | Barrier_RISCV_r_rw
+ | Barrier_RISCV_r_r
+ | Barrier_RISCV_rw_w
+ | Barrier_RISCV_w_w
+ | Barrier_RISCV_w_rw
+ | Barrier_RISCV_rw_r
+ | Barrier_RISCV_r_w
+ | Barrier_RISCV_w_r
+ | Barrier_RISCV_tso
+ | Barrier_RISCV_i
+ (* X86 *)
+ | Barrier_x86_MFENCE`;
+
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ Barrier_Sync => "Barrier_Sync"
+ | Barrier_LwSync => "Barrier_LwSync"
+ | Barrier_Eieio => "Barrier_Eieio"
+ | Barrier_Isync => "Barrier_Isync"
+ | Barrier_DMB => "Barrier_DMB"
+ | Barrier_DMB_ST => "Barrier_DMB_ST"
+ | Barrier_DMB_LD => "Barrier_DMB_LD"
+ | Barrier_DSB => "Barrier_DSB"
+ | Barrier_DSB_ST => "Barrier_DSB_ST"
+ | Barrier_DSB_LD => "Barrier_DSB_LD"
+ | Barrier_ISB => "Barrier_ISB"
+ | Barrier_TM_COMMIT => "Barrier_TM_COMMIT"
+ | Barrier_MIPS_SYNC => "Barrier_MIPS_SYNC"
+ | Barrier_RISCV_rw_rw => "Barrier_RISCV_rw_rw"
+ | Barrier_RISCV_r_rw => "Barrier_RISCV_r_rw"
+ | Barrier_RISCV_r_r => "Barrier_RISCV_r_r"
+ | Barrier_RISCV_rw_w => "Barrier_RISCV_rw_w"
+ | Barrier_RISCV_w_w => "Barrier_RISCV_w_w"
+ | Barrier_RISCV_w_rw => "Barrier_RISCV_w_rw"
+ | Barrier_RISCV_rw_r => "Barrier_RISCV_rw_r"
+ | Barrier_RISCV_r_w => "Barrier_RISCV_r_w"
+ | Barrier_RISCV_w_r => "Barrier_RISCV_w_r"
+ | Barrier_RISCV_tso => "Barrier_RISCV_tso"
+ | Barrier_RISCV_i => "Barrier_RISCV_i"
+ | Barrier_x86_MFENCE => "Barrier_x86_MFENCE"
+ ))|>))`;
+
+
+val _ = Hol_datatype `
+ trans_kind =
+ (* AArch64 *)
+ Transaction_start | Transaction_commit | Transaction_abort`;
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ Transaction_start => "Transaction_start"
+ | Transaction_commit => "Transaction_commit"
+ | Transaction_abort => "Transaction_abort"
+ ))|>))`;
+
+
+(* cache maintenance instructions *)
+val _ = Hol_datatype `
+ cache_op_kind =
+ (* AArch64 DC *)
+ Cache_op_D_IVAC | Cache_op_D_ISW | Cache_op_D_CSW | Cache_op_D_CISW
+ | Cache_op_D_ZVA | Cache_op_D_CVAC | Cache_op_D_CVAU | Cache_op_D_CIVAC
+ (* AArch64 IC *)
+ | Cache_op_I_IALLUIS | Cache_op_I_IALLU | Cache_op_I_IVAU`;
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_cache_op_kind_dict:(cache_op_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ Cache_op_D_IVAC => "Cache_op_D_IVAC"
+ | Cache_op_D_ISW => "Cache_op_D_ISW"
+ | Cache_op_D_CSW => "Cache_op_D_CSW"
+ | Cache_op_D_CISW => "Cache_op_D_CISW"
+ | Cache_op_D_ZVA => "Cache_op_D_ZVA"
+ | Cache_op_D_CVAC => "Cache_op_D_CVAC"
+ | Cache_op_D_CVAU => "Cache_op_D_CVAU"
+ | Cache_op_D_CIVAC => "Cache_op_D_CIVAC"
+ | Cache_op_I_IALLUIS => "Cache_op_I_IALLUIS"
+ | Cache_op_I_IALLU => "Cache_op_I_IALLU"
+ | Cache_op_I_IVAU => "Cache_op_I_IVAU"
+ ))|>))`;
+
+
+val _ = Hol_datatype `
+ instruction_kind =
+ IK_barrier of barrier_kind
+ | IK_mem_read of read_kind
+ | IK_mem_write of write_kind
+ | IK_mem_rmw of (read_kind # write_kind)
+ | IK_branch of unit(* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+ indirect/computed-branch (single nia of kind NIA_indirect_address)
+ and branch/jump (single nia of kind NIA_concrete_address) *)
+ | IK_trans of trans_kind
+ | IK_simple of unit
+ | IK_cache_op of cache_op_kind`;
+
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<|
+
+ show_method := (\x .
+ (case x of
+ IK_barrier barrier_kind => STRCAT "IK_barrier "
+ (((\x . (case x of
+ Barrier_Sync => "Barrier_Sync"
+ | Barrier_LwSync => "Barrier_LwSync"
+ | Barrier_Eieio => "Barrier_Eieio"
+ | Barrier_Isync => "Barrier_Isync"
+ | Barrier_DMB => "Barrier_DMB"
+ | Barrier_DMB_ST => "Barrier_DMB_ST"
+ | Barrier_DMB_LD => "Barrier_DMB_LD"
+ | Barrier_DSB => "Barrier_DSB"
+ | Barrier_DSB_ST => "Barrier_DSB_ST"
+ | Barrier_DSB_LD => "Barrier_DSB_LD"
+ | Barrier_ISB => "Barrier_ISB"
+ | Barrier_TM_COMMIT =>
+ "Barrier_TM_COMMIT"
+ | Barrier_MIPS_SYNC =>
+ "Barrier_MIPS_SYNC"
+ | Barrier_RISCV_rw_rw =>
+ "Barrier_RISCV_rw_rw"
+ | Barrier_RISCV_r_rw =>
+ "Barrier_RISCV_r_rw"
+ | Barrier_RISCV_r_r =>
+ "Barrier_RISCV_r_r"
+ | Barrier_RISCV_rw_w =>
+ "Barrier_RISCV_rw_w"
+ | Barrier_RISCV_w_w =>
+ "Barrier_RISCV_w_w"
+ | Barrier_RISCV_w_rw =>
+ "Barrier_RISCV_w_rw"
+ | Barrier_RISCV_rw_r =>
+ "Barrier_RISCV_rw_r"
+ | Barrier_RISCV_r_w =>
+ "Barrier_RISCV_r_w"
+ | Barrier_RISCV_w_r =>
+ "Barrier_RISCV_w_r"
+ | Barrier_RISCV_tso =>
+ "Barrier_RISCV_tso"
+ | Barrier_RISCV_i =>
+ "Barrier_RISCV_i"
+ | Barrier_x86_MFENCE =>
+ "Barrier_x86_MFENCE"
+ )) barrier_kind))
+ | IK_mem_read read_kind => STRCAT "IK_mem_read "
+ (((\x . (case x of
+ Read_plain => "Read_plain"
+ | Read_reserve => "Read_reserve"
+ | Read_acquire => "Read_acquire"
+ | Read_exclusive => "Read_exclusive"
+ | Read_exclusive_acquire =>
+ "Read_exclusive_acquire"
+ | Read_stream => "Read_stream"
+ | Read_RISCV_acquire => "Read_RISCV_acquire"
+ | Read_RISCV_strong_acquire =>
+ "Read_RISCV_strong_acquire"
+ | Read_RISCV_reserved =>
+ "Read_RISCV_reserved"
+ | Read_RISCV_reserved_acquire =>
+ "Read_RISCV_reserved_acquire"
+ | Read_RISCV_reserved_strong_acquire =>
+ "Read_RISCV_reserved_strong_acquire"
+ | Read_X86_locked => "Read_X86_locked"
+ )) read_kind))
+ | IK_mem_write write_kind => STRCAT "IK_mem_write "
+ (((\x . (case x of
+ Write_plain => "Write_plain"
+ | Write_conditional =>
+ "Write_conditional"
+ | Write_release => "Write_release"
+ | Write_exclusive => "Write_exclusive"
+ | Write_exclusive_release =>
+ "Write_exclusive_release"
+ | Write_RISCV_release =>
+ "Write_RISCV_release"
+ | Write_RISCV_strong_release =>
+ "Write_RISCV_strong_release"
+ | Write_RISCV_conditional =>
+ "Write_RISCV_conditional"
+ | Write_RISCV_conditional_release =>
+ "Write_RISCV_conditional_release"
+ | Write_RISCV_conditional_strong_release =>
+ "Write_RISCV_conditional_strong_release"
+ | Write_X86_locked => "Write_X86_locked"
+ )) write_kind))
+ | IK_mem_rmw (r, w) => STRCAT "IK_mem_rmw "
+ (STRCAT
+ (((\x . (case x of
+ Read_plain => "Read_plain"
+ | Read_reserve => "Read_reserve"
+ | Read_acquire => "Read_acquire"
+ | Read_exclusive => "Read_exclusive"
+ | Read_exclusive_acquire =>
+ "Read_exclusive_acquire"
+ | Read_stream => "Read_stream"
+ | Read_RISCV_acquire => "Read_RISCV_acquire"
+ | Read_RISCV_strong_acquire =>
+ "Read_RISCV_strong_acquire"
+ | Read_RISCV_reserved => "Read_RISCV_reserved"
+ | Read_RISCV_reserved_acquire =>
+ "Read_RISCV_reserved_acquire"
+ | Read_RISCV_reserved_strong_acquire =>
+ "Read_RISCV_reserved_strong_acquire"
+ | Read_X86_locked => "Read_X86_locked"
+ )) r))
+ (STRCAT " "
+ (((\x . (case x of
+ Write_plain => "Write_plain"
+ | Write_conditional =>
+ "Write_conditional"
+ | Write_release => "Write_release"
+ | Write_exclusive => "Write_exclusive"
+ | Write_exclusive_release =>
+ "Write_exclusive_release"
+ | Write_RISCV_release =>
+ "Write_RISCV_release"
+ | Write_RISCV_strong_release =>
+ "Write_RISCV_strong_release"
+ | Write_RISCV_conditional =>
+ "Write_RISCV_conditional"
+ | Write_RISCV_conditional_release =>
+ "Write_RISCV_conditional_release"
+ | Write_RISCV_conditional_strong_release =>
+ "Write_RISCV_conditional_strong_release"
+ | Write_X86_locked => "Write_X86_locked"
+ )) w))))
+ | IK_branch () => "IK_branch"
+ | IK_trans trans_kind => STRCAT "IK_trans "
+ (((\x . (case x of
+ Transaction_start => "Transaction_start"
+ | Transaction_commit => "Transaction_commit"
+ | Transaction_abort => "Transaction_abort"
+ )) trans_kind))
+ | IK_simple () => "IK_simple"
+ | IK_cache_op cache_kind => STRCAT "IK_cache_op "
+ (((\x . (case x of
+ Cache_op_D_IVAC => "Cache_op_D_IVAC"
+ | Cache_op_D_ISW => "Cache_op_D_ISW"
+ | Cache_op_D_CSW => "Cache_op_D_CSW"
+ | Cache_op_D_CISW => "Cache_op_D_CISW"
+ | Cache_op_D_ZVA => "Cache_op_D_ZVA"
+ | Cache_op_D_CVAC => "Cache_op_D_CVAC"
+ | Cache_op_D_CVAU => "Cache_op_D_CVAU"
+ | Cache_op_D_CIVAC => "Cache_op_D_CIVAC"
+ | Cache_op_I_IALLUIS =>
+ "Cache_op_I_IALLUIS"
+ | Cache_op_I_IALLU => "Cache_op_I_IALLU"
+ | Cache_op_I_IVAU => "Cache_op_I_IVAU"
+ )) cache_kind))
+ ))|>))`;
+
+
+
+val _ = Define `
+ ((read_is_exclusive:read_kind -> bool)=
+ (\x . (case x of
+ Read_plain => F
+ | Read_reserve => T
+ | Read_acquire => F
+ | Read_exclusive => T
+ | Read_exclusive_acquire => T
+ | Read_stream => F
+ | Read_RISCV_acquire => F
+ | Read_RISCV_strong_acquire => F
+ | Read_RISCV_reserved => T
+ | Read_RISCV_reserved_acquire => T
+ | Read_RISCV_reserved_strong_acquire => T
+ | Read_X86_locked => T
+ )))`;
+
+
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<|
+
+ toNat_method := (\x .
+ (case x of
+ Read_plain =>( 0 : num)
+ | Read_reserve =>( 1 : num)
+ | Read_acquire =>( 2 : num)
+ | Read_exclusive =>( 3 : num)
+ | Read_exclusive_acquire =>( 4 : num)
+ | Read_stream =>( 5 : num)
+ | Read_RISCV_acquire =>( 6 : num)
+ | Read_RISCV_strong_acquire =>( 7 : num)
+ | Read_RISCV_reserved =>( 8 : num)
+ | Read_RISCV_reserved_acquire =>( 9 : num)
+ | Read_RISCV_reserved_strong_acquire =>( 10 : num)
+ | Read_X86_locked =>( 11 : num)
+ ))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<|
+
+ toNat_method := (\x .
+ (case x of
+ Write_plain =>( 0 : num)
+ | Write_conditional =>( 1 : num)
+ | Write_release =>( 2 : num)
+ | Write_exclusive =>( 3 : num)
+ | Write_exclusive_release =>( 4 : num)
+ | Write_RISCV_release =>( 5 : num)
+ | Write_RISCV_strong_release =>( 6 : num)
+ | Write_RISCV_conditional =>( 7 : num)
+ | Write_RISCV_conditional_release =>( 8 : num)
+ | Write_RISCV_conditional_strong_release =>( 9 : num)
+ | Write_X86_locked =>( 10 : num)
+ ))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<|
+
+ toNat_method := (\x .
+ (case x of
+ Barrier_Sync =>( 0 : num)
+ | Barrier_LwSync =>( 1 : num)
+ | Barrier_Eieio =>( 2 : num)
+ | Barrier_Isync =>( 3 : num)
+ | Barrier_DMB =>( 4 : num)
+ | Barrier_DMB_ST =>( 5 : num)
+ | Barrier_DMB_LD =>( 6 : num)
+ | Barrier_DSB =>( 7 : num)
+ | Barrier_DSB_ST =>( 8 : num)
+ | Barrier_DSB_LD =>( 9 : num)
+ | Barrier_ISB =>( 10 : num)
+ | Barrier_TM_COMMIT =>( 11 : num)
+ | Barrier_MIPS_SYNC =>( 12 : num)
+ | Barrier_RISCV_rw_rw =>( 13 : num)
+ | Barrier_RISCV_r_rw =>( 14 : num)
+ | Barrier_RISCV_r_r =>( 15 : num)
+ | Barrier_RISCV_rw_w =>( 16 : num)
+ | Barrier_RISCV_w_w =>( 17 : num)
+ | Barrier_RISCV_w_rw =>( 18 : num)
+ | Barrier_RISCV_rw_r =>( 19 : num)
+ | Barrier_RISCV_r_w =>( 20 : num)
+ | Barrier_RISCV_w_r =>( 21 : num)
+ | Barrier_RISCV_tso =>( 22 : num)
+ | Barrier_RISCV_i =>( 23 : num)
+ | Barrier_x86_MFENCE =>( 24 : num)
+ ))|>))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_operatorsScript.sml b/prover_snapshots/hol4/lib/sail/sail2_operatorsScript.sml
new file mode 100644
index 0000000..af45ac4
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_operatorsScript.sml
@@ -0,0 +1,327 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+
+(*** Bit vector operations *)
+
+(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*)
+val _ = Define `
+ ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r= (
+ dict_Sail2_values_Bitvector_a.bits_of_method l ++ dict_Sail2_values_Bitvector_b.bits_of_method r))`;
+
+
+(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*)
+val _ = Define `
+ ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a b v= (b ::
+ dict_Sail2_values_Bitvector_a.bits_of_method v))`;
+
+
+(*val cast_unit_bv : bitU -> list bitU*)
+val _ = Define `
+ ((cast_unit_bv:bitU ->(bitU)list) b= ([b]))`;
+
+
+(*val bv_of_bit : integer -> bitU -> list bitU*)
+val _ = Define `
+ ((bv_of_bit:int -> bitU ->(bitU)list) len b= (extz_bits len [b]))`;
+
+
+val _ = Define `
+ ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail2_values_Bitvector_a v= ((case
+ dict_Sail2_values_Bitvector_a.bits_of_method v of
+ b :: _ => b
+ | _ => B0 (* Treat empty bitvector as all zeros *)
+ )))`;
+
+
+val _ = Define `
+ ((get_max_representable_in:bool -> int -> int) sign (n : int) : int=
+ (if (n =( 64 : int)) then (case sign of T => max_64 | F => max_64u )
+ else if (n=( 32 : int)) then (case sign of T => max_32 | F => max_32u )
+ else if (n=( 8 : int)) then max_8
+ else if (n=( 5 : int)) then max_5
+ else (case sign of T => (( 2 : int))** ((Num (ABS (I n))) -( 1 : num))
+ | F => (( 2 : int))** (Num (ABS (I n)))
+ )))`;
+
+
+val _ = Define `
+ ((get_min_representable_in:'a -> int -> int) _ (n : int) : int=
+ (if n =( 64 : int) then min_64
+ else if n =( 32 : int) then min_32
+ else if n =( 8 : int) then min_8
+ else if n =( 5 : int) then min_5
+ else( 0 : int) - ((( 2 : int))** (Num (ABS (I n))))))`;
+
+
+(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+val _ = Define `
+ ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail2_values_Bitvector_a op sign l r=
+ (let r' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r) in dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l r'))`;
+
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+val _ = Define `
+ ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail2_values_Bitvector_a op sign l r=
+ (let l' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method r) l) in dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l' r))`;
+
+
+val _ = Define `
+ ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a op sign l r= (arith_op_bv_int
+ dict_Sail2_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`;
+
+val _ = Define `
+ ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a op sign l) (bool_of_bitU r)))`;
+
+
+(* TODO (or just omit and define it per spec if needed)
+val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv op sign size l r =
+ let len = length l in
+ let act_size = len * size in
+ match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
+ | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
+ let n = op l_sign r_sign in
+ let n_unsign = op l_unsign r_unsign in
+ let correct_size = of_int act_size n in
+ let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
+ let overflow =
+ if n <= get_max_representable_in sign len &&
+ n >= get_min_representable_in sign len
+ then B0 else B1 in
+ let c_out = most_significant one_more_size_u in
+ (correct_size,overflow,c_out)
+ | (_, _, _, _) ->
+ (repeat [BU] act_size, BU, BU)
+ end
+
+let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
+let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
+let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
+let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
+let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
+let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv_bit op sign size l r_bit =
+ let act_size = length l * size in
+ match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
+ | (Just l', Just l_u, false) ->
+ let (n, nu, changed) = match r_bit with
+ | B1 -> (op l' 1, op l_u 1, true)
+ | B0 -> (l', l_u, false)
+ | BU -> (* unreachable due to check above *)
+ failwith "arith_op_overflow_bv_bit applied to undefined bit"
+ end in
+ let correct_size = of_int act_size n in
+ let one_larger = bits_of_int (act_size + 1) nu in
+ let overflow =
+ if changed
+ then
+ if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+ then B0 else B1
+ else B0 in
+ (correct_size, overflow, most_significant one_larger)
+ | (_, _, _) ->
+ (repeat [BU] act_size, BU, BU)
+ end
+
+let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
+let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
+let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
+let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*)
+
+val _ = Hol_datatype `
+ shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot`;
+
+
+val _ = Define `
+ ((invert_shift:shift -> shift)=
+ (\x . (case x of
+ LL_shift => RR_shift
+ | RR_shift => LL_shift
+ | RR_shift_arith => LL_shift
+ | LL_rot => RR_rot
+ | RR_rot => LL_rot
+ )))`;
+
+
+(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*)
+val _ = Define `
+ ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a op v n=
+ (let v = (dict_Sail2_values_Bitvector_a.bits_of_method v) in
+ if n =( 0 : int) then v else
+ let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in
+ (case op of
+ LL_shift =>
+ subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ repeat [B0] n
+ | RR_shift =>
+ repeat [B0] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
+ | RR_shift_arith =>
+ repeat [most_significant
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int))
+ | LL_rot =>
+ subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ subrange_list T v(( 0 : int)) (n -( 1 : int))
+ | RR_rot =>
+ subrange_list F v(( 0 : int)) (n -( 1 : int)) ++ subrange_list F v n (int_of_num (LENGTH v) -( 1 : int))
+ )))`;
+
+
+val _ = Define `
+ ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_shift))`;
+ (*"<<"*)
+val _ = Define `
+ ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv
+ dict_Sail2_values_Bitvector_a RR_shift))`;
+ (*">>"*)
+val _ = Define `
+ ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv
+ dict_Sail2_values_Bitvector_a RR_shift_arith))`;
+
+val _ = Define `
+ ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_rot))`;
+ (*"<<<"*)
+val _ = Define `
+ ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_rot))`;
+ (*">>>"*)
+
+val _ = Define `
+ ((shiftl_mword:'a words$word -> int -> 'a words$word) w n= (words$word_lsl w (nat_of_int n)))`;
+
+val _ = Define `
+ ((shiftr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_lsr w (nat_of_int n)))`;
+
+val _ = Define `
+ ((arith_shiftr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_asr w (nat_of_int n)))`;
+
+val _ = Define `
+ ((rotl_mword:'a words$word -> int -> 'a words$word) w n= (words$word_rol w (nat_of_int n)))`;
+
+val _ = Define `
+ ((rotr_mword:'a words$word -> int -> 'a words$word) w n= (words$word_ror w (nat_of_int n)))`;
+
+
+ val _ = Define `
+ ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r=
+ (if r =( 0 : int)
+ then NONE
+ else SOME (op l r)))`;
+
+
+(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*)
+val _ = Define `
+ ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r=
+ (OPTION_BIND (int_of_bv
+ dict_Sail2_values_Bitvector_a sign l) (\ l' .
+ OPTION_BIND (int_of_bv
+ dict_Sail2_values_Bitvector_a sign r) (\ r' .
+ if r' =( 0 : int) then NONE else SOME (
+ dict_Sail2_values_Bitvector_b.of_int_method (dict_Sail2_values_Bitvector_a.length_method l * size1) (op l' r'))))))`;
+
+
+val _ = Define `
+ ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a tmod_int F(( 1 : int))))`;
+
+val _ = Define `
+ ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a tdiv_int F(( 1 : int))))`;
+
+val _ = Define `
+ ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a tdiv_int T(( 1 : int))))`;
+
+
+val _ = Define `
+ ((mod_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_mod)`;
+
+val _ = Define `
+ ((quot_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_div)`;
+
+val _ = Define `
+ ((quots_mword:'a words$word -> 'a words$word -> 'a words$word)= words$word_quot)`;
+
+
+val _ = Define `
+ ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r=
+ (arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r)))`;
+
+
+val _ = Define `
+ ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_int_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a tdiv_int F(( 1 : int))))`;
+
+val _ = Define `
+ ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_int_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a tmod_int F(( 1 : int))))`;
+
+
+val _ = Define `
+ ((mod_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_mod l (integer_word$i2w r)))`;
+
+val _ = Define `
+ ((quot_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_div l (integer_word$i2w r)))`;
+
+val _ = Define `
+ ((quots_mword_int:'a words$word -> int -> 'a words$word) l r= (words$word_quot l (integer_word$i2w r)))`;
+
+
+val _ = Define `
+ ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v count1= (repeat (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) count1))`;
+
+val _ = Define `
+ ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail2_values_BitU_a bit len= (replicate_bits_bv
+ (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len))`;
+
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+val _ = Define `
+ ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r= (
+ dict_Sail2_values_Bitvector_a.bits_of_method l = dict_Sail2_values_Bitvector_a.bits_of_method r))`;
+
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+val _ = Define `
+ ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r= (~ (eq_bv
+ dict_Sail2_values_Bitvector_a l r)))`;
+
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)
+val _ = Define `
+ ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo=
+ (let hi = ((lo + len) -( 1 : int)) in
+ let bs = (bools_of_int (hi +( 1 : int)) n) in
+ dict_Sail2_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`;
+
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*)
+val _ = Define `
+ ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail2_values_Bitvector_a len n lo v=
+ (let hi = ((lo + len) -( 1 : int)) in
+ let bs = (bits_of_int (hi +( 1 : int)) n) in
+ maybe_failwith (signed_of_bits (update_subrange_list F bs hi lo (
+ dict_Sail2_values_Bitvector_a.bits_of_method v)))))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_operators_bitlistsScript.sml b/prover_snapshots/hol4/lib/sail/sail2_operators_bitlistsScript.sml
new file mode 100644
index 0000000..7055b1e
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_operators_bitlistsScript.sml
@@ -0,0 +1,746 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators_bitlists.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators_bitlists"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+
+(* Specialisation of operators to bit lists *)
+
+(*val uint_maybe : list bitU -> maybe integer*)
+val _ = Define `
+ ((uint_maybe0:(bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`;
+
+val _ = Define `
+ ((uint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v= (sail2_state_monad$maybe_failS "uint" (
+ dict_Sail2_values_Bitvector_a.unsigned_method v)))`;
+
+val _ = Define `
+ ((uint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS
+ (sail2_state$bools_of_bits_nondetS v) (\ bs .
+ sail2_state_monad$returnS (int_of_bools F bs))))`;
+
+val _ = Define `
+ ((uint:(bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`;
+
+
+(*val sint_maybe : list bitU -> maybe integer*)
+val _ = Define `
+ ((sint_maybe0:(bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`;
+
+val _ = Define `
+ ((sint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v= (sail2_state_monad$maybe_failS "sint" (
+ dict_Sail2_values_Bitvector_a.signed_method v)))`;
+
+val _ = Define `
+ ((sint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS
+ (sail2_state$bools_of_bits_nondetS v) (\ bs .
+ sail2_state_monad$returnS (int_of_bools T bs))))`;
+
+val _ = Define `
+ ((sint:(bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`;
+
+
+(*val extz_vec : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((extz_vec0:int ->(bitU)list ->(bitU)list)=
+ (extz_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val exts_vec : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((exts_vec0:int ->(bitU)list ->(bitU)list)=
+ (exts_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val zero_extend : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len= (extz_bits len bits))`;
+
+
+(*val sign_extend : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len= (exts_bits len bits))`;
+
+
+(*val zeros : integer -> list bitU*)
+val _ = Define `
+ ((zeros0:int ->(bitU)list) len= (repeat [B0] len))`;
+
+
+(*val vector_truncate : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len= (extz_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs))`;
+
+
+(*val vector_truncateLSB : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((vector_truncateLSB0:(bitU)list -> int ->(bitU)list) bs len= (take_list len bs))`;
+
+
+(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*)
+(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*)
+(*val vec_of_bits_failwith : list bitU -> list bitU*)
+(*val vec_of_bits : list bitU -> list bitU*)
+
+(*val access_vec_inc : list bitU -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_inc0:(bitU)list -> int -> bitU)=
+ (access_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val access_vec_dec : list bitU -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_dec0:(bitU)list -> int -> bitU)=
+ (access_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*)
+val _ = Define `
+ ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)=
+ (update_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_inc0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_inc_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_inc0 v i b)))`;
+
+
+(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*)
+val _ = Define `
+ ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)=
+ (update_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_dec0 v i b)))`;
+
+val _ = Define `
+ ((update_vec_dec_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_dec0 v i b)))`;
+
+
+(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)=
+ (subrange_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)=
+ (subrange_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)=
+ (update_subrange_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)=
+ (update_subrange_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val concat_vec : list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)=
+ (concat_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val cons_vec : bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((cons_vec0:bitU ->(bitU)list ->(bitU)list)=
+ (cons_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v= (SOME (cons_vec0 b v)))`;
+
+val _ = Define `
+ ((cons_vec_fail0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v= (sail2_state_monad$returnS (cons_vec0 b v)))`;
+
+val _ = Define `
+ ((cons_vec_nondet0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v= (sail2_state_monad$returnS (cons_vec0 b v)))`;
+
+
+(*val cast_unit_vec : bitU -> list bitU*)
+val _ = Define `
+ ((cast_unit_vec0:bitU ->(bitU)list)= cast_unit_bv)`;
+
+val _ = Define `
+ ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b= (SOME (cast_unit_vec0 b)))`;
+
+val _ = Define `
+ ((cast_unit_vec_fail0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$returnS (cast_unit_vec0 b)))`;
+
+val _ = Define `
+ ((cast_unit_vec_nondet0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$returnS (cast_unit_vec0 b)))`;
+
+
+(*val vec_of_bit : integer -> bitU -> list bitU*)
+val _ = Define `
+ ((vec_of_bit0:int -> bitU ->(bitU)list)= bv_of_bit)`;
+
+val _ = Define `
+ ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`;
+
+val _ = Define `
+ ((vec_of_bit_fail0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$returnS (vec_of_bit0 len b)))`;
+
+val _ = Define `
+ ((vec_of_bit_nondet0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$returnS (vec_of_bit0 len b)))`;
+
+
+(*val msb : list bitU -> bitU*)
+val _ = Define `
+ ((msb0:(bitU)list -> bitU)=
+ (most_significant
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*)
+val _ = Define `
+ ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)=
+ (int_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((int_of_vec_fail0:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v= (sail2_state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`;
+
+val _ = Define `
+ ((int_of_vec_nondet:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v= (sail2_state_monad$bindS (sail2_state$bools_of_bits_nondetS v) (\ v . sail2_state_monad$returnS (int_of_bools sign v))))`;
+
+val _ = Define `
+ ((int_of_vec0:bool ->(bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`;
+
+
+(*val string_of_bits : list bitU -> string*)
+val _ = Define `
+ ((string_of_bits0:(bitU)list -> string)=
+ (string_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val decimal_string_of_bits : list bitU -> string*)
+val _ = Define `
+ ((decimal_string_of_bits0:(bitU)list -> string)=
+ (decimal_string_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val and_vec : list bitU -> list bitU -> list bitU*)
+(*val or_vec : list bitU -> list bitU -> list bitU*)
+(*val xor_vec : list bitU -> list bitU -> list bitU*)
+(*val not_vec : list bitU -> list bitU*)
+val _ = Define `
+ ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list and_bit))`;
+
+val _ = Define `
+ ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list or_bit))`;
+
+val _ = Define `
+ ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list xor_bit))`;
+
+val _ = Define `
+ ((not_vec0:(bitU)list ->(bitU)list)= (MAP not_bit))`;
+
+
+(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*)
+val _ = Define `
+ ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a op sign l r=
+ (let len =(( 2 : int) *
+ dict_Sail2_values_Bitvector_a.length_method l) in
+ let l' = (if sign then exts_bv
+ dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in
+ let r' = (if sign then exts_bv
+ dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in
+ MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`;
+
+
+(*val add_vec : list bitU -> list bitU -> list bitU*)
+(*val adds_vec : list bitU -> list bitU -> list bitU*)
+(*val sub_vec : list bitU -> list bitU -> list bitU*)
+(*val subs_vec : list bitU -> list bitU -> list bitU*)
+(*val mult_vec : list bitU -> list bitU -> list bitU*)
+(*val mults_vec : list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`;
+
+val _ = Define `
+ ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F))`;
+
+val _ = Define `
+ ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T))`;
+
+
+(*val add_vec_int : list bitU -> integer -> list bitU*)
+(*val sub_vec_int : list bitU -> integer -> list bitU*)
+(*val mult_vec_int : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((add_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
+
+val _ = Define `
+ ((sub_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
+
+val _ = Define `
+ ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`;
+
+
+(*val add_int_vec : integer -> list bitU -> list bitU*)
+(*val sub_int_vec : integer -> list bitU -> list bitU*)
+(*val mult_int_vec : integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((add_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`;
+
+val _ = Define `
+ ((sub_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`;
+
+val _ = Define `
+ ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`;
+
+
+(*val add_vec_bit : list bitU -> bitU -> list bitU*)
+(*val adds_vec_bit : list bitU -> bitU -> list bitU*)
+(*val sub_vec_bit : list bitU -> bitU -> list bitU*)
+(*val subs_vec_bit : list bitU -> bitU -> list bitU*)
+
+val _ = Define `
+ ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0
+ dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((add_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (add_vec_bool0
+ dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (add_vec_bit_maybe0
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (+) T l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (+) T l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0
+ dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((adds_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (adds_vec_bool0
+ dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (adds_vec_bit_maybe0
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0
+ dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((sub_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (sub_vec_bool0
+ dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (sub_vec_bit_maybe0
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+val _ = Define `
+ ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (-) T l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (-) T l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0
+ dict_Sail2_values_Bitvector_a l r)))`;
+
+val _ = Define `
+ ((subs_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (subs_vec_bool0
+ dict_Sail2_values_Bitvector_a l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (subs_vec_bit_maybe0
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+
+(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec = add_overflow_bv
+let add_overflow_vec_signed = add_overflow_bv_signed
+let sub_overflow_vec = sub_overflow_bv
+let sub_overflow_vec_signed = sub_overflow_bv_signed
+let mult_overflow_vec = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit = add_overflow_bv_bit
+let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*)
+
+(*val shiftl : list bitU -> integer -> list bitU*)
+(*val shiftr : list bitU -> integer -> list bitU*)
+(*val arith_shiftr : list bitU -> integer -> list bitU*)
+(*val rotl : list bitU -> integer -> list bitU*)
+(*val rotr : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((shiftl0:(bitU)list -> int ->(bitU)list)=
+ (shiftl_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((shiftr0:(bitU)list -> int ->(bitU)list)=
+ (shiftr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((arith_shiftr0:(bitU)list -> int ->(bitU)list)=
+ (arith_shiftr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((rotl0:(bitU)list -> int ->(bitU)list)=
+ (rotl_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((rotr0:(bitU)list -> int ->(bitU)list)=
+ (rotr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val mod_vec : list bitU -> list bitU -> list bitU*)
+(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*)
+(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec" (mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((mod_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec0 l r)))`;
+
+
+(*val quot_vec : list bitU -> list bitU -> list bitU*)
+(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec" (quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quot_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec0 l r)))`;
+
+
+(*val quots_vec : list bitU -> list bitU -> list bitU*)
+(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*)
+(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+(*val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quots_vec" (quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quots_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec0 l r)))`;
+
+
+(*val mod_vec_int : list bitU -> integer -> list bitU*)
+(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*)
+(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((mod_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((mod_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((mod_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int0 l r)))`;
+
+
+(*val quot_vec_int : list bitU -> integer -> list bitU*)
+(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*)
+(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*)
+val _ = Define `
+ ((quot_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`;
+
+val _ = Define `
+ ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`;
+
+val _ = Define `
+ ((quot_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`;
+
+val _ = Define `
+ ((quot_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int0 l r)))`;
+
+
+(*val replicate_bits : list bitU -> integer -> list bitU*)
+val _ = Define `
+ ((replicate_bits0:(bitU)list -> int ->(bitU)list)=
+ (replicate_bits_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val duplicate : bitU -> integer -> list bitU*)
+val _ = Define `
+ ((duplicate0:bitU -> int ->(bitU)list)=
+ (duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict))`;
+
+val _ = Define `
+ ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n= (SOME (duplicate0 b n)))`;
+
+val _ = Define `
+ ((duplicate_fail0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$returnS (duplicate0 b n)))`;
+
+val _ = Define `
+ ((duplicate_nondet0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS
+ (sail2_state$bool_of_bitU_nondetS b) (\ b .
+ sail2_state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`;
+
+
+(*val reverse_endianness : list bitU -> list bitU*)
+val _ = Define `
+ ((reverse_endianness0:(bitU)list ->(bitU)list) v= (reverse_endianness_list v))`;
+
+
+(*val get_slice_int : integer -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((get_slice_int0:int -> int -> int ->(bitU)list)=
+ (get_slice_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*)
+val _ = Define `
+ ((set_slice_int0:int -> int -> int ->(bitU)list -> int)=
+ (set_slice_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+
+(*val slice : list bitU -> integer -> integer -> list bitU*)
+val _ = Define `
+ ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len=
+ (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`;
+
+
+(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*)
+val _ = Define `
+ ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v=
+ (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`;
+
+
+(*val eq_vec : list bitU -> list bitU -> bool*)
+(*val neq_vec : list bitU -> list bitU -> bool*)
+val _ = Define `
+ ((eq_vec:(bitU)list ->(bitU)list -> bool)=
+ (eq_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = Define `
+ ((neq_vec:(bitU)list ->(bitU)list -> bool)=
+ (neq_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_operators_mwordsScript.sml b/prover_snapshots/hol4/lib/sail/sail2_operators_mwordsScript.sml
new file mode 100644
index 0000000..5736b29
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_operators_mwordsScript.sml
@@ -0,0 +1,627 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_operators_mwords.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_operators_mwords"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail2_values*)
+(*open import Sail2_operators*)
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_prompt*)
+val _ = Define `
+ ((uint_maybe:'a words$word ->(int)option) v= (SOME (lem$w2ui v)))`;
+
+val _ = Define `
+ ((uint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (lem$w2ui v)))`;
+
+val _ = Define `
+ ((uint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (lem$w2ui v)))`;
+
+val _ = Define `
+ ((sint_maybe:'a words$word ->(int)option) v= (SOME (integer_word$w2i v)))`;
+
+val _ = Define `
+ ((sint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (integer_word$w2i v)))`;
+
+val _ = Define `
+ ((sint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (integer_word$w2i v)))`;
+
+
+(*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*)
+(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_nondet : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*)
+(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*)
+(*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*)
+val _ = Define `
+ ((vec_of_bits_maybe:(bitU)list ->('a words$word)option) bits= (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`;
+
+val _ = Define `
+ ((vec_of_bits_fail:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits= (sail2_state$of_bits_failS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits_nondet:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits= (sail2_state$of_bits_nondetS
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits_failwith:(bitU)list -> 'a words$word) bits= (of_bits_failwith
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+val _ = Define `
+ ((vec_of_bits:(bitU)list -> 'a words$word) bits= (of_bits_failwith
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`;
+
+
+(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_inc:'a words$word -> int -> bitU)=
+ (access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_vec_dec:'a words$word -> int -> bitU)=
+ (access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+val _ = Define `
+ ((update_vec_dec_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_dec w i b))`;
+
+val _ = Define `
+ ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS
+ (sail2_state$bool_of_bitU_fail b) (\ b .
+ sail2_state_monad$returnS (update_mword_bool_dec w i b))))`;
+
+val _ = Define `
+ ((update_vec_dec_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS
+ (sail2_state$bool_of_bitU_nondetS b) (\ b .
+ sail2_state_monad$returnS (update_mword_bool_dec w i b))))`;
+
+val _ = Define `
+ ((update_vec_dec:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_dec_maybe w i b)))`;
+
+
+val _ = Define `
+ ((update_vec_inc_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_inc w i b))`;
+
+val _ = Define `
+ ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS
+ (sail2_state$bool_of_bitU_fail b) (\ b .
+ sail2_state_monad$returnS (update_mword_bool_inc w i b))))`;
+
+val _ = Define `
+ ((update_vec_inc_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS
+ (sail2_state$bool_of_bitU_nondetS b) (\ b .
+ sail2_state_monad$returnS (update_mword_bool_inc w i b))))`;
+
+val _ = Define `
+ ((update_vec_inc:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_inc_maybe w i b)))`;
+
+
+(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((subrange_vec_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int i) (nat_of_int j) w))`;
+
+
+(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((subrange_vec_inc:'a words$word -> int -> int -> 'b words$word) w i j= (subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j)))`;
+
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_subrange_vec_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int i) (nat_of_int j) w' w))`;
+
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_subrange_vec_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (update_subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j) w'))`;
+
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((extz_vec:int -> 'a words$word -> 'b words$word) _ w= (words$w2w w))`;
+
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((exts_vec:int -> 'a words$word -> 'b words$word) _ w= (words$sw2sw w))`;
+
+
+(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((zero_extend:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`;
+
+
+(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((sign_extend:'a words$word -> int -> 'b words$word) w _= (words$sw2sw w))`;
+
+
+(*val zeros : forall 'a. Size 'a => integer -> mword 'a*)
+val _ = Define `
+ ((zeros:int -> 'a words$word) _= (words$n2w(( 0:num))))`;
+
+
+(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((vector_truncate:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`;
+
+
+(*val vector_truncateLSB : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((vector_truncateLSB:'a words$word -> int -> 'b words$word) w len=
+ (let len = (nat_of_int len) in
+ let lo = (words$word_len w - len) in
+ let hi = ((lo + len) -( 1 : num)) in
+ words$word_extract hi lo w))`;
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+val _ = Define `
+ ((concat_vec:'a words$word -> 'b words$word -> 'c words$word)= words$word_concat)`;
+
+
+(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((cons_vec_bool:bool -> 'a words$word -> 'b words$word) b w= (bitstring$v2w (b :: bitstring$w2v w)))`;
+
+val _ = Define `
+ ((cons_vec_maybe:bitU -> 'c words$word ->('b words$word)option) b w= (OPTION_MAP (\ b . cons_vec_bool b w) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((cons_vec_fail:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (cons_vec_bool b w))))`;
+
+val _ = Define `
+ ((cons_vec_nondet:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (cons_vec_bool b w))))`;
+
+val _ = Define `
+ ((cons_vec:bitU -> 'a words$word -> 'b words$word) b w= (maybe_failwith (cons_vec_maybe b w)))`;
+
+
+(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*)
+val _ = Define `
+ ((vec_of_bool:int -> bool -> 'a words$word) _ b= (bitstring$v2w [b]))`;
+
+val _ = Define `
+ ((vec_of_bit_maybe:int -> bitU ->('a words$word)option) len b= (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((vec_of_bit_fail:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (vec_of_bool len b))))`;
+
+val _ = Define `
+ ((vec_of_bit_nondet:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (vec_of_bool len b))))`;
+
+val _ = Define `
+ ((vec_of_bit:int -> bitU -> 'a words$word) len b= (maybe_failwith (vec_of_bit_maybe len b)))`;
+
+
+(*val cast_bool_vec : bool -> mword ty1*)
+val _ = Define `
+ ((cast_bool_vec:bool ->(1)words$word) b= (vec_of_bool(( 1 : int)) b))`;
+
+val _ = Define `
+ ((cast_unit_vec_maybe:bitU ->('a words$word)option) b= (vec_of_bit_maybe(( 1 : int)) b))`;
+
+val _ = Define `
+ ((cast_unit_vec_fail:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (cast_bool_vec b))))`;
+
+val _ = Define `
+ ((cast_unit_vec_nondet:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (cast_bool_vec b))))`;
+
+val _ = Define `
+ ((cast_unit_vec:bitU -> 'a words$word) b= (maybe_failwith (cast_unit_vec_maybe b)))`;
+
+
+(*val msb : forall 'a. Size 'a => mword 'a -> bitU*)
+val _ = Define `
+ ((msb:'a words$word -> bitU)=
+ (most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*)
+val _ = Define `
+ ((int_of_vec:bool -> 'a words$word -> int) sign w=
+ (if sign
+ then integer_word$w2i w
+ else lem$w2ui w))`;
+
+val _ = Define `
+ ((int_of_vec_maybe:bool -> 'a words$word ->(int)option) sign w= (SOME (int_of_vec sign w)))`;
+
+val _ = Define `
+ ((int_of_vec_fail:bool -> 'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) sign w= (sail2_state_monad$returnS (int_of_vec sign w)))`;
+
+
+(*val string_of_bits : forall 'a. Size 'a => mword 'a -> string*)
+val _ = Define `
+ ((string_of_bits:'a words$word -> string)=
+ (string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val decimal_string_of_bits : forall 'a. Size 'a => mword 'a -> string*)
+val _ = Define `
+ ((decimal_string_of_bits:'a words$word -> string)=
+ (decimal_string_of_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+val _ = Define `
+ ((and_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_and)`;
+
+val _ = Define `
+ ((or_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_or)`;
+
+val _ = Define `
+ ((xor_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_xor)`;
+
+val _ = Define `
+ ((not_vec:'a words$word -> 'a words$word)= words$word_1comp)`;
+
+
+(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val adds_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val subs_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((add_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword F l) + (int_of_mword F r))))`;
+
+val _ = Define `
+ ((adds_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword T l) + (int_of_mword T r))))`;
+
+val _ = Define `
+ ((sub_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword F l) - (int_of_mword F r))))`;
+
+val _ = Define `
+ ((subs_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword T l) - (int_of_mword T r))))`;
+
+val _ = Define `
+ ((mult_vec:'a words$word -> 'a words$word -> 'b words$word) l r= (integer_word$i2w ((int_of_mword F (words$w2w l : 'b words$word)) * (int_of_mword F (words$w2w r : 'b words$word)))))`;
+
+val _ = Define `
+ ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r= (integer_word$i2w ((int_of_mword T (words$sw2sw l : 'b words$word)) * (int_of_mword T (words$sw2sw r : 'b words$word)))))`;
+
+
+(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((add_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`;
+
+val _ = Define `
+ ((sub_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((mult_vec_int:'a words$word -> int -> 'b words$word) l r= (arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) F (words$w2w l : 'b words$word) r))`;
+
+
+(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*)
+(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+val _ = Define `
+ ((add_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`;
+
+val _ = Define `
+ ((sub_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((mult_int_vec:int -> 'a words$word -> 'b words$word) l r= (arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) F l (words$w2w r : 'b words$word)))`;
+
+
+(*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val sub_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*)
+
+val _ = Define `
+ ((add_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`;
+
+val _ = Define `
+ ((add_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((add_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (add_vec_bool l r))))`;
+
+val _ = Define `
+ ((add_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (add_vec_bool l r))))`;
+
+val _ = Define `
+ ((add_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (add_vec_bit_maybe l r)))`;
+
+
+val _ = Define `
+ ((adds_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) T l r))`;
+
+val _ = Define `
+ ((adds_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((adds_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (adds_vec_bool l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (adds_vec_bool l r))))`;
+
+val _ = Define `
+ ((adds_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (adds_vec_bit_maybe l r)))`;
+
+
+val _ = Define `
+ ((sub_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`;
+
+val _ = Define `
+ ((sub_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((sub_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (sub_vec_bool l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (sub_vec_bool l r))))`;
+
+val _ = Define `
+ ((sub_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (sub_vec_bit_maybe l r)))`;
+
+
+val _ = Define `
+ ((subs_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T l r))`;
+
+val _ = Define `
+ ((subs_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`;
+
+val _ = Define `
+ ((subs_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (subs_vec_bool l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (subs_vec_bool l r))))`;
+
+val _ = Define `
+ ((subs_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (subs_vec_bit_maybe l r)))`;
+
+
+(* TODO
+val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
+let maybe_mword_of_bits_overflow (bits, overflow, carry) =
+ Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
+
+val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val adds_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val subs_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+let add_overflow_vec l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
+let adds_overflow_vec l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
+let sub_overflow_vec l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
+let subs_overflow_vec l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
+let mult_overflow_vec l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
+let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
+
+val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+let add_overflow_vec_bit = add_overflow_bv_bit
+let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*)
+
+(*val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+val _ = Define `
+ ((shiftl:'a words$word -> int -> 'a words$word)= shiftl_mword)`;
+
+val _ = Define `
+ ((shiftr:'a words$word -> int -> 'a words$word)= shiftr_mword)`;
+
+val _ = Define `
+ ((arith_shiftr:'a words$word -> int -> 'a words$word)= arith_shiftr_mword)`;
+
+val _ = Define `
+ ((rotl:'a words$word -> int -> 'a words$word)= rotl_mword)`;
+
+val _ = Define `
+ ((rotr:'a words$word -> int -> 'a words$word)= rotr_mword)`;
+
+
+(*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mod_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (mod_mword l r))`;
+
+val _ = Define `
+ ((mod_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (mod_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec" (mod_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((mod_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+ ((case (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ SOME w => sail2_state_monad$returnS w
+ | NONE => sail2_state$mword_nondetS ()
+ )))`;
+
+
+(*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quot_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quot_mword l r))`;
+
+val _ = Define `
+ ((quot_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quot_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec" (quot_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quot_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+ ((case (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ SOME w => sail2_state_monad$returnS w
+ | NONE => sail2_state$mword_nondetS ()
+ )))`;
+
+
+(*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*)
+(*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*)
+(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+(*val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quots_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quots_mword l r))`;
+
+val _ = Define `
+ ((quots_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quots_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quots_vec" (quots_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quots_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+ ((case (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ SOME w => sail2_state_monad$returnS w
+ | NONE => sail2_state$mword_nondetS ()
+ )))`;
+
+
+(*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mod_vec_int:'a words$word -> int -> 'a words$word) l r= (mod_mword_int l r))`;
+
+val _ = Define `
+ ((mod_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (mod_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((mod_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((mod_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+ ((case (mod_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ SOME w => sail2_state_monad$returnS w
+ | NONE => sail2_state$mword_nondetS ()
+ )))`;
+
+
+(*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*)
+(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+(*val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((quot_vec_int:'a words$word -> int -> 'a words$word) l r= (quot_mword_int l r))`;
+
+val _ = Define `
+ ((quot_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`;
+
+val _ = Define `
+ ((quot_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`;
+
+val _ = Define `
+ ((quot_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r=
+ ((case (quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ SOME w => sail2_state_monad$returnS w
+ | NONE => sail2_state$mword_nondetS ()
+ )))`;
+
+
+(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+val _ = Define `
+ ((replicate_bits:'a words$word -> int -> 'b words$word) v count1= (bitstring$v2w (repeat (bitstring$w2v v) count1)))`;
+
+
+(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*)
+val _ = Define `
+ ((duplicate_bool:bool -> int -> 'a words$word) b n= (bitstring$v2w (repeat [b] n)))`;
+
+val _ = Define `
+ ((duplicate_maybe:bitU -> int ->('a words$word)option) b n= (OPTION_MAP (\ b . duplicate_bool b n) (bool_of_bitU b)))`;
+
+val _ = Define `
+ ((duplicate_fail:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (duplicate_bool b n))))`;
+
+val _ = Define `
+ ((duplicate_nondet:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (duplicate_bool b n))))`;
+
+val _ = Define `
+ ((duplicate:bitU -> int -> 'a words$word) b n= (maybe_failwith (duplicate_maybe b n)))`;
+
+
+(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*)
+val _ = Define `
+ ((reverse_endianness:'a words$word -> 'a words$word) v= (bitstring$v2w (reverse_endianness_list (bitstring$w2v v))))`;
+
+
+(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*)
+val _ = Define `
+ ((get_slice_int:int -> int -> int -> 'a words$word)=
+ (get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*)
+val _ = Define `
+ ((set_slice_int:int -> int -> int -> 'a words$word -> int)=
+ (set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`;
+
+
+(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice:'a words$word -> int -> int -> 'b words$word) v lo len=
+ (subrange_vec_dec v ((lo + len) -( 1 : int)) lo))`;
+
+
+(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((set_slice:int -> int -> 'a words$word -> int -> 'b words$word -> 'a words$word) (out_len:ii) (slice_len:ii) out (n:ii) v=
+ (update_subrange_vec_dec out ((n + slice_len) -( 1 : int)) n v))`;
+
+
+(*val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+(*val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+
+(*val count_leading_zeros : forall 'a. Size 'a => mword 'a -> integer*)
+val _ = Define `
+ ((count_leading_zeros:'a words$word -> int) v= (count_leading_zeros_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict v))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_promptScript.sml b/prover_snapshots/hol4/lib/sail/sail2_promptScript.sml
new file mode 100644
index 0000000..629c902
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_promptScript.sml
@@ -0,0 +1,15 @@
+(*Generated by Lem from sail2_prompt.lem.*)
+open HolKernel Parse boolLib bossLib;
+open sail2_prompt_monadTheory sail2_state_monadTheory sail2_stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_prompt"
+
+(*open import Sail2_prompt_monad*)
+(*open import Sail2_state_monad*)
+(*open import Sail2_state*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_prompt_monadScript.sml b/prover_snapshots/hol4/lib/sail/sail2_prompt_monadScript.sml
new file mode 100644
index 0000000..cd49cd5
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_prompt_monadScript.sml
@@ -0,0 +1,34 @@
+(*Generated by Lem from sail2_prompt_monad.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory sail2_state_monadTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_prompt_monad"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+(*open import Sail2_state_monad*)
+
+(* Fake interface of the prompt monad by redirecting to the state monad, since
+ the former is not currently supported by HOL4 *)
+
+val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) monadS``);
+val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) monadRS``);
+
+(* We need to use a target_rep for these because HOL doesn't handle unused
+ type parameters well. *)
+
+(*type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e*)
+(*type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e*)
+val _ = Define `
+ ((barrier:'c -> 'a sequential_state ->(((unit),'b)result#'a sequential_state)set) _= (returnS () ))`;
+
+val _ = Define `
+ ((footprint:'c -> 'a sequential_state ->(((unit),'b)result#'a sequential_state)set) _= (returnS () ))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_stateAuxiliaryScript.sml b/prover_snapshots/hol4/lib/sail/sail2_stateAuxiliaryScript.sml
new file mode 100644
index 0000000..4d70b03
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_stateAuxiliaryScript.sml
@@ -0,0 +1,61 @@
+(*Generated by Lem from ../../src/gen_lib/state.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory sail2_stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_stateAuxiliary"
+
+
+(****************************************************)
+(* *)
+(* Termination Proofs *)
+(* *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (iterS_aux_def, iterS_aux_ind) *)
+val (iterS_aux_rw, iterS_aux_ind_rw) =
+ Defn.tprove_no_defn ((iterS_aux_def, iterS_aux_ind),
+ WF_REL_TAC`measure (LENGTH o SND o SND)` \\ rw[]
+ )
+val iterS_aux_rw = save_thm ("iterS_aux_rw", iterS_aux_rw);
+val iterS_aux_ind_rw = save_thm ("iterS_aux_ind_rw", iterS_aux_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (foreachS_def, foreachS_ind) *)
+val (foreachS_rw, foreachS_ind_rw) =
+ Defn.tprove_no_defn ((foreachS_def, foreachS_ind),
+ WF_REL_TAC`measure (LENGTH o FST)` \\ rw[]
+ )
+val foreachS_rw = save_thm ("foreachS_rw", foreachS_rw);
+val foreachS_ind_rw = save_thm ("foreachS_ind_rw", foreachS_ind_rw);
+
+
+(*
+These are unprovable.
+
+(* val gst = Defn.tgoal_no_defn (whileS_def, whileS_ind) *)
+val (whileS_rw, whileS_ind_rw) =
+ Defn.tprove_no_defn ((whileS_def, whileS_ind),
+ cheat (* the termination proof *)
+ )
+val whileS_rw = save_thm ("whileS_rw", whileS_rw);
+val whileS_ind_rw = save_thm ("whileS_ind_rw", whileS_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (untilS_def, untilS_ind) *)
+val (untilS_rw, untilS_ind_rw) =
+ Defn.tprove_no_defn ((untilS_def, untilS_ind),
+ cheat (* the termination proof *)
+ )
+val untilS_rw = save_thm ("untilS_rw", untilS_rw);
+val untilS_ind_rw = save_thm ("untilS_ind_rw", untilS_ind_rw);
+*)
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_stateScript.sml b/prover_snapshots/hol4/lib/sail/sail2_stateScript.sml
new file mode 100644
index 0000000..a19a974
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_stateScript.sml
@@ -0,0 +1,156 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_state.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_state"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_values*)
+(*open import Sail2_state_monad*)
+(*open import {isabelle} `Sail2_state_monad_lemmas`*)
+
+(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+ val iterS_aux_defn = Hol_defn "iterS_aux" `
+ ((iterS_aux:int ->(int -> 'a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) i f xs= ((case xs of
+ x :: xs => seqS (f i x) (iterS_aux (i +( 1 : int)) f xs)
+ | [] => returnS ()
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn iterS_aux_defn;
+
+(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+val _ = Define `
+ ((iteriS:(int -> 'a ->('rv,(unit),'e)monadS) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs= (iterS_aux(( 0 : int)) f xs))`;
+
+
+(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*)
+val _ = Define `
+ ((iterS:('a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs= (iteriS (\i x .
+ (case (i ,x ) of ( _ , x ) => f x )) xs))`;
+
+
+(*val foreachS : forall 'a 'rv 'vars 'e.
+ list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val foreachS_defn = Hol_defn "foreachS" `
+ ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) xs vars body= ((case xs of
+ [] => returnS vars
+ | x :: xs => bindS
+ (body x vars) (\ vars .
+ foreachS xs vars body)
+)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreachS_defn;
+
+(*val genlistS : forall 'a 'rv 'e. (nat -> monadS 'rv 'a 'e) -> nat -> monadS 'rv (list 'a) 'e*)
+val _ = Define `
+ ((genlistS:(num -> 'rv sequential_state ->(('a,'e)result#'rv sequential_state)set) -> num -> 'rv sequential_state ->((('a list),'e)result#'rv sequential_state)set) f n=
+ (let indices = (GENLIST (\ n . n) n) in
+ foreachS indices [] (\ n xs . ( bindS(f n) (\ x . returnS (xs ++ [x]))))))`;
+
+
+(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((and_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r= (bindS l (\ l . if l then r else returnS F)))`;
+
+
+(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((or_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r= (bindS l (\ l . if l then returnS T else r)))`;
+
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((bool_of_bitU_fail:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)=
+ (\x . (case x of
+ B0 => returnS F
+ | B1 => returnS T
+ | BU => failS "bool_of_bitU"
+ )))`;
+
+
+(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*)
+val _ = Define `
+ ((bool_of_bitU_nondetS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)=
+ (\x . (case x of
+ B0 => returnS F
+ | B1 => returnS T
+ | BU => undefined_boolS ()
+ )))`;
+
+
+(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*)
+val _ = Define `
+ ((bools_of_bits_nondetS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits=
+ (foreachS bits []
+ (\ b bools . bindS
+ (bool_of_bitU_nondetS b) (\ b .
+ returnS (bools ++ [b])))))`;
+
+
+(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((of_bits_nondetS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits= (bindS
+ (bools_of_bits_nondetS bits) (\ bs .
+ returnS (dict_Sail2_values_Bitvector_a.of_bools_method bs))))`;
+
+
+(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits= (maybe_failS "of_bits" (
+ dict_Sail2_values_Bitvector_a.of_bits_method bits)))`;
+
+
+(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*)
+val _ = Define `
+ ((mword_nondetS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () = (bindS
+ (bools_of_bits_nondetS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs .
+ returnS (bitstring$v2w bs))))`;
+
+
+
+(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val whileS_defn = Hol_defn "whileS" `
+ ((whileS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
+ (( bindS(cond vars) (\ cond_val s' .
+ if cond_val then
+ ( bindS(body vars) (\ vars s'' . whileS vars cond body s'')) s'
+ else returnS vars s')) s))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn whileS_defn;
+
+(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*)
+ val untilS_defn = Hol_defn "untilS" `
+ ((untilS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s=
+ (( bindS(body vars) (\ vars s' .
+ ( bindS(cond vars) (\ cond_val s'' .
+ if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn untilS_defn;
+
+(*val choose_boolsS : forall 'rv 'e. nat -> monadS 'rv (list bool) 'e*)
+val _ = Define `
+ ((choose_boolsS:num -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) n= (genlistS (\n .
+ (case (n ) of ( _ ) => choose_boolS () )) n))`;
+
+
+(* TODO: Replace by chooseS and prove equivalence to prompt monad version *)
+(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*)
+val _ = Define `
+ ((internal_pickS:'a list -> 'rv sequential_state ->(('a,'e)result#'rv sequential_state)set) xs= (bindS
+ (
+ (* Use sufficiently many nondeterministically chosen bits and convert into an
+ index into the list *)choose_boolsS (LENGTH xs)) (\ bs .
+ let idx = ((((nat_of_bools bs):num)) MOD LENGTH xs) in
+ (case list_index xs idx of
+ SOME x => returnS x
+ | NONE => failS "choose internal_pick"
+ ))))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_state_monadScript.sml b/prover_snapshots/hol4/lib/sail/sail2_state_monadScript.sml
new file mode 100644
index 0000000..6af7a24
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_state_monadScript.sml
@@ -0,0 +1,370 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_state_monad.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_state_monad"
+
+(*open import Pervasives_extra*)
+(*open import Sail2_instr_kinds*)
+(*open import Sail2_values*)
+
+(* 'a is result type *)
+
+val _ = type_abbrev( "memstate" , ``: (num, memory_byte) fmap``);
+val _ = type_abbrev( "tagstate" , ``: (num, bitU) fmap``);
+(* type regstate = map string (vector bitU) *)
+
+val _ = Hol_datatype `
+(* 'regs *) sequential_state =
+ <| regstate : 'regs;
+ memstate : memstate;
+ tagstate : tagstate |>`;
+
+
+(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*)
+val _ = Define `
+ ((init_state:'regs -> 'regs sequential_state) regs=
+ (<| regstate := regs;
+ memstate := FEMPTY;
+ tagstate := FEMPTY |>))`;
+
+
+val _ = Hol_datatype `
+ ex =
+ Failure of string
+ | Throw of 'e`;
+
+
+val _ = Hol_datatype `
+ result =
+ Value of 'a
+ | Ex of ( 'e ex)`;
+
+
+(* State, nondeterminism and exception monad with result value type 'a
+ and exception type 'e. *)
+val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_e) *) "monadS" , ``:'a_regs sequential_state -> (('b_a,'c_e)result #'a_regs sequential_state) set``);
+
+(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((returnS:'a -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) a s= ({(Value a,s)}))`;
+
+
+(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)=
+ (BIGUNION (IMAGE (\x .
+ (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s))))`;
+
+
+(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((seqS:('regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) ->('regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m n= (bindS m (\u .
+ (case (u ) of ( (_ : unit) ) => n ))))`;
+
+
+(*val chooseS : forall 'regs 'a 'e. SetType 'a => list 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((chooseS:'a list -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) xs s= (LIST_TO_SET (MAP (\ x . (Value x, s)) xs)))`;
+
+
+(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((readS:('regs sequential_state -> 'a) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) f= (\ s . returnS (f s) s))`;
+
+
+(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((updateS:('regs sequential_state -> 'regs sequential_state) -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) f= (\ s . returnS () (f s)))`;
+
+
+(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((failS:string -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg s= ({(Ex (Failure msg), s)}))`;
+
+
+(*val choose_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((choose_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (chooseS [F; T]))`;
+
+val _ = Define `
+ ((undefined_boolS:unit ->('c,(bool),'a)monadS)= choose_boolS)`;
+
+
+(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((exitS:unit -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) () = (failS "exit"))`;
+
+
+(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((throwS:'e -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) e s= ({(Ex (Throw e), s)}))`;
+
+
+(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*)
+val _ = Define `
+ ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s=
+ (BIGUNION (IMAGE (\x .
+ (case x of
+ (Value a, s') => returnS a s'
+ | (Ex (Throw e), s') => h e s'
+ | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
+ )) (m s))))`;
+
+
+(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((assert_expS:bool -> string -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) exp msg= (if exp then returnS () else failS msg))`;
+
+
+(* For early return, we abuse exceptions by throwing and catching
+ the return value. The exception type is "either 'r 'e", where "Right e"
+ represents a proper exception and "Left r" an early return of value "r". *)
+val _ = type_abbrev((* ( 'a_regs, 'b_a, 'c_r, 'd_e) *) "monadRS" , ``:('a_regs,'b_a, (('c_r,'d_e)sum)) monadS``);
+
+(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*)
+val _ = Define `
+ ((early_returnS:'r -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) r= (throwS (INL r)))`;
+
+
+(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m=
+ (try_catchS m
+ (\x . (case x of INL a => returnS a | INR e => throwS e ))))`;
+
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*)
+val _ = Define `
+ ((liftRS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e)sum))result#'regs sequential_state)set) m= (try_catchS m (\ e . throwS (INR e))))`;
+
+
+(* Catch exceptions in the presence of early returns *)
+(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2*)
+val _ = Define `
+ ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h=
+ (try_catchS m
+ (\x . (case x of INL r => throwS (INL r) | INR e => h e ))))`;
+
+
+(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((maybe_failS:string -> 'a option -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg=
+ (\x . (case x of SOME a => returnS a | NONE => failS msg )))`;
+
+
+(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*)
+val _ = Define `
+ ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail2_values_Bitvector_a addr= (bindS
+ (maybe_failS "nat_of_bv" (nat_of_bv
+ dict_Sail2_values_Bitvector_a addr)) (\ addr .
+ readS (\ s . option_CASE (FLOOKUP s.tagstate addr) B0 I))))`;
+
+
+(* Read bytes from memory and return in little endian order *)
+(*val get_mem_bytes : forall 'regs. nat -> nat -> sequential_state 'regs -> maybe (list memory_byte * bitU)*)
+val _ = Define `
+ ((get_mem_bytes:num -> num -> 'regs sequential_state ->(((bitU)list)list#bitU)option) addr sz s=
+ (let addrs = (GENLIST (\ n . addr + n) sz) in
+ let read_byte = (\ s addr . FLOOKUP s.memstate addr) in
+ let read_tag = (\ s addr . option_CASE (FLOOKUP s.tagstate addr) B0 I) in
+ OPTION_MAP
+ (\ mem_val . (mem_val, FOLDL and_bit B1 (MAP (read_tag s) addrs)))
+ (just_list (MAP (read_byte s) addrs))))`;
+
+
+(*val read_memt_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte * bitU) 'e*)
+val _ = Define `
+ ((read_memt_bytesS:read_kind -> num -> num -> 'regs sequential_state ->((((memory_byte)list#bitU),'e)result#'regs sequential_state)set) _ addr sz= (bindS
+ (readS (get_mem_bytes addr sz))
+ (maybe_failS "read_memS")))`;
+
+
+(*val read_mem_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte) 'e*)
+val _ = Define `
+ ((read_mem_bytesS:read_kind -> num -> num -> 'regs sequential_state ->((((memory_byte)list),'e)result#'regs sequential_state)set) rk addr sz= (bindS
+ (read_memt_bytesS rk addr sz) (\p .
+ (case (p ) of ( (bytes, _) ) => returnS bytes ))))`;
+
+
+(*val read_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs ('b * bitU) 'e*)
+val _ = Define `
+ ((read_memtS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,('b#bitU),'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz= (bindS
+ (maybe_failS "nat_of_bv" (nat_of_bv
+ dict_Sail2_values_Bitvector_a a)) (\ a . bindS
+ (read_memt_bytesS rk a (nat_of_int sz)) (\ (bytes, tag) . bindS
+ (maybe_failS "bits_of_mem_bytes" (
+ dict_Sail2_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes))) (\ mem_val .
+ returnS (mem_val, tag))))))`;
+
+
+(*val read_memS : forall 'regs 'e 'a 'b 'addrsize. Bitvector 'a, Bitvector 'b => read_kind -> 'addrsize -> 'a -> integer -> monadS 'regs 'b 'e*)
+val _ = Define `
+ ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'addrsize -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr_size a sz= (bindS
+ (read_memtS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz) (\p . (case (p ) of ( (bytes, _) ) => returnS bytes ))))`;
+
+
+(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((excl_resultS:unit ->('regs,(bool),'e)monadS)=
+ (* TODO: This used to be more deterministic, checking a flag in the state
+ whether an exclusive load has occurred before. However, this does not
+ seem very precise; it might be safer to overapproximate the possible
+ behaviours by always making a nondeterministic choice. *)
+ undefined_boolS)`;
+
+
+(* Write little-endian list of bytes to given address *)
+(*val put_mem_bytes : forall 'regs. nat -> nat -> list memory_byte -> bitU -> sequential_state 'regs -> sequential_state 'regs*)
+val _ = Define `
+ ((put_mem_bytes:num -> num ->((bitU)list)list -> bitU -> 'regs sequential_state -> 'regs sequential_state) addr sz v tag s=
+ (let addrs = (GENLIST (\ n . addr + n) sz) in
+ let a_v = (lem_list$list_combine addrs v) in
+ let write_byte = (\mem p . (case (mem ,p ) of
+ ( mem , (addr, v) ) => mem |+ ( addr ,
+ v )
+ )) in
+ let write_tag = (\ mem addr . mem |+ ( addr , tag )) in
+ ( s with<| memstate := (FOLDL write_byte s.memstate a_v);
+ tagstate := (FOLDL write_tag s.tagstate addrs) |>)))`;
+
+
+(*val write_memt_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> bitU -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_memt_bytesS:write_kind -> num -> num ->(memory_byte)list -> bitU -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) _ addr sz v t= (seqS
+ (updateS (put_mem_bytes addr sz v t))
+ (returnS T)))`;
+
+
+(*val write_mem_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_mem_bytesS:write_kind -> num -> num ->(memory_byte)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) wk addr sz v= (write_memt_bytesS wk addr sz v B0))`;
+
+
+(*val write_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> bitU -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_memtS:'a Bitvector_class -> 'b Bitvector_class -> write_kind -> 'a -> int -> 'b -> bitU ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr sz v t=
+ ((case (nat_of_bv dict_Sail2_values_Bitvector_a addr, mem_bytes_of_bits
+ dict_Sail2_values_Bitvector_b v) of
+ (SOME addr, SOME v) => write_memt_bytesS wk addr (nat_of_int sz) v t
+ | _ => failS "write_mem"
+ )))`;
+
+
+(*val write_memS : forall 'regs 'e 'a 'b 'addrsize. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'addrsize -> 'a -> integer -> 'b -> monadS 'regs bool 'e*)
+val _ = Define `
+ ((write_memS:'a Bitvector_class -> 'b Bitvector_class -> write_kind -> 'addrsize -> 'a -> int -> 'b ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr_size addr sz v= (write_memtS
+ dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr sz v B0))`;
+
+
+(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*)
+val _ = Define `
+ ((read_regS:('regs,'rv,'a)register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg= (readS (\ s . reg.read_from s.regstate)))`;
+
+
+(* TODO
+let read_reg_range reg i j state =
+ let v = slice (get_reg state (name_of_reg reg)) i j in
+ [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+ let v = access (get_reg state (name_of_reg reg)) i in
+ [(Value v,state)]
+let read_reg_field reg regfield =
+ let (i,j) = register_field_indices reg regfield in
+ read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+ let (i,_) = register_field_indices reg regfield in
+ read_reg_bit reg i *)
+
+(*val read_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*)
+val _ = Define `
+ ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg= (bindS
+ (readS (\ s . read reg s.regstate)) (\x .
+ (case x of
+ SOME v => returnS v
+ | NONE => failS ( STRCAT "read_regvalS " reg)
+ ))))`;
+
+
+(*val write_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v= (bindS
+ (readS (\ s . write reg v s.regstate)) (\x .
+ (case x of
+ SOME rs' => updateS (\ s . ( s with<| regstate := rs' |>))
+ | NONE => failS ( STRCAT "write_regvalS " reg)
+ ))))`;
+
+
+(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*)
+val _ = Define `
+ ((write_regS:('regs,'rv,'a)register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v=
+ (updateS (\ s . ( s with<| regstate := (reg.write_to v s.regstate) |>))))`;
+
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+ let current_value = get_reg state reg in
+ let new_value = f current_value v in
+ [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+
+(* TODO Add Show typeclass for value and exception type *)
+(*val show_result : forall 'a 'e. result 'a 'e -> string*)
+val _ = Define `
+ ((show_result:('a,'e)result -> string)=
+ (\x . (case x of
+ Value _ => "Value ()"
+ | Ex (Failure msg) => STRCAT "Failure " msg
+ | Ex (Throw _) => "Throw"
+ )))`;
+
+
+(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*)
+val _ = Define `
+ ((prerr_results:(('a,'e)result#'s)set -> unit) rs=
+ (let _ = (IMAGE (\p .
+ (case (p ) of ( (r, _) ) => let _ = (prerr_endline (show_result r)) in () )) rs) in
+ () ))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_stringScript.sml b/prover_snapshots/hol4/lib/sail/sail2_stringScript.sml
new file mode 100644
index 0000000..d50f817
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_stringScript.sml
@@ -0,0 +1,555 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_string.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_listTheory sail2_valuesTheory sail2_operatorsTheory lem_list_extraTheory lem_stringTheory lem_string_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_string"
+
+(*open import Pervasives*)
+(*open import List*)
+(*open import List_extra*)
+(*open import String*)
+(*open import String_extra*)
+
+(*open import Sail2_operators*)
+(*open import Sail2_values*)
+
+(*val string_sub : string -> ii -> ii -> string*)
+val _ = Define `
+ ((string_sub:string -> int -> int -> string) str start len=
+ (IMPLODE (TAKE (Num (ABS (I len))) (DROP (Num (ABS (I start))) (EXPLODE str)))))`;
+
+
+(*val string_startswith : string -> string -> bool*)
+val _ = Define `
+ ((string_startswith:string -> string -> bool) str1 str2=
+ (let prefix = (string_sub str1(( 0 : int)) (int_of_num (STRLEN str2))) in
+ (prefix = str2)))`;
+
+
+(*val string_drop : string -> ii -> string*)
+val _ = Define `
+ ((string_drop:string -> int -> string) str n=
+ (IMPLODE (DROP (Num (ABS (I n))) (EXPLODE str))))`;
+
+
+(*val string_take : string -> ii -> string*)
+val _ = Define `
+ ((string_take:string -> int -> string) str n=
+ (IMPLODE (TAKE (Num (ABS (I n))) (EXPLODE str))))`;
+
+
+(*val string_length : string -> ii*)
+val _ = Define `
+ ((string_length:string -> int) s= (int_of_num (STRLEN s)))`;
+
+
+val _ = Define `
+ ((string_append:string -> string -> string)= STRCAT)`;
+
+
+(***********************************************
+ * Begin stuff that should be in Lem Num_extra *
+ ***********************************************)
+
+(*val maybeIntegerOfString : string -> maybe integer*)
+val _ = Define `
+ ((maybeIntegerOfString:string ->(int)option) _= NONE)`;
+
+
+(***********************************************
+ * end stuff that should be in Lem Num_extra *
+ ***********************************************)
+
+ val maybe_int_of_prefix_defn = Hol_defn "maybe_int_of_prefix" `
+ ((maybe_int_of_prefix:string ->(int#int)option) s=
+ ((case s of
+ "" => NONE
+ | str =>
+ let len = (string_length str) in
+ (case maybeIntegerOfString str of
+ SOME n => SOME (n, len)
+ | NONE => maybe_int_of_prefix (string_sub str(( 0 : int)) (len -( 1 : int)))
+ )
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn maybe_int_of_prefix_defn;
+
+val _ = Define `
+ ((maybe_int_of_string:string ->(int)option)= maybeIntegerOfString)`;
+
+
+(*val n_leading_spaces : string -> ii*)
+ val n_leading_spaces_defn = Hol_defn "n_leading_spaces" `
+ ((n_leading_spaces:string -> int) s=
+ (let len = (string_length s) in
+ if len =( 0 : int) then( 0 : int) else
+ if len =( 1 : int) then
+ (case s of
+ " " =>( 1 : int)
+ | _ =>( 0 : int)
+ )
+ else
+ (* Isabelle generation for pattern matching on characters
+ is currently broken, so use an if-expression *)
+ if SUB (s, (( 0 : num))) = #" "
+ then( 1 : int) + (n_leading_spaces (string_sub s(( 1 : int)) (len -( 1 : int))))
+ else( 0 : int)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn n_leading_spaces_defn;
+ (* end *)
+
+val _ = Define `
+ ((opt_spc_matches_prefix:string ->(unit#int)option) s=
+ (SOME (() , n_leading_spaces s)))`;
+
+
+val _ = Define `
+ ((spc_matches_prefix:string ->(unit#int)option) s=
+ (let n = (n_leading_spaces s) in
+ (* match n with *)
+(* | 0 -> Nothing *)
+ if n =( 0 : int) then NONE else
+ (* | n -> *) SOME (() , n)))`;
+
+ (* end *)
+
+(* Python:
+f = """let hex_bits_{0}_matches_prefix s =
+ match maybe_int_of_prefix s with
+ | Nothing -> Nothing
+ | Just (n, len) ->
+ if 0 <= n && n < (2 ** {0}) then
+ Just ((of_int {0} n, len))
+ else
+ Nothing
+ end
+"""
+
+for i in list(range(1, 34)) + [48, 64]:
+ print(f.format(i))
+*)
+val _ = Define `
+ ((hex_bits_1_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 1 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 1 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_2_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 2 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 2 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_3_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 3 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 3 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_4_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 4 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 4 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_5_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 5 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 5 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_6_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 6 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 6 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_7_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 7 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 7 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_8_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 8 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 8 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_9_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 9 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 9 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_10_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 10 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 10 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_11_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 11 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 11 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_12_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 12 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 12 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_13_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 13 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 13 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_14_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 14 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 14 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_15_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 15 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 15 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_16_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 16 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 16 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_17_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 17 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 17 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_18_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 18 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 18 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_19_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 19 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 19 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_20_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 20 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 20 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_21_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 21 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 21 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_22_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 22 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 22 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_23_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 23 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 23 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_24_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 24 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 24 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_25_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 25 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 25 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_26_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 26 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 26 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_27_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 27 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 27 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_28_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 28 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 28 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_29_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 29 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 29 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_30_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 30 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 30 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_31_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 31 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 31 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_32_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 32 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 32 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_33_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 33 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 33 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_48_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 48 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 48 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+
+val _ = Define `
+ ((hex_bits_64_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s=
+ ((case maybe_int_of_prefix s of
+ NONE => NONE
+ | SOME (n, len) =>
+ if(( 0 : int) <= n) /\ (n < (( 2 : int) **( 64 : num))) then
+ SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 64 : int)) n, len))
+ else
+ NONE
+ )))`;
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_valuesAuxiliaryScript.sml b/prover_snapshots/hol4/lib/sail/sail2_valuesAuxiliaryScript.sml
new file mode 100644
index 0000000..b475c5e
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_valuesAuxiliaryScript.sml
@@ -0,0 +1,139 @@
+(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory;
+open intLib;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "sail2_valuesAuxiliary"
+
+
+(****************************************************)
+(* *)
+(* Termination Proofs *)
+(* *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *)
+val (shr_int_rw, shr_int_ind_rw) =
+ Defn.tprove_no_defn ((shr_int_def, shr_int_ind),
+ WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+ )
+val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw);
+val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw);
+val () = computeLib.add_persistent_funs["shr_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *)
+val (shl_int_rw, shl_int_ind_rw) =
+ Defn.tprove_no_defn ((shl_int_def, shl_int_ind),
+ WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+ )
+val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw);
+val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw);
+val () = computeLib.add_persistent_funs["shl_int_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *)
+val (repeat_rw, repeat_ind_rw) =
+ Defn.tprove_no_defn ((repeat_def, repeat_ind),
+ WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC
+ )
+val repeat_rw = save_thm ("repeat_rw", repeat_rw);
+val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw);
+val () = computeLib.add_persistent_funs["repeat_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *)
+val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) =
+ Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind),
+ WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC
+ )
+val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw);
+val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw);
+val () = computeLib.add_persistent_funs["bools_of_nat_aux_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *)
+val (pad_list_rw, pad_list_ind_rw) =
+ Defn.tprove_no_defn ((pad_list_def, pad_list_ind),
+ WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC
+ )
+val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw);
+val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw);
+val () = computeLib.add_persistent_funs["pad_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *)
+val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) =
+ Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind),
+ WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def]
+ )
+val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw);
+val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw);
+val () = computeLib.add_persistent_funs["reverse_endianness_list_rw"];
+
+
+(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *)
+val (index_list_rw, index_list_ind_rw) =
+ Defn.tprove_no_defn ((index_list_def, index_list_ind),
+ WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))`
+ \\ rw[integerTheory.INT_MAX]
+ \\ intLib.COOPER_TAC
+ )
+val index_list_rw = save_thm ("index_list_rw", index_list_rw);
+val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw);
+val () = computeLib.add_persistent_funs["index_list_rw"];
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *)
+val (while_rw, while_ind_rw) =
+ Defn.tprove_no_defn ((while_def, while_ind),
+ cheat (* the termination proof *)
+ )
+val while_rw = save_thm ("while_rw", while_rw);
+val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw);
+*)
+
+
+(*
+(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *)
+val (until_rw, until_ind_rw) =
+ Defn.tprove_no_defn ((until_def, until_ind),
+ cheat (* the termination proof *)
+ )
+val until_rw = save_thm ("until_rw", until_rw);
+val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw);
+*)
+
+
+(****************************************************)
+(* *)
+(* Lemmata *)
+(* *)
+(****************************************************)
+
+val just_list_spec = store_thm("just_list_spec",
+``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\
+ (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``,
+ (* Theorem: just_list_spec*)
+ conj_tac
+ \\ ho_match_mp_tac just_list_ind
+ \\ Cases \\ rw[]
+ \\ rw[Once just_list_def]
+ >- ( CASE_TAC \\ fs[] \\ CASE_TAC )
+ >- PROVE_TAC[]
+ \\ Cases_on`es` \\ fs[]
+ \\ CASE_TAC \\ fs[]
+ \\ CASE_TAC \\ fs[]
+);
+
+
+
+val _ = export_theory()
+
diff --git a/prover_snapshots/hol4/lib/sail/sail2_valuesScript.sml b/prover_snapshots/hol4/lib/sail/sail2_valuesScript.sml
new file mode 100644
index 0000000..134b086
--- /dev/null
+++ b/prover_snapshots/hol4/lib/sail/sail2_valuesScript.sml
@@ -0,0 +1,1318 @@
+(*Generated by Lem from ../../src/gen_lib/sail2_values.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory lem_machine_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "sail2_values"
+
+(*open import Pervasives_extra*)
+(*open import Machine_word*)
+(*open import Sail_impl_base*)
+
+
+val _ = type_abbrev( "ii" , ``: int``);
+val _ = type_abbrev( "nn" , ``: num``);
+
+(*val nat_of_int : integer -> nat*)
+val _ = Define `
+ ((nat_of_int:int -> num) i= (if i <( 0 : int) then( 0 : num) else Num (ABS (I i))))`;
+
+
+(*val pow : integer -> integer -> integer*)
+val _ = Define `
+ ((pow0:int -> int -> int) m n= (m ** (nat_of_int n)))`;
+
+
+val _ = Define `
+ ((pow2:int -> int) n= (pow0(( 2 : int)) n))`;
+
+
+(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*)
+
+(*let add_int l r = integerAdd l r
+let add_signed l r = integerAdd l r
+let sub_int l r = integerMinus l r
+let mult_int l r = integerMult l r
+let div_int l r = integerDiv l r
+let div_nat l r = natDiv l r
+let power_int_nat l r = integerPow l r
+let power_int_int l r = integerPow l (nat_of_int r)
+let negate_int i = integerNegate i
+let min_int l r = integerMin l r
+let max_int l r = integerMax l r
+
+let add_real l r = realAdd l r
+let sub_real l r = realMinus l r
+let mult_real l r = realMult l r
+let div_real l r = realDiv l r
+let negate_real r = realNegate r
+let abs_real r = realAbs r
+let power_real b e = realPowInteger b e*)
+
+(*val print_endline : string -> unit*)
+val _ = Define `
+ ((print_endline:string -> unit) _= () )`;
+
+
+(*val print : string -> unit*)
+val _ = Define `
+ ((print:string -> unit) _= () )`;
+
+
+(*val prerr_endline : string -> unit*)
+val _ = Define `
+ ((prerr_endline:string -> unit) _= () )`;
+
+
+val _ = Define `
+ ((prerr:string -> unit) x= (prerr_endline x))`;
+
+
+(*val print_int : string -> integer -> unit*)
+val _ = Define `
+ ((print_int:string -> int -> unit) msg i= (print_endline ( STRCAT msg (stringFromInteger i))))`;
+
+
+(*val prerr_int : string -> integer -> unit*)
+val _ = Define `
+ ((prerr_int:string -> int -> unit) msg i= (prerr_endline ( STRCAT msg (stringFromInteger i))))`;
+
+
+(*val putchar : integer -> unit*)
+val _ = Define `
+ ((putchar:int -> unit) _= () )`;
+
+
+(*val shr_int : ii -> ii -> ii*)
+ val shr_int_defn = Hol_defn "shr_int" `
+ ((shr_int:int -> int -> int) x s= (if s >( 0 : int) then shr_int (x /( 2 : int)) (s -( 1 : int)) else x))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shr_int_defn;
+
+(*val shl_int : integer -> integer -> integer*)
+ val shl_int_defn = Hol_defn "shl_int" `
+ ((shl_int:int -> int -> int) i shift= (if shift >( 0 : int) then( 2 : int) * shl_int i (shift -( 1 : int)) else i))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shl_int_defn;
+val _ = Define `
+ ((take_list:int -> 'a list -> 'a list) n xs= (TAKE (nat_of_int n) xs))`;
+
+val _ = Define `
+ ((drop_list:int -> 'a list -> 'a list) n xs= (DROP (nat_of_int n) xs))`;
+
+
+(*val repeat : forall 'a. list 'a -> integer -> list 'a*)
+ val repeat_defn = Hol_defn "repeat" `
+ ((repeat:'a list -> int -> 'a list) xs n=
+ (if n <=( 0 : int) then []
+ else xs ++ repeat xs (n -( 1 : int))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn repeat_defn;
+
+val _ = Define `
+ ((duplicate_to_list:'a -> int -> 'a list) bit length= (repeat [bit] length))`;
+
+
+ val _ = Define `
+ ((replace:'a list -> int -> 'a -> 'a list) bs (n : int) b'= ((case bs of
+ [] => []
+ | b :: bs =>
+ if n =( 0 : int) then b' :: bs
+ else b :: replace bs (n -( 1 : int)) b'
+ )))`;
+
+
+val _ = Define `
+ ((upper:'a -> 'a) n= n)`;
+
+
+(* Modulus operation corresponding to quot below -- result
+ has sign of dividend. *)
+val _ = Define `
+ ((tmod_int:int -> int -> int) (a: int) (b:int) : int=
+ (let m = ((ABS a) % (ABS b)) in
+ if a <( 0 : int) then ~ m else m))`;
+
+
+val _ = Define `
+ ((hardware_mod:int -> int -> int)= tmod_int)`;
+
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+val _ = Define `
+ ((tdiv_int:int -> int -> int) (a:int) (b:int) : int=
+ (let q = ((ABS a) / (ABS b)) in
+ if ((a<( 0 : int)) <=> (b<( 0 : int))) then
+ q (* same sign -- result positive *)
+ else
+ ~ q))`;
+ (* different sign -- result negative *)
+
+val _ = Define `
+ ((hardware_quot:int -> int -> int)= tdiv_int)`;
+
+
+val _ = Define `
+ ((max_64u:int)= (((( 2 : int))**(( 64 : num))) -( 1 : int)))`;
+
+val _ = Define `
+ ((max_64:int)= (((( 2 : int))**(( 63 : num))) -( 1 : int)))`;
+
+val _ = Define `
+ ((min_64:int)= (( 0 : int) - ((( 2 : int))**(( 63 : num)))))`;
+
+val _ = Define `
+ ((max_32u:int)= ((( 4294967295 : int) : int)))`;
+
+val _ = Define `
+ ((max_32:int)= ((( 2147483647 : int) : int)))`;
+
+val _ = Define `
+ ((min_32:int)= ((( 0 : int) -( 2147483648 : int) : int)))`;
+
+val _ = Define `
+ ((max_8:int)= ((( 127 : int) : int)))`;
+
+val _ = Define `
+ ((min_8:int)= ((( 0 : int) -( 128 : int) : int)))`;
+
+val _ = Define `
+ ((max_5:int)= ((( 31 : int) : int)))`;
+
+val _ = Define `
+ ((min_5:int)= ((( 0 : int) -( 32 : int) : int)))`;
+
+
+(* just_list takes a list of maybes and returns Just xs if all elements have
+ a value, and Nothing if one of the elements is Nothing. *)
+(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*)
+ val _ = Define `
+ ((just_list:('a option)list ->('a list)option) l= ((case l of
+ [] => SOME []
+ | (x :: xs) =>
+ (case (x, just_list xs) of
+ (SOME x, SOME xs) => SOME (x :: xs)
+ | (_, _) => NONE
+ )
+ )))`;
+
+
+(*val maybe_failwith : forall 'a. maybe 'a -> 'a*)
+val _ = Define `
+ ((maybe_failwith:'a option -> 'a)=
+ (\x . (case x of SOME a => a | NONE => failwith "maybe_failwith" )))`;
+
+
+(*** Bits *)
+val _ = Hol_datatype `
+ bitU = B0 | B1 | BU`;
+
+
+val _ = Define `
+ ((showBitU:bitU -> string)=
+ (\x . (case x of B0 => "O" | B1 => "I" | BU => "U" )))`;
+
+
+val _ = Define `
+ ((bitU_char:bitU -> char)=
+ (\x . (case x of B0 => #"0" | B1 => #"1" | BU => #"?" )))`;
+
+
+val _ = Define `
+((instance_Show_Show_Sail2_values_bitU_dict:(bitU)Show_class)= (<|
+
+ show_method := showBitU|>))`;
+
+
+(*val compare_bitU : bitU -> bitU -> ordering*)
+val _ = Define `
+ ((compare_bitU:bitU -> bitU -> ordering) l r= ((case (l, r) of
+ (BU, BU) => EQUAL
+ | (B0, B0) => EQUAL
+ | (B1, B1) => EQUAL
+ | (BU, _) => LESS
+ | (_, BU) => GREATER
+ | (B0, _) => LESS
+ | (_, _) => GREATER
+)))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Sail2_values_bitU_dict:(bitU)Ord_class)= (<|
+
+ compare_method := compare_bitU;
+
+ isLess_method := (\ l r. (compare_bitU l r) = LESS);
+
+ isLessEqual_method := (\ l r. (compare_bitU l r) <> GREATER);
+
+ isGreater_method := (\ l r. (compare_bitU l r) = GREATER);
+
+ isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LESS)|>))`;
+
+
+val _ = Hol_datatype `
+(* 'a *) BitU_class= <|
+ to_bitU_method : 'a -> bitU;
+ of_bitU_method : bitU -> 'a
+|>`;
+
+
+val _ = Define `
+((instance_Sail2_values_BitU_Sail2_values_bitU_dict:(bitU)BitU_class)= (<|
+
+ to_bitU_method := (\ b. b);
+
+ of_bitU_method := (\ b. b)|>))`;
+
+
+val _ = Define `
+ ((bool_of_bitU:bitU ->(bool)option)=
+ (\x . (case x of B0 => SOME F | B1 => SOME T | BU => NONE )))`;
+
+
+val _ = Define `
+ ((bitU_of_bool:bool -> bitU) b= (if b then B1 else B0))`;
+
+
+(*instance (BitU bool)
+ let to_bitU = bitU_of_bool
+ let of_bitU = bool_of_bitU
+end*)
+
+val _ = Define `
+ ((cast_bit_bool:bitU ->(bool)option)= bool_of_bitU)`;
+
+
+val _ = Define `
+ ((not_bit:bitU -> bitU)=
+ (\x . (case x of B1 => B0 | B0 => B1 | BU => BU )))`;
+
+
+(*val is_one : integer -> bitU*)
+val _ = Define `
+ ((is_one:int -> bitU) i=
+ (if i =( 1 : int) then B1 else B0))`;
+
+
+(*val and_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((and_bit:bitU -> bitU -> bitU) x y=
+ ((case (x, y) of
+ (B0, _) => B0
+ | (_, B0) => B0
+ | (B1, B1) => B1
+ | (_, _) => BU
+ )))`;
+
+
+(*val or_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((or_bit:bitU -> bitU -> bitU) x y=
+ ((case (x, y) of
+ (B1, _) => B1
+ | (_, B1) => B1
+ | (B0, B0) => B0
+ | (_, _) => BU
+ )))`;
+
+
+(*val xor_bit : bitU -> bitU -> bitU*)
+val _ = Define `
+ ((xor_bit:bitU -> bitU -> bitU) x y=
+ ((case (x, y) of
+ (B0, B0) => B0
+ | (B0, B1) => B1
+ | (B1, B0) => B1
+ | (B1, B1) => B0
+ | (_, _) => BU
+ )))`;
+
+
+(*val &. : bitU -> bitU -> bitU*)
+
+(*val |. : bitU -> bitU -> bitU*)
+
+(*val +. : bitU -> bitU -> bitU*)
+
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+ val bools_of_nat_aux_defn = Hol_defn "bools_of_nat_aux" `
+ ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc=
+ (if len <=( 0 : int) then acc
+ else bools_of_nat_aux (len -( 1 : int)) (x DIV( 2:num)) ((if (x MOD( 2:num)) =( 1:num) then T else F) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn bools_of_nat_aux_defn;
+val _ = Define `
+ ((bools_of_nat:int -> num ->(bool)list) len n= (bools_of_nat_aux len n []))`;
+ (*List.reverse (bools_of_nat_aux n)*)
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+ val _ = Define `
+ ((nat_of_bools_aux:num ->(bool)list -> num) acc bs= ((case bs of
+ [] => acc
+ | T :: bs => nat_of_bools_aux ((( 2:num) * acc) +( 1:num)) bs
+ | F :: bs => nat_of_bools_aux (( 2:num) * acc) bs
+)))`;
+
+val _ = Define `
+ ((nat_of_bools:(bool)list -> num) bs= (nat_of_bools_aux(( 0:num)) bs))`;
+
+
+(*val unsigned_of_bools : list bool -> integer*)
+val _ = Define `
+ ((unsigned_of_bools:(bool)list -> int) bs= (int_of_num (nat_of_bools bs)))`;
+
+
+(*val signed_of_bools : list bool -> integer*)
+val _ = Define `
+ ((signed_of_bools:(bool)list -> int) bs=
+ ((case bs of
+ T :: _ =>( 0 : int) - (( 1 : int) + (unsigned_of_bools (MAP (\ x. ~ x) bs)))
+ | F :: _ => unsigned_of_bools bs
+ | [] =>( 0 : int) (* Treat empty list as all zeros *)
+ )))`;
+
+
+(*val int_of_bools : bool -> list bool -> integer*)
+val _ = Define `
+ ((int_of_bools:bool ->(bool)list -> int) sign bs= (if sign then signed_of_bools bs else unsigned_of_bools bs))`;
+
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+ val pad_list_defn = Hol_defn "pad_list" `
+ ((pad_list:'a -> 'a list -> int -> 'a list) x xs n=
+ (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn pad_list_defn;
+
+val _ = Define `
+ ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs=
+ (let longer = (len - (int_of_num (LENGTH xs))) in
+ if longer <( 0 : int) then DROP (nat_of_int (ABS (longer))) xs
+ else pad_list pad xs longer))`;
+
+
+val _ = Define `
+ ((extz_bools:int ->(bool)list ->(bool)list) len bs= (ext_list F len bs))`;
+
+val _ = Define `
+ ((exts_bools:int ->(bool)list ->(bool)list) len bs=
+ ((case bs of
+ T :: _ => ext_list T len bs
+ | _ => ext_list F len bs
+ )))`;
+
+
+ val _ = Define `
+ ((add_one_bool_ignore_overflow_aux:(bool)list ->(bool)list) bits= ((case bits of
+ [] => []
+ | F :: bits => T :: bits
+ | T :: bits => F :: add_one_bool_ignore_overflow_aux bits
+)))`;
+
+
+val _ = Define `
+ ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits=
+ (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`;
+
+
+(*let bool_list_of_int n =
+ let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+ if n >= (0 : integer) then bs_abs
+ else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
+val _ = Define `
+ ((bools_of_int:int -> int ->(bool)list) len n=
+ (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in
+ if n >= (( 0 : int) : int) then bs_abs
+ else add_one_bool_ignore_overflow (MAP (\ x. ~ x) bs_abs)))`;
+
+
+(*** Bit lists ***)
+
+(*val has_undefined_bits : list bitU -> bool*)
+val _ = Define `
+ ((has_undefined_bits:(bitU)list -> bool) bs= (EXISTS (\x .
+ (case x of BU => T | _ => F )) bs))`;
+
+
+val _ = Define `
+ ((bits_of_nat:int -> num ->(bitU)list) len n= (MAP bitU_of_bool (bools_of_nat len n)))`;
+
+
+val _ = Define `
+ ((nat_of_bits:(bitU)list ->(num)option) bits=
+ ((case (just_list (MAP bool_of_bitU bits)) of
+ SOME bs => SOME (nat_of_bools bs)
+ | NONE => NONE
+ )))`;
+
+
+val _ = Define `
+ ((not_bits:(bitU)list ->(bitU)list)= (MAP not_bit))`;
+
+
+(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*)
+val _ = Define `
+ ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys=
+ (FOLDR (\ (x, y) acc . op x y :: acc) [] (list_combine xs ys)))`;
+
+
+val _ = Define `
+ ((unsigned_of_bits:(bitU)list ->(int)option) bits=
+ ((case (just_list (MAP bool_of_bitU bits)) of
+ SOME bs => SOME (unsigned_of_bools bs)
+ | NONE => NONE
+ )))`;
+
+
+val _ = Define `
+ ((signed_of_bits:(bitU)list ->(int)option) bits=
+ ((case (just_list (MAP bool_of_bitU bits)) of
+ SOME bs => SOME (signed_of_bools bs)
+ | NONE => NONE
+ )))`;
+
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+val _ = Define `
+ ((int_of_bits:bool ->(bitU)list ->(int)option) sign bs= (if sign then signed_of_bits bs else unsigned_of_bits bs))`;
+
+
+val _ = Define `
+ ((extz_bits:int ->(bitU)list ->(bitU)list) len bits= (ext_list B0 len bits))`;
+
+val _ = Define `
+ ((exts_bits:int ->(bitU)list ->(bitU)list) len bits=
+ ((case bits of
+ BU :: _ => ext_list BU len bits
+ | B1 :: _ => ext_list B1 len bits
+ | _ => ext_list B0 len bits
+ )))`;
+
+
+ val _ = Define `
+ ((add_one_bit_ignore_overflow_aux:(bitU)list ->(bitU)list) bits= ((case bits of
+ [] => []
+ | B0 :: bits => B1 :: bits
+ | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
+ | BU :: bits => BU :: MAP (\b .
+ (case (b ) of ( _ ) => BU )) bits
+)))`;
+
+
+val _ = Define `
+ ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits=
+ (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`;
+
+
+(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
+let bits_of_int len n = exts_bits len (bit_list_of_int n)*)
+val _ = Define `
+ ((bits_of_int:int -> int ->(bitU)list) len n= (MAP bitU_of_bool (bools_of_int len n)))`;
+
+
+(*val arith_op_bits :
+ (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+val _ = Define `
+ ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r=
+ ((case (int_of_bits sign l, int_of_bits sign r) of
+ (SOME li, SOME ri) => bits_of_int (int_of_num (LENGTH l)) (op li ri)
+ | (_, _) => repeat [BU] (int_of_num (LENGTH l))
+ )))`;
+
+
+val _ = Define `
+ ((char_of_nibble:bitU#bitU#bitU#bitU ->(char)option)=
+ (\x . (case x of
+ (B0, B0, B0, B0) => SOME #"0"
+ | (B0, B0, B0, B1) => SOME #"1"
+ | (B0, B0, B1, B0) => SOME #"2"
+ | (B0, B0, B1, B1) => SOME #"3"
+ | (B0, B1, B0, B0) => SOME #"4"
+ | (B0, B1, B0, B1) => SOME #"5"
+ | (B0, B1, B1, B0) => SOME #"6"
+ | (B0, B1, B1, B1) => SOME #"7"
+ | (B1, B0, B0, B0) => SOME #"8"
+ | (B1, B0, B0, B1) => SOME #"9"
+ | (B1, B0, B1, B0) => SOME #"A"
+ | (B1, B0, B1, B1) => SOME #"B"
+ | (B1, B1, B0, B0) => SOME #"C"
+ | (B1, B1, B0, B1) => SOME #"D"
+ | (B1, B1, B1, B0) => SOME #"E"
+ | (B1, B1, B1, B1) => SOME #"F"
+ | _ => NONE
+ )))`;
+
+
+ val _ = Define `
+ ((hexstring_of_bits:(bitU)list ->((char)list)option) bs= ((case bs of
+ b1 :: b2 :: b3 :: b4 :: bs =>
+ let n = (char_of_nibble (b1, b2, b3, b4)) in
+ let s = (hexstring_of_bits bs) in
+ (case (n, s) of
+ (SOME n, SOME s) => SOME (n :: s)
+ | _ => NONE
+ )
+ | [] => SOME []
+ | _ => NONE
+ )))`;
+
+
+val _ = Define `
+ ((show_bitlist:(bitU)list -> string) bs=
+ ((case hexstring_of_bits bs of
+ SOME s => IMPLODE (#"0" :: (#"x" :: s))
+ | NONE => IMPLODE (#"0" :: (#"b" :: MAP bitU_char bs))
+ )))`;
+
+
+(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j=
+ (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
+ let (prefix0,fromItoJ) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
+ fromItoJ))`;
+
+
+(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j=
+ (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+ subrange_list_inc xs (top - i) (top - j)))`;
+
+
+(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*)
+val _ = Define `
+ ((subrange_list:bool -> 'a list -> int -> int -> 'a list) is_inc xs i j= (if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j))`;
+
+
+(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
+ (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in
+ let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in
+ (prefix ++ xs') ++ suffix))`;
+
+
+(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'=
+ (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+ update_subrange_list_inc xs (top - i) (top - j) xs'))`;
+
+
+(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*)
+val _ = Define `
+ ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'=
+ (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`;
+
+
+(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list_inc:'a list -> int -> 'a) xs n= (EL (nat_of_int n) xs))`;
+
+
+(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list_dec:'a list -> int -> 'a) xs n=
+ (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+ access_list_inc xs (top - n)))`;
+
+
+(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*)
+val _ = Define `
+ ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n=
+ (if is_inc then access_list_inc xs n else access_list_dec xs n))`;
+
+
+(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list_inc:'a list -> int -> 'a -> 'a list) xs n x= (LUPDATE x (nat_of_int n) xs))`;
+
+
+(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x=
+ (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in
+ update_list_inc xs (top - n) x))`;
+
+
+(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*)
+val _ = Define `
+ ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x=
+ (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`;
+
+
+val _ = Define `
+ ((extract_only_bit:(bitU)list -> bitU)=
+ (\x . (case x of [] => BU | [e] => e | _ => BU )))`;
+
+
+(*** Machine words *)
+
+(*val length_mword : forall 'a. mword 'a -> integer*)
+
+(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int j) (nat_of_int i) w))`;
+
+
+(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j=
+ (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+ slice_mword_dec w (top - i) (top - j)))`;
+
+
+(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*)
+val _ = Define `
+ ((slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word) is_inc w i j= (if is_inc then slice_mword_inc w i j else slice_mword_dec w i j))`;
+
+
+(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int j) (nat_of_int i) w' w))`;
+
+
+(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'=
+ (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+ update_slice_mword_dec w (top - i) (top - j) w'))`;
+
+
+(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+val _ = Define `
+ ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'=
+ (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`;
+
+
+(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword_dec:'a words$word -> int -> bitU) w n= (bitU_of_bool (words$word_bit (nat_of_int n) w)))`;
+
+
+(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword_inc:'a words$word -> int -> bitU) w n=
+ (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+ access_mword_dec w (top - n)))`;
+
+
+(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*)
+val _ = Define `
+ ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n=
+ (if is_inc then access_mword_inc w n else access_mword_dec w n))`;
+
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+val _ = Define `
+ ((update_mword_bool_dec:'a words$word -> int -> bool -> 'a words$word) w n b= ($:+ (nat_of_int n) b w))`;
+
+val _ = Define `
+ ((update_mword_dec:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_dec w n) (bool_of_bitU b)))`;
+
+
+(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+val _ = Define `
+ ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b=
+ (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in
+ update_mword_bool_dec w (top - n) b))`;
+
+val _ = Define `
+ ((update_mword_inc:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_inc w n) (bool_of_bitU b)))`;
+
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+val _ = Define `
+ ((int_of_mword:bool -> 'a words$word -> int) sign w=
+ (if sign then integer_word$w2i w else lem$w2ui w))`;
+
+
+(* Translating between a type level number (itself 'n) and an integer *)
+
+val _ = Define `
+ ((size_itself_int:'a itself -> int) x= (int_of_num (size_itself x)))`;
+
+
+(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
+ the actual integer is ignored. *)
+
+(*val make_the_value : forall 'n. integer -> itself 'n*)
+val _ = Define `
+ ((make_the_value:int -> 'n itself) _= the_value)`;
+
+
+(*** Bitvectors *)
+
+val _ = Hol_datatype `
+(* 'a *) Bitvector_class= <|
+ bits_of_method : 'a -> bitU list;
+ (* We allow of_bits to be partial, as not all bitvector representations
+ support undefined bits *)
+ of_bits_method : bitU list -> 'a option;
+ of_bools_method : bool list -> 'a;
+ length_method : 'a -> int;
+ (* of_int: the first parameter specifies the desired length of the bitvector *)
+ of_int_method : int -> int -> 'a;
+ (* Conversion to integers is undefined if any bit is undefined *)
+ unsigned_method : 'a -> int option;
+ signed_method : 'a -> int option;
+ (* Lifting of integer operations to bitvectors: The boolean flag indicates
+ whether to treat the bitvectors as signed (true) or not (false). *)
+ arith_op_bv_method : (int -> int -> int) -> bool -> 'a -> 'a -> 'a
+|>`;
+
+
+(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*)
+val _ = Define `
+ ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail2_values_Bitvector_a bits= (maybe_failwith (
+ dict_Sail2_values_Bitvector_a.of_bits_method bits)))`;
+
+
+val _ = Define `
+ ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail2_values_Bitvector_a sign= (if sign then
+ dict_Sail2_values_Bitvector_a.signed_method else dict_Sail2_values_Bitvector_a.unsigned_method))`;
+
+
+val _ = Define `
+((instance_Sail2_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail2_values_BitU_a= (<|
+
+ bits_of_method := (\ v. MAP
+ dict_Sail2_values_BitU_a.to_bitU_method v);
+
+ of_bits_method := (\ v. SOME (MAP
+ dict_Sail2_values_BitU_a.of_bitU_method v));
+
+ of_bools_method := (\ v. MAP
+ dict_Sail2_values_BitU_a.of_bitU_method (MAP bitU_of_bool v));
+
+ length_method := (\ xs. int_of_num (LENGTH xs));
+
+ of_int_method := (\ len n. MAP
+ dict_Sail2_values_BitU_a.of_bitU_method (bits_of_int len n));
+
+ unsigned_method := (\ v. unsigned_of_bits (MAP
+ dict_Sail2_values_BitU_a.to_bitU_method v));
+
+ signed_method := (\ v. signed_of_bits (MAP
+ dict_Sail2_values_BitU_a.to_bitU_method v));
+
+ arith_op_bv_method := (\ op sign l r. MAP
+ dict_Sail2_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP
+ dict_Sail2_values_BitU_a.to_bitU_method l) (MAP dict_Sail2_values_BitU_a.to_bitU_method r)))|>))`;
+
+
+val _ = Define `
+((instance_Sail2_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<|
+
+ bits_of_method := (\ v. MAP bitU_of_bool (bitstring$w2v v));
+
+ of_bits_method := (\ v. OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU v)));
+
+ of_bools_method := (\ v. bitstring$v2w v);
+
+ length_method := (\ v. int_of_num (words$word_len v));
+
+ of_int_method := (\i n .
+ (case (i ,n ) of ( _ , n ) => integer_word$i2w n ));
+
+ unsigned_method := (\ v. SOME (lem$w2ui v));
+
+ signed_method := (\ v. SOME (integer_word$w2i v));
+
+ arith_op_bv_method := (\ op sign l r. integer_word$i2w (op (int_of_mword sign l) (int_of_mword sign r)))|>))`;
+
+
+val _ = Define `
+ ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n= (access_list T (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) n))`;
+
+val _ = Define `
+ ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n= (access_list F (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) n))`;
+
+
+val _ = Define `
+ ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b= (update_list T (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`;
+
+val _ = Define `
+ ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b= (update_list F (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`;
+
+
+val _ = Define `
+ ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j= (subrange_list T (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`;
+
+val _ = Define `
+ ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j= (subrange_list F (
+ dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`;
+
+
+val _ = Define `
+ ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'= (update_subrange_list T (
+ dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`;
+
+val _ = Define `
+ ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'= (update_subrange_list F (
+ dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`;
+
+
+(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+val _ = Define `
+ ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v= (extz_bits n (
+ dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*)
+val _ = Define `
+ ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v= (exts_bits n (
+ dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val nat_of_bv : forall 'a. Bitvector 'a => 'a -> maybe nat*)
+val _ = Define `
+ ((nat_of_bv:'a Bitvector_class -> 'a ->(num)option)dict_Sail2_values_Bitvector_a v= (OPTION_MAP nat_of_int (
+ dict_Sail2_values_Bitvector_a.unsigned_method v)))`;
+
+
+(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
+val _ = Define `
+ ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail2_values_Bitvector_a v= (show_bitlist (
+ dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val print_bits : forall 'a. Bitvector 'a => string -> 'a -> unit*)
+val _ = Define `
+ ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a str v= (print_endline ( STRCAT str (string_of_bv
+ dict_Sail2_values_Bitvector_a v))))`;
+
+
+(*val dec_str : integer -> string*)
+val _ = Define `
+ ((dec_str:int -> string) bv= (lem_string_extra$stringFromInteger bv))`;
+
+
+(*val concat_str : string -> string -> string*)
+val _ = Define `
+ ((concat_str:string -> string -> string) str1 str2= (STRCAT str1 str2))`;
+
+
+(*val int_of_bit : bitU -> integer*)
+val _ = Define `
+ ((int_of_bit:bitU -> int) b=
+ ((case b of
+ B0 =>( 0 : int)
+ | B1 =>( 1 : int)
+ | _ => failwith "int_of_bit saw unknown"
+ )))`;
+
+
+(*val count_leading_zero_bits : list bitU -> integer*)
+ val count_leading_zero_bits_defn = Hol_defn "count_leading_zero_bits" `
+ ((count_leading_zero_bits:(bitU)list -> int) v=
+ ((case v of
+ B0 :: v' => count_leading_zero_bits v' +( 1 : int)
+ | _ =>( 0 : int)
+ )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn count_leading_zero_bits_defn;
+
+(*val count_leading_zeros_bv : forall 'a. Bitvector 'a => 'a -> integer*)
+val _ = Define `
+ ((count_leading_zeros_bv:'a Bitvector_class -> 'a -> int)dict_Sail2_values_Bitvector_a v= (count_leading_zero_bits (
+ dict_Sail2_values_Bitvector_a.bits_of_method v)))`;
+
+
+(*val decimal_string_of_bv : forall 'a. Bitvector 'a => 'a -> string*)
+val _ = Define `
+ ((decimal_string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail2_values_Bitvector_a bv=
+ (let place_values =
+ (lem_list$mapi
+ (\ i b . (int_of_bit b) * (( 2 : int) ** i))
+ (REVERSE (dict_Sail2_values_Bitvector_a.bits_of_method bv)))
+ in
+ let sum = (FOLDL (+)(( 0 : int)) place_values) in
+ lem_string_extra$stringFromInteger sum))`;
+
+
+(*** Bytes and addresses *)
+
+val _ = type_abbrev( "memory_byte" , ``: bitU list``);
+
+(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*)
+ val _ = Define `
+ ((byte_chunks:'a list ->(('a list)list)option) bs= ((case bs of
+ [] => SOME []
+ | a::b::c::d::e::f::g::h::rest =>
+ OPTION_BIND (byte_chunks rest) (\ rest . SOME ([a;b;c;d;e;f;g;h] :: rest))
+ | _ => NONE
+)))`;
+
+
+(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*)
+val _ = Define `
+ ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail2_values_Bitvector_a bs= (byte_chunks (
+ dict_Sail2_values_Bitvector_a.bits_of_method bs)))`;
+
+
+(*val bits_of_bytes : list memory_byte -> list bitU*)
+val _ = Define `
+ ((bits_of_bytes:((bitU)list)list ->(bitU)list) bs= (FLAT (MAP (\ v. MAP (\ b. b) v) bs)))`;
+
+
+val _ = Define `
+ ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail2_values_Bitvector_a bs= (OPTION_MAP REVERSE (bytes_of_bits
+ dict_Sail2_values_Bitvector_a bs)))`;
+
+val _ = Define `
+ ((bits_of_mem_bytes:((bitU)list)list ->(bitU)list) bs= (bits_of_bytes (REVERSE bs)))`;
+
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+let bitv_of_byte_lifteds v =
+ foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+let bitv_of_bytes v =
+ foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+let byte_lifteds_of_bitv bits =
+ let bits = List.map bit_lifted_of_bitU bits in
+ byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+let bytes_of_bitv bits =
+ let bits = List.map bit_of_bitU bits in
+ bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+let address_lifted_of_bitv v =
+ let byte_lifteds = byte_lifteds_of_bitv v in
+ let maybe_address_integer =
+ match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+ | Just bs -> Just (integer_of_byte_list bs)
+ | _ -> Nothing
+ end in
+ Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+let address_of_bitv v =
+ let bytes = bytes_of_bitv v in
+ address_of_byte_list bytes*)
+
+ val reverse_endianness_list_defn = Hol_defn "reverse_endianness_list" `
+ ((reverse_endianness_list:'a list -> 'a list) bits=
+ (if LENGTH bits <=( 8 : num) then bits else
+ reverse_endianness_list (drop_list(( 8 : int)) bits) ++ take_list(( 8 : int)) bits))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn reverse_endianness_list_defn;
+
+
+(*** Registers *)
+
+(*type register_field = string
+type register_field_index = string * (integer * integer) (* name, start and end *)
+
+type register =
+ | Register of string * (* name *)
+ integer * (* length *)
+ integer * (* start index *)
+ bool * (* is increasing *)
+ list register_field_index
+ | UndefinedRegister of integer (* length *)
+ | RegisterPair of register * register*)
+
+val _ = Hol_datatype `
+(* ( 'a_regstate, 'b_regval, 'c_a) *) register_ref =
+ <| name : string;
+ (*is_inc : bool;*)
+ read_from :'a_regstate -> 'c_a;
+ write_to :'c_a -> 'a_regstate -> 'a_regstate;
+ of_regval :'b_regval -> 'c_a option;
+ regval_of :'c_a -> 'b_regval |>`;
+
+
+(* Register accessors: pair of functions for reading and writing register values *)
+val _ = type_abbrev((* ( 'regstate, 'regval) *) "register_accessors" , ``:
+ ((string -> 'regstate -> 'regval option) #
+ (string -> 'regval -> 'regstate -> 'regstate option))``);
+
+val _ = Hol_datatype `
+(* ( 'a_regtype, 'b_a) *) field_ref =
+ <| field_name : string;
+ field_start : int;
+ field_is_inc : bool;
+ get_field :'a_regtype -> 'b_a;
+ set_field :'a_regtype -> 'b_a -> 'a_regtype |>`;
+
+
+(*let name_of_reg = function
+ | Register name _ _ _ _ -> name
+ | UndefinedRegister _ -> failwith "name_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "name_of_reg RegisterPair"
+end
+
+let size_of_reg = function
+ | Register _ size _ _ _ -> size
+ | UndefinedRegister size -> size
+ | RegisterPair _ _ -> failwith "size_of_reg RegisterPair"
+end
+
+let start_of_reg = function
+ | Register _ _ start _ _ -> start
+ | UndefinedRegister _ -> failwith "start_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "start_of_reg RegisterPair"
+end
+
+let is_inc_of_reg = function
+ | Register _ _ _ is_inc _ -> is_inc
+ | UndefinedRegister _ -> failwith "is_inc_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "in_inc_of_reg RegisterPair"
+end
+
+let dir_of_reg = function
+ | Register _ _ _ is_inc _ -> dir_of_bool is_inc
+ | UndefinedRegister _ -> failwith "dir_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "dir_of_reg RegisterPair"
+end
+
+let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
+let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
+let rec register_field_indices_aux register rfield =
+ match register with
+ | Register _ _ _ _ rfields -> List.lookup rfield rfields
+ | RegisterPair r1 r2 ->
+ let m_indices = register_field_indices_aux r1 rfield in
+ if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
+ | UndefinedRegister _ -> Nothing
+ end
+
+val register_field_indices : register -> register_field -> integer * integer
+let register_field_indices register rfield =
+ match register_field_indices_aux register rfield with
+ | Just indices -> indices
+ | Nothing -> failwith "Invalid register/register-field combination"
+ end
+
+let register_field_indices_nat reg regfield=
+ let (i,j) = register_field_indices reg regfield in
+ (natFromInteger i,natFromInteger j)*)
+
+(*let rec external_reg_value reg_name v =
+ let (internal_start, external_start, direction) =
+ match reg_name with
+ | Reg _ start size dir ->
+ (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+ | Reg_slice _ reg_start dir (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_field _ reg_start dir _ (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ end in
+ let bits = bit_lifteds_of_bitv v in
+ <| rv_bits = bits;
+ rv_dir = direction;
+ rv_start = external_start;
+ rv_start_internal = internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+let internal_reg_value v =
+ List.map bitU_of_bit_lifted v.rv_bits
+ (*(integerFromNat v.rv_start_internal)
+ (v.rv_dir = D_increasing)*)
+
+
+let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
+ match d with
+ (*This is the case the thread/concurrecny model expects, so no change needed*)
+ | D_increasing -> (i,j)
+ | D_decreasing -> let slice_i = start - i in
+ let slice_j = (i - j) + slice_i in
+ (slice_i,slice_j)
+ end *)
+
+(* TODO
+let external_reg_whole r =
+ Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
+
+let external_reg_slice r (i,j) =
+ let start = natFromInteger r.start in
+ let dir = dir_of_bool r.is_inc in
+ Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+let external_reg_field_whole reg rfield =
+ let (m,n) = register_field_indices_nat reg rfield in
+ let start = start_of_reg_nat reg in
+ let dir = dir_of_reg reg in
+ Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+let external_reg_field_slice reg rfield (i,j) =
+ let (m,n) = register_field_indices_nat reg rfield in
+ let start = start_of_reg_nat reg in
+ let dir = dir_of_reg reg in
+ Reg_f_slice (name_of_reg reg) start dir rfield
+ (external_slice dir start (m,n))
+ (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+let external_mem_value v =
+ byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+let internal_mem_value bytes =
+ List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+(*val foreach : forall 'a 'vars.
+ (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*)
+ val _ = Define `
+ ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body=
+ ((case l of
+ [] => vars
+ | (x :: xs) => foreach xs (body x vars) body
+ )))`;
+
+
+(*val index_list : integer -> integer -> integer -> list integer*)
+ val index_list_defn = Hol_defn "index_list" `
+ ((index_list:int -> int -> int ->(int)list) from to step=
+ (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then
+ from :: index_list (from + step) to step
+ else []))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn index_list_defn;
+
+(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+ val while_defn = Hol_defn "while" `
+ ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
+ (if cond vars then while (body vars) cond body else vars))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn while_defn;
+
+(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*)
+ val until_defn = Hol_defn "until" `
+ ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body=
+ (let vars = (body vars) in
+ if cond vars then vars else until (body vars) cond body))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn until_defn;
+
+
+(* convert numbers unsafely to naturals *)
+
+val _ = Hol_datatype `
+(* 'a *) ToNatural_class= <| toNatural_method : 'a -> num |>`;
+
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<|
+
+ toNatural_method := (\ n . Num (ABS n))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<|
+
+ toNatural_method := (\ n . ((Num (ABS n)):num))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_nat_dict:(num)ToNatural_class)= (<|
+
+ toNatural_method := (\ n . ( n:num))|>))`;
+
+val _ = Define `
+((instance_Sail2_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<|
+
+ toNatural_method := (\ n . n)|>))`;
+
+
+val _ = Define `
+ ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5)=
+ (dict_Sail2_values_ToNatural_d.toNatural_method n1, dict_Sail2_values_ToNatural_c.toNatural_method n2, dict_Sail2_values_ToNatural_b.toNatural_method n3, dict_Sail2_values_ToNatural_a.toNatural_method n4, dict_Sail2_values_ToNatural_e.toNatural_method n5))`;
+
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+ or machine words as bitvector representation *)
+(*type regfp =
+ | RFull of (string)
+ | RSlice of (string * integer * integer)
+ | RSliceBit of (string * integer)
+ | RField of (string * string)
+
+type niafp =
+ | NIAFP_successor
+ | NIAFP_concrete_address of vector bitU
+ | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp =
+ | DIAFP_none
+ | DIAFP_concrete of vector bitU
+ | DIAFP_reg of regfp
+
+let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
+ | RFull name ->
+ let (start,length,direction,_) = reg_info name Nothing in
+ Reg name start length direction
+ | RSlice (name,i,j) ->
+ let i = natFromInteger i in
+ let j = natFromInteger j in
+ let (start,length,direction,_) = reg_info name Nothing in
+ let slice = external_slice direction start (i,j) in
+ Reg_slice name start direction slice
+ | RSliceBit (name,i) ->
+ let i = natFromInteger i in
+ let (start,length,direction,_) = reg_info name Nothing in
+ let slice = external_slice direction start (i,i) in
+ Reg_slice name start direction slice
+ | RField (name,field_name) ->
+ let (start,length,direction,span) = reg_info name (Just field_name) in
+ let slice = external_slice direction start span in
+ Reg_field name start direction field_name slice
+end
+
+let niafp_to_nia reginfo = function
+ | NIAFP_successor -> NIA_successor
+ | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
+ | NIAFP_indirect_address -> NIA_indirect_address
+end
+
+let diafp_to_dia reginfo = function
+ | DIAFP_none -> DIA_none
+ | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
+ | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
+end
+*)
+val _ = export_theory()
+
diff --git a/prover_snapshots/isabelle/README.md b/prover_snapshots/isabelle/README.md
new file mode 100644
index 0000000..463bc1c
--- /dev/null
+++ b/prover_snapshots/isabelle/README.md
@@ -0,0 +1,25 @@
+# Snapshot of Isabelle definitions of RISC-V
+
+This directory contains snapshots of the Isabelle theories generated by Sail
+for the RISC-V model (RV32 and RV64).
+
+A heap image containing the architecture definitions (as well as the Lem and
+Sail libraries in the [lem](lem/) subdirectory) can be built using
+
+```
+isabelle build -b -D .
+```
+
+This takes roughly 10 minutes on an Intel Core i7-7700 with 64GB RAM.
+
+An interactive session based on this heap image can be started using the
+following command (replacing `$DIR` with the path of this directory):
+
+```
+isabelle jedit -d $DIR -l Sail-RV64
+```
+
+The model was built with
+* `sail` release 0.10, commit `da307c67`
+* `sail-riscv` commit `7e6ffe2`
+and checked against Isabelle 2018.
diff --git a/prover_snapshots/isabelle/ROOTS b/prover_snapshots/isabelle/ROOTS
new file mode 100644
index 0000000..9459630
--- /dev/null
+++ b/prover_snapshots/isabelle/ROOTS
@@ -0,0 +1,3 @@
+lib
+RV32
+RV64
diff --git a/prover_snapshots/isabelle/RV32/ROOT b/prover_snapshots/isabelle/RV32/ROOT
new file mode 100644
index 0000000..367f184
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/ROOT
@@ -0,0 +1,4 @@
+session "Sail-RV32" = "Sail" +
+ options [document = false]
+ theories
+ "Riscv_lemmas"
diff --git a/prover_snapshots/isabelle/RV32/Riscv.thy b/prover_snapshots/isabelle/RV32/Riscv.thy
new file mode 100644
index 0000000..8dfe545
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/Riscv.thy
@@ -0,0 +1,36556 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV32/riscv.lem\<close>.\<close>
+
+theory "Riscv"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+ "Riscv_types"
+ "Riscv_extras"
+
+begin
+
+\<comment> \<open>\<open>Generated by Sail from riscv.\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_string\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+\<comment> \<open>\<open>open import Riscv_types\<close>\<close>
+\<comment> \<open>\<open>open import Riscv_extras\<close>\<close>
+
+\<comment> \<open>\<open>val is_none : forall 'a. maybe 'a -> bool\<close>\<close>
+
+fun is_none :: " 'a option \<Rightarrow> bool " where
+ " is_none (Some (_)) = ( False )"
+|" is_none None = ( True )"
+
+
+\<comment> \<open>\<open>val is_some : forall 'a. maybe 'a -> bool\<close>\<close>
+
+fun is_some :: " 'a option \<Rightarrow> bool " where
+ " is_some (Some (_)) = ( True )"
+|" is_some None = ( False )"
+
+
+\<comment> \<open>\<open>val eq_unit : unit -> unit -> bool\<close>\<close>
+
+definition eq_unit :: " unit \<Rightarrow> unit \<Rightarrow> bool " where
+ " eq_unit _ _ = ( True )"
+
+
+
+
+\<comment> \<open>\<open>val neq_bool : bool -> bool -> bool\<close>\<close>
+
+definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where
+ " neq_bool x y = ( \<not> (((x = y))))"
+ for x :: " bool "
+ and y :: " bool "
+
+
+\<comment> \<open>\<open>val __id : integer -> integer\<close>\<close>
+
+definition id0 :: " int \<Rightarrow> int " where
+ " id0 x = ( x )"
+ for x :: " int "
+
+
+\<comment> \<open>\<open>val concat_str_bits : forall 'n. Size 'n => string -> mword 'n -> string\<close>\<close>
+
+definition concat_str_bits :: " string \<Rightarrow>('n::len)Word.word \<Rightarrow> string " where
+ " concat_str_bits str x = ( (@) str ((string_of_bits x)))"
+ for str :: " string "
+ and x :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val concat_str_dec : string -> ii -> string\<close>\<close>
+
+definition concat_str_dec :: " string \<Rightarrow> int \<Rightarrow> string " where
+ " concat_str_dec str x = ( (@) str ((dec_str x)))"
+ for str :: " string "
+ and x :: " int "
+
+
+
+
+\<comment> \<open>\<open>val sail_mask : forall 'len 'v. Size 'len, Size 'v => integer -> mword 'v -> mword 'len\<close>\<close>
+
+definition sail_mask :: " int \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word " where
+ " sail_mask len v = (
+ if ((len \<le> ((int (size v))))) then (vector_truncate v len :: ( 'len::len)Word.word)
+ else (zero_extend v len :: ( 'len::len)Word.word))"
+ for len :: " int "
+ and v :: "('v::len)Word.word "
+
+
+\<comment> \<open>\<open>val sail_ones : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition sail_ones :: " int \<Rightarrow>('n::len)Word.word " where
+ " sail_ones n = ( (not_vec ((zeros n :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val slice_mask : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n\<close>\<close>
+
+definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where
+ " slice_mask n i l = (
+ if ((l \<ge> n)) then (shiftl ((sail_ones n :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)
+ else
+ (let one = ((sail_mask n (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in
+ (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))"
+ for n :: " int "
+ and i :: " int "
+ and l :: " int "
+
+
+\<comment> \<open>\<open>val read_kind_of_num : integer -> read_kind\<close>\<close>
+
+definition read_kind_of_num :: " int \<Rightarrow> read_kind " where
+ " read_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Read_plain
+ else if (((p00 = (( 1 :: int)::ii)))) then Read_reserve
+ else if (((p00 = (( 2 :: int)::ii)))) then Read_acquire
+ else if (((p00 = (( 3 :: int)::ii)))) then Read_exclusive
+ else if (((p00 = (( 4 :: int)::ii)))) then Read_exclusive_acquire
+ else if (((p00 = (( 5 :: int)::ii)))) then Read_stream
+ else if (((p00 = (( 6 :: int)::ii)))) then Read_RISCV_acquire
+ else if (((p00 = (( 7 :: int)::ii)))) then Read_RISCV_strong_acquire
+ else if (((p00 = (( 8 :: int)::ii)))) then Read_RISCV_reserved
+ else if (((p00 = (( 9 :: int)::ii)))) then Read_RISCV_reserved_acquire
+ else if (((p00 = (( 10 :: int)::ii)))) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_read_kind : read_kind -> integer\<close>\<close>
+
+fun num_of_read_kind :: " read_kind \<Rightarrow> int " where
+ " num_of_read_kind Read_plain = ( (( 0 :: int)::ii))"
+|" num_of_read_kind Read_reserve = ( (( 1 :: int)::ii))"
+|" num_of_read_kind Read_acquire = ( (( 2 :: int)::ii))"
+|" num_of_read_kind Read_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_read_kind Read_exclusive_acquire = ( (( 4 :: int)::ii))"
+|" num_of_read_kind Read_stream = ( (( 5 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_acquire = ( (( 6 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_strong_acquire = ( (( 7 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved = ( (( 8 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_acquire = ( (( 9 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_strong_acquire = ( (( 10 :: int)::ii))"
+|" num_of_read_kind Read_X86_locked = ( (( 11 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val write_kind_of_num : integer -> write_kind\<close>\<close>
+
+definition write_kind_of_num :: " int \<Rightarrow> write_kind " where
+ " write_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Write_plain
+ else if (((p00 = (( 1 :: int)::ii)))) then Write_conditional
+ else if (((p00 = (( 2 :: int)::ii)))) then Write_release
+ else if (((p00 = (( 3 :: int)::ii)))) then Write_exclusive
+ else if (((p00 = (( 4 :: int)::ii)))) then Write_exclusive_release
+ else if (((p00 = (( 5 :: int)::ii)))) then Write_RISCV_release
+ else if (((p00 = (( 6 :: int)::ii)))) then Write_RISCV_strong_release
+ else if (((p00 = (( 7 :: int)::ii)))) then Write_RISCV_conditional
+ else if (((p00 = (( 8 :: int)::ii)))) then Write_RISCV_conditional_release
+ else if (((p00 = (( 9 :: int)::ii)))) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_write_kind : write_kind -> integer\<close>\<close>
+
+fun num_of_write_kind :: " write_kind \<Rightarrow> int " where
+ " num_of_write_kind Write_plain = ( (( 0 :: int)::ii))"
+|" num_of_write_kind Write_conditional = ( (( 1 :: int)::ii))"
+|" num_of_write_kind Write_release = ( (( 2 :: int)::ii))"
+|" num_of_write_kind Write_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_write_kind Write_exclusive_release = ( (( 4 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_release = ( (( 5 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_strong_release = ( (( 6 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional = ( (( 7 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_release = ( (( 8 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_strong_release = ( (( 9 :: int)::ii))"
+|" num_of_write_kind Write_X86_locked = ( (( 10 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val barrier_kind_of_num : integer -> barrier_kind\<close>\<close>
+
+definition barrier_kind_of_num :: " int \<Rightarrow> barrier_kind " where
+ " barrier_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Barrier_Sync
+ else if (((p00 = (( 1 :: int)::ii)))) then Barrier_LwSync
+ else if (((p00 = (( 2 :: int)::ii)))) then Barrier_Eieio
+ else if (((p00 = (( 3 :: int)::ii)))) then Barrier_Isync
+ else if (((p00 = (( 4 :: int)::ii)))) then Barrier_DMB
+ else if (((p00 = (( 5 :: int)::ii)))) then Barrier_DMB_ST
+ else if (((p00 = (( 6 :: int)::ii)))) then Barrier_DMB_LD
+ else if (((p00 = (( 7 :: int)::ii)))) then Barrier_DSB
+ else if (((p00 = (( 8 :: int)::ii)))) then Barrier_DSB_ST
+ else if (((p00 = (( 9 :: int)::ii)))) then Barrier_DSB_LD
+ else if (((p00 = (( 10 :: int)::ii)))) then Barrier_ISB
+ else if (((p00 = (( 11 :: int)::ii)))) then Barrier_MIPS_SYNC
+ else if (((p00 = (( 12 :: int)::ii)))) then Barrier_RISCV_rw_rw
+ else if (((p00 = (( 13 :: int)::ii)))) then Barrier_RISCV_r_rw
+ else if (((p00 = (( 14 :: int)::ii)))) then Barrier_RISCV_r_r
+ else if (((p00 = (( 15 :: int)::ii)))) then Barrier_RISCV_rw_w
+ else if (((p00 = (( 16 :: int)::ii)))) then Barrier_RISCV_w_w
+ else if (((p00 = (( 17 :: int)::ii)))) then Barrier_RISCV_w_rw
+ else if (((p00 = (( 18 :: int)::ii)))) then Barrier_RISCV_rw_r
+ else if (((p00 = (( 19 :: int)::ii)))) then Barrier_RISCV_r_w
+ else if (((p00 = (( 20 :: int)::ii)))) then Barrier_RISCV_w_r
+ else if (((p00 = (( 21 :: int)::ii)))) then Barrier_RISCV_tso
+ else if (((p00 = (( 22 :: int)::ii)))) then Barrier_RISCV_i
+ else Barrier_x86_MFENCE))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_barrier_kind : barrier_kind -> integer\<close>\<close>
+
+fun num_of_barrier_kind :: " barrier_kind \<Rightarrow> int " where
+ " num_of_barrier_kind Barrier_Sync = ( (( 0 :: int)::ii))"
+|" num_of_barrier_kind Barrier_LwSync = ( (( 1 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Eieio = ( (( 2 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Isync = ( (( 3 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB = ( (( 4 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_ST = ( (( 5 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_LD = ( (( 6 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB = ( (( 7 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_ST = ( (( 8 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_LD = ( (( 9 :: int)::ii))"
+|" num_of_barrier_kind Barrier_ISB = ( (( 10 :: int)::ii))"
+|" num_of_barrier_kind Barrier_MIPS_SYNC = ( (( 11 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_rw = ( (( 12 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_rw = ( (( 13 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_r = ( (( 14 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_w = ( (( 15 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_w = ( (( 16 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_rw = ( (( 17 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_r = ( (( 18 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_w = ( (( 19 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_r = ( (( 20 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_tso = ( (( 21 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_i = ( (( 22 :: int)::ii))"
+|" num_of_barrier_kind Barrier_x86_MFENCE = ( (( 23 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val trans_kind_of_num : integer -> trans_kind\<close>\<close>
+
+definition trans_kind_of_num :: " int \<Rightarrow> trans_kind " where
+ " trans_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Transaction_start
+ else if (((p00 = (( 1 :: int)::ii)))) then Transaction_commit
+ else Transaction_abort))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_trans_kind : trans_kind -> integer\<close>\<close>
+
+fun num_of_trans_kind :: " trans_kind \<Rightarrow> int " where
+ " num_of_trans_kind Transaction_start = ( (( 0 :: int)::ii))"
+|" num_of_trans_kind Transaction_commit = ( (( 1 :: int)::ii))"
+|" num_of_trans_kind Transaction_abort = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val cache_op_kind_of_num : integer -> cache_op_kind\<close>\<close>
+
+definition cache_op_kind_of_num :: " int \<Rightarrow> cache_op_kind " where
+ " cache_op_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Cache_op_D_IVAC
+ else if (((p00 = (( 1 :: int)::ii)))) then Cache_op_D_ISW
+ else if (((p00 = (( 2 :: int)::ii)))) then Cache_op_D_CSW
+ else if (((p00 = (( 3 :: int)::ii)))) then Cache_op_D_CISW
+ else if (((p00 = (( 4 :: int)::ii)))) then Cache_op_D_ZVA
+ else if (((p00 = (( 5 :: int)::ii)))) then Cache_op_D_CVAC
+ else if (((p00 = (( 6 :: int)::ii)))) then Cache_op_D_CVAU
+ else if (((p00 = (( 7 :: int)::ii)))) then Cache_op_D_CIVAC
+ else if (((p00 = (( 8 :: int)::ii)))) then Cache_op_I_IALLUIS
+ else if (((p00 = (( 9 :: int)::ii)))) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_cache_op_kind : cache_op_kind -> integer\<close>\<close>
+
+fun num_of_cache_op_kind :: " cache_op_kind \<Rightarrow> int " where
+ " num_of_cache_op_kind Cache_op_D_IVAC = ( (( 0 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_ISW = ( (( 1 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CSW = ( (( 2 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CISW = ( (( 3 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_ZVA = ( (( 4 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CVAC = ( (( 5 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CVAU = ( (( 6 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CIVAC = ( (( 7 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IALLUIS = ( (( 8 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IALLU = ( (( 9 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IVAU = ( (( 10 :: int)::ii))"
+
+
+
+
+
+
+\<comment> \<open>\<open>val cast_unit_vec : bitU -> mword ty1\<close>\<close>
+
+fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where
+ " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))"
+|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val get_config_print_instr : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_reg : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_mem : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_platform : unit -> bool\<close>\<close>
+
+definition get_config_print_instr :: " unit \<Rightarrow> bool " where
+ " get_config_print_instr _ = ( False )"
+
+
+definition get_config_print_reg :: " unit \<Rightarrow> bool " where
+ " get_config_print_reg _ = ( False )"
+
+
+definition get_config_print_mem :: " unit \<Rightarrow> bool " where
+ " get_config_print_mem _ = ( False )"
+
+
+definition get_config_print_platform :: " unit \<Rightarrow> bool " where
+ " get_config_print_platform _ = ( False )"
+
+
+\<comment> \<open>\<open>val EXTS : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm\<close>\<close>
+
+\<comment> \<open>\<open>val EXTZ : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm\<close>\<close>
+
+definition EXTS :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
+ " EXTS m v = ( (sign_extend v m :: ( 'm::len)Word.word))"
+ for m :: " int "
+ and v :: "('n::len)Word.word "
+
+
+definition EXTZ :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
+ " EXTZ m v = ( (zero_extend v m :: ( 'm::len)Word.word))"
+ for m :: " int "
+ and v :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val zeros_implicit : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition zeros_implicit :: " int \<Rightarrow>('n::len)Word.word " where
+ " zeros_implicit n = ( (zeros n :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val ones : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition ones :: " int \<Rightarrow>('n::len)Word.word " where
+ " ones n = ( (sail_ones n :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val bool_to_bits : bool -> mword ty1\<close>\<close>
+
+definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))"
+ for x :: " bool "
+
+
+\<comment> \<open>\<open>val bit_to_bool : bitU -> bool\<close>\<close>
+
+fun bit_to_bool :: " bitU \<Rightarrow> bool " where
+ " bit_to_bool B1 = ( True )"
+|" bit_to_bool B0 = ( False )"
+
+
+\<comment> \<open>\<open>val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l\<close>\<close>
+
+definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where
+ " to_bits l n = ( (get_slice_int l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))"
+ for l :: " int "
+ and n :: " int "
+
+
+\<comment> \<open>\<open>val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zIzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64\<close>\<close>
+
+definition shift_right_arith64 :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word " where
+ " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = (
+ (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in
+ (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))"
+ for v :: "(64)Word.word "
+ and shift :: "(6)Word.word "
+
+
+\<comment> \<open>\<open>val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32\<close>\<close>
+
+definition shift_right_arith32 :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word " where
+ " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = (
+ (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in
+ (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))"
+ for v :: "(32)Word.word "
+ and shift :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val n_leading_spaces : string -> ii\<close>\<close>
+
+function (sequential,domintros) n_leading_spaces0 :: " string \<Rightarrow> int " where
+ " n_leading_spaces0 s = (
+ (let p00 = s in
+ if (((p00 = ('''')))) then (( 0 :: int)::ii)
+ else
+ (let p00 = (string_take s (( 1 :: int)::ii)) in
+ if (((p00 = ('' '')))) then (( 1 :: int)::ii) + ((n_leading_spaces0 ((string_drop s (( 1 :: int)::ii)))))
+ else (( 0 :: int)::ii))))"
+ for s :: " string "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val spc_forwards : unit -> string\<close>\<close>
+
+definition spc_forwards :: " unit \<Rightarrow> string " where
+ " spc_forwards _ = ( ('' ''))"
+
+
+\<comment> \<open>\<open>val spc_backwards : string -> unit\<close>\<close>
+
+definition spc_backwards :: " string \<Rightarrow> unit " where
+ " spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition spc_matches_prefix0 :: " string \<Rightarrow>(unit*int)option " where
+ " spc_matches_prefix0 s = (
+ (let n = (n_leading_spaces0 s) in
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then None
+ else Some (() , n))))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val opt_spc_forwards : unit -> string\<close>\<close>
+
+definition opt_spc_forwards :: " unit \<Rightarrow> string " where
+ " opt_spc_forwards _ = ( (''''))"
+
+
+\<comment> \<open>\<open>val opt_spc_backwards : string -> unit\<close>\<close>
+
+definition opt_spc_backwards :: " string \<Rightarrow> unit " where
+ " opt_spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val opt_spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition opt_spc_matches_prefix0 :: " string \<Rightarrow>(unit*int)option " where
+ " opt_spc_matches_prefix0 s = ( Some (() , n_leading_spaces0 s))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val def_spc_forwards : unit -> string\<close>\<close>
+
+definition def_spc_forwards :: " unit \<Rightarrow> string " where
+ " def_spc_forwards _ = ( ('' ''))"
+
+
+\<comment> \<open>\<open>val def_spc_backwards : string -> unit\<close>\<close>
+
+definition def_spc_backwards :: " string \<Rightarrow> unit " where
+ " def_spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val def_spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition def_spc_matches_prefix :: " string \<Rightarrow>(unit*ii)option " where
+ " def_spc_matches_prefix s = ( opt_spc_matches_prefix0 s )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_1_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition hex_bits_1_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " hex_bits_1_forwards_matches bv = ( True )"
+ for bv :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_1_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_1_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_1_backwards_matches s = (
+ if ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 1 Word.word * ii))option)) of
+ Some ((g__39, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_1_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition hex_bits_1_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " hex_bits_1_backwards s = (
+ (case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 1 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_2_forwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition hex_bits_2_forwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " hex_bits_2_forwards_matches bv = ( True )"
+ for bv :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_2_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_2_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_2_backwards_matches s = (
+ if ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 2 Word.word * ii))option)) of
+ Some ((g__38, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_2_backwards : string -> M (mword ty2)\<close>\<close>
+
+definition hex_bits_2_backwards :: " string \<Rightarrow>((register_value),((2)Word.word),(exception))monad " where
+ " hex_bits_2_backwards s = (
+ (case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 2 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_3_forwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition hex_bits_3_forwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " hex_bits_3_forwards_matches bv = ( True )"
+ for bv :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_3_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_3_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_3_backwards_matches s = (
+ if ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 3 Word.word * ii))option)) of
+ Some ((g__37, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_3_backwards : string -> M (mword ty3)\<close>\<close>
+
+definition hex_bits_3_backwards :: " string \<Rightarrow>((register_value),((3)Word.word),(exception))monad " where
+ " hex_bits_3_backwards s = (
+ (case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 3 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_4_forwards_matches : mword ty4 -> bool\<close>\<close>
+
+definition hex_bits_4_forwards_matches :: "(4)Word.word \<Rightarrow> bool " where
+ " hex_bits_4_forwards_matches bv = ( True )"
+ for bv :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_4_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_4_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_4_backwards_matches s = (
+ if ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 4 Word.word * ii))option)) of
+ Some ((g__36, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_4_backwards : string -> M (mword ty4)\<close>\<close>
+
+definition hex_bits_4_backwards :: " string \<Rightarrow>((register_value),((4)Word.word),(exception))monad " where
+ " hex_bits_4_backwards s = (
+ (case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 4 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_5_forwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition hex_bits_5_forwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " hex_bits_5_forwards_matches bv = ( True )"
+ for bv :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_5_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_5_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_5_backwards_matches s = (
+ if ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 5 Word.word * ii))option)) of
+ Some ((g__35, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_5_backwards : string -> M (mword ty5)\<close>\<close>
+
+definition hex_bits_5_backwards :: " string \<Rightarrow>((register_value),((5)Word.word),(exception))monad " where
+ " hex_bits_5_backwards s = (
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 5 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_6_forwards_matches : mword ty6 -> bool\<close>\<close>
+
+definition hex_bits_6_forwards_matches :: "(6)Word.word \<Rightarrow> bool " where
+ " hex_bits_6_forwards_matches bv = ( True )"
+ for bv :: "(6)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_6_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_6_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_6_backwards_matches s = (
+ if ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 6 Word.word * ii))option)) of
+ Some ((g__34, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_6_backwards : string -> M (mword ty6)\<close>\<close>
+
+definition hex_bits_6_backwards :: " string \<Rightarrow>((register_value),((6)Word.word),(exception))monad " where
+ " hex_bits_6_backwards s = (
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 6 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_7_forwards_matches : mword ty7 -> bool\<close>\<close>
+
+definition hex_bits_7_forwards_matches :: "(7)Word.word \<Rightarrow> bool " where
+ " hex_bits_7_forwards_matches bv = ( True )"
+ for bv :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_7_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_7_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_7_backwards_matches s = (
+ if ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 7 Word.word * ii))option)) of
+ Some ((g__33, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_7_backwards : string -> M (mword ty7)\<close>\<close>
+
+definition hex_bits_7_backwards :: " string \<Rightarrow>((register_value),((7)Word.word),(exception))monad " where
+ " hex_bits_7_backwards s = (
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 7 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_8_forwards_matches : mword ty8 -> bool\<close>\<close>
+
+definition hex_bits_8_forwards_matches :: "(8)Word.word \<Rightarrow> bool " where
+ " hex_bits_8_forwards_matches bv = ( True )"
+ for bv :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_8_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_8_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_8_backwards_matches s = (
+ if ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 8 Word.word * ii))option)) of
+ Some ((g__32, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_8_backwards : string -> M (mword ty8)\<close>\<close>
+
+definition hex_bits_8_backwards :: " string \<Rightarrow>((register_value),((8)Word.word),(exception))monad " where
+ " hex_bits_8_backwards s = (
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 8 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_9_forwards_matches : mword ty9 -> bool\<close>\<close>
+
+definition hex_bits_9_forwards_matches :: "(9)Word.word \<Rightarrow> bool " where
+ " hex_bits_9_forwards_matches bv = ( True )"
+ for bv :: "(9)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_9_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_9_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_9_backwards_matches s = (
+ if ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 9 Word.word * ii))option)) of
+ Some ((g__31, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_9_backwards : string -> M (mword ty9)\<close>\<close>
+
+definition hex_bits_9_backwards :: " string \<Rightarrow>((register_value),((9)Word.word),(exception))monad " where
+ " hex_bits_9_backwards s = (
+ (case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 9 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_10_forwards_matches : mword ty10 -> bool\<close>\<close>
+
+definition hex_bits_10_forwards_matches :: "(10)Word.word \<Rightarrow> bool " where
+ " hex_bits_10_forwards_matches bv = ( True )"
+ for bv :: "(10)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_10_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_10_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_10_backwards_matches s = (
+ if ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 10 Word.word * ii))option)) of
+ Some ((g__30, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_10_backwards : string -> M (mword ty10)\<close>\<close>
+
+definition hex_bits_10_backwards :: " string \<Rightarrow>((register_value),((10)Word.word),(exception))monad " where
+ " hex_bits_10_backwards s = (
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 10 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_11_forwards_matches : mword ty11 -> bool\<close>\<close>
+
+definition hex_bits_11_forwards_matches :: "(11)Word.word \<Rightarrow> bool " where
+ " hex_bits_11_forwards_matches bv = ( True )"
+ for bv :: "(11)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_11_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_11_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_11_backwards_matches s = (
+ if ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 11 Word.word * ii))option)) of
+ Some ((g__29, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_11_backwards : string -> M (mword ty11)\<close>\<close>
+
+definition hex_bits_11_backwards :: " string \<Rightarrow>((register_value),((11)Word.word),(exception))monad " where
+ " hex_bits_11_backwards s = (
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 11 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_12_forwards_matches : mword ty12 -> bool\<close>\<close>
+
+definition hex_bits_12_forwards_matches :: "(12)Word.word \<Rightarrow> bool " where
+ " hex_bits_12_forwards_matches bv = ( True )"
+ for bv :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_12_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_12_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_12_backwards_matches s = (
+ if ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 12 Word.word * ii))option)) of
+ Some ((g__28, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_12_backwards : string -> M (mword ty12)\<close>\<close>
+
+definition hex_bits_12_backwards :: " string \<Rightarrow>((register_value),((12)Word.word),(exception))monad " where
+ " hex_bits_12_backwards s = (
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 12 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_13_forwards_matches : mword ty13 -> bool\<close>\<close>
+
+definition hex_bits_13_forwards_matches :: "(13)Word.word \<Rightarrow> bool " where
+ " hex_bits_13_forwards_matches bv = ( True )"
+ for bv :: "(13)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_13_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_13_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_13_backwards_matches s = (
+ if ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 13 Word.word * ii))option)) of
+ Some ((g__27, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_13_backwards : string -> M (mword ty13)\<close>\<close>
+
+definition hex_bits_13_backwards :: " string \<Rightarrow>((register_value),((13)Word.word),(exception))monad " where
+ " hex_bits_13_backwards s = (
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 13 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_14_forwards_matches : mword ty14 -> bool\<close>\<close>
+
+definition hex_bits_14_forwards_matches :: "(14)Word.word \<Rightarrow> bool " where
+ " hex_bits_14_forwards_matches bv = ( True )"
+ for bv :: "(14)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_14_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_14_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_14_backwards_matches s = (
+ if ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 14 Word.word * ii))option)) of
+ Some ((g__26, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_14_backwards : string -> M (mword ty14)\<close>\<close>
+
+definition hex_bits_14_backwards :: " string \<Rightarrow>((register_value),((14)Word.word),(exception))monad " where
+ " hex_bits_14_backwards s = (
+ (case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 14 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_15_forwards_matches : mword ty15 -> bool\<close>\<close>
+
+definition hex_bits_15_forwards_matches :: "(15)Word.word \<Rightarrow> bool " where
+ " hex_bits_15_forwards_matches bv = ( True )"
+ for bv :: "(15)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_15_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_15_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_15_backwards_matches s = (
+ if ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 15 Word.word * ii))option)) of
+ Some ((g__25, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_15_backwards : string -> M (mword ty15)\<close>\<close>
+
+definition hex_bits_15_backwards :: " string \<Rightarrow>((register_value),((15)Word.word),(exception))monad " where
+ " hex_bits_15_backwards s = (
+ (case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 15 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_16_forwards_matches : mword ty16 -> bool\<close>\<close>
+
+definition hex_bits_16_forwards_matches :: "(16)Word.word \<Rightarrow> bool " where
+ " hex_bits_16_forwards_matches bv = ( True )"
+ for bv :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_16_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_16_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_16_backwards_matches s = (
+ if ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 16 Word.word * ii))option)) of
+ Some ((g__24, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_16_backwards : string -> M (mword ty16)\<close>\<close>
+
+definition hex_bits_16_backwards :: " string \<Rightarrow>((register_value),((16)Word.word),(exception))monad " where
+ " hex_bits_16_backwards s = (
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 16 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_17_forwards_matches : mword ty17 -> bool\<close>\<close>
+
+definition hex_bits_17_forwards_matches :: "(17)Word.word \<Rightarrow> bool " where
+ " hex_bits_17_forwards_matches bv = ( True )"
+ for bv :: "(17)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_17_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_17_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_17_backwards_matches s = (
+ if ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 17 Word.word * ii))option)) of
+ Some ((g__23, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_17_backwards : string -> M (mword ty17)\<close>\<close>
+
+definition hex_bits_17_backwards :: " string \<Rightarrow>((register_value),((17)Word.word),(exception))monad " where
+ " hex_bits_17_backwards s = (
+ (case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 17 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_18_forwards_matches : mword ty18 -> bool\<close>\<close>
+
+definition hex_bits_18_forwards_matches :: "(18)Word.word \<Rightarrow> bool " where
+ " hex_bits_18_forwards_matches bv = ( True )"
+ for bv :: "(18)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_18_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_18_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_18_backwards_matches s = (
+ if ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 18 Word.word * ii))option)) of
+ Some ((g__22, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_18_backwards : string -> M (mword ty18)\<close>\<close>
+
+definition hex_bits_18_backwards :: " string \<Rightarrow>((register_value),((18)Word.word),(exception))monad " where
+ " hex_bits_18_backwards s = (
+ (case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 18 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_19_forwards_matches : mword ty19 -> bool\<close>\<close>
+
+definition hex_bits_19_forwards_matches :: "(19)Word.word \<Rightarrow> bool " where
+ " hex_bits_19_forwards_matches bv = ( True )"
+ for bv :: "(19)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_19_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_19_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_19_backwards_matches s = (
+ if ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 19 Word.word * ii))option)) of
+ Some ((g__21, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_19_backwards : string -> M (mword ty19)\<close>\<close>
+
+definition hex_bits_19_backwards :: " string \<Rightarrow>((register_value),((19)Word.word),(exception))monad " where
+ " hex_bits_19_backwards s = (
+ (case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 19 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_20_forwards_matches : mword ty20 -> bool\<close>\<close>
+
+definition hex_bits_20_forwards_matches :: "(20)Word.word \<Rightarrow> bool " where
+ " hex_bits_20_forwards_matches bv = ( True )"
+ for bv :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_20_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_20_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_20_backwards_matches s = (
+ if ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 20 Word.word * ii))option)) of
+ Some ((g__20, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_20_backwards : string -> M (mword ty20)\<close>\<close>
+
+definition hex_bits_20_backwards :: " string \<Rightarrow>((register_value),((20)Word.word),(exception))monad " where
+ " hex_bits_20_backwards s = (
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 20 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_21_forwards_matches : mword ty21 -> bool\<close>\<close>
+
+definition hex_bits_21_forwards_matches :: "(21)Word.word \<Rightarrow> bool " where
+ " hex_bits_21_forwards_matches bv = ( True )"
+ for bv :: "(21)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_21_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_21_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_21_backwards_matches s = (
+ if ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 21 Word.word * ii))option)) of
+ Some ((g__19, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_21_backwards : string -> M (mword ty21)\<close>\<close>
+
+definition hex_bits_21_backwards :: " string \<Rightarrow>((register_value),((21)Word.word),(exception))monad " where
+ " hex_bits_21_backwards s = (
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 21 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_22_forwards_matches : mword ty22 -> bool\<close>\<close>
+
+definition hex_bits_22_forwards_matches :: "(22)Word.word \<Rightarrow> bool " where
+ " hex_bits_22_forwards_matches bv = ( True )"
+ for bv :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_22_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_22_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_22_backwards_matches s = (
+ if ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 22 Word.word * ii))option)) of
+ Some ((g__18, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_22_backwards : string -> M (mword ty22)\<close>\<close>
+
+definition hex_bits_22_backwards :: " string \<Rightarrow>((register_value),((22)Word.word),(exception))monad " where
+ " hex_bits_22_backwards s = (
+ (case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 22 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_23_forwards_matches : mword ty23 -> bool\<close>\<close>
+
+definition hex_bits_23_forwards_matches :: "(23)Word.word \<Rightarrow> bool " where
+ " hex_bits_23_forwards_matches bv = ( True )"
+ for bv :: "(23)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_23_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_23_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_23_backwards_matches s = (
+ if ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 23 Word.word * ii))option)) of
+ Some ((g__17, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_23_backwards : string -> M (mword ty23)\<close>\<close>
+
+definition hex_bits_23_backwards :: " string \<Rightarrow>((register_value),((23)Word.word),(exception))monad " where
+ " hex_bits_23_backwards s = (
+ (case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 23 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_24_forwards_matches : mword ty24 -> bool\<close>\<close>
+
+definition hex_bits_24_forwards_matches :: "(24)Word.word \<Rightarrow> bool " where
+ " hex_bits_24_forwards_matches bv = ( True )"
+ for bv :: "(24)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_24_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_24_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_24_backwards_matches s = (
+ if ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 24 Word.word * ii))option)) of
+ Some ((g__16, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_24_backwards : string -> M (mword ty24)\<close>\<close>
+
+definition hex_bits_24_backwards :: " string \<Rightarrow>((register_value),((24)Word.word),(exception))monad " where
+ " hex_bits_24_backwards s = (
+ (case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 24 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_25_forwards_matches : mword ty25 -> bool\<close>\<close>
+
+definition hex_bits_25_forwards_matches :: "(25)Word.word \<Rightarrow> bool " where
+ " hex_bits_25_forwards_matches bv = ( True )"
+ for bv :: "(25)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_25_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_25_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_25_backwards_matches s = (
+ if ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 25 Word.word * ii))option)) of
+ Some ((g__15, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_25_backwards : string -> M (mword ty25)\<close>\<close>
+
+definition hex_bits_25_backwards :: " string \<Rightarrow>((register_value),((25)Word.word),(exception))monad " where
+ " hex_bits_25_backwards s = (
+ (case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 25 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_26_forwards_matches : mword ty26 -> bool\<close>\<close>
+
+definition hex_bits_26_forwards_matches :: "(26)Word.word \<Rightarrow> bool " where
+ " hex_bits_26_forwards_matches bv = ( True )"
+ for bv :: "(26)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_26_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_26_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_26_backwards_matches s = (
+ if ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 26 Word.word * ii))option)) of
+ Some ((g__14, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_26_backwards : string -> M (mword ty26)\<close>\<close>
+
+definition hex_bits_26_backwards :: " string \<Rightarrow>((register_value),((26)Word.word),(exception))monad " where
+ " hex_bits_26_backwards s = (
+ (case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 26 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_27_forwards_matches : mword ty27 -> bool\<close>\<close>
+
+definition hex_bits_27_forwards_matches :: "(27)Word.word \<Rightarrow> bool " where
+ " hex_bits_27_forwards_matches bv = ( True )"
+ for bv :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_27_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_27_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_27_backwards_matches s = (
+ if ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 27 Word.word * ii))option)) of
+ Some ((g__13, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_27_backwards : string -> M (mword ty27)\<close>\<close>
+
+definition hex_bits_27_backwards :: " string \<Rightarrow>((register_value),((27)Word.word),(exception))monad " where
+ " hex_bits_27_backwards s = (
+ (case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 27 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_28_forwards_matches : mword ty28 -> bool\<close>\<close>
+
+definition hex_bits_28_forwards_matches :: "(28)Word.word \<Rightarrow> bool " where
+ " hex_bits_28_forwards_matches bv = ( True )"
+ for bv :: "(28)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_28_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_28_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_28_backwards_matches s = (
+ if ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 28 Word.word * ii))option)) of
+ Some ((g__12, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_28_backwards : string -> M (mword ty28)\<close>\<close>
+
+definition hex_bits_28_backwards :: " string \<Rightarrow>((register_value),((28)Word.word),(exception))monad " where
+ " hex_bits_28_backwards s = (
+ (case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 28 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_29_forwards_matches : mword ty29 -> bool\<close>\<close>
+
+definition hex_bits_29_forwards_matches :: "(29)Word.word \<Rightarrow> bool " where
+ " hex_bits_29_forwards_matches bv = ( True )"
+ for bv :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_29_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_29_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_29_backwards_matches s = (
+ if ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 29 Word.word * ii))option)) of
+ Some ((g__11, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_29_backwards : string -> M (mword ty29)\<close>\<close>
+
+definition hex_bits_29_backwards :: " string \<Rightarrow>((register_value),((29)Word.word),(exception))monad " where
+ " hex_bits_29_backwards s = (
+ (case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 29 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_30_forwards_matches : mword ty30 -> bool\<close>\<close>
+
+definition hex_bits_30_forwards_matches :: "(30)Word.word \<Rightarrow> bool " where
+ " hex_bits_30_forwards_matches bv = ( True )"
+ for bv :: "(30)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_30_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_30_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_30_backwards_matches s = (
+ if ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 30 Word.word * ii))option)) of
+ Some ((g__10, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_30_backwards : string -> M (mword ty30)\<close>\<close>
+
+definition hex_bits_30_backwards :: " string \<Rightarrow>((register_value),((30)Word.word),(exception))monad " where
+ " hex_bits_30_backwards s = (
+ (case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 30 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_31_forwards_matches : mword ty31 -> bool\<close>\<close>
+
+definition hex_bits_31_forwards_matches :: "(31)Word.word \<Rightarrow> bool " where
+ " hex_bits_31_forwards_matches bv = ( True )"
+ for bv :: "(31)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_31_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_31_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_31_backwards_matches s = (
+ if ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 31 Word.word * ii))option)) of
+ Some ((g__9, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_31_backwards : string -> M (mword ty31)\<close>\<close>
+
+definition hex_bits_31_backwards :: " string \<Rightarrow>((register_value),((31)Word.word),(exception))monad " where
+ " hex_bits_31_backwards s = (
+ (case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 31 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_32_forwards_matches : mword ty32 -> bool\<close>\<close>
+
+definition hex_bits_32_forwards_matches :: "(32)Word.word \<Rightarrow> bool " where
+ " hex_bits_32_forwards_matches bv = ( True )"
+ for bv :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_32_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_32_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_32_backwards_matches s = (
+ if ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 32 Word.word * ii))option)) of
+ Some ((g__8, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_32_backwards : string -> M (mword ty32)\<close>\<close>
+
+definition hex_bits_32_backwards :: " string \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " hex_bits_32_backwards s = (
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 32 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_33_forwards_matches : mword ty33 -> bool\<close>\<close>
+
+definition hex_bits_33_forwards_matches :: "(33)Word.word \<Rightarrow> bool " where
+ " hex_bits_33_forwards_matches bv = ( True )"
+ for bv :: "(33)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_33_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_33_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_33_backwards_matches s = (
+ if ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 33 Word.word * ii))option)) of
+ Some ((g__7, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_33_backwards : string -> M (mword ty33)\<close>\<close>
+
+definition hex_bits_33_backwards :: " string \<Rightarrow>((register_value),((33)Word.word),(exception))monad " where
+ " hex_bits_33_backwards s = (
+ (case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 33 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_48_forwards_matches : mword ty48 -> bool\<close>\<close>
+
+definition hex_bits_48_forwards_matches :: "(48)Word.word \<Rightarrow> bool " where
+ " hex_bits_48_forwards_matches bv = ( True )"
+ for bv :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_48_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_48_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_48_backwards_matches s = (
+ if ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 48 Word.word * ii))option)) of
+ Some ((g__6, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_48_backwards : string -> M (mword ty48)\<close>\<close>
+
+definition hex_bits_48_backwards :: " string \<Rightarrow>((register_value),((48)Word.word),(exception))monad " where
+ " hex_bits_48_backwards s = (
+ (case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 48 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_64_forwards_matches : mword ty64 -> bool\<close>\<close>
+
+definition hex_bits_64_forwards_matches :: "(64)Word.word \<Rightarrow> bool " where
+ " hex_bits_64_forwards_matches bv = ( True )"
+ for bv :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_64_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_64_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_64_backwards_matches s = (
+ if ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 64 Word.word * ii))option)) of
+ Some ((g__5, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_64_backwards : string -> M (mword ty64)\<close>\<close>
+
+definition hex_bits_64_backwards :: " string \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " hex_bits_64_backwards s = (
+ (case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 64 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+definition default_meta :: " unit " where
+ " default_meta = ( () )"
+
+
+\<comment> \<open>\<open>val __WriteRAM_Meta : mword ty32 -> integer -> unit -> M unit\<close>\<close>
+
+definition WriteRAM_Meta :: "(32)Word.word \<Rightarrow> int \<Rightarrow> unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " WriteRAM_Meta addr width meta = ( return () )"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val __ReadRAM_Meta : mword ty32 -> integer -> M unit\<close>\<close>
+
+definition ReadRAM_Meta :: "(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ReadRAM_Meta addr width = ( return () )"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val write_ram : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M bool\<close>\<close>
+
+definition write_ram :: " write_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " write_ram wk addr width data meta = (
+ write_mem instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 32 :: int)::ii) addr width data \<bind> (\<lambda> (ret :: bool) .
+ (if ret then WriteRAM_Meta addr width meta else return () ) \<then> return ret))"
+ for wk :: " write_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val write_ram_ea : write_kind -> mword ty32 -> integer -> M unit\<close>\<close>
+
+definition write_ram_ea :: " write_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " write_ram_ea wk addr width = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 32 :: int)::ii) addr width )"
+ for wk :: " write_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val read_ram : forall 'int8_times_n. Size 'int8_times_n => read_kind -> mword ty32 -> integer -> M (mword 'int8_times_n)\<close>\<close>
+
+definition read_ram :: " read_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('int8_times_n::len)Word.word),(exception))monad " where
+ " read_ram rk addr width = ( (read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rk (( 32 :: int)::ii) addr width :: (( 'int8_times_n::len)Word.word) M))"
+ for rk :: " read_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val __TraceMemoryWrite : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit\<close>\<close>
+
+\<comment> \<open>\<open>val __TraceMemoryRead : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit\<close>\<close>
+
+definition xlen_val :: " int " where
+ " xlen_val = ( (( 32 :: int)::ii))"
+
+
+definition xlen_max_unsigned :: " int " where
+ " xlen_max_unsigned = ( ((pow2 (( 32 :: int)::ii))) - (( 1 :: int)::ii))"
+
+
+definition xlen_max_signed :: " int " where
+ " xlen_max_signed = ( ((pow2 (((( 32 :: int)::ii) - (( 1 :: int)::ii))))) - (( 1 :: int)::ii))"
+
+
+definition xlen_min_signed :: " int " where
+ " xlen_min_signed = ( (( 0 :: int)::ii) - ((pow2 (((( 32 :: int)::ii) - (( 1 :: int)::ii))))))"
+
+
+\<comment> \<open>\<open>val regidx_to_regno : mword ty5 -> integer\<close>\<close>
+
+definition regidx_to_regno :: "(5)Word.word \<Rightarrow> int " where
+ " regidx_to_regno b = (
+ (let r = (Word.uint b) in
+ r))"
+ for b :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val creg2reg_idx : mword ty3 -> mword ty5\<close>\<close>
+
+definition creg2reg_idx :: "(3)Word.word \<Rightarrow>(5)Word.word " where
+ " creg2reg_idx creg = ( (concat_vec (vec_of_bits [B0,B1] :: 2 Word.word) creg :: 5 Word.word))"
+ for creg :: "(3)Word.word "
+
+
+definition zreg :: "(5)Word.word " where
+ " zreg = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))"
+
+
+definition ra :: "(5)Word.word " where
+ " ra = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))"
+
+
+definition sp :: "(5)Word.word " where
+ " sp = ( (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))"
+
+
+\<comment> \<open>\<open>val Architecture_of_num : integer -> Architecture\<close>\<close>
+
+definition Architecture_of_num :: " int \<Rightarrow> Architecture " where
+ " Architecture_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RV32
+ else if (((p00 = (( 1 :: int)::ii)))) then RV64
+ else RV128))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Architecture : Architecture -> integer\<close>\<close>
+
+fun num_of_Architecture :: " Architecture \<Rightarrow> int " where
+ " num_of_Architecture RV32 = ( (( 0 :: int)::ii))"
+|" num_of_Architecture RV64 = ( (( 1 :: int)::ii))"
+|" num_of_Architecture RV128 = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val architecture : mword ty2 -> maybe Architecture\<close>\<close>
+
+definition architecture :: "(2)Word.word \<Rightarrow>(Architecture)option " where
+ " architecture a = (
+ (let b__0 = a in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Some RV32
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Some RV64
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then Some RV128
+ else None))"
+ for a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val arch_to_bits : Architecture -> mword ty2\<close>\<close>
+
+fun arch_to_bits :: " Architecture \<Rightarrow>(2)Word.word " where
+ " arch_to_bits RV32 = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" arch_to_bits RV64 = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" arch_to_bits RV128 = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val Privilege_of_num : integer -> Privilege\<close>\<close>
+
+definition Privilege_of_num :: " int \<Rightarrow> Privilege " where
+ " Privilege_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then User
+ else if (((p00 = (( 1 :: int)::ii)))) then Supervisor
+ else Machine))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Privilege : Privilege -> integer\<close>\<close>
+
+fun num_of_Privilege :: " Privilege \<Rightarrow> int " where
+ " num_of_Privilege User = ( (( 0 :: int)::ii))"
+|" num_of_Privilege Supervisor = ( (( 1 :: int)::ii))"
+|" num_of_Privilege Machine = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val privLevel_to_bits : Privilege -> mword ty2\<close>\<close>
+
+fun privLevel_to_bits :: " Privilege \<Rightarrow>(2)Word.word " where
+ " privLevel_to_bits User = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" privLevel_to_bits Supervisor = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" privLevel_to_bits Machine = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val privLevel_of_bits : mword ty2 -> M Privilege\<close>\<close>
+
+definition privLevel_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " privLevel_of_bits p = (
+ (let b__0 = p in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return User
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return Supervisor
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return Machine
+ else assert_exp False (''Pattern match failure at model/riscv_types.sail 78:2 - 82:3'') \<then> exit0 () ))"
+ for p :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val privLevel_to_str : Privilege -> string\<close>\<close>
+
+fun privLevel_to_str :: " Privilege \<Rightarrow> string " where
+ " privLevel_to_str User = ( (''U''))"
+|" privLevel_to_str Supervisor = ( (''S''))"
+|" privLevel_to_str Machine = ( (''M''))"
+
+
+\<comment> \<open>\<open>val print_insn : ast -> M string\<close>\<close>
+
+\<comment> \<open>\<open>val Retired_of_num : integer -> Retired\<close>\<close>
+
+definition Retired_of_num :: " int \<Rightarrow> Retired " where
+ " Retired_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RETIRE_SUCCESS
+ else RETIRE_FAIL))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Retired : Retired -> integer\<close>\<close>
+
+fun num_of_Retired :: " Retired \<Rightarrow> int " where
+ " num_of_Retired RETIRE_SUCCESS = ( (( 0 :: int)::ii))"
+|" num_of_Retired RETIRE_FAIL = ( (( 1 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val AccessType_of_num : integer -> AccessType\<close>\<close>
+
+definition AccessType_of_num :: " int \<Rightarrow> AccessType " where
+ " AccessType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Read
+ else if (((p00 = (( 1 :: int)::ii)))) then Write
+ else if (((p00 = (( 2 :: int)::ii)))) then ReadWrite
+ else Execute))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_AccessType : AccessType -> integer\<close>\<close>
+
+fun num_of_AccessType :: " AccessType \<Rightarrow> int " where
+ " num_of_AccessType Read = ( (( 0 :: int)::ii))"
+|" num_of_AccessType Write = ( (( 1 :: int)::ii))"
+|" num_of_AccessType ReadWrite = ( (( 2 :: int)::ii))"
+|" num_of_AccessType Execute = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val accessType_to_str : AccessType -> string\<close>\<close>
+
+fun accessType_to_str :: " AccessType \<Rightarrow> string " where
+ " accessType_to_str Read = ( (''R''))"
+|" accessType_to_str Write = ( (''W''))"
+|" accessType_to_str ReadWrite = ( (''RW''))"
+|" accessType_to_str Execute = ( (''X''))"
+
+
+\<comment> \<open>\<open>val word_width_of_num : integer -> word_width\<close>\<close>
+
+definition word_width_of_num :: " int \<Rightarrow> word_width " where
+ " word_width_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then BYTE
+ else if (((p00 = (( 1 :: int)::ii)))) then HALF
+ else if (((p00 = (( 2 :: int)::ii)))) then WORD
+ else DOUBLE))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_word_width : word_width -> integer\<close>\<close>
+
+fun num_of_word_width :: " word_width \<Rightarrow> int " where
+ " num_of_word_width BYTE = ( (( 0 :: int)::ii))"
+|" num_of_word_width HALF = ( (( 1 :: int)::ii))"
+|" num_of_word_width WORD = ( (( 2 :: int)::ii))"
+|" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val InterruptType_of_num : integer -> InterruptType\<close>\<close>
+
+definition InterruptType_of_num :: " int \<Rightarrow> InterruptType " where
+ " InterruptType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then I_U_Software
+ else if (((p00 = (( 1 :: int)::ii)))) then I_S_Software
+ else if (((p00 = (( 2 :: int)::ii)))) then I_M_Software
+ else if (((p00 = (( 3 :: int)::ii)))) then I_U_Timer
+ else if (((p00 = (( 4 :: int)::ii)))) then I_S_Timer
+ else if (((p00 = (( 5 :: int)::ii)))) then I_M_Timer
+ else if (((p00 = (( 6 :: int)::ii)))) then I_U_External
+ else if (((p00 = (( 7 :: int)::ii)))) then I_S_External
+ else I_M_External))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_InterruptType : InterruptType -> integer\<close>\<close>
+
+fun num_of_InterruptType :: " InterruptType \<Rightarrow> int " where
+ " num_of_InterruptType I_U_Software = ( (( 0 :: int)::ii))"
+|" num_of_InterruptType I_S_Software = ( (( 1 :: int)::ii))"
+|" num_of_InterruptType I_M_Software = ( (( 2 :: int)::ii))"
+|" num_of_InterruptType I_U_Timer = ( (( 3 :: int)::ii))"
+|" num_of_InterruptType I_S_Timer = ( (( 4 :: int)::ii))"
+|" num_of_InterruptType I_M_Timer = ( (( 5 :: int)::ii))"
+|" num_of_InterruptType I_U_External = ( (( 6 :: int)::ii))"
+|" num_of_InterruptType I_S_External = ( (( 7 :: int)::ii))"
+|" num_of_InterruptType I_M_External = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val interruptType_to_bits : InterruptType -> mword ty8\<close>\<close>
+
+fun interruptType_to_bits :: " InterruptType \<Rightarrow>(8)Word.word " where
+ " interruptType_to_bits I_U_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_U_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_U_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word))"
+
+
+\<comment> \<open>\<open>val ExceptionType_of_num : integer -> ExceptionType\<close>\<close>
+
+definition ExceptionType_of_num :: " int \<Rightarrow> ExceptionType " where
+ " ExceptionType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align
+ else if (((p00 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault
+ else if (((p00 = (( 2 :: int)::ii)))) then E_Illegal_Instr
+ else if (((p00 = (( 3 :: int)::ii)))) then E_Breakpoint
+ else if (((p00 = (( 4 :: int)::ii)))) then E_Load_Addr_Align
+ else if (((p00 = (( 5 :: int)::ii)))) then E_Load_Access_Fault
+ else if (((p00 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align
+ else if (((p00 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault
+ else if (((p00 = (( 8 :: int)::ii)))) then E_U_EnvCall
+ else if (((p00 = (( 9 :: int)::ii)))) then E_S_EnvCall
+ else if (((p00 = (( 10 :: int)::ii)))) then E_Reserved_10
+ else if (((p00 = (( 11 :: int)::ii)))) then E_M_EnvCall
+ else if (((p00 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault
+ else if (((p00 = (( 13 :: int)::ii)))) then E_Load_Page_Fault
+ else if (((p00 = (( 14 :: int)::ii)))) then E_Reserved_14
+ else if (((p00 = (( 15 :: int)::ii)))) then E_SAMO_Page_Fault
+ else E_CHERI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ExceptionType : ExceptionType -> integer\<close>\<close>
+
+fun num_of_ExceptionType :: " ExceptionType \<Rightarrow> int " where
+ " num_of_ExceptionType E_Fetch_Addr_Align = ( (( 0 :: int)::ii))"
+|" num_of_ExceptionType E_Fetch_Access_Fault = ( (( 1 :: int)::ii))"
+|" num_of_ExceptionType E_Illegal_Instr = ( (( 2 :: int)::ii))"
+|" num_of_ExceptionType E_Breakpoint = ( (( 3 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Addr_Align = ( (( 4 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Access_Fault = ( (( 5 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Addr_Align = ( (( 6 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Access_Fault = ( (( 7 :: int)::ii))"
+|" num_of_ExceptionType E_U_EnvCall = ( (( 8 :: int)::ii))"
+|" num_of_ExceptionType E_S_EnvCall = ( (( 9 :: int)::ii))"
+|" num_of_ExceptionType E_Reserved_10 = ( (( 10 :: int)::ii))"
+|" num_of_ExceptionType E_M_EnvCall = ( (( 11 :: int)::ii))"
+|" num_of_ExceptionType E_Fetch_Page_Fault = ( (( 12 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Page_Fault = ( (( 13 :: int)::ii))"
+|" num_of_ExceptionType E_Reserved_14 = ( (( 14 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Page_Fault = ( (( 15 :: int)::ii))"
+|" num_of_ExceptionType E_CHERI = ( (( 16 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val exceptionType_to_bits : ExceptionType -> mword ty8\<close>\<close>
+
+fun exceptionType_to_bits :: " ExceptionType \<Rightarrow>(8)Word.word " where
+ " exceptionType_to_bits E_Fetch_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Fetch_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Illegal_Instr = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Breakpoint = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_U_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_S_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Reserved_10 = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_M_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Fetch_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Reserved_14 = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_CHERI = ( (vec_of_bits [B0,B0,B1,B0,B0,B0,B0,B0] :: 8 Word.word))"
+
+
+\<comment> \<open>\<open>val exceptionType_to_str : ExceptionType -> string\<close>\<close>
+
+fun exceptionType_to_str :: " ExceptionType \<Rightarrow> string " where
+ " exceptionType_to_str E_Fetch_Addr_Align = ( (''misaligned-fetch''))"
+|" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))"
+|" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))"
+|" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))"
+|" exceptionType_to_str E_Load_Addr_Align = ( (''misaligned-load''))"
+|" exceptionType_to_str E_Load_Access_Fault = ( (''load-access-fault''))"
+|" exceptionType_to_str E_SAMO_Addr_Align = ( (''misaliged-store/amo''))"
+|" exceptionType_to_str E_SAMO_Access_Fault = ( (''store/amo-access-fault''))"
+|" exceptionType_to_str E_U_EnvCall = ( (''u-call''))"
+|" exceptionType_to_str E_S_EnvCall = ( (''s-call''))"
+|" exceptionType_to_str E_Reserved_10 = ( (''reserved-0''))"
+|" exceptionType_to_str E_M_EnvCall = ( (''m-call''))"
+|" exceptionType_to_str E_Fetch_Page_Fault = ( (''fetch-page-fault''))"
+|" exceptionType_to_str E_Load_Page_Fault = ( (''load-page-fault''))"
+|" exceptionType_to_str E_Reserved_14 = ( (''reserved-1''))"
+|" exceptionType_to_str E_SAMO_Page_Fault = ( (''store/amo-page-fault''))"
+|" exceptionType_to_str E_CHERI = ( (''CHERI''))"
+
+
+\<comment> \<open>\<open>val not_implemented : forall 'a. string -> M 'a\<close>\<close>
+
+definition not_implemented :: " string \<Rightarrow>((register_value),'a,(exception))monad " where
+ " not_implemented message = ( throw (Error_not_implemented message))"
+ for message :: " string "
+
+
+\<comment> \<open>\<open>val internal_error : forall 'a. string -> M 'a\<close>\<close>
+
+definition internal_error :: " string \<Rightarrow>((register_value),'a,(exception))monad " where
+ " internal_error s = ( assert_exp False s \<then> exit0 () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val TrapVectorMode_of_num : integer -> TrapVectorMode\<close>\<close>
+
+definition TrapVectorMode_of_num :: " int \<Rightarrow> TrapVectorMode " where
+ " TrapVectorMode_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then TV_Direct
+ else if (((p00 = (( 1 :: int)::ii)))) then TV_Vector
+ else TV_Reserved))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_TrapVectorMode : TrapVectorMode -> integer\<close>\<close>
+
+fun num_of_TrapVectorMode :: " TrapVectorMode \<Rightarrow> int " where
+ " num_of_TrapVectorMode TV_Direct = ( (( 0 :: int)::ii))"
+|" num_of_TrapVectorMode TV_Vector = ( (( 1 :: int)::ii))"
+|" num_of_TrapVectorMode TV_Reserved = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode\<close>\<close>
+
+definition trapVectorMode_of_bits :: "(2)Word.word \<Rightarrow> TrapVectorMode " where
+ " trapVectorMode_of_bits m = (
+ (let b__0 = m in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then TV_Direct
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then TV_Vector
+ else TV_Reserved))"
+ for m :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val ExtStatus_of_num : integer -> ExtStatus\<close>\<close>
+
+definition ExtStatus_of_num :: " int \<Rightarrow> ExtStatus " where
+ " ExtStatus_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Off
+ else if (((p00 = (( 1 :: int)::ii)))) then Initial
+ else if (((p00 = (( 2 :: int)::ii)))) then Clean
+ else Dirty))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ExtStatus : ExtStatus -> integer\<close>\<close>
+
+fun num_of_ExtStatus :: " ExtStatus \<Rightarrow> int " where
+ " num_of_ExtStatus Off = ( (( 0 :: int)::ii))"
+|" num_of_ExtStatus Initial = ( (( 1 :: int)::ii))"
+|" num_of_ExtStatus Clean = ( (( 2 :: int)::ii))"
+|" num_of_ExtStatus Dirty = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val extStatus_to_bits : ExtStatus -> mword ty2\<close>\<close>
+
+fun extStatus_to_bits :: " ExtStatus \<Rightarrow>(2)Word.word " where
+ " extStatus_to_bits Off = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" extStatus_to_bits Initial = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" extStatus_to_bits Clean = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" extStatus_to_bits Dirty = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val extStatus_of_bits : mword ty2 -> M ExtStatus\<close>\<close>
+
+definition extStatus_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(ExtStatus),(exception))monad " where
+ " extStatus_of_bits e = (
+ (let b__0 = e in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return Off
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return Initial
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return Clean
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return Dirty
+ else assert_exp False (''Pattern match failure at model/riscv_types.sail 264:2 - 269:3'') \<then> exit0 () ))"
+ for e :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val SATPMode_of_num : integer -> SATPMode\<close>\<close>
+
+definition SATPMode_of_num :: " int \<Rightarrow> SATPMode " where
+ " SATPMode_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Sbare
+ else if (((p00 = (( 1 :: int)::ii)))) then Sv32
+ else if (((p00 = (( 2 :: int)::ii)))) then Sv39
+ else Sv48))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_SATPMode : SATPMode -> integer\<close>\<close>
+
+fun num_of_SATPMode :: " SATPMode \<Rightarrow> int " where
+ " num_of_SATPMode Sbare = ( (( 0 :: int)::ii))"
+|" num_of_SATPMode Sv32 = ( (( 1 :: int)::ii))"
+|" num_of_SATPMode Sv39 = ( (( 2 :: int)::ii))"
+|" num_of_SATPMode Sv48 = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val satp64Mode_of_bits : Architecture -> mword ty4 -> maybe SATPMode\<close>\<close>
+
+definition satp64Mode_of_bits :: " Architecture \<Rightarrow>(4)Word.word \<Rightarrow>(SATPMode)option " where
+ " satp64Mode_of_bits (g__4 :: Architecture) (b__0 :: satp_mode) = (
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then Some Sbare
+ else
+ (case (g__4, b__0) of
+ (RV32, b__0) =>
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then Some Sv32
+ else (case (RV32, b__0) of (_, _) => None )
+ | (RV64, b__0) =>
+ if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then Some Sv39
+ else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then Some Sv48
+ else (case (RV64, b__0) of (_, _) => None )
+ | (_, _) => None
+ ))"
+ for g__4 :: " Architecture "
+ and b__0 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val uop_of_num : integer -> uop\<close>\<close>
+
+definition uop_of_num :: " int \<Rightarrow> uop " where
+ " uop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_LUI
+ else RISCV_AUIPC))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_uop : uop -> integer\<close>\<close>
+
+fun num_of_uop :: " uop \<Rightarrow> int " where
+ " num_of_uop RISCV_LUI = ( (( 0 :: int)::ii))"
+|" num_of_uop RISCV_AUIPC = ( (( 1 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val bop_of_num : integer -> bop\<close>\<close>
+
+definition bop_of_num :: " int \<Rightarrow> bop " where
+ " bop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_BEQ
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_BNE
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_BLT
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_BGE
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_BLTU
+ else RISCV_BGEU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_bop : bop -> integer\<close>\<close>
+
+fun num_of_bop :: " bop \<Rightarrow> int " where
+ " num_of_bop RISCV_BEQ = ( (( 0 :: int)::ii))"
+|" num_of_bop RISCV_BNE = ( (( 1 :: int)::ii))"
+|" num_of_bop RISCV_BLT = ( (( 2 :: int)::ii))"
+|" num_of_bop RISCV_BGE = ( (( 3 :: int)::ii))"
+|" num_of_bop RISCV_BLTU = ( (( 4 :: int)::ii))"
+|" num_of_bop RISCV_BGEU = ( (( 5 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val iop_of_num : integer -> iop\<close>\<close>
+
+definition iop_of_num :: " int \<Rightarrow> iop " where
+ " iop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDI
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SLTI
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLTIU
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_XORI
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_ORI
+ else RISCV_ANDI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_iop : iop -> integer\<close>\<close>
+
+fun num_of_iop :: " iop \<Rightarrow> int " where
+ " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))"
+|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))"
+|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))"
+|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))"
+|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))"
+|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sop_of_num : integer -> sop\<close>\<close>
+
+definition sop_of_num :: " int \<Rightarrow> sop " where
+ " sop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLI
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLI
+ else RISCV_SRAI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_sop : sop -> integer\<close>\<close>
+
+fun num_of_sop :: " sop \<Rightarrow> int " where
+ " num_of_sop RISCV_SLLI = ( (( 0 :: int)::ii))"
+|" num_of_sop RISCV_SRLI = ( (( 1 :: int)::ii))"
+|" num_of_sop RISCV_SRAI = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val rop_of_num : integer -> rop\<close>\<close>
+
+definition rop_of_num :: " int \<Rightarrow> rop " where
+ " rop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADD
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUB
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLL
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SLT
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_SLTU
+ else if (((p00 = (( 5 :: int)::ii)))) then RISCV_XOR
+ else if (((p00 = (( 6 :: int)::ii)))) then RISCV_SRL
+ else if (((p00 = (( 7 :: int)::ii)))) then RISCV_SRA
+ else if (((p00 = (( 8 :: int)::ii)))) then RISCV_OR
+ else RISCV_AND))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_rop : rop -> integer\<close>\<close>
+
+fun num_of_rop :: " rop \<Rightarrow> int " where
+ " num_of_rop RISCV_ADD = ( (( 0 :: int)::ii))"
+|" num_of_rop RISCV_SUB = ( (( 1 :: int)::ii))"
+|" num_of_rop RISCV_SLL = ( (( 2 :: int)::ii))"
+|" num_of_rop RISCV_SLT = ( (( 3 :: int)::ii))"
+|" num_of_rop RISCV_SLTU = ( (( 4 :: int)::ii))"
+|" num_of_rop RISCV_XOR = ( (( 5 :: int)::ii))"
+|" num_of_rop RISCV_SRL = ( (( 6 :: int)::ii))"
+|" num_of_rop RISCV_SRA = ( (( 7 :: int)::ii))"
+|" num_of_rop RISCV_OR = ( (( 8 :: int)::ii))"
+|" num_of_rop RISCV_AND = ( (( 9 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val ropw_of_num : integer -> ropw\<close>\<close>
+
+definition ropw_of_num :: " int \<Rightarrow> ropw " where
+ " ropw_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDW
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUBW
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLLW
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SRLW
+ else RISCV_SRAW))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ropw : ropw -> integer\<close>\<close>
+
+fun num_of_ropw :: " ropw \<Rightarrow> int " where
+ " num_of_ropw RISCV_ADDW = ( (( 0 :: int)::ii))"
+|" num_of_ropw RISCV_SUBW = ( (( 1 :: int)::ii))"
+|" num_of_ropw RISCV_SLLW = ( (( 2 :: int)::ii))"
+|" num_of_ropw RISCV_SRLW = ( (( 3 :: int)::ii))"
+|" num_of_ropw RISCV_SRAW = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sopw_of_num : integer -> sopw\<close>\<close>
+
+definition sopw_of_num :: " int \<Rightarrow> sopw " where
+ " sopw_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLIW
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLIW
+ else RISCV_SRAIW))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_sopw : sopw -> integer\<close>\<close>
+
+fun num_of_sopw :: " sopw \<Rightarrow> int " where
+ " num_of_sopw RISCV_SLLIW = ( (( 0 :: int)::ii))"
+|" num_of_sopw RISCV_SRLIW = ( (( 1 :: int)::ii))"
+|" num_of_sopw RISCV_SRAIW = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val amoop_of_num : integer -> amoop\<close>\<close>
+
+definition amoop_of_num :: " int \<Rightarrow> amoop " where
+ " amoop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then AMOSWAP
+ else if (((p00 = (( 1 :: int)::ii)))) then AMOADD
+ else if (((p00 = (( 2 :: int)::ii)))) then AMOXOR
+ else if (((p00 = (( 3 :: int)::ii)))) then AMOAND
+ else if (((p00 = (( 4 :: int)::ii)))) then AMOOR
+ else if (((p00 = (( 5 :: int)::ii)))) then AMOMIN
+ else if (((p00 = (( 6 :: int)::ii)))) then AMOMAX
+ else if (((p00 = (( 7 :: int)::ii)))) then AMOMINU
+ else AMOMAXU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_amoop : amoop -> integer\<close>\<close>
+
+fun num_of_amoop :: " amoop \<Rightarrow> int " where
+ " num_of_amoop AMOSWAP = ( (( 0 :: int)::ii))"
+|" num_of_amoop AMOADD = ( (( 1 :: int)::ii))"
+|" num_of_amoop AMOXOR = ( (( 2 :: int)::ii))"
+|" num_of_amoop AMOAND = ( (( 3 :: int)::ii))"
+|" num_of_amoop AMOOR = ( (( 4 :: int)::ii))"
+|" num_of_amoop AMOMIN = ( (( 5 :: int)::ii))"
+|" num_of_amoop AMOMAX = ( (( 6 :: int)::ii))"
+|" num_of_amoop AMOMINU = ( (( 7 :: int)::ii))"
+|" num_of_amoop AMOMAXU = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val csrop_of_num : integer -> csrop\<close>\<close>
+
+definition csrop_of_num :: " int \<Rightarrow> csrop " where
+ " csrop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then CSRRW
+ else if (((p00 = (( 1 :: int)::ii)))) then CSRRS
+ else CSRRC))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_csrop : csrop -> integer\<close>\<close>
+
+fun num_of_csrop :: " csrop \<Rightarrow> int " where
+ " num_of_csrop CSRRW = ( (( 0 :: int)::ii))"
+|" num_of_csrop CSRRS = ( (( 1 :: int)::ii))"
+|" num_of_csrop CSRRC = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sep_forwards : unit -> string\<close>\<close>
+
+definition sep_forwards :: " unit \<Rightarrow> string " where
+ " sep_forwards _ = (
+ string_append ((opt_spc_forwards () ))
+ ((string_append ('','') ((string_append ((def_spc_forwards () )) (''''))))))"
+
+
+\<comment> \<open>\<open>val sep_backwards : string -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _s0_ : string -> maybe unit\<close>\<close>
+
+definition s0 :: " string \<Rightarrow>(unit)option " where
+ " s0 s20 = (
+ (case ((opt_spc_matches_prefix0 s20)) of
+ Some ((_, s30)) =>
+ (let s41 = (string_drop s20 s30) in
+ if ((string_startswith s41 ('',''))) then
+ (case ((string_drop s41 ((string_length ('',''))))) of
+ s50 =>
+ (case ((def_spc_matches_prefix s50)) of
+ Some ((_, s61)) =>
+ (let p00 = (string_drop s50 s61) in
+ if (((p00 = ('''')))) then Some () else None)
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s20 :: " string "
+
+
+definition sep_backwards :: " string \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " sep_backwards arg1 = (
+ (let s70 = arg1 in
+ if ((case ((s0 s70)) of Some (_) => True | _ => False )) then
+ (case s0 s70 of (Some (_)) => return () )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val sep_forwards_matches : unit -> bool\<close>\<close>
+
+definition sep_forwards_matches :: " unit \<Rightarrow> bool " where
+ " sep_forwards_matches _ = ( True )"
+
+
+\<comment> \<open>\<open>val sep_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s8_ : string -> maybe unit\<close>\<close>
+
+definition s8 :: " string \<Rightarrow>(unit)option " where
+ " s8 s101 = (
+ (case ((opt_spc_matches_prefix0 s101)) of
+ Some ((_, s110)) =>
+ (let s121 = (string_drop s101 s110) in
+ if ((string_startswith s121 ('',''))) then
+ (case ((string_drop s121 ((string_length ('',''))))) of
+ s130 =>
+ (case ((def_spc_matches_prefix s130)) of
+ Some ((_, s141)) =>
+ (let p00 = (string_drop s130 s141) in
+ if (((p00 = ('''')))) then Some () else None)
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s101 :: " string "
+
+
+definition sep_backwards_matches :: " string \<Rightarrow> bool " where
+ " sep_backwards_matches arg1 = (
+ (let s150 = arg1 in
+ if ((case ((s8 s150)) of Some (_) => True | _ => False )) then
+ (case s8 s150 of (Some (_)) => True )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val sep_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s16_ : string -> maybe string\<close>\<close>
+
+definition s16 :: " string \<Rightarrow>(string)option " where
+ " s16 s181 = (
+ (case ((opt_spc_matches_prefix0 s181)) of
+ Some ((_, s190)) =>
+ (let s201 = (string_drop s181 s190) in
+ if ((string_startswith s201 ('',''))) then
+ (case ((string_drop s201 ((string_length ('',''))))) of
+ s210 =>
+ (case ((def_spc_matches_prefix s210)) of
+ Some ((_, s221)) =>
+ (case ((string_drop s210 s221)) of s1 => Some s1 )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s181 :: " string "
+
+
+definition sep_matches_prefix :: " string \<Rightarrow>(unit*int)option " where
+ " sep_matches_prefix arg1 = (
+ (let s230 = arg1 in
+ if ((case ((s16 s230)) of Some (s1) => True | _ => False )) then
+ (case s16 s230 of
+ (Some (s1)) =>
+ Some (() , ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bool_bits_forwards : bool -> mword ty1\<close>\<close>
+
+fun bool_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_bits_forwards True = ( (vec_of_bits [B1] :: 1 Word.word))"
+|" bool_bits_forwards False = ( (vec_of_bits [B0] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val bool_bits_backwards : mword ty1 -> M bool\<close>\<close>
+
+definition bool_bits_backwards :: "(1)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " bool_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_bits_forwards_matches : bool -> bool\<close>\<close>
+
+fun bool_bits_forwards_matches :: " bool \<Rightarrow> bool " where
+ " bool_bits_forwards_matches True = ( True )"
+|" bool_bits_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val bool_bits_backwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bool_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bool_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_not_bits_forwards : bool -> mword ty1\<close>\<close>
+
+fun bool_not_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_not_bits_forwards True = ( (vec_of_bits [B0] :: 1 Word.word))"
+|" bool_not_bits_forwards False = ( (vec_of_bits [B1] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val bool_not_bits_backwards : mword ty1 -> M bool\<close>\<close>
+
+definition bool_not_bits_backwards :: "(1)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " bool_not_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return True
+ else if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_not_bits_forwards_matches : bool -> bool\<close>\<close>
+
+fun bool_not_bits_forwards_matches :: " bool \<Rightarrow> bool " where
+ " bool_not_bits_forwards_matches True = ( True )"
+|" bool_not_bits_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val bool_not_bits_backwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bool_not_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bool_not_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val size_bits_forwards : word_width -> mword ty2\<close>\<close>
+
+fun size_bits_forwards :: " word_width \<Rightarrow>(2)Word.word " where
+ " size_bits_forwards BYTE = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" size_bits_forwards HALF = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" size_bits_forwards WORD = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" size_bits_forwards DOUBLE = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val size_bits_backwards : mword ty2 -> M word_width\<close>\<close>
+
+definition size_bits_backwards :: "(2)Word.word \<Rightarrow>((register_value),(word_width),(exception))monad " where
+ " size_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return BYTE
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return HALF
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return WORD
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return DOUBLE
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val size_bits_forwards_matches : word_width -> bool\<close>\<close>
+
+fun size_bits_forwards_matches :: " word_width \<Rightarrow> bool " where
+ " size_bits_forwards_matches BYTE = ( True )"
+|" size_bits_forwards_matches HALF = ( True )"
+|" size_bits_forwards_matches WORD = ( True )"
+|" size_bits_forwards_matches DOUBLE = ( True )"
+
+
+\<comment> \<open>\<open>val size_bits_backwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition size_bits_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " size_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True
+ else False))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val size_mnemonic_forwards : word_width -> string\<close>\<close>
+
+fun size_mnemonic_forwards :: " word_width \<Rightarrow> string " where
+ " size_mnemonic_forwards BYTE = ( (''b''))"
+|" size_mnemonic_forwards HALF = ( (''h''))"
+|" size_mnemonic_forwards WORD = ( (''w''))"
+|" size_mnemonic_forwards DOUBLE = ( (''d''))"
+
+
+\<comment> \<open>\<open>val size_mnemonic_backwards : string -> M word_width\<close>\<close>
+
+definition size_mnemonic_backwards :: " string \<Rightarrow>((register_value),(word_width),(exception))monad " where
+ " size_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''b'')))) then return BYTE
+ else if (((p00 = (''h'')))) then return HALF
+ else if (((p00 = (''w'')))) then return WORD
+ else if (((p00 = (''d'')))) then return DOUBLE
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val size_mnemonic_forwards_matches : word_width -> bool\<close>\<close>
+
+fun size_mnemonic_forwards_matches :: " word_width \<Rightarrow> bool " where
+ " size_mnemonic_forwards_matches BYTE = ( True )"
+|" size_mnemonic_forwards_matches HALF = ( True )"
+|" size_mnemonic_forwards_matches WORD = ( True )"
+|" size_mnemonic_forwards_matches DOUBLE = ( True )"
+
+
+\<comment> \<open>\<open>val size_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition size_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " size_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''b'')))) then True
+ else if (((p00 = (''h'')))) then True
+ else if (((p00 = (''w'')))) then True
+ else if (((p00 = (''d'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s36_ : string -> maybe string\<close>\<close>
+
+definition s36 :: " string \<Rightarrow>(string)option " where
+ " s36 s370 = (
+ (let s381 = s370 in
+ if ((string_startswith s381 (''d''))) then
+ (case ((string_drop s381 ((string_length (''d''))))) of s1 => Some s1 )
+ else None))"
+ for s370 :: " string "
+
+
+\<comment> \<open>\<open>val _s32_ : string -> maybe string\<close>\<close>
+
+definition s32 :: " string \<Rightarrow>(string)option " where
+ " s32 s330 = (
+ (let s341 = s330 in
+ if ((string_startswith s341 (''w''))) then
+ (case ((string_drop s341 ((string_length (''w''))))) of s1 => Some s1 )
+ else None))"
+ for s330 :: " string "
+
+
+\<comment> \<open>\<open>val _s28_ : string -> maybe string\<close>\<close>
+
+definition s28 :: " string \<Rightarrow>(string)option " where
+ " s28 s290 = (
+ (let s301 = s290 in
+ if ((string_startswith s301 (''h''))) then
+ (case ((string_drop s301 ((string_length (''h''))))) of s1 => Some s1 )
+ else None))"
+ for s290 :: " string "
+
+
+\<comment> \<open>\<open>val _s24_ : string -> maybe string\<close>\<close>
+
+definition s24 :: " string \<Rightarrow>(string)option " where
+ " s24 s250 = (
+ (let s261 = s250 in
+ if ((string_startswith s261 (''b''))) then
+ (case ((string_drop s261 ((string_length (''b''))))) of s1 => Some s1 )
+ else None))"
+ for s250 :: " string "
+
+
+definition size_mnemonic_matches_prefix :: " string \<Rightarrow>(word_width*int)option " where
+ " size_mnemonic_matches_prefix arg1 = (
+ (let s270 = arg1 in
+ if ((case ((s24 s270)) of Some (s1) => True | _ => False )) then
+ (case s24 s270 of
+ (Some (s1)) =>
+ Some (BYTE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s28 s270)) of Some (s1) => True | _ => False )) then
+ (case s28 s270 of
+ (Some (s1)) =>
+ Some (HALF, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s32 s270)) of Some (s1) => True | _ => False )) then
+ (case s32 s270 of
+ (Some (s1)) =>
+ Some (WORD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s36 s270)) of Some (s1) => True | _ => False )) then
+ (case s36 s270 of
+ (Some (s1)) =>
+ Some (DOUBLE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val word_width_bytes : word_width -> integer\<close>\<close>
+
+fun word_width_bytes :: " word_width \<Rightarrow> int " where
+ " word_width_bytes BYTE = ( (( 1 :: int)::ii))"
+|" word_width_bytes HALF = ( (( 2 :: int)::ii))"
+|" word_width_bytes WORD = ( (( 4 :: int)::ii))"
+|" word_width_bytes DOUBLE = ( (( 8 :: int)::ii))"
+
+
+definition zero_reg :: "(32)Word.word " where
+ " zero_reg = ( (EXTZ (( 32 :: int)::ii) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 32 Word.word))"
+
+
+\<comment> \<open>\<open>val RegStr : mword ty32 -> string\<close>\<close>
+
+definition RegStr :: "(32)Word.word \<Rightarrow> string " where
+ " RegStr r = ( string_of_bits r )"
+ for r :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val regval_from_reg : mword ty32 -> mword ty32\<close>\<close>
+
+definition regval_from_reg :: "(32)Word.word \<Rightarrow>(32)Word.word " where
+ " regval_from_reg r = ( r )"
+ for r :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val regval_into_reg : mword ty32 -> mword ty32\<close>\<close>
+
+definition regval_into_reg :: "(32)Word.word \<Rightarrow>(32)Word.word " where
+ " regval_into_reg v = ( v )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val rX : integer -> M (mword ty32)\<close>\<close>
+
+definition rX :: " int \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " rX r = (
+ (let p00 = r in
+ (if (((p00 = (( 0 :: int)::ii)))) then return zero_reg
+ else if (((p00 = (( 1 :: int)::ii)))) then (read_reg x1_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 2 :: int)::ii)))) then (read_reg x2_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 3 :: int)::ii)))) then (read_reg x3_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 4 :: int)::ii)))) then (read_reg x4_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 5 :: int)::ii)))) then (read_reg x5_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 6 :: int)::ii)))) then (read_reg x6_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 7 :: int)::ii)))) then (read_reg x7_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 8 :: int)::ii)))) then (read_reg x8_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 9 :: int)::ii)))) then (read_reg x9_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 10 :: int)::ii)))) then (read_reg x10_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 11 :: int)::ii)))) then (read_reg x11_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 12 :: int)::ii)))) then (read_reg x12_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 13 :: int)::ii)))) then (read_reg x13_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 14 :: int)::ii)))) then (read_reg x14_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 15 :: int)::ii)))) then (read_reg x15_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 16 :: int)::ii)))) then (read_reg x16_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 17 :: int)::ii)))) then (read_reg x17_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 18 :: int)::ii)))) then (read_reg x18_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 19 :: int)::ii)))) then (read_reg x19_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 20 :: int)::ii)))) then (read_reg x20_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 21 :: int)::ii)))) then (read_reg x21_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 22 :: int)::ii)))) then (read_reg x22_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 23 :: int)::ii)))) then (read_reg x23_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 24 :: int)::ii)))) then (read_reg x24_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 25 :: int)::ii)))) then (read_reg x25_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 26 :: int)::ii)))) then (read_reg x26_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 27 :: int)::ii)))) then (read_reg x27_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 28 :: int)::ii)))) then (read_reg x28_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 29 :: int)::ii)))) then (read_reg x29_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 30 :: int)::ii)))) then (read_reg x30_ref :: ( 32 Word.word) M)
+ else if (((p00 = (( 31 :: int)::ii)))) then (read_reg x31_ref :: ( 32 Word.word) M)
+ else assert_exp False (''invalid register number'') \<then> exit0 () ) \<bind> (\<lambda> (v :: regtype) .
+ return ((regval_from_reg v :: 32 Word.word)))))"
+ for r :: " int "
+
+
+\<comment> \<open>\<open>val rvfi_wX : integer -> mword ty32 -> unit\<close>\<close>
+
+definition rvfi_wX :: " int \<Rightarrow>(32)Word.word \<Rightarrow> unit " where
+ " rvfi_wX r v = ( () )"
+ for r :: " int "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val wX : integer -> mword ty32 -> M unit\<close>\<close>
+
+definition wX :: " int \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " wX r in_v = (
+ (let v = ((regval_into_reg in_v :: 32 Word.word)) in
+ (let p00 = r in
+ (if (((p00 = (( 0 :: int)::ii)))) then return ()
+ else if (((p00 = (( 1 :: int)::ii)))) then write_reg x1_ref v
+ else if (((p00 = (( 2 :: int)::ii)))) then write_reg x2_ref v
+ else if (((p00 = (( 3 :: int)::ii)))) then write_reg x3_ref v
+ else if (((p00 = (( 4 :: int)::ii)))) then write_reg x4_ref v
+ else if (((p00 = (( 5 :: int)::ii)))) then write_reg x5_ref v
+ else if (((p00 = (( 6 :: int)::ii)))) then write_reg x6_ref v
+ else if (((p00 = (( 7 :: int)::ii)))) then write_reg x7_ref v
+ else if (((p00 = (( 8 :: int)::ii)))) then write_reg x8_ref v
+ else if (((p00 = (( 9 :: int)::ii)))) then write_reg x9_ref v
+ else if (((p00 = (( 10 :: int)::ii)))) then write_reg x10_ref v
+ else if (((p00 = (( 11 :: int)::ii)))) then write_reg x11_ref v
+ else if (((p00 = (( 12 :: int)::ii)))) then write_reg x12_ref v
+ else if (((p00 = (( 13 :: int)::ii)))) then write_reg x13_ref v
+ else if (((p00 = (( 14 :: int)::ii)))) then write_reg x14_ref v
+ else if (((p00 = (( 15 :: int)::ii)))) then write_reg x15_ref v
+ else if (((p00 = (( 16 :: int)::ii)))) then write_reg x16_ref v
+ else if (((p00 = (( 17 :: int)::ii)))) then write_reg x17_ref v
+ else if (((p00 = (( 18 :: int)::ii)))) then write_reg x18_ref v
+ else if (((p00 = (( 19 :: int)::ii)))) then write_reg x19_ref v
+ else if (((p00 = (( 20 :: int)::ii)))) then write_reg x20_ref v
+ else if (((p00 = (( 21 :: int)::ii)))) then write_reg x21_ref v
+ else if (((p00 = (( 22 :: int)::ii)))) then write_reg x22_ref v
+ else if (((p00 = (( 23 :: int)::ii)))) then write_reg x23_ref v
+ else if (((p00 = (( 24 :: int)::ii)))) then write_reg x24_ref v
+ else if (((p00 = (( 25 :: int)::ii)))) then write_reg x25_ref v
+ else if (((p00 = (( 26 :: int)::ii)))) then write_reg x26_ref v
+ else if (((p00 = (( 27 :: int)::ii)))) then write_reg x27_ref v
+ else if (((p00 = (( 28 :: int)::ii)))) then write_reg x28_ref v
+ else if (((p00 = (( 29 :: int)::ii)))) then write_reg x29_ref v
+ else if (((p00 = (( 30 :: int)::ii)))) then write_reg x30_ref v
+ else if (((p00 = (( 31 :: int)::ii)))) then write_reg x31_ref v
+ else assert_exp False (''invalid register number'') \<then> exit0 () ) \<then>
+ return (if (((r \<noteq> (( 0 :: int)::ii)))) then
+ (let (_ :: unit) = (rvfi_wX r in_v) in
+ if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''x'')
+ (((@) ((stringFromInteger r)) (((@) ('' <- '') ((RegStr v))))))))
+ else () )
+ else () ))))"
+ for r :: " int "
+ and in_v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_abi : mword ty5 -> M string\<close>\<close>
+
+definition reg_name_abi :: "(5)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " reg_name_abi r = (
+ (let b__0 = r in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ return (''zero'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''ra'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''sp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''gp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''tp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''fp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''a0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''a1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''a2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''a3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''a4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''a5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''a6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''a7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''s4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''s5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''s6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''s7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''s8'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s9'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s10'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s11'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''t3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t6'')
+ else assert_exp False (''Pattern match failure at model/riscv_regs.sail 149:2 - 182:3'') \<then> exit0 () ))"
+ for r :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_forwards : mword ty5 -> M string\<close>\<close>
+
+definition reg_name_forwards :: "(5)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " reg_name_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ return (''zero'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''ra'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''sp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''gp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''tp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''fp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''a0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''a1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''a2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''a3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''a4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''a5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''a6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''a7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''s4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''s5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''s6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''s7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''s8'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s9'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s10'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s11'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''t3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t6'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_backwards : string -> M (mword ty5)\<close>\<close>
+
+definition reg_name_backwards :: " string \<Rightarrow>((register_value),((5)Word.word),(exception))monad " where
+ " reg_name_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''zero'')))) then return (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''ra'')))) then return (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''sp'')))) then return (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''gp'')))) then return (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''tp'')))) then return (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''t0'')))) then return (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''t1'')))) then return (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''t2'')))) then return (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''fp'')))) then return (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s1'')))) then return (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''a0'')))) then return (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''a1'')))) then return (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''a2'')))) then return (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''a3'')))) then return (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''a4'')))) then return (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''a5'')))) then return (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''a6'')))) then return (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''a7'')))) then return (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s2'')))) then return (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s3'')))) then return (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''s4'')))) then return (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s5'')))) then return (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s6'')))) then return (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s7'')))) then return (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''s8'')))) then return (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s9'')))) then return (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s10'')))) then return (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s11'')))) then return (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''t3'')))) then return (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''t4'')))) then return (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''t5'')))) then return (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''t6'')))) then return (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val reg_name_forwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition reg_name_forwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " reg_name_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else False))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_backwards_matches : string -> bool\<close>\<close>
+
+definition reg_name_backwards_matches :: " string \<Rightarrow> bool " where
+ " reg_name_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''zero'')))) then True
+ else if (((p00 = (''ra'')))) then True
+ else if (((p00 = (''sp'')))) then True
+ else if (((p00 = (''gp'')))) then True
+ else if (((p00 = (''tp'')))) then True
+ else if (((p00 = (''t0'')))) then True
+ else if (((p00 = (''t1'')))) then True
+ else if (((p00 = (''t2'')))) then True
+ else if (((p00 = (''fp'')))) then True
+ else if (((p00 = (''s1'')))) then True
+ else if (((p00 = (''a0'')))) then True
+ else if (((p00 = (''a1'')))) then True
+ else if (((p00 = (''a2'')))) then True
+ else if (((p00 = (''a3'')))) then True
+ else if (((p00 = (''a4'')))) then True
+ else if (((p00 = (''a5'')))) then True
+ else if (((p00 = (''a6'')))) then True
+ else if (((p00 = (''a7'')))) then True
+ else if (((p00 = (''s2'')))) then True
+ else if (((p00 = (''s3'')))) then True
+ else if (((p00 = (''s4'')))) then True
+ else if (((p00 = (''s5'')))) then True
+ else if (((p00 = (''s6'')))) then True
+ else if (((p00 = (''s7'')))) then True
+ else if (((p00 = (''s8'')))) then True
+ else if (((p00 = (''s9'')))) then True
+ else if (((p00 = (''s10'')))) then True
+ else if (((p00 = (''s11'')))) then True
+ else if (((p00 = (''t3'')))) then True
+ else if (((p00 = (''t4'')))) then True
+ else if (((p00 = (''t5'')))) then True
+ else if (((p00 = (''t6'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s164_ : string -> maybe string\<close>\<close>
+
+definition s164 :: " string \<Rightarrow>(string)option " where
+ " s164 s1650 = (
+ (let s1660 = s1650 in
+ if ((string_startswith s1660 (''t6''))) then
+ (case ((string_drop s1660 ((string_length (''t6''))))) of s1 => Some s1 )
+ else None))"
+ for s1650 :: " string "
+
+
+\<comment> \<open>\<open>val _s160_ : string -> maybe string\<close>\<close>
+
+definition s160 :: " string \<Rightarrow>(string)option " where
+ " s160 s1610 = (
+ (let s1620 = s1610 in
+ if ((string_startswith s1620 (''t5''))) then
+ (case ((string_drop s1620 ((string_length (''t5''))))) of s1 => Some s1 )
+ else None))"
+ for s1610 :: " string "
+
+
+\<comment> \<open>\<open>val _s156_ : string -> maybe string\<close>\<close>
+
+definition s156 :: " string \<Rightarrow>(string)option " where
+ " s156 s1570 = (
+ (let s1581 = s1570 in
+ if ((string_startswith s1581 (''t4''))) then
+ (case ((string_drop s1581 ((string_length (''t4''))))) of s1 => Some s1 )
+ else None))"
+ for s1570 :: " string "
+
+
+\<comment> \<open>\<open>val _s152_ : string -> maybe string\<close>\<close>
+
+definition s152 :: " string \<Rightarrow>(string)option " where
+ " s152 s1530 = (
+ (let s1540 = s1530 in
+ if ((string_startswith s1540 (''t3''))) then
+ (case ((string_drop s1540 ((string_length (''t3''))))) of s1 => Some s1 )
+ else None))"
+ for s1530 :: " string "
+
+
+\<comment> \<open>\<open>val _s148_ : string -> maybe string\<close>\<close>
+
+definition s148 :: " string \<Rightarrow>(string)option " where
+ " s148 s1490 = (
+ (let s1500 = s1490 in
+ if ((string_startswith s1500 (''s11''))) then
+ (case ((string_drop s1500 ((string_length (''s11''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s1490 :: " string "
+
+
+\<comment> \<open>\<open>val _s144_ : string -> maybe string\<close>\<close>
+
+definition s144 :: " string \<Rightarrow>(string)option " where
+ " s144 s1450 = (
+ (let s1460 = s1450 in
+ if ((string_startswith s1460 (''s10''))) then
+ (case ((string_drop s1460 ((string_length (''s10''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s1450 :: " string "
+
+
+\<comment> \<open>\<open>val _s140_ : string -> maybe string\<close>\<close>
+
+definition s140 :: " string \<Rightarrow>(string)option " where
+ " s140 s1410 = (
+ (let s1420 = s1410 in
+ if ((string_startswith s1420 (''s9''))) then
+ (case ((string_drop s1420 ((string_length (''s9''))))) of s1 => Some s1 )
+ else None))"
+ for s1410 :: " string "
+
+
+\<comment> \<open>\<open>val _s136_ : string -> maybe string\<close>\<close>
+
+definition s136 :: " string \<Rightarrow>(string)option " where
+ " s136 s1370 = (
+ (let s1380 = s1370 in
+ if ((string_startswith s1380 (''s8''))) then
+ (case ((string_drop s1380 ((string_length (''s8''))))) of s1 => Some s1 )
+ else None))"
+ for s1370 :: " string "
+
+
+\<comment> \<open>\<open>val _s132_ : string -> maybe string\<close>\<close>
+
+definition s132 :: " string \<Rightarrow>(string)option " where
+ " s132 s1330 = (
+ (let s1340 = s1330 in
+ if ((string_startswith s1340 (''s7''))) then
+ (case ((string_drop s1340 ((string_length (''s7''))))) of s1 => Some s1 )
+ else None))"
+ for s1330 :: " string "
+
+
+\<comment> \<open>\<open>val _s128_ : string -> maybe string\<close>\<close>
+
+definition s128 :: " string \<Rightarrow>(string)option " where
+ " s128 s1290 = (
+ (let s1300 = s1290 in
+ if ((string_startswith s1300 (''s6''))) then
+ (case ((string_drop s1300 ((string_length (''s6''))))) of s1 => Some s1 )
+ else None))"
+ for s1290 :: " string "
+
+
+\<comment> \<open>\<open>val _s124_ : string -> maybe string\<close>\<close>
+
+definition s124 :: " string \<Rightarrow>(string)option " where
+ " s124 s1250 = (
+ (let s1260 = s1250 in
+ if ((string_startswith s1260 (''s5''))) then
+ (case ((string_drop s1260 ((string_length (''s5''))))) of s1 => Some s1 )
+ else None))"
+ for s1250 :: " string "
+
+
+\<comment> \<open>\<open>val _s120_ : string -> maybe string\<close>\<close>
+
+definition s120 :: " string \<Rightarrow>(string)option " where
+ " s120 s1210 = (
+ (let s1220 = s1210 in
+ if ((string_startswith s1220 (''s4''))) then
+ (case ((string_drop s1220 ((string_length (''s4''))))) of s1 => Some s1 )
+ else None))"
+ for s1210 :: " string "
+
+
+\<comment> \<open>\<open>val _s116_ : string -> maybe string\<close>\<close>
+
+definition s116 :: " string \<Rightarrow>(string)option " where
+ " s116 s1170 = (
+ (let s1180 = s1170 in
+ if ((string_startswith s1180 (''s3''))) then
+ (case ((string_drop s1180 ((string_length (''s3''))))) of s1 => Some s1 )
+ else None))"
+ for s1170 :: " string "
+
+
+\<comment> \<open>\<open>val _s112_ : string -> maybe string\<close>\<close>
+
+definition s112 :: " string \<Rightarrow>(string)option " where
+ " s112 s1130 = (
+ (let s1140 = s1130 in
+ if ((string_startswith s1140 (''s2''))) then
+ (case ((string_drop s1140 ((string_length (''s2''))))) of s1 => Some s1 )
+ else None))"
+ for s1130 :: " string "
+
+
+\<comment> \<open>\<open>val _s108_ : string -> maybe string\<close>\<close>
+
+definition s108 :: " string \<Rightarrow>(string)option " where
+ " s108 s1090 = (
+ (let s1100 = s1090 in
+ if ((string_startswith s1100 (''a7''))) then
+ (case ((string_drop s1100 ((string_length (''a7''))))) of s1 => Some s1 )
+ else None))"
+ for s1090 :: " string "
+
+
+\<comment> \<open>\<open>val _s104_ : string -> maybe string\<close>\<close>
+
+definition s104 :: " string \<Rightarrow>(string)option " where
+ " s104 s1050 = (
+ (let s1060 = s1050 in
+ if ((string_startswith s1060 (''a6''))) then
+ (case ((string_drop s1060 ((string_length (''a6''))))) of s1 => Some s1 )
+ else None))"
+ for s1050 :: " string "
+
+
+\<comment> \<open>\<open>val _s100_ : string -> maybe string\<close>\<close>
+
+definition s100 :: " string \<Rightarrow>(string)option " where
+ " s100 s1010 = (
+ (let s1020 = s1010 in
+ if ((string_startswith s1020 (''a5''))) then
+ (case ((string_drop s1020 ((string_length (''a5''))))) of s1 => Some s1 )
+ else None))"
+ for s1010 :: " string "
+
+
+\<comment> \<open>\<open>val _s96_ : string -> maybe string\<close>\<close>
+
+definition s96 :: " string \<Rightarrow>(string)option " where
+ " s96 s970 = (
+ (let s981 = s970 in
+ if ((string_startswith s981 (''a4''))) then
+ (case ((string_drop s981 ((string_length (''a4''))))) of s1 => Some s1 )
+ else None))"
+ for s970 :: " string "
+
+
+\<comment> \<open>\<open>val _s92_ : string -> maybe string\<close>\<close>
+
+definition s92 :: " string \<Rightarrow>(string)option " where
+ " s92 s930 = (
+ (let s940 = s930 in
+ if ((string_startswith s940 (''a3''))) then
+ (case ((string_drop s940 ((string_length (''a3''))))) of s1 => Some s1 )
+ else None))"
+ for s930 :: " string "
+
+
+\<comment> \<open>\<open>val _s88_ : string -> maybe string\<close>\<close>
+
+definition s88 :: " string \<Rightarrow>(string)option " where
+ " s88 s890 = (
+ (let s900 = s890 in
+ if ((string_startswith s900 (''a2''))) then
+ (case ((string_drop s900 ((string_length (''a2''))))) of s1 => Some s1 )
+ else None))"
+ for s890 :: " string "
+
+
+\<comment> \<open>\<open>val _s84_ : string -> maybe string\<close>\<close>
+
+definition s84 :: " string \<Rightarrow>(string)option " where
+ " s84 s850 = (
+ (let s860 = s850 in
+ if ((string_startswith s860 (''a1''))) then
+ (case ((string_drop s860 ((string_length (''a1''))))) of s1 => Some s1 )
+ else None))"
+ for s850 :: " string "
+
+
+\<comment> \<open>\<open>val _s80_ : string -> maybe string\<close>\<close>
+
+definition s80 :: " string \<Rightarrow>(string)option " where
+ " s80 s810 = (
+ (let s820 = s810 in
+ if ((string_startswith s820 (''a0''))) then
+ (case ((string_drop s820 ((string_length (''a0''))))) of s1 => Some s1 )
+ else None))"
+ for s810 :: " string "
+
+
+\<comment> \<open>\<open>val _s76_ : string -> maybe string\<close>\<close>
+
+definition s76 :: " string \<Rightarrow>(string)option " where
+ " s76 s770 = (
+ (let s780 = s770 in
+ if ((string_startswith s780 (''s1''))) then
+ (case ((string_drop s780 ((string_length (''s1''))))) of s1 => Some s1 )
+ else None))"
+ for s770 :: " string "
+
+
+\<comment> \<open>\<open>val _s72_ : string -> maybe string\<close>\<close>
+
+definition s72 :: " string \<Rightarrow>(string)option " where
+ " s72 s730 = (
+ (let s740 = s730 in
+ if ((string_startswith s740 (''fp''))) then
+ (case ((string_drop s740 ((string_length (''fp''))))) of s1 => Some s1 )
+ else None))"
+ for s730 :: " string "
+
+
+\<comment> \<open>\<open>val _s68_ : string -> maybe string\<close>\<close>
+
+definition s68 :: " string \<Rightarrow>(string)option " where
+ " s68 s690 = (
+ (let s701 = s690 in
+ if ((string_startswith s701 (''t2''))) then
+ (case ((string_drop s701 ((string_length (''t2''))))) of s1 => Some s1 )
+ else None))"
+ for s690 :: " string "
+
+
+\<comment> \<open>\<open>val _s64_ : string -> maybe string\<close>\<close>
+
+definition s64 :: " string \<Rightarrow>(string)option " where
+ " s64 s650 = (
+ (let s661 = s650 in
+ if ((string_startswith s661 (''t1''))) then
+ (case ((string_drop s661 ((string_length (''t1''))))) of s1 => Some s1 )
+ else None))"
+ for s650 :: " string "
+
+
+\<comment> \<open>\<open>val _s60_ : string -> maybe string\<close>\<close>
+
+definition s60 :: " string \<Rightarrow>(string)option " where
+ " s60 s610 = (
+ (let s621 = s610 in
+ if ((string_startswith s621 (''t0''))) then
+ (case ((string_drop s621 ((string_length (''t0''))))) of s1 => Some s1 )
+ else None))"
+ for s610 :: " string "
+
+
+\<comment> \<open>\<open>val _s56_ : string -> maybe string\<close>\<close>
+
+definition s56 :: " string \<Rightarrow>(string)option " where
+ " s56 s570 = (
+ (let s581 = s570 in
+ if ((string_startswith s581 (''tp''))) then
+ (case ((string_drop s581 ((string_length (''tp''))))) of s1 => Some s1 )
+ else None))"
+ for s570 :: " string "
+
+
+\<comment> \<open>\<open>val _s52_ : string -> maybe string\<close>\<close>
+
+definition s52 :: " string \<Rightarrow>(string)option " where
+ " s52 s530 = (
+ (let s541 = s530 in
+ if ((string_startswith s541 (''gp''))) then
+ (case ((string_drop s541 ((string_length (''gp''))))) of s1 => Some s1 )
+ else None))"
+ for s530 :: " string "
+
+
+\<comment> \<open>\<open>val _s48_ : string -> maybe string\<close>\<close>
+
+definition s48 :: " string \<Rightarrow>(string)option " where
+ " s48 s490 = (
+ (let s501 = s490 in
+ if ((string_startswith s501 (''sp''))) then
+ (case ((string_drop s501 ((string_length (''sp''))))) of s1 => Some s1 )
+ else None))"
+ for s490 :: " string "
+
+
+\<comment> \<open>\<open>val _s44_ : string -> maybe string\<close>\<close>
+
+definition s44 :: " string \<Rightarrow>(string)option " where
+ " s44 s450 = (
+ (let s461 = s450 in
+ if ((string_startswith s461 (''ra''))) then
+ (case ((string_drop s461 ((string_length (''ra''))))) of s1 => Some s1 )
+ else None))"
+ for s450 :: " string "
+
+
+\<comment> \<open>\<open>val _s40_ : string -> maybe string\<close>\<close>
+
+definition s40 :: " string \<Rightarrow>(string)option " where
+ " s40 s410 = (
+ (let s421 = s410 in
+ if ((string_startswith s421 (''zero''))) then
+ (case ((string_drop s421 ((string_length (''zero''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s410 :: " string "
+
+
+definition reg_name_matches_prefix :: " string \<Rightarrow>((5)Word.word*int)option " where
+ " reg_name_matches_prefix arg1 = (
+ (let s430 = arg1 in
+ if ((case ((s40 s430)) of Some (s1) => True | _ => False )) then
+ (case s40 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s44 s430)) of Some (s1) => True | _ => False )) then
+ (case s44 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s48 s430)) of Some (s1) => True | _ => False )) then
+ (case s48 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s52 s430)) of Some (s1) => True | _ => False )) then
+ (case s52 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s56 s430)) of Some (s1) => True | _ => False )) then
+ (case s56 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s60 s430)) of Some (s1) => True | _ => False )) then
+ (case s60 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s64 s430)) of Some (s1) => True | _ => False )) then
+ (case s64 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s68 s430)) of Some (s1) => True | _ => False )) then
+ (case s68 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s72 s430)) of Some (s1) => True | _ => False )) then
+ (case s72 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s76 s430)) of Some (s1) => True | _ => False )) then
+ (case s76 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s80 s430)) of Some (s1) => True | _ => False )) then
+ (case s80 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s84 s430)) of Some (s1) => True | _ => False )) then
+ (case s84 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s88 s430)) of Some (s1) => True | _ => False )) then
+ (case s88 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s92 s430)) of Some (s1) => True | _ => False )) then
+ (case s92 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s96 s430)) of Some (s1) => True | _ => False )) then
+ (case s96 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s100 s430)) of Some (s1) => True | _ => False )) then
+ (case s100 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s104 s430)) of Some (s1) => True | _ => False )) then
+ (case s104 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s108 s430)) of Some (s1) => True | _ => False )) then
+ (case s108 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s112 s430)) of Some (s1) => True | _ => False )) then
+ (case s112 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s116 s430)) of Some (s1) => True | _ => False )) then
+ (case s116 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s120 s430)) of Some (s1) => True | _ => False )) then
+ (case s120 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s124 s430)) of Some (s1) => True | _ => False )) then
+ (case s124 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s128 s430)) of Some (s1) => True | _ => False )) then
+ (case s128 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s132 s430)) of Some (s1) => True | _ => False )) then
+ (case s132 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s136 s430)) of Some (s1) => True | _ => False )) then
+ (case s136 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s140 s430)) of Some (s1) => True | _ => False )) then
+ (case s140 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s144 s430)) of Some (s1) => True | _ => False )) then
+ (case s144 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s148 s430)) of Some (s1) => True | _ => False )) then
+ (case s148 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s152 s430)) of Some (s1) => True | _ => False )) then
+ (case s152 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s156 s430)) of Some (s1) => True | _ => False )) then
+ (case s156 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s160 s430)) of Some (s1) => True | _ => False )) then
+ (case s160 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s164 s430)) of Some (s1) => True | _ => False )) then
+ (case s164 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_forwards : mword ty3 -> M string\<close>\<close>
+
+definition creg_name_forwards :: "(3)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " creg_name_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return (''s0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return (''s1'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return (''a0'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return (''a1'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return (''a2'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return (''a3'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return (''a4'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return (''a5'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val creg_name_backwards : string -> M (mword ty3)\<close>\<close>
+
+definition creg_name_backwards :: " string \<Rightarrow>((register_value),((3)Word.word),(exception))monad " where
+ " creg_name_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''s0'')))) then return (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ else if (((p00 = (''s1'')))) then return (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ else if (((p00 = (''a0'')))) then return (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ else if (((p00 = (''a1'')))) then return (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ else if (((p00 = (''a2'')))) then return (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ else if (((p00 = (''a3'')))) then return (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ else if (((p00 = (''a4'')))) then return (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ else if (((p00 = (''a5'')))) then return (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_forwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition creg_name_forwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " creg_name_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val creg_name_backwards_matches : string -> bool\<close>\<close>
+
+definition creg_name_backwards_matches :: " string \<Rightarrow> bool " where
+ " creg_name_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''s0'')))) then True
+ else if (((p00 = (''s1'')))) then True
+ else if (((p00 = (''a0'')))) then True
+ else if (((p00 = (''a1'')))) then True
+ else if (((p00 = (''a2'')))) then True
+ else if (((p00 = (''a3'')))) then True
+ else if (((p00 = (''a4'')))) then True
+ else if (((p00 = (''a5'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_matches_prefix : string -> maybe ((mword ty3 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s196_ : string -> maybe string\<close>\<close>
+
+definition s196 :: " string \<Rightarrow>(string)option " where
+ " s196 s1970 = (
+ (let s1980 = s1970 in
+ if ((string_startswith s1980 (''a5''))) then
+ (case ((string_drop s1980 ((string_length (''a5''))))) of s1 => Some s1 )
+ else None))"
+ for s1970 :: " string "
+
+
+\<comment> \<open>\<open>val _s192_ : string -> maybe string\<close>\<close>
+
+definition s192 :: " string \<Rightarrow>(string)option " where
+ " s192 s1930 = (
+ (let s1940 = s1930 in
+ if ((string_startswith s1940 (''a4''))) then
+ (case ((string_drop s1940 ((string_length (''a4''))))) of s1 => Some s1 )
+ else None))"
+ for s1930 :: " string "
+
+
+\<comment> \<open>\<open>val _s188_ : string -> maybe string\<close>\<close>
+
+definition s188 :: " string \<Rightarrow>(string)option " where
+ " s188 s1890 = (
+ (let s1900 = s1890 in
+ if ((string_startswith s1900 (''a3''))) then
+ (case ((string_drop s1900 ((string_length (''a3''))))) of s1 => Some s1 )
+ else None))"
+ for s1890 :: " string "
+
+
+\<comment> \<open>\<open>val _s184_ : string -> maybe string\<close>\<close>
+
+definition s184 :: " string \<Rightarrow>(string)option " where
+ " s184 s1850 = (
+ (let s1860 = s1850 in
+ if ((string_startswith s1860 (''a2''))) then
+ (case ((string_drop s1860 ((string_length (''a2''))))) of s1 => Some s1 )
+ else None))"
+ for s1850 :: " string "
+
+
+\<comment> \<open>\<open>val _s180_ : string -> maybe string\<close>\<close>
+
+definition s180 :: " string \<Rightarrow>(string)option " where
+ " s180 s1810 = (
+ (let s1820 = s1810 in
+ if ((string_startswith s1820 (''a1''))) then
+ (case ((string_drop s1820 ((string_length (''a1''))))) of s1 => Some s1 )
+ else None))"
+ for s1810 :: " string "
+
+
+\<comment> \<open>\<open>val _s176_ : string -> maybe string\<close>\<close>
+
+definition s176 :: " string \<Rightarrow>(string)option " where
+ " s176 s1770 = (
+ (let s1780 = s1770 in
+ if ((string_startswith s1780 (''a0''))) then
+ (case ((string_drop s1780 ((string_length (''a0''))))) of s1 => Some s1 )
+ else None))"
+ for s1770 :: " string "
+
+
+\<comment> \<open>\<open>val _s172_ : string -> maybe string\<close>\<close>
+
+definition s172 :: " string \<Rightarrow>(string)option " where
+ " s172 s1730 = (
+ (let s1740 = s1730 in
+ if ((string_startswith s1740 (''s1''))) then
+ (case ((string_drop s1740 ((string_length (''s1''))))) of s1 => Some s1 )
+ else None))"
+ for s1730 :: " string "
+
+
+\<comment> \<open>\<open>val _s168_ : string -> maybe string\<close>\<close>
+
+definition s168 :: " string \<Rightarrow>(string)option " where
+ " s168 s1690 = (
+ (let s1700 = s1690 in
+ if ((string_startswith s1700 (''s0''))) then
+ (case ((string_drop s1700 ((string_length (''s0''))))) of s1 => Some s1 )
+ else None))"
+ for s1690 :: " string "
+
+
+definition creg_name_matches_prefix :: " string \<Rightarrow>((3)Word.word*int)option " where
+ " creg_name_matches_prefix arg1 = (
+ (let s1711 = arg1 in
+ if ((case ((s168 s1711)) of Some (s1) => True | _ => False )) then
+ (case s168 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s172 s1711)) of Some (s1) => True | _ => False )) then
+ (case s172 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s176 s1711)) of Some (s1) => True | _ => False )) then
+ (case s176 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s180 s1711)) of Some (s1) => True | _ => False )) then
+ (case s180 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s184 s1711)) of Some (s1) => True | _ => False )) then
+ (case s184 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s188 s1711)) of Some (s1) => True | _ => False )) then
+ (case s188 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s192 s1711)) of Some (s1) => True | _ => False )) then
+ (case s192 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s196 s1711)) of Some (s1) => True | _ => False )) then
+ (case s196 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val init_base_regs : unit -> M unit\<close>\<close>
+
+definition init_base_regs :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_base_regs _ = (
+ (((((((((((((((((((((((((((((write_reg x1_ref zero_reg \<then>
+ write_reg x2_ref zero_reg) \<then>
+ write_reg x3_ref zero_reg) \<then>
+ write_reg x4_ref zero_reg) \<then>
+ write_reg x5_ref zero_reg) \<then>
+ write_reg x6_ref zero_reg) \<then>
+ write_reg x7_ref zero_reg) \<then>
+ write_reg x8_ref zero_reg) \<then>
+ write_reg x9_ref zero_reg) \<then>
+ write_reg x10_ref zero_reg) \<then>
+ write_reg x11_ref zero_reg) \<then>
+ write_reg x12_ref zero_reg) \<then>
+ write_reg x13_ref zero_reg) \<then>
+ write_reg x14_ref zero_reg) \<then>
+ write_reg x15_ref zero_reg) \<then>
+ write_reg x16_ref zero_reg) \<then>
+ write_reg x17_ref zero_reg) \<then>
+ write_reg x18_ref zero_reg) \<then>
+ write_reg x19_ref zero_reg) \<then>
+ write_reg x20_ref zero_reg) \<then>
+ write_reg x21_ref zero_reg) \<then>
+ write_reg x22_ref zero_reg) \<then>
+ write_reg x23_ref zero_reg) \<then>
+ write_reg x24_ref zero_reg) \<then>
+ write_reg x25_ref zero_reg) \<then>
+ write_reg x26_ref zero_reg) \<then>
+ write_reg x27_ref zero_reg) \<then>
+ write_reg x28_ref zero_reg) \<then>
+ write_reg x29_ref zero_reg) \<then> write_reg x30_ref zero_reg) \<then> write_reg x31_ref zero_reg )"
+
+
+\<comment> \<open>\<open>
+ Retrieves the architectural PC value. This is not necessarily the value
+ found in the PC register as extensions may choose to override this function.
+ The value in the PC register is the absolute virtual address of the instruction
+ to fetch.
+ \<close>\<close>
+\<comment> \<open>\<open>val get_arch_pc : unit -> M (mword ty32)\<close>\<close>
+
+definition get_arch_pc :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_arch_pc _ = ( (read_reg PC_ref :: ( 32 Word.word) M))"
+
+
+\<comment> \<open>\<open>val get_next_pc : unit -> M (mword ty32)\<close>\<close>
+
+definition get_next_pc :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_next_pc _ = ( (read_reg nextPC_ref :: ( 32 Word.word) M))"
+
+
+\<comment> \<open>\<open>val set_next_pc : mword ty32 -> M unit\<close>\<close>
+
+definition set_next_pc :: "(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_next_pc pc = ( write_reg nextPC_ref pc )"
+ for pc :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val tick_pc : unit -> M unit\<close>\<close>
+
+definition tick_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_pc _ = (
+ (read_reg nextPC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . write_reg PC_ref w__0))"
+
+
+\<comment> \<open>\<open>val Mk_Misa : mword ty32 -> Misa\<close>\<close>
+
+definition Mk_Misa :: "(32)Word.word \<Rightarrow> Misa " where
+ " Mk_Misa v = ( (| Misa_Misa_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_bits : Misa -> mword ty32\<close>\<close>
+
+definition get_Misa_bits :: " Misa \<Rightarrow>(32)Word.word " where
+ " get_Misa_bits v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Misa_bits :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_bits : Misa -> mword ty32 -> Misa\<close>\<close>
+
+definition update_Misa_bits :: " Misa \<Rightarrow>(32)Word.word \<Rightarrow> Misa " where
+ " update_Misa_bits v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_bits : SV48_PTE -> mword ty64 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_bits : SV48_PTE -> mword ty64\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_bits : register_ref regstate register_value SV48_PTE -> mword ty64 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_MXL : Misa -> mword ty2\<close>\<close>
+
+definition get_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word " where
+ " get_Misa_MXL v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 31 :: int)::ii) (( 30 :: int)::ii) :: 2 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Misa_MXL :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_MXL r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 31 :: int)::ii) (( 30 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_MXL : Misa -> mword ty2 -> Misa\<close>\<close>
+
+definition update_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa " where
+ " update_Misa_MXL v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 31 :: int)::ii) (( 30 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_Z : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Z :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Z v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Z :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Z r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 25 :: int)::ii) (( 25 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Z : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Z :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Z v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_Y : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Y :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Y v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Y :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Y r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 24 :: int)::ii) (( 24 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Y : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Y :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Y v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_X : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_X :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_X v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_X :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_X : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_X v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_X : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_W : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_W :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_W v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_W :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_W : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_W v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_W : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_V : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_V :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_V v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_V :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_V r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_V : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_V v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_V : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_U : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_U :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_U v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_U :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_U r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_U : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_U v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_U : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_T : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_T :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_T v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_T :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_T r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_T : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_T :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_T v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_S : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_S :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_S v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_S :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_S r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_S : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_S :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_S v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_R : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_R :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_R v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_R :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_R : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_R v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_R : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_Q : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Q :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Q v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Q :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Q r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 16 :: int)::ii) (( 16 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Q : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Q :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Q v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_P : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_P :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_P v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_P :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_P r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_P : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_P :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_P v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_O : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_O :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_O v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_O :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_O r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 14 :: int)::ii) (( 14 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_O : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_O :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_O v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_N : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_N :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_N v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_N :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_N r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_N : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_N :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_N v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_M : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_M :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_M v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_M :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_M r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_M : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_M :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_M v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_L : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_L :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_L v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_L :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_L r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_L : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_L :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_L v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_L : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_K : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_K :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_K v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_K :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_K r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_K : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_K :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_K v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_J : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_J :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_J v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_J :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_J r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_J : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_J :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_J v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_I : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_I :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_I v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_I :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_I r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_I : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_I :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_I v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_H : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_H :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_H v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_H :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_H r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_H : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_H :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_H v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_G : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_G :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_G v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_G :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_G r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_G : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_G v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_G : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_F : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_F :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_F v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_F :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_F r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_F : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_F :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_F v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_E : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_E :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_E v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_E :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_E r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_E : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_E :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_E v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_D : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_D :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_D v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_D :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_D r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_D : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_D v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_D : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_C : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_C :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_C v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_C :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_C r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_C : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_C :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_C v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_B : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_B :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_B v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_B :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_B r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_B : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_B :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_B v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_A : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_A :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_A v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_A :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_A : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_A v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_A : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_misa : Misa -> mword ty32 -> M Misa\<close>\<close>
+
+definition legalize_misa :: " Misa \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Misa),(exception))monad " where
+ " legalize_misa (m :: Misa) (v :: xlenbits) = (
+ if ((sys_enable_writable_misa () )) then
+ (let v = (Mk_Misa v) in
+ and_boolM
+ (return (((((get_Misa_C v :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))))
+ ((read_reg nextPC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ return (((((bit_to_bool ((access_vec_dec w__0 (( 1 :: int)::ii))))) = True))))) \<bind> (\<lambda> (w__1 :: bool) .
+ return (if w__1 then m
+ else update_Misa_C m ((get_Misa_C v :: 1 Word.word)))))
+ else return m )"
+ for m :: " Misa "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val haveAtomics : unit -> M bool\<close>\<close>
+
+definition haveAtomics :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveAtomics _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_A w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveRVC : unit -> M bool\<close>\<close>
+
+definition haveRVC :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveRVC _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveMulDiv : unit -> M bool\<close>\<close>
+
+definition haveMulDiv :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveMulDiv _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_M w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveSupMode : unit -> M bool\<close>\<close>
+
+definition haveSupMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveSupMode _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_S w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveUsrMode : unit -> M bool\<close>\<close>
+
+definition haveUsrMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveUsrMode _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_U w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveNExt : unit -> M bool\<close>\<close>
+
+definition haveNExt :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveNExt _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_N w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val Mk_Mstatus : mword ty32 -> Mstatus\<close>\<close>
+
+definition Mk_Mstatus :: "(32)Word.word \<Rightarrow> Mstatus " where
+ " Mk_Mstatus v = (
+ (| Mstatus_Mstatus_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_bits : Mstatus -> mword ty32\<close>\<close>
+
+definition get_Mstatus_bits :: " Mstatus \<Rightarrow>(32)Word.word " where
+ " get_Mstatus_bits v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Mstatus_bits :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_bits : Mstatus -> mword ty32 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_bits :: " Mstatus \<Rightarrow>(32)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_bits v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SD : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SD v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SD :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SD r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SD v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SD : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_TSR : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TSR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TSR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TSR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TSR v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_TW : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TW v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TW :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TW v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_TVM : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TVM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TVM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TVM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TVM v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_MXR : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MXR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MXR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MXR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MXR v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_MXR : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_SUM : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SUM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SUM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SUM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SUM v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SUM : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPRV : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MPRV v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPRV :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPRV r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPRV v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_XS : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_XS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_XS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_XS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_XS v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_XS : Sstatus -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_FS : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_FS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_FS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_FS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_FS v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_FS : Sstatus -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPP : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_MPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 12 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPP v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SPP : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SPP v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SPP : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SPIE : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_UPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_UPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_UPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_UPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_UPIE : Ustatus -> mword ty1 -> Ustatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Ustatus_UPIE : Ustatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Ustatus_UPIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SIE : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_UIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_UIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_UIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_UIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_UIE : Ustatus -> mword ty1 -> Ustatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Ustatus_UIE : Ustatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Ustatus_UIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val effectivePrivilege : Mstatus -> Privilege -> M Privilege\<close>\<close>
+
+definition effectivePrivilege :: " Mstatus \<Rightarrow> Privilege \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " effectivePrivilege (m :: Mstatus) (priv :: Privilege) = (
+ if (((((get_Mstatus_MPRV m :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__0 :: 2 Word.word)))
+ else read_reg cur_privilege_ref )"
+ for m :: " Mstatus "
+ and priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val get_mstatus_SXL : Mstatus -> mword ty2\<close>\<close>
+
+definition get_mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_mstatus_SXL m = ( (arch_to_bits RV32 :: 2 Word.word))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val set_mstatus_SXL : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition set_mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " set_mstatus_SXL (m :: Mstatus) (a :: arch_xlen) = ( m )"
+ for m :: " Mstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val get_mstatus_UXL : Mstatus -> mword ty2\<close>\<close>
+
+definition get_mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_mstatus_UXL m = ( (arch_to_bits RV32 :: 2 Word.word))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val set_mstatus_UXL : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition set_mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " set_mstatus_UXL (m :: Mstatus) (a :: arch_xlen) = ( m )"
+ for m :: " Mstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mstatus : Mstatus -> mword ty32 -> M Mstatus\<close>\<close>
+
+definition legalize_mstatus :: " Mstatus \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_mstatus (o1 :: Mstatus) (v :: xlenbits) = (
+ (let (m :: Mstatus) = (Mk_Mstatus v) in
+ (let m = (update_Mstatus_XS m ((extStatus_to_bits Off :: 2 Word.word))) in
+ or_boolM
+ (extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: ExtStatus) .
+ return (((((extStatus_to_bits w__0 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))
+ (extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)) \<bind> (\<lambda> (w__1 :: ExtStatus) .
+ return (((((extStatus_to_bits w__1 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))))) \<bind> (\<lambda> (w__2 :: bool) .
+ (let m = (update_Mstatus_SD m ((bool_to_bits w__2 :: 1 Word.word))) in
+ (let m = (set_mstatus_SXL m ((get_mstatus_SXL o1 :: 2 Word.word))) in
+ (let m = (set_mstatus_UXL m ((get_mstatus_UXL o1 :: 2 Word.word))) in
+ (let m = (update_Mstatus_UPIE m ((bool_to_bits False :: 1 Word.word))) in
+ (let m = (update_Mstatus_UIE m ((bool_to_bits False :: 1 Word.word))) in
+ return m)))))))))"
+ for o1 :: " Mstatus "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val cur_Architecture : unit -> M Architecture\<close>\<close>
+
+definition cur_Architecture :: " unit \<Rightarrow>((register_value),(Architecture),(exception))monad " where
+ " cur_Architecture _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ Machine =>
+ read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) . return ((get_Misa_MXL w__1 :: 2 Word.word)))
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . return ((get_mstatus_SXL w__2 :: 2 Word.word)))
+ | User =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) . return ((get_mstatus_UXL w__3 :: 2 Word.word)))
+ ) \<bind> (\<lambda> (a :: arch_xlen) .
+ (case ((architecture a)) of
+ Some (a) => return a
+ | None => internal_error (''Invalid current architecture'')
+ ))))"
+
+
+\<comment> \<open>\<open>val in32BitMode : unit -> M bool\<close>\<close>
+
+definition in32BitMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " in32BitMode _ = ( cur_Architecture () \<bind> (\<lambda> (w__0 :: Architecture) . return (((w__0 = RV32)))))"
+
+
+\<comment> \<open>\<open>val Mk_Minterrupts : mword ty32 -> Minterrupts\<close>\<close>
+
+definition Mk_Minterrupts :: "(32)Word.word \<Rightarrow> Minterrupts " where
+ " Mk_Minterrupts v = (
+ (| Minterrupts_Minterrupts_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_bits : Minterrupts -> mword ty32\<close>\<close>
+
+definition get_Minterrupts_bits :: " Minterrupts \<Rightarrow>(32)Word.word " where
+ " get_Minterrupts_bits v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Minterrupts_bits :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_bits : Minterrupts -> mword ty32 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_bits :: " Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_bits v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_MEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_SEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_SEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_SEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_SEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_SEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_UEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_UEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_UEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_UEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_UEI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_UEI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_UEI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_MTI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MTI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MTI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_STI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_STI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_STI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_STI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_STI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_STI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_UTI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_UTI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_UTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_UTI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_UTI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_UTI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_UTI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_MSI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MSI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MSI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_SSI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_SSI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_SSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_SSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_SSI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_USI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_USI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_USI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_USI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_USI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_USI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_USI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_mip : Minterrupts -> mword ty32 -> M Minterrupts\<close>\<close>
+
+definition legalize_mip :: " Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_mip (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let v = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))) in
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v :: 1 Word.word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v :: 1 Word.word))))
+ else m)))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mie : Minterrupts -> mword ty32 -> M Minterrupts\<close>\<close>
+
+definition legalize_mie :: " Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_mie (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let v = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))) in
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v :: 1 Word.word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v :: 1 Word.word))))
+ else m))))))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mideleg : Minterrupts -> mword ty32 -> Minterrupts\<close>\<close>
+
+definition legalize_mideleg :: " Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Minterrupts " where
+ " legalize_mideleg (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let m = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_MEI m ((bool_to_bits False :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MTI m ((bool_to_bits False :: 1 Word.word))) in
+ update_Minterrupts_MSI m ((bool_to_bits False :: 1 Word.word))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Medeleg : mword ty32 -> Medeleg\<close>\<close>
+
+definition Mk_Medeleg :: "(32)Word.word \<Rightarrow> Medeleg " where
+ " Mk_Medeleg v = (
+ (| Medeleg_Medeleg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_bits : Medeleg -> mword ty32\<close>\<close>
+
+definition get_Medeleg_bits :: " Medeleg \<Rightarrow>(32)Word.word " where
+ " get_Medeleg_bits v = ( (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Medeleg_bits :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_bits : Medeleg -> mword ty32 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_bits :: " Medeleg \<Rightarrow>(32)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_bits v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_MEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_MEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_MEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_MEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_MEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_SEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_UEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_UEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_UEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_UEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_UEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Breakpoint : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Breakpoint v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Breakpoint :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Breakpoint r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Breakpoint v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Illegal_Instr v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Illegal_Instr :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Illegal_Instr r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Illegal_Instr v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_medeleg : Medeleg -> mword ty32 -> Medeleg\<close>\<close>
+
+definition legalize_medeleg :: " Medeleg \<Rightarrow>(32)Word.word \<Rightarrow> Medeleg " where
+ " legalize_medeleg (o1 :: Medeleg) (v :: xlenbits) = (
+ (let m = (Mk_Medeleg v) in
+ update_Medeleg_MEnvCall m ((bool_to_bits False :: 1 Word.word))))"
+ for o1 :: " Medeleg "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Mtvec : mword ty32 -> Mtvec\<close>\<close>
+
+definition Mk_Mtvec :: "(32)Word.word \<Rightarrow> Mtvec " where
+ " Mk_Mtvec v = ( (| Mtvec_Mtvec_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_bits : Mtvec -> mword ty32\<close>\<close>
+
+definition get_Mtvec_bits :: " Mtvec \<Rightarrow>(32)Word.word " where
+ " get_Mtvec_bits v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Mtvec_bits :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_bits : Mtvec -> mword ty32 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_bits :: " Mtvec \<Rightarrow>(32)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_bits v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_Base : Mtvec -> mword ty30\<close>\<close>
+
+definition get_Mtvec_Base :: " Mtvec \<Rightarrow>(30)Word.word " where
+ " get_Mtvec_Base v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 31 :: int)::ii) (( 2 :: int)::ii) :: 30 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty30 -> M unit\<close>\<close>
+
+definition set_Mtvec_Base :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(30)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_Base r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 31 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 29 :: int)::ii) (( 0 :: int)::ii) :: 30 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(30)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_Base : Mtvec -> mword ty30 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_Base :: " Mtvec \<Rightarrow>(30)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_Base v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 31 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 29 :: int)::ii) (( 0 :: int)::ii) :: 30 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(30)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_Mode : Mtvec -> mword ty2\<close>\<close>
+
+definition get_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word " where
+ " get_Mtvec_Mode v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mtvec_Mode :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 1 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_Mode v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_Mode : Satp32 -> mword ty1 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_Mode : Satp32 -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_Mode : register_ref regstate register_value Satp32 -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_tvec : Mtvec -> mword ty32 -> Mtvec\<close>\<close>
+
+definition legalize_tvec :: " Mtvec \<Rightarrow>(32)Word.word \<Rightarrow> Mtvec " where
+ " legalize_tvec (o1 :: Mtvec) (v :: xlenbits) = (
+ (let v = (Mk_Mtvec v) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v :: 2 Word.word)))) of
+ TV_Direct => v
+ | TV_Vector => v
+ | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 :: 2 Word.word))
+ )))"
+ for o1 :: " Mtvec "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Mcause : mword ty32 -> Mcause\<close>\<close>
+
+definition Mk_Mcause :: "(32)Word.word \<Rightarrow> Mcause " where
+ " Mk_Mcause v = ( (| Mcause_Mcause_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_bits : Mcause -> mword ty32\<close>\<close>
+
+definition get_Mcause_bits :: " Mcause \<Rightarrow>(32)Word.word " where
+ " get_Mcause_bits v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Mcause_bits :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_bits : Mcause -> mword ty32 -> Mcause\<close>\<close>
+
+definition update_Mcause_bits :: " Mcause \<Rightarrow>(32)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_bits v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_IsInterrupt : Mcause -> mword ty1\<close>\<close>
+
+definition get_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word " where
+ " get_Mcause_IsInterrupt v = (
+ (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mcause_IsInterrupt :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_IsInterrupt r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause\<close>\<close>
+
+definition update_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_IsInterrupt v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_Cause : Mcause -> mword ty31\<close>\<close>
+
+definition get_Mcause_Cause :: " Mcause \<Rightarrow>(31)Word.word " where
+ " get_Mcause_Cause v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty31 -> M unit\<close>\<close>
+
+definition set_Mcause_Cause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_Cause r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 30 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(31)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_Cause : Mcause -> mword ty31 -> Mcause\<close>\<close>
+
+definition update_Mcause_Cause :: " Mcause \<Rightarrow>(31)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_Cause v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 30 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(31)Word.word "
+
+
+\<comment> \<open>\<open>val tvec_addr : Mtvec -> Mcause -> maybe (mword ty32)\<close>\<close>
+
+definition tvec_addr :: " Mtvec \<Rightarrow> Mcause \<Rightarrow>((32)Word.word)option " where
+ " tvec_addr (m :: Mtvec) (c :: Mcause) = (
+ (let (base :: xlenbits) =
+ ((concat_vec ((get_Mtvec_Base m :: 30 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 32 Word.word)) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m :: 2 Word.word)))) of
+ TV_Direct => Some base
+ | TV_Vector =>
+ if (((((get_Mcause_IsInterrupt c :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some ((add_vec base
+ ((shiftl ((EXTZ (( 32 :: int)::ii) ((get_Mcause_Cause c :: 31 Word.word)) :: 32 Word.word))
+ (( 2 :: int)::ii)
+ :: 32 Word.word))
+ :: 32 Word.word))
+ else Some base
+ | TV_Reserved => None
+ )))"
+ for m :: " Mtvec "
+ and c :: " Mcause "
+
+
+\<comment> \<open>\<open>val legalize_xepc : mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition legalize_xepc :: "(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " legalize_xepc v = (
+ or_boolM (return ((sys_enable_writable_misa () )))
+ (read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) \<bind> (\<lambda> (w__1 ::
+ bool) .
+ return (if w__1 then (update_vec_dec v (( 0 :: int)::ii) B0 :: 32 Word.word)
+ else
+ (and_vec v ((EXTS (( 32 :: int)::ii) (vec_of_bits [B1,B0,B0] :: 3 Word.word) :: 32 Word.word))
+ :: 32 Word.word))))"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pc_alignment_mask : unit -> M (mword ty32)\<close>\<close>
+
+definition pc_alignment_mask :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " pc_alignment_mask _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return ((not_vec
+ ((EXTZ (( 32 :: int)::ii)
+ (if (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ (vec_of_bits [B0,B0] :: 2 Word.word)
+ else (vec_of_bits [B1,B0] :: 2 Word.word))
+ :: 32 Word.word))
+ :: 32 Word.word))))"
+
+
+\<comment> \<open>\<open>val Mk_Counteren : mword ty32 -> Counteren\<close>\<close>
+
+definition Mk_Counteren :: "(32)Word.word \<Rightarrow> Counteren " where
+ " Mk_Counteren v = (
+ (| Counteren_Counteren_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_bits : Counteren -> mword ty32\<close>\<close>
+
+definition get_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word " where
+ " get_Counteren_bits v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Counteren_bits :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren\<close>\<close>
+
+definition update_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_bits v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_HPM : Counteren -> mword ty29\<close>\<close>
+
+definition get_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word " where
+ " get_Counteren_HPM v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii) :: 29 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit\<close>\<close>
+
+definition set_Counteren_HPM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(29)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_HPM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren\<close>\<close>
+
+definition update_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_HPM v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_IR : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_IR v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_IR :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_IR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_IR v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_TM : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_TM v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_TM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_TM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_TM v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_CY : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_CY v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_CY :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_CY r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_CY v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mcounteren : Counteren -> mword ty32 -> Counteren\<close>\<close>
+
+definition legalize_mcounteren :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren " where
+ " legalize_mcounteren (c :: Counteren) (v :: xlenbits) = (
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in
+ (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))"
+ for c :: " Counteren "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_scounteren : Counteren -> mword ty32 -> Counteren\<close>\<close>
+
+definition legalize_scounteren :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren " where
+ " legalize_scounteren (c :: Counteren) (v :: xlenbits) = (
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in
+ (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))"
+ for c :: " Counteren "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val retire_instruction : unit -> M unit\<close>\<close>
+
+definition retire_instruction :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " retire_instruction _ = (
+ read_reg minstret_written_ref \<bind> (\<lambda> (w__0 :: bool) .
+ if (((w__0 = True))) then write_reg minstret_written_ref False
+ else
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg minstret_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)))))"
+
+
+\<comment> \<open>\<open>val Mk_Sstatus : mword ty32 -> Sstatus\<close>\<close>
+
+definition Mk_Sstatus :: "(32)Word.word \<Rightarrow> Sstatus " where
+ " Mk_Sstatus v = (
+ (| Sstatus_Sstatus_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_bits : Sstatus -> mword ty32\<close>\<close>
+
+definition get_Sstatus_bits :: " Sstatus \<Rightarrow>(32)Word.word " where
+ " get_Sstatus_bits v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Sstatus_bits :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_bits : Sstatus -> mword ty32 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_bits :: " Sstatus \<Rightarrow>(32)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_bits v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(32)Word.word "
+
+
+definition get_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SD v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SD :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SD r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SD v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_MXR v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_MXR :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_MXR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_MXR v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SUM v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SUM :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SUM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SUM v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_Sstatus_XS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_XS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_XS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_XS v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(2)Word.word "
+
+
+definition get_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_Sstatus_FS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_FS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_FS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_FS v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(2)Word.word "
+
+
+definition get_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SPP v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SPP :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SPP v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SPIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_UPIE : Sstatus -> mword ty1\<close>\<close>
+
+definition get_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_UPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sstatus_UPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_UPIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_UIE : Sstatus -> mword ty1\<close>\<close>
+
+definition get_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_UIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sstatus_UIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_UIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val get_sstatus_UXL : Sstatus -> mword ty2\<close>\<close>
+
+definition get_sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_sstatus_UXL s = (
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s :: 32 Word.word))) in
+ (get_mstatus_UXL m :: 2 Word.word)))"
+ for s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val set_sstatus_UXL : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+definition set_sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " set_sstatus_UXL (s :: Sstatus) (a :: arch_xlen) = (
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s :: 32 Word.word))) in
+ (let m = (set_mstatus_UXL m a) in
+ Mk_Sstatus ((get_Mstatus_bits m :: 32 Word.word)))))"
+ for s :: " Sstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val lower_mstatus : Mstatus -> Sstatus\<close>\<close>
+
+definition lower_mstatus :: " Mstatus \<Rightarrow> Sstatus " where
+ " lower_mstatus m = (
+ (let s = (Mk_Sstatus ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let s = (update_Sstatus_SD s ((get_Mstatus_SD m :: 1 Word.word))) in
+ (let s = (set_sstatus_UXL s ((get_mstatus_UXL m :: 2 Word.word))) in
+ (let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m :: 1 Word.word))) in
+ (let s = (update_Sstatus_XS s ((get_Mstatus_XS m :: 2 Word.word))) in
+ (let s = (update_Sstatus_FS s ((get_Mstatus_FS m :: 2 Word.word))) in
+ (let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m :: 1 Word.word))) in
+ (let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m :: 1 Word.word))) in
+ update_Sstatus_UIE s ((get_Mstatus_UIE m :: 1 Word.word))))))))))))))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val lift_sstatus : Mstatus -> Sstatus -> M Mstatus\<close>\<close>
+
+definition lift_sstatus :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " lift_sstatus (m :: Mstatus) (s :: Sstatus) = (
+ (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s :: 1 Word.word))) in
+ (let m = (update_Mstatus_XS m ((get_Sstatus_XS s :: 2 Word.word))) in
+ (let m = (update_Mstatus_FS m ((get_Sstatus_FS s :: 2 Word.word))) in
+ or_boolM
+ (extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: ExtStatus) .
+ return (((((extStatus_to_bits w__0 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))
+ (extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)) \<bind> (\<lambda> (w__1 :: ExtStatus) .
+ return (((((extStatus_to_bits w__1 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))))) \<bind> (\<lambda> (w__2 :: bool) .
+ (let m = (update_Mstatus_SD m ((bool_to_bits w__2 :: 1 Word.word))) in
+ (let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word))) in
+ return m))))))))))))"
+ for m :: " Mstatus "
+ and s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val legalize_sstatus : Mstatus -> mword ty32 -> M Mstatus\<close>\<close>
+
+definition legalize_sstatus :: " Mstatus \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m ((Mk_Sstatus v)))"
+ for m :: " Mstatus "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Sedeleg : mword ty32 -> Sedeleg\<close>\<close>
+
+definition Mk_Sedeleg :: "(32)Word.word \<Rightarrow> Sedeleg " where
+ " Mk_Sedeleg v = (
+ (| Sedeleg_Sedeleg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sedeleg_bits : Sedeleg -> mword ty32\<close>\<close>
+
+definition get_Sedeleg_bits :: " Sedeleg \<Rightarrow>(32)Word.word " where
+ " get_Sedeleg_bits v = ( (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Sedeleg "
+
+
+\<comment> \<open>\<open>val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Sedeleg_bits :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_bits : Sedeleg -> mword ty32 -> Sedeleg\<close>\<close>
+
+definition update_Sedeleg_bits :: " Sedeleg \<Rightarrow>(32)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_bits v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(32)Word.word "
+
+
+definition get_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_UEnvCall v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_UEnvCall :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_UEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_UEnvCall v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_SAMO_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_SAMO_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_SAMO_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_SAMO_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_SAMO_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_SAMO_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Load_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Load_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Load_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Load_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Load_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Load_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Load_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Load_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Breakpoint v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Breakpoint :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Breakpoint r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Breakpoint v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Illegal_Instr v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Illegal_Instr :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Illegal_Instr r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Illegal_Instr v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Fetch_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Fetch_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Fetch_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Fetch_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Fetch_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Fetch_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_sedeleg : Sedeleg -> mword ty32 -> Sedeleg\<close>\<close>
+
+definition legalize_sedeleg :: " Sedeleg \<Rightarrow>(32)Word.word \<Rightarrow> Sedeleg " where
+ " legalize_sedeleg (s :: Sedeleg) (v :: xlenbits) = (
+ Mk_Sedeleg ((EXTZ (( 32 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word)) :: 32 Word.word)))"
+ for s :: " Sedeleg "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Sinterrupts : mword ty32 -> Sinterrupts\<close>\<close>
+
+definition Mk_Sinterrupts :: "(32)Word.word \<Rightarrow> Sinterrupts " where
+ " Mk_Sinterrupts v = (
+ (| Sinterrupts_Sinterrupts_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_bits : Sinterrupts -> mword ty32\<close>\<close>
+
+definition get_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(32)Word.word " where
+ " get_Sinterrupts_bits v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_bits :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_bits : Sinterrupts -> mword ty32 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_bits v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(32)Word.word "
+
+
+definition get_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_SEI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_SEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_SEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_SEI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_UEI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_UEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_UEI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_STI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_STI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_STI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_STI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_UTI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_UTI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_UTI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_SSI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_SSI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_SSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_SSI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_USI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_USI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_USI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_USI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts\<close>\<close>
+
+definition lower_mip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where
+ " lower_mip (m :: Minterrupts) (d :: Minterrupts) = (
+ (let (s :: Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word)))))))))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts\<close>\<close>
+
+definition lower_mie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where
+ " lower_mie (m :: Minterrupts) (d :: Minterrupts) = (
+ (let (s :: Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word)))))))))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts\<close>\<close>
+
+definition lift_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " lift_sip (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = (
+ (let (m :: Minterrupts) = o1 in
+ (let m =
+ (update_Minterrupts_SSI m
+ ((and_vec ((get_Sinterrupts_SSI s :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ haveNExt () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m =
+ (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word))
+ else m) in
+ if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word))
+ else m)
+ else m)))))"
+ for o1 :: " Minterrupts "
+ and d :: " Minterrupts "
+ and s :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_sip : Minterrupts -> Minterrupts -> mword ty32 -> M Minterrupts\<close>\<close>
+
+definition legalize_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
+ lift_sip m d ((Mk_Sinterrupts v)))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts\<close>\<close>
+
+definition lift_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " lift_sie (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = (
+ (let (m :: Minterrupts) = o1 in
+ (let m =
+ (if (((((get_Minterrupts_SEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_SEI m ((get_Sinterrupts_SEI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_STI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_STI m ((get_Sinterrupts_STI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_SSI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_SSI m ((get_Sinterrupts_SSI s :: 1 Word.word))
+ else m) in
+ haveNExt () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m =
+ (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UTI m ((get_Sinterrupts_UTI s :: 1 Word.word))
+ else m) in
+ if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word))
+ else m))
+ else m)))))))"
+ for o1 :: " Minterrupts "
+ and d :: " Minterrupts "
+ and s :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_sie : Minterrupts -> Minterrupts -> mword ty32 -> M Minterrupts\<close>\<close>
+
+definition legalize_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
+ lift_sie m d ((Mk_Sinterrupts v)))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Satp64 : mword ty64 -> Satp64\<close>\<close>
+
+definition Mk_Satp64 :: "(64)Word.word \<Rightarrow> Satp64 " where
+ " Mk_Satp64 v = ( (| Satp64_Satp64_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_bits : Satp64 -> mword ty64\<close>\<close>
+
+definition get_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word " where
+ " get_Satp64_bits v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Satp64_bits :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64\<close>\<close>
+
+definition update_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_bits v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_Mode : Satp64 -> mword ty4\<close>\<close>
+
+definition get_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word " where
+ " get_Satp64_Mode v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit\<close>\<close>
+
+definition set_Satp64_Mode :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 60 :: int)::ii)
+ ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64\<close>\<close>
+
+definition update_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_Mode v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii)
+ ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_Asid : Satp64 -> mword ty16\<close>\<close>
+
+definition get_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word " where
+ " get_Satp64_Asid v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit\<close>\<close>
+
+definition set_Satp64_Asid :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_Asid r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 59 :: int)::ii) (( 44 :: int)::ii)
+ ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64\<close>\<close>
+
+definition update_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_Asid v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii)
+ ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_Asid : Satp32 -> mword ty9 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_Asid : Satp32 -> mword ty9\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_Asid : register_ref regstate register_value Satp32 -> mword ty9 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp64_PPN : Satp64 -> mword ty44\<close>\<close>
+
+definition get_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word " where
+ " get_Satp64_PPN v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit\<close>\<close>
+
+definition set_Satp64_PPN :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_PPN r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 43 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64\<close>\<close>
+
+definition update_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_PPN v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_PPN : Satp32 -> mword ty22 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_PPN : Satp32 -> mword ty22\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_PPN : register_ref regstate register_value Satp32 -> mword ty22 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_satp64 : Architecture -> mword ty64 -> mword ty64 -> mword ty64\<close>\<close>
+
+definition legalize_satp64 :: " Architecture \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word " where
+ " legalize_satp64 (a :: Architecture) (o1 :: 64 bits) (v :: 64 bits) = (
+ (let s = (Mk_Satp64 v) in
+ (case ((satp64Mode_of_bits a ((get_Satp64_Mode s :: 4 Word.word)))) of
+ None => o1
+ | Some (Sv32) => o1
+ | Some (_) => (get_Satp64_bits s :: 64 Word.word)
+ )))"
+ for a :: " Architecture "
+ and o1 :: "(64)Word.word "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Satp32 : mword ty32 -> Satp32\<close>\<close>
+
+definition Mk_Satp32 :: "(32)Word.word \<Rightarrow> Satp32 " where
+ " Mk_Satp32 v = ( (| Satp32_Satp32_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp32_bits : Satp32 -> mword ty32\<close>\<close>
+
+definition get_Satp32_bits :: " Satp32 \<Rightarrow>(32)Word.word " where
+ " get_Satp32_bits v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Satp32 "
+
+
+\<comment> \<open>\<open>val _set_Satp32_bits : register_ref regstate register_value Satp32 -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Satp32_bits :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_bits : Satp32 -> mword ty32 -> Satp32\<close>\<close>
+
+definition update_Satp32_bits :: " Satp32 \<Rightarrow>(32)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_bits v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(32)Word.word "
+
+
+definition get_Satp32_Mode :: " Satp32 \<Rightarrow>(1)Word.word " where
+ " get_Satp32_Mode v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_Mode :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Satp32_Mode :: " Satp32 \<Rightarrow>(1)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_Mode v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(1)Word.word "
+
+
+definition get_Satp32_Asid :: " Satp32 \<Rightarrow>(9)Word.word " where
+ " get_Satp32_Asid v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 30 :: int)::ii) (( 22 :: int)::ii) :: 9 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_Asid :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(9)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_Asid r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 30 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(9)Word.word "
+
+
+definition update_Satp32_Asid :: " Satp32 \<Rightarrow>(9)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_Asid v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 30 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(9)Word.word "
+
+
+definition get_Satp32_PPN :: " Satp32 \<Rightarrow>(22)Word.word " where
+ " get_Satp32_PPN v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_PPN :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_PPN r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 21 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(22)Word.word "
+
+
+definition update_Satp32_PPN :: " Satp32 \<Rightarrow>(22)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_PPN v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 21 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_satp32 : Architecture -> mword ty32 -> mword ty32 -> mword ty32\<close>\<close>
+
+definition legalize_satp32 :: " Architecture \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word " where
+ " legalize_satp32 (a :: Architecture) (o1 :: 32 bits) (v :: 32 bits) = ( v )"
+ for a :: " Architecture "
+ and o1 :: "(32)Word.word "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val PmpAddrMatchType_of_num : integer -> PmpAddrMatchType\<close>\<close>
+
+definition PmpAddrMatchType_of_num :: " int \<Rightarrow> PmpAddrMatchType " where
+ " PmpAddrMatchType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then OFF
+ else if (((p00 = (( 1 :: int)::ii)))) then TOR
+ else if (((p00 = (( 2 :: int)::ii)))) then NA4
+ else NAPOT))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_PmpAddrMatchType : PmpAddrMatchType -> integer\<close>\<close>
+
+fun num_of_PmpAddrMatchType :: " PmpAddrMatchType \<Rightarrow> int " where
+ " num_of_PmpAddrMatchType OFF = ( (( 0 :: int)::ii))"
+|" num_of_PmpAddrMatchType TOR = ( (( 1 :: int)::ii))"
+|" num_of_PmpAddrMatchType NA4 = ( (( 2 :: int)::ii))"
+|" num_of_PmpAddrMatchType NAPOT = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpAddrMatchType_of_bits : mword ty2 -> M PmpAddrMatchType\<close>\<close>
+
+definition pmpAddrMatchType_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(PmpAddrMatchType),(exception))monad " where
+ " pmpAddrMatchType_of_bits bs = (
+ (let b__0 = bs in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return OFF
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return TOR
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return NA4
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return NAPOT
+ else assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3'') \<then> exit0 () ))"
+ for bs :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val pmpAddrMatchType_to_bits : PmpAddrMatchType -> mword ty2\<close>\<close>
+
+fun pmpAddrMatchType_to_bits :: " PmpAddrMatchType \<Rightarrow>(2)Word.word " where
+ " pmpAddrMatchType_to_bits OFF = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits TOR = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits NA4 = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits NAPOT = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val Mk_Pmpcfg_ent : mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition Mk_Pmpcfg_ent :: "(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " Mk_Pmpcfg_ent v = (
+ (| Pmpcfg_ent_Pmpcfg_ent_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) |) )"
+ for v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8\<close>\<close>
+
+definition get_Pmpcfg_ent_bits :: " Pmpcfg_ent \<Rightarrow>(8)Word.word " where
+ " get_Pmpcfg_ent_bits v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_bits : register_ref regstate register_value Pmpcfg_ent -> mword ty8 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_bits :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_bits :: " Pmpcfg_ent \<Rightarrow>(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_bits v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(8)Word.word "
+
+
+definition get_Pmpcfg_ent_L :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_L v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+definition set_Pmpcfg_ent_L :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_L r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Pmpcfg_ent_L :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_L v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2\<close>\<close>
+
+definition get_Pmpcfg_ent_A :: " Pmpcfg_ent \<Rightarrow>(2)Word.word " where
+ " get_Pmpcfg_ent_A v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_A : register_ref regstate register_value Pmpcfg_ent -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_A :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 4 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_A :: " Pmpcfg_ent \<Rightarrow>(2)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_A v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_X :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_X v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_X : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_X :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_X :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_X v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_W :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_W v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_W : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_W :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_W :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_W v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_R :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_R v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_R : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_R :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_R :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_R v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val pmpReadCfgReg : integer -> M (mword ty32)\<close>\<close>
+
+definition pmpReadCfgReg :: " int \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " pmpReadCfgReg n = (
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__0 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__1 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__2 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__3 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))))))
+ else if (((p00 = (( 1 :: int)::ii)))) then
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__4 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__5 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__6 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__7 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))))))
+ else if (((p00 = (( 2 :: int)::ii)))) then
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__8 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__9 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__10 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__11 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))))))
+ else if (((p00 = (( 3 :: int)::ii)))) then
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__12 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__13 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__14 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__15 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))))))
+ else assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8'') \<then> exit0 () ))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val pmpWriteCfg : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition pmpWriteCfg :: " Pmpcfg_ent \<Rightarrow>(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " pmpWriteCfg (cfg :: Pmpcfg_ent) (v :: 8 bits) = (
+ if (((((get_Pmpcfg_ent_L cfg :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then cfg
+ else Mk_Pmpcfg_ent v )"
+ for cfg :: " Pmpcfg_ent "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val pmpWriteCfgReg : integer -> mword ty32 -> M unit\<close>\<close>
+
+definition pmpWriteCfgReg :: " int \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " pmpWriteCfgReg n v = (
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (write_reg pmp0cfg_ref ((pmpWriteCfg w__0 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp1cfg_ref) \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ (write_reg pmp1cfg_ref ((pmpWriteCfg w__1 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp2cfg_ref) \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ (write_reg pmp2cfg_ref ((pmpWriteCfg w__2 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp3cfg_ref) \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ write_reg pmp3cfg_ref ((pmpWriteCfg w__3 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))
+ else if (((p00 = (( 1 :: int)::ii)))) then
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ (write_reg pmp4cfg_ref ((pmpWriteCfg w__4 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp5cfg_ref) \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ (write_reg pmp5cfg_ref ((pmpWriteCfg w__5 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp6cfg_ref) \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ (write_reg pmp6cfg_ref ((pmpWriteCfg w__6 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp7cfg_ref) \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ write_reg pmp7cfg_ref ((pmpWriteCfg w__7 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))
+ else if (((p00 = (( 2 :: int)::ii)))) then
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ (let pmp8cfg8 = (pmpWriteCfg w__8 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))) in
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ (let pmp9cfg9 = (pmpWriteCfg w__9 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) in
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ (write_reg
+ pmp10cfg_ref
+ ((pmpWriteCfg w__10 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp11cfg_ref) \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ write_reg
+ pmp11cfg_ref
+ ((pmpWriteCfg w__11 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))))
+ else if (((p00 = (( 3 :: int)::ii)))) then
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ (write_reg pmp12cfg_ref ((pmpWriteCfg w__12 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp13cfg_ref) \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ (write_reg pmp13cfg_ref ((pmpWriteCfg w__13 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp14cfg_ref) \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ (write_reg
+ pmp14cfg_ref
+ ((pmpWriteCfg w__14 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp15cfg_ref) \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ write_reg
+ pmp15cfg_ref
+ ((pmpWriteCfg w__15 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))
+ else
+ assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8'') \<then> exit0 () ))"
+ for n :: " int "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pmpWriteAddr : Pmpcfg_ent -> mword ty32 -> mword ty32 -> mword ty32\<close>\<close>
+
+definition pmpWriteAddr :: " Pmpcfg_ent \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word " where
+ " pmpWriteAddr (cfg :: Pmpcfg_ent) (reg :: xlenbits) (v :: xlenbits) = (
+ if (((((get_Pmpcfg_ent_L cfg :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then reg
+ else v )"
+ for cfg :: " Pmpcfg_ent "
+ and reg :: "(32)Word.word "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pmpAddrRange : Pmpcfg_ent -> mword ty32 -> mword ty32 -> M (maybe ((mword ty32 * mword ty32)))\<close>\<close>
+
+definition pmpAddrRange :: " Pmpcfg_ent \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(((32)Word.word*(32)Word.word)option),(exception))monad " where
+ " pmpAddrRange (cfg :: Pmpcfg_ent) (pmpaddr :: xlenbits) (prev_pmpaddr :: xlenbits) = (
+ pmpAddrMatchType_of_bits ((get_Pmpcfg_ent_A cfg :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: PmpAddrMatchType) .
+ return ((case w__0 of
+ OFF => None
+ | TOR => Some ((shiftl prev_pmpaddr (( 2 :: int)::ii) :: 32 Word.word), (shiftl pmpaddr (( 2 :: int)::ii) :: 32 Word.word))
+ | NA4 =>
+ (let lo = ((shiftl pmpaddr (( 2 :: int)::ii) :: 32 Word.word)) in
+ Some (lo, (add_vec_int lo (( 4 :: int)::ii) :: 32 Word.word)))
+ | NAPOT =>
+ (let mask1 = ((xor_vec pmpaddr ((add_vec_int pmpaddr (( 1 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) in
+ (let lo = ((and_vec pmpaddr ((not_vec mask1 :: 32 Word.word)) :: 32 Word.word)) in
+ (let len = ((add_vec_int mask1 (( 1 :: int)::ii) :: 32 Word.word)) in
+ Some ((shiftl lo (( 2 :: int)::ii) :: 32 Word.word),
+ (shiftl ((add_vec lo len :: 32 Word.word)) (( 2 :: int)::ii) :: 32 Word.word)))))
+ ))))"
+ for cfg :: " Pmpcfg_ent "
+ and pmpaddr :: "(32)Word.word "
+ and prev_pmpaddr :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pmpCheckRWX : Pmpcfg_ent -> AccessType -> bool\<close>\<close>
+
+fun pmpCheckRWX :: " Pmpcfg_ent \<Rightarrow> AccessType \<Rightarrow> bool " where
+ " pmpCheckRWX ent Read = ( (((get_Pmpcfg_ent_R ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent Write = ( (((get_Pmpcfg_ent_W ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent ReadWrite = (
+ ((((((get_Pmpcfg_ent_R ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_Pmpcfg_ent_W ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent Execute = ( (((get_Pmpcfg_ent_X ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val pmpCheckPerms : Pmpcfg_ent -> AccessType -> Privilege -> bool\<close>\<close>
+
+fun pmpCheckPerms :: " Pmpcfg_ent \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool " where
+ " pmpCheckPerms ent acc1 Machine = (
+ if (((((get_Pmpcfg_ent_L ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ pmpCheckRWX ent acc1
+ else True )"
+ for ent :: " Pmpcfg_ent "
+ and acc1 :: " AccessType "
+|" pmpCheckPerms ent acc1 _ = ( pmpCheckRWX ent acc1 )"
+ for ent :: " Pmpcfg_ent "
+ and acc1 :: " AccessType "
+
+
+\<comment> \<open>\<open>val pmpAddrMatch_of_num : integer -> pmpAddrMatch\<close>\<close>
+
+definition pmpAddrMatch_of_num :: " int \<Rightarrow> pmpAddrMatch " where
+ " pmpAddrMatch_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PMP_NoMatch
+ else if (((p00 = (( 1 :: int)::ii)))) then PMP_PartialMatch
+ else PMP_Match))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_pmpAddrMatch : pmpAddrMatch -> integer\<close>\<close>
+
+fun num_of_pmpAddrMatch :: " pmpAddrMatch \<Rightarrow> int " where
+ " num_of_pmpAddrMatch PMP_NoMatch = ( (( 0 :: int)::ii))"
+|" num_of_pmpAddrMatch PMP_PartialMatch = ( (( 1 :: int)::ii))"
+|" num_of_pmpAddrMatch PMP_Match = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpMatchAddr : mword ty32 -> mword ty32 -> maybe ((mword ty32 * mword ty32)) -> pmpAddrMatch\<close>\<close>
+
+fun pmpMatchAddr :: "(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(xlenbits*xlenbits)option \<Rightarrow> pmpAddrMatch " where
+ " pmpMatchAddr (addr :: xlenbits) (width :: xlenbits) (None :: pmp_addr_range) = ( PMP_NoMatch )"
+ for addr :: "(32)Word.word "
+ and width :: "(32)Word.word "
+|" pmpMatchAddr (addr :: xlenbits) (width :: xlenbits) ((Some ((lo, hi))) :: pmp_addr_range) = (
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if (((((zopz0zI_u ((add_vec addr width :: 32 Word.word)) lo)) \<or> ((zopz0zI_u hi addr)))))
+ then
+ PMP_NoMatch
+ else if (((((zopz0zIzJ_u lo addr)) \<and> ((zopz0zIzJ_u ((add_vec addr width :: 32 Word.word)) hi))))) then
+ PMP_Match
+ else PMP_PartialMatch )"
+ for addr :: "(32)Word.word "
+ and width :: "(32)Word.word "
+ and hi :: "(32)Word.word "
+ and lo :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pmpMatch_of_num : integer -> pmpMatch\<close>\<close>
+
+definition pmpMatch_of_num :: " int \<Rightarrow> pmpMatch " where
+ " pmpMatch_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PMP_Success
+ else if (((p00 = (( 1 :: int)::ii)))) then PMP_Continue
+ else PMP_Fail))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_pmpMatch : pmpMatch -> integer\<close>\<close>
+
+fun num_of_pmpMatch :: " pmpMatch \<Rightarrow> int " where
+ " num_of_pmpMatch PMP_Success = ( (( 0 :: int)::ii))"
+|" num_of_pmpMatch PMP_Continue = ( (( 1 :: int)::ii))"
+|" num_of_pmpMatch PMP_Fail = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpMatchEntry : mword ty32 -> mword ty32 -> AccessType -> Privilege -> Pmpcfg_ent -> mword ty32 -> mword ty32 -> M pmpMatch\<close>\<close>
+
+definition pmpMatchEntry :: "(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> Pmpcfg_ent \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(pmpMatch),(exception))monad " where
+ " pmpMatchEntry (addr :: xlenbits) (width :: xlenbits) (acc1 :: AccessType) (priv :: Privilege) (ent ::
+ Pmpcfg_ent) (pmpaddr :: xlenbits) (prev_pmpaddr :: xlenbits) = (
+ (pmpAddrRange ent pmpaddr prev_pmpaddr :: ( (( 32 Word.word * 32 Word.word))option) M) \<bind> (\<lambda> rng .
+ return ((case ((pmpMatchAddr addr width rng)) of
+ PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc1 priv)) then PMP_Success else PMP_Fail
+ ))))"
+ for addr :: "(32)Word.word "
+ and width :: "(32)Word.word "
+ and acc1 :: " AccessType "
+ and priv :: " Privilege "
+ and ent :: " Pmpcfg_ent "
+ and pmpaddr :: "(32)Word.word "
+ and prev_pmpaddr :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val pmpCheck : mword ty32 -> integer -> AccessType -> Privilege -> M (maybe ExceptionType)\<close>\<close>
+
+definition pmpCheck :: "(32)Word.word \<Rightarrow> int \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow>((register_value),((ExceptionType)option),(exception))monad " where
+ " pmpCheck (addr :: xlenbits) (width :: int) (acc1 :: AccessType) (priv :: Privilege) = (
+ (let (width :: xlenbits) = ((to_bits (( 32 :: int)::ii) width :: 32 Word.word)) in
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (read_reg pmpaddr0_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__0 w__1 ((zeros_implicit (( 32 :: int)::ii) :: 32 Word.word)) \<bind> (\<lambda> (w__2 ::
+ pmpMatch) .
+ (case w__2 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ (read_reg pmpaddr1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) .
+ (read_reg pmpaddr0_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__3 w__4 w__5 \<bind> (\<lambda> (w__6 :: pmpMatch) .
+ (case w__6 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ (read_reg pmpaddr2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) .
+ (read_reg pmpaddr1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__7 w__8 w__9 \<bind> (\<lambda> (w__10 :: pmpMatch) .
+ (case w__10 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ (read_reg pmpaddr3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) .
+ (read_reg pmpaddr2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__11 w__12 w__13 \<bind> (\<lambda> (w__14 :: pmpMatch) .
+ (case w__14 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ (read_reg pmpaddr4_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 Word.word) .
+ (read_reg pmpaddr3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__15 w__16 w__17 \<bind> (\<lambda> (w__18 :: pmpMatch) .
+ (case w__18 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__19 :: Pmpcfg_ent) .
+ (read_reg pmpaddr5_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 Word.word) .
+ (read_reg pmpaddr4_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__21 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__19 w__20 w__21 \<bind> (\<lambda> (w__22 :: pmpMatch) .
+ (case w__22 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__23 :: Pmpcfg_ent) .
+ (read_reg pmpaddr6_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 Word.word) .
+ (read_reg pmpaddr5_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__23 w__24 w__25 \<bind> (\<lambda> (w__26 :: pmpMatch) .
+ (case w__26 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__27 :: Pmpcfg_ent) .
+ (read_reg pmpaddr7_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__28 :: 32 Word.word) .
+ (read_reg pmpaddr6_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__29 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__27 w__28 w__29 \<bind> (\<lambda> (w__30 ::
+ pmpMatch) .
+ (case w__30 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__31 :: Pmpcfg_ent) .
+ (read_reg pmpaddr8_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__32 :: 32 Word.word) .
+ (read_reg pmpaddr7_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__33 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__31 w__32 w__33 \<bind> (\<lambda> (w__34 ::
+ pmpMatch) .
+ (case w__34 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__35 :: Pmpcfg_ent) .
+ (read_reg pmpaddr9_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__36 :: 32 Word.word) .
+ (read_reg pmpaddr8_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__37 :: 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__35 w__36 w__37 \<bind> (\<lambda> (w__38 ::
+ pmpMatch) .
+ (case w__38 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__39 :: Pmpcfg_ent) .
+ (read_reg pmpaddr10_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__40 ::
+ 32 Word.word) .
+ (read_reg pmpaddr9_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__41 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__39 w__40 w__41 \<bind> (\<lambda> (w__42 ::
+ pmpMatch) .
+ (case w__42 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__43 :: Pmpcfg_ent) .
+ (read_reg pmpaddr11_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__44 ::
+ 32 Word.word) .
+ (read_reg pmpaddr10_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__45 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__43 w__44 w__45 \<bind> (\<lambda> (w__46 ::
+ pmpMatch) .
+ (case w__46 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__47 :: Pmpcfg_ent) .
+ (read_reg pmpaddr12_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__48 ::
+ 32 Word.word) .
+ (read_reg pmpaddr11_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__49 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__47 w__48 w__49 \<bind> (\<lambda> (w__50 ::
+ pmpMatch) .
+ (case w__50 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__51 :: Pmpcfg_ent) .
+ (read_reg pmpaddr13_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__52 ::
+ 32 Word.word) .
+ (read_reg pmpaddr12_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__53 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__51 w__52 w__53 \<bind> (\<lambda> (w__54 ::
+ pmpMatch) .
+ (case w__54 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__55 :: Pmpcfg_ent) .
+ (read_reg pmpaddr14_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__56 ::
+ 32 Word.word) .
+ (read_reg pmpaddr13_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__57 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__55 w__56 w__57 \<bind> (\<lambda> (w__58 ::
+ pmpMatch) .
+ (case w__58 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__59 :: Pmpcfg_ent) .
+ (read_reg pmpaddr15_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__60 ::
+ 32 Word.word) .
+ (read_reg pmpaddr14_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__61 ::
+ 32 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__59 w__60 w__61 \<bind> (\<lambda> (w__62 ::
+ pmpMatch) .
+ return ((case w__62 of
+ PMP_Success => True
+ | PMP_Fail => False
+ | PMP_Continue =>
+ (case priv of
+ Machine => True
+ | _ => False
+ )
+ ))))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ ) \<bind> (\<lambda> (check' :: bool) .
+ return (if check' then None
+ else
+ (case acc1 of
+ Read => Some E_Load_Access_Fault
+ | Write => Some E_SAMO_Access_Fault
+ | ReadWrite => Some E_SAMO_Access_Fault
+ | Execute => Some E_Fetch_Access_Fault
+ ))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and acc1 :: " AccessType "
+ and priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val init_pmp : unit -> M unit\<close>\<close>
+
+definition init_pmp :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_pmp _ = (
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (write_reg pmp0cfg_ref ((update_Pmpcfg_ent_A w__0 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp1cfg_ref) \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ (write_reg pmp1cfg_ref ((update_Pmpcfg_ent_A w__1 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp2cfg_ref) \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ (write_reg pmp2cfg_ref ((update_Pmpcfg_ent_A w__2 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp3cfg_ref) \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ (write_reg pmp3cfg_ref ((update_Pmpcfg_ent_A w__3 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp4cfg_ref) \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ (write_reg pmp4cfg_ref ((update_Pmpcfg_ent_A w__4 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp5cfg_ref) \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ (write_reg pmp5cfg_ref ((update_Pmpcfg_ent_A w__5 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp6cfg_ref) \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ (write_reg pmp6cfg_ref ((update_Pmpcfg_ent_A w__6 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp7cfg_ref) \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ (write_reg pmp7cfg_ref ((update_Pmpcfg_ent_A w__7 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp8cfg_ref) \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ (write_reg pmp8cfg_ref ((update_Pmpcfg_ent_A w__8 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp9cfg_ref) \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ (write_reg pmp9cfg_ref ((update_Pmpcfg_ent_A w__9 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp10cfg_ref) \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ (write_reg
+ pmp10cfg_ref
+ ((update_Pmpcfg_ent_A w__10 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp11cfg_ref) \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ (write_reg
+ pmp11cfg_ref
+ ((update_Pmpcfg_ent_A w__11 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp12cfg_ref) \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ (write_reg
+ pmp12cfg_ref
+ ((update_Pmpcfg_ent_A w__12 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp13cfg_ref) \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ (write_reg
+ pmp13cfg_ref
+ ((update_Pmpcfg_ent_A w__13 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp14cfg_ref) \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ (write_reg
+ pmp14cfg_ref
+ ((update_Pmpcfg_ent_A w__14 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp15cfg_ref) \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ write_reg
+ pmp15cfg_ref
+ ((update_Pmpcfg_ent_A w__15 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))))))))))))))))))))"
+
+
+\<comment> \<open>\<open>val ext_init_regs : unit -> M unit\<close>\<close>
+
+definition ext_init_regs :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ext_init_regs _ = ( return () )"
+
+
+\<comment> \<open>\<open>
+This function is called after above when running rvfi and allows the model
+to be initialised differently (e.g. CHERI cap regs are initialised
+to omnipotent instead of null).
+ \<close>\<close>
+\<comment> \<open>\<open>val ext_rvfi_init : unit -> M unit\<close>\<close>
+
+definition ext_rvfi_init :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ext_rvfi_init _ = ( return () )"
+
+
+\<comment> \<open>\<open>val ext_fetch_check_pc : mword ty32 -> mword ty32 -> Ext_FetchAddr_Check unit\<close>\<close>
+
+definition ext_fetch_check_pc :: "(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(unit)Ext_FetchAddr_Check " where
+ " ext_fetch_check_pc (start_pc :: xlenbits) (pc :: xlenbits) = ( Ext_FetchAddr_OK pc )"
+ for start_pc :: "(32)Word.word "
+ and pc :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val ext_handle_fetch_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_fetch_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_fetch_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val ext_control_check_addr : mword ty32 -> Ext_ControlAddr_Check unit\<close>\<close>
+
+definition ext_control_check_addr :: "(32)Word.word \<Rightarrow>(unit)Ext_ControlAddr_Check " where
+ " ext_control_check_addr pc = ( Ext_ControlAddr_OK pc )"
+ for pc :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val ext_control_check_pc : mword ty32 -> Ext_ControlAddr_Check unit\<close>\<close>
+
+definition ext_control_check_pc :: "(32)Word.word \<Rightarrow>(unit)Ext_ControlAddr_Check " where
+ " ext_control_check_pc pc = ( Ext_ControlAddr_OK pc )"
+ for pc :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val ext_handle_control_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_control_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_control_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val ext_data_get_addr : mword ty5 -> mword ty32 -> AccessType -> word_width -> M (Ext_DataAddr_Check unit)\<close>\<close>
+
+definition ext_data_get_addr :: "(5)Word.word \<Rightarrow>(32)Word.word \<Rightarrow> AccessType \<Rightarrow> word_width \<Rightarrow>((register_value),((unit)Ext_DataAddr_Check),(exception))monad " where
+ " ext_data_get_addr (base :: regidx) (offset :: xlenbits) (acc1 :: AccessType) (width :: word_width) = (
+ (rX ((regidx_to_regno base)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let addr = ((add_vec w__0 offset :: 32 Word.word)) in
+ return (Ext_DataAddr_OK addr))))"
+ for base :: "(5)Word.word "
+ and offset :: "(32)Word.word "
+ and acc1 :: " AccessType "
+ and width :: " word_width "
+
+
+\<comment> \<open>\<open>val ext_handle_data_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_data_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_data_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val csr_name : mword ty12 -> string\<close>\<close>
+
+definition csr_name :: "(12)Word.word \<Rightarrow> string " where
+ " csr_name csr = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''ustatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''uie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''utvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''uscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''uepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''ucause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''utval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''uip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''fflags'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''frm'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''fcsr'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''cycle'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''time'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''instret'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''cycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''timeh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''instreth'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''sstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''sedeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''sideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''sie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''stvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (''scounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''sscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''sepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''scause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''stval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''sip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''satp'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''mvendorid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''marchid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mimpid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mhartid'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''misa'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''medeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''mtvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (''mcounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''mepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''mcause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mtval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''pmpcfg0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''pmpaddr0'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mcycle'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''minstret'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mcycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''minstreth'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''tselect'')
+ else (''UNKNOWN'')))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_forwards : mword ty12 -> M string\<close>\<close>
+
+definition csr_name_map_forwards :: "(12)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " csr_name_map_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''ustatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''uie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''utvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''uscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''uepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''ucause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''utval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''uip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''fflags'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''frm'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''fcsr'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''cycle'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''time'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''instret'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''cycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''timeh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''instreth'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''sstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''sedeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''sideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''sie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''stvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''scounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''sscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''sepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''scause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''stval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''sip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''satp'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''mvendorid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''marchid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mimpid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mhartid'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''misa'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''medeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''mtvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''mcounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''mepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''mcause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mtval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpcfg0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpcfg1'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpcfg2'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpcfg3'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr1'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr2'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr3'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr4'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr5'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr6'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr7'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr8'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr9'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr10'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr11'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr12'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr13'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr14'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr15'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mcycle'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''minstret'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mcycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''minstreth'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''tselect'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''tdata1'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''tdata2'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''tdata3'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_backwards : string -> M (mword ty12)\<close>\<close>
+
+definition csr_name_map_backwards :: " string \<Rightarrow>((register_value),((12)Word.word),(exception))monad " where
+ " csr_name_map_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''ustatus'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''uie'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''utvec'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''uscratch'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''uepc'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''ucause'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''utval'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''uip'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''fflags'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''frm'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''fcsr'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''cycle'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''time'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''instret'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''cycleh'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''timeh'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''instreth'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sstatus'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''sedeleg'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sideleg'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''sie'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''stvec'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''scounteren'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sscratch'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''sepc'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''scause'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''stval'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''sip'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''satp'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mvendorid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''marchid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mimpid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mhartid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mstatus'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''misa'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''medeleg'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mideleg'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mie'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mtvec'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''mcounteren'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mscratch'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mepc'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''mcause'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mtval'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mip'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg0'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg1'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg2'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg3'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr0'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr1'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr2'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr3'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr4'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr5'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr6'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr7'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr8'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr9'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr10'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr11'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr12'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr13'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr14'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr15'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mcycle'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''minstret'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mcycleh'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''minstreth'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''tselect'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''tdata1'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''tdata2'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''tdata3'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_name_map_forwards_matches : mword ty12 -> bool\<close>\<close>
+
+definition csr_name_map_forwards_matches :: "(12)Word.word \<Rightarrow> bool " where
+ " csr_name_map_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else False))"
+ for arg1 :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_backwards_matches : string -> bool\<close>\<close>
+
+definition csr_name_map_backwards_matches :: " string \<Rightarrow> bool " where
+ " csr_name_map_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''ustatus'')))) then True
+ else if (((p00 = (''uie'')))) then True
+ else if (((p00 = (''utvec'')))) then True
+ else if (((p00 = (''uscratch'')))) then True
+ else if (((p00 = (''uepc'')))) then True
+ else if (((p00 = (''ucause'')))) then True
+ else if (((p00 = (''utval'')))) then True
+ else if (((p00 = (''uip'')))) then True
+ else if (((p00 = (''fflags'')))) then True
+ else if (((p00 = (''frm'')))) then True
+ else if (((p00 = (''fcsr'')))) then True
+ else if (((p00 = (''cycle'')))) then True
+ else if (((p00 = (''time'')))) then True
+ else if (((p00 = (''instret'')))) then True
+ else if (((p00 = (''cycleh'')))) then True
+ else if (((p00 = (''timeh'')))) then True
+ else if (((p00 = (''instreth'')))) then True
+ else if (((p00 = (''sstatus'')))) then True
+ else if (((p00 = (''sedeleg'')))) then True
+ else if (((p00 = (''sideleg'')))) then True
+ else if (((p00 = (''sie'')))) then True
+ else if (((p00 = (''stvec'')))) then True
+ else if (((p00 = (''scounteren'')))) then True
+ else if (((p00 = (''sscratch'')))) then True
+ else if (((p00 = (''sepc'')))) then True
+ else if (((p00 = (''scause'')))) then True
+ else if (((p00 = (''stval'')))) then True
+ else if (((p00 = (''sip'')))) then True
+ else if (((p00 = (''satp'')))) then True
+ else if (((p00 = (''mvendorid'')))) then True
+ else if (((p00 = (''marchid'')))) then True
+ else if (((p00 = (''mimpid'')))) then True
+ else if (((p00 = (''mhartid'')))) then True
+ else if (((p00 = (''mstatus'')))) then True
+ else if (((p00 = (''misa'')))) then True
+ else if (((p00 = (''medeleg'')))) then True
+ else if (((p00 = (''mideleg'')))) then True
+ else if (((p00 = (''mie'')))) then True
+ else if (((p00 = (''mtvec'')))) then True
+ else if (((p00 = (''mcounteren'')))) then True
+ else if (((p00 = (''mscratch'')))) then True
+ else if (((p00 = (''mepc'')))) then True
+ else if (((p00 = (''mcause'')))) then True
+ else if (((p00 = (''mtval'')))) then True
+ else if (((p00 = (''mip'')))) then True
+ else if (((p00 = (''pmpcfg0'')))) then True
+ else if (((p00 = (''pmpcfg1'')))) then True
+ else if (((p00 = (''pmpcfg2'')))) then True
+ else if (((p00 = (''pmpcfg3'')))) then True
+ else if (((p00 = (''pmpaddr0'')))) then True
+ else if (((p00 = (''pmpaddr1'')))) then True
+ else if (((p00 = (''pmpaddr2'')))) then True
+ else if (((p00 = (''pmpaddr3'')))) then True
+ else if (((p00 = (''pmpaddr4'')))) then True
+ else if (((p00 = (''pmpaddr5'')))) then True
+ else if (((p00 = (''pmpaddr6'')))) then True
+ else if (((p00 = (''pmpaddr7'')))) then True
+ else if (((p00 = (''pmpaddr8'')))) then True
+ else if (((p00 = (''pmpaddr9'')))) then True
+ else if (((p00 = (''pmpaddr10'')))) then True
+ else if (((p00 = (''pmpaddr11'')))) then True
+ else if (((p00 = (''pmpaddr12'')))) then True
+ else if (((p00 = (''pmpaddr13'')))) then True
+ else if (((p00 = (''pmpaddr14'')))) then True
+ else if (((p00 = (''pmpaddr15'')))) then True
+ else if (((p00 = (''mcycle'')))) then True
+ else if (((p00 = (''minstret'')))) then True
+ else if (((p00 = (''mcycleh'')))) then True
+ else if (((p00 = (''minstreth'')))) then True
+ else if (((p00 = (''tselect'')))) then True
+ else if (((p00 = (''tdata1'')))) then True
+ else if (((p00 = (''tdata2'')))) then True
+ else if (((p00 = (''tdata3'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s488_ : string -> maybe string\<close>\<close>
+
+definition s488 :: " string \<Rightarrow>(string)option " where
+ " s488 s4890 = (
+ (let s4900 = s4890 in
+ if ((string_startswith s4900 (''tdata3''))) then
+ (case ((string_drop s4900 ((string_length (''tdata3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4890 :: " string "
+
+
+\<comment> \<open>\<open>val _s484_ : string -> maybe string\<close>\<close>
+
+definition s484 :: " string \<Rightarrow>(string)option " where
+ " s484 s4850 = (
+ (let s4860 = s4850 in
+ if ((string_startswith s4860 (''tdata2''))) then
+ (case ((string_drop s4860 ((string_length (''tdata2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4850 :: " string "
+
+
+\<comment> \<open>\<open>val _s480_ : string -> maybe string\<close>\<close>
+
+definition s480 :: " string \<Rightarrow>(string)option " where
+ " s480 s4810 = (
+ (let s4820 = s4810 in
+ if ((string_startswith s4820 (''tdata1''))) then
+ (case ((string_drop s4820 ((string_length (''tdata1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4810 :: " string "
+
+
+\<comment> \<open>\<open>val _s476_ : string -> maybe string\<close>\<close>
+
+definition s476 :: " string \<Rightarrow>(string)option " where
+ " s476 s4770 = (
+ (let s4780 = s4770 in
+ if ((string_startswith s4780 (''tselect''))) then
+ (case ((string_drop s4780 ((string_length (''tselect''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4770 :: " string "
+
+
+\<comment> \<open>\<open>val _s472_ : string -> maybe string\<close>\<close>
+
+definition s472 :: " string \<Rightarrow>(string)option " where
+ " s472 s4730 = (
+ (let s4740 = s4730 in
+ if ((string_startswith s4740 (''minstreth''))) then
+ (case ((string_drop s4740 ((string_length (''minstreth''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4730 :: " string "
+
+
+\<comment> \<open>\<open>val _s468_ : string -> maybe string\<close>\<close>
+
+definition s468 :: " string \<Rightarrow>(string)option " where
+ " s468 s4690 = (
+ (let s4700 = s4690 in
+ if ((string_startswith s4700 (''mcycleh''))) then
+ (case ((string_drop s4700 ((string_length (''mcycleh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4690 :: " string "
+
+
+\<comment> \<open>\<open>val _s464_ : string -> maybe string\<close>\<close>
+
+definition s464 :: " string \<Rightarrow>(string)option " where
+ " s464 s4650 = (
+ (let s4660 = s4650 in
+ if ((string_startswith s4660 (''minstret''))) then
+ (case ((string_drop s4660 ((string_length (''minstret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4650 :: " string "
+
+
+\<comment> \<open>\<open>val _s460_ : string -> maybe string\<close>\<close>
+
+definition s460 :: " string \<Rightarrow>(string)option " where
+ " s460 s4610 = (
+ (let s4620 = s4610 in
+ if ((string_startswith s4620 (''mcycle''))) then
+ (case ((string_drop s4620 ((string_length (''mcycle''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4610 :: " string "
+
+
+\<comment> \<open>\<open>val _s456_ : string -> maybe string\<close>\<close>
+
+definition s456 :: " string \<Rightarrow>(string)option " where
+ " s456 s4570 = (
+ (let s4580 = s4570 in
+ if ((string_startswith s4580 (''pmpaddr15''))) then
+ (case ((string_drop s4580 ((string_length (''pmpaddr15''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4570 :: " string "
+
+
+\<comment> \<open>\<open>val _s452_ : string -> maybe string\<close>\<close>
+
+definition s452 :: " string \<Rightarrow>(string)option " where
+ " s452 s4530 = (
+ (let s4540 = s4530 in
+ if ((string_startswith s4540 (''pmpaddr14''))) then
+ (case ((string_drop s4540 ((string_length (''pmpaddr14''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4530 :: " string "
+
+
+\<comment> \<open>\<open>val _s448_ : string -> maybe string\<close>\<close>
+
+definition s448 :: " string \<Rightarrow>(string)option " where
+ " s448 s4490 = (
+ (let s4500 = s4490 in
+ if ((string_startswith s4500 (''pmpaddr13''))) then
+ (case ((string_drop s4500 ((string_length (''pmpaddr13''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4490 :: " string "
+
+
+\<comment> \<open>\<open>val _s444_ : string -> maybe string\<close>\<close>
+
+definition s444 :: " string \<Rightarrow>(string)option " where
+ " s444 s4450 = (
+ (let s4460 = s4450 in
+ if ((string_startswith s4460 (''pmpaddr12''))) then
+ (case ((string_drop s4460 ((string_length (''pmpaddr12''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4450 :: " string "
+
+
+\<comment> \<open>\<open>val _s440_ : string -> maybe string\<close>\<close>
+
+definition s440 :: " string \<Rightarrow>(string)option " where
+ " s440 s4410 = (
+ (let s4420 = s4410 in
+ if ((string_startswith s4420 (''pmpaddr11''))) then
+ (case ((string_drop s4420 ((string_length (''pmpaddr11''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4410 :: " string "
+
+
+\<comment> \<open>\<open>val _s436_ : string -> maybe string\<close>\<close>
+
+definition s436 :: " string \<Rightarrow>(string)option " where
+ " s436 s4370 = (
+ (let s4380 = s4370 in
+ if ((string_startswith s4380 (''pmpaddr10''))) then
+ (case ((string_drop s4380 ((string_length (''pmpaddr10''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4370 :: " string "
+
+
+\<comment> \<open>\<open>val _s432_ : string -> maybe string\<close>\<close>
+
+definition s432 :: " string \<Rightarrow>(string)option " where
+ " s432 s4330 = (
+ (let s4340 = s4330 in
+ if ((string_startswith s4340 (''pmpaddr9''))) then
+ (case ((string_drop s4340 ((string_length (''pmpaddr9''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4330 :: " string "
+
+
+\<comment> \<open>\<open>val _s428_ : string -> maybe string\<close>\<close>
+
+definition s428 :: " string \<Rightarrow>(string)option " where
+ " s428 s4290 = (
+ (let s4300 = s4290 in
+ if ((string_startswith s4300 (''pmpaddr8''))) then
+ (case ((string_drop s4300 ((string_length (''pmpaddr8''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4290 :: " string "
+
+
+\<comment> \<open>\<open>val _s424_ : string -> maybe string\<close>\<close>
+
+definition s424 :: " string \<Rightarrow>(string)option " where
+ " s424 s4250 = (
+ (let s4260 = s4250 in
+ if ((string_startswith s4260 (''pmpaddr7''))) then
+ (case ((string_drop s4260 ((string_length (''pmpaddr7''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4250 :: " string "
+
+
+\<comment> \<open>\<open>val _s420_ : string -> maybe string\<close>\<close>
+
+definition s420 :: " string \<Rightarrow>(string)option " where
+ " s420 s4210 = (
+ (let s4220 = s4210 in
+ if ((string_startswith s4220 (''pmpaddr6''))) then
+ (case ((string_drop s4220 ((string_length (''pmpaddr6''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4210 :: " string "
+
+
+\<comment> \<open>\<open>val _s416_ : string -> maybe string\<close>\<close>
+
+definition s416 :: " string \<Rightarrow>(string)option " where
+ " s416 s4170 = (
+ (let s4180 = s4170 in
+ if ((string_startswith s4180 (''pmpaddr5''))) then
+ (case ((string_drop s4180 ((string_length (''pmpaddr5''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4170 :: " string "
+
+
+\<comment> \<open>\<open>val _s412_ : string -> maybe string\<close>\<close>
+
+definition s412 :: " string \<Rightarrow>(string)option " where
+ " s412 s4130 = (
+ (let s4140 = s4130 in
+ if ((string_startswith s4140 (''pmpaddr4''))) then
+ (case ((string_drop s4140 ((string_length (''pmpaddr4''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4130 :: " string "
+
+
+\<comment> \<open>\<open>val _s408_ : string -> maybe string\<close>\<close>
+
+definition s408 :: " string \<Rightarrow>(string)option " where
+ " s408 s4090 = (
+ (let s4100 = s4090 in
+ if ((string_startswith s4100 (''pmpaddr3''))) then
+ (case ((string_drop s4100 ((string_length (''pmpaddr3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4090 :: " string "
+
+
+\<comment> \<open>\<open>val _s404_ : string -> maybe string\<close>\<close>
+
+definition s404 :: " string \<Rightarrow>(string)option " where
+ " s404 s4050 = (
+ (let s4060 = s4050 in
+ if ((string_startswith s4060 (''pmpaddr2''))) then
+ (case ((string_drop s4060 ((string_length (''pmpaddr2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4050 :: " string "
+
+
+\<comment> \<open>\<open>val _s400_ : string -> maybe string\<close>\<close>
+
+definition s400 :: " string \<Rightarrow>(string)option " where
+ " s400 s4010 = (
+ (let s4020 = s4010 in
+ if ((string_startswith s4020 (''pmpaddr1''))) then
+ (case ((string_drop s4020 ((string_length (''pmpaddr1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4010 :: " string "
+
+
+\<comment> \<open>\<open>val _s396_ : string -> maybe string\<close>\<close>
+
+definition s396 :: " string \<Rightarrow>(string)option " where
+ " s396 s3970 = (
+ (let s3980 = s3970 in
+ if ((string_startswith s3980 (''pmpaddr0''))) then
+ (case ((string_drop s3980 ((string_length (''pmpaddr0''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3970 :: " string "
+
+
+\<comment> \<open>\<open>val _s392_ : string -> maybe string\<close>\<close>
+
+definition s392 :: " string \<Rightarrow>(string)option " where
+ " s392 s3930 = (
+ (let s3940 = s3930 in
+ if ((string_startswith s3940 (''pmpcfg3''))) then
+ (case ((string_drop s3940 ((string_length (''pmpcfg3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3930 :: " string "
+
+
+\<comment> \<open>\<open>val _s388_ : string -> maybe string\<close>\<close>
+
+definition s388 :: " string \<Rightarrow>(string)option " where
+ " s388 s3890 = (
+ (let s3900 = s3890 in
+ if ((string_startswith s3900 (''pmpcfg2''))) then
+ (case ((string_drop s3900 ((string_length (''pmpcfg2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3890 :: " string "
+
+
+\<comment> \<open>\<open>val _s384_ : string -> maybe string\<close>\<close>
+
+definition s384 :: " string \<Rightarrow>(string)option " where
+ " s384 s3850 = (
+ (let s3860 = s3850 in
+ if ((string_startswith s3860 (''pmpcfg1''))) then
+ (case ((string_drop s3860 ((string_length (''pmpcfg1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3850 :: " string "
+
+
+\<comment> \<open>\<open>val _s380_ : string -> maybe string\<close>\<close>
+
+definition s380 :: " string \<Rightarrow>(string)option " where
+ " s380 s3810 = (
+ (let s3820 = s3810 in
+ if ((string_startswith s3820 (''pmpcfg0''))) then
+ (case ((string_drop s3820 ((string_length (''pmpcfg0''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3810 :: " string "
+
+
+\<comment> \<open>\<open>val _s376_ : string -> maybe string\<close>\<close>
+
+definition s376 :: " string \<Rightarrow>(string)option " where
+ " s376 s3770 = (
+ (let s3780 = s3770 in
+ if ((string_startswith s3780 (''mip''))) then
+ (case ((string_drop s3780 ((string_length (''mip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3770 :: " string "
+
+
+\<comment> \<open>\<open>val _s372_ : string -> maybe string\<close>\<close>
+
+definition s372 :: " string \<Rightarrow>(string)option " where
+ " s372 s3730 = (
+ (let s3740 = s3730 in
+ if ((string_startswith s3740 (''mtval''))) then
+ (case ((string_drop s3740 ((string_length (''mtval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3730 :: " string "
+
+
+\<comment> \<open>\<open>val _s368_ : string -> maybe string\<close>\<close>
+
+definition s368 :: " string \<Rightarrow>(string)option " where
+ " s368 s3690 = (
+ (let s3700 = s3690 in
+ if ((string_startswith s3700 (''mcause''))) then
+ (case ((string_drop s3700 ((string_length (''mcause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3690 :: " string "
+
+
+\<comment> \<open>\<open>val _s364_ : string -> maybe string\<close>\<close>
+
+definition s364 :: " string \<Rightarrow>(string)option " where
+ " s364 s3650 = (
+ (let s3660 = s3650 in
+ if ((string_startswith s3660 (''mepc''))) then
+ (case ((string_drop s3660 ((string_length (''mepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3650 :: " string "
+
+
+\<comment> \<open>\<open>val _s360_ : string -> maybe string\<close>\<close>
+
+definition s360 :: " string \<Rightarrow>(string)option " where
+ " s360 s3610 = (
+ (let s3620 = s3610 in
+ if ((string_startswith s3620 (''mscratch''))) then
+ (case ((string_drop s3620 ((string_length (''mscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3610 :: " string "
+
+
+\<comment> \<open>\<open>val _s356_ : string -> maybe string\<close>\<close>
+
+definition s356 :: " string \<Rightarrow>(string)option " where
+ " s356 s3570 = (
+ (let s3580 = s3570 in
+ if ((string_startswith s3580 (''mcounteren''))) then
+ (case ((string_drop s3580 ((string_length (''mcounteren''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3570 :: " string "
+
+
+\<comment> \<open>\<open>val _s352_ : string -> maybe string\<close>\<close>
+
+definition s352 :: " string \<Rightarrow>(string)option " where
+ " s352 s3530 = (
+ (let s3540 = s3530 in
+ if ((string_startswith s3540 (''mtvec''))) then
+ (case ((string_drop s3540 ((string_length (''mtvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3530 :: " string "
+
+
+\<comment> \<open>\<open>val _s348_ : string -> maybe string\<close>\<close>
+
+definition s348 :: " string \<Rightarrow>(string)option " where
+ " s348 s3490 = (
+ (let s3500 = s3490 in
+ if ((string_startswith s3500 (''mie''))) then
+ (case ((string_drop s3500 ((string_length (''mie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3490 :: " string "
+
+
+\<comment> \<open>\<open>val _s344_ : string -> maybe string\<close>\<close>
+
+definition s344 :: " string \<Rightarrow>(string)option " where
+ " s344 s3450 = (
+ (let s3460 = s3450 in
+ if ((string_startswith s3460 (''mideleg''))) then
+ (case ((string_drop s3460 ((string_length (''mideleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3450 :: " string "
+
+
+\<comment> \<open>\<open>val _s340_ : string -> maybe string\<close>\<close>
+
+definition s340 :: " string \<Rightarrow>(string)option " where
+ " s340 s3411 = (
+ (let s3420 = s3411 in
+ if ((string_startswith s3420 (''medeleg''))) then
+ (case ((string_drop s3420 ((string_length (''medeleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3411 :: " string "
+
+
+\<comment> \<open>\<open>val _s336_ : string -> maybe string\<close>\<close>
+
+definition s336 :: " string \<Rightarrow>(string)option " where
+ " s336 s3370 = (
+ (let s3380 = s3370 in
+ if ((string_startswith s3380 (''misa''))) then
+ (case ((string_drop s3380 ((string_length (''misa''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3370 :: " string "
+
+
+\<comment> \<open>\<open>val _s332_ : string -> maybe string\<close>\<close>
+
+definition s332 :: " string \<Rightarrow>(string)option " where
+ " s332 s3330 = (
+ (let s3340 = s3330 in
+ if ((string_startswith s3340 (''mstatus''))) then
+ (case ((string_drop s3340 ((string_length (''mstatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3330 :: " string "
+
+
+\<comment> \<open>\<open>val _s328_ : string -> maybe string\<close>\<close>
+
+definition s328 :: " string \<Rightarrow>(string)option " where
+ " s328 s3290 = (
+ (let s3300 = s3290 in
+ if ((string_startswith s3300 (''mhartid''))) then
+ (case ((string_drop s3300 ((string_length (''mhartid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3290 :: " string "
+
+
+\<comment> \<open>\<open>val _s324_ : string -> maybe string\<close>\<close>
+
+definition s324 :: " string \<Rightarrow>(string)option " where
+ " s324 s3250 = (
+ (let s3260 = s3250 in
+ if ((string_startswith s3260 (''mimpid''))) then
+ (case ((string_drop s3260 ((string_length (''mimpid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3250 :: " string "
+
+
+\<comment> \<open>\<open>val _s320_ : string -> maybe string\<close>\<close>
+
+definition s320 :: " string \<Rightarrow>(string)option " where
+ " s320 s3210 = (
+ (let s3220 = s3210 in
+ if ((string_startswith s3220 (''marchid''))) then
+ (case ((string_drop s3220 ((string_length (''marchid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3210 :: " string "
+
+
+\<comment> \<open>\<open>val _s316_ : string -> maybe string\<close>\<close>
+
+definition s316 :: " string \<Rightarrow>(string)option " where
+ " s316 s3170 = (
+ (let s3180 = s3170 in
+ if ((string_startswith s3180 (''mvendorid''))) then
+ (case ((string_drop s3180 ((string_length (''mvendorid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3170 :: " string "
+
+
+\<comment> \<open>\<open>val _s312_ : string -> maybe string\<close>\<close>
+
+definition s312 :: " string \<Rightarrow>(string)option " where
+ " s312 s3130 = (
+ (let s3140 = s3130 in
+ if ((string_startswith s3140 (''satp''))) then
+ (case ((string_drop s3140 ((string_length (''satp''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3130 :: " string "
+
+
+\<comment> \<open>\<open>val _s308_ : string -> maybe string\<close>\<close>
+
+definition s308 :: " string \<Rightarrow>(string)option " where
+ " s308 s3090 = (
+ (let s3100 = s3090 in
+ if ((string_startswith s3100 (''sip''))) then
+ (case ((string_drop s3100 ((string_length (''sip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3090 :: " string "
+
+
+\<comment> \<open>\<open>val _s304_ : string -> maybe string\<close>\<close>
+
+definition s304 :: " string \<Rightarrow>(string)option " where
+ " s304 s3050 = (
+ (let s3060 = s3050 in
+ if ((string_startswith s3060 (''stval''))) then
+ (case ((string_drop s3060 ((string_length (''stval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3050 :: " string "
+
+
+\<comment> \<open>\<open>val _s300_ : string -> maybe string\<close>\<close>
+
+definition s300 :: " string \<Rightarrow>(string)option " where
+ " s300 s3010 = (
+ (let s3020 = s3010 in
+ if ((string_startswith s3020 (''scause''))) then
+ (case ((string_drop s3020 ((string_length (''scause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3010 :: " string "
+
+
+\<comment> \<open>\<open>val _s296_ : string -> maybe string\<close>\<close>
+
+definition s296 :: " string \<Rightarrow>(string)option " where
+ " s296 s2970 = (
+ (let s2980 = s2970 in
+ if ((string_startswith s2980 (''sepc''))) then
+ (case ((string_drop s2980 ((string_length (''sepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2970 :: " string "
+
+
+\<comment> \<open>\<open>val _s292_ : string -> maybe string\<close>\<close>
+
+definition s292 :: " string \<Rightarrow>(string)option " where
+ " s292 s2930 = (
+ (let s2940 = s2930 in
+ if ((string_startswith s2940 (''sscratch''))) then
+ (case ((string_drop s2940 ((string_length (''sscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2930 :: " string "
+
+
+\<comment> \<open>\<open>val _s288_ : string -> maybe string\<close>\<close>
+
+definition s288 :: " string \<Rightarrow>(string)option " where
+ " s288 s2890 = (
+ (let s2900 = s2890 in
+ if ((string_startswith s2900 (''scounteren''))) then
+ (case ((string_drop s2900 ((string_length (''scounteren''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2890 :: " string "
+
+
+\<comment> \<open>\<open>val _s284_ : string -> maybe string\<close>\<close>
+
+definition s284 :: " string \<Rightarrow>(string)option " where
+ " s284 s2850 = (
+ (let s2860 = s2850 in
+ if ((string_startswith s2860 (''stvec''))) then
+ (case ((string_drop s2860 ((string_length (''stvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2850 :: " string "
+
+
+\<comment> \<open>\<open>val _s280_ : string -> maybe string\<close>\<close>
+
+definition s280 :: " string \<Rightarrow>(string)option " where
+ " s280 s2810 = (
+ (let s2820 = s2810 in
+ if ((string_startswith s2820 (''sie''))) then
+ (case ((string_drop s2820 ((string_length (''sie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2810 :: " string "
+
+
+\<comment> \<open>\<open>val _s276_ : string -> maybe string\<close>\<close>
+
+definition s276 :: " string \<Rightarrow>(string)option " where
+ " s276 s2770 = (
+ (let s2780 = s2770 in
+ if ((string_startswith s2780 (''sideleg''))) then
+ (case ((string_drop s2780 ((string_length (''sideleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2770 :: " string "
+
+
+\<comment> \<open>\<open>val _s272_ : string -> maybe string\<close>\<close>
+
+definition s272 :: " string \<Rightarrow>(string)option " where
+ " s272 s2730 = (
+ (let s2741 = s2730 in
+ if ((string_startswith s2741 (''sedeleg''))) then
+ (case ((string_drop s2741 ((string_length (''sedeleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2730 :: " string "
+
+
+\<comment> \<open>\<open>val _s268_ : string -> maybe string\<close>\<close>
+
+definition s268 :: " string \<Rightarrow>(string)option " where
+ " s268 s2690 = (
+ (let s2700 = s2690 in
+ if ((string_startswith s2700 (''sstatus''))) then
+ (case ((string_drop s2700 ((string_length (''sstatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2690 :: " string "
+
+
+\<comment> \<open>\<open>val _s264_ : string -> maybe string\<close>\<close>
+
+definition s264 :: " string \<Rightarrow>(string)option " where
+ " s264 s2650 = (
+ (let s2660 = s2650 in
+ if ((string_startswith s2660 (''instreth''))) then
+ (case ((string_drop s2660 ((string_length (''instreth''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2650 :: " string "
+
+
+\<comment> \<open>\<open>val _s260_ : string -> maybe string\<close>\<close>
+
+definition s260 :: " string \<Rightarrow>(string)option " where
+ " s260 s2610 = (
+ (let s2620 = s2610 in
+ if ((string_startswith s2620 (''timeh''))) then
+ (case ((string_drop s2620 ((string_length (''timeh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2610 :: " string "
+
+
+\<comment> \<open>\<open>val _s256_ : string -> maybe string\<close>\<close>
+
+definition s256 :: " string \<Rightarrow>(string)option " where
+ " s256 s2571 = (
+ (let s2580 = s2571 in
+ if ((string_startswith s2580 (''cycleh''))) then
+ (case ((string_drop s2580 ((string_length (''cycleh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2571 :: " string "
+
+
+\<comment> \<open>\<open>val _s252_ : string -> maybe string\<close>\<close>
+
+definition s252 :: " string \<Rightarrow>(string)option " where
+ " s252 s2530 = (
+ (let s2540 = s2530 in
+ if ((string_startswith s2540 (''instret''))) then
+ (case ((string_drop s2540 ((string_length (''instret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2530 :: " string "
+
+
+\<comment> \<open>\<open>val _s248_ : string -> maybe string\<close>\<close>
+
+definition s248 :: " string \<Rightarrow>(string)option " where
+ " s248 s2490 = (
+ (let s2500 = s2490 in
+ if ((string_startswith s2500 (''time''))) then
+ (case ((string_drop s2500 ((string_length (''time''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2490 :: " string "
+
+
+\<comment> \<open>\<open>val _s244_ : string -> maybe string\<close>\<close>
+
+definition s244 :: " string \<Rightarrow>(string)option " where
+ " s244 s2450 = (
+ (let s2460 = s2450 in
+ if ((string_startswith s2460 (''cycle''))) then
+ (case ((string_drop s2460 ((string_length (''cycle''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2450 :: " string "
+
+
+\<comment> \<open>\<open>val _s240_ : string -> maybe string\<close>\<close>
+
+definition s240 :: " string \<Rightarrow>(string)option " where
+ " s240 s2410 = (
+ (let s2420 = s2410 in
+ if ((string_startswith s2420 (''fcsr''))) then
+ (case ((string_drop s2420 ((string_length (''fcsr''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2410 :: " string "
+
+
+\<comment> \<open>\<open>val _s236_ : string -> maybe string\<close>\<close>
+
+definition s236 :: " string \<Rightarrow>(string)option " where
+ " s236 s2370 = (
+ (let s2380 = s2370 in
+ if ((string_startswith s2380 (''frm''))) then
+ (case ((string_drop s2380 ((string_length (''frm''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2370 :: " string "
+
+
+\<comment> \<open>\<open>val _s232_ : string -> maybe string\<close>\<close>
+
+definition s232 :: " string \<Rightarrow>(string)option " where
+ " s232 s2330 = (
+ (let s2340 = s2330 in
+ if ((string_startswith s2340 (''fflags''))) then
+ (case ((string_drop s2340 ((string_length (''fflags''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2330 :: " string "
+
+
+\<comment> \<open>\<open>val _s228_ : string -> maybe string\<close>\<close>
+
+definition s228 :: " string \<Rightarrow>(string)option " where
+ " s228 s2290 = (
+ (let s2300 = s2290 in
+ if ((string_startswith s2300 (''uip''))) then
+ (case ((string_drop s2300 ((string_length (''uip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2290 :: " string "
+
+
+\<comment> \<open>\<open>val _s224_ : string -> maybe string\<close>\<close>
+
+definition s224 :: " string \<Rightarrow>(string)option " where
+ " s224 s2250 = (
+ (let s2260 = s2250 in
+ if ((string_startswith s2260 (''utval''))) then
+ (case ((string_drop s2260 ((string_length (''utval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2250 :: " string "
+
+
+\<comment> \<open>\<open>val _s220_ : string -> maybe string\<close>\<close>
+
+definition s220 :: " string \<Rightarrow>(string)option " where
+ " s220 s2210 = (
+ (let s2220 = s2210 in
+ if ((string_startswith s2220 (''ucause''))) then
+ (case ((string_drop s2220 ((string_length (''ucause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2210 :: " string "
+
+
+\<comment> \<open>\<open>val _s216_ : string -> maybe string\<close>\<close>
+
+definition s216 :: " string \<Rightarrow>(string)option " where
+ " s216 s2170 = (
+ (let s2180 = s2170 in
+ if ((string_startswith s2180 (''uepc''))) then
+ (case ((string_drop s2180 ((string_length (''uepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2170 :: " string "
+
+
+\<comment> \<open>\<open>val _s212_ : string -> maybe string\<close>\<close>
+
+definition s212 :: " string \<Rightarrow>(string)option " where
+ " s212 s2130 = (
+ (let s2140 = s2130 in
+ if ((string_startswith s2140 (''uscratch''))) then
+ (case ((string_drop s2140 ((string_length (''uscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2130 :: " string "
+
+
+\<comment> \<open>\<open>val _s208_ : string -> maybe string\<close>\<close>
+
+definition s208 :: " string \<Rightarrow>(string)option " where
+ " s208 s2090 = (
+ (let s2100 = s2090 in
+ if ((string_startswith s2100 (''utvec''))) then
+ (case ((string_drop s2100 ((string_length (''utvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2090 :: " string "
+
+
+\<comment> \<open>\<open>val _s204_ : string -> maybe string\<close>\<close>
+
+definition s204 :: " string \<Rightarrow>(string)option " where
+ " s204 s2050 = (
+ (let s2060 = s2050 in
+ if ((string_startswith s2060 (''uie''))) then
+ (case ((string_drop s2060 ((string_length (''uie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2050 :: " string "
+
+
+\<comment> \<open>\<open>val _s200_ : string -> maybe string\<close>\<close>
+
+definition s200 :: " string \<Rightarrow>(string)option " where
+ " s200 s2010 = (
+ (let s2020 = s2010 in
+ if ((string_startswith s2020 (''ustatus''))) then
+ (case ((string_drop s2020 ((string_length (''ustatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2010 :: " string "
+
+
+definition csr_name_map_matches_prefix :: " string \<Rightarrow>((12)Word.word*int)option " where
+ " csr_name_map_matches_prefix arg1 = (
+ (let s2030 = arg1 in
+ if ((case ((s200 s2030)) of Some (s1) => True | _ => False )) then
+ (case s200 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s204 s2030)) of Some (s1) => True | _ => False )) then
+ (case s204 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s208 s2030)) of Some (s1) => True | _ => False )) then
+ (case s208 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s212 s2030)) of Some (s1) => True | _ => False )) then
+ (case s212 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s216 s2030)) of Some (s1) => True | _ => False )) then
+ (case s216 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s220 s2030)) of Some (s1) => True | _ => False )) then
+ (case s220 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s224 s2030)) of Some (s1) => True | _ => False )) then
+ (case s224 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s228 s2030)) of Some (s1) => True | _ => False )) then
+ (case s228 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s232 s2030)) of Some (s1) => True | _ => False )) then
+ (case s232 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s236 s2030)) of Some (s1) => True | _ => False )) then
+ (case s236 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s240 s2030)) of Some (s1) => True | _ => False )) then
+ (case s240 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s244 s2030)) of Some (s1) => True | _ => False )) then
+ (case s244 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s248 s2030)) of Some (s1) => True | _ => False )) then
+ (case s248 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s252 s2030)) of Some (s1) => True | _ => False )) then
+ (case s252 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s256 s2030)) of Some (s1) => True | _ => False )) then
+ (case s256 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s260 s2030)) of Some (s1) => True | _ => False )) then
+ (case s260 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s264 s2030)) of Some (s1) => True | _ => False )) then
+ (case s264 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s268 s2030)) of Some (s1) => True | _ => False )) then
+ (case s268 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s272 s2030)) of Some (s1) => True | _ => False )) then
+ (case s272 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s276 s2030)) of Some (s1) => True | _ => False )) then
+ (case s276 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s280 s2030)) of Some (s1) => True | _ => False )) then
+ (case s280 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s284 s2030)) of Some (s1) => True | _ => False )) then
+ (case s284 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s288 s2030)) of Some (s1) => True | _ => False )) then
+ (case s288 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s292 s2030)) of Some (s1) => True | _ => False )) then
+ (case s292 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s296 s2030)) of Some (s1) => True | _ => False )) then
+ (case s296 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s300 s2030)) of Some (s1) => True | _ => False )) then
+ (case s300 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s304 s2030)) of Some (s1) => True | _ => False )) then
+ (case s304 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s308 s2030)) of Some (s1) => True | _ => False )) then
+ (case s308 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s312 s2030)) of Some (s1) => True | _ => False )) then
+ (case s312 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s316 s2030)) of Some (s1) => True | _ => False )) then
+ (case s316 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s320 s2030)) of Some (s1) => True | _ => False )) then
+ (case s320 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s324 s2030)) of Some (s1) => True | _ => False )) then
+ (case s324 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s328 s2030)) of Some (s1) => True | _ => False )) then
+ (case s328 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s332 s2030)) of Some (s1) => True | _ => False )) then
+ (case s332 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s336 s2030)) of Some (s1) => True | _ => False )) then
+ (case s336 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s340 s2030)) of Some (s1) => True | _ => False )) then
+ (case s340 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s344 s2030)) of Some (s1) => True | _ => False )) then
+ (case s344 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s348 s2030)) of Some (s1) => True | _ => False )) then
+ (case s348 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s352 s2030)) of Some (s1) => True | _ => False )) then
+ (case s352 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s356 s2030)) of Some (s1) => True | _ => False )) then
+ (case s356 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s360 s2030)) of Some (s1) => True | _ => False )) then
+ (case s360 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s364 s2030)) of Some (s1) => True | _ => False )) then
+ (case s364 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s368 s2030)) of Some (s1) => True | _ => False )) then
+ (case s368 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s372 s2030)) of Some (s1) => True | _ => False )) then
+ (case s372 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s376 s2030)) of Some (s1) => True | _ => False )) then
+ (case s376 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s380 s2030)) of Some (s1) => True | _ => False )) then
+ (case s380 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s384 s2030)) of Some (s1) => True | _ => False )) then
+ (case s384 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s388 s2030)) of Some (s1) => True | _ => False )) then
+ (case s388 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s392 s2030)) of Some (s1) => True | _ => False )) then
+ (case s392 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s396 s2030)) of Some (s1) => True | _ => False )) then
+ (case s396 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s400 s2030)) of Some (s1) => True | _ => False )) then
+ (case s400 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s404 s2030)) of Some (s1) => True | _ => False )) then
+ (case s404 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s408 s2030)) of Some (s1) => True | _ => False )) then
+ (case s408 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s412 s2030)) of Some (s1) => True | _ => False )) then
+ (case s412 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s416 s2030)) of Some (s1) => True | _ => False )) then
+ (case s416 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s420 s2030)) of Some (s1) => True | _ => False )) then
+ (case s420 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s424 s2030)) of Some (s1) => True | _ => False )) then
+ (case s424 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s428 s2030)) of Some (s1) => True | _ => False )) then
+ (case s428 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s432 s2030)) of Some (s1) => True | _ => False )) then
+ (case s432 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s436 s2030)) of Some (s1) => True | _ => False )) then
+ (case s436 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s440 s2030)) of Some (s1) => True | _ => False )) then
+ (case s440 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s444 s2030)) of Some (s1) => True | _ => False )) then
+ (case s444 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s448 s2030)) of Some (s1) => True | _ => False )) then
+ (case s448 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s452 s2030)) of Some (s1) => True | _ => False )) then
+ (case s452 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s456 s2030)) of Some (s1) => True | _ => False )) then
+ (case s456 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s460 s2030)) of Some (s1) => True | _ => False )) then
+ (case s460 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s464 s2030)) of Some (s1) => True | _ => False )) then
+ (case s464 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s468 s2030)) of Some (s1) => True | _ => False )) then
+ (case s468 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s472 s2030)) of Some (s1) => True | _ => False )) then
+ (case s472 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s476 s2030)) of Some (s1) => True | _ => False )) then
+ (case s476 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s480 s2030)) of Some (s1) => True | _ => False )) then
+ (case s480 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s484 s2030)) of Some (s1) => True | _ => False )) then
+ (case s484 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s488 s2030)) of Some (s1) => True | _ => False )) then
+ (case s488 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val Mk_Ustatus : mword ty32 -> Ustatus\<close>\<close>
+
+definition Mk_Ustatus :: "(32)Word.word \<Rightarrow> Ustatus " where
+ " Mk_Ustatus v = (
+ (| Ustatus_Ustatus_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Ustatus_bits : Ustatus -> mword ty32\<close>\<close>
+
+definition get_Ustatus_bits :: " Ustatus \<Rightarrow>(32)Word.word " where
+ " get_Ustatus_bits v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Ustatus "
+
+
+\<comment> \<open>\<open>val _set_Ustatus_bits : register_ref regstate register_value Ustatus -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Ustatus_bits :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_bits : Ustatus -> mword ty32 -> Ustatus\<close>\<close>
+
+definition update_Ustatus_bits :: " Ustatus \<Rightarrow>(32)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_bits v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(32)Word.word "
+
+
+definition get_Ustatus_UPIE :: " Ustatus \<Rightarrow>(1)Word.word " where
+ " get_Ustatus_UPIE v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Ustatus "
+
+
+definition set_Ustatus_UPIE :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Ustatus_UPIE :: " Ustatus \<Rightarrow>(1)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_UPIE v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Ustatus_UIE :: " Ustatus \<Rightarrow>(1)Word.word " where
+ " get_Ustatus_UIE v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Ustatus "
+
+
+definition set_Ustatus_UIE :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Ustatus_UIE :: " Ustatus \<Rightarrow>(1)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_UIE v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_sstatus : Sstatus -> Ustatus\<close>\<close>
+
+definition lower_sstatus :: " Sstatus \<Rightarrow> Ustatus " where
+ " lower_sstatus s = (
+ (let u = (Mk_Ustatus ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let u = (update_Ustatus_UPIE u ((get_Sstatus_UPIE s :: 1 Word.word))) in
+ update_Ustatus_UIE u ((get_Sstatus_UIE s :: 1 Word.word)))))"
+ for s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val lift_ustatus : Sstatus -> Ustatus -> Sstatus\<close>\<close>
+
+definition lift_ustatus :: " Sstatus \<Rightarrow> Ustatus \<Rightarrow> Sstatus " where
+ " lift_ustatus (s :: Sstatus) (u :: Ustatus) = (
+ (let s = (update_Sstatus_UPIE s ((get_Ustatus_UPIE u :: 1 Word.word))) in
+ update_Sstatus_UIE s ((get_Ustatus_UIE u :: 1 Word.word))))"
+ for s :: " Sstatus "
+ and u :: " Ustatus "
+
+
+\<comment> \<open>\<open>val legalize_ustatus : Mstatus -> mword ty32 -> M Mstatus\<close>\<close>
+
+definition legalize_ustatus :: " Mstatus \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_ustatus (m :: Mstatus) (v :: xlenbits) = (
+ (let u = (Mk_Ustatus v) in
+ (let s = (lower_mstatus m) in
+ (let s = (lift_ustatus s u) in
+ lift_sstatus m s))))"
+ for m :: " Mstatus "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Uinterrupts : mword ty32 -> Uinterrupts\<close>\<close>
+
+definition Mk_Uinterrupts :: "(32)Word.word \<Rightarrow> Uinterrupts " where
+ " Mk_Uinterrupts v = (
+ (| Uinterrupts_Uinterrupts_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Uinterrupts_bits : Uinterrupts -> mword ty32\<close>\<close>
+
+definition get_Uinterrupts_bits :: " Uinterrupts \<Rightarrow>(32)Word.word " where
+ " get_Uinterrupts_bits v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Uinterrupts_bits : register_ref regstate register_value Uinterrupts -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Uinterrupts_bits :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_bits : Uinterrupts -> mword ty32 -> Uinterrupts\<close>\<close>
+
+definition update_Uinterrupts_bits :: " Uinterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_bits v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(32)Word.word "
+
+
+definition get_Uinterrupts_UEI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_UEI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_UEI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_UEI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_UEI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Uinterrupts_UTI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_UTI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_UTI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_UTI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_UTI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Uinterrupts_USI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_USI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_USI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_USI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_USI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_sip : Sinterrupts -> Sinterrupts -> Uinterrupts\<close>\<close>
+
+definition lower_sip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts " where
+ " lower_sip (s :: Sinterrupts) (d :: Sinterrupts) = (
+ (let (u :: Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s :: 1 Word.word)) ((get_Sinterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s :: 1 Word.word)) ((get_Sinterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s :: 1 Word.word)) ((get_Sinterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word))))))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val lower_sie : Sinterrupts -> Sinterrupts -> Uinterrupts\<close>\<close>
+
+definition lower_sie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts " where
+ " lower_sie (s :: Sinterrupts) (d :: Sinterrupts) = (
+ (let (u :: Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s :: 1 Word.word)) ((get_Sinterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s :: 1 Word.word)) ((get_Sinterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s :: 1 Word.word)) ((get_Sinterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word))))))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val lift_uip : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts\<close>\<close>
+
+definition lift_uip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts \<Rightarrow> Sinterrupts " where
+ " lift_uip (o1 :: Sinterrupts) (d :: Sinterrupts) (u :: Uinterrupts) = (
+ (let (s :: Sinterrupts) = o1 in
+ if (((((get_Sinterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u :: 1 Word.word))
+ else s))"
+ for o1 :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and u :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_uip : Sinterrupts -> Sinterrupts -> mword ty32 -> Sinterrupts\<close>\<close>
+
+definition legalize_uip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Sinterrupts " where
+ " legalize_uip (s :: Sinterrupts) (d :: Sinterrupts) (v :: xlenbits) = (
+ lift_uip s d ((Mk_Uinterrupts v)))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val lift_uie : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts\<close>\<close>
+
+definition lift_uie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts \<Rightarrow> Sinterrupts " where
+ " lift_uie (o1 :: Sinterrupts) (d :: Sinterrupts) (u :: Uinterrupts) = (
+ (let (s :: Sinterrupts) = o1 in
+ (let s =
+ (if (((((get_Sinterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_UEI s ((get_Uinterrupts_UEI u :: 1 Word.word))
+ else s) in
+ (let s =
+ (if (((((get_Sinterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_UTI s ((get_Uinterrupts_UTI u :: 1 Word.word))
+ else s) in
+ if (((((get_Sinterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u :: 1 Word.word))
+ else s))))"
+ for o1 :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and u :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_uie : Sinterrupts -> Sinterrupts -> mword ty32 -> Sinterrupts\<close>\<close>
+
+definition legalize_uie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow>(32)Word.word \<Rightarrow> Sinterrupts " where
+ " legalize_uie (s :: Sinterrupts) (d :: Sinterrupts) (v :: xlenbits) = (
+ lift_uie s d ((Mk_Uinterrupts v)))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val handle_trap_extension : Privilege -> mword ty32 -> maybe unit -> unit\<close>\<close>
+
+definition handle_trap_extension :: " Privilege \<Rightarrow>(32)Word.word \<Rightarrow>(unit)option \<Rightarrow> unit " where
+ " handle_trap_extension (p :: Privilege) (pc :: xlenbits) (u :: unit option) = ( () )"
+ for p :: " Privilege "
+ and pc :: "(32)Word.word "
+ and u :: "(unit)option "
+
+
+\<comment> \<open>\<open>val prepare_trap_vector : Privilege -> Mcause -> M (mword ty32)\<close>\<close>
+
+definition prepare_trap_vector :: " Privilege \<Rightarrow> Mcause \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " prepare_trap_vector (p :: Privilege) (cause :: Mcause) = (
+ (case p of
+ Machine => read_reg mtvec_ref
+ | Supervisor => read_reg stvec_ref
+ | User => read_reg utvec_ref
+ ) \<bind> (\<lambda> (tvec :: Mtvec) .
+ (case ((tvec_addr tvec cause :: ( 32 Word.word)option)) of
+ Some (epc) => return epc
+ | None => (internal_error (''Invalid tvec mode'') :: ( 32 Word.word) M)
+ )))"
+ for p :: " Privilege "
+ and cause :: " Mcause "
+
+
+\<comment> \<open>\<open>val get_xret_target : Privilege -> M (mword ty32)\<close>\<close>
+
+fun get_xret_target :: " Privilege \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_xret_target Machine = ( (read_reg mepc_ref :: ( 32 Word.word) M))"
+|" get_xret_target Supervisor = ( (read_reg sepc_ref :: ( 32 Word.word) M))"
+|" get_xret_target User = ( (read_reg uepc_ref :: ( 32 Word.word) M))"
+
+
+\<comment> \<open>\<open>val set_xret_target : Privilege -> mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition set_xret_target :: " Privilege \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " set_xret_target p value1 = (
+ (legalize_xepc value1 :: ( 32 Word.word) M) \<bind> (\<lambda> target .
+ (case p of
+ Machine => write_reg mepc_ref target
+ | Supervisor => write_reg sepc_ref target
+ | User => write_reg uepc_ref target
+ ) \<then>
+ return target))"
+ for p :: " Privilege "
+ and value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val prepare_xret_target : Privilege -> M (mword ty32)\<close>\<close>
+
+definition prepare_xret_target :: " Privilege \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " prepare_xret_target p = ( (get_xret_target p :: ( 32 Word.word) M))"
+ for p :: " Privilege "
+
+
+\<comment> \<open>\<open>val get_mtvec : unit -> M (mword ty32)\<close>\<close>
+
+definition get_mtvec :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_mtvec _ = (
+ read_reg mtvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 32 Word.word))))"
+
+
+\<comment> \<open>\<open>val get_stvec : unit -> M (mword ty32)\<close>\<close>
+
+definition get_stvec :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_stvec _ = (
+ read_reg stvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 32 Word.word))))"
+
+
+\<comment> \<open>\<open>val get_utvec : unit -> M (mword ty32)\<close>\<close>
+
+definition get_utvec :: " unit \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " get_utvec _ = (
+ read_reg utvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 32 Word.word))))"
+
+
+\<comment> \<open>\<open>val set_mtvec : mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition set_mtvec :: "(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " set_mtvec value1 = (
+ read_reg mtvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg mtvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg mtvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 32 Word.word)))))"
+ for value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val set_stvec : mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition set_stvec :: "(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " set_stvec value1 = (
+ read_reg stvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg stvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg stvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 32 Word.word)))))"
+ for value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val set_utvec : mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition set_utvec :: "(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " set_utvec value1 = (
+ read_reg utvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg utvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg utvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 32 Word.word)))))"
+ for value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val is_NExt_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition is_NExt_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " is_NExt_CSR_defined (csr :: 12 bits) (p :: Privilege) = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else return False))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val read_NExt_CSR : mword ty12 -> M (maybe (mword ty32))\<close>\<close>
+
+definition read_NExt_CSR :: "(12)Word.word \<Rightarrow>((register_value),(((32)Word.word)option),(exception))monad " where
+ " read_NExt_CSR csr = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ return (Some ((get_Ustatus_bits ((lower_sstatus ((lower_mstatus w__0)))) :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__2 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__3 :: Sinterrupts) .
+ return (Some ((get_Uinterrupts_bits ((lower_sie ((lower_mie w__1 w__2)) w__3)) :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_utvec () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . return (Some w__4))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg uscratch_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . return (Some w__5))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target User :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) .
+ return (Some ((and_vec w__6 w__7 :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg ucause_ref \<bind> (\<lambda> (w__8 :: Mcause) .
+ return (Some ((get_Mcause_bits w__8 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg utval_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . return (Some w__9))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__10 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__11 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__12 :: Sinterrupts) .
+ return (Some ((get_Uinterrupts_bits ((lower_sip ((lower_mip w__10 w__11)) w__12))
+ :: 32 Word.word))))))
+ else return None))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val write_NExt_CSR : mword ty12 -> mword ty32 -> M bool\<close>\<close>
+
+definition write_NExt_CSR :: "(12)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " write_NExt_CSR (csr :: csreg) (value1 :: xlenbits) = (
+ (let b__0 = csr in
+ (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ legalize_ustatus w__0 value1 \<bind> (\<lambda> (w__1 :: Mstatus) .
+ (write_reg mstatus_ref w__1 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__2 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__3 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__4 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__5 :: Sinterrupts) .
+ (let sie = (legalize_uie ((lower_mie w__3 w__4)) w__5 value1) in
+ read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) .
+ lift_sie w__6 w__7 sie \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ (write_reg mie_ref w__8 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__9 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__9 :: 32 Word.word)))))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_utvec value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . return (Some w__10))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg uscratch_ref value1 \<then>
+ (read_reg uscratch_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__11 :: 32 Word.word) . return (Some w__11))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target User value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) .
+ return (Some w__12))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits ucause_ref value1 \<then>
+ read_reg ucause_ref) \<bind> (\<lambda> (w__13 :: Mcause) .
+ return (Some ((get_Mcause_bits w__13 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg utval_ref value1 \<then>
+ (read_reg utval_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 Word.word) . return (Some w__14))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__15 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) .
+ (let sip = (legalize_uip ((lower_mip w__15 w__16)) w__17 value1) in
+ read_reg mip_ref \<bind> (\<lambda> (w__18 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__19 :: Minterrupts) .
+ lift_sip w__18 w__19 sip \<bind> (\<lambda> (w__20 :: Minterrupts) .
+ (write_reg mip_ref w__20 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__21 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__21 :: 32 Word.word)))))))))))
+ else return None) \<bind> (\<lambda> (res :: xlenbits option) .
+ return ((case res of
+ Some (v) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr))
+ (((@) ('' <- '')
+ (((@) ((string_of_bits v))
+ (((@) ('' (input: '') (((@) ((string_of_bits value1)) ('')'')))))))))))))
+ else () ) in
+ True)
+ | None => False
+ )))))"
+ for csr :: "(12)Word.word "
+ and value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val ext_is_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition ext_is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " ext_is_CSR_defined (csr :: csreg) (p :: Privilege) = ( is_NExt_CSR_defined csr p )"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val ext_read_CSR : mword ty12 -> M (maybe (mword ty32))\<close>\<close>
+
+definition ext_read_CSR :: "(12)Word.word \<Rightarrow>((register_value),(((32)Word.word)option),(exception))monad " where
+ " ext_read_CSR csr = ( (read_NExt_CSR csr :: ( ( 32 Word.word)option) M))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val ext_write_CSR : mword ty12 -> mword ty32 -> M bool\<close>\<close>
+
+definition ext_write_CSR :: "(12)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " ext_write_CSR (csr :: csreg) (value1 :: xlenbits) = ( write_NExt_CSR csr value1 )"
+ for csr :: "(12)Word.word "
+ and value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val csrAccess : mword ty12 -> mword ty2\<close>\<close>
+
+definition csrAccess :: "(12)Word.word \<Rightarrow>(2)Word.word " where
+ " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csrPriv : mword ty12 -> mword ty2\<close>\<close>
+
+definition csrPriv :: "(12)Word.word \<Rightarrow>(2)Word.word " where
+ " csrPriv csr = ( (subrange_vec_dec csr (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val is_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " is_CSR_defined (csr :: csreg) (p :: Privilege) = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else ext_is_CSR_defined csr p))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool\<close>\<close>
+
+definition check_CSR_access :: "(2)Word.word \<Rightarrow>(2)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool " where
+ " check_CSR_access csrrw csrpr p isWrite = (
+ (((\<not> ((((((isWrite = True))) \<and> (((csrrw = (vec_of_bits [B1,B1] :: 2 Word.word))))))))) \<and> ((zopz0zKzJ_u ((privLevel_to_bits p :: 2 Word.word)) csrpr))))"
+ for csrrw :: "(2)Word.word "
+ and csrpr :: "(2)Word.word "
+ and p :: " Privilege "
+ and isWrite :: " bool "
+
+
+\<comment> \<open>\<open>val check_TVM_SATP : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition check_TVM_SATP :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_TVM_SATP (csr :: csreg) (p :: Privilege) = (
+ and_boolM
+ (return (((csr = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))))
+ (and_boolM
+ (return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ return (((((get_Mstatus_TVM w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> (w__2 ::
+ bool) .
+ return ((\<not> w__2))))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_Counteren : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition check_Counteren :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_Counteren (csr :: csreg) (p :: Privilege) = (
+ (case (csr, p) of
+ (b__0, Supervisor) =>
+ if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__0 :: Counteren) .
+ return (((((get_Counteren_CY w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__1 :: Counteren) .
+ return (((((get_Counteren_TM w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__2 :: Counteren) .
+ return (((((get_Counteren_IR w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else
+ return ((case (b__0, Supervisor) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True
+ ))
+ | (b__3, User) =>
+ if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__6 :: Counteren) .
+ return (((((get_Counteren_CY w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__7 :: bool) . return ((\<not> w__7))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__8 :: Counteren) .
+ return (((((get_Counteren_CY w__8 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__11 :: Counteren) .
+ return (((((get_Counteren_TM w__11 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__12 :: bool) . return ((\<not> w__12))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__13 :: Counteren) .
+ return (((((get_Counteren_TM w__13 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__16 :: Counteren) .
+ return (((((get_Counteren_IR w__16 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__17 :: bool) . return ((\<not> w__17))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__18 :: Counteren) .
+ return (((((get_Counteren_IR w__18 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else
+ return ((case (b__3, User) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True
+ ))
+ | (_, _) =>
+ return (if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True)
+ ))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_CSR : mword ty12 -> Privilege -> bool -> M bool\<close>\<close>
+
+definition check_CSR :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_CSR (csr :: csreg) (p :: Privilege) (isWrite :: bool) = (
+ and_boolM ((is_CSR_defined csr p))
+ (and_boolM
+ (return ((check_CSR_access ((csrAccess csr :: 2 Word.word)) ((csrPriv csr :: 2 Word.word)) p
+ isWrite))) (and_boolM ((check_TVM_SATP csr p)) ((check_Counteren csr p)))))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+ and isWrite :: " bool "
+
+
+\<comment> \<open>\<open>val exception_delegatee : ExceptionType -> Privilege -> M Privilege\<close>\<close>
+
+definition exception_delegatee :: " ExceptionType \<Rightarrow> Privilege \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " exception_delegatee (e :: ExceptionType) (p :: Privilege) = (
+ (let idx = (num_of_ExceptionType e) in
+ read_reg medeleg_ref \<bind> (\<lambda> (w__0 :: Medeleg) .
+ (let super = (access_vec_dec ((get_Medeleg_bits w__0 :: 32 Word.word)) idx) in
+ haveSupMode () \<bind> (\<lambda> (w__1 :: bool) .
+ (if w__1 then
+ and_boolM (return ((bit_to_bool super)))
+ (and_boolM ((haveNExt () ))
+ (read_reg sedeleg_ref \<bind> (\<lambda> (w__3 :: Sedeleg) .
+ return ((bit_to_bool ((access_vec_dec ((get_Sedeleg_bits w__3 :: 32 Word.word)) idx)))))))
+ else and_boolM (return ((bit_to_bool super))) ((haveNExt () ))) \<bind> (\<lambda> user .
+ and_boolM ((haveUsrMode () )) (return user) \<bind> (\<lambda> w__9 .
+ (if w__9 then return User
+ else
+ and_boolM ((haveSupMode () )) (return ((bit_to_bool super))) \<bind> (\<lambda> (w__11 :: bool) .
+ return (if w__11 then Supervisor
+ else Machine))) \<bind> (\<lambda> deleg .
+ return (if ((zopz0zI_u ((privLevel_to_bits deleg :: 2 Word.word))
+ ((privLevel_to_bits p :: 2 Word.word)))) then
+ p
+ else deleg)))))))))"
+ for e :: " ExceptionType "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val findPendingInterrupt : mword ty32 -> maybe InterruptType\<close>\<close>
+
+definition findPendingInterrupt :: "(32)Word.word \<Rightarrow>(InterruptType)option " where
+ " findPendingInterrupt ip = (
+ (let ip = (Mk_Minterrupts ip) in
+ if (((((get_Minterrupts_MEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ Some I_M_External
+ else if (((((get_Minterrupts_MSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_M_Software
+ else if (((((get_Minterrupts_MTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_M_Timer
+ else if (((((get_Minterrupts_SEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_External
+ else if (((((get_Minterrupts_SSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_Software
+ else if (((((get_Minterrupts_STI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_Timer
+ else if (((((get_Minterrupts_UEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_External
+ else if (((((get_Minterrupts_USI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_Software
+ else if (((((get_Minterrupts_UTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_Timer
+ else None))"
+ for ip :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val processPending : Minterrupts -> Minterrupts -> mword ty32 -> bool -> interrupt_set\<close>\<close>
+
+definition processPending :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(32)Word.word \<Rightarrow> bool \<Rightarrow> interrupt_set " where
+ " processPending (xip :: Minterrupts) (xie :: Minterrupts) (xideleg :: xlenbits) (priv_enabled :: bool) = (
+ (let effective_pend =
+ ((and_vec ((get_Minterrupts_bits xip :: 32 Word.word))
+ ((and_vec ((get_Minterrupts_bits xie :: 32 Word.word)) ((not_vec xideleg :: 32 Word.word))
+ :: 32 Word.word))
+ :: 32 Word.word)) in
+ (let effective_delg = ((and_vec ((get_Minterrupts_bits xip :: 32 Word.word)) xideleg :: 32 Word.word)) in
+ if (((priv_enabled \<and> (((effective_pend \<noteq> ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))))))))
+ then
+ Ints_Pending effective_pend
+ else if (((effective_delg \<noteq> ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)))))
+ then
+ Ints_Delegated effective_delg
+ else Ints_Empty () )))"
+ for xip :: " Minterrupts "
+ and xie :: " Minterrupts "
+ and xideleg :: "(32)Word.word "
+ and priv_enabled :: " bool "
+
+
+\<comment> \<open>\<open>val getPendingSet : Privilege -> M (maybe ((mword ty32 * Privilege)))\<close>\<close>
+
+definition getPendingSet :: " Privilege \<Rightarrow>((register_value),(((32)Word.word*Privilege)option),(exception))monad " where
+ " getPendingSet priv = (
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ (assert_exp w__0 (''no user mode: M/U or M/S/U system required'') \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__2 :: Minterrupts) .
+ (let effective_pending =
+ ((and_vec ((get_Minterrupts_bits w__1 :: 32 Word.word))
+ ((get_Minterrupts_bits w__2 :: 32 Word.word))
+ :: 32 Word.word)) in
+ if (((effective_pending = ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)))))
+ then
+ return None
+ else
+ or_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) \<noteq> ((privLevel_to_bits Machine :: 2 Word.word))))))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) .
+ return (((((get_Mstatus_MIE w__3 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> mIE .
+ and_boolM ((haveSupMode () ))
+ (or_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__6 :: Mstatus) .
+ return (((((get_Mstatus_SIE w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))) \<bind> (\<lambda> sIE .
+ and_boolM ((haveNExt () ))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) .
+ return (((((get_Mstatus_UIE w__10 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> uIE .
+ read_reg mip_ref \<bind> (\<lambda> (w__12 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__13 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__14 :: Minterrupts) .
+ (case ((processPending w__12 w__13 ((get_Minterrupts_bits w__14 :: 32 Word.word)) mIE)) of
+ Ints_Empty (_) => return None
+ | Ints_Pending (p) =>
+ (let r = (p, Machine) in
+ return (Some r))
+ | Ints_Delegated (d) =>
+ haveSupMode () \<bind> (\<lambda> (w__15 :: bool) .
+ if ((\<not> w__15)) then
+ return (if uIE then
+ (let r = (d, User) in
+ Some r)
+ else None)
+ else
+ read_reg mie_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) .
+ return ((case ((processPending ((Mk_Minterrupts d)) w__16
+ ((get_Sinterrupts_bits w__17 :: 32 Word.word)) sIE)) of
+ Ints_Empty (_) => None
+ | Ints_Pending (p) =>
+ (let r = (p, Supervisor) in
+ Some r)
+ | Ints_Delegated (d) =>
+ if uIE then
+ (let r = (d, User) in
+ Some r)
+ else None
+ )))))
+ ))))))))))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val dispatchInterrupt : Privilege -> M (maybe ((InterruptType * Privilege)))\<close>\<close>
+
+definition dispatchInterrupt :: " Privilege \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad " where
+ " dispatchInterrupt priv = (
+ or_boolM (haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0))))
+ (and_boolM (haveSupMode () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1))))
+ (haveNExt () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (assert_exp (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) (''invalid current privilege'') \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__5 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) .
+ (let enabled_pending =
+ ((and_vec ((get_Minterrupts_bits w__5 :: 32 Word.word))
+ ((get_Minterrupts_bits w__6 :: 32 Word.word))
+ :: 32 Word.word)) in
+ return ((case ((findPendingInterrupt enabled_pending)) of
+ Some (i) =>
+ (let r = (i, Machine) in
+ Some r)
+ | None => None
+ )))))
+ else
+ (getPendingSet priv :: ( (( 32 Word.word * Privilege))option) M) \<bind> (\<lambda> (w__7 ::
+ (( 32 Word.word * Privilege))option) .
+ return ((case w__7 of
+ None => None
+ | Some ((ip, p)) =>
+ (case ((findPendingInterrupt ip)) of
+ None => None
+ | Some (i) =>
+ (let r = (i, p) in
+ Some r)
+ )
+ )))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val tval : maybe (mword ty32) -> mword ty32\<close>\<close>
+
+fun tval :: "((32)Word.word)option \<Rightarrow>(32)Word.word " where
+ " tval (Some (e)) = ( e )"
+ for e :: "(32)Word.word "
+|" tval None = ( (EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))"
+
+
+\<comment> \<open>\<open>val rvfi_trap : unit -> unit\<close>\<close>
+
+definition rvfi_trap :: " unit \<Rightarrow> unit " where
+ " rvfi_trap _ = ( () )"
+
+
+\<comment> \<open>\<open>val trap_handler : Privilege -> bool -> mword ty8 -> mword ty32 -> maybe (mword ty32) -> maybe unit -> M (mword ty32)\<close>\<close>
+
+definition trap_handler :: " Privilege \<Rightarrow> bool \<Rightarrow>(8)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(xlenbits)option \<Rightarrow>(ext_exception)option \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " trap_handler (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info ::
+ xlenbits option) (ext :: ext_exception option) = (
+ (let (_ :: unit) = (rvfi_trap () ) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''handling '')
+ (((@) (if intr then (''int#'') else (''exc#''))
+ (((@) ((string_of_bits c))
+ (((@) ('' at priv '')
+ (((@) ((privLevel_to_str del_priv))
+ (((@) ('' with tval '')
+ ((string_of_bits ((tval info :: 32 Word.word))))))))))))))))
+ else () ) in
+ (let (_ :: unit) = (cancel_reservation () ) in
+ (case del_priv of
+ Machine =>
+ ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr :: 1 Word.word)) \<then>
+ set_Mcause_Cause mcause_ref ((EXTZ (( 31 :: int)::ii) c :: 31 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__0 :: Mstatus) .
+ ((set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 :: 1 Word.word)) \<then>
+ set_Mstatus_MIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__1 :: Privilege) .
+ (((set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 :: 2 Word.word)) \<then>
+ write_reg mtval_ref ((tval info :: 32 Word.word))) \<then>
+ write_reg mepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__2 :: 32 Word.word)))))))))
+ else return () ) \<then>
+ read_reg mcause_ref) \<bind> (\<lambda> (w__3 :: Mcause) .
+ (prepare_trap_vector del_priv w__3 :: ( 32 Word.word) M))))))
+ | Supervisor =>
+ haveSupMode () \<bind> (\<lambda> (w__5 :: bool) .
+ (((assert_exp w__5 (''no supervisor mode present for delegation'') \<then>
+ set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr :: 1 Word.word))) \<then>
+ set_Mcause_Cause scause_ref ((EXTZ (( 31 :: int)::ii) c :: 31 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) .
+ ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 :: 1 Word.word)) \<then>
+ set_Mstatus_SIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) .
+ (case w__7 of
+ User => return ((bool_to_bits False :: 1 Word.word))
+ | Supervisor => return ((bool_to_bits True :: 1 Word.word))
+ | Machine => (internal_error (''invalid privilege for s-mode trap'') :: ( 1 Word.word) M)
+ ) \<bind> (\<lambda> (w__9 :: 1 Word.word) .
+ (((set_Mstatus_SPP mstatus_ref w__9 \<then>
+ write_reg stval_ref ((tval info :: 32 Word.word))) \<then>
+ write_reg sepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__10 :: 32 Word.word)))))))))
+ else return () ) \<then>
+ read_reg scause_ref) \<bind> (\<lambda> (w__11 :: Mcause) .
+ (prepare_trap_vector del_priv w__11 :: ( 32 Word.word) M))))))))
+ | User =>
+ haveUsrMode () \<bind> (\<lambda> (w__13 :: bool) .
+ (((assert_exp w__13 (''no user mode present for delegation'') \<then>
+ set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr :: 1 Word.word))) \<then>
+ set_Mcause_Cause ucause_ref ((EXTZ (( 31 :: int)::ii) c :: 31 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__14 :: Mstatus) .
+ ((((set_Mstatus_UPIE mstatus_ref ((get_Mstatus_UIE w__14 :: 1 Word.word)) \<then>
+ set_Mstatus_UIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ write_reg utval_ref ((tval info :: 32 Word.word))) \<then>
+ write_reg uepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__15 :: 32 Word.word)))))))))
+ else return () ) \<then>
+ read_reg ucause_ref) \<bind> (\<lambda> (w__16 :: Mcause) .
+ (prepare_trap_vector del_priv w__16 :: ( 32 Word.word) M))))))
+ )))))"
+ for del_priv :: " Privilege "
+ and intr :: " bool "
+ and c :: "(8)Word.word "
+ and pc :: "(32)Word.word "
+ and info :: "(xlenbits)option "
+ and ext :: "(ext_exception)option "
+
+
+\<comment> \<open>\<open>val exception_handler : Privilege -> ctl_result -> mword ty32 -> M (mword ty32)\<close>\<close>
+
+definition exception_handler :: " Privilege \<Rightarrow> ctl_result \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " exception_handler (cur_priv :: Privilege) (ctl :: ctl_result) (pc :: xlenbits) = (
+ (case (cur_priv, ctl) of
+ (_, CTL_TRAP (e)) =>
+ exception_delegatee(sync_exception_trap e) cur_priv \<bind> (\<lambda> del_priv .
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''trapping from '')
+ (((@) ((privLevel_to_str cur_priv))
+ (((@) ('' to '')
+ (((@) ((privLevel_to_str del_priv))
+ (((@) ('' to handle '')
+ ((exceptionType_to_str(sync_exception_trap e)))))))))))))
+ else () ) in
+ (trap_handler del_priv False ((exceptionType_to_bits(sync_exception_trap e) :: 8 Word.word)) pc(sync_exception_excinfo
+ e)(sync_exception_ext_exception e)
+ :: ( 32 Word.word) M)))
+ | (_, CTL_MRET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ ((set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 :: 1 Word.word)) \<then>
+ set_Mstatus_MPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word)) \<bind> (\<lambda> (w__3 :: Privilege) .
+ (write_reg cur_privilege_ref w__3 \<then>
+ haveUsrMode () ) \<bind> (\<lambda> (w__4 :: bool) .
+ ((set_Mstatus_MPP mstatus_ref
+ ((privLevel_to_bits (if w__4 then User else Machine) :: 2 Word.word)) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__5 :: 32 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__6 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__6)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target Machine :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) .
+ return ((and_vec w__7 w__8 :: 32 Word.word)))))))))))
+ | (_, CTL_SRET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__9 :: Mstatus) .
+ ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__9 :: 1 Word.word)) \<then>
+ set_Mstatus_SPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__10 :: Mstatus) .
+ (((write_reg
+ cur_privilege_ref
+ (if (((((get_Mstatus_SPP w__10 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Supervisor
+ else User) \<then>
+ set_Mstatus_SPP mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__11 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__11 :: 32 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__12 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__12)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target Supervisor :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 Word.word) .
+ return ((and_vec w__13 w__14 :: 32 Word.word)))))))))
+ | (_, CTL_URET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) .
+ ((((set_Mstatus_UIE mstatus_ref ((get_Mstatus_UPIE w__15 :: 1 Word.word)) \<then>
+ set_Mstatus_UPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ write_reg cur_privilege_ref User) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__16 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__16 :: 32 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__17 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__17)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target User :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__19 :: 32 Word.word) .
+ return ((and_vec w__18 w__19 :: 32 Word.word))))))))
+ ))"
+ for cur_priv :: " Privilege "
+ and ctl :: " ctl_result "
+ and pc :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val handle_mem_exception : mword ty32 -> ExceptionType -> M unit\<close>\<close>
+
+definition handle_mem_exception :: "(32)Word.word \<Rightarrow> ExceptionType \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_mem_exception (addr :: xlenbits) (e :: ExceptionType) = (
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap = e,
+ sync_exception_excinfo = (Some addr),
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (exception_handler w__0 (CTL_TRAP t) w__1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ set_next_pc w__2)))))"
+ for addr :: "(32)Word.word "
+ and e :: " ExceptionType "
+
+
+\<comment> \<open>\<open>val handle_interrupt : InterruptType -> Privilege -> M unit\<close>\<close>
+
+definition handle_interrupt :: " InterruptType \<Rightarrow> Privilege \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_interrupt (i :: InterruptType) (del_priv :: Privilege) = (
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (trap_handler del_priv True ((interruptType_to_bits i :: 8 Word.word)) w__0 None None
+ :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ set_next_pc w__1)))"
+ for i :: " InterruptType "
+ and del_priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val init_sys : unit -> M unit\<close>\<close>
+
+definition init_sys :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_sys _ = (
+ (((((((((write_reg cur_privilege_ref Machine \<then>
+ write_reg mhartid_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Misa_MXL misa_ref ((arch_to_bits RV32 :: 2 Word.word))) \<then>
+ set_Misa_A misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_C misa_ref ((bool_to_bits ((sys_enable_rvc () )) :: 1 Word.word))) \<then>
+ set_Misa_I misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_M misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_U misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_S misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__0 :: Mstatus) .
+ read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) .
+ (write_reg mstatus_ref ((set_mstatus_SXL w__0 ((get_Misa_MXL w__1 :: 2 Word.word)))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ read_reg misa_ref \<bind> (\<lambda> (w__3 :: Misa) .
+ ((((((((((((((((write_reg mstatus_ref ((set_mstatus_UXL w__2 ((get_Misa_MXL w__3 :: 2 Word.word)))) \<then>
+ set_Mstatus_SD mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ set_Minterrupts_bits mip_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Minterrupts_bits mie_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Minterrupts_bits mideleg_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Medeleg_bits medeleg_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Mtvec_bits mtvec_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ set_Mcause_bits mcause_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg mepc_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg mtval_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg mscratch_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg mcycle_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mtime_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Counteren_bits mcounteren_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg minstret_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg minstret_written_ref False) \<then>
+ init_pmp () ) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ (((@) ((string_of_bits ((get_Mstatus_bits w__4 :: 32 Word.word))))
+ (((@) ('' (input: '')
+ (((@)
+ ((string_of_bits
+ ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))))
+ ('')''))))))))))))
+ else return () ))))))"
+
+
+\<comment> \<open>\<open>val elf_tohost : unit -> ii\<close>\<close>
+
+\<comment> \<open>\<open>val elf_entry : unit -> ii\<close>\<close>
+
+
+
+\<comment> \<open>\<open>val phys_mem_segments : unit -> list ((mword ty32 * mword ty32))\<close>\<close>
+
+definition phys_mem_segments :: " unit \<Rightarrow>((32)Word.word*(32)Word.word)list " where
+ " phys_mem_segments _ = (
+ ((plat_rom_base () :: 32 Word.word), (plat_rom_size () :: 32 Word.word)) #
+ (((plat_ram_base () :: 32 Word.word), (plat_ram_size () :: 32 Word.word)) # []))"
+
+
+\<comment> \<open>\<open>val within_phys_mem : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_phys_mem :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_phys_mem (addr :: xlenbits) (width :: int) = (
+ (let addr_int = (Word.uint addr) in
+ (let ram_base_int = (Word.uint ((plat_ram_base () :: 32 Word.word))) in
+ (let rom_base_int = (Word.uint ((plat_rom_base () :: 32 Word.word))) in
+ (let ram_size_int = (Word.uint ((plat_ram_size () :: 32 Word.word))) in
+ (let rom_size_int = (Word.uint ((plat_rom_size () :: 32 Word.word))) in
+ if (((((ram_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le> ((ram_base_int + ram_size_int)))))))
+ then
+ True
+ else if (((((rom_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le>
+ ((rom_base_int + rom_size_int))))))) then
+ True
+ else
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) (''within_phys_mem: '')
+ (((@) ((string_of_bits addr)) ('' not within phys-mem:'')))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_rom_base: '') ((string_of_bits ((plat_rom_base () :: 32 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_rom_size: '') ((string_of_bits ((plat_rom_size () :: 32 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_ram_base: '') ((string_of_bits ((plat_ram_base () :: 32 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_ram_size: '') ((string_of_bits ((plat_ram_size () :: 32 Word.word))))))) in
+ False)))))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_clint : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_clint :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_clint (addr :: xlenbits) (width :: int) = (
+ (let addr_int = (Word.uint addr) in
+ (let clint_base_int = (Word.uint ((plat_clint_base () :: 32 Word.word))) in
+ (let clint_size_int = (Word.uint ((plat_clint_size () :: 32 Word.word))) in
+ (((clint_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le> ((clint_base_int + clint_size_int)))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_htif_writable : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_htif_writable :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_htif_writable (addr :: xlenbits) (width :: int) = (
+ ((((((plat_htif_tohost () :: 32 Word.word)) = addr))) \<or> ((((((((add_vec_int ((plat_htif_tohost () :: 32 Word.word)) (( 4 :: int)::ii) :: 32 Word.word)) = addr))) \<and> (((width = (( 4 :: int)::ii)))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_htif_readable : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_htif_readable :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_htif_readable (addr :: xlenbits) (width :: int) = (
+ ((((((plat_htif_tohost () :: 32 Word.word)) = addr))) \<or> ((((((((add_vec_int ((plat_htif_tohost () :: 32 Word.word)) (( 4 :: int)::ii) :: 32 Word.word)) = addr))) \<and> (((width = (( 4 :: int)::ii)))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+definition MSIP_BASE :: "(32)Word.word " where
+ " MSIP_BASE = (
+ (EXTZ (( 32 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 20 Word.word)
+ :: 32 Word.word))"
+
+
+definition MTIMECMP_BASE :: "(32)Word.word " where
+ " MTIMECMP_BASE = (
+ (EXTZ (( 32 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 20 Word.word)
+ :: 32 Word.word))"
+
+
+definition MTIMECMP_BASE_HI :: "(32)Word.word " where
+ " MTIMECMP_BASE_HI = (
+ (EXTZ (( 32 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 20 Word.word)
+ :: 32 Word.word))"
+
+
+definition MTIME_BASE :: "(32)Word.word " where
+ " MTIME_BASE = (
+ (EXTZ (( 32 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0] :: 20 Word.word)
+ :: 32 Word.word))"
+
+
+definition MTIME_BASE_HI :: "(32)Word.word " where
+ " MTIME_BASE_HI = (
+ (EXTZ (( 32 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0] :: 20 Word.word)
+ :: 32 Word.word))"
+
+
+\<comment> \<open>\<open>val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition clint_load :: "(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " clint_load addr width = (
+ (let addr = ((sub_vec addr ((plat_clint_base () :: 32 Word.word)) :: 32 Word.word)) in
+ if ((((((addr = MSIP_BASE))) \<and> ((((((((id0 width)) = (( 8 :: int)::ii)))) \<or> (((((id0 width)) = (( 4 :: int)::ii)))))))))) then
+ ((if ((get_config_print_platform () )) then
+ read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits ((get_Minterrupts_MSI w__0 :: 1 Word.word)))))))))))))
+ else return () ) \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ return (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 :: 1 Word.word))
+ (((( 8 :: int)::ii) * ((id0 width))))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits
+ ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__3 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint<8>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__4)))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__5 (( 64 :: int)::ii) :: 64 Word.word)) :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint-hi<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits
+ ((subrange_vec_dec w__6 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__7 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__8)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__9 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__9 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__10)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__11 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__11 (( 64 :: int)::ii) :: 64 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__12)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__13 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__13 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['') (((@) ((string_of_bits addr)) (''] -> <not-mapped>'')))))
+ else () ) in
+ return (MemException E_Load_Access_Fault))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val clint_dispatch : unit -> M unit\<close>\<close>
+
+definition clint_dispatch :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " clint_dispatch _ = (
+ (((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg (((@) (''clint::tick mtime <- '') ((string_of_bits w__0)))))))
+ else return () ) \<then>
+ set_Minterrupts_MTI mip_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ if ((zopz0zIzJ_u w__1 w__2)) then
+ (if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return ((print_dbg (((@) ('' clint timer pending at mtime '') ((string_of_bits w__3)))))))
+ else return () ) \<then>
+ set_Minterrupts_MTI mip_ref ((bool_to_bits True :: 1 Word.word))
+ else return () )))"
+
+
+\<comment> \<open>\<open>val clint_store : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition clint_store :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " clint_store addr width data = (
+ (let addr = ((sub_vec addr ((plat_clint_base () :: 32 Word.word)) :: 32 Word.word)) in
+ if ((((((addr = MSIP_BASE))) \<and> ((((((((id0 width)) = (( 8 :: int)::ii)))) \<or> (((((id0 width)) = (( 4 :: int)::ii)))))))))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '')
+ (((@) ((string_of_bits data))
+ (((@) ('' (mip.MSI <- '')
+ (((@)
+ ((string_of_bits
+ ((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word))))
+ ('')'')))))))))))))
+ else () ) in
+ (set_Minterrupts_MSI mip_ref
+ ((bool_to_bits
+ (((((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word))))
+ :: 1 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ (let (data :: 64 Word.word) = ((Word.ucast data :: 64 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<8>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (write_reg mtimecmp_ref ((zero_extend data (( 64 :: int)::ii) :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True)))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (write_reg
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) ((zero_extend data (( 32 :: int)::ii) :: 32 Word.word))
+ :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (write_reg
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__1 (( 63 :: int)::ii) (( 32 :: int)::ii) ((zero_extend data (( 32 :: int)::ii) :: 32 Word.word))
+ :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))))
+ else
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (<unmapped>)'')))))))))
+ else () ) in
+ return (MemException E_SAMO_Access_Fault))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val tick_clock : unit -> M unit\<close>\<close>
+
+definition tick_clock :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_clock _ = (
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word)) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg mtime_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)) \<then> clint_dispatch () )))"
+
+
+\<comment> \<open>\<open>val Mk_htif_cmd : mword ty64 -> htif_cmd\<close>\<close>
+
+definition Mk_htif_cmd :: "(64)Word.word \<Rightarrow> htif_cmd " where
+ " Mk_htif_cmd v = (
+ (| htif_cmd_htif_cmd_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_bits : htif_cmd -> mword ty64\<close>\<close>
+
+definition get_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word " where
+ " get_htif_cmd_bits v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit\<close>\<close>
+
+definition set_htif_cmd_bits :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_bits v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_device : htif_cmd -> mword ty8\<close>\<close>
+
+definition get_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word " where
+ " get_htif_cmd_device v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit\<close>\<close>
+
+definition set_htif_cmd_device :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_device r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 56 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_device v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_cmd : htif_cmd -> mword ty8\<close>\<close>
+
+definition get_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word " where
+ " get_htif_cmd_cmd v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii) :: 8 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit\<close>\<close>
+
+definition set_htif_cmd_cmd :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_cmd r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 55 :: int)::ii) (( 48 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_cmd v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_payload : htif_cmd -> mword ty48\<close>\<close>
+
+definition get_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word " where
+ " get_htif_cmd_payload v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit\<close>\<close>
+
+definition set_htif_cmd_payload :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_payload r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_payload v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val htif_load : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition htif_load :: "(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " htif_load addr width = (
+ (if ((get_config_print_platform () )) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''htif['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__0)))))))))))
+ else return () ) \<then>
+ (if ((((((width = (( 8 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 32 Word.word)))))))) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__1 (( 64 :: int)::ii) :: 64 Word.word)) :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 32 Word.word))))))))
+ then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((add_vec_int ((plat_htif_tohost () :: 32 Word.word)) (( 4 :: int)::ii) :: 32 Word.word))))))))
+ then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__3 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else return (MemException E_Load_Access_Fault)))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val htif_store : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition htif_store :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " htif_store addr width data = (
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif['')
+ (((@) ((string_of_bits addr)) (((@) (''] <- '') ((string_of_bits data))))))))
+ else () ) in
+ ((if (((width = (( 8 :: int)::ii)))) then
+ (let (data :: 64 Word.word) = ((Word.ucast data :: 64 Word.word)) in
+ write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) data :: 64 Word.word)))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 32 Word.word))))))))
+ then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ write_reg htif_tohost_ref ((update_subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) data :: 64 Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((add_vec_int ((plat_htif_tohost () :: 32 Word.word)) (( 4 :: int)::ii) :: 32 Word.word))))))))
+ then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg htif_tohost_ref ((update_subrange_vec_dec w__1 (( 63 :: int)::ii) (( 32 :: int)::ii) data :: 64 Word.word))))
+ else write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) data :: 64 Word.word))) \<then>
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let cmd = (Mk_htif_cmd w__2) in
+ (let b__0 = ((get_htif_cmd_device cmd :: 8 Word.word)) in
+ (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif-syscall-proxy cmd: '')
+ ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))
+ else () ) in
+ if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 0 :: int)::ii)))
+ :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) then
+ write_reg htif_done_ref True \<then>
+ write_reg
+ htif_exit_code_ref
+ ((shiftr ((zero_extend ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 64 :: int)::ii) :: 64 Word.word))
+ (( 1 :: int)::ii)
+ :: 64 Word.word))
+ else return () )
+ else
+ return (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif-term cmd: '')
+ ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))
+ else () ) in
+ (let b__2 = ((get_htif_cmd_cmd cmd :: 8 Word.word)) in
+ if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then ()
+ else if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then
+ plat_term_write
+ ((subrange_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ :: 8 Word.word))
+ else print_endline (((@) (''Unknown term cmd: '') ((string_of_bits b__2))))))
+ else print_endline (((@) (''htif-???? cmd: '') ((string_of_bits data)))))) \<then>
+ return (MemValue True))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val htif_tick : unit -> M unit\<close>\<close>
+
+definition htif_tick :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " htif_tick _ = (
+ (if ((get_config_print_platform () )) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg (((@) (''htif::tick '') ((string_of_bits w__0)))))))
+ else return () ) \<then>
+ write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))"
+
+
+\<comment> \<open>\<open>val within_mmio_readable : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_mmio_readable :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_mmio_readable (addr :: xlenbits) (width :: int) = (
+ (((within_clint addr width)) \<or> (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> ((id0 width)))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_mmio_writable : mword ty32 -> integer -> bool\<close>\<close>
+
+definition within_mmio_writable :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_mmio_writable (addr :: xlenbits) (width :: int) = (
+ (((within_clint addr width)) \<or> (((((within_htif_writable addr width)) \<and> ((((id0 width)) \<le> (( 8 :: int)::ii))))))))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition mmio_read :: "(32)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " mmio_read (addr :: xlenbits) (width :: int) = (
+ if ((within_clint addr width)) then (clint_load addr width )
+ else if (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> ((id0 width))))))) then
+ (htif_load addr width )
+ else return (MemException E_Load_Access_Fault))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val mmio_write : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mmio_write :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mmio_write (addr :: xlenbits) (width :: int) data = (
+ if ((within_clint addr width)) then clint_store addr width data
+ else if (((((within_htif_writable addr width)) \<and> ((((id0 width)) \<le> (( 8 :: int)::ii)))))) then
+ htif_store addr width data
+ else return (MemException E_SAMO_Access_Fault))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val init_platform : unit -> M unit\<close>\<close>
+
+definition init_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_platform _ = (
+ (write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) \<then>
+ write_reg htif_done_ref False) \<then>
+ write_reg htif_exit_code_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))"
+
+
+\<comment> \<open>\<open>val tick_platform : unit -> M unit\<close>\<close>
+
+definition tick_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_platform _ = ( htif_tick () )"
+
+
+\<comment> \<open>\<open>val handle_illegal : unit -> M unit\<close>\<close>
+
+definition handle_illegal :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_illegal _ = (
+ (if ((plat_mtval_has_illegal_inst_bits () )) then
+ (read_reg instbits_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . return (Some w__0))
+ else return None) \<bind> (\<lambda> info .
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap = E_Illegal_Instr,
+ sync_exception_excinfo = info,
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (exception_handler w__1 (CTL_TRAP t) w__2 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ set_next_pc w__3))))))"
+
+
+\<comment> \<open>\<open>val platform_wfi : unit -> M unit\<close>\<close>
+
+definition platform_wfi :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " platform_wfi _ = (
+ (let (_ :: unit) = (cancel_reservation () ) in
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ if ((zopz0zI_u w__0 w__1)) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (write_reg mtime_ref w__2 \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ write_reg mcycle_ref w__3))
+ else return () ))))"
+
+
+\<comment> \<open>\<open>val is_aligned_addr : mword ty32 -> integer -> bool\<close>\<close>
+
+definition is_aligned_addr :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " is_aligned_addr (addr :: xlenbits) (width :: int) = (
+ (((((Word.uint addr)) mod width)) = (( 0 :: int)::ii)))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition phys_mem_read :: " AccessType \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " phys_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ (case (aq, rl, res) of
+ (False, False, False) =>
+ (read_ram Read_plain addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__0))
+ | (True, False, False) =>
+ (read_ram Read_RISCV_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__1 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__1))
+ | (True, True, False) =>
+ (read_ram Read_RISCV_strong_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__2 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__2))
+ | (False, False, True) =>
+ (read_ram Read_RISCV_reserved addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__3 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__3))
+ | (True, False, True) =>
+ (read_ram Read_RISCV_reserved_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__4 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__4))
+ | (True, True, True) =>
+ (read_ram Read_RISCV_reserved_strong_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__5 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__5))
+ | (False, True, False) => return None
+ | (False, True, True) => return None
+ ) \<bind> (\<lambda> w__6 .
+ (let result = w__6 in
+ return ((case (t, result) of
+ (Execute, None) => MemException E_Fetch_Access_Fault
+ | (Read, None) => MemException E_Load_Access_Fault
+ | (_, None) => MemException E_SAMO_Access_Fault
+ | (_, Some (v)) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ (((@) (''mem['')
+ (((@) ((accessType_to_str t))
+ (((@) ('','')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits v))))))))))))
+ else () ) in
+ MemValue v)
+ )))))"
+ for t :: " AccessType "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition checked_mem_read :: " AccessType \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " checked_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ if ((within_mmio_readable addr width)) then (mmio_read addr width )
+ else if ((within_phys_mem addr width)) then (phys_mem_read t addr width aq rl res )
+ else return (MemException E_Load_Access_Fault))"
+ for t :: " AccessType "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val pmp_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition pmp_mem_read :: " AccessType \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " pmp_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ if ((\<not> ((plat_enable_pmp () )))) then (checked_mem_read t addr width aq rl res )
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ effectivePrivilege w__1 w__2 \<bind> (\<lambda> (w__3 :: Privilege) .
+ pmpCheck addr width t w__3 \<bind> (\<lambda> (w__4 :: ExceptionType option) .
+ (case w__4 of
+ None => (checked_mem_read t addr width aq rl res )
+ | Some (e) => return (MemException e)
+ ))))))"
+ for t :: " AccessType "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val rvfi_read : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> MemoryOpResult (mword 'int8_times_n) -> unit\<close>\<close>
+
+definition rvfi_read :: "(32)Word.word \<Rightarrow> int \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> unit " where
+ " rvfi_read addr width value1 = ( () )"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+
+
+\<comment> \<open>\<open>val mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition mem_read :: " AccessType \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " mem_read typ1 addr width aq rl res = (
+ (if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_Load_Addr_Align)
+ else
+ (case (aq, rl, res) of
+ (False, True, False) => throw (Error_not_implemented (''load.rl''))
+ | (False, True, True) => throw (Error_not_implemented (''lr.rl''))
+ | (_, _, _) => (pmp_mem_read typ1 addr width aq rl res )
+ )) \<bind> (\<lambda> result .
+ (let (_ :: unit) = (rvfi_read addr width result) in
+ return result)))"
+ for typ1 :: " AccessType "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val mem_write_ea : mword ty32 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)\<close>\<close>
+
+definition mem_write_ea :: "(32)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where
+ " mem_write_ea addr width aq rl con = (
+ if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (False, False, False) => write_ram_ea Write_plain addr width \<then> return (MemValue () )
+ | (False, True, False) => write_ram_ea Write_RISCV_release addr width \<then> return (MemValue () )
+ | (False, False, True) =>
+ write_ram_ea Write_RISCV_conditional addr width \<then> return (MemValue () )
+ | (False, True, True) =>
+ write_ram_ea Write_RISCV_conditional_release addr width \<then> return (MemValue () )
+ | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+ | (True, True, False) =>
+ write_ram_ea Write_RISCV_strong_release addr width \<then> return (MemValue () )
+ | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+ | (True, True, True) =>
+ write_ram_ea Write_RISCV_conditional_strong_release addr width \<then> return (MemValue () )
+ ))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+\<comment> \<open>\<open>val rvfi_write : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> unit\<close>\<close>
+
+definition rvfi_write :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit " where
+ " rvfi_write addr width value1 = ( () )"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition phys_mem_write :: " write_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " phys_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ (let (_ :: unit) = (rvfi_write addr width data) in
+ write_ram wk addr width data meta \<bind> (\<lambda> (w__0 :: bool) .
+ (let result = (MemValue w__0) in
+ (let (_ :: unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ (((@) (''mem['')
+ (((@) ((string_of_bits addr)) (((@) (''] <- '') ((string_of_bits data))))))))
+ else () ) in
+ return result)))))"
+ for wk :: " write_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition checked_mem_write :: " write_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " checked_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ if ((within_mmio_writable addr width)) then mmio_write addr width data
+ else if ((within_phys_mem addr width)) then phys_mem_write wk addr width data meta
+ else return (MemException E_SAMO_Access_Fault))"
+ for wk :: " write_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val pmp_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty32 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition pmp_mem_write :: " write_kind \<Rightarrow>(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " pmp_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ if ((\<not> ((plat_enable_pmp () )))) then checked_mem_write wk addr width data meta
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ effectivePrivilege w__1 w__2 \<bind> (\<lambda> (w__3 :: Privilege) .
+ pmpCheck addr width Write w__3 \<bind> (\<lambda> (w__4 :: ExceptionType option) .
+ (case w__4 of
+ None => checked_mem_write wk addr width data meta
+ | Some (e) => return (MemException e)
+ ))))))"
+ for wk :: " write_kind "
+ and addr :: "(32)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val mem_write_value_meta : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> unit -> bool -> bool -> bool -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mem_write_value_meta :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mem_write_value_meta addr width value1 meta aq rl con = (
+ (let (_ :: unit) = (rvfi_write addr width value1) in
+ if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (False, False, False) => pmp_mem_write Write_plain addr width value1 meta
+ | (False, True, False) => pmp_mem_write Write_RISCV_release addr width value1 meta
+ | (False, False, True) => pmp_mem_write Write_RISCV_conditional addr width value1 meta
+ | (False, True, True) => pmp_mem_write Write_RISCV_conditional_release addr width value1 meta
+ | (True, True, False) => pmp_mem_write Write_RISCV_strong_release addr width value1 meta
+ | (True, True, True) =>
+ pmp_mem_write Write_RISCV_conditional_strong_release addr width value1 meta
+ | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+ | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+ )))"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+\<comment> \<open>\<open>val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty32 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mem_write_value :: "(32)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mem_write_value addr width value1 aq rl con = (
+ mem_write_value_meta addr width value1 default_meta aq rl con )"
+ for addr :: "(32)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+definition PAGESIZE_BITS :: " int " where
+ " PAGESIZE_BITS = ( (( 12 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_PTE_Bits : mword ty8 -> PTE_Bits\<close>\<close>
+
+definition Mk_PTE_Bits :: "(8)Word.word \<Rightarrow> PTE_Bits " where
+ " Mk_PTE_Bits v = (
+ (| PTE_Bits_PTE_Bits_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) |) )"
+ for v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_PTE_Bits_bits : PTE_Bits -> mword ty8\<close>\<close>
+
+definition get_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word " where
+ " get_PTE_Bits_bits v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " PTE_Bits "
+
+
+\<comment> \<open>\<open>val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit\<close>\<close>
+
+definition set_PTE_Bits_bits :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits\<close>\<close>
+
+definition update_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_bits v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(8)Word.word "
+
+
+definition get_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_D v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_D :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_D r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_D v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_A v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_A :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_A v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_G v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_G :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_G r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_G v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_U v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_U :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_U r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_U v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_X v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_X :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_X v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_W v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_W :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_W v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_R v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_R :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_R v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_V v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_V :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_V r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_V v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val isPTEPtr : mword ty8 -> bool\<close>\<close>
+
+definition isPTEPtr :: "(8)Word.word \<Rightarrow> bool " where
+ " isPTEPtr p = (
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))"
+ for p :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val isInvalidPTE : mword ty8 -> bool\<close>\<close>
+
+definition isInvalidPTE :: "(8)Word.word \<Rightarrow> bool " where
+ " isInvalidPTE p = (
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_V a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))"
+ for p :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool\<close>\<close>
+
+fun checkPTEPermission :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> PTE_Bits \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = ( internal_error (''m-mode mem perm check''))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+
+
+\<comment> \<open>\<open>val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits\<close>\<close>
+
+definition update_PTE_Bits :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option " where
+ " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = (
+ (let update_d =
+ (((((((a = Write))) \<or> (((a = ReadWrite)))))) \<and> (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in
+ (let update_a = (((get_PTE_Bits_A p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))) in
+ if (((update_d \<or> update_a))) then
+ (let np = (update_PTE_Bits_A p ((bool_to_bits True :: 1 Word.word))) in
+ (let np = (if update_d then update_PTE_Bits_D np ((bool_to_bits True :: 1 Word.word)) else np) in
+ Some np))
+ else None)))"
+ for p :: " PTE_Bits "
+ and a :: " AccessType "
+
+
+\<comment> \<open>\<open>val PTW_Error_of_num : integer -> PTW_Error\<close>\<close>
+
+definition PTW_Error_of_num :: " int \<Rightarrow> PTW_Error " where
+ " PTW_Error_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PTW_Access
+ else if (((p00 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE
+ else if (((p00 = (( 2 :: int)::ii)))) then PTW_No_Permission
+ else if (((p00 = (( 3 :: int)::ii)))) then PTW_Misaligned
+ else PTW_PTE_Update))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_PTW_Error : PTW_Error -> integer\<close>\<close>
+
+fun num_of_PTW_Error :: " PTW_Error \<Rightarrow> int " where
+ " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))"
+|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))"
+|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))"
+|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))"
+|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val ptw_error_to_str : PTW_Error -> string\<close>\<close>
+
+fun ptw_error_to_str :: " PTW_Error \<Rightarrow> string " where
+ " ptw_error_to_str PTW_Access = ( (''mem-access-error''))"
+|" ptw_error_to_str PTW_Invalid_PTE = ( (''invalid-pte''))"
+|" ptw_error_to_str PTW_No_Permission = ( (''no-permission''))"
+|" ptw_error_to_str PTW_Misaligned = ( (''misaligned-superpage''))"
+|" ptw_error_to_str PTW_PTE_Update = ( (''pte-update-needed''))"
+
+
+\<comment> \<open>\<open>val translationException : AccessType -> PTW_Error -> ExceptionType\<close>\<close>
+
+fun translationException :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType " where
+ " translationException (ReadWrite :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )"
+|" translationException (ReadWrite :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )"
+|" translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )"
+|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )"
+|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )"
+|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )"
+|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )"
+ for Fetch :: " AccessType "
+|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )"
+ for Fetch :: " AccessType "
+
+
+\<comment> \<open>\<open>val curAsid32 : mword ty32 -> mword ty9\<close>\<close>
+
+definition curAsid32 :: "(32)Word.word \<Rightarrow>(9)Word.word " where
+ " curAsid32 satp1 = (
+ (let s = (Mk_Satp32 satp1) in
+ (get_Satp32_Asid s :: 9 Word.word)))"
+ for satp1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val curPTB32 : mword ty32 -> mword ty34\<close>\<close>
+
+definition curPTB32 :: "(32)Word.word \<Rightarrow>(34)Word.word " where
+ " curPTB32 satp1 = (
+ (let (s :: Satp32) = (Mk_Satp32 satp1) in
+ (shiftl ((EXTZ (( 34 :: int)::ii) ((get_Satp32_PPN s :: 22 Word.word)) :: 34 Word.word)) PAGESIZE_BITS
+ :: 34 Word.word)))"
+ for satp1 :: "(32)Word.word "
+
+
+definition SV32_LEVEL_BITS :: " int " where
+ " SV32_LEVEL_BITS = ( (( 10 :: int)::ii))"
+
+
+definition SV32_LEVELS :: " int " where
+ " SV32_LEVELS = ( (( 2 :: int)::ii))"
+
+
+definition PTE32_LOG_SIZE :: " int " where
+ " PTE32_LOG_SIZE = ( (( 2 :: int)::ii))"
+
+
+definition PTE32_SIZE :: " int " where
+ " PTE32_SIZE = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV32_Vaddr : mword ty32 -> SV32_Vaddr\<close>\<close>
+
+definition Mk_SV32_Vaddr :: "(32)Word.word \<Rightarrow> SV32_Vaddr " where
+ " Mk_SV32_Vaddr v = (
+ (| SV32_Vaddr_SV32_Vaddr_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32\<close>\<close>
+
+definition get_SV32_Vaddr_bits :: " SV32_Vaddr \<Rightarrow>(32)Word.word " where
+ " get_SV32_Vaddr_bits v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_bits : register_ref regstate register_value SV32_Vaddr -> mword ty32 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_bits :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_bits :: " SV32_Vaddr \<Rightarrow>(32)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_bits v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20\<close>\<close>
+
+definition get_SV32_Vaddr_VPNi :: " SV32_Vaddr \<Rightarrow>(20)Word.word " where
+ " get_SV32_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_VPNi : register_ref regstate register_value SV32_Vaddr -> mword ty20 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_VPNi :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(20)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 31 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_VPNi :: " SV32_Vaddr \<Rightarrow>(20)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_VPNi v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27 -> SV48_Vaddr\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_VPNi : register_ref regstate register_value SV48_Vaddr -> mword ty27 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV32_Vaddr_PgOfs :: " SV32_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV32_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_PgOfs : register_ref regstate register_value SV32_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_PgOfs :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_PgOfs :: " SV32_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_PgOfs v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12 -> SV48_Paddr\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_PgOfs : register_ref regstate register_value SV48_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val Mk_SV32_Paddr : mword ty34 -> SV32_Paddr\<close>\<close>
+
+definition Mk_SV32_Paddr :: "(34)Word.word \<Rightarrow> SV32_Paddr " where
+ " Mk_SV32_Paddr v = (
+ (| SV32_Paddr_SV32_Paddr_chunk_0 = ((subrange_vec_dec v (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word)) |) )"
+ for v :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_bits : SV32_Paddr -> mword ty34\<close>\<close>
+
+definition get_SV32_Paddr_bits :: " SV32_Paddr \<Rightarrow>(34)Word.word " where
+ " get_SV32_Paddr_bits v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_bits : register_ref regstate register_value SV32_Paddr -> mword ty34 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_bits :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(34)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 33 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_bits : SV32_Paddr -> mword ty34 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_bits :: " SV32_Paddr \<Rightarrow>(34)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_bits v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22\<close>\<close>
+
+definition get_SV32_Paddr_PPNi :: " SV32_Paddr \<Rightarrow>(22)Word.word " where
+ " get_SV32_Paddr_PPNi v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 12 :: int)::ii) :: 22 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_PPNi : register_ref regstate register_value SV32_Paddr -> mword ty22 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_PPNi :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 33 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_PPNi :: " SV32_Paddr \<Rightarrow>(22)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_PPNi v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_PPNi : SV48_PTE -> mword ty44 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_PPNi : SV48_PTE -> mword ty44\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_PPNi : register_ref regstate register_value SV48_PTE -> mword ty44 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12\<close>\<close>
+
+definition get_SV32_Paddr_PgOfs :: " SV32_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV32_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_PgOfs : register_ref regstate register_value SV32_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_PgOfs :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_PgOfs :: " SV32_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_PgOfs v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV32_PTE : mword ty32 -> SV32_PTE\<close>\<close>
+
+definition Mk_SV32_PTE :: "(32)Word.word \<Rightarrow> SV32_PTE " where
+ " Mk_SV32_PTE v = (
+ (| SV32_PTE_SV32_PTE_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_bits : SV32_PTE -> mword ty32\<close>\<close>
+
+definition get_SV32_PTE_bits :: " SV32_PTE \<Rightarrow>(32)Word.word " where
+ " get_SV32_PTE_bits v = (
+ (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_bits : register_ref regstate register_value SV32_PTE -> mword ty32 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_bits :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_bits : SV32_PTE -> mword ty32 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_bits :: " SV32_PTE \<Rightarrow>(32)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_bits v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_PPNi : SV32_PTE -> mword ty22\<close>\<close>
+
+definition get_SV32_PTE_PPNi :: " SV32_PTE \<Rightarrow>(22)Word.word " where
+ " get_SV32_PTE_PPNi v = (
+ (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 10 :: int)::ii) :: 22 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_PPNi : register_ref regstate register_value SV32_PTE -> mword ty22 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_PPNi :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 31 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_PPNi : SV32_PTE -> mword ty22 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_PPNi :: " SV32_PTE \<Rightarrow>(22)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_PPNi v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_RSW : SV32_PTE -> mword ty2\<close>\<close>
+
+definition get_SV32_PTE_RSW :: " SV32_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV32_PTE_RSW v = ( (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_RSW : register_ref regstate register_value SV32_PTE -> mword ty2 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_RSW :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_RSW : SV32_PTE -> mword ty2 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_RSW :: " SV32_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_RSW v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_RSW : SV48_PTE -> mword ty2 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_RSW : SV48_PTE -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_RSW : register_ref regstate register_value SV48_PTE -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_PTE_BITS : SV32_PTE -> mword ty8\<close>\<close>
+
+definition get_SV32_PTE_BITS :: " SV32_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV32_PTE_BITS v = ( (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_BITS : register_ref regstate register_value SV32_PTE -> mword ty8 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_BITS :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_BITS : SV32_PTE -> mword ty8 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_BITS :: " SV32_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_BITS v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_BITS : SV48_PTE -> mword ty8 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_BITS : SV48_PTE -> mword ty8\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_BITS : register_ref regstate register_value SV48_PTE -> mword ty8 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val curAsid64 : mword ty64 -> mword ty16\<close>\<close>
+
+definition curAsid64 :: "(64)Word.word \<Rightarrow>(16)Word.word " where
+ " curAsid64 satp1 = (
+ (let s = (Mk_Satp64 satp1) in
+ (get_Satp64_Asid s :: 16 Word.word)))"
+ for satp1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val curPTB64 : mword ty64 -> mword ty56\<close>\<close>
+
+definition curPTB64 :: "(64)Word.word \<Rightarrow>(56)Word.word " where
+ " curPTB64 satp1 = (
+ (let s = (Mk_Satp64 satp1) in
+ (shiftl ((EXTZ (( 56 :: int)::ii) ((get_Satp64_PPN s :: 44 Word.word)) :: 56 Word.word)) PAGESIZE_BITS
+ :: 56 Word.word)))"
+ for satp1 :: "(64)Word.word "
+
+
+definition SV39_LEVEL_BITS :: " int " where
+ " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))"
+
+
+definition SV39_LEVELS :: " int " where
+ " SV39_LEVELS = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_LOG_SIZE :: " int " where
+ " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_SIZE :: " int " where
+ " PTE39_SIZE = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr\<close>\<close>
+
+definition Mk_SV39_Vaddr :: "(39)Word.word \<Rightarrow> SV39_Vaddr " where
+ " Mk_SV39_Vaddr v = (
+ (| SV39_Vaddr_SV39_Vaddr_chunk_0 = ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) |) )"
+ for v :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39\<close>\<close>
+
+definition get_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word " where
+ " get_SV39_Vaddr_bits v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_bits :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_bits v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27\<close>\<close>
+
+definition get_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word " where
+ " get_SV39_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_VPNi :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_VPNi v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV39_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_PgOfs :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_PgOfs v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr\<close>\<close>
+
+definition Mk_SV39_Paddr :: "(56)Word.word \<Rightarrow> SV39_Paddr " where
+ " Mk_SV39_Paddr v = (
+ (| SV39_Paddr_SV39_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) |) )"
+ for v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56\<close>\<close>
+
+definition get_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word " where
+ " get_SV39_Paddr_bits v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_bits :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_bits v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44\<close>\<close>
+
+definition get_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word " where
+ " get_SV39_Paddr_PPNi v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_PPNi :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_PPNi v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12\<close>\<close>
+
+definition get_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV39_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_PgOfs :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_PgOfs v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV39_PTE : mword ty64 -> SV39_PTE\<close>\<close>
+
+definition Mk_SV39_PTE :: "(64)Word.word \<Rightarrow> SV39_PTE " where
+ " Mk_SV39_PTE v = (
+ (| SV39_PTE_SV39_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_bits : SV39_PTE -> mword ty64\<close>\<close>
+
+definition get_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word " where
+ " get_SV39_PTE_bits v = (
+ (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_bits :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_bits v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44\<close>\<close>
+
+definition get_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word " where
+ " get_SV39_PTE_PPNi v = (
+ (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_PPNi :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_PPNi v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2\<close>\<close>
+
+definition get_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV39_PTE_RSW v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_RSW :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_RSW v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8\<close>\<close>
+
+definition get_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV39_PTE_BITS v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_BITS :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_BITS v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(8)Word.word "
+
+
+definition SV48_LEVEL_BITS :: " int " where
+ " SV48_LEVEL_BITS = ( (( 9 :: int)::ii))"
+
+
+definition SV48_LEVELS :: " int " where
+ " SV48_LEVELS = ( (( 4 :: int)::ii))"
+
+
+definition PTE48_LOG_SIZE :: " int " where
+ " PTE48_LOG_SIZE = ( (( 3 :: int)::ii))"
+
+
+definition PTE48_SIZE :: " int " where
+ " PTE48_SIZE = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV48_Vaddr : mword ty48 -> SV48_Vaddr\<close>\<close>
+
+definition Mk_SV48_Vaddr :: "(48)Word.word \<Rightarrow> SV48_Vaddr " where
+ " Mk_SV48_Vaddr v = (
+ (| SV48_Vaddr_SV48_Vaddr_chunk_0 = ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) |) )"
+ for v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48\<close>\<close>
+
+definition get_SV48_Vaddr_bits :: " SV48_Vaddr \<Rightarrow>(48)Word.word " where
+ " get_SV48_Vaddr_bits v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_bits : register_ref regstate register_value SV48_Vaddr -> mword ty48 -> M unit\<close>\<close>
+
+definition set_SV48_Vaddr_bits :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48 -> SV48_Vaddr\<close>\<close>
+
+definition update_SV48_Vaddr_bits :: " SV48_Vaddr \<Rightarrow>(48)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_bits v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(48)Word.word "
+
+
+definition get_SV48_Vaddr_VPNi :: " SV48_Vaddr \<Rightarrow>(27)Word.word " where
+ " get_SV48_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+definition set_SV48_Vaddr_VPNi :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(27)Word.word "
+
+
+definition update_SV48_Vaddr_VPNi :: " SV48_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_VPNi v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV48_Vaddr_PgOfs :: " SV48_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV48_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_PgOfs : register_ref regstate register_value SV48_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV48_Vaddr_PgOfs :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12 -> SV48_Vaddr\<close>\<close>
+
+definition update_SV48_Vaddr_PgOfs :: " SV48_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_PgOfs v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV48_Paddr : mword ty56 -> SV48_Paddr\<close>\<close>
+
+definition Mk_SV48_Paddr :: "(56)Word.word \<Rightarrow> SV48_Paddr " where
+ " Mk_SV48_Paddr v = (
+ (| SV48_Paddr_SV48_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) |) )"
+ for v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_bits : SV48_Paddr -> mword ty56\<close>\<close>
+
+definition get_SV48_Paddr_bits :: " SV48_Paddr \<Rightarrow>(56)Word.word " where
+ " get_SV48_Paddr_bits v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_bits : register_ref regstate register_value SV48_Paddr -> mword ty56 -> M unit\<close>\<close>
+
+definition set_SV48_Paddr_bits :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_bits : SV48_Paddr -> mword ty56 -> SV48_Paddr\<close>\<close>
+
+definition update_SV48_Paddr_bits :: " SV48_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_bits v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44\<close>\<close>
+
+definition get_SV48_Paddr_PPNi :: " SV48_Paddr \<Rightarrow>(44)Word.word " where
+ " get_SV48_Paddr_PPNi v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_PPNi : register_ref regstate register_value SV48_Paddr -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV48_Paddr_PPNi :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44 -> SV48_Paddr\<close>\<close>
+
+definition update_SV48_Paddr_PPNi :: " SV48_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_PPNi v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(44)Word.word "
+
+
+definition get_SV48_Paddr_PgOfs :: " SV48_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV48_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+definition set_SV48_Paddr_PgOfs :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+definition update_SV48_Paddr_PgOfs :: " SV48_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_PgOfs v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV48_PTE : mword ty64 -> SV48_PTE\<close>\<close>
+
+definition Mk_SV48_PTE :: "(64)Word.word \<Rightarrow> SV48_PTE " where
+ " Mk_SV48_PTE v = (
+ (| SV48_PTE_SV48_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+definition get_SV48_PTE_bits :: " SV48_PTE \<Rightarrow>(64)Word.word " where
+ " get_SV48_PTE_bits v = (
+ (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_bits :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(64)Word.word "
+
+
+definition update_SV48_PTE_bits :: " SV48_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_bits v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(64)Word.word "
+
+
+definition get_SV48_PTE_PPNi :: " SV48_PTE \<Rightarrow>(44)Word.word " where
+ " get_SV48_PTE_PPNi v = (
+ (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_PPNi :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(44)Word.word "
+
+
+definition update_SV48_PTE_PPNi :: " SV48_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_PPNi v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(44)Word.word "
+
+
+definition get_SV48_PTE_RSW :: " SV48_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV48_PTE_RSW v = ( (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_RSW :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_SV48_PTE_RSW :: " SV48_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_RSW v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(2)Word.word "
+
+
+definition get_SV48_PTE_BITS :: " SV48_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV48_PTE_BITS v = ( (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_BITS :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+definition update_SV48_PTE_BITS :: " SV48_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_BITS v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val make_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'palen, Size 'ptelen, Size 'valen => mword 'asidlen -> bool -> mword 'valen -> mword 'palen -> mword 'ptelen -> ii -> mword 'palen -> ii -> M (TLB_Entry 'asidlen 'valen 'palen 'ptelen)\<close>\<close>
+
+definition make_TLB_Entry :: "('asidlen::len)Word.word \<Rightarrow> bool \<Rightarrow>('valen::len)Word.word \<Rightarrow>('palen::len)Word.word \<Rightarrow>('ptelen::len)Word.word \<Rightarrow> int \<Rightarrow>('palen::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry),(exception))monad " where
+ " make_TLB_Entry asid global1 vAddr pAddr pte level pteAddr levelBitSize = (
+ (let (shift :: ii) = (PAGESIZE_BITS + ((level * levelBitSize))) in
+ (let vAddrMask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec vAddr
+ ((xor_vec vAddr
+ ((EXTZ ((int (size vAddr))) (vec_of_bits [B1] :: 1 Word.word) :: ( 'valen::len)Word.word))
+ :: ( 'valen::len)Word.word))
+ :: ( 'valen::len)Word.word)) shift
+ :: ( 'valen::len)Word.word)) (( 1 :: int)::ii)
+ :: ( 'valen::len)Word.word)) in
+ (let vMatchMask = ((not_vec vAddrMask :: ( 'valen::len)Word.word)) in
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((| TLB_Entry_asid = asid,
+ TLB_Entry_global = global1,
+ TLB_Entry_vAddr = ((and_vec vAddr vMatchMask :: ( 'valen::len)Word.word)),
+ TLB_Entry_pAddr =
+ ((shiftl ((shiftr pAddr shift :: ( 'palen::len)Word.word)) shift :: ( 'palen::len)Word.word)),
+ TLB_Entry_vMatchMask = vMatchMask,
+ TLB_Entry_vAddrMask = vAddrMask,
+ TLB_Entry_pte = pte,
+ TLB_Entry_pteAddr = pteAddr,
+ TLB_Entry_age = w__0 |)))))))"
+ for asid :: "('asidlen::len)Word.word "
+ and global1 :: " bool "
+ and vAddr :: "('valen::len)Word.word "
+ and pAddr :: "('palen::len)Word.word "
+ and pte :: "('ptelen::len)Word.word "
+ and level :: " int "
+ and pteAddr :: "('palen::len)Word.word "
+ and levelBitSize :: " int "
+
+
+\<comment> \<open>\<open>val match_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> mword 'asidlen -> mword 'valen -> bool\<close>\<close>
+
+definition match_TLB_Entry :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry \<Rightarrow>('asidlen::len)Word.word \<Rightarrow>('valen::len)Word.word \<Rightarrow> bool " where
+ " match_TLB_Entry ent asid vaddr = (
+ (((((TLB_Entry_global ent) \<or> ((((TLB_Entry_asid ent) = asid)))))) \<and> ((((TLB_Entry_vAddr ent) = ((and_vec(TLB_Entry_vMatchMask ent) vaddr :: ( 'valen::len)Word.word)))))))"
+ for ent :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and asid :: "('asidlen::len)Word.word "
+ and vaddr :: "('valen::len)Word.word "
+
+
+\<comment> \<open>\<open>val flush_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> maybe (mword 'asidlen) -> maybe (mword 'valen) -> bool\<close>\<close>
+
+fun flush_TLB_Entry :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry \<Rightarrow>(('asidlen::len)Word.word)option \<Rightarrow>(('valen::len)Word.word)option \<Rightarrow> bool " where
+ " flush_TLB_Entry e None None = ( True )"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+|" flush_TLB_Entry e None (Some (a)) = (
+ ((TLB_Entry_vAddr e) = ((and_vec(TLB_Entry_vMatchMask e) a :: ( 'valen::len)Word.word))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and a :: "('valen::len)Word.word "
+|" flush_TLB_Entry e (Some (i)) None = ( (((((TLB_Entry_asid e) = i))) \<and> ((\<not>(TLB_Entry_global e)))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and i :: "('asidlen::len)Word.word "
+|" flush_TLB_Entry e (Some (i)) (Some (a)) = (
+ (((((TLB_Entry_asid e) = i))) \<and> (((((((TLB_Entry_vAddr e) = ((and_vec a(TLB_Entry_vMatchMask e) :: ( 'valen::len)Word.word))))) \<and> ((\<not>(TLB_Entry_global e))))))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and i :: "('asidlen::len)Word.word "
+ and a :: "('valen::len)Word.word "
+
+
+\<comment> \<open>\<open>val to_phys_addr : mword ty34 -> mword ty32\<close>\<close>
+
+definition to_phys_addr :: "(34)Word.word \<Rightarrow>(32)Word.word " where
+ " to_phys_addr a = ( (subrange_vec_dec a (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for a :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val walk32 : mword ty32 -> AccessType -> Privilege -> bool -> bool -> mword ty34 -> ii -> bool -> M (PTW_Result (mword ty34) SV32_PTE)\<close>\<close>
+
+function (sequential,domintros) walk32 :: "(32)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(34)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),((((34)Word.word),(SV32_PTE))PTW_Result),(exception))monad " where
+ " walk32 vaddr ac priv mxr do_sum ptb level global1 = (
+ (let va = (Mk_SV32_Vaddr vaddr) in
+ (let (pt_ofs :: paddr32) =
+ ((shiftl
+ ((EXTZ (( 34 :: int)::ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV32_Vaddr_VPNi va :: 20 Word.word))
+ ((level * SV32_LEVEL_BITS))
+ :: 20 Word.word)) ((SV32_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii)
+ :: 10 Word.word))
+ :: 34 Word.word)) PTE32_LOG_SIZE
+ :: 34 Word.word)) in
+ (let pte_addr = ((add_vec ptb pt_ofs :: 34 Word.word)) in
+ (mem_read ac ((to_phys_addr pte_addr :: 32 Word.word)) (( 4 :: int)::ii) False False False
+ :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 32 Word.word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => return (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ (let pte = (Mk_SV32_PTE v) in
+ (let pbits = ((get_SV32_PTE_BITS pte :: 8 Word.word)) in
+ (let pattr = (Mk_PTE_Bits pbits) in
+ (let is_global =
+ (global1 \<or> (((((get_PTE_Bits_G pattr :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) in
+ if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk32 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 34 :: int)::ii) ((get_SV32_PTE_PPNi pte :: 22 Word.word)) :: 34 Word.word))
+ PAGESIZE_BITS
+ :: 34 Word.word)) ((level - (( 1 :: int)::ii))) is_global
+ :: ( (( 34 Word.word), SV32_PTE)PTW_Result) M)
+ else
+ checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) .
+ return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 :: int)::ii))) then
+ (let mask1 =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV32_PTE_PPNi pte :: 22 Word.word))
+ ((xor_vec ((get_SV32_PTE_PPNi pte :: 22 Word.word))
+ ((EXTZ (( 22 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 22 Word.word))
+ :: 22 Word.word))
+ :: 22 Word.word)) ((level * SV32_LEVEL_BITS))
+ :: 22 Word.word)) (( 1 :: int)::ii)
+ :: 22 Word.word)) in
+ if (((((and_vec ((get_SV32_PTE_PPNi pte :: 22 Word.word)) mask1 :: 22 Word.word)) \<noteq> ((EXTZ (( 22 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 22 Word.word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ (let ppn =
+ ((or_vec ((get_SV32_PTE_PPNi pte :: 22 Word.word))
+ ((and_vec
+ ((EXTZ (( 22 :: int)::ii) ((get_SV32_Vaddr_VPNi va :: 20 Word.word)) :: 22 Word.word))
+ mask1
+ :: 22 Word.word))
+ :: 22 Word.word)) in
+ PTW_Success ((concat_vec ppn ((get_SV32_Vaddr_PgOfs va :: 12 Word.word))
+ :: 34 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ else
+ PTW_Success ((concat_vec ((get_SV32_PTE_PPNi pte :: 22 Word.word))
+ ((get_SV32_Vaddr_PgOfs va :: 12 Word.word))
+ :: 34 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))))))
+ ))))))"
+ for vaddr :: "(32)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and ptb :: "(34)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val lookup_TLB32 : mword ty9 -> mword ty32 -> M (maybe ((ii * TLB_Entry ty9 ty32 ty34 ty32)))\<close>\<close>
+
+definition lookup_TLB32 :: "(9)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),((int*((9),(32),(34),(32))TLB_Entry)option),(exception))monad " where
+ " lookup_TLB32 asid vaddr = (
+ read_reg tlb32_ref \<bind> (\<lambda> (w__0 :: ( (9, 32, 34, 32)TLB_Entry)option) .
+ return ((case w__0 of
+ None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((( 0 :: int)::ii), e) else None
+ ))))"
+ for asid :: "(9)Word.word "
+ and vaddr :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val add_to_TLB32 : mword ty9 -> mword ty32 -> mword ty34 -> SV32_PTE -> mword ty34 -> ii -> bool -> M unit\<close>\<close>
+
+definition add_to_TLB32 :: "(9)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(34)Word.word \<Rightarrow> SV32_PTE \<Rightarrow>(34)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " add_to_TLB32 asid vAddr pAddr pte pteAddr level global1 = (
+ make_TLB_Entry asid global1 vAddr pAddr ((get_SV32_PTE_bits pte :: 32 Word.word)) level pteAddr
+ SV32_LEVEL_BITS \<bind> (\<lambda> (ent :: TLB32_Entry) .
+ write_reg tlb32_ref (Some ent)))"
+ for asid :: "(9)Word.word "
+ and vAddr :: "(32)Word.word "
+ and pAddr :: "(34)Word.word "
+ and pte :: " SV32_PTE "
+ and pteAddr :: "(34)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+
+
+\<comment> \<open>\<open>val write_TLB32 : ii -> TLB_Entry ty9 ty32 ty34 ty32 -> M unit\<close>\<close>
+
+definition write_TLB32 :: " int \<Rightarrow>((9),(32),(34),(32))TLB_Entry \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " write_TLB32 (idx :: ii) (ent :: TLB32_Entry) = ( write_reg tlb32_ref (Some ent))"
+ for idx :: " int "
+ and ent :: "((9),(32),(34),(32))TLB_Entry "
+
+
+\<comment> \<open>\<open>val flush_TLB32 : maybe (mword ty9) -> maybe (mword ty32) -> M unit\<close>\<close>
+
+definition flush_TLB32 :: "((9)Word.word)option \<Rightarrow>((32)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " flush_TLB32 asid addr = (
+ read_reg tlb32_ref \<bind> (\<lambda> (w__0 :: ( (9, 32, 34, 32)TLB_Entry)option) .
+ (case w__0 of
+ None => return ()
+ | Some (e) => if ((flush_TLB_Entry e asid addr)) then write_reg tlb32_ref None else return ()
+ )))"
+ for asid :: "((9)Word.word)option "
+ and addr :: "((32)Word.word)option "
+
+
+\<comment> \<open>\<open>val translate32 : mword ty9 -> mword ty34 -> mword ty32 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty34) PTW_Error)\<close>\<close>
+
+definition translate32 :: "(9)Word.word \<Rightarrow>(34)Word.word \<Rightarrow>(32)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),((((34)Word.word),(PTW_Error))TR_Result),(exception))monad " where
+ " translate32 asid ptb vAddr ac priv mxr do_sum level = (
+ lookup_TLB32 asid vAddr \<bind> (\<lambda> (w__0 :: ((ii * (9, 32, 34, 32) TLB_Entry))option) .
+ (case w__0 of
+ Some ((idx, ent)) =>
+ (let pte = (Mk_SV32_PTE(TLB_Entry_pte ent)) in
+ (let pteBits = (Mk_PTE_Bits ((get_SV32_PTE_BITS pte :: 8 Word.word))) in
+ checkPTEPermission ac priv mxr do_sum pteBits \<bind> (\<lambda> (w__1 :: bool) .
+ if ((\<not> w__1)) then return (TR_Failure PTW_No_Permission)
+ else
+ (case ((update_PTE_Bits pteBits ac)) of
+ None =>
+ return (TR_Address ((or_vec(TLB_Entry_pAddr ent)
+ ((EXTZ (( 34 :: int)::ii)
+ ((and_vec vAddr(TLB_Entry_vAddrMask ent) :: 32 Word.word))
+ :: 34 Word.word))
+ :: 34 Word.word)))
+ | Some (pbits) =>
+ if ((\<not> ((plat_enable_dirty_update () )))) then return (TR_Failure PTW_PTE_Update)
+ else
+ (let n_pte = (update_SV32_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in
+ (let (n_ent :: TLB32_Entry) = ent in
+ (let n_ent = ((n_ent (| TLB_Entry_pte := ((get_SV32_PTE_bits n_pte :: 32 Word.word))|))) in
+ (write_TLB32 idx n_ent \<then>
+ mem_write_value
+ ((to_phys_addr ((EXTZ (( 34 :: int)::ii)(TLB_Entry_pteAddr ent) :: 34 Word.word)) :: 32 Word.word))
+ (( 4 :: int)::ii) ((get_SV32_PTE_bits n_pte :: 32 Word.word)) False False False) \<bind> (\<lambda> (w__2 :: bool
+ MemoryOpResult) .
+ (case w__2 of
+ MemValue (_) => return ()
+ | MemException (e) => internal_error (''invalid physical address in TLB'')
+ ) \<then>
+ return (TR_Address ((or_vec(TLB_Entry_pAddr ent)
+ ((EXTZ (( 34 :: int)::ii)
+ ((and_vec vAddr(TLB_Entry_vAddrMask ent) :: 32 Word.word))
+ :: 34 Word.word))
+ :: 34 Word.word)))))))
+ ))))
+ | None =>
+ (walk32 vAddr ac priv mxr do_sum ptb level False :: ( (( 34 Word.word), SV32_PTE)PTW_Result) M) \<bind> (\<lambda> (w__6 :: (( 34 Word.word), SV32_PTE)
+ PTW_Result) .
+ (case w__6 of
+ PTW_Failure (f) => return (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global1)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV32_PTE_BITS pte :: 8 Word.word)))) ac)) of
+ None =>
+ add_to_TLB32 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR_Address pAddr)
+ | Some (pbits) =>
+ if ((\<not> ((plat_enable_dirty_update () )))) then return (TR_Failure PTW_PTE_Update)
+ else
+ (let (w_pte :: SV32_PTE) =
+ (update_SV32_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in
+ mem_write_value ((to_phys_addr pteAddr :: 32 Word.word)) (( 4 :: int)::ii)
+ ((get_SV32_PTE_bits w_pte :: 32 Word.word)) False False False \<bind> (\<lambda> (w__7 :: bool
+ MemoryOpResult) .
+ (case w__7 of
+ MemValue (_) =>
+ add_to_TLB32 asid vAddr pAddr w_pte pteAddr level global1 \<then>
+ return (TR_Address pAddr)
+ | MemException (e) => return (TR_Failure PTW_Access)
+ )))
+ )
+ ))
+ )))"
+ for asid :: "(9)Word.word "
+ and ptb :: "(34)Word.word "
+ and vAddr :: "(32)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and level :: " int "
+
+
+\<comment> \<open>\<open>val init_vmem_sv32 : unit -> M unit\<close>\<close>
+
+definition init_vmem_sv32 :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_vmem_sv32 _ = ( write_reg tlb32_ref None )"
+
+
+\<comment> \<open>\<open>val legalize_satp : Architecture -> mword ty32 -> mword ty32 -> mword ty32\<close>\<close>
+
+definition legalize_satp :: " Architecture \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word " where
+ " legalize_satp (a :: Architecture) (o1 :: xlenbits) (v :: xlenbits) = (
+ (legalize_satp32 a o1 v :: 32 Word.word))"
+ for a :: " Architecture "
+ and o1 :: "(32)Word.word "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val translationMode : Privilege -> M SATPMode\<close>\<close>
+
+definition translationMode :: " Privilege \<Rightarrow>((register_value),(SATPMode),(exception))monad " where
+ " translationMode priv = (
+ if (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ then
+ return Sbare
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ (let arch = (architecture ((get_mstatus_SXL w__0 :: 2 Word.word))) in
+ (case arch of
+ Some (RV32) =>
+ (read_reg satp_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (let s = (Mk_Satp32 ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in
+ return (if (((((get_Satp32_Mode s :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))
+ then
+ Sbare
+ else Sv32)))
+ | _ => internal_error (''unsupported address translation arch'')
+ ))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val translateAddr : mword ty32 -> AccessType -> M (TR_Result (mword ty32) ExceptionType)\<close>\<close>
+
+definition translateAddr :: "(32)Word.word \<Rightarrow> AccessType \<Rightarrow>((register_value),((((32)Word.word),(ExceptionType))TR_Result),(exception))monad " where
+ " translateAddr vAddr ac = (
+ (case ac of
+ Execute => read_reg cur_privilege_ref
+ | _ =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) . effectivePrivilege w__1 w__2))
+ ) \<bind> (\<lambda> (effPriv :: Privilege) .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ (let (mxr :: bool) =
+ (((get_Mstatus_MXR w__4 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in
+ read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) .
+ (let (do_sum :: bool) =
+ (((get_Mstatus_SUM w__5 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in
+ translationMode effPriv \<bind> (\<lambda> (mode :: SATPMode) .
+ (read_reg satp_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) .
+ (let asid = ((curAsid32 w__6 :: 9 Word.word)) in
+ (read_reg satp_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) .
+ (let ptb = ((curPTB32 w__7 :: 34 Word.word)) in
+ (case mode of
+ Sbare => return (TR_Address vAddr)
+ | Sv32 =>
+ (translate32 asid ptb vAddr ac effPriv mxr do_sum ((SV32_LEVELS - (( 1 :: int)::ii)))
+ :: ( (( 34 Word.word), PTW_Error)TR_Result) M) \<bind> (\<lambda> (w__8 :: (( 34 Word.word), PTW_Error) TR_Result) .
+ return ((case w__8 of
+ TR_Address (pa) => TR_Address ((to_phys_addr pa :: 32 Word.word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | _ =>
+ (internal_error (''unsupported address translation scheme'')
+ :: ( (( 32 Word.word), ExceptionType)TR_Result) M)
+ ))))))))))))"
+ for vAddr :: "(32)Word.word "
+ and ac :: " AccessType "
+
+
+\<comment> \<open>\<open>val flush_TLB : maybe (mword ty32) -> maybe (mword ty32) -> M unit\<close>\<close>
+
+definition flush_TLB :: "((32)Word.word)option \<Rightarrow>((32)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " flush_TLB asid_xlen addr_xlen = (
+ (let (asid :: asid32 option) =
+ ((case asid_xlen of
+ None => None
+ | Some (a) => Some ((subrange_vec_dec a (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word))
+ )) in
+ flush_TLB32 asid addr_xlen))"
+ for asid_xlen :: "((32)Word.word)option "
+ and addr_xlen :: "((32)Word.word)option "
+
+
+\<comment> \<open>\<open>val init_vmem : unit -> M unit\<close>\<close>
+
+definition init_vmem :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_vmem _ = ( init_vmem_sv32 () )"
+
+
+\<comment> \<open>\<open>val execute : ast -> M Retired\<close>\<close>
+
+\<comment> \<open>\<open>val encdec_uop_forwards : uop -> mword ty7\<close>\<close>
+
+fun encdec_uop_forwards :: " uop \<Rightarrow>(7)Word.word " where
+ " encdec_uop_forwards RISCV_LUI = ( (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word))"
+|" encdec_uop_forwards RISCV_AUIPC = ( (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_uop_backwards : mword ty7 -> M uop\<close>\<close>
+
+definition encdec_uop_backwards :: "(7)Word.word \<Rightarrow>((register_value),(uop),(exception))monad " where
+ " encdec_uop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then return RISCV_LUI
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then return RISCV_AUIPC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_uop_forwards_matches : uop -> bool\<close>\<close>
+
+fun encdec_uop_forwards_matches :: " uop \<Rightarrow> bool " where
+ " encdec_uop_forwards_matches RISCV_LUI = ( True )"
+|" encdec_uop_forwards_matches RISCV_AUIPC = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_uop_backwards_matches : mword ty7 -> bool\<close>\<close>
+
+definition encdec_uop_backwards_matches :: "(7)Word.word \<Rightarrow> bool " where
+ " encdec_uop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True
+ else False))"
+ for arg1 :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_forwards : uop -> string\<close>\<close>
+
+fun utype_mnemonic_forwards :: " uop \<Rightarrow> string " where
+ " utype_mnemonic_forwards RISCV_LUI = ( (''lui''))"
+|" utype_mnemonic_forwards RISCV_AUIPC = ( (''auipc''))"
+
+
+\<comment> \<open>\<open>val utype_mnemonic_backwards : string -> M uop\<close>\<close>
+
+definition utype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(uop),(exception))monad " where
+ " utype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''lui'')))) then return RISCV_LUI
+ else if (((p00 = (''auipc'')))) then return RISCV_AUIPC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_forwards_matches : uop -> bool\<close>\<close>
+
+fun utype_mnemonic_forwards_matches :: " uop \<Rightarrow> bool " where
+ " utype_mnemonic_forwards_matches RISCV_LUI = ( True )"
+|" utype_mnemonic_forwards_matches RISCV_AUIPC = ( True )"
+
+
+\<comment> \<open>\<open>val utype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition utype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " utype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''lui'')))) then True
+ else if (((p00 = (''auipc'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s496_ : string -> maybe string\<close>\<close>
+
+definition s496 :: " string \<Rightarrow>(string)option " where
+ " s496 s4970 = (
+ (let s4980 = s4970 in
+ if ((string_startswith s4980 (''auipc''))) then
+ (case ((string_drop s4980 ((string_length (''auipc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4970 :: " string "
+
+
+\<comment> \<open>\<open>val _s492_ : string -> maybe string\<close>\<close>
+
+definition s492 :: " string \<Rightarrow>(string)option " where
+ " s492 s4930 = (
+ (let s4940 = s4930 in
+ if ((string_startswith s4940 (''lui''))) then
+ (case ((string_drop s4940 ((string_length (''lui''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4930 :: " string "
+
+
+definition utype_mnemonic_matches_prefix :: " string \<Rightarrow>(uop*int)option " where
+ " utype_mnemonic_matches_prefix arg1 = (
+ (let s4950 = arg1 in
+ if ((case ((s492 s4950)) of Some (s1) => True | _ => False )) then
+ (case s492 s4950 of
+ (Some (s1)) =>
+ Some (RISCV_LUI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s496 s4950)) of Some (s1) => True | _ => False )) then
+ (case s496 s4950 of
+ (Some (s1)) =>
+ Some (RISCV_AUIPC, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_bop_forwards : bop -> mword ty3\<close>\<close>
+
+fun encdec_bop_forwards :: " bop \<Rightarrow>(3)Word.word " where
+ " encdec_bop_forwards RISCV_BEQ = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BNE = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BLT = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BGE = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BLTU = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BGEU = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_bop_backwards : mword ty3 -> M bop\<close>\<close>
+
+definition encdec_bop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(bop),(exception))monad " where
+ " encdec_bop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return RISCV_BEQ
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return RISCV_BNE
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return RISCV_BLT
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_BGE
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return RISCV_BLTU
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return RISCV_BGEU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_bop_forwards_matches : bop -> bool\<close>\<close>
+
+fun encdec_bop_forwards_matches :: " bop \<Rightarrow> bool " where
+ " encdec_bop_forwards_matches RISCV_BEQ = ( True )"
+|" encdec_bop_forwards_matches RISCV_BNE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLT = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLTU = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGEU = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_bop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_bop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_bop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_forwards : bop -> string\<close>\<close>
+
+fun btype_mnemonic_forwards :: " bop \<Rightarrow> string " where
+ " btype_mnemonic_forwards RISCV_BEQ = ( (''beq''))"
+|" btype_mnemonic_forwards RISCV_BNE = ( (''bne''))"
+|" btype_mnemonic_forwards RISCV_BLT = ( (''blt''))"
+|" btype_mnemonic_forwards RISCV_BGE = ( (''bge''))"
+|" btype_mnemonic_forwards RISCV_BLTU = ( (''bltu''))"
+|" btype_mnemonic_forwards RISCV_BGEU = ( (''bgeu''))"
+
+
+\<comment> \<open>\<open>val btype_mnemonic_backwards : string -> M bop\<close>\<close>
+
+definition btype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(bop),(exception))monad " where
+ " btype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''beq'')))) then return RISCV_BEQ
+ else if (((p00 = (''bne'')))) then return RISCV_BNE
+ else if (((p00 = (''blt'')))) then return RISCV_BLT
+ else if (((p00 = (''bge'')))) then return RISCV_BGE
+ else if (((p00 = (''bltu'')))) then return RISCV_BLTU
+ else if (((p00 = (''bgeu'')))) then return RISCV_BGEU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_forwards_matches : bop -> bool\<close>\<close>
+
+fun btype_mnemonic_forwards_matches :: " bop \<Rightarrow> bool " where
+ " btype_mnemonic_forwards_matches RISCV_BEQ = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BNE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLT = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLTU = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGEU = ( True )"
+
+
+\<comment> \<open>\<open>val btype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition btype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " btype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''beq'')))) then True
+ else if (((p00 = (''bne'')))) then True
+ else if (((p00 = (''blt'')))) then True
+ else if (((p00 = (''bge'')))) then True
+ else if (((p00 = (''bltu'')))) then True
+ else if (((p00 = (''bgeu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s520_ : string -> maybe string\<close>\<close>
+
+definition s520 :: " string \<Rightarrow>(string)option " where
+ " s520 s5210 = (
+ (let s5220 = s5210 in
+ if ((string_startswith s5220 (''bgeu''))) then
+ (case ((string_drop s5220 ((string_length (''bgeu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5210 :: " string "
+
+
+\<comment> \<open>\<open>val _s516_ : string -> maybe string\<close>\<close>
+
+definition s516 :: " string \<Rightarrow>(string)option " where
+ " s516 s5170 = (
+ (let s5180 = s5170 in
+ if ((string_startswith s5180 (''bltu''))) then
+ (case ((string_drop s5180 ((string_length (''bltu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5170 :: " string "
+
+
+\<comment> \<open>\<open>val _s512_ : string -> maybe string\<close>\<close>
+
+definition s512 :: " string \<Rightarrow>(string)option " where
+ " s512 s5130 = (
+ (let s5140 = s5130 in
+ if ((string_startswith s5140 (''bge''))) then
+ (case ((string_drop s5140 ((string_length (''bge''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5130 :: " string "
+
+
+\<comment> \<open>\<open>val _s508_ : string -> maybe string\<close>\<close>
+
+definition s508 :: " string \<Rightarrow>(string)option " where
+ " s508 s5090 = (
+ (let s5100 = s5090 in
+ if ((string_startswith s5100 (''blt''))) then
+ (case ((string_drop s5100 ((string_length (''blt''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5090 :: " string "
+
+
+\<comment> \<open>\<open>val _s504_ : string -> maybe string\<close>\<close>
+
+definition s504 :: " string \<Rightarrow>(string)option " where
+ " s504 s5050 = (
+ (let s5060 = s5050 in
+ if ((string_startswith s5060 (''bne''))) then
+ (case ((string_drop s5060 ((string_length (''bne''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5050 :: " string "
+
+
+\<comment> \<open>\<open>val _s500_ : string -> maybe string\<close>\<close>
+
+definition s500 :: " string \<Rightarrow>(string)option " where
+ " s500 s5010 = (
+ (let s5020 = s5010 in
+ if ((string_startswith s5020 (''beq''))) then
+ (case ((string_drop s5020 ((string_length (''beq''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5010 :: " string "
+
+
+definition btype_mnemonic_matches_prefix :: " string \<Rightarrow>(bop*int)option " where
+ " btype_mnemonic_matches_prefix arg1 = (
+ (let s5030 = arg1 in
+ if ((case ((s500 s5030)) of Some (s1) => True | _ => False )) then
+ (case s500 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BEQ, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s504 s5030)) of Some (s1) => True | _ => False )) then
+ (case s504 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BNE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s508 s5030)) of Some (s1) => True | _ => False )) then
+ (case s508 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BLT, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s512 s5030)) of Some (s1) => True | _ => False )) then
+ (case s512 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BGE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s516 s5030)) of Some (s1) => True | _ => False )) then
+ (case s516 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BLTU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s520 s5030)) of Some (s1) => True | _ => False )) then
+ (case s520 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BGEU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_iop_forwards : iop -> mword ty3\<close>\<close>
+
+fun encdec_iop_forwards :: " iop \<Rightarrow>(3)Word.word " where
+ " encdec_iop_forwards RISCV_ADDI = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTI = ( (vec_of_bits [B0,B1,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTIU = ( (vec_of_bits [B0,B1,B1] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_ANDI = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_ORI = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_XORI = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_iop_backwards : mword ty3 -> M iop\<close>\<close>
+
+definition encdec_iop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(iop),(exception))monad " where
+ " encdec_iop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return RISCV_ADDI
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return RISCV_SLTI
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return RISCV_SLTIU
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return RISCV_ANDI
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return RISCV_ORI
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return RISCV_XORI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_iop_forwards_matches : iop -> bool\<close>\<close>
+
+fun encdec_iop_forwards_matches :: " iop \<Rightarrow> bool " where
+ " encdec_iop_forwards_matches RISCV_ADDI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTIU = ( True )"
+|" encdec_iop_forwards_matches RISCV_ANDI = ( True )"
+|" encdec_iop_forwards_matches RISCV_ORI = ( True )"
+|" encdec_iop_forwards_matches RISCV_XORI = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_iop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_iop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_iop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_forwards : iop -> string\<close>\<close>
+
+fun itype_mnemonic_forwards :: " iop \<Rightarrow> string " where
+ " itype_mnemonic_forwards RISCV_ADDI = ( (''addi''))"
+|" itype_mnemonic_forwards RISCV_SLTI = ( (''slti''))"
+|" itype_mnemonic_forwards RISCV_SLTIU = ( (''sltiu''))"
+|" itype_mnemonic_forwards RISCV_XORI = ( (''xori''))"
+|" itype_mnemonic_forwards RISCV_ORI = ( (''ori''))"
+|" itype_mnemonic_forwards RISCV_ANDI = ( (''andi''))"
+
+
+\<comment> \<open>\<open>val itype_mnemonic_backwards : string -> M iop\<close>\<close>
+
+definition itype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(iop),(exception))monad " where
+ " itype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addi'')))) then return RISCV_ADDI
+ else if (((p00 = (''slti'')))) then return RISCV_SLTI
+ else if (((p00 = (''sltiu'')))) then return RISCV_SLTIU
+ else if (((p00 = (''xori'')))) then return RISCV_XORI
+ else if (((p00 = (''ori'')))) then return RISCV_ORI
+ else if (((p00 = (''andi'')))) then return RISCV_ANDI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_forwards_matches : iop -> bool\<close>\<close>
+
+fun itype_mnemonic_forwards_matches :: " iop \<Rightarrow> bool " where
+ " itype_mnemonic_forwards_matches RISCV_ADDI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTIU = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_XORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ANDI = ( True )"
+
+
+\<comment> \<open>\<open>val itype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition itype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " itype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addi'')))) then True
+ else if (((p00 = (''slti'')))) then True
+ else if (((p00 = (''sltiu'')))) then True
+ else if (((p00 = (''xori'')))) then True
+ else if (((p00 = (''ori'')))) then True
+ else if (((p00 = (''andi'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s544_ : string -> maybe string\<close>\<close>
+
+definition s544 :: " string \<Rightarrow>(string)option " where
+ " s544 s5450 = (
+ (let s5460 = s5450 in
+ if ((string_startswith s5460 (''andi''))) then
+ (case ((string_drop s5460 ((string_length (''andi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5450 :: " string "
+
+
+\<comment> \<open>\<open>val _s540_ : string -> maybe string\<close>\<close>
+
+definition s540 :: " string \<Rightarrow>(string)option " where
+ " s540 s5410 = (
+ (let s5420 = s5410 in
+ if ((string_startswith s5420 (''ori''))) then
+ (case ((string_drop s5420 ((string_length (''ori''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5410 :: " string "
+
+
+\<comment> \<open>\<open>val _s536_ : string -> maybe string\<close>\<close>
+
+definition s536 :: " string \<Rightarrow>(string)option " where
+ " s536 s5370 = (
+ (let s5380 = s5370 in
+ if ((string_startswith s5380 (''xori''))) then
+ (case ((string_drop s5380 ((string_length (''xori''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5370 :: " string "
+
+
+\<comment> \<open>\<open>val _s532_ : string -> maybe string\<close>\<close>
+
+definition s532 :: " string \<Rightarrow>(string)option " where
+ " s532 s5330 = (
+ (let s5340 = s5330 in
+ if ((string_startswith s5340 (''sltiu''))) then
+ (case ((string_drop s5340 ((string_length (''sltiu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5330 :: " string "
+
+
+\<comment> \<open>\<open>val _s528_ : string -> maybe string\<close>\<close>
+
+definition s528 :: " string \<Rightarrow>(string)option " where
+ " s528 s5290 = (
+ (let s5300 = s5290 in
+ if ((string_startswith s5300 (''slti''))) then
+ (case ((string_drop s5300 ((string_length (''slti''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5290 :: " string "
+
+
+\<comment> \<open>\<open>val _s524_ : string -> maybe string\<close>\<close>
+
+definition s524 :: " string \<Rightarrow>(string)option " where
+ " s524 s5250 = (
+ (let s5260 = s5250 in
+ if ((string_startswith s5260 (''addi''))) then
+ (case ((string_drop s5260 ((string_length (''addi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5250 :: " string "
+
+
+definition itype_mnemonic_matches_prefix :: " string \<Rightarrow>(iop*int)option " where
+ " itype_mnemonic_matches_prefix arg1 = (
+ (let s5270 = arg1 in
+ if ((case ((s524 s5270)) of Some (s1) => True | _ => False )) then
+ (case s524 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ADDI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s528 s5270)) of Some (s1) => True | _ => False )) then
+ (case s528 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_SLTI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s532 s5270)) of Some (s1) => True | _ => False )) then
+ (case s532 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_SLTIU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s536 s5270)) of Some (s1) => True | _ => False )) then
+ (case s536 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_XORI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s540 s5270)) of Some (s1) => True | _ => False )) then
+ (case s540 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ORI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s544 s5270)) of Some (s1) => True | _ => False )) then
+ (case s544 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ANDI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_sop_forwards : sop -> mword ty3\<close>\<close>
+
+fun encdec_sop_forwards :: " sop \<Rightarrow>(3)Word.word " where
+ " encdec_sop_forwards RISCV_SLLI = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_sop_forwards RISCV_SRLI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+|" encdec_sop_forwards RISCV_SRAI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_sop_backwards : mword ty3 -> M sop\<close>\<close>
+
+definition encdec_sop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " encdec_sop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return RISCV_SLLI
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_SRLI
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_sop_forwards_matches : sop -> bool\<close>\<close>
+
+fun encdec_sop_forwards_matches :: " sop \<Rightarrow> bool " where
+ " encdec_sop_forwards_matches RISCV_SLLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_sop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_sop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_sop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_forwards : sop -> string\<close>\<close>
+
+fun shiftiop_mnemonic_forwards :: " sop \<Rightarrow> string " where
+ " shiftiop_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_backwards : string -> M sop\<close>\<close>
+
+definition shiftiop_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " shiftiop_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then return RISCV_SLLI
+ else if (((p00 = (''srli'')))) then return RISCV_SRLI
+ else if (((p00 = (''srai'')))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_forwards_matches : sop -> bool\<close>\<close>
+
+fun shiftiop_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where
+ " shiftiop_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftiop_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftiop_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then True
+ else if (((p00 = (''srli'')))) then True
+ else if (((p00 = (''srai'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s556_ : string -> maybe string\<close>\<close>
+
+definition s556 :: " string \<Rightarrow>(string)option " where
+ " s556 s5570 = (
+ (let s5580 = s5570 in
+ if ((string_startswith s5580 (''srai''))) then
+ (case ((string_drop s5580 ((string_length (''srai''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5570 :: " string "
+
+
+\<comment> \<open>\<open>val _s552_ : string -> maybe string\<close>\<close>
+
+definition s552 :: " string \<Rightarrow>(string)option " where
+ " s552 s5530 = (
+ (let s5540 = s5530 in
+ if ((string_startswith s5540 (''srli''))) then
+ (case ((string_drop s5540 ((string_length (''srli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5530 :: " string "
+
+
+\<comment> \<open>\<open>val _s548_ : string -> maybe string\<close>\<close>
+
+definition s548 :: " string \<Rightarrow>(string)option " where
+ " s548 s5490 = (
+ (let s5500 = s5490 in
+ if ((string_startswith s5500 (''slli''))) then
+ (case ((string_drop s5500 ((string_length (''slli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5490 :: " string "
+
+
+definition shiftiop_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where
+ " shiftiop_mnemonic_matches_prefix arg1 = (
+ (let s5510 = arg1 in
+ if ((case ((s548 s5510)) of Some (s1) => True | _ => False )) then
+ (case s548 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SLLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s552 s5510)) of Some (s1) => True | _ => False )) then
+ (case s552 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SRLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s556 s5510)) of Some (s1) => True | _ => False )) then
+ (case s556 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SRAI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_forwards : rop -> string\<close>\<close>
+
+fun rtype_mnemonic_forwards :: " rop \<Rightarrow> string " where
+ " rtype_mnemonic_forwards RISCV_ADD = ( (''add''))"
+|" rtype_mnemonic_forwards RISCV_SLT = ( (''slt''))"
+|" rtype_mnemonic_forwards RISCV_SLTU = ( (''sltu''))"
+|" rtype_mnemonic_forwards RISCV_AND = ( (''and''))"
+|" rtype_mnemonic_forwards RISCV_OR = ( (''or''))"
+|" rtype_mnemonic_forwards RISCV_XOR = ( (''xor''))"
+|" rtype_mnemonic_forwards RISCV_SLL = ( (''sll''))"
+|" rtype_mnemonic_forwards RISCV_SRL = ( (''srl''))"
+|" rtype_mnemonic_forwards RISCV_SUB = ( (''sub''))"
+|" rtype_mnemonic_forwards RISCV_SRA = ( (''sra''))"
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_backwards : string -> M rop\<close>\<close>
+
+definition rtype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(rop),(exception))monad " where
+ " rtype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''add'')))) then return RISCV_ADD
+ else if (((p00 = (''slt'')))) then return RISCV_SLT
+ else if (((p00 = (''sltu'')))) then return RISCV_SLTU
+ else if (((p00 = (''and'')))) then return RISCV_AND
+ else if (((p00 = (''or'')))) then return RISCV_OR
+ else if (((p00 = (''xor'')))) then return RISCV_XOR
+ else if (((p00 = (''sll'')))) then return RISCV_SLL
+ else if (((p00 = (''srl'')))) then return RISCV_SRL
+ else if (((p00 = (''sub'')))) then return RISCV_SUB
+ else if (((p00 = (''sra'')))) then return RISCV_SRA
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_forwards_matches : rop -> bool\<close>\<close>
+
+fun rtype_mnemonic_forwards_matches :: " rop \<Rightarrow> bool " where
+ " rtype_mnemonic_forwards_matches RISCV_ADD = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLT = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLTU = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_AND = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_OR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_XOR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SUB = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRA = ( True )"
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition rtype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " rtype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''add'')))) then True
+ else if (((p00 = (''slt'')))) then True
+ else if (((p00 = (''sltu'')))) then True
+ else if (((p00 = (''and'')))) then True
+ else if (((p00 = (''or'')))) then True
+ else if (((p00 = (''xor'')))) then True
+ else if (((p00 = (''sll'')))) then True
+ else if (((p00 = (''srl'')))) then True
+ else if (((p00 = (''sub'')))) then True
+ else if (((p00 = (''sra'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s596_ : string -> maybe string\<close>\<close>
+
+definition s596 :: " string \<Rightarrow>(string)option " where
+ " s596 s5970 = (
+ (let s5980 = s5970 in
+ if ((string_startswith s5980 (''sra''))) then
+ (case ((string_drop s5980 ((string_length (''sra''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5970 :: " string "
+
+
+\<comment> \<open>\<open>val _s592_ : string -> maybe string\<close>\<close>
+
+definition s592 :: " string \<Rightarrow>(string)option " where
+ " s592 s5930 = (
+ (let s5940 = s5930 in
+ if ((string_startswith s5940 (''sub''))) then
+ (case ((string_drop s5940 ((string_length (''sub''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5930 :: " string "
+
+
+\<comment> \<open>\<open>val _s588_ : string -> maybe string\<close>\<close>
+
+definition s588 :: " string \<Rightarrow>(string)option " where
+ " s588 s5890 = (
+ (let s5900 = s5890 in
+ if ((string_startswith s5900 (''srl''))) then
+ (case ((string_drop s5900 ((string_length (''srl''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5890 :: " string "
+
+
+\<comment> \<open>\<open>val _s584_ : string -> maybe string\<close>\<close>
+
+definition s584 :: " string \<Rightarrow>(string)option " where
+ " s584 s5850 = (
+ (let s5860 = s5850 in
+ if ((string_startswith s5860 (''sll''))) then
+ (case ((string_drop s5860 ((string_length (''sll''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5850 :: " string "
+
+
+\<comment> \<open>\<open>val _s580_ : string -> maybe string\<close>\<close>
+
+definition s580 :: " string \<Rightarrow>(string)option " where
+ " s580 s5810 = (
+ (let s5820 = s5810 in
+ if ((string_startswith s5820 (''xor''))) then
+ (case ((string_drop s5820 ((string_length (''xor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5810 :: " string "
+
+
+\<comment> \<open>\<open>val _s576_ : string -> maybe string\<close>\<close>
+
+definition s576 :: " string \<Rightarrow>(string)option " where
+ " s576 s5770 = (
+ (let s5780 = s5770 in
+ if ((string_startswith s5780 (''or''))) then
+ (case ((string_drop s5780 ((string_length (''or''))))) of s1 => Some s1 )
+ else None))"
+ for s5770 :: " string "
+
+
+\<comment> \<open>\<open>val _s572_ : string -> maybe string\<close>\<close>
+
+definition s572 :: " string \<Rightarrow>(string)option " where
+ " s572 s5730 = (
+ (let s5740 = s5730 in
+ if ((string_startswith s5740 (''and''))) then
+ (case ((string_drop s5740 ((string_length (''and''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5730 :: " string "
+
+
+\<comment> \<open>\<open>val _s568_ : string -> maybe string\<close>\<close>
+
+definition s568 :: " string \<Rightarrow>(string)option " where
+ " s568 s5690 = (
+ (let s5700 = s5690 in
+ if ((string_startswith s5700 (''sltu''))) then
+ (case ((string_drop s5700 ((string_length (''sltu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5690 :: " string "
+
+
+\<comment> \<open>\<open>val _s564_ : string -> maybe string\<close>\<close>
+
+definition s564 :: " string \<Rightarrow>(string)option " where
+ " s564 s5650 = (
+ (let s5660 = s5650 in
+ if ((string_startswith s5660 (''slt''))) then
+ (case ((string_drop s5660 ((string_length (''slt''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5650 :: " string "
+
+
+\<comment> \<open>\<open>val _s560_ : string -> maybe string\<close>\<close>
+
+definition s560 :: " string \<Rightarrow>(string)option " where
+ " s560 s5610 = (
+ (let s5620 = s5610 in
+ if ((string_startswith s5620 (''add''))) then
+ (case ((string_drop s5620 ((string_length (''add''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5610 :: " string "
+
+
+definition rtype_mnemonic_matches_prefix :: " string \<Rightarrow>(rop*int)option " where
+ " rtype_mnemonic_matches_prefix arg1 = (
+ (let s5630 = arg1 in
+ if ((case ((s560 s5630)) of Some (s1) => True | _ => False )) then
+ (case s560 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_ADD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s564 s5630)) of Some (s1) => True | _ => False )) then
+ (case s564 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLT, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s568 s5630)) of Some (s1) => True | _ => False )) then
+ (case s568 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLTU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s572 s5630)) of Some (s1) => True | _ => False )) then
+ (case s572 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_AND, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s576 s5630)) of Some (s1) => True | _ => False )) then
+ (case s576 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_OR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s580 s5630)) of Some (s1) => True | _ => False )) then
+ (case s580 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_XOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s584 s5630)) of Some (s1) => True | _ => False )) then
+ (case s584 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLL, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s588 s5630)) of Some (s1) => True | _ => False )) then
+ (case s588 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SRL, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s592 s5630)) of Some (s1) => True | _ => False )) then
+ (case s592 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SUB, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s596 s5630)) of Some (s1) => True | _ => False )) then
+ (case s596 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SRA, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val extend_value : forall 'int8_times_n. Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty32)\<close>\<close>
+
+fun extend_value :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow>((32)Word.word)MemoryOpResult " where
+ " extend_value is_unsigned (MemValue (v)) = (
+ MemValue (if is_unsigned then (EXTZ (( 32 :: int)::ii) v :: 32 Word.word)
+ else (EXTS (( 32 :: int)::ii) v :: 32 Word.word)))"
+ for is_unsigned :: " bool "
+ and v :: "('int8_times_n::len)Word.word "
+|" extend_value is_unsigned (MemException (e)) = ( MemException e )"
+ for is_unsigned :: " bool "
+ and e :: " ExceptionType "
+
+
+\<comment> \<open>\<open>val process_load : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty32 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired\<close>\<close>
+
+definition process_load :: "(5)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " process_load rd addr value1 is_unsigned = (
+ (case ((extend_value is_unsigned value1 :: ( 32 Word.word) MemoryOpResult)) of
+ MemValue (result) => wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ ))"
+ for rd :: "(5)Word.word "
+ and addr :: "(32)Word.word "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+ and is_unsigned :: " bool "
+
+
+\<comment> \<open>\<open>val check_misaligned : mword ty32 -> word_width -> bool\<close>\<close>
+
+definition check_misaligned :: "(32)Word.word \<Rightarrow> word_width \<Rightarrow> bool " where
+ " check_misaligned (vaddr :: xlenbits) (width :: word_width) = (
+ if ((plat_enable_misaligned_access () )) then False
+ else
+ (case width of
+ BYTE => False
+ | HALF => (((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True)
+ | WORD =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True))) \<or> (((((bit_to_bool ((access_vec_dec vaddr (( 1 :: int)::ii))))) = True))))
+ | DOUBLE =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True))) \<or> ((((((((bit_to_bool ((access_vec_dec vaddr (( 1 :: int)::ii))))) = True))) \<or> (((((bit_to_bool ((access_vec_dec vaddr (( 2 :: int)::ii))))) = True)))))))
+ ))"
+ for vaddr :: "(32)Word.word "
+ and width :: " word_width "
+
+
+\<comment> \<open>\<open>val maybe_aq_forwards : bool -> string\<close>\<close>
+
+fun maybe_aq_forwards :: " bool \<Rightarrow> string " where
+ " maybe_aq_forwards True = ( (''.aq''))"
+|" maybe_aq_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_aq_backwards : string -> M bool\<close>\<close>
+
+definition maybe_aq_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_aq_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.aq'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_aq_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_aq_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_aq_forwards_matches True = ( True )"
+|" maybe_aq_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_aq_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_aq_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_aq_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.aq'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_aq_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s604_ : string -> maybe string\<close>\<close>
+
+definition s604 :: " string \<Rightarrow>(string)option " where
+ " s604 s6050 = (
+ (let s6060 = s6050 in
+ if ((string_startswith s6060 (''''))) then
+ (case ((string_drop s6060 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6050 :: " string "
+
+
+\<comment> \<open>\<open>val _s600_ : string -> maybe string\<close>\<close>
+
+definition s600 :: " string \<Rightarrow>(string)option " where
+ " s600 s6010 = (
+ (let s6020 = s6010 in
+ if ((string_startswith s6020 (''.aq''))) then
+ (case ((string_drop s6020 ((string_length (''.aq''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6010 :: " string "
+
+
+definition maybe_aq_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_aq_matches_prefix arg1 = (
+ (let s6030 = arg1 in
+ if ((case ((s600 s6030)) of Some (s1) => True | _ => False )) then
+ (case s600 s6030 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s604 s6030)) of Some (s1) => True | _ => False )) then
+ (case s604 s6030 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_forwards : bool -> string\<close>\<close>
+
+fun maybe_rl_forwards :: " bool \<Rightarrow> string " where
+ " maybe_rl_forwards True = ( (''.rl''))"
+|" maybe_rl_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_rl_backwards : string -> M bool\<close>\<close>
+
+definition maybe_rl_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_rl_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.rl'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_rl_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_rl_forwards_matches True = ( True )"
+|" maybe_rl_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_rl_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_rl_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_rl_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.rl'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s612_ : string -> maybe string\<close>\<close>
+
+definition s612 :: " string \<Rightarrow>(string)option " where
+ " s612 s6130 = (
+ (let s6140 = s6130 in
+ if ((string_startswith s6140 (''''))) then
+ (case ((string_drop s6140 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6130 :: " string "
+
+
+\<comment> \<open>\<open>val _s608_ : string -> maybe string\<close>\<close>
+
+definition s608 :: " string \<Rightarrow>(string)option " where
+ " s608 s6090 = (
+ (let s6100 = s6090 in
+ if ((string_startswith s6100 (''.rl''))) then
+ (case ((string_drop s6100 ((string_length (''.rl''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6090 :: " string "
+
+
+definition maybe_rl_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_rl_matches_prefix arg1 = (
+ (let s6110 = arg1 in
+ if ((case ((s608 s6110)) of Some (s1) => True | _ => False )) then
+ (case s608 s6110 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s612 s6110)) of Some (s1) => True | _ => False )) then
+ (case s612 s6110 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_forwards : bool -> string\<close>\<close>
+
+fun maybe_u_forwards :: " bool \<Rightarrow> string " where
+ " maybe_u_forwards True = ( (''u''))"
+|" maybe_u_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_u_backwards : string -> M bool\<close>\<close>
+
+definition maybe_u_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_u_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_u_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_u_forwards_matches True = ( True )"
+|" maybe_u_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_u_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_u_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_u_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s620_ : string -> maybe string\<close>\<close>
+
+definition s620 :: " string \<Rightarrow>(string)option " where
+ " s620 s6210 = (
+ (let s6220 = s6210 in
+ if ((string_startswith s6220 (''''))) then
+ (case ((string_drop s6220 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6210 :: " string "
+
+
+\<comment> \<open>\<open>val _s616_ : string -> maybe string\<close>\<close>
+
+definition s616 :: " string \<Rightarrow>(string)option " where
+ " s616 s6170 = (
+ (let s6180 = s6170 in
+ if ((string_startswith s6180 (''u''))) then
+ (case ((string_drop s6180 ((string_length (''u''))))) of s1 => Some s1 )
+ else None))"
+ for s6170 :: " string "
+
+
+definition maybe_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_u_matches_prefix arg1 = (
+ (let s6190 = arg1 in
+ if ((case ((s616 s6190)) of Some (s1) => True | _ => False )) then
+ (case s616 s6190 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s620 s6190)) of Some (s1) => True | _ => False )) then
+ (case s620 s6190 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_forwards : sop -> string\<close>\<close>
+
+fun shiftw_mnemonic_forwards :: " sop \<Rightarrow> string " where
+ " shiftw_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftw_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftw_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_backwards : string -> M sop\<close>\<close>
+
+definition shiftw_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " shiftw_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then return RISCV_SLLI
+ else if (((p00 = (''srli'')))) then return RISCV_SRLI
+ else if (((p00 = (''srai'')))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_forwards_matches : sop -> bool\<close>\<close>
+
+fun shiftw_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where
+ " shiftw_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftw_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftw_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then True
+ else if (((p00 = (''srli'')))) then True
+ else if (((p00 = (''srai'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s632_ : string -> maybe string\<close>\<close>
+
+definition s632 :: " string \<Rightarrow>(string)option " where
+ " s632 s6330 = (
+ (let s6340 = s6330 in
+ if ((string_startswith s6340 (''srai''))) then
+ (case ((string_drop s6340 ((string_length (''srai''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6330 :: " string "
+
+
+\<comment> \<open>\<open>val _s628_ : string -> maybe string\<close>\<close>
+
+definition s628 :: " string \<Rightarrow>(string)option " where
+ " s628 s6290 = (
+ (let s6300 = s6290 in
+ if ((string_startswith s6300 (''srli''))) then
+ (case ((string_drop s6300 ((string_length (''srli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6290 :: " string "
+
+
+\<comment> \<open>\<open>val _s624_ : string -> maybe string\<close>\<close>
+
+definition s624 :: " string \<Rightarrow>(string)option " where
+ " s624 s6250 = (
+ (let s6260 = s6250 in
+ if ((string_startswith s6260 (''slli''))) then
+ (case ((string_drop s6260 ((string_length (''slli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6250 :: " string "
+
+
+definition shiftw_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where
+ " shiftw_mnemonic_matches_prefix arg1 = (
+ (let s6270 = arg1 in
+ if ((case ((s624 s6270)) of Some (s1) => True | _ => False )) then
+ (case s624 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SLLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s628 s6270)) of Some (s1) => True | _ => False )) then
+ (case s628 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SRLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s632 s6270)) of Some (s1) => True | _ => False )) then
+ (case s632 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SRAI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_forwards : ropw -> string\<close>\<close>
+
+fun rtypew_mnemonic_forwards :: " ropw \<Rightarrow> string " where
+ " rtypew_mnemonic_forwards RISCV_ADDW = ( (''addw''))"
+|" rtypew_mnemonic_forwards RISCV_SUBW = ( (''subw''))"
+|" rtypew_mnemonic_forwards RISCV_SLLW = ( (''sllw''))"
+|" rtypew_mnemonic_forwards RISCV_SRLW = ( (''srlw''))"
+|" rtypew_mnemonic_forwards RISCV_SRAW = ( (''sraw''))"
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_backwards : string -> M ropw\<close>\<close>
+
+definition rtypew_mnemonic_backwards :: " string \<Rightarrow>((register_value),(ropw),(exception))monad " where
+ " rtypew_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addw'')))) then return RISCV_ADDW
+ else if (((p00 = (''subw'')))) then return RISCV_SUBW
+ else if (((p00 = (''sllw'')))) then return RISCV_SLLW
+ else if (((p00 = (''srlw'')))) then return RISCV_SRLW
+ else if (((p00 = (''sraw'')))) then return RISCV_SRAW
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_forwards_matches : ropw -> bool\<close>\<close>
+
+fun rtypew_mnemonic_forwards_matches :: " ropw \<Rightarrow> bool " where
+ " rtypew_mnemonic_forwards_matches RISCV_ADDW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SUBW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SLLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRAW = ( True )"
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition rtypew_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " rtypew_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addw'')))) then True
+ else if (((p00 = (''subw'')))) then True
+ else if (((p00 = (''sllw'')))) then True
+ else if (((p00 = (''srlw'')))) then True
+ else if (((p00 = (''sraw'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s652_ : string -> maybe string\<close>\<close>
+
+definition s652 :: " string \<Rightarrow>(string)option " where
+ " s652 s6530 = (
+ (let s6540 = s6530 in
+ if ((string_startswith s6540 (''sraw''))) then
+ (case ((string_drop s6540 ((string_length (''sraw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6530 :: " string "
+
+
+\<comment> \<open>\<open>val _s648_ : string -> maybe string\<close>\<close>
+
+definition s648 :: " string \<Rightarrow>(string)option " where
+ " s648 s6490 = (
+ (let s6500 = s6490 in
+ if ((string_startswith s6500 (''srlw''))) then
+ (case ((string_drop s6500 ((string_length (''srlw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6490 :: " string "
+
+
+\<comment> \<open>\<open>val _s644_ : string -> maybe string\<close>\<close>
+
+definition s644 :: " string \<Rightarrow>(string)option " where
+ " s644 s6450 = (
+ (let s6460 = s6450 in
+ if ((string_startswith s6460 (''sllw''))) then
+ (case ((string_drop s6460 ((string_length (''sllw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6450 :: " string "
+
+
+\<comment> \<open>\<open>val _s640_ : string -> maybe string\<close>\<close>
+
+definition s640 :: " string \<Rightarrow>(string)option " where
+ " s640 s6410 = (
+ (let s6420 = s6410 in
+ if ((string_startswith s6420 (''subw''))) then
+ (case ((string_drop s6420 ((string_length (''subw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6410 :: " string "
+
+
+\<comment> \<open>\<open>val _s636_ : string -> maybe string\<close>\<close>
+
+definition s636 :: " string \<Rightarrow>(string)option " where
+ " s636 s6370 = (
+ (let s6380 = s6370 in
+ if ((string_startswith s6380 (''addw''))) then
+ (case ((string_drop s6380 ((string_length (''addw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6370 :: " string "
+
+
+definition rtypew_mnemonic_matches_prefix :: " string \<Rightarrow>(ropw*int)option " where
+ " rtypew_mnemonic_matches_prefix arg1 = (
+ (let s6390 = arg1 in
+ if ((case ((s636 s6390)) of Some (s1) => True | _ => False )) then
+ (case s636 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_ADDW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s640 s6390)) of Some (s1) => True | _ => False )) then
+ (case s640 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SUBW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s644 s6390)) of Some (s1) => True | _ => False )) then
+ (case s644 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SLLW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s648 s6390)) of Some (s1) => True | _ => False )) then
+ (case s648 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SRLW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s652 s6390)) of Some (s1) => True | _ => False )) then
+ (case s652 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SRAW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_forwards : sopw -> string\<close>\<close>
+
+fun shiftiwop_mnemonic_forwards :: " sopw \<Rightarrow> string " where
+ " shiftiwop_mnemonic_forwards RISCV_SLLIW = ( (''slliw''))"
+|" shiftiwop_mnemonic_forwards RISCV_SRLIW = ( (''srliw''))"
+|" shiftiwop_mnemonic_forwards RISCV_SRAIW = ( (''sraiw''))"
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_backwards : string -> M sopw\<close>\<close>
+
+definition shiftiwop_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sopw),(exception))monad " where
+ " shiftiwop_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slliw'')))) then return RISCV_SLLIW
+ else if (((p00 = (''srliw'')))) then return RISCV_SRLIW
+ else if (((p00 = (''sraiw'')))) then return RISCV_SRAIW
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_forwards_matches : sopw -> bool\<close>\<close>
+
+fun shiftiwop_mnemonic_forwards_matches :: " sopw \<Rightarrow> bool " where
+ " shiftiwop_mnemonic_forwards_matches RISCV_SLLIW = ( True )"
+|" shiftiwop_mnemonic_forwards_matches RISCV_SRLIW = ( True )"
+|" shiftiwop_mnemonic_forwards_matches RISCV_SRAIW = ( True )"
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftiwop_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftiwop_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slliw'')))) then True
+ else if (((p00 = (''srliw'')))) then True
+ else if (((p00 = (''sraiw'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_matches_prefix : string -> maybe ((sopw * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s664_ : string -> maybe string\<close>\<close>
+
+definition s664 :: " string \<Rightarrow>(string)option " where
+ " s664 s6650 = (
+ (let s6660 = s6650 in
+ if ((string_startswith s6660 (''sraiw''))) then
+ (case ((string_drop s6660 ((string_length (''sraiw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6650 :: " string "
+
+
+\<comment> \<open>\<open>val _s660_ : string -> maybe string\<close>\<close>
+
+definition s660 :: " string \<Rightarrow>(string)option " where
+ " s660 s6610 = (
+ (let s6620 = s6610 in
+ if ((string_startswith s6620 (''srliw''))) then
+ (case ((string_drop s6620 ((string_length (''srliw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6610 :: " string "
+
+
+\<comment> \<open>\<open>val _s656_ : string -> maybe string\<close>\<close>
+
+definition s656 :: " string \<Rightarrow>(string)option " where
+ " s656 s6570 = (
+ (let s6580 = s6570 in
+ if ((string_startswith s6580 (''slliw''))) then
+ (case ((string_drop s6580 ((string_length (''slliw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6570 :: " string "
+
+
+definition shiftiwop_mnemonic_matches_prefix :: " string \<Rightarrow>(sopw*int)option " where
+ " shiftiwop_mnemonic_matches_prefix arg1 = (
+ (let s6590 = arg1 in
+ if ((case ((s656 s6590)) of Some (s1) => True | _ => False )) then
+ (case s656 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SLLIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s660 s6590)) of Some (s1) => True | _ => False )) then
+ (case s660 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SRLIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s664 s6590)) of Some (s1) => True | _ => False )) then
+ (case s664 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SRAIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_r_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_r_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''r'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_r_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_r_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''r'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_r_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_r_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_r_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_r_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''r'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s672_ : string -> maybe string\<close>\<close>
+
+definition s672 :: " string \<Rightarrow>(string)option " where
+ " s672 s6730 = (
+ (let s6740 = s6730 in
+ if ((string_startswith s6740 (''''))) then
+ (case ((string_drop s6740 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6730 :: " string "
+
+
+\<comment> \<open>\<open>val _s668_ : string -> maybe string\<close>\<close>
+
+definition s668 :: " string \<Rightarrow>(string)option " where
+ " s668 s6690 = (
+ (let s6700 = s6690 in
+ if ((string_startswith s6700 (''r''))) then
+ (case ((string_drop s6700 ((string_length (''r''))))) of s1 => Some s1 )
+ else None))"
+ for s6690 :: " string "
+
+
+definition bit_maybe_r_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_r_matches_prefix arg1 = (
+ (let s6710 = arg1 in
+ if ((case ((s668 s6710)) of Some (s1) => True | _ => False )) then
+ (case s668 s6710 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s672 s6710)) of Some (s1) => True | _ => False )) then
+ (case s672 s6710 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_w_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_w_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''w'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_w_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_w_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''w'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_w_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_w_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_w_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_w_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''w'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s680_ : string -> maybe string\<close>\<close>
+
+definition s680 :: " string \<Rightarrow>(string)option " where
+ " s680 s6810 = (
+ (let s6820 = s6810 in
+ if ((string_startswith s6820 (''''))) then
+ (case ((string_drop s6820 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6810 :: " string "
+
+
+\<comment> \<open>\<open>val _s676_ : string -> maybe string\<close>\<close>
+
+definition s676 :: " string \<Rightarrow>(string)option " where
+ " s676 s6770 = (
+ (let s6780 = s6770 in
+ if ((string_startswith s6780 (''w''))) then
+ (case ((string_drop s6780 ((string_length (''w''))))) of s1 => Some s1 )
+ else None))"
+ for s6770 :: " string "
+
+
+definition bit_maybe_w_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_w_matches_prefix arg1 = (
+ (let s6790 = arg1 in
+ if ((case ((s676 s6790)) of Some (s1) => True | _ => False )) then
+ (case s676 s6790 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s680 s6790)) of Some (s1) => True | _ => False )) then
+ (case s680 s6790 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_i_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_i_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''i'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_i_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_i_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_i_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_i_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_i_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_i_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s688_ : string -> maybe string\<close>\<close>
+
+definition s688 :: " string \<Rightarrow>(string)option " where
+ " s688 s6890 = (
+ (let s6900 = s6890 in
+ if ((string_startswith s6900 (''''))) then
+ (case ((string_drop s6900 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6890 :: " string "
+
+
+\<comment> \<open>\<open>val _s684_ : string -> maybe string\<close>\<close>
+
+definition s684 :: " string \<Rightarrow>(string)option " where
+ " s684 s6850 = (
+ (let s6860 = s6850 in
+ if ((string_startswith s6860 (''i''))) then
+ (case ((string_drop s6860 ((string_length (''i''))))) of s1 => Some s1 )
+ else None))"
+ for s6850 :: " string "
+
+
+definition bit_maybe_i_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_i_matches_prefix arg1 = (
+ (let s6870 = arg1 in
+ if ((case ((s684 s6870)) of Some (s1) => True | _ => False )) then
+ (case s684 s6870 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s688 s6870)) of Some (s1) => True | _ => False )) then
+ (case s688 s6870 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_o_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_o_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''o'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_o_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_o_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''o'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_o_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_o_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_o_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_o_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''o'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s696_ : string -> maybe string\<close>\<close>
+
+definition s696 :: " string \<Rightarrow>(string)option " where
+ " s696 s6970 = (
+ (let s6980 = s6970 in
+ if ((string_startswith s6980 (''''))) then
+ (case ((string_drop s6980 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6970 :: " string "
+
+
+\<comment> \<open>\<open>val _s692_ : string -> maybe string\<close>\<close>
+
+definition s692 :: " string \<Rightarrow>(string)option " where
+ " s692 s6930 = (
+ (let s6940 = s6930 in
+ if ((string_startswith s6940 (''o''))) then
+ (case ((string_drop s6940 ((string_length (''o''))))) of s1 => Some s1 )
+ else None))"
+ for s6930 :: " string "
+
+
+definition bit_maybe_o_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_o_matches_prefix arg1 = (
+ (let s6950 = arg1 in
+ if ((case ((s692 s6950)) of Some (s1) => True | _ => False )) then
+ (case s692 s6950 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s696 s6950)) of Some (s1) => True | _ => False )) then
+ (case s696 s6950 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_forwards : mword ty4 -> M string\<close>\<close>
+
+definition fence_bits_forwards :: "(4)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " fence_bits_forwards v__0 = (
+ (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (w :: 1 bits) = ((subrange_vec_dec v__0 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (let (r :: 1 bits) = ((subrange_vec_dec v__0 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (o1 :: 1 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ bit_maybe_i_forwards i \<bind> (\<lambda> (w__0 :: string) .
+ bit_maybe_o_forwards o1 \<bind> (\<lambda> (w__1 :: string) .
+ bit_maybe_r_forwards r \<bind> (\<lambda> (w__2 :: string) .
+ bit_maybe_w_forwards w \<bind> (\<lambda> (w__3 :: string) .
+ return ((string_append w__0
+ ((string_append w__1 ((string_append w__2 ((string_append w__3 ('''')))))))))))))))))))"
+ for v__0 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val fence_bits_backwards : string -> M (mword ty4)\<close>\<close>
+
+\<comment> \<open>\<open>val _s700_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))\<close>\<close>
+
+definition s700 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word)option " where
+ " s700 s7020 = (
+ (case ((bit_maybe_i_matches_prefix s7020 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7030)) =>
+ (case ((string_drop s7020 s7030)) of
+ s7040 =>
+ (case ((bit_maybe_o_matches_prefix s7040 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7050)) =>
+ (case ((string_drop s7040 s7050)) of
+ s7060 =>
+ (case ((bit_maybe_r_matches_prefix s7060 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7070)) =>
+ (case ((string_drop s7060 s7070)) of
+ s7080 =>
+ (case ((bit_maybe_w_matches_prefix s7080 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7090)) =>
+ (let p00 = (string_drop s7080 s7090) in
+ if (((p00 = ('''')))) then Some (i, o1, r, w) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7020 :: " string "
+
+
+definition fence_bits_backwards :: " string \<Rightarrow>((register_value),((4)Word.word),(exception))monad " where
+ " fence_bits_backwards arg1 = (
+ (let s7100 = arg1 in
+ if ((case ((s700 s7100 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word))option)) of
+ Some ((i, o1, r, w)) => True
+ | _ => False
+ )) then (case
+ (s700 s7100 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word)) option) of
+ (Some ((i, o1, r, w))) =>
+ return
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w :: 2 Word.word)) :: 3 Word.word))
+ :: 4 Word.word))
+ )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_forwards_matches : mword ty4 -> bool\<close>\<close>
+
+definition fence_bits_forwards_matches :: "(4)Word.word \<Rightarrow> bool " where
+ " fence_bits_forwards_matches v__1 = ( True )"
+ for v__1 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val fence_bits_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s711_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))\<close>\<close>
+
+definition s711 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word)option " where
+ " s711 s7130 = (
+ (case ((bit_maybe_i_matches_prefix s7130 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7140)) =>
+ (case ((string_drop s7130 s7140)) of
+ s7150 =>
+ (case ((bit_maybe_o_matches_prefix s7150 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7160)) =>
+ (case ((string_drop s7150 s7160)) of
+ s7170 =>
+ (case ((bit_maybe_r_matches_prefix s7170 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7180)) =>
+ (case ((string_drop s7170 s7180)) of
+ s7190 =>
+ (case ((bit_maybe_w_matches_prefix s7190 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7200)) =>
+ (let p00 = (string_drop s7190 s7200) in
+ if (((p00 = ('''')))) then Some (i, o1, r, w) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7130 :: " string "
+
+
+definition fence_bits_backwards_matches :: " string \<Rightarrow> bool " where
+ " fence_bits_backwards_matches arg1 = (
+ (let s7210 = arg1 in
+ if ((case ((s711 s7210 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word))option)) of
+ Some ((i, o1, r, w)) => True
+ | _ => False
+ )) then (case
+ (s711 s7210 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word)) option) of
+ (Some ((i, o1, r, w))) =>
+ True
+ )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s722_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1 * string))\<close>\<close>
+
+definition s722 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word*string)option " where
+ " s722 s7240 = (
+ (case ((bit_maybe_i_matches_prefix s7240 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7250)) =>
+ (case ((string_drop s7240 s7250)) of
+ s7260 =>
+ (case ((bit_maybe_o_matches_prefix s7260 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7270)) =>
+ (case ((string_drop s7260 s7270)) of
+ s7280 =>
+ (case ((bit_maybe_r_matches_prefix s7280 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7290)) =>
+ (case ((string_drop s7280 s7290)) of
+ s7300 =>
+ (case ((bit_maybe_w_matches_prefix s7300 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7310)) =>
+ (case ((string_drop s7300 s7310)) of s1 => Some (i, o1, r, w, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7240 :: " string "
+
+
+definition fence_bits_matches_prefix :: " string \<Rightarrow>((4)Word.word*int)option " where
+ " fence_bits_matches_prefix arg1 = (
+ (let s7320 = arg1 in
+ if ((case ((s722 s7320 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word * string))option)) of
+ Some ((i, o1, r, w, s1)) => True
+ | _ => False
+ )) then (case
+ (s722 s7320 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word * string)) option) of
+ (Some ((i, o1, r, w, s1))) =>
+ Some
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w :: 2 Word.word)) :: 3 Word.word)) :: 4 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val aqrl_str : bool -> bool -> string\<close>\<close>
+
+fun aqrl_str :: " bool \<Rightarrow> bool \<Rightarrow> string " where
+ " aqrl_str (False :: bool) (False :: bool) = ( (''''))"
+|" aqrl_str (False :: bool) (True :: bool) = ( (''.rl''))"
+|" aqrl_str (True :: bool) (False :: bool) = ( (''.aq''))"
+|" aqrl_str (True :: bool) (True :: bool) = ( (''.aqrl''))"
+
+
+\<comment> \<open>\<open>val lrsc_width_str : word_width -> string\<close>\<close>
+
+fun lrsc_width_str :: " word_width \<Rightarrow> string " where
+ " lrsc_width_str BYTE = ( (''.b''))"
+|" lrsc_width_str HALF = ( (''.h''))"
+|" lrsc_width_str WORD = ( (''.w''))"
+|" lrsc_width_str DOUBLE = ( (''.d''))"
+
+
+\<comment> \<open>\<open>val process_loadres : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty32 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired\<close>\<close>
+
+definition process_loadres :: "(5)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " process_loadres rd addr value1 is_unsigned = (
+ (case ((extend_value is_unsigned value1 :: ( 32 Word.word) MemoryOpResult)) of
+ MemValue (result) =>
+ (let (_ :: unit) = (load_reservation addr) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS)
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ ))"
+ for rd :: "(5)Word.word "
+ and addr :: "(32)Word.word "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+ and is_unsigned :: " bool "
+
+
+\<comment> \<open>\<open>val encdec_amoop_forwards : amoop -> mword ty5\<close>\<close>
+
+fun encdec_amoop_forwards :: " amoop \<Rightarrow>(5)Word.word " where
+ " encdec_amoop_forwards AMOSWAP = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOADD = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOXOR = ( (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOAND = ( (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOOR = ( (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMIN = ( (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMAX = ( (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMINU = ( (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMAXU = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_amoop_backwards : mword ty5 -> M amoop\<close>\<close>
+
+definition encdec_amoop_backwards :: "(5)Word.word \<Rightarrow>((register_value),(amoop),(exception))monad " where
+ " encdec_amoop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))
+ then
+ return AMOSWAP
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOADD
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOXOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOAND
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOMIN
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOMAX
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOMINU
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOMAXU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_amoop_forwards_matches : amoop -> bool\<close>\<close>
+
+fun encdec_amoop_forwards_matches :: " amoop \<Rightarrow> bool " where
+ " encdec_amoop_forwards_matches AMOSWAP = ( True )"
+|" encdec_amoop_forwards_matches AMOADD = ( True )"
+|" encdec_amoop_forwards_matches AMOXOR = ( True )"
+|" encdec_amoop_forwards_matches AMOAND = ( True )"
+|" encdec_amoop_forwards_matches AMOOR = ( True )"
+|" encdec_amoop_forwards_matches AMOMIN = ( True )"
+|" encdec_amoop_forwards_matches AMOMAX = ( True )"
+|" encdec_amoop_forwards_matches AMOMINU = ( True )"
+|" encdec_amoop_forwards_matches AMOMAXU = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_amoop_backwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition encdec_amoop_backwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " encdec_amoop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))
+ then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else False))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_forwards : amoop -> string\<close>\<close>
+
+fun amo_mnemonic_forwards :: " amoop \<Rightarrow> string " where
+ " amo_mnemonic_forwards AMOSWAP = ( (''amoswap''))"
+|" amo_mnemonic_forwards AMOADD = ( (''amoadd''))"
+|" amo_mnemonic_forwards AMOXOR = ( (''amoxor''))"
+|" amo_mnemonic_forwards AMOAND = ( (''amoand''))"
+|" amo_mnemonic_forwards AMOOR = ( (''amoor''))"
+|" amo_mnemonic_forwards AMOMIN = ( (''amomin''))"
+|" amo_mnemonic_forwards AMOMAX = ( (''amomax''))"
+|" amo_mnemonic_forwards AMOMINU = ( (''amominu''))"
+|" amo_mnemonic_forwards AMOMAXU = ( (''amomaxu''))"
+
+
+\<comment> \<open>\<open>val amo_mnemonic_backwards : string -> M amoop\<close>\<close>
+
+definition amo_mnemonic_backwards :: " string \<Rightarrow>((register_value),(amoop),(exception))monad " where
+ " amo_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''amoswap'')))) then return AMOSWAP
+ else if (((p00 = (''amoadd'')))) then return AMOADD
+ else if (((p00 = (''amoxor'')))) then return AMOXOR
+ else if (((p00 = (''amoand'')))) then return AMOAND
+ else if (((p00 = (''amoor'')))) then return AMOOR
+ else if (((p00 = (''amomin'')))) then return AMOMIN
+ else if (((p00 = (''amomax'')))) then return AMOMAX
+ else if (((p00 = (''amominu'')))) then return AMOMINU
+ else if (((p00 = (''amomaxu'')))) then return AMOMAXU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_forwards_matches : amoop -> bool\<close>\<close>
+
+fun amo_mnemonic_forwards_matches :: " amoop \<Rightarrow> bool " where
+ " amo_mnemonic_forwards_matches AMOSWAP = ( True )"
+|" amo_mnemonic_forwards_matches AMOADD = ( True )"
+|" amo_mnemonic_forwards_matches AMOXOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOAND = ( True )"
+|" amo_mnemonic_forwards_matches AMOOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOMIN = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAX = ( True )"
+|" amo_mnemonic_forwards_matches AMOMINU = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAXU = ( True )"
+
+
+\<comment> \<open>\<open>val amo_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition amo_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " amo_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''amoswap'')))) then True
+ else if (((p00 = (''amoadd'')))) then True
+ else if (((p00 = (''amoxor'')))) then True
+ else if (((p00 = (''amoand'')))) then True
+ else if (((p00 = (''amoor'')))) then True
+ else if (((p00 = (''amomin'')))) then True
+ else if (((p00 = (''amomax'')))) then True
+ else if (((p00 = (''amominu'')))) then True
+ else if (((p00 = (''amomaxu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s765_ : string -> maybe string\<close>\<close>
+
+definition s765 :: " string \<Rightarrow>(string)option " where
+ " s765 s7660 = (
+ (let s7670 = s7660 in
+ if ((string_startswith s7670 (''amomaxu''))) then
+ (case ((string_drop s7670 ((string_length (''amomaxu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7660 :: " string "
+
+
+\<comment> \<open>\<open>val _s761_ : string -> maybe string\<close>\<close>
+
+definition s761 :: " string \<Rightarrow>(string)option " where
+ " s761 s7620 = (
+ (let s7630 = s7620 in
+ if ((string_startswith s7630 (''amominu''))) then
+ (case ((string_drop s7630 ((string_length (''amominu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7620 :: " string "
+
+
+\<comment> \<open>\<open>val _s757_ : string -> maybe string\<close>\<close>
+
+definition s757 :: " string \<Rightarrow>(string)option " where
+ " s757 s7580 = (
+ (let s7590 = s7580 in
+ if ((string_startswith s7590 (''amomax''))) then
+ (case ((string_drop s7590 ((string_length (''amomax''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7580 :: " string "
+
+
+\<comment> \<open>\<open>val _s753_ : string -> maybe string\<close>\<close>
+
+definition s753 :: " string \<Rightarrow>(string)option " where
+ " s753 s7540 = (
+ (let s7550 = s7540 in
+ if ((string_startswith s7550 (''amomin''))) then
+ (case ((string_drop s7550 ((string_length (''amomin''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7540 :: " string "
+
+
+\<comment> \<open>\<open>val _s749_ : string -> maybe string\<close>\<close>
+
+definition s749 :: " string \<Rightarrow>(string)option " where
+ " s749 s7500 = (
+ (let s7510 = s7500 in
+ if ((string_startswith s7510 (''amoor''))) then
+ (case ((string_drop s7510 ((string_length (''amoor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7500 :: " string "
+
+
+\<comment> \<open>\<open>val _s745_ : string -> maybe string\<close>\<close>
+
+definition s745 :: " string \<Rightarrow>(string)option " where
+ " s745 s7460 = (
+ (let s7470 = s7460 in
+ if ((string_startswith s7470 (''amoand''))) then
+ (case ((string_drop s7470 ((string_length (''amoand''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7460 :: " string "
+
+
+\<comment> \<open>\<open>val _s741_ : string -> maybe string\<close>\<close>
+
+definition s741 :: " string \<Rightarrow>(string)option " where
+ " s741 s7420 = (
+ (let s7430 = s7420 in
+ if ((string_startswith s7430 (''amoxor''))) then
+ (case ((string_drop s7430 ((string_length (''amoxor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7420 :: " string "
+
+
+\<comment> \<open>\<open>val _s737_ : string -> maybe string\<close>\<close>
+
+definition s737 :: " string \<Rightarrow>(string)option " where
+ " s737 s7380 = (
+ (let s7390 = s7380 in
+ if ((string_startswith s7390 (''amoadd''))) then
+ (case ((string_drop s7390 ((string_length (''amoadd''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7380 :: " string "
+
+
+\<comment> \<open>\<open>val _s733_ : string -> maybe string\<close>\<close>
+
+definition s733 :: " string \<Rightarrow>(string)option " where
+ " s733 s7340 = (
+ (let s7350 = s7340 in
+ if ((string_startswith s7350 (''amoswap''))) then
+ (case ((string_drop s7350 ((string_length (''amoswap''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7340 :: " string "
+
+
+definition amo_mnemonic_matches_prefix :: " string \<Rightarrow>(amoop*int)option " where
+ " amo_mnemonic_matches_prefix arg1 = (
+ (let s7360 = arg1 in
+ if ((case ((s733 s7360)) of Some (s1) => True | _ => False )) then
+ (case s733 s7360 of
+ (Some (s1)) =>
+ Some (AMOSWAP, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s737 s7360)) of Some (s1) => True | _ => False )) then
+ (case s737 s7360 of
+ (Some (s1)) =>
+ Some (AMOADD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s741 s7360)) of Some (s1) => True | _ => False )) then
+ (case s741 s7360 of
+ (Some (s1)) =>
+ Some (AMOXOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s745 s7360)) of Some (s1) => True | _ => False )) then
+ (case s745 s7360 of
+ (Some (s1)) =>
+ Some (AMOAND, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s749 s7360)) of Some (s1) => True | _ => False )) then
+ (case s749 s7360 of
+ (Some (s1)) =>
+ Some (AMOOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s753 s7360)) of Some (s1) => True | _ => False )) then
+ (case s753 s7360 of
+ (Some (s1)) =>
+ Some (AMOMIN, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s757 s7360)) of Some (s1) => True | _ => False )) then
+ (case s757 s7360 of
+ (Some (s1)) =>
+ Some (AMOMAX, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s761 s7360)) of Some (s1) => True | _ => False )) then
+ (case s761 s7360 of
+ (Some (s1)) =>
+ Some (AMOMINU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s765 s7360)) of Some (s1) => True | _ => False )) then
+ (case s765 s7360 of
+ (Some (s1)) =>
+ Some (AMOMAXU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_mul_op_forwards : (bool * bool * bool) -> mword ty3\<close>\<close>
+
+fun encdec_mul_op_forwards :: " bool*bool*bool \<Rightarrow>(3)Word.word " where
+ " encdec_mul_op_forwards (False, True, True) = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, True, True) = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, True, False) = ( (vec_of_bits [B0,B1,B0] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, False, False) = ( (vec_of_bits [B0,B1,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_mul_op_backwards : mword ty3 -> M (bool * bool * bool)\<close>\<close>
+
+definition encdec_mul_op_backwards :: "(3)Word.word \<Rightarrow>((register_value),(bool*bool*bool),(exception))monad " where
+ " encdec_mul_op_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return (False, True, True)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return (True, True, True)
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return (True, True, False)
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return (True, False, False)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_mul_op_forwards_matches : (bool * bool * bool) -> bool\<close>\<close>
+
+fun encdec_mul_op_forwards_matches :: " bool*bool*bool \<Rightarrow> bool " where
+ " encdec_mul_op_forwards_matches (False, True, True) = ( True )"
+|" encdec_mul_op_forwards_matches (True, True, True) = ( True )"
+|" encdec_mul_op_forwards_matches (True, True, False) = ( True )"
+|" encdec_mul_op_forwards_matches (True, False, False) = ( True )"
+|" encdec_mul_op_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_mul_op_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_mul_op_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_mul_op_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_forwards : (bool * bool * bool) -> string\<close>\<close>
+
+fun mul_mnemonic_forwards :: " bool*bool*bool \<Rightarrow> string " where
+ " mul_mnemonic_forwards (False, True, True) = ( (''mul''))"
+|" mul_mnemonic_forwards (True, True, True) = ( (''mulh''))"
+|" mul_mnemonic_forwards (True, True, False) = ( (''mulhsu''))"
+|" mul_mnemonic_forwards (True, False, False) = ( (''mulhu''))"
+
+
+\<comment> \<open>\<open>val mul_mnemonic_backwards : string -> M (bool * bool * bool)\<close>\<close>
+
+definition mul_mnemonic_backwards :: " string \<Rightarrow>((register_value),(bool*bool*bool),(exception))monad " where
+ " mul_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''mul'')))) then return (False, True, True)
+ else if (((p00 = (''mulh'')))) then return (True, True, True)
+ else if (((p00 = (''mulhsu'')))) then return (True, True, False)
+ else if (((p00 = (''mulhu'')))) then return (True, False, False)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_forwards_matches : (bool * bool * bool) -> bool\<close>\<close>
+
+fun mul_mnemonic_forwards_matches :: " bool*bool*bool \<Rightarrow> bool " where
+ " mul_mnemonic_forwards_matches (False, True, True) = ( True )"
+|" mul_mnemonic_forwards_matches (True, True, True) = ( True )"
+|" mul_mnemonic_forwards_matches (True, True, False) = ( True )"
+|" mul_mnemonic_forwards_matches (True, False, False) = ( True )"
+|" mul_mnemonic_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val mul_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition mul_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " mul_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''mul'')))) then True
+ else if (((p00 = (''mulh'')))) then True
+ else if (((p00 = (''mulhsu'')))) then True
+ else if (((p00 = (''mulhu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s781_ : string -> maybe string\<close>\<close>
+
+definition s781 :: " string \<Rightarrow>(string)option " where
+ " s781 s7820 = (
+ (let s7830 = s7820 in
+ if ((string_startswith s7830 (''mulhu''))) then
+ (case ((string_drop s7830 ((string_length (''mulhu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7820 :: " string "
+
+
+\<comment> \<open>\<open>val _s777_ : string -> maybe string\<close>\<close>
+
+definition s777 :: " string \<Rightarrow>(string)option " where
+ " s777 s7780 = (
+ (let s7790 = s7780 in
+ if ((string_startswith s7790 (''mulhsu''))) then
+ (case ((string_drop s7790 ((string_length (''mulhsu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7780 :: " string "
+
+
+\<comment> \<open>\<open>val _s773_ : string -> maybe string\<close>\<close>
+
+definition s773 :: " string \<Rightarrow>(string)option " where
+ " s773 s7740 = (
+ (let s7750 = s7740 in
+ if ((string_startswith s7750 (''mulh''))) then
+ (case ((string_drop s7750 ((string_length (''mulh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7740 :: " string "
+
+
+\<comment> \<open>\<open>val _s769_ : string -> maybe string\<close>\<close>
+
+definition s769 :: " string \<Rightarrow>(string)option " where
+ " s769 s7700 = (
+ (let s7710 = s7700 in
+ if ((string_startswith s7710 (''mul''))) then
+ (case ((string_drop s7710 ((string_length (''mul''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7700 :: " string "
+
+
+definition mul_mnemonic_matches_prefix :: " string \<Rightarrow>((bool*bool*bool)*int)option " where
+ " mul_mnemonic_matches_prefix arg1 = (
+ (let s7720 = arg1 in
+ if ((case ((s769 s7720)) of Some (s1) => True | _ => False )) then
+ (case s769 s7720 of
+ (Some (s1)) =>
+ Some ((False, True, True), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s773 s7720)) of Some (s1) => True | _ => False )) then
+ (case s773 s7720 of
+ (Some (s1)) =>
+ Some ((True, True, True), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s777 s7720)) of Some (s1) => True | _ => False )) then
+ (case s777 s7720 of
+ (Some (s1)) =>
+ Some ((True, True, False), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s781 s7720)) of Some (s1) => True | _ => False )) then
+ (case s781 s7720 of
+ (Some (s1)) =>
+ Some ((True, False, False), ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_forwards : bool -> string\<close>\<close>
+
+fun maybe_not_u_forwards :: " bool \<Rightarrow> string " where
+ " maybe_not_u_forwards False = ( (''u''))"
+|" maybe_not_u_forwards True = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_not_u_backwards : string -> M bool\<close>\<close>
+
+definition maybe_not_u_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_not_u_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then return False
+ else if (((p00 = ('''')))) then return True
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_not_u_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_not_u_forwards_matches False = ( True )"
+|" maybe_not_u_forwards_matches True = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_not_u_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_not_u_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_not_u_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s789_ : string -> maybe string\<close>\<close>
+
+definition s789 :: " string \<Rightarrow>(string)option " where
+ " s789 s7900 = (
+ (let s7910 = s7900 in
+ if ((string_startswith s7910 (''''))) then
+ (case ((string_drop s7910 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s7900 :: " string "
+
+
+\<comment> \<open>\<open>val _s785_ : string -> maybe string\<close>\<close>
+
+definition s785 :: " string \<Rightarrow>(string)option " where
+ " s785 s7860 = (
+ (let s7870 = s7860 in
+ if ((string_startswith s7870 (''u''))) then
+ (case ((string_drop s7870 ((string_length (''u''))))) of s1 => Some s1 )
+ else None))"
+ for s7860 :: " string "
+
+
+definition maybe_not_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_not_u_matches_prefix arg1 = (
+ (let s7880 = arg1 in
+ if ((case ((s785 s7880)) of Some (s1) => True | _ => False )) then
+ (case s785 s7880 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s789 s7880)) of Some (s1) => True | _ => False )) then
+ (case s789 s7880 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_csrop_forwards : csrop -> mword ty2\<close>\<close>
+
+fun encdec_csrop_forwards :: " csrop \<Rightarrow>(2)Word.word " where
+ " encdec_csrop_forwards CSRRW = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" encdec_csrop_forwards CSRRS = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" encdec_csrop_forwards CSRRC = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_csrop_backwards : mword ty2 -> M csrop\<close>\<close>
+
+definition encdec_csrop_backwards :: "(2)Word.word \<Rightarrow>((register_value),(csrop),(exception))monad " where
+ " encdec_csrop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return CSRRW
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return CSRRS
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return CSRRC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_csrop_forwards_matches : csrop -> bool\<close>\<close>
+
+fun encdec_csrop_forwards_matches :: " csrop \<Rightarrow> bool " where
+ " encdec_csrop_forwards_matches CSRRW = ( True )"
+|" encdec_csrop_forwards_matches CSRRS = ( True )"
+|" encdec_csrop_forwards_matches CSRRC = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_csrop_backwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition encdec_csrop_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " encdec_csrop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True
+ else False))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val readCSR : mword ty12 -> M (mword ty32)\<close>\<close>
+
+definition readCSR :: "(12)Word.word \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " readCSR csr = (
+ (case (csr, (( 32 :: int)::ii)) of
+ (b__0, g__3) =>
+ if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg mvendorid_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ return ((EXTZ (( 32 :: int)::ii) w__0 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg marchid_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg mimpid_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg mhartid_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ return ((get_Mstatus_bits w__4 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) . return ((get_Misa_bits w__5 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) .
+ return ((get_Medeleg_bits w__6 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__7 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__8 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_mtvec () :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__10 :: Counteren) .
+ return ((EXTZ (( 32 :: int)::ii) ((get_Counteren_bits w__10 :: 32 Word.word)) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mscratch_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target Machine :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) .
+ return ((and_vec w__12 w__13 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg mcause_ref \<bind> (\<lambda> (w__14 :: Mcause) .
+ return ((get_Mcause_bits w__14 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg mtval_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__16 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (pmpReadCfgReg (( 0 :: int)::ii) :: ( 32 Word.word) M)
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))))))
+ then
+ (pmpReadCfgReg (( 1 :: int)::ii) :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (pmpReadCfgReg (( 2 :: int)::ii) :: ( 32 Word.word) M)
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))))))
+ then
+ (pmpReadCfgReg (( 3 :: int)::ii) :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr0_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr1_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr2_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr3_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr4_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr5_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr6_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr7_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr8_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr9_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr10_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr11_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr12_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr13_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr14_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr15_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: 64 Word.word) .
+ return ((subrange_vec_dec w__37 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__38 :: 64 Word.word) .
+ return ((subrange_vec_dec w__38 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)))
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))))))
+ then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__39 :: 64 Word.word) .
+ return ((subrange_vec_dec w__39 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))))))
+ then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__40 :: 64 Word.word) .
+ return ((subrange_vec_dec w__40 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg tselect_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__41 :: 32 Word.word) .
+ return ((not_vec w__41 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__42 :: Mstatus) .
+ return ((get_Sstatus_bits ((lower_mstatus w__42)) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg sedeleg_ref \<bind> (\<lambda> (w__43 :: Sedeleg) .
+ return ((get_Sedeleg_bits w__43 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg sideleg_ref \<bind> (\<lambda> (w__44 :: Sinterrupts) .
+ return ((get_Sinterrupts_bits w__44 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__45 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__46 :: Minterrupts) .
+ return ((get_Sinterrupts_bits ((lower_mie w__45 w__46)) :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_stvec () :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg scounteren_ref \<bind> (\<lambda> (w__48 :: Counteren) .
+ return ((EXTZ (( 32 :: int)::ii) ((get_Counteren_bits w__48 :: 32 Word.word)) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg sscratch_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target Supervisor :: ( 32 Word.word) M) \<bind> (\<lambda> (w__50 :: 32 Word.word) .
+ (pc_alignment_mask () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__51 :: 32 Word.word) .
+ return ((and_vec w__50 w__51 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg scause_ref \<bind> (\<lambda> (w__52 :: Mcause) .
+ return ((get_Mcause_bits w__52 :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg stval_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__54 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__55 :: Minterrupts) .
+ return ((get_Sinterrupts_bits ((lower_mip w__54 w__55)) :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg satp_ref :: ( 32 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__57 :: 64 Word.word) .
+ return ((subrange_vec_dec w__57 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__58 :: 64 Word.word) .
+ return ((subrange_vec_dec w__58 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__59 :: 64 Word.word) .
+ return ((subrange_vec_dec w__59 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)))
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))))))
+ then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 Word.word) .
+ return ((subrange_vec_dec w__60 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))))))
+ then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__61 :: 64 Word.word) .
+ return ((subrange_vec_dec w__61 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))
+ else if ((((((g__3 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))))))
+ then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__62 :: 64 Word.word) .
+ return ((subrange_vec_dec w__62 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))
+ else
+ (ext_read_CSR csr :: ( ( 32 Word.word)option) M) \<bind> (\<lambda> (w__63 :: ( 32 Word.word)option) .
+ return ((case w__63 of
+ Some (res) => res
+ | None =>
+ (let (_ :: unit) = (print_bits0 (''unhandled read to CSR '') csr) in
+ (EXTZ (( 32 :: int)::ii) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 32 Word.word))
+ )))
+ ) \<bind> (\<lambda> (res :: xlenbits) .
+ (let (_ :: unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr)) (((@) ('' -> '') ((string_of_bits res))))))))
+ else () ) in
+ return res)))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val writeCSR : mword ty12 -> mword ty32 -> M unit\<close>\<close>
+
+definition writeCSR :: "(12)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " writeCSR (csr :: csreg) (value1 :: xlenbits) = (
+ (case (csr, (( 32 :: int)::ii)) of
+ (b__0, g__2) =>
+ if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ legalize_mstatus w__0 value1 \<bind> (\<lambda> (w__1 :: Mstatus) .
+ (write_reg mstatus_ref w__1 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__2 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg misa_ref \<bind> (\<lambda> (w__3 :: Misa) .
+ legalize_misa w__3 value1 \<bind> (\<lambda> (w__4 :: Misa) .
+ (write_reg misa_ref w__4 \<then>
+ read_reg misa_ref) \<bind> (\<lambda> (w__5 :: Misa) .
+ return (Some ((get_Misa_bits w__5 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) .
+ (write_reg medeleg_ref ((legalize_medeleg w__6 value1)) \<then>
+ read_reg medeleg_ref) \<bind> (\<lambda> (w__7 :: Medeleg) .
+ return (Some ((get_Medeleg_bits w__7 :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg mideleg_ref \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ (write_reg mideleg_ref ((legalize_mideleg w__8 value1)) \<then>
+ read_reg mideleg_ref) \<bind> (\<lambda> (w__9 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__9 :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__10 :: Minterrupts) .
+ legalize_mie w__10 value1 \<bind> (\<lambda> (w__11 :: Minterrupts) .
+ (write_reg mie_ref w__11 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__12 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__12 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_mtvec value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) . return (Some w__13))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__14 :: Counteren) .
+ (write_reg mcounteren_ref ((legalize_mcounteren w__14 value1)) \<then>
+ read_reg mcounteren_ref) \<bind> (\<lambda> (w__15 :: Counteren) .
+ return (Some ((EXTZ (( 32 :: int)::ii) ((get_Counteren_bits w__15 :: 32 Word.word)) :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg mscratch_ref value1 \<then>
+ (read_reg mscratch_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 Word.word) .
+ return (Some w__16))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target Machine value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 Word.word) .
+ return (Some w__17))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits mcause_ref value1 \<then>
+ read_reg mcause_ref) \<bind> (\<lambda> (w__18 :: Mcause) .
+ return (Some ((get_Mcause_bits w__18 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg mtval_ref value1 \<then>
+ (read_reg mtval_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__19 :: 32 Word.word) . return (Some w__19))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__20 :: Minterrupts) .
+ legalize_mip w__20 value1 \<bind> (\<lambda> (w__21 :: Minterrupts) .
+ (write_reg mip_ref w__21 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__22 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__22 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ pmpWriteCfgReg (( 0 :: int)::ii) value1 \<then> return (Some value1)
+ else if ((((((g__2 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))))))
+ then
+ pmpWriteCfgReg (( 1 :: int)::ii) value1 \<then> return (Some value1)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ pmpWriteCfgReg (( 2 :: int)::ii) value1 \<then> return (Some value1)
+ else if ((((((g__2 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))))))
+ then
+ pmpWriteCfgReg (( 3 :: int)::ii) value1 \<then> return (Some value1)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__23 :: Pmpcfg_ent) .
+ (read_reg pmpaddr0_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 Word.word) .
+ (write_reg pmpaddr0_ref ((pmpWriteAddr w__23 w__24 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr0_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__25 :: 32 Word.word) .
+ return (Some w__25))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__26 :: Pmpcfg_ent) .
+ (read_reg pmpaddr1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__27 :: 32 Word.word) .
+ (write_reg pmpaddr1_ref ((pmpWriteAddr w__26 w__27 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr1_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__28 :: 32 Word.word) .
+ return (Some w__28))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__29 :: Pmpcfg_ent) .
+ (read_reg pmpaddr2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__30 :: 32 Word.word) .
+ (write_reg pmpaddr2_ref ((pmpWriteAddr w__29 w__30 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__31 :: 32 Word.word) .
+ return (Some w__31))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__32 :: Pmpcfg_ent) .
+ (read_reg pmpaddr3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__33 :: 32 Word.word) .
+ (write_reg pmpaddr3_ref ((pmpWriteAddr w__32 w__33 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__34 :: 32 Word.word) .
+ return (Some w__34))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__35 :: Pmpcfg_ent) .
+ (read_reg pmpaddr4_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__36 :: 32 Word.word) .
+ (write_reg pmpaddr4_ref ((pmpWriteAddr w__35 w__36 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr4_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__37 :: 32 Word.word) .
+ return (Some w__37))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__38 :: Pmpcfg_ent) .
+ (read_reg pmpaddr5_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__39 :: 32 Word.word) .
+ (write_reg pmpaddr5_ref ((pmpWriteAddr w__38 w__39 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr5_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__40 :: 32 Word.word) .
+ return (Some w__40))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__41 :: Pmpcfg_ent) .
+ (read_reg pmpaddr6_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__42 :: 32 Word.word) .
+ (write_reg pmpaddr6_ref ((pmpWriteAddr w__41 w__42 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr6_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__43 :: 32 Word.word) .
+ return (Some w__43))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__44 :: Pmpcfg_ent) .
+ (read_reg pmpaddr7_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__45 :: 32 Word.word) .
+ (write_reg pmpaddr7_ref ((pmpWriteAddr w__44 w__45 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr7_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__46 :: 32 Word.word) .
+ return (Some w__46))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__47 :: Pmpcfg_ent) .
+ (read_reg pmpaddr8_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__48 :: 32 Word.word) .
+ (write_reg pmpaddr8_ref ((pmpWriteAddr w__47 w__48 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr8_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__49 :: 32 Word.word) .
+ return (Some w__49))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__50 :: Pmpcfg_ent) .
+ (read_reg pmpaddr9_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__51 :: 32 Word.word) .
+ (write_reg pmpaddr9_ref ((pmpWriteAddr w__50 w__51 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr9_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__52 :: 32 Word.word) .
+ return (Some w__52))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__53 :: Pmpcfg_ent) .
+ (read_reg pmpaddr10_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__54 :: 32 Word.word) .
+ (write_reg pmpaddr10_ref ((pmpWriteAddr w__53 w__54 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr10_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__55 :: 32 Word.word) .
+ return (Some w__55))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__56 :: Pmpcfg_ent) .
+ (read_reg pmpaddr11_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__57 :: 32 Word.word) .
+ (write_reg pmpaddr11_ref ((pmpWriteAddr w__56 w__57 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr11_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__58 :: 32 Word.word) .
+ return (Some w__58))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__59 :: Pmpcfg_ent) .
+ (read_reg pmpaddr12_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__60 :: 32 Word.word) .
+ (write_reg pmpaddr12_ref ((pmpWriteAddr w__59 w__60 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr12_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__61 :: 32 Word.word) .
+ return (Some w__61))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__62 :: Pmpcfg_ent) .
+ (read_reg pmpaddr13_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__63 :: 32 Word.word) .
+ (write_reg pmpaddr13_ref ((pmpWriteAddr w__62 w__63 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr13_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__64 :: 32 Word.word) .
+ return (Some w__64))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__65 :: Pmpcfg_ent) .
+ (read_reg pmpaddr14_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__66 :: 32 Word.word) .
+ (write_reg pmpaddr14_ref ((pmpWriteAddr w__65 w__66 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr14_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__67 :: 32 Word.word) .
+ return (Some w__67))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__68 :: Pmpcfg_ent) .
+ (read_reg pmpaddr15_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__69 :: 32 Word.word) .
+ (write_reg pmpaddr15_ref ((pmpWriteAddr w__68 w__69 value1 :: 32 Word.word)) \<then>
+ (read_reg pmpaddr15_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__70 :: 32 Word.word) .
+ return (Some w__70))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__71 :: 64 Word.word) .
+ write_reg
+ mcycle_ref
+ ((update_subrange_vec_dec w__71 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ return (Some value1))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__72 :: 64 Word.word) .
+ (write_reg
+ minstret_ref
+ ((update_subrange_vec_dec w__72 (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ write_reg minstret_written_ref True) \<then> return (Some value1))
+ else if ((((((g__2 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))))))
+ then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__73 :: 64 Word.word) .
+ write_reg mcycle_ref ((update_subrange_vec_dec w__73 (( 63 :: int)::ii) (( 32 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ return (Some value1))
+ else if ((((((g__2 = (( 32 :: int)::ii)))) \<and> (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))))))
+ then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__74 :: 64 Word.word) .
+ (write_reg minstret_ref ((update_subrange_vec_dec w__74 (( 63 :: int)::ii) (( 32 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ write_reg minstret_written_ref True) \<then> return (Some value1))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg tselect_ref value1 \<then>
+ (read_reg tselect_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__75 :: 32 Word.word) . return (Some w__75))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__76 :: Mstatus) .
+ legalize_sstatus w__76 value1 \<bind> (\<lambda> (w__77 :: Mstatus) .
+ (write_reg mstatus_ref w__77 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__78 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__78 :: 32 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg sedeleg_ref \<bind> (\<lambda> (w__79 :: Sedeleg) .
+ (write_reg sedeleg_ref ((legalize_sedeleg w__79 value1)) \<then>
+ read_reg sedeleg_ref) \<bind> (\<lambda> (w__80 :: Sedeleg) .
+ return (Some ((get_Sedeleg_bits w__80 :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (set_Sinterrupts_bits sideleg_ref value1 \<then>
+ read_reg sideleg_ref) \<bind> (\<lambda> (w__81 :: Sinterrupts) .
+ return (Some ((get_Sinterrupts_bits w__81 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__82 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__83 :: Minterrupts) .
+ legalize_sie w__82 w__83 value1 \<bind> (\<lambda> (w__84 :: Minterrupts) .
+ (write_reg mie_ref w__84 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__85 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__85 :: 32 Word.word)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_stvec value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__86 :: 32 Word.word) . return (Some w__86))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg scounteren_ref \<bind> (\<lambda> (w__87 :: Counteren) .
+ (write_reg scounteren_ref ((legalize_scounteren w__87 value1)) \<then>
+ read_reg scounteren_ref) \<bind> (\<lambda> (w__88 :: Counteren) .
+ return (Some ((EXTZ (( 32 :: int)::ii) ((get_Counteren_bits w__88 :: 32 Word.word)) :: 32 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg sscratch_ref value1 \<then>
+ (read_reg sscratch_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__89 :: 32 Word.word) .
+ return (Some w__89))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target Supervisor value1 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__90 :: 32 Word.word) .
+ return (Some w__90))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits scause_ref value1 \<then>
+ read_reg scause_ref) \<bind> (\<lambda> (w__91 :: Mcause) .
+ return (Some ((get_Mcause_bits w__91 :: 32 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg stval_ref value1 \<then>
+ (read_reg stval_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__92 :: 32 Word.word) . return (Some w__92))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__93 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__94 :: Minterrupts) .
+ legalize_sip w__93 w__94 value1 \<bind> (\<lambda> (w__95 :: Minterrupts) .
+ (write_reg mip_ref w__95 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__96 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__96 :: 32 Word.word)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ cur_Architecture () \<bind> (\<lambda> (w__97 :: Architecture) .
+ (read_reg satp_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__98 :: 32 Word.word) .
+ (write_reg satp_ref ((legalize_satp w__97 w__98 value1 :: 32 Word.word)) \<then>
+ (read_reg satp_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__99 :: 32 Word.word) . return (Some w__99))))
+ else return None
+ ) \<bind> (\<lambda> (res :: xlenbits option) .
+ (case res of
+ Some (v) =>
+ return (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr))
+ (((@) ('' <- '')
+ (((@) ((string_of_bits v))
+ (((@) ('' (input: '')
+ (((@) ((string_of_bits value1)) ('')'')))))))))))))
+ else () )
+ | None =>
+ ext_write_CSR csr value1 \<bind> (\<lambda> (w__149 :: bool) .
+ return (if w__149 then ()
+ else print_bits0 (''unhandled write to CSR '') csr))
+ )))"
+ for csr :: "(12)Word.word "
+ and value1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val maybe_i_forwards : bool -> string\<close>\<close>
+
+fun maybe_i_forwards :: " bool \<Rightarrow> string " where
+ " maybe_i_forwards True = ( (''i''))"
+|" maybe_i_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_i_backwards : string -> M bool\<close>\<close>
+
+definition maybe_i_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_i_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_i_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_i_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_i_forwards_matches True = ( True )"
+|" maybe_i_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_i_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_i_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_i_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_i_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s797_ : string -> maybe string\<close>\<close>
+
+definition s797 :: " string \<Rightarrow>(string)option " where
+ " s797 s7980 = (
+ (let s7990 = s7980 in
+ if ((string_startswith s7990 (''''))) then
+ (case ((string_drop s7990 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s7980 :: " string "
+
+
+\<comment> \<open>\<open>val _s793_ : string -> maybe string\<close>\<close>
+
+definition s793 :: " string \<Rightarrow>(string)option " where
+ " s793 s7940 = (
+ (let s7950 = s7940 in
+ if ((string_startswith s7950 (''i''))) then
+ (case ((string_drop s7950 ((string_length (''i''))))) of s1 => Some s1 )
+ else None))"
+ for s7940 :: " string "
+
+
+definition maybe_i_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_i_matches_prefix arg1 = (
+ (let s7960 = arg1 in
+ if ((case ((s793 s7960)) of Some (s1) => True | _ => False )) then
+ (case s793 s7960 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s797 s7960)) of Some (s1) => True | _ => False )) then
+ (case s797 s7960 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_forwards : csrop -> string\<close>\<close>
+
+fun csr_mnemonic_forwards :: " csrop \<Rightarrow> string " where
+ " csr_mnemonic_forwards CSRRW = ( (''csrrw''))"
+|" csr_mnemonic_forwards CSRRS = ( (''csrrs''))"
+|" csr_mnemonic_forwards CSRRC = ( (''csrrc''))"
+
+
+\<comment> \<open>\<open>val csr_mnemonic_backwards : string -> M csrop\<close>\<close>
+
+definition csr_mnemonic_backwards :: " string \<Rightarrow>((register_value),(csrop),(exception))monad " where
+ " csr_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''csrrw'')))) then return CSRRW
+ else if (((p00 = (''csrrs'')))) then return CSRRS
+ else if (((p00 = (''csrrc'')))) then return CSRRC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_forwards_matches : csrop -> bool\<close>\<close>
+
+fun csr_mnemonic_forwards_matches :: " csrop \<Rightarrow> bool " where
+ " csr_mnemonic_forwards_matches CSRRW = ( True )"
+|" csr_mnemonic_forwards_matches CSRRS = ( True )"
+|" csr_mnemonic_forwards_matches CSRRC = ( True )"
+
+
+\<comment> \<open>\<open>val csr_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition csr_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " csr_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''csrrw'')))) then True
+ else if (((p00 = (''csrrs'')))) then True
+ else if (((p00 = (''csrrc'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s809_ : string -> maybe string\<close>\<close>
+
+definition s809 :: " string \<Rightarrow>(string)option " where
+ " s809 s8100 = (
+ (let s8110 = s8100 in
+ if ((string_startswith s8110 (''csrrc''))) then
+ (case ((string_drop s8110 ((string_length (''csrrc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8100 :: " string "
+
+
+\<comment> \<open>\<open>val _s805_ : string -> maybe string\<close>\<close>
+
+definition s805 :: " string \<Rightarrow>(string)option " where
+ " s805 s8060 = (
+ (let s8070 = s8060 in
+ if ((string_startswith s8070 (''csrrs''))) then
+ (case ((string_drop s8070 ((string_length (''csrrs''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8060 :: " string "
+
+
+\<comment> \<open>\<open>val _s801_ : string -> maybe string\<close>\<close>
+
+definition s801 :: " string \<Rightarrow>(string)option " where
+ " s801 s8020 = (
+ (let s8030 = s8020 in
+ if ((string_startswith s8030 (''csrrw''))) then
+ (case ((string_drop s8030 ((string_length (''csrrw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8020 :: " string "
+
+
+definition csr_mnemonic_matches_prefix :: " string \<Rightarrow>(csrop*int)option " where
+ " csr_mnemonic_matches_prefix arg1 = (
+ (let s8040 = arg1 in
+ if ((case ((s801 s8040)) of Some (s1) => True | _ => False )) then
+ (case s801 s8040 of
+ (Some (s1)) =>
+ Some (CSRRW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s805 s8040)) of Some (s1) => True | _ => False )) then
+ (case s805 s8040 of
+ (Some (s1)) =>
+ Some (CSRRS, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s809 s8040)) of Some (s1) => True | _ => False )) then
+ (case s809 s8040 of
+ (Some (s1)) =>
+ Some (CSRRC, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_forwards : ast -> M (mword ty32)\<close>\<close>
+
+fun encdec_forwards :: " ast \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " encdec_forwards (UTYPE ((imm, rd, op1))) = (
+ return ((concat_vec imm
+ ((concat_vec rd ((encdec_uop_forwards op1 :: 7 Word.word)) :: 12 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RISCV_JAL ((v__2, rd))) = (
+ if (((((subrange_vec_dec v__2 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__2 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__2 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__2 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in
+ (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in
+ return ((concat_vec imm_19
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9
+ ((concat_vec imm_8
+ ((concat_vec imm_7_0
+ ((concat_vec rd (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 20 Word.word))
+ :: 21 Word.word))
+ :: 25 Word.word))
+ :: 31 Word.word))
+ :: 32 Word.word))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__2 :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RISCV_JALR ((imm, rs1, rd))) = (
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (BTYPE ((v__4, rs2, rs1, op1))) = (
+ if (((((subrange_vec_dec v__4 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__4 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__4 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__4 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in
+ (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__4 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in
+ (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__4 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec imm7_6
+ ((concat_vec imm7_5_0
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec ((encdec_bop_forwards op1 :: 3 Word.word))
+ ((concat_vec imm5_4_1
+ ((concat_vec imm5_0
+ (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 8 Word.word))
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 31 Word.word))
+ :: 32 Word.word)))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and v__4 :: "(13)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (ITYPE ((imm, rs1, rd, op1))) = (
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((encdec_iop_forwards op1 :: 3 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_ADD))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLT))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLTU))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_AND))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_OR))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_XOR))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLL))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SRL))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SUB))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SRA))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (LOAD ((imm, rs1, rd, is_unsigned, size1, False, False))) = (
+ if (((((((word_width_bytes size1)) < (( 4 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))))))) then
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_unsigned :: 1 Word.word))
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+|" encdec_forwards (STORE ((v__6, rs2, rs1, size1, False, False))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__6 (( 11 :: int)::ii) (( 5 :: int)::ii) :: 7 Word.word)) in
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__6 (( 11 :: int)::ii) (( 5 :: int)::ii) :: 7 Word.word)) in
+ (let (imm5 :: 5 bits) = ((subrange_vec_dec v__6 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec imm7
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec imm5
+ (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and v__6 :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (ADDIW ((imm, rs1, rd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SLLI))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SRLI))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SRAI))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_ADDW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SUBW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SLLW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SRLW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SRAW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (FENCE ((pred, succ))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 24 Word.word))
+ :: 28 Word.word))
+ :: 32 Word.word)))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards (FENCE_TSO ((pred, succ))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 24 Word.word))
+ :: 28 Word.word))
+ :: 32 Word.word)))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards (FENCEI (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (ECALL (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (MRET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (SRET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (EBREAK (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (WFI (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (SFENCE_VMA ((rs1, rs2))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (AMO ((op1, aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then
+ return ((concat_vec ((encdec_amoop_forwards op1 :: 5 Word.word))
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (MUL ((rs2, rs1, rd, high, signed1, signed2))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec
+ ((encdec_mul_op_forwards (high, signed1, signed2) :: 3 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (DIV ((rs2, rs1, rd, s))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (REM ((rs2, rs1, rd, s))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (MULW ((rs2, rs1, rd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (DIVW ((rs2, rs1, rd, s))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (REMW ((rs2, rs1, rd, s))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (CSR ((csr, rs1, rd, is_imm, op1))) = (
+ return ((concat_vec csr
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_imm :: 1 Word.word))
+ ((concat_vec ((encdec_csrop_forwards op1 :: 2 Word.word))
+ ((concat_vec rd (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" encdec_forwards (URET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (ILLEGAL (s)) = ( return s )"
+ for s :: "(32)Word.word "
+|" encdec_forwards _ = ( assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+
+
+\<comment> \<open>\<open>val encdec_backwards : mword ty32 -> M ast\<close>\<close>
+
+definition encdec_backwards :: "(32)Word.word \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " encdec_backwards arg1 = (
+ (let v__7 = arg1 in
+ (let (mappingpatterns_230 :: 7 Word.word) = ((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ and_boolM (return ((encdec_uop_backwards_matches mappingpatterns_230)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_230)) then
+ encdec_uop_backwards mappingpatterns_230 \<bind> (\<lambda> op1 . return True)
+ else return False) \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ (let (imm :: 20 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 20 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in
+ (let (mappingpatterns_230 :: 7 Word.word) = ((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ encdec_uop_backwards mappingpatterns_230 \<bind> (\<lambda> op1 . return (UTYPE (imm, rd, op1)))))))
+ else if (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__7 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__7 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in
+ (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 21 :: int)::ii) :: 4 Word.word)) in
+ return (RISCV_JAL ((concat_vec imm_19
+ ((concat_vec imm_7_0
+ ((concat_vec imm_8
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9 (vec_of_bits [B0] :: 1 Word.word)
+ :: 5 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 20 Word.word))
+ :: 21 Word.word),
+ rd)))))))))
+ else if ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ return (RISCV_JALR (imm, rs1, rd))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_240 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_bop_backwards_matches mappingpatterns_240)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_240)) then
+ encdec_bop_backwards mappingpatterns_240 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__7 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in
+ (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in
+ (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__7 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_240 :: 3 Word.word) = ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_bop_backwards mappingpatterns_240 \<bind> (\<lambda> op1 .
+ return (BTYPE ((concat_vec imm7_6
+ ((concat_vec imm5_0
+ ((concat_vec imm7_5_0
+ ((concat_vec imm5_4_1 (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word),
+ rs2,
+ rs1,
+ op1)))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_250 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_iop_backwards_matches mappingpatterns_250)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_250)) then
+ encdec_iop_backwards mappingpatterns_250 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__7 :: bool) .
+ if w__7 then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_250 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_iop_backwards mappingpatterns_250 \<bind> (\<lambda> op1 . return (ITYPE (imm, rs1, rd, op1))))))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SLLI)))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SRLI)))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SRAI)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_ADD)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLT)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLTU)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_AND)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_OR)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_XOR)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLL)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SRL)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SUB)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SRA)))))
+ else
+ and_boolM
+ ((let (mappingpatterns_270 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_260 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_270)))
+ (if ((size_bits_backwards_matches mappingpatterns_270)) then
+ size_bits_backwards mappingpatterns_270 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_260)))
+ (if ((bool_bits_backwards_matches mappingpatterns_260)) then
+ bool_bits_backwards mappingpatterns_260 \<bind> (\<lambda> is_unsigned .
+ return (((((((word_width_bytes size1)) < (( 4 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))))))))
+ else return False) \<bind> (\<lambda> (w__9 :: bool) .
+ return w__9))
+ else return False))))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__12 :: bool) .
+ if w__12 then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_270 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_260 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_270 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_260 \<bind> (\<lambda> is_unsigned .
+ return (LOAD (imm, rs1, rd, is_unsigned, size1, False, False))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_280 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_280)))
+ (if ((size_bits_backwards_matches mappingpatterns_280)) then
+ size_bits_backwards mappingpatterns_280 \<bind> (\<lambda> size1 .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__15 ::
+ bool) .
+ if w__15 then
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in
+ (let (imm5 :: 5 bits) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_280 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ size_bits_backwards mappingpatterns_280 \<bind> (\<lambda> size1 .
+ return (STORE ((concat_vec imm7 imm5 :: 12 Word.word), rs2, rs1, size1, False, False)))))))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ return (ADDIW (imm, rs1, rd))))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SLLI)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SRLI)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SRAI)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_ADDW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SUBW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SLLW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SRLW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SRAW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SLLIW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SRLIW)))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SRAIW)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ (let (succ :: 4 Word.word) = ((subrange_vec_dec v__7 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in
+ (let (pred :: 4 Word.word) = ((subrange_vec_dec v__7 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in
+ return (FENCE (pred, succ))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ (let (succ :: 4 Word.word) = ((subrange_vec_dec v__7 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in
+ (let (pred :: 4 Word.word) = ((subrange_vec_dec v__7 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in
+ return (FENCE_TSO (pred, succ))))
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,
+ B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 32 Word.word)))) then
+ return (FENCEI () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (ECALL () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (MRET () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (SRET () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (EBREAK () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (WFI () )
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word)))))))
+ then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ return (SFENCE_VMA (rs1, rs2))))
+ else
+ and_boolM
+ ((let (mappingpatterns_310 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_300 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_290 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_310)))
+ (if ((size_bits_backwards_matches mappingpatterns_310)) then
+ size_bits_backwards mappingpatterns_310 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_300)))
+ (if ((bool_bits_backwards_matches mappingpatterns_300)) then
+ bool_bits_backwards mappingpatterns_300 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_290)))
+ (if ((bool_bits_backwards_matches mappingpatterns_290)) then
+ bool_bits_backwards mappingpatterns_290 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__17 :: bool) .
+ return w__17))
+ else return False) \<bind> (\<lambda> (w__19 :: bool) .
+ return w__19))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))))))) \<bind> (\<lambda> (w__22 ::
+ bool) .
+ if w__22 then
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_310 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_300 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_290 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_310 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_300 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_290 \<bind> (\<lambda> aq .
+ return (LOADRES (aq, rl, rs1, size1, rd))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_340 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_330 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_320 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_340)))
+ (if ((size_bits_backwards_matches mappingpatterns_340)) then
+ size_bits_backwards mappingpatterns_340 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_330)))
+ (if ((bool_bits_backwards_matches mappingpatterns_330)) then
+ bool_bits_backwards mappingpatterns_330 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_320)))
+ (if ((bool_bits_backwards_matches mappingpatterns_320)) then
+ bool_bits_backwards mappingpatterns_320 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__24 :: bool) .
+ return w__24))
+ else return False) \<bind> (\<lambda> (w__26 :: bool) .
+ return w__26))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__29 ::
+ bool) .
+ if w__29 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_340 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_330 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_320 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_340 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_330 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_320 \<bind> (\<lambda> aq .
+ return (STORECON (aq, rl, rs2, rs1, size1, rd)))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_380 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_370 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_360 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_380)))
+ (if ((size_bits_backwards_matches mappingpatterns_380)) then
+ size_bits_backwards mappingpatterns_380 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_370)))
+ (if ((bool_bits_backwards_matches mappingpatterns_370)) then
+ bool_bits_backwards mappingpatterns_370 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_360)))
+ (if ((bool_bits_backwards_matches mappingpatterns_360)) then
+ bool_bits_backwards mappingpatterns_360 \<bind> (\<lambda> aq .
+ and_boolM
+ (return ((encdec_amoop_backwards_matches mappingpatterns_350)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_350)) then
+ encdec_amoop_backwards mappingpatterns_350 \<bind> (\<lambda> op1 .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__31 :: bool) .
+ return w__31))
+ else return False) \<bind> (\<lambda> (w__33 :: bool) .
+ return w__33))
+ else return False) \<bind> (\<lambda> (w__35 :: bool) .
+ return w__35))
+ else return False)))))))
+ (return ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__38 ::
+ bool) .
+ if w__38 then
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_380 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_370 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_360 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ size_bits_backwards mappingpatterns_380 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_370 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_360 \<bind> (\<lambda> aq .
+ encdec_amoop_backwards mappingpatterns_350 \<bind> (\<lambda> op1 .
+ return (AMO (op1, aq, rl, rs2, rs1, size1, rd))))))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_390 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_mul_op_backwards_matches mappingpatterns_390)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_390)) then
+ encdec_mul_op_backwards mappingpatterns_390 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__41 ::
+ bool) .
+ if w__41 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_390 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_mul_op_backwards mappingpatterns_390 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return (MUL (rs2, rs1, rd, high, signed1, signed2))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_400 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_400)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_400)) then
+ bool_not_bits_backwards mappingpatterns_400 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__44 ::
+ bool) .
+ if w__44 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_400 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_400 \<bind> (\<lambda> s .
+ return (DIV (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_410 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_410)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_410)) then
+ bool_not_bits_backwards mappingpatterns_410 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__47 ::
+ bool) .
+ if w__47 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_410 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_410 \<bind> (\<lambda> s .
+ return (REM (rs2, rs1, rd, s)))))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))))))
+ then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (MULW (rs2, rs1, rd)))))
+ else
+ and_boolM
+ ((let (mappingpatterns_420 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_420)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_420)) then
+ bool_not_bits_backwards mappingpatterns_420 \<bind> (\<lambda> s .
+ return ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__50 ::
+ bool) .
+ if w__50 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_420 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_420 \<bind> (\<lambda> s .
+ return (DIVW (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_430 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_430)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_430)) then
+ bool_not_bits_backwards mappingpatterns_430 \<bind> (\<lambda> s .
+ return ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__53 ::
+ bool) .
+ if w__53 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_430 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_430 \<bind> (\<lambda> s .
+ return (REMW (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_450 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_440 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((encdec_csrop_backwards_matches mappingpatterns_450)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_450)) then
+ encdec_csrop_backwards mappingpatterns_450 \<bind> (\<lambda> op1 .
+ and_boolM
+ (return ((bool_bits_backwards_matches mappingpatterns_440)))
+ (if ((bool_bits_backwards_matches mappingpatterns_440)) then
+ bool_bits_backwards mappingpatterns_440 \<bind> (\<lambda> is_imm .
+ return True)
+ else return False) \<bind> (\<lambda> (w__55 :: bool) .
+ return w__55))
+ else return False))))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__58 ::
+ bool) .
+ if w__58 then
+ (let (csr :: 12 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (csr :: 12 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_450 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_440 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ encdec_csrop_backwards mappingpatterns_450 \<bind> (\<lambda> op1 .
+ bool_bits_backwards mappingpatterns_440 \<bind> (\<lambda> is_imm .
+ return (CSR (csr, rs1, rd, is_imm, op1))))))))))
+ else
+ return (if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,
+ B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+ B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ URET ()
+ else ILLEGAL v__7))))))))))))))))))"
+ for arg1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_forwards_matches : ast -> bool\<close>\<close>
+
+fun encdec_forwards_matches :: " ast \<Rightarrow> bool " where
+ " encdec_forwards_matches (UTYPE ((imm, rd, op1))) = ( True )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RISCV_JAL ((v__220, rd))) = (
+ if (((((subrange_vec_dec v__220 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ True
+ else False )"
+ for v__220 :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RISCV_JALR ((imm, rs1, rd))) = ( True )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (BTYPE ((v__222, rs2, rs1, op1))) = (
+ if (((((subrange_vec_dec v__222 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ True
+ else False )"
+ for op1 :: " bop "
+ and v__222 :: "(13)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (ITYPE ((imm, rs1, rd, op1))) = ( True )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_ADD))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLT))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLTU))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_AND))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_OR))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_XOR))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLL))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SRL))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SUB))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SRA))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (LOAD ((imm, rs1, rd, is_unsigned, size1, False, False))) = (
+ if (((((((word_width_bytes size1)) < (( 4 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))))))) then
+ True
+ else False )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+|" encdec_forwards_matches (STORE ((v__224, rs2, rs1, size1, False, False))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and v__224 :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (ADDIW ((imm, rs1, rd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SLLI))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SRLI))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SRAI))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_ADDW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SUBW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SLLW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SRLW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SRAW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (FENCE ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards_matches (FENCE_TSO ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards_matches (FENCEI (_)) = ( True )"
+|" encdec_forwards_matches (ECALL (_)) = ( True )"
+|" encdec_forwards_matches (MRET (_)) = ( True )"
+|" encdec_forwards_matches (SRET (_)) = ( True )"
+|" encdec_forwards_matches (EBREAK (_)) = ( True )"
+|" encdec_forwards_matches (WFI (_)) = ( True )"
+|" encdec_forwards_matches (SFENCE_VMA ((rs1, rs2))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (AMO ((op1, aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( True )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (DIV ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (REM ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (MULW ((rs2, rs1, rd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (DIVW ((rs2, rs1, rd, s))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (REMW ((rs2, rs1, rd, s))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (CSR ((csr, rs1, rd, is_imm, op1))) = ( True )"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" encdec_forwards_matches (URET (_)) = ( True )"
+|" encdec_forwards_matches (ILLEGAL (s)) = ( True )"
+ for s :: "(32)Word.word "
+|" encdec_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_backwards_matches : mword ty32 -> M bool\<close>\<close>
+
+definition encdec_backwards_matches :: "(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " encdec_backwards_matches arg1 = (
+ (let v__225 = arg1 in
+ (let (mappingpatterns_00 :: 7 Word.word) = ((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ and_boolM (return ((encdec_uop_backwards_matches mappingpatterns_00)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_00)) then
+ encdec_uop_backwards mappingpatterns_00 \<bind> (\<lambda> op1 . return True)
+ else return False) \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ (let (mappingpatterns_00 :: 7 Word.word) = ((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ encdec_uop_backwards mappingpatterns_00 \<bind> (\<lambda> op1 . return True))
+ else if (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_10 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_bop_backwards_matches mappingpatterns_10)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_10)) then
+ encdec_bop_backwards mappingpatterns_10 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (let (mappingpatterns_10 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_bop_backwards mappingpatterns_10 \<bind> (\<lambda> op1 . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_20 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_iop_backwards_matches mappingpatterns_20)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_20)) then
+ encdec_iop_backwards mappingpatterns_20 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__7 :: bool) .
+ if w__7 then
+ (let (mappingpatterns_20 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_iop_backwards mappingpatterns_20 \<bind> (\<lambda> op1 . return True))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_40 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_30 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_40)))
+ (if ((size_bits_backwards_matches mappingpatterns_40)) then
+ size_bits_backwards mappingpatterns_40 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_30)))
+ (if ((bool_bits_backwards_matches mappingpatterns_30)) then
+ bool_bits_backwards mappingpatterns_30 \<bind> (\<lambda> is_unsigned .
+ return (((((((word_width_bytes size1)) < (( 4 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))))))))
+ else return False) \<bind> (\<lambda> (w__9 :: bool) .
+ return w__9))
+ else return False))))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__12 :: bool) .
+ if w__12 then
+ (let (mappingpatterns_40 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_30 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_40 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_30 \<bind> (\<lambda> is_unsigned . return True))))
+ else
+ and_boolM
+ ((let (mappingpatterns_50 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_50)))
+ (if ((size_bits_backwards_matches mappingpatterns_50)) then
+ size_bits_backwards mappingpatterns_50 \<bind> (\<lambda> size1 .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__15 ::
+ bool) .
+ if w__15 then
+ (let (mappingpatterns_50 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ size_bits_backwards mappingpatterns_50 \<bind> (\<lambda> size1 . return True))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,
+ B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word)))))))
+ then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_80 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_70 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_60 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_80)))
+ (if ((size_bits_backwards_matches mappingpatterns_80)) then
+ size_bits_backwards mappingpatterns_80 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_70)))
+ (if ((bool_bits_backwards_matches mappingpatterns_70)) then
+ bool_bits_backwards mappingpatterns_70 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_60)))
+ (if ((bool_bits_backwards_matches mappingpatterns_60)) then
+ bool_bits_backwards mappingpatterns_60 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__17 :: bool) .
+ return w__17))
+ else return False) \<bind> (\<lambda> (w__19 :: bool) .
+ return w__19))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))))))) \<bind> (\<lambda> (w__22 ::
+ bool) .
+ if w__22 then
+ (let (mappingpatterns_80 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_70 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_60 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_80 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_70 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_60 \<bind> (\<lambda> aq . return True))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_90 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_110 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_100 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_110)))
+ (if ((size_bits_backwards_matches mappingpatterns_110)) then
+ size_bits_backwards mappingpatterns_110 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_100)))
+ (if ((bool_bits_backwards_matches mappingpatterns_100)) then
+ bool_bits_backwards mappingpatterns_100 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_90)))
+ (if ((bool_bits_backwards_matches mappingpatterns_90)) then
+ bool_bits_backwards mappingpatterns_90 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__24 :: bool) .
+ return w__24))
+ else return False) \<bind> (\<lambda> (w__26 :: bool) .
+ return w__26))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__29 ::
+ bool) .
+ if w__29 then
+ (let (mappingpatterns_90 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_110 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_100 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_110 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_100 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_90 \<bind> (\<lambda> aq . return True))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_150 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_140 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_130 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_150)))
+ (if ((size_bits_backwards_matches mappingpatterns_150)) then
+ size_bits_backwards mappingpatterns_150 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_140)))
+ (if ((bool_bits_backwards_matches mappingpatterns_140)) then
+ bool_bits_backwards mappingpatterns_140 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_130)))
+ (if ((bool_bits_backwards_matches mappingpatterns_130)) then
+ bool_bits_backwards mappingpatterns_130 \<bind> (\<lambda> aq .
+ and_boolM
+ (return ((encdec_amoop_backwards_matches mappingpatterns_120)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_120)) then
+ encdec_amoop_backwards mappingpatterns_120 \<bind> (\<lambda> op1 .
+ return ((((word_width_bytes size1)) \<le> (( 4 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__31 :: bool) .
+ return w__31))
+ else return False) \<bind> (\<lambda> (w__33 :: bool) .
+ return w__33))
+ else return False) \<bind> (\<lambda> (w__35 :: bool) .
+ return w__35))
+ else return False)))))))
+ (return ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__38 ::
+ bool) .
+ if w__38 then
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_150 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_140 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_130 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ size_bits_backwards mappingpatterns_150 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_140 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_130 \<bind> (\<lambda> aq .
+ encdec_amoop_backwards mappingpatterns_120 \<bind> (\<lambda> op1 . return True)))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_160 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_mul_op_backwards_matches mappingpatterns_160)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_160)) then
+ encdec_mul_op_backwards mappingpatterns_160 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__41 ::
+ bool) .
+ if w__41 then
+ (let (mappingpatterns_160 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_mul_op_backwards mappingpatterns_160 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True)))
+ else
+ and_boolM
+ ((let (mappingpatterns_170 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_170)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_170)) then
+ bool_not_bits_backwards mappingpatterns_170 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__44 ::
+ bool) .
+ if w__44 then
+ (let (mappingpatterns_170 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_170 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_180 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_180)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_180)) then
+ bool_not_bits_backwards mappingpatterns_180 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__47 ::
+ bool) .
+ if w__47 then
+ (let (mappingpatterns_180 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_180 \<bind> (\<lambda> s . return True))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii)
+ :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))))))
+ then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_190 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_190)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_190)) then
+ bool_not_bits_backwards mappingpatterns_190 \<bind> (\<lambda> s .
+ return ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__50 ::
+ bool) .
+ if w__50 then
+ (let (mappingpatterns_190 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_190 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_200 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_200)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_200)) then
+ bool_not_bits_backwards mappingpatterns_200 \<bind> (\<lambda> s .
+ return ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii)
+ :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__53 ::
+ bool) .
+ if w__53 then
+ (let (mappingpatterns_200 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_200 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_220 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_210 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((encdec_csrop_backwards_matches mappingpatterns_220)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_220)) then
+ encdec_csrop_backwards mappingpatterns_220 \<bind> (\<lambda> op1 .
+ and_boolM
+ (return ((bool_bits_backwards_matches mappingpatterns_210)))
+ (if ((bool_bits_backwards_matches mappingpatterns_210)) then
+ bool_bits_backwards mappingpatterns_210 \<bind> (\<lambda> is_imm .
+ return True)
+ else return False) \<bind> (\<lambda> (w__55 :: bool) .
+ return w__55))
+ else return False))))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__58 ::
+ bool) .
+ if w__58 then
+ (let (mappingpatterns_220 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_210 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ encdec_csrop_backwards mappingpatterns_220 \<bind> (\<lambda> op1 .
+ bool_bits_backwards mappingpatterns_210 \<bind> (\<lambda> is_imm .
+ return True))))
+ else
+ return (if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,
+ B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+ B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ True
+ else True))))))))))))))))))"
+ for arg1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_compressed_forwards : ast -> M (mword ty16)\<close>\<close>
+
+fun encdec_compressed_forwards :: " ast \<Rightarrow>((register_value),((16)Word.word),(exception))monad " where
+ " encdec_compressed_forwards (C_NOP (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+|" encdec_compressed_forwards (C_ADDI4SPN ((rd, v__438))) = (
+ if ((let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__438 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__438 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__438 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))))))) then
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__438 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__438 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__438 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nz54
+ ((concat_vec nz96
+ ((concat_vec nz2
+ ((concat_vec nz3
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 11 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__438 :: "(8)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_LW ((v__439, rs1, rd))) = (
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__439 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__439 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__439 (( 3 :: int)::ii) (( 1 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__439 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))"
+ for v__439 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_LD ((v__440, rs1, rd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__440 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__440 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__440 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__440 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SW ((v__441, rs1, rs2))) = (
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__441 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__441 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__441 (( 3 :: int)::ii) (( 1 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__441 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rs2 (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))"
+ for v__441 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SD ((v__442, rs1, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__442 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__442 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__442 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__442 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ADDI ((v__443, rsd))) = (
+ if ((let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__443 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) then
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__443 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nzi5
+ ((concat_vec rsd
+ ((concat_vec nzi40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and v__443 :: "(6)Word.word "
+|" encdec_compressed_forwards (C_JAL (v__444)) = (
+ if ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) then
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__444 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__444 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__444 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__444 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__444 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__444 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__444 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__444 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__444 (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word))
+ :: 9 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__444 :: "(11)Word.word "
+|" encdec_compressed_forwards (C_ADDIW ((v__445, rsd))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__445 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__445 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__445 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec imm5
+ ((concat_vec rsd
+ ((concat_vec imm40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__445 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LI ((v__446, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__446 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__446 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__446 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec imm5
+ ((concat_vec rd
+ ((concat_vec imm40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__446 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_ADDI16SP (v__447)) = (
+ if ((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__447 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__447 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__447 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__447 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__447 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__447 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__447 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__447 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec nzi9
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec nzi4
+ ((concat_vec nzi6
+ ((concat_vec nzi87
+ ((concat_vec nzi5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__447 :: "(6)Word.word "
+|" encdec_compressed_forwards (C_LUI ((v__448, rd))) = (
+ if ((let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__448 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) then
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__448 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec imm17
+ ((concat_vec rd
+ ((concat_vec imm1612 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__448 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SRLI ((v__449, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__449 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__449 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__449 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SRAI ((v__450, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__450 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__450 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__450 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ANDI ((v__451, rsd))) = (
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__451 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__451 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i40 :: 5 bits) = ((subrange_vec_dec v__451 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec i5
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec i40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))"
+ for v__451 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SUB ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_XOR ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_OR ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_AND ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SUBW ((rsd, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ADDW ((rsd, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_J (v__452)) = (
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__452 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__452 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__452 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__452 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__452 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__452 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__452 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__452 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__452 (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word))
+ :: 9 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))))))))"
+ for v__452 :: "(11)Word.word "
+|" encdec_compressed_forwards (C_BEQZ ((v__453, rs))) = (
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__453 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__453 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__453 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__453 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__453 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__453 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))"
+ for rs :: "(3)Word.word "
+ and v__453 :: "(8)Word.word "
+|" encdec_compressed_forwards (C_BNEZ ((v__454, rs))) = (
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__454 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__454 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__454 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__454 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__454 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__454 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))"
+ for v__454 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SLLI ((v__455, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__455 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word))))))))))))))))
+ then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__455 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__455 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LWSP ((v__456, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__456 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__456 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__456 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (ui42 :: 3 bits) = ((subrange_vec_dec v__456 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui42
+ ((concat_vec ui76 (vec_of_bits [B1,B0] :: 2 Word.word) :: 4 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__456 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LDSP ((v__457, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__457 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__457 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__457 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (ui43 :: 2 bits) = ((subrange_vec_dec v__457 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui43
+ ((concat_vec ui86 (vec_of_bits [B1,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__457 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SWSP ((v__458, rs2))) = (
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__458 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__458 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui52 :: 4 bits) = ((subrange_vec_dec v__458 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec ui52
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 9 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))"
+ for v__458 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SDSP ((v__459, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__459 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__459 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__459 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec ui86
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__459 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_JR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec rd
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_EBREAK (_)) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+|" encdec_compressed_forwards (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec rsd
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_ILLEGAL (s)) = ( return s )"
+ for s :: "(16)Word.word "
+|" encdec_compressed_forwards _ = ( assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+
+
+\<comment> \<open>\<open>val encdec_compressed_backwards : mword ty16 -> ast\<close>\<close>
+
+definition encdec_compressed_backwards :: "(16)Word.word \<Rightarrow> ast " where
+ " encdec_compressed_backwards arg1 = (
+ (let v__460 = arg1 in
+ if (((v__460 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))
+ then
+ C_NOP ()
+ else if (((((let (nz96 :: 4 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ C_ADDI4SPN (rd,
+ (concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_LW ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word), rs1, rd))))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_LD ((concat_vec ui76 ui53 :: 5 Word.word), rs1, rd)))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ C_SW ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word), rs1, rs2))))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: 3 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: 3 bits) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ C_SD ((concat_vec ui76 ui53 :: 5 Word.word), rs1, rs2)))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADDI ((concat_vec nzi5 nzi40 :: 6 Word.word), rsd))))
+ else if (((((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__460 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in
+ C_JAL ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 9 Word.word))
+ :: 10 Word.word))
+ :: 11 Word.word))))))))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADDIW ((concat_vec imm5 imm40 :: 6 Word.word), rsd))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_LI ((concat_vec imm5 imm40 :: 6 Word.word), rd))))
+ else if (((((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regidx_to_regno ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ C_ADDI16SP ((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)))))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_LUI ((concat_vec imm17 imm1612 :: 6 Word.word), rd))))
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SRLI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SRAI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ANDI ((concat_vec i5 i40 :: 6 Word.word), rsd))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_SUB (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_XOR (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_OR (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_AND (rsd, rs2)))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_SUBW (rsd, rs2)))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_ADDW (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__460 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in
+ C_J ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 9 Word.word))
+ :: 10 Word.word))
+ :: 11 Word.word))))))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (rs :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ C_BEQZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word),
+ rs)))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (rs :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ C_BNEZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word),
+ rs)))))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word)))))))))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SLLI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (ui42 :: 3 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_LWSP ((concat_vec ui76 ((concat_vec ui5 ui42 :: 4 Word.word)) :: 6 Word.word), rd)))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (ui43 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_LDSP ((concat_vec ui86 ((concat_vec ui5 ui43 :: 3 Word.word)) :: 6 Word.word), rd)))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (ui52 :: 4 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SWSP ((concat_vec ui76 ui52 :: 6 Word.word), rs2))))
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SDSP ((concat_vec ui86 ui53 :: 6 Word.word), rs2))))
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ (let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_JR rs1)
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ (let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_JALR rs1)
+ else if (((((let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_MV (rd, rs2)))
+ else if (((v__460 = (vec_of_bits [B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 16 Word.word)))) then
+ C_EBREAK ()
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADD (rsd, rs2)))
+ else C_ILLEGAL v__460))"
+ for arg1 :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_compressed_forwards_matches : ast -> bool\<close>\<close>
+
+fun encdec_compressed_forwards_matches :: " ast \<Rightarrow> bool " where
+ " encdec_compressed_forwards_matches (C_NOP (_)) = ( True )"
+|" encdec_compressed_forwards_matches (C_ADDI4SPN ((rd, v__596))) = (
+ if ((let (nz96 :: 4 bits) = ((subrange_vec_dec v__596 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__596 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__596 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__596 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__596 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))))))) then
+ True
+ else False )"
+ for v__596 :: "(8)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_LW ((v__597, rs1, rd))) = ( True )"
+ for v__597 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_LD ((v__598, rs1, rd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__598 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SW ((v__599, rs1, rs2))) = ( True )"
+ for v__599 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SD ((v__600, rs1, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__600 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDI ((v__601, rsd))) = (
+ if ((let (nzi5 :: 1 bits) = ((subrange_vec_dec v__601 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__601 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__601 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) then
+ True
+ else False )"
+ for v__601 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JAL (v__602)) = ( if ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) then True else False )"
+ for v__602 :: "(11)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDIW ((v__603, rsd))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for v__603 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LI ((v__604, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for v__604 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDI16SP (v__605)) = (
+ if ((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__605 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__605 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__605 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__605 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__605 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__605 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then
+ True
+ else False )"
+ for v__605 :: "(6)Word.word "
+|" encdec_compressed_forwards_matches (C_LUI ((v__606, rd))) = (
+ if ((let (imm17 :: 1 bits) = ((subrange_vec_dec v__606 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__606 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__606 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) then
+ True
+ else False )"
+ for v__606 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SRLI ((v__607, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__607 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__607 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__607 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ True
+ else False )"
+ for v__607 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SRAI ((v__608, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__608 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__608 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__608 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ True
+ else False )"
+ for v__608 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ANDI ((v__609, rsd))) = ( True )"
+ for v__609 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SUB ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_XOR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_OR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_AND ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SUBW ((rsd, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDW ((rsd, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_J (v__610)) = ( True )"
+ for v__610 :: "(11)Word.word "
+|" encdec_compressed_forwards_matches (C_BEQZ ((v__611, rs))) = ( True )"
+ for v__611 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_BNEZ ((v__612, rs))) = ( True )"
+ for v__612 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SLLI ((v__613, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__613 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__613 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__613 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word))))))))))))))))
+ then
+ True
+ else False )"
+ for v__613 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LWSP ((v__614, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for v__614 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LDSP ((v__615, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for v__615 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SWSP ((v__616, rs2))) = ( True )"
+ for v__616 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SDSP ((v__617, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__617 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JR (rs1)) = ( if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_EBREAK (_)) = ( True )"
+|" encdec_compressed_forwards_matches (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_ILLEGAL (s)) = ( True )"
+ for s :: "(16)Word.word "
+|" encdec_compressed_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_compressed_backwards_matches : mword ty16 -> bool\<close>\<close>
+
+definition encdec_compressed_backwards_matches :: "(16)Word.word \<Rightarrow> bool " where
+ " encdec_compressed_backwards_matches arg1 = (
+ (let v__618 = arg1 in
+ if (((v__618 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))
+ then
+ True
+ else if (((((let (nz96 :: 4 bits) = ((subrange_vec_dec v__618 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__618 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__618 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__618 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__618 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regidx_to_regno ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word)))))))))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ True
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ True
+ else if (((((let (rs2 :: regidx) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((v__618 = (vec_of_bits [B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 16 Word.word)))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else True))"
+ for arg1 :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val execute_WFI : unit -> M Retired\<close>\<close>
+
+definition execute_WFI :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_WFI _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ Machine => platform_wfi () \<then> return RETIRE_SUCCESS
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ if (((((get_Mstatus_TW w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ handle_illegal () \<then> return RETIRE_FAIL
+ else platform_wfi () \<then> return RETIRE_SUCCESS)
+ | User => handle_illegal () \<then> return RETIRE_FAIL
+ )))"
+
+
+\<comment> \<open>\<open>val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M Retired\<close>\<close>
+
+definition execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_UTYPE imm rd op1 = (
+ (let (off :: xlenbits) =
+ ((EXTS (( 32 :: int)::ii)
+ ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ :: 32 Word.word))
+ :: 32 Word.word)) in
+ (case op1 of
+ RISCV_LUI => return off
+ | RISCV_AUIPC =>
+ (get_arch_pc () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ return ((add_vec w__0 off :: 32 Word.word)))
+ ) \<bind> (\<lambda> (ret :: xlenbits) .
+ wX ((regidx_to_regno rd)) ret \<then> return RETIRE_SUCCESS)))"
+ for imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " uop "
+
+
+\<comment> \<open>\<open>val execute_URET : unit -> M Retired\<close>\<close>
+
+definition execute_URET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_URET _ = (
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ (if ((\<not> w__0)) then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (exception_handler w__1 (CTL_URET () ) w__2 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ set_next_pc w__3)))) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_STORECON :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_STORECON aq rl rs2 rs1 width rd = (
+ speculate_conditional_success () \<bind> (\<lambda> (w__0 :: bool) .
+ if (((w__0 = False))) then
+ wX ((regidx_to_regno rd)) ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) \<then>
+ return RETIRE_SUCCESS
+ else
+ haveAtomics () \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 32 :: int)::ii) :: 32 Word.word)) Write width \<bind> (\<lambda> (w__2 :: unit
+ Ext_DataAddr_Check) .
+ (case w__2 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (let (aligned :: bool) =
+ ((case width of
+ BYTE => True
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))
+ )) in
+ if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return RETIRE_FAIL
+ else if (((((match_reservation vaddr)) = False))) then
+ wX ((regidx_to_regno rd)) ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ else
+ (translateAddr vaddr Write :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__3 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__3 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) => mem_write_ea addr (( 4 :: int)::ii) aq rl True
+ | _ => internal_error (''STORECON expected word or double'')
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) =>
+ mem_write_value addr (( 4 :: int)::ii)
+ ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq rl True
+ | _ => internal_error (''STORECON expected word or double'')
+ ) \<bind> (\<lambda> (res :: bool MemoryOpResult) .
+ (case res of
+ MemValue (True) =>
+ wX ((regidx_to_regno rd))
+ ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ | MemValue (False) =>
+ wX ((regidx_to_regno rd))
+ ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ )))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL)))"
+ for aq :: " bool "
+ and rl :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_STORE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_STORE imm rs2 rs1 width aq rl = (
+ (let (offset :: xlenbits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in
+ ext_data_get_addr rs1 offset Write width \<bind> (\<lambda> (w__0 :: unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then
+ handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Write :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__1 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case width of
+ BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False
+ | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False
+ | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False
+ | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (case (width, (( 32 :: int)::ii)) of
+ (BYTE, _) =>
+ mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ aq rl False
+ | (HALF, _) =>
+ mem_write_value addr (( 2 :: int)::ii)
+ ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) aq rl False
+ | (WORD, _) =>
+ mem_write_value addr (( 4 :: int)::ii)
+ ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq rl False
+ ) \<bind> (\<lambda> (res :: bool MemoryOpResult) .
+ (case res of
+ MemValue (True) => return RETIRE_SUCCESS
+ | MemValue (False) => internal_error (''store got false from mem_write_value'')
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ ))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and aq :: " bool "
+ and rl :: " bool "
+
+
+\<comment> \<open>\<open>val execute_SRET : unit -> M Retired\<close>\<close>
+
+definition execute_SRET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SRET _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ User => handle_illegal ()
+ | Supervisor =>
+ or_boolM (haveSupMode () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (((((get_Mstatus_TSR w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) \<bind> (\<lambda> (w__3 ::
+ bool) .
+ if w__3 then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__4 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) .
+ (exception_handler w__4 (CTL_SRET () ) w__5 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) .
+ set_next_pc w__6))))
+ | Machine =>
+ haveSupMode () \<bind> (\<lambda> (w__7 :: bool) .
+ if ((\<not> w__7)) then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__8 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) .
+ (exception_handler w__8 (CTL_SRET () ) w__9 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) .
+ set_next_pc w__10))))
+ ) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M Retired\<close>\<close>
+
+definition execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTW shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt :: 32 Word.word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 32 Word.word)
+ | RISCV_SRAI => (shift_right_arith32 rs1_val shamt :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 32 :: int)::ii) result :: 32 Word.word)) \<then> return RETIRE_SUCCESS))))"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sop "
+
+
+\<comment> \<open>\<open>val execute_SHIFTIWOP : mword ty5 -> mword ty5 -> mword ty5 -> sopw -> M Retired\<close>\<close>
+
+definition execute_SHIFTIWOP :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sopw \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTIWOP shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_SLLIW =>
+ (shift_bits_left ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ | RISCV_SRLIW =>
+ (shift_bits_right ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ | RISCV_SRAIW =>
+ (shift_right_arith32 ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 32 :: int)::ii) result :: 32 Word.word)) \<then> return RETIRE_SUCCESS)))"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sopw "
+
+
+\<comment> \<open>\<open>val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M Retired\<close>\<close>
+
+definition execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTIOP shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_SLLI =>
+ (shift_bits_left rs1_val ((subrange_vec_dec shamt (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) :: 32 Word.word)
+ | RISCV_SRLI =>
+ (shift_bits_right rs1_val ((subrange_vec_dec shamt (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRAI =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec shamt (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sop "
+
+
+\<comment> \<open>\<open>val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SFENCE_VMA rs1 rs2 = (
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then return None
+ else
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ return (Some w__0))) \<bind> (\<lambda> (addr :: xlenbits option) .
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then return None
+ else
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ return (Some w__1))) \<bind> (\<lambda> (asid :: xlenbits option) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ (case w__2 of
+ User => handle_illegal () \<then> return RETIRE_FAIL
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ (let p__1 =
+ (architecture ((get_mstatus_SXL w__3 :: 2 Word.word)), (get_Mstatus_TVM w__4 :: 1 Word.word)) in
+ (case p__1 of
+ (Some (g__0), v_0) =>
+ if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then
+ handle_illegal () \<then> return RETIRE_FAIL
+ else if (((v_0 = ((bool_to_bits False :: 1 Word.word))))) then
+ flush_TLB asid addr \<then> return RETIRE_SUCCESS
+ else
+ (case (Some g__0, v_0) of
+ (_, _) => internal_error (''unimplemented sfence architecture'')
+ )
+ | (_, _) => internal_error (''unimplemented sfence architecture'')
+ ))))
+ | Machine => flush_TLB asid addr \<then> return RETIRE_SUCCESS
+ )))))"
+ for rs1 :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M Retired\<close>\<close>
+
+definition execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RTYPEW rs2 rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_ADDW => (add_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SUBW => (sub_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SLLW =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRLW =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRAW =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 32 :: int)::ii) result :: 32 Word.word)) \<then> return RETIRE_SUCCESS))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " ropw "
+
+
+\<comment> \<open>\<open>val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M Retired\<close>\<close>
+
+definition execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RTYPE rs2 rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_ADD => (add_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SLT =>
+ (EXTZ (( 32 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) :: 1 Word.word)) :: 32 Word.word)
+ | RISCV_SLTU =>
+ (EXTZ (( 32 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) :: 1 Word.word)) :: 32 Word.word)
+ | RISCV_AND => (and_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_OR => (or_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_XOR => (xor_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SLL =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRL =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SUB => (sub_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SRA =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " rop "
+
+
+\<comment> \<open>\<open>val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RISCV_JALR imm rs1 rd = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) :: 32 Word.word)) in
+ (case ((ext_control_check_addr t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (addr) =>
+ (let target = ((update_vec_dec addr (( 0 :: int)::ii) B0 :: 32 Word.word)) in
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (get_next_pc () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ (wX ((regidx_to_regno rd)) w__3 \<then> set_next_pc target) \<then> return RETIRE_SUCCESS)))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_RISCV_JAL :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RISCV_JAL imm rd = (
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) :: 32 Word.word)) in
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (target) =>
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (get_next_pc () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ (wX ((regidx_to_regno rd)) w__3 \<then> set_next_pc target) \<then> return RETIRE_SUCCESS))
+ ))))"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_REMW rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 32 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 32 Word.word)) \<then>
+ return RETIRE_SUCCESS)))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_REM :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_REM rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+ wX ((regidx_to_regno rd)) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) \<then> return RETIRE_SUCCESS)))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MULW rs2 rs1 rd = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (Word.sint rs1_val) in
+ (let (rs2_int :: ii) = (Word.sint rs2_val) in
+ (let result32 =
+ ((subrange_vec_dec ((to_bits (( 64 :: int)::ii) ((rs1_int * rs2_int)) :: 64 Word.word)) (( 31 :: int)::ii)
+ (( 0 :: int)::ii)
+ :: 32 Word.word)) in
+ (let (result :: xlenbits) = ((EXTS (( 32 :: int)::ii) result32 :: 32 Word.word)) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MUL rs2 rs1 rd high signed1 signed2 = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if signed1 then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if signed2 then Word.sint rs2_val else Word.uint rs2_val) in
+ (let result_wide =
+ ((to_bits (((( 2 :: int)::ii) * (( 32 :: int)::ii))) ((rs1_int * rs2_int)) :: 64 Word.word)) in
+ (let result =
+ (if high then
+ (subrange_vec_dec result_wide (((((( 2 :: int)::ii) * (( 32 :: int)::ii))) - (( 1 :: int)::ii)))
+ (( 32 :: int)::ii)
+ :: 32 Word.word)
+ else (subrange_vec_dec result_wide (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 32 Word.word)) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and high :: " bool "
+ and signed1 :: " bool "
+ and signed2 :: " bool "
+
+
+\<comment> \<open>\<open>val execute_MRET : unit -> M Retired\<close>\<close>
+
+definition execute_MRET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MRET _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (exception_handler w__1 (CTL_MRET () ) w__2 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ set_next_pc w__3)))
+ else handle_illegal () ) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_LOADRES :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_LOADRES aq rl rs1 width rd = (
+ haveAtomics () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 32 :: int)::ii) :: 32 Word.word)) Read width \<bind> (\<lambda> (w__1 :: unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (let (aligned :: bool) =
+ ((case width of
+ BYTE => True
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))
+ )) in
+ if ((\<not> aligned)) then handle_mem_exception vaddr E_Load_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Read :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__2 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) =>
+ (mem_read Read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 32 Word.word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__3 False)
+ | _ => internal_error (''LOADRES expected WORD or DOUBLE'')
+ )
+ )))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for aq :: " bool "
+ and rl :: " bool "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_LOAD imm rs1 rd is_unsigned width aq rl = (
+ (let (offset :: xlenbits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in
+ ext_data_get_addr rs1 offset Read width \<bind> (\<lambda> (w__0 :: unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then
+ handle_mem_exception vaddr E_Load_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Read :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__1 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 32 :: int)::ii)) of
+ (BYTE, _) =>
+ (mem_read Read addr (( 1 :: int)::ii) aq rl False :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word)
+ MemoryOpResult) .
+ process_load rd vaddr w__2 is_unsigned)
+ | (HALF, _) =>
+ (mem_read Read addr (( 2 :: int)::ii) aq rl False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 16 Word.word)
+ MemoryOpResult) .
+ process_load rd vaddr w__4 is_unsigned)
+ | (WORD, _) =>
+ (mem_read Read addr (( 4 :: int)::ii) aq rl False :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__6 :: ( 32 Word.word)
+ MemoryOpResult) .
+ process_load rd vaddr w__6 is_unsigned)
+ )
+ ))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and width :: " word_width "
+ and aq :: " bool "
+ and rl :: " bool "
+
+
+\<comment> \<open>\<open>val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M Retired\<close>\<close>
+
+definition execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ITYPE imm rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (immext :: xlenbits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_ADDI => (add_vec rs1_val immext :: 32 Word.word)
+ | RISCV_SLTI =>
+ (EXTZ (( 32 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) :: 1 Word.word)) :: 32 Word.word)
+ | RISCV_SLTIU =>
+ (EXTZ (( 32 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) :: 1 Word.word)) :: 32 Word.word)
+ | RISCV_ANDI => (and_vec rs1_val immext :: 32 Word.word)
+ | RISCV_ORI => (or_vec rs1_val immext :: 32 Word.word)
+ | RISCV_XORI => (xor_vec rs1_val immext :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " iop "
+
+
+\<comment> \<open>\<open>val execute_ILLEGAL : mword ty32 -> M Retired\<close>\<close>
+
+definition execute_ILLEGAL :: "(32)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ILLEGAL s = ( handle_illegal () \<then> return RETIRE_FAIL )"
+ for s :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val execute_FENCE_TSO : mword ty4 -> mword ty4 -> M Retired\<close>\<close>
+
+definition execute_FENCE_TSO :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_FENCE_TSO pred succ = (
+ (case (pred, succ) of
+ (v__794, v__795) =>
+ if ((((((((subrange_vec_dec v__794 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__795 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_tso
+ else
+ return (if ((((((((subrange_vec_dec v__794 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__795 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ ()
+ else
+ (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in
+ () ))
+ ) \<then>
+ return RETIRE_SUCCESS )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val execute_FENCEI : unit -> Retired\<close>\<close>
+
+definition execute_FENCEI :: " unit \<Rightarrow> Retired " where
+ " execute_FENCEI _ = ( RETIRE_SUCCESS )"
+
+
+\<comment> \<open>\<open>val execute_FENCE : mword ty4 -> mword ty4 -> M Retired\<close>\<close>
+
+definition execute_FENCE :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_FENCE pred succ = (
+ (case (pred, succ) of
+ (v__754, v__755) =>
+ if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_r
+ else
+ return (if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ ()
+ else
+ (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in
+ () ))
+ ) \<then>
+ return RETIRE_SUCCESS )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val execute_ECALL : unit -> M Retired\<close>\<close>
+
+definition execute_ECALL :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ECALL _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap =
+ ((case w__0 of
+ User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ )),
+ sync_exception_excinfo = None,
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (exception_handler w__1 (CTL_TRAP t) w__2 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) .
+ set_next_pc w__3 \<then> return RETIRE_FAIL))))))"
+
+
+\<comment> \<open>\<open>val execute_EBREAK : unit -> M Retired\<close>\<close>
+
+definition execute_EBREAK :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_EBREAK _ = (
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ handle_mem_exception w__0 E_Breakpoint \<then> return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_DIVW rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in
+ (let (q' :: ii) =
+ (if (((s \<and> ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then
+ (( 0 :: int)::ii) - ((pow (( 2 :: int)::ii) (( 31 :: int)::ii)))
+ else q) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 32 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 32 Word.word)) \<then>
+ return RETIRE_SUCCESS))))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_DIV rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in
+ (let (q' :: ii) = (if (((s \<and> ((q > xlen_max_signed))))) then xlen_min_signed else q) in
+ wX ((regidx_to_regno rd)) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) \<then> return RETIRE_SUCCESS))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_C_NOP : unit -> Retired\<close>\<close>
+
+definition execute_C_NOP :: " unit \<Rightarrow> Retired " where
+ " execute_C_NOP _ = ( RETIRE_SUCCESS )"
+
+
+\<comment> \<open>\<open>val execute_C_ILLEGAL : mword ty16 -> M Retired\<close>\<close>
+
+definition execute_C_ILLEGAL :: "(16)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_C_ILLEGAL s = ( handle_illegal () \<then> return RETIRE_FAIL )"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M Retired\<close>\<close>
+
+definition execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_CSR csr rs1 rd is_imm op1 = (
+ (if is_imm then return ((EXTZ (( 32 :: int)::ii) rs1 :: 32 Word.word))
+ else (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M)) \<bind> (\<lambda> (rs1_val :: xlenbits) .
+ (let (isWrite :: bool) =
+ ((case op1 of
+ CSRRW => True
+ | _ => if is_imm then (((Word.uint rs1_val)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii))
+ )) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ check_CSR csr w__1 isWrite \<bind> (\<lambda> (w__2 :: bool) .
+ if ((\<not> w__2)) then handle_illegal () \<then> return RETIRE_FAIL
+ else
+ (readCSR csr :: ( 32 Word.word) M) \<bind> (\<lambda> csr_val .
+ ((if isWrite then
+ (let (new_val :: xlenbits) =
+ ((case op1 of
+ CSRRW => rs1_val
+ | CSRRS => (or_vec csr_val rs1_val :: 32 Word.word)
+ | CSRRC => (and_vec csr_val ((not_vec rs1_val :: 32 Word.word)) :: 32 Word.word)
+ )) in
+ writeCSR csr new_val)
+ else return () ) \<then>
+ wX ((regidx_to_regno rd)) csr_val) \<then> return RETIRE_SUCCESS))))))"
+ for csr :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and is_imm :: " bool "
+ and op1 :: " csrop "
+
+
+\<comment> \<open>\<open>val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M Retired\<close>\<close>
+
+definition execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_BTYPE imm rs2 rs1 op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (taken :: bool) =
+ ((case op1 of
+ RISCV_BEQ => (rs1_val = rs2_val)
+ | RISCV_BNE => (rs1_val \<noteq> rs2_val)
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ )) in
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) :: 32 Word.word)) in
+ if taken then
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (target) =>
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else set_next_pc target \<then> return RETIRE_SUCCESS)
+ )
+ else return RETIRE_SUCCESS))))))"
+ for imm :: "(13)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and op1 :: " bop "
+
+
+\<comment> \<open>\<open>val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_AMO op1 aq rl rs2 rs1 width rd = (
+ haveAtomics () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 32 :: int)::ii) :: 32 Word.word)) ReadWrite width \<bind> (\<lambda> (w__1 :: unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (translateAddr vaddr ReadWrite :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__2 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) => mem_write_ea addr (( 4 :: int)::ii) (((aq \<and> rl))) rl True
+ | _ => internal_error (''AMO expected WORD or DOUBLE'')
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (rX ((regidx_to_regno rs2)) :: ( 32 Word.word) M) \<bind> (\<lambda> (rs2_val :: xlenbits) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) =>
+ (mem_read ReadWrite addr (( 4 :: int)::ii) aq (((aq \<and> rl))) True
+ :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 32 Word.word) MemoryOpResult) .
+ return ((extend_value False w__5 :: ( 32 Word.word) MemoryOpResult)))
+ | _ =>
+ (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 32 Word.word)MemoryOpResult) M)
+ ) \<bind> (\<lambda> (rval :: xlenbits MemoryOpResult) .
+ (case rval of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (loaded) =>
+ (let (result :: xlenbits) =
+ ((case op1 of
+ AMOSWAP => rs2_val
+ | AMOADD => (add_vec rs2_val loaded :: 32 Word.word)
+ | AMOXOR => (xor_vec rs2_val loaded :: 32 Word.word)
+ | AMOAND => (and_vec rs2_val loaded :: 32 Word.word)
+ | AMOOR => (or_vec rs2_val loaded :: 32 Word.word)
+ | AMOMIN =>
+ (to_bits (( 32 :: int)::ii) ((min ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 32 Word.word)
+ | AMOMAX =>
+ (to_bits (( 32 :: int)::ii) ((max ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 32 Word.word)
+ | AMOMINU =>
+ (to_bits (( 32 :: int)::ii) ((min ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 32 Word.word)
+ | AMOMAXU =>
+ (to_bits (( 32 :: int)::ii) ((max ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 32 Word.word)
+ )) in
+ (case (width, (( 32 :: int)::ii)) of
+ (WORD, _) =>
+ mem_write_value addr (( 4 :: int)::ii)
+ ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) (((aq \<and> rl))) rl
+ True
+ | _ => internal_error (''AMO expected WORD or DOUBLE'')
+ ) \<bind> (\<lambda> (wval :: bool MemoryOpResult) .
+ (case wval of
+ MemValue (True) => wX ((regidx_to_regno rd)) loaded \<then> return RETIRE_SUCCESS
+ | MemValue (False) => internal_error (''AMO got false from mem_write_value'')
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ )))
+ ))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for op1 :: " amoop "
+ and aq :: " bool "
+ and rl :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_ADDIW :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ADDIW imm rs1 rd = (
+ (rX ((regidx_to_regno rs1)) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (let (result :: xlenbits) = ((add_vec ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) w__0 :: 32 Word.word)) in
+ wX ((regidx_to_regno rd))
+ ((EXTS (( 32 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) \<then>
+ return RETIRE_SUCCESS)))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute (C_ADDI4SPN ((rdc, nzimm))) = (
+ (let (imm :: 12 bits) =
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 10 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ execute (ITYPE (imm, sp, rd, RISCV_ADDI)))))"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_LW ((uimm, rsc, rdc))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ (let rs = ((creg2reg_idx rsc :: 5 Word.word)) in
+ execute (LOAD (imm, rs, rd, False, WORD, False, False))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_LD ((uimm, rsc, rdc))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ (let rs = ((creg2reg_idx rsc :: 5 Word.word)) in
+ execute (LOAD (imm, rs, rd, False, DOUBLE, False, False))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_SW ((uimm, rsc1, rsc2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word)) in
+ (let rs1 = ((creg2reg_idx rsc1 :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rsc2 :: 5 Word.word)) in
+ execute (STORE (imm, rs2, rs1, WORD, False, False))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" execute (C_SD ((uimm, rsc1, rsc2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ (let rs1 = ((creg2reg_idx rsc1 :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rsc2 :: 5 Word.word)) in
+ execute (STORE (imm, rs2, rs1, DOUBLE, False, False))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" execute (C_ADDI ((nzi, rsd))) = (
+ (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) nzi :: 12 Word.word)) in
+ execute (ITYPE (imm, rsd, rsd, RISCV_ADDI))))"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" execute (C_JAL (imm)) = (
+ execute
+ (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word))
+ :: 21 Word.word),
+ ra)))"
+ for imm :: "(11)Word.word "
+|" execute (C_ADDIW ((imm, rsd))) = ( execute (ADDIW ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word), rsd, rsd)))"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" execute (C_LI ((imm, rd))) = (
+ (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word)) in
+ execute (ITYPE (imm, zreg, rd, RISCV_ADDI))))"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_ADDI16SP (imm)) = (
+ (let (imm :: 12 bits) =
+ ((EXTS (( 12 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 10 Word.word))
+ :: 12 Word.word)) in
+ execute (ITYPE (imm, sp, sp, RISCV_ADDI))))"
+ for imm :: "(6)Word.word "
+|" execute (C_LUI ((imm, rd))) = (
+ (let (res :: 20 bits) = ((EXTS (( 20 :: int)::ii) imm :: 20 Word.word)) in
+ execute (UTYPE (res, rd, RISCV_LUI))))"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_SRLI ((shamt, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))))"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_SRAI ((shamt, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))))"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_ANDI ((imm, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (ITYPE ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word), rsd, rsd, RISCV_ANDI))))"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" execute (C_SUB ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_SUB)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_XOR ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_XOR)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_OR ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_OR)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_AND ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_AND)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_SUBW ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_SUBW)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_ADDW ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_ADDW)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_J (imm)) = (
+ execute
+ (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word))
+ :: 21 Word.word),
+ zreg)))"
+ for imm :: "(11)Word.word "
+|" execute (C_BEQZ ((imm, rs))) = (
+ execute
+ (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word))
+ :: 13 Word.word),
+ zreg,
+ (creg2reg_idx rs :: 5 Word.word),
+ RISCV_BEQ)))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" execute (C_BNEZ ((imm, rs))) = (
+ execute
+ (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word))
+ :: 13 Word.word),
+ zreg,
+ (creg2reg_idx rs :: 5 Word.word),
+ RISCV_BNE)))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" execute (C_SLLI ((shamt, rsd))) = ( execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI)))"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_LWSP ((uimm, rd))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ execute (LOAD (imm, sp, rd, False, WORD, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_LDSP ((uimm, rd))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word))
+ :: 12 Word.word)) in
+ execute (LOAD (imm, sp, rd, False, DOUBLE, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_SWSP ((uimm, rs2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ execute (STORE (imm, rs2, sp, WORD, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (C_SDSP ((uimm, rs2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word))
+ :: 12 Word.word)) in
+ execute (STORE (imm, rs2, sp, DOUBLE, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (C_JR (rs1)) = (
+ execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word), rs1, zreg)))"
+ for rs1 :: "(5)Word.word "
+|" execute (C_JALR (rs1)) = (
+ execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word), rs1, ra)))"
+ for rs1 :: "(5)Word.word "
+|" execute (C_MV ((rd, rs2))) = ( execute (RTYPE (rs2, zreg, rd, RISCV_ADD)))"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_EBREAK (_)) = ( execute (EBREAK () ))"
+|" execute (C_ADD ((rsd, rs2))) = ( execute (RTYPE (rs2, rsd, rsd, RISCV_ADD)))"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (UTYPE ((imm, rd, op1))) = ( execute_UTYPE imm rd op1 )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RISCV_JAL ((imm, rd))) = ( execute_RISCV_JAL imm rd )"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (BTYPE ((imm, rs2, rs1, op1))) = ( execute_BTYPE imm rs2 rs1 op1 )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" execute (ITYPE ((imm, rs1, rd, op1))) = ( execute_ITYPE imm rs1 rd op1 )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTIOP ((shamt, rs1, rd, op1))) = ( execute_SHIFTIOP shamt rs1 rd op1 )"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RTYPE ((rs2, rs1, rd, op1))) = ( execute_RTYPE rs2 rs1 rd op1 )"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl))) = (
+ execute_LOAD imm rs1 rd is_unsigned width aq rl )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (STORE ((imm, rs2, rs1, width, aq, rl))) = ( execute_STORE imm rs2 rs1 width aq rl )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (ADDIW ((imm, rs1, rd))) = ( execute_ADDIW imm rs1 rd )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTW ((shamt, rs1, rd, op1))) = ( execute_SHIFTW shamt rs1 rd op1 )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RTYPEW ((rs2, rs1, rd, op1))) = ( execute_RTYPEW rs2 rs1 rd op1 )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTIWOP ((shamt, rs1, rd, op1))) = ( execute_SHIFTIWOP shamt rs1 rd op1 )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (FENCE ((pred, succ))) = ( execute_FENCE pred succ )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" execute (FENCE_TSO ((pred, succ))) = ( execute_FENCE_TSO pred succ )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" execute (FENCEI (arg0)) = ( return ((execute_FENCEI arg0)))"
+ for arg0 :: " unit "
+|" execute (ECALL (arg0)) = ( execute_ECALL arg0 )"
+ for arg0 :: " unit "
+|" execute (MRET (arg0)) = ( execute_MRET arg0 )"
+ for arg0 :: " unit "
+|" execute (SRET (arg0)) = ( execute_SRET arg0 )"
+ for arg0 :: " unit "
+|" execute (EBREAK (arg0)) = ( execute_EBREAK arg0 )"
+ for arg0 :: " unit "
+|" execute (WFI (arg0)) = ( execute_WFI arg0 )"
+ for arg0 :: " unit "
+|" execute (SFENCE_VMA ((rs1, rs2))) = ( execute_SFENCE_VMA rs1 rs2 )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" execute (LOADRES ((aq, rl, rs1, width, rd))) = ( execute_LOADRES aq rl rs1 width rd )"
+ for rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (STORECON ((aq, rl, rs2, rs1, width, rd))) = ( execute_STORECON aq rl rs2 rs1 width rd )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = ( execute_AMO op1 aq rl rs2 rs1 width rd )"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (C_NOP (arg0)) = ( return ((execute_C_NOP arg0)))"
+ for arg0 :: " unit "
+|" execute (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( execute_MUL rs2 rs1 rd high signed1 signed2 )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (DIV ((rs2, rs1, rd, s))) = ( execute_DIV rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (REM ((rs2, rs1, rd, s))) = ( execute_REM rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (MULW ((rs2, rs1, rd))) = ( execute_MULW rs2 rs1 rd )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (DIVW ((rs2, rs1, rd, s))) = ( execute_DIVW rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (REMW ((rs2, rs1, rd, s))) = ( execute_REMW rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (CSR ((csr, rs1, rd, is_imm, op1))) = ( execute_CSR csr rs1 rd is_imm op1 )"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" execute (URET (arg0)) = ( execute_URET arg0 )"
+ for arg0 :: " unit "
+|" execute (RISCV_JALR ((imm, rs1, rd))) = ( execute_RISCV_JALR imm rs1 rd )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (ILLEGAL (s)) = ( execute_ILLEGAL s )"
+ for s :: "(32)Word.word "
+|" execute (C_ILLEGAL (s)) = ( execute_C_ILLEGAL s )"
+ for s :: "(16)Word.word "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val assembly_forwards : ast -> M string\<close>\<close>
+
+fun assembly_forwards :: " ast \<Rightarrow>((register_value),(string),(exception))monad " where
+ " assembly_forwards (UTYPE ((imm, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__0 :: string) .
+ return ((string_append ((utype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__0
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RISCV_JAL ((imm, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__1 :: string) .
+ return ((string_append (''jal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__1
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RISCV_JALR ((imm, rs1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__2 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__3 :: string) .
+ return ((string_append (''jalr'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__2
+ ((string_append ((sep_forwards () ))
+ ((string_append w__3
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (BTYPE ((imm, rs2, rs1, op1))) = (
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__4 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__5 :: string) .
+ return ((string_append ((btype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__4
+ ((string_append ((sep_forwards () ))
+ ((string_append w__5
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" assembly_forwards (ITYPE ((imm, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__6 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__7 :: string) .
+ return ((string_append ((itype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__6
+ ((string_append ((sep_forwards () ))
+ ((string_append w__7
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTIOP ((shamt, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__8 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__9 :: string) .
+ return ((string_append ((shiftiop_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__8
+ ((string_append ((sep_forwards () ))
+ ((string_append w__9
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))))))))"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RTYPE ((rs2, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__10 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__11 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__12 :: string) .
+ return ((string_append ((rtype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__10
+ ((string_append ((sep_forwards () ))
+ ((string_append w__11
+ ((string_append ((sep_forwards () )) ((string_append w__12 ('''')))))))))))))))))))"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__13 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__14 :: string) .
+ return ((string_append (''l'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_u_forwards is_unsigned))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__13
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm))
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append (''('')
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append w__14
+ ((string_append
+ ((opt_spc_forwards () ))
+ ((string_append ('')'') (''''))))))))))))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (STORE ((imm, rs2, rs1, size1, aq, rl))) = (
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__15 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__16 :: string) .
+ return ((string_append (''s'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__15
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm))
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append (''('')
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append w__16
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append ('')'') (''''))))))))))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (ADDIW ((imm, rs1, rd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__17 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__18 :: string) .
+ return ((string_append (''addiw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__17
+ ((string_append ((sep_forwards () ))
+ ((string_append w__18
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTW ((shamt, rs1, rd, op1))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__21 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__22 :: string) .
+ return ((string_append ((shiftw_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__21
+ ((string_append ((sep_forwards () ))
+ ((string_append w__22
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RTYPEW ((rs2, rs1, rd, op1))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__25 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__26 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__27 :: string) .
+ return ((string_append ((rtypew_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__25
+ ((string_append ((sep_forwards () ))
+ ((string_append w__26
+ ((string_append ((sep_forwards () )) ((string_append w__27 (''''))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTIWOP ((shamt, rs1, rd, op1))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__30 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__31 :: string) .
+ return ((string_append ((shiftiwop_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__30
+ ((string_append ((sep_forwards () ))
+ ((string_append w__31
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (FENCE ((pred, succ))) = (
+ fence_bits_forwards pred \<bind> (\<lambda> (w__34 :: string) .
+ fence_bits_forwards succ \<bind> (\<lambda> (w__35 :: string) .
+ return ((string_append (''fence'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__34
+ ((string_append ((sep_forwards () )) ((string_append w__35 (''''))))))))))))))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards (FENCE_TSO ((pred, succ))) = (
+ fence_bits_forwards pred \<bind> (\<lambda> (w__36 :: string) .
+ fence_bits_forwards succ \<bind> (\<lambda> (w__37 :: string) .
+ return ((string_append (''fence.tso'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__36
+ ((string_append ((sep_forwards () )) ((string_append w__37 (''''))))))))))))))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards (FENCEI (_)) = ( return (''fence.i''))"
+|" assembly_forwards (ECALL (_)) = ( return (''ecall''))"
+|" assembly_forwards (MRET (_)) = ( return (''mret''))"
+|" assembly_forwards (SRET (_)) = ( return (''sret''))"
+|" assembly_forwards (EBREAK (_)) = ( return (''ebreak''))"
+|" assembly_forwards (WFI (_)) = ( return (''wfi''))"
+|" assembly_forwards (SFENCE_VMA ((rs1, rs2))) = (
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__38 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__39 :: string) .
+ return ((string_append (''sfence.vma'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__38
+ ((string_append ((sep_forwards () )) ((string_append w__39 (''''))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" assembly_forwards (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__40 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__41 :: string) .
+ return ((string_append (''lr.'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__40
+ ((string_append ((sep_forwards () )) ((string_append w__41 (''''))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__42 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__43 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__44 :: string) .
+ return ((string_append (''sc.'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__42
+ ((string_append ((sep_forwards () ))
+ ((string_append w__43
+ ((string_append ((sep_forwards () ))
+ ((string_append w__44 ('''')))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__45 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__46 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__47 :: string) .
+ return ((string_append ((amo_mnemonic_forwards op1))
+ ((string_append (''.'')
+ ((string_append ((size_mnemonic_forwards width))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__45
+ ((string_append ((sep_forwards () ))
+ ((string_append w__46
+ ((string_append ((sep_forwards () ))
+ ((string_append w__47 ('''')))))))))))))))))))))))))))"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" assembly_forwards (C_NOP (_)) = ( return (''c.nop''))"
+|" assembly_forwards (C_ADDI4SPN ((rdc, nzimm))) = (
+ if (((nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then
+ creg_name_forwards rdc \<bind> (\<lambda> (w__48 :: string) .
+ return ((string_append (''c.addi4spn'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__48
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 10 Word.word)))) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_LW ((uimm, rsc, rdc))) = (
+ creg_name_forwards rdc \<bind> (\<lambda> (w__51 :: string) .
+ creg_name_forwards rsc \<bind> (\<lambda> (w__52 :: string) .
+ return ((string_append (''c.lw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__51
+ ((string_append ((sep_forwards () ))
+ ((string_append w__52
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 7 Word.word)))) (''''))))))))))))))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_LD ((uimm, rsc, rdc))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rdc \<bind> (\<lambda> (w__53 :: string) .
+ creg_name_forwards rsc \<bind> (\<lambda> (w__54 :: string) .
+ return ((string_append (''c.ld'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__53
+ ((string_append ((sep_forwards () ))
+ ((string_append w__54
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm
+ (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ :: 8 Word.word)))) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_SW ((uimm, rsc1, rsc2))) = (
+ creg_name_forwards rsc1 \<bind> (\<lambda> (w__57 :: string) .
+ creg_name_forwards rsc2 \<bind> (\<lambda> (w__58 :: string) .
+ return ((string_append (''c.sw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__57
+ ((string_append ((sep_forwards () ))
+ ((string_append w__58
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 7 Word.word)))) (''''))))))))))))))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards (C_SD ((uimm, rsc1, rsc2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsc1 \<bind> (\<lambda> (w__59 :: string) .
+ creg_name_forwards rsc2 \<bind> (\<lambda> (w__60 :: string) .
+ return ((string_append (''c.sd'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__59
+ ((string_append ((sep_forwards () ))
+ ((string_append w__60
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm
+ (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ :: 8 Word.word)))) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards (C_ADDI ((nzi, rsd))) = (
+ if ((((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__63 :: string) .
+ return ((string_append (''c.addi'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__63
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits nzi)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" assembly_forwards (C_JAL (imm)) = (
+ if ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) then
+ return ((string_append (''c.jal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)))) ('''')))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards (C_ADDIW ((imm, rsd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__68 :: string) .
+ return ((string_append (''c.addiw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__68
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards (C_LI ((imm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__71 :: string) .
+ return ((string_append (''c.li'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__71
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_ADDI16SP (imm)) = (
+ if (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ return ((string_append (''c.addi16sp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+|" assembly_forwards (C_LUI ((imm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__76 :: string) .
+ return ((string_append (''c.lui'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__76
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SRLI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__79 :: string) .
+ return ((string_append (''c.srli'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__79
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_SRAI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__82 :: string) .
+ return ((string_append (''c.srai'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__82
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_ANDI ((imm, rsd))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__85 :: string) .
+ return ((string_append (''c.andi'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__85
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards (C_SUB ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__86 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__87 :: string) .
+ return ((string_append (''c.sub'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__86
+ ((string_append ((sep_forwards () )) ((string_append w__87 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_XOR ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__88 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__89 :: string) .
+ return ((string_append (''c.xor'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__88
+ ((string_append ((sep_forwards () )) ((string_append w__89 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_OR ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__90 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__91 :: string) .
+ return ((string_append (''c.or'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__90
+ ((string_append ((sep_forwards () )) ((string_append w__91 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_AND ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__92 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__93 :: string) .
+ return ((string_append (''c.and'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__92
+ ((string_append ((sep_forwards () )) ((string_append w__93 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_SUBW ((rsd, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__94 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__95 :: string) .
+ return ((string_append (''c.subw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__94
+ ((string_append ((sep_forwards () )) ((string_append w__95 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_ADDW ((rsd, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__98 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__99 :: string) .
+ return ((string_append (''c.addw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__98
+ ((string_append ((sep_forwards () )) ((string_append w__99 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_J (imm)) = (
+ return ((string_append (''c.j'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))"
+ for imm :: "(11)Word.word "
+|" assembly_forwards (C_BEQZ ((imm, rs))) = (
+ creg_name_forwards rs \<bind> (\<lambda> (w__102 :: string) .
+ return ((string_append (''c.beqz'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__102
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards (C_BNEZ ((imm, rs))) = (
+ creg_name_forwards rs \<bind> (\<lambda> (w__103 :: string) .
+ return ((string_append (''c.bnez'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__103
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards (C_SLLI ((shamt, rsd))) = (
+ if ((((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__104 :: string) .
+ return ((string_append (''c.slli'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__104
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_LWSP ((uimm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__107 :: string) .
+ return ((string_append (''c.lwsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__107
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_LDSP ((uimm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ reg_name_forwards rd \<bind> (\<lambda> (w__110 :: string) .
+ return ((string_append (''c.ldsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__110
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SWSP ((uimm, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__113 :: string) .
+ return ((string_append (''c.swsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__113
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) ('''')))))))))))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SDSP ((uimm, rs2))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__114 :: string) .
+ return ((string_append (''c.sdsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__114
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards (C_JR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__117 :: string) .
+ return ((string_append (''c.jr'')
+ ((string_append ((spc_forwards () )) ((string_append w__117 (''''))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__120 :: string) .
+ return ((string_append (''c.jalr'')
+ ((string_append ((spc_forwards () )) ((string_append w__120 (''''))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__123 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__124 :: string) .
+ return ((string_append (''c.mv'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__123
+ ((string_append ((sep_forwards () )) ((string_append w__124 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_EBREAK (_)) = ( return (''c.ebreak''))"
+|" assembly_forwards (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__127 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__128 :: string) .
+ return ((string_append (''c.add'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__127
+ ((string_append ((sep_forwards () )) ((string_append w__128 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards (MUL ((rs2, rs1, rd, high, signed1, signed2))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__131 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__132 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__133 :: string) .
+ return ((string_append ((mul_mnemonic_forwards (high, signed1, signed2)))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__131
+ ((string_append ((sep_forwards () ))
+ ((string_append w__132
+ ((string_append ((sep_forwards () )) ((string_append w__133 ('''')))))))))))))))))))"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (DIV ((rs2, rs1, rd, s))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__134 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__135 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__136 :: string) .
+ return ((string_append (''div'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__134
+ ((string_append ((sep_forwards () ))
+ ((string_append w__135
+ ((string_append ((sep_forwards () )) ((string_append w__136 ('''')))))))))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (REM ((rs2, rs1, rd, s))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__137 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__138 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__139 :: string) .
+ return ((string_append (''rem'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__137
+ ((string_append ((sep_forwards () ))
+ ((string_append w__138
+ ((string_append ((sep_forwards () )) ((string_append w__139 ('''')))))))))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (MULW ((rs2, rs1, rd))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__140 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__141 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__142 :: string) .
+ return ((string_append (''mulw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__140
+ ((string_append ((sep_forwards () ))
+ ((string_append w__141
+ ((string_append ((sep_forwards () )) ((string_append w__142 (''''))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (DIVW ((rs2, rs1, rd, s))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__145 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__146 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__147 :: string) .
+ return ((string_append (''div'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append (''w'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__145
+ ((string_append ((sep_forwards () ))
+ ((string_append w__146
+ ((string_append ((sep_forwards () ))
+ ((string_append w__147 (''''))))))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (REMW ((rs2, rs1, rd, s))) = (
+ if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__150 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__151 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__152 :: string) .
+ return ((string_append (''rem'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append (''w'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__150
+ ((string_append ((sep_forwards () ))
+ ((string_append w__151
+ ((string_append ((sep_forwards () ))
+ ((string_append w__152 (''''))))))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (CSR ((csr, rs1, rd, True, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__155 :: string) .
+ csr_name_map_forwards csr \<bind> (\<lambda> (w__156 :: string) .
+ return ((string_append ((csr_mnemonic_forwards op1))
+ ((string_append (''i'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__155
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits rs1))
+ ((string_append ((sep_forwards () )) ((string_append w__156 (''''))))))))))))))))))))"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards (CSR ((csr, rs1, rd, False, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__157 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__158 :: string) .
+ csr_name_map_forwards csr \<bind> (\<lambda> (w__159 :: string) .
+ return ((string_append ((csr_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__157
+ ((string_append ((sep_forwards () ))
+ ((string_append w__158
+ ((string_append ((sep_forwards () )) ((string_append w__159 ('''')))))))))))))))))))"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards (URET (_)) = ( return (''uret''))"
+|" assembly_forwards (ILLEGAL (s)) = (
+ return ((string_append (''illegal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) (''''))))))))"
+ for s :: "(32)Word.word "
+|" assembly_forwards (C_ILLEGAL (s)) = (
+ return ((string_append (''c.illegal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) (''''))))))))"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val assembly_backwards : string -> M ast\<close>\<close>
+
+\<comment> \<open>\<open>val _s1677_ : string -> maybe (mword ty16)\<close>\<close>
+
+definition s1677 :: " string \<Rightarrow>((16)Word.word)option " where
+ " s1677 s16780 = (
+ (let s16790 = s16780 in
+ if ((string_startswith s16790 (''c.illegal''))) then
+ (case ((string_drop s16790 ((string_length (''c.illegal''))))) of
+ s16800 =>
+ (case ((spc_matches_prefix0 s16800)) of
+ Some ((_, s16810)) =>
+ (case ((string_drop s16800 s16810)) of
+ s16820 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16820 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s16830)) =>
+ (let p00 = (string_drop s16820 s16830) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16780 :: " string "
+
+
+\<comment> \<open>\<open>val _s1669_ : string -> maybe (mword ty32)\<close>\<close>
+
+definition s1669 :: " string \<Rightarrow>((32)Word.word)option " where
+ " s1669 s16700 = (
+ (let s16710 = s16700 in
+ if ((string_startswith s16710 (''illegal''))) then
+ (case ((string_drop s16710 ((string_length (''illegal''))))) of
+ s16720 =>
+ (case ((spc_matches_prefix0 s16720)) of
+ Some ((_, s16730)) =>
+ (case ((string_drop s16720 s16730)) of
+ s16740 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16740 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s16750)) =>
+ (let p00 = (string_drop s16740 s16750) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16700 :: " string "
+
+
+\<comment> \<open>\<open>val _s1652_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1652 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1652 s16540 = (
+ (case ((csr_mnemonic_matches_prefix s16540)) of
+ Some ((op1, s16550)) =>
+ (case ((string_drop s16540 s16550)) of
+ s16560 =>
+ (case ((spc_matches_prefix0 s16560)) of
+ Some ((_, s16570)) =>
+ (case ((string_drop s16560 s16570)) of
+ s16580 =>
+ (case ((reg_name_matches_prefix s16580 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16590)) =>
+ (case ((string_drop s16580 s16590)) of
+ s16600 =>
+ (case ((sep_matches_prefix s16600)) of
+ Some ((_, s16610)) =>
+ (case ((string_drop s16600 s16610)) of
+ s16620 =>
+ (case ((reg_name_matches_prefix s16620 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16630)) =>
+ (case ((string_drop s16620 s16630)) of
+ s16640 =>
+ (case ((sep_matches_prefix s16640)) of
+ Some ((_, s16650)) =>
+ (case ((string_drop s16640 s16650)) of
+ s16660 =>
+ (case ((csr_name_map_matches_prefix s16660
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s16670)) =>
+ (let p00 = (string_drop s16660 s16670) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s16540 :: " string "
+
+
+\<comment> \<open>\<open>val _s1634_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1634 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1634 s16360 = (
+ (case ((csr_mnemonic_matches_prefix s16360)) of
+ Some ((op1, s16370)) =>
+ (let s16380 = (string_drop s16360 s16370) in
+ if ((string_startswith s16380 (''i''))) then
+ (case ((string_drop s16380 ((string_length (''i''))))) of
+ s16390 =>
+ (case ((spc_matches_prefix0 s16390)) of
+ Some ((_, s16400)) =>
+ (case ((string_drop s16390 s16400)) of
+ s16410 =>
+ (case ((reg_name_matches_prefix s16410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16420)) =>
+ (case ((string_drop s16410 s16420)) of
+ s16430 =>
+ (case ((sep_matches_prefix s16430)) of
+ Some ((_, s16440)) =>
+ (case ((string_drop s16430 s16440)) of
+ s16450 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16460)) =>
+ (case ((string_drop s16450 s16460)) of
+ s16470 =>
+ (case ((sep_matches_prefix s16470)) of
+ Some ((_, s16480)) =>
+ (case ((string_drop s16470 s16480)) of
+ s16490 =>
+ (case ((csr_name_map_matches_prefix s16490
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s16500)) =>
+ (let p00 = (string_drop s16490 s16500) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s16360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1615_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1615 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1615 s16160 = (
+ (let s16170 = s16160 in
+ if ((string_startswith s16170 (''rem''))) then
+ (case ((string_drop s16170 ((string_length (''rem''))))) of
+ s16180 =>
+ (case ((maybe_not_u_matches_prefix s16180)) of
+ Some ((s, s16190)) =>
+ (let s16200 = (string_drop s16180 s16190) in
+ if ((string_startswith s16200 (''w''))) then
+ (case ((string_drop s16200 ((string_length (''w''))))) of
+ s16210 =>
+ (case ((spc_matches_prefix0 s16210)) of
+ Some ((_, s16220)) =>
+ (case ((string_drop s16210 s16220)) of
+ s16230 =>
+ (case ((reg_name_matches_prefix s16230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16240)) =>
+ (case ((string_drop s16230 s16240)) of
+ s16250 =>
+ (case ((sep_matches_prefix s16250)) of
+ Some ((_, s16260)) =>
+ (case ((string_drop s16250 s16260)) of
+ s16270 =>
+ (case ((reg_name_matches_prefix s16270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16280)) =>
+ (case ((string_drop s16270 s16280)) of
+ s16290 =>
+ (case ((sep_matches_prefix s16290)) of
+ Some ((_, s16300)) =>
+ (case ((string_drop s16290 s16300)) of
+ s16310 =>
+ (case ((reg_name_matches_prefix s16310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s16320)) =>
+ (let p00 = (string_drop s16310 s16320) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s16160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1596_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1596 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1596 s15970 = (
+ (let s15980 = s15970 in
+ if ((string_startswith s15980 (''div''))) then
+ (case ((string_drop s15980 ((string_length (''div''))))) of
+ s15990 =>
+ (case ((maybe_not_u_matches_prefix s15990)) of
+ Some ((s, s16000)) =>
+ (let s16010 = (string_drop s15990 s16000) in
+ if ((string_startswith s16010 (''w''))) then
+ (case ((string_drop s16010 ((string_length (''w''))))) of
+ s16020 =>
+ (case ((spc_matches_prefix0 s16020)) of
+ Some ((_, s16030)) =>
+ (case ((string_drop s16020 s16030)) of
+ s16040 =>
+ (case ((reg_name_matches_prefix s16040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16050)) =>
+ (case ((string_drop s16040 s16050)) of
+ s16060 =>
+ (case ((sep_matches_prefix s16060)) of
+ Some ((_, s16070)) =>
+ (case ((string_drop s16060 s16070)) of
+ s16080 =>
+ (case ((reg_name_matches_prefix s16080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16090)) =>
+ (case ((string_drop s16080 s16090)) of
+ s16100 =>
+ (case ((sep_matches_prefix s16100)) of
+ Some ((_, s16110)) =>
+ (case ((string_drop s16100 s16110)) of
+ s16120 =>
+ (case ((reg_name_matches_prefix s16120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s16130)) =>
+ (let p00 = (string_drop s16120 s16130) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s15970 :: " string "
+
+
+\<comment> \<open>\<open>val _s1580_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1580 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1580 s15810 = (
+ (let s15820 = s15810 in
+ if ((string_startswith s15820 (''mulw''))) then
+ (case ((string_drop s15820 ((string_length (''mulw''))))) of
+ s15830 =>
+ (case ((spc_matches_prefix0 s15830)) of
+ Some ((_, s15840)) =>
+ (case ((string_drop s15830 s15840)) of
+ s15850 =>
+ (case ((reg_name_matches_prefix s15850 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15860)) =>
+ (case ((string_drop s15850 s15860)) of
+ s15870 =>
+ (case ((sep_matches_prefix s15870)) of
+ Some ((_, s15880)) =>
+ (case ((string_drop s15870 s15880)) of
+ s15890 =>
+ (case ((reg_name_matches_prefix s15890 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15900)) =>
+ (case ((string_drop s15890 s15900)) of
+ s15910 =>
+ (case ((sep_matches_prefix s15910)) of
+ Some ((_, s15920)) =>
+ (case ((string_drop s15910 s15920)) of
+ s15930 =>
+ (case ((reg_name_matches_prefix s15930 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15940)) =>
+ (let p00 = (string_drop s15930 s15940) in
+ if (((p00 = ('''')))) then Some (rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15810 :: " string "
+
+
+\<comment> \<open>\<open>val _s1562_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1562 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1562 s15630 = (
+ (let s15640 = s15630 in
+ if ((string_startswith s15640 (''rem''))) then
+ (case ((string_drop s15640 ((string_length (''rem''))))) of
+ s15650 =>
+ (case ((maybe_not_u_matches_prefix s15650)) of
+ Some ((s, s15660)) =>
+ (case ((string_drop s15650 s15660)) of
+ s15670 =>
+ (case ((spc_matches_prefix0 s15670)) of
+ Some ((_, s15680)) =>
+ (case ((string_drop s15670 s15680)) of
+ s15690 =>
+ (case ((reg_name_matches_prefix s15690 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15700)) =>
+ (case ((string_drop s15690 s15700)) of
+ s15710 =>
+ (case ((sep_matches_prefix s15710)) of
+ Some ((_, s15720)) =>
+ (case ((string_drop s15710 s15720)) of
+ s15730 =>
+ (case ((reg_name_matches_prefix s15730 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15740)) =>
+ (case ((string_drop s15730 s15740)) of
+ s15750 =>
+ (case ((sep_matches_prefix s15750)) of
+ Some ((_, s15760)) =>
+ (case ((string_drop s15750 s15760)) of
+ s15770 =>
+ (case ((reg_name_matches_prefix s15770 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15780)) =>
+ (let p00 = (string_drop s15770 s15780) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15630 :: " string "
+
+
+\<comment> \<open>\<open>val _s1544_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1544 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1544 s15450 = (
+ (let s15460 = s15450 in
+ if ((string_startswith s15460 (''div''))) then
+ (case ((string_drop s15460 ((string_length (''div''))))) of
+ s15470 =>
+ (case ((maybe_not_u_matches_prefix s15470)) of
+ Some ((s, s15480)) =>
+ (case ((string_drop s15470 s15480)) of
+ s15490 =>
+ (case ((spc_matches_prefix0 s15490)) of
+ Some ((_, s15500)) =>
+ (case ((string_drop s15490 s15500)) of
+ s15510 =>
+ (case ((reg_name_matches_prefix s15510 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15520)) =>
+ (case ((string_drop s15510 s15520)) of
+ s15530 =>
+ (case ((sep_matches_prefix s15530)) of
+ Some ((_, s15540)) =>
+ (case ((string_drop s15530 s15540)) of
+ s15550 =>
+ (case ((reg_name_matches_prefix s15550 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15560)) =>
+ (case ((string_drop s15550 s15560)) of
+ s15570 =>
+ (case ((sep_matches_prefix s15570)) of
+ Some ((_, s15580)) =>
+ (case ((string_drop s15570 s15580)) of
+ s15590 =>
+ (case ((reg_name_matches_prefix s15590 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15600)) =>
+ (let p00 = (string_drop s15590 s15600) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15450 :: " string "
+
+
+\<comment> \<open>\<open>val _s1527_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1527 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1527 s15290 = (
+ (case ((mul_mnemonic_matches_prefix s15290)) of
+ Some (((high, signed1, signed2), s15300)) =>
+ (case ((string_drop s15290 s15300)) of
+ s15310 =>
+ (case ((spc_matches_prefix0 s15310)) of
+ Some ((_, s15320)) =>
+ (case ((string_drop s15310 s15320)) of
+ s15330 =>
+ (case ((reg_name_matches_prefix s15330 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15340)) =>
+ (case ((string_drop s15330 s15340)) of
+ s15350 =>
+ (case ((sep_matches_prefix s15350)) of
+ Some ((_, s15360)) =>
+ (case ((string_drop s15350 s15360)) of
+ s15370 =>
+ (case ((reg_name_matches_prefix s15370 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15380)) =>
+ (case ((string_drop s15370 s15380)) of
+ s15390 =>
+ (case ((sep_matches_prefix s15390)) of
+ Some ((_, s15400)) =>
+ (case ((string_drop s15390 s15400)) of
+ s15410 =>
+ (case ((reg_name_matches_prefix s15410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15420)) =>
+ (let p00 = (string_drop s15410 s15420) in
+ if (((p00 = ('''')))) then Some (high, signed1, signed2, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s15290 :: " string "
+
+
+\<comment> \<open>\<open>val _s1515_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1515 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1515 s15160 = (
+ (let s15170 = s15160 in
+ if ((string_startswith s15170 (''c.add''))) then
+ (case ((string_drop s15170 ((string_length (''c.add''))))) of
+ s15180 =>
+ (case ((spc_matches_prefix0 s15180)) of
+ Some ((_, s15190)) =>
+ (case ((string_drop s15180 s15190)) of
+ s15200 =>
+ (case ((reg_name_matches_prefix s15200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s15210)) =>
+ (case ((string_drop s15200 s15210)) of
+ s15220 =>
+ (case ((sep_matches_prefix s15220)) of
+ Some ((_, s15230)) =>
+ (case ((string_drop s15220 s15230)) of
+ s15240 =>
+ (case ((reg_name_matches_prefix s15240 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15250)) =>
+ (let p00 = (string_drop s15240 s15250) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1503_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1503 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1503 s15040 = (
+ (let s15050 = s15040 in
+ if ((string_startswith s15050 (''c.mv''))) then
+ (case ((string_drop s15050 ((string_length (''c.mv''))))) of
+ s15060 =>
+ (case ((spc_matches_prefix0 s15060)) of
+ Some ((_, s15070)) =>
+ (case ((string_drop s15060 s15070)) of
+ s15080 =>
+ (case ((reg_name_matches_prefix s15080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15090)) =>
+ (case ((string_drop s15080 s15090)) of
+ s15100 =>
+ (case ((sep_matches_prefix s15100)) of
+ Some ((_, s15110)) =>
+ (case ((string_drop s15100 s15110)) of
+ s15120 =>
+ (case ((reg_name_matches_prefix s15120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15130)) =>
+ (let p00 = (string_drop s15120 s15130) in
+ if (((p00 = ('''')))) then Some (rd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1495_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s1495 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s1495 s14960 = (
+ (let s14970 = s14960 in
+ if ((string_startswith s14970 (''c.jalr''))) then
+ (case ((string_drop s14970 ((string_length (''c.jalr''))))) of
+ s14980 =>
+ (case ((spc_matches_prefix0 s14980)) of
+ Some ((_, s14990)) =>
+ (case ((string_drop s14980 s14990)) of
+ s15000 =>
+ (case ((reg_name_matches_prefix s15000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15010)) =>
+ (let p00 = (string_drop s15000 s15010) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14960 :: " string "
+
+
+\<comment> \<open>\<open>val _s1487_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s1487 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s1487 s14880 = (
+ (let s14890 = s14880 in
+ if ((string_startswith s14890 (''c.jr''))) then
+ (case ((string_drop s14890 ((string_length (''c.jr''))))) of
+ s14900 =>
+ (case ((spc_matches_prefix0 s14900)) of
+ Some ((_, s14910)) =>
+ (case ((string_drop s14900 s14910)) of
+ s14920 =>
+ (case ((reg_name_matches_prefix s14920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s14930)) =>
+ (let p00 = (string_drop s14920 s14930) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14880 :: " string "
+
+
+\<comment> \<open>\<open>val _s1475_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1475 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1475 s14760 = (
+ (let s14770 = s14760 in
+ if ((string_startswith s14770 (''c.sdsp''))) then
+ (case ((string_drop s14770 ((string_length (''c.sdsp''))))) of
+ s14780 =>
+ (case ((spc_matches_prefix0 s14780)) of
+ Some ((_, s14790)) =>
+ (case ((string_drop s14780 s14790)) of
+ s14800 =>
+ (case ((reg_name_matches_prefix s14800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s14810)) =>
+ (case ((string_drop s14800 s14810)) of
+ s14820 =>
+ (case ((sep_matches_prefix s14820)) of
+ Some ((_, s14830)) =>
+ (case ((string_drop s14820 s14830)) of
+ s14840 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14840 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14850)) =>
+ (let p00 = (string_drop s14840 s14850) in
+ if (((p00 = ('''')))) then Some (rs2, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1463_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1463 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1463 s14640 = (
+ (let s14650 = s14640 in
+ if ((string_startswith s14650 (''c.swsp''))) then
+ (case ((string_drop s14650 ((string_length (''c.swsp''))))) of
+ s14660 =>
+ (case ((spc_matches_prefix0 s14660)) of
+ Some ((_, s14670)) =>
+ (case ((string_drop s14660 s14670)) of
+ s14680 =>
+ (case ((reg_name_matches_prefix s14680 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14690)) =>
+ (case ((string_drop s14680 s14690)) of
+ s14700 =>
+ (case ((sep_matches_prefix s14700)) of
+ Some ((_, s14710)) =>
+ (case ((string_drop s14700 s14710)) of
+ s14720 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14720 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14730)) =>
+ (let p00 = (string_drop s14720 s14730) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14640 :: " string "
+
+
+\<comment> \<open>\<open>val _s1451_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1451 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1451 s14520 = (
+ (let s14530 = s14520 in
+ if ((string_startswith s14530 (''c.ldsp''))) then
+ (case ((string_drop s14530 ((string_length (''c.ldsp''))))) of
+ s14540 =>
+ (case ((spc_matches_prefix0 s14540)) of
+ Some ((_, s14550)) =>
+ (case ((string_drop s14540 s14550)) of
+ s14560 =>
+ (case ((reg_name_matches_prefix s14560 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14570)) =>
+ (case ((string_drop s14560 s14570)) of
+ s14580 =>
+ (case ((sep_matches_prefix s14580)) of
+ Some ((_, s14590)) =>
+ (case ((string_drop s14580 s14590)) of
+ s14600 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14600 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14610)) =>
+ (let p00 = (string_drop s14600 s14610) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14520 :: " string "
+
+
+\<comment> \<open>\<open>val _s1439_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1439 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1439 s14400 = (
+ (let s14410 = s14400 in
+ if ((string_startswith s14410 (''c.lwsp''))) then
+ (case ((string_drop s14410 ((string_length (''c.lwsp''))))) of
+ s14420 =>
+ (case ((spc_matches_prefix0 s14420)) of
+ Some ((_, s14430)) =>
+ (case ((string_drop s14420 s14430)) of
+ s14440 =>
+ (case ((reg_name_matches_prefix s14440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14450)) =>
+ (case ((string_drop s14440 s14450)) of
+ s14460 =>
+ (case ((sep_matches_prefix s14460)) of
+ Some ((_, s14470)) =>
+ (case ((string_drop s14460 s14470)) of
+ s14480 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14480 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14490)) =>
+ (let p00 = (string_drop s14480 s14490) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14400 :: " string "
+
+
+\<comment> \<open>\<open>val _s1427_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1427 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1427 s14280 = (
+ (let s14290 = s14280 in
+ if ((string_startswith s14290 (''c.slli''))) then
+ (case ((string_drop s14290 ((string_length (''c.slli''))))) of
+ s14300 =>
+ (case ((spc_matches_prefix0 s14300)) of
+ Some ((_, s14310)) =>
+ (case ((string_drop s14300 s14310)) of
+ s14320 =>
+ (case ((reg_name_matches_prefix s14320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s14330)) =>
+ (case ((string_drop s14320 s14330)) of
+ s14340 =>
+ (case ((sep_matches_prefix s14340)) of
+ Some ((_, s14350)) =>
+ (case ((string_drop s14340 s14350)) of
+ s14360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14360 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s14370)) =>
+ (let p00 = (string_drop s14360 s14370) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14280 :: " string "
+
+
+\<comment> \<open>\<open>val _s1415_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1415 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1415 s14160 = (
+ (let s14170 = s14160 in
+ if ((string_startswith s14170 (''c.bnez''))) then
+ (case ((string_drop s14170 ((string_length (''c.bnez''))))) of
+ s14180 =>
+ (case ((spc_matches_prefix0 s14180)) of
+ Some ((_, s14190)) =>
+ (case ((string_drop s14180 s14190)) of
+ s14200 =>
+ (case ((creg_name_matches_prefix s14200 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s14210)) =>
+ (case ((string_drop s14200 s14210)) of
+ s14220 =>
+ (case ((sep_matches_prefix s14220)) of
+ Some ((_, s14230)) =>
+ (case ((string_drop s14220 s14230)) of
+ s14240 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14240 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s14250)) =>
+ (let p00 = (string_drop s14240 s14250) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1403_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1403 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1403 s14040 = (
+ (let s14050 = s14040 in
+ if ((string_startswith s14050 (''c.beqz''))) then
+ (case ((string_drop s14050 ((string_length (''c.beqz''))))) of
+ s14060 =>
+ (case ((spc_matches_prefix0 s14060)) of
+ Some ((_, s14070)) =>
+ (case ((string_drop s14060 s14070)) of
+ s14080 =>
+ (case ((creg_name_matches_prefix s14080 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s14090)) =>
+ (case ((string_drop s14080 s14090)) of
+ s14100 =>
+ (case ((sep_matches_prefix s14100)) of
+ Some ((_, s14110)) =>
+ (case ((string_drop s14100 s14110)) of
+ s14120 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14120 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s14130)) =>
+ (let p00 = (string_drop s14120 s14130) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1395_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s1395 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s1395 s13960 = (
+ (let s13970 = s13960 in
+ if ((string_startswith s13970 (''c.j''))) then
+ (case ((string_drop s13970 ((string_length (''c.j''))))) of
+ s13980 =>
+ (case ((spc_matches_prefix0 s13980)) of
+ Some ((_, s13990)) =>
+ (case ((string_drop s13980 s13990)) of
+ s14000 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14000 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s14010)) =>
+ (let p00 = (string_drop s14000 s14010) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13960 :: " string "
+
+
+\<comment> \<open>\<open>val _s1383_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1383 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1383 s13840 = (
+ (let s13850 = s13840 in
+ if ((string_startswith s13850 (''c.addw''))) then
+ (case ((string_drop s13850 ((string_length (''c.addw''))))) of
+ s13860 =>
+ (case ((spc_matches_prefix0 s13860)) of
+ Some ((_, s13870)) =>
+ (case ((string_drop s13860 s13870)) of
+ s13880 =>
+ (case ((creg_name_matches_prefix s13880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13890)) =>
+ (case ((string_drop s13880 s13890)) of
+ s13900 =>
+ (case ((sep_matches_prefix s13900)) of
+ Some ((_, s13910)) =>
+ (case ((string_drop s13900 s13910)) of
+ s13920 =>
+ (case ((creg_name_matches_prefix s13920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13930)) =>
+ (let p00 = (string_drop s13920 s13930) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13840 :: " string "
+
+
+\<comment> \<open>\<open>val _s1371_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1371 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1371 s13720 = (
+ (let s13730 = s13720 in
+ if ((string_startswith s13730 (''c.subw''))) then
+ (case ((string_drop s13730 ((string_length (''c.subw''))))) of
+ s13740 =>
+ (case ((spc_matches_prefix0 s13740)) of
+ Some ((_, s13750)) =>
+ (case ((string_drop s13740 s13750)) of
+ s13760 =>
+ (case ((creg_name_matches_prefix s13760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13770)) =>
+ (case ((string_drop s13760 s13770)) of
+ s13780 =>
+ (case ((sep_matches_prefix s13780)) of
+ Some ((_, s13790)) =>
+ (case ((string_drop s13780 s13790)) of
+ s13800 =>
+ (case ((creg_name_matches_prefix s13800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13810)) =>
+ (let p00 = (string_drop s13800 s13810) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13720 :: " string "
+
+
+\<comment> \<open>\<open>val _s1359_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1359 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1359 s13600 = (
+ (let s13610 = s13600 in
+ if ((string_startswith s13610 (''c.and''))) then
+ (case ((string_drop s13610 ((string_length (''c.and''))))) of
+ s13620 =>
+ (case ((spc_matches_prefix0 s13620)) of
+ Some ((_, s13630)) =>
+ (case ((string_drop s13620 s13630)) of
+ s13640 =>
+ (case ((creg_name_matches_prefix s13640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13650)) =>
+ (case ((string_drop s13640 s13650)) of
+ s13660 =>
+ (case ((sep_matches_prefix s13660)) of
+ Some ((_, s13670)) =>
+ (case ((string_drop s13660 s13670)) of
+ s13680 =>
+ (case ((creg_name_matches_prefix s13680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13690)) =>
+ (let p00 = (string_drop s13680 s13690) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1347_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1347 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1347 s13480 = (
+ (let s13490 = s13480 in
+ if ((string_startswith s13490 (''c.or''))) then
+ (case ((string_drop s13490 ((string_length (''c.or''))))) of
+ s13500 =>
+ (case ((spc_matches_prefix0 s13500)) of
+ Some ((_, s13510)) =>
+ (case ((string_drop s13500 s13510)) of
+ s13520 =>
+ (case ((creg_name_matches_prefix s13520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13530)) =>
+ (case ((string_drop s13520 s13530)) of
+ s13540 =>
+ (case ((sep_matches_prefix s13540)) of
+ Some ((_, s13550)) =>
+ (case ((string_drop s13540 s13550)) of
+ s13560 =>
+ (case ((creg_name_matches_prefix s13560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13570)) =>
+ (let p00 = (string_drop s13560 s13570) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1335_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1335 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1335 s13360 = (
+ (let s13370 = s13360 in
+ if ((string_startswith s13370 (''c.xor''))) then
+ (case ((string_drop s13370 ((string_length (''c.xor''))))) of
+ s13380 =>
+ (case ((spc_matches_prefix0 s13380)) of
+ Some ((_, s13390)) =>
+ (case ((string_drop s13380 s13390)) of
+ s13400 =>
+ (case ((creg_name_matches_prefix s13400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13410)) =>
+ (case ((string_drop s13400 s13410)) of
+ s13420 =>
+ (case ((sep_matches_prefix s13420)) of
+ Some ((_, s13430)) =>
+ (case ((string_drop s13420 s13430)) of
+ s13440 =>
+ (case ((creg_name_matches_prefix s13440 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13450)) =>
+ (let p00 = (string_drop s13440 s13450) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1323_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1323 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1323 s13240 = (
+ (let s13250 = s13240 in
+ if ((string_startswith s13250 (''c.sub''))) then
+ (case ((string_drop s13250 ((string_length (''c.sub''))))) of
+ s13260 =>
+ (case ((spc_matches_prefix0 s13260)) of
+ Some ((_, s13270)) =>
+ (case ((string_drop s13260 s13270)) of
+ s13280 =>
+ (case ((creg_name_matches_prefix s13280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13290)) =>
+ (case ((string_drop s13280 s13290)) of
+ s13300 =>
+ (case ((sep_matches_prefix s13300)) of
+ Some ((_, s13310)) =>
+ (case ((string_drop s13300 s13310)) of
+ s13320 =>
+ (case ((creg_name_matches_prefix s13320 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13330)) =>
+ (let p00 = (string_drop s13320 s13330) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13240 :: " string "
+
+
+\<comment> \<open>\<open>val _s1311_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1311 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1311 s13120 = (
+ (let s13130 = s13120 in
+ if ((string_startswith s13130 (''c.andi''))) then
+ (case ((string_drop s13130 ((string_length (''c.andi''))))) of
+ s13140 =>
+ (case ((spc_matches_prefix0 s13140)) of
+ Some ((_, s13150)) =>
+ (case ((string_drop s13140 s13150)) of
+ s13160 =>
+ (case ((creg_name_matches_prefix s13160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13170)) =>
+ (case ((string_drop s13160 s13170)) of
+ s13180 =>
+ (case ((sep_matches_prefix s13180)) of
+ Some ((_, s13190)) =>
+ (case ((string_drop s13180 s13190)) of
+ s13200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s13200 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s13210)) =>
+ (let p00 = (string_drop s13200 s13210) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13120 :: " string "
+
+
+\<comment> \<open>\<open>val _s1299_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1299 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1299 s13000 = (
+ (let s13010 = s13000 in
+ if ((string_startswith s13010 (''c.srai''))) then
+ (case ((string_drop s13010 ((string_length (''c.srai''))))) of
+ s13020 =>
+ (case ((spc_matches_prefix0 s13020)) of
+ Some ((_, s13030)) =>
+ (case ((string_drop s13020 s13030)) of
+ s13040 =>
+ (case ((creg_name_matches_prefix s13040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13050)) =>
+ (case ((string_drop s13040 s13050)) of
+ s13060 =>
+ (case ((sep_matches_prefix s13060)) of
+ Some ((_, s13070)) =>
+ (case ((string_drop s13060 s13070)) of
+ s13080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s13080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s13090)) =>
+ (let p00 = (string_drop s13080 s13090) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13000 :: " string "
+
+
+\<comment> \<open>\<open>val _s1287_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1287 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1287 s12880 = (
+ (let s12890 = s12880 in
+ if ((string_startswith s12890 (''c.srli''))) then
+ (case ((string_drop s12890 ((string_length (''c.srli''))))) of
+ s12900 =>
+ (case ((spc_matches_prefix0 s12900)) of
+ Some ((_, s12910)) =>
+ (case ((string_drop s12900 s12910)) of
+ s12920 =>
+ (case ((creg_name_matches_prefix s12920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s12930)) =>
+ (case ((string_drop s12920 s12930)) of
+ s12940 =>
+ (case ((sep_matches_prefix s12940)) of
+ Some ((_, s12950)) =>
+ (case ((string_drop s12940 s12950)) of
+ s12960 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12960 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s12970)) =>
+ (let p00 = (string_drop s12960 s12970) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12880 :: " string "
+
+
+\<comment> \<open>\<open>val _s1275_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1275 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1275 s12760 = (
+ (let s12770 = s12760 in
+ if ((string_startswith s12770 (''c.lui''))) then
+ (case ((string_drop s12770 ((string_length (''c.lui''))))) of
+ s12780 =>
+ (case ((spc_matches_prefix0 s12780)) of
+ Some ((_, s12790)) =>
+ (case ((string_drop s12780 s12790)) of
+ s12800 =>
+ (case ((reg_name_matches_prefix s12800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s12810)) =>
+ (case ((string_drop s12800 s12810)) of
+ s12820 =>
+ (case ((sep_matches_prefix s12820)) of
+ Some ((_, s12830)) =>
+ (case ((string_drop s12820 s12830)) of
+ s12840 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12840 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12850)) =>
+ (let p00 = (string_drop s12840 s12850) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1267_ : string -> maybe (mword ty6)\<close>\<close>
+
+definition s1267 :: " string \<Rightarrow>((6)Word.word)option " where
+ " s1267 s12680 = (
+ (let s12690 = s12680 in
+ if ((string_startswith s12690 (''c.addi16sp''))) then
+ (case ((string_drop s12690 ((string_length (''c.addi16sp''))))) of
+ s12700 =>
+ (case ((spc_matches_prefix0 s12700)) of
+ Some ((_, s12710)) =>
+ (case ((string_drop s12700 s12710)) of
+ s12720 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12720 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12730)) =>
+ (let p00 = (string_drop s12720 s12730) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12680 :: " string "
+
+
+\<comment> \<open>\<open>val _s1255_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1255 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1255 s12560 = (
+ (let s12570 = s12560 in
+ if ((string_startswith s12570 (''c.li''))) then
+ (case ((string_drop s12570 ((string_length (''c.li''))))) of
+ s12580 =>
+ (case ((spc_matches_prefix0 s12580)) of
+ Some ((_, s12590)) =>
+ (case ((string_drop s12580 s12590)) of
+ s12600 =>
+ (case ((reg_name_matches_prefix s12600 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s12610)) =>
+ (case ((string_drop s12600 s12610)) of
+ s12620 =>
+ (case ((sep_matches_prefix s12620)) of
+ Some ((_, s12630)) =>
+ (case ((string_drop s12620 s12630)) of
+ s12640 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12640 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12650)) =>
+ (let p00 = (string_drop s12640 s12650) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12560 :: " string "
+
+
+\<comment> \<open>\<open>val _s1243_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1243 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1243 s12440 = (
+ (let s12450 = s12440 in
+ if ((string_startswith s12450 (''c.addiw''))) then
+ (case ((string_drop s12450 ((string_length (''c.addiw''))))) of
+ s12460 =>
+ (case ((spc_matches_prefix0 s12460)) of
+ Some ((_, s12470)) =>
+ (case ((string_drop s12460 s12470)) of
+ s12480 =>
+ (case ((reg_name_matches_prefix s12480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s12490)) =>
+ (case ((string_drop s12480 s12490)) of
+ s12500 =>
+ (case ((sep_matches_prefix s12500)) of
+ Some ((_, s12510)) =>
+ (case ((string_drop s12500 s12510)) of
+ s12520 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12520 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12530)) =>
+ (let p00 = (string_drop s12520 s12530) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12440 :: " string "
+
+
+\<comment> \<open>\<open>val _s1235_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s1235 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s1235 s12360 = (
+ (let s12370 = s12360 in
+ if ((string_startswith s12370 (''c.jal''))) then
+ (case ((string_drop s12370 ((string_length (''c.jal''))))) of
+ s12380 =>
+ (case ((spc_matches_prefix0 s12380)) of
+ Some ((_, s12390)) =>
+ (case ((string_drop s12380 s12390)) of
+ s12400 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12400 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__802, s12410)) =>
+ if (((((subrange_vec_dec v__802 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__802
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__802
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let p00 = (string_drop s12400 s12410) in
+ if (((p00 = ('''')))) then Some imm else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1223_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1223 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1223 s12240 = (
+ (let s12250 = s12240 in
+ if ((string_startswith s12250 (''c.addi''))) then
+ (case ((string_drop s12250 ((string_length (''c.addi''))))) of
+ s12260 =>
+ (case ((spc_matches_prefix0 s12260)) of
+ Some ((_, s12270)) =>
+ (case ((string_drop s12260 s12270)) of
+ s12280 =>
+ (case ((reg_name_matches_prefix s12280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s12290)) =>
+ (case ((string_drop s12280 s12290)) of
+ s12300 =>
+ (case ((sep_matches_prefix s12300)) of
+ Some ((_, s12310)) =>
+ (case ((string_drop s12300 s12310)) of
+ s12320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12320 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s12330)) =>
+ (let p00 = (string_drop s12320 s12330) in
+ if (((p00 = ('''')))) then Some (rsd, nzi) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12240 :: " string "
+
+
+\<comment> \<open>\<open>val _s1207_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1207 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1207 s12080 = (
+ (let s12090 = s12080 in
+ if ((string_startswith s12090 (''c.sd''))) then
+ (case ((string_drop s12090 ((string_length (''c.sd''))))) of
+ s12100 =>
+ (case ((spc_matches_prefix0 s12100)) of
+ Some ((_, s12110)) =>
+ (case ((string_drop s12100 s12110)) of
+ s12120 =>
+ (case ((creg_name_matches_prefix s12120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s12130)) =>
+ (case ((string_drop s12120 s12130)) of
+ s12140 =>
+ (case ((sep_matches_prefix s12140)) of
+ Some ((_, s12150)) =>
+ (case ((string_drop s12140 s12150)) of
+ s12160 =>
+ (case ((creg_name_matches_prefix s12160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s12170)) =>
+ (case ((string_drop s12160 s12170)) of
+ s12180 =>
+ (case ((sep_matches_prefix s12180)) of
+ Some ((_, s12190)) =>
+ (case ((string_drop s12180 s12190)) of
+ s12200 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12200 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__804, s12210)) =>
+ if (((((subrange_vec_dec v__804 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__804 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__804 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s12200 s12210) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12080 :: " string "
+
+
+\<comment> \<open>\<open>val _s1191_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1191 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1191 s11920 = (
+ (let s11930 = s11920 in
+ if ((string_startswith s11930 (''c.sw''))) then
+ (case ((string_drop s11930 ((string_length (''c.sw''))))) of
+ s11940 =>
+ (case ((spc_matches_prefix0 s11940)) of
+ Some ((_, s11950)) =>
+ (case ((string_drop s11940 s11950)) of
+ s11960 =>
+ (case ((creg_name_matches_prefix s11960 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s11970)) =>
+ (case ((string_drop s11960 s11970)) of
+ s11980 =>
+ (case ((sep_matches_prefix s11980)) of
+ Some ((_, s11990)) =>
+ (case ((string_drop s11980 s11990)) of
+ s12000 =>
+ (case ((creg_name_matches_prefix s12000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s12010)) =>
+ (case ((string_drop s12000 s12010)) of
+ s12020 =>
+ (case ((sep_matches_prefix s12020)) of
+ Some ((_, s12030)) =>
+ (case ((string_drop s12020 s12030)) of
+ s12040 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12040 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__806, s12050)) =>
+ if (((((subrange_vec_dec v__806 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__806 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__806 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s12040 s12050) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11920 :: " string "
+
+
+\<comment> \<open>\<open>val _s1175_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1175 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1175 s11760 = (
+ (let s11770 = s11760 in
+ if ((string_startswith s11770 (''c.ld''))) then
+ (case ((string_drop s11770 ((string_length (''c.ld''))))) of
+ s11780 =>
+ (case ((spc_matches_prefix0 s11780)) of
+ Some ((_, s11790)) =>
+ (case ((string_drop s11780 s11790)) of
+ s11800 =>
+ (case ((creg_name_matches_prefix s11800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11810)) =>
+ (case ((string_drop s11800 s11810)) of
+ s11820 =>
+ (case ((sep_matches_prefix s11820)) of
+ Some ((_, s11830)) =>
+ (case ((string_drop s11820 s11830)) of
+ s11840 =>
+ (case ((creg_name_matches_prefix s11840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s11850)) =>
+ (case ((string_drop s11840 s11850)) of
+ s11860 =>
+ (case ((sep_matches_prefix s11860)) of
+ Some ((_, s11870)) =>
+ (case ((string_drop s11860 s11870)) of
+ s11880 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11880 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__808, s11890)) =>
+ if (((((subrange_vec_dec v__808 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__808 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__808 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s11880 s11890) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1159_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1159 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1159 s11600 = (
+ (let s11610 = s11600 in
+ if ((string_startswith s11610 (''c.lw''))) then
+ (case ((string_drop s11610 ((string_length (''c.lw''))))) of
+ s11620 =>
+ (case ((spc_matches_prefix0 s11620)) of
+ Some ((_, s11630)) =>
+ (case ((string_drop s11620 s11630)) of
+ s11640 =>
+ (case ((creg_name_matches_prefix s11640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11650)) =>
+ (case ((string_drop s11640 s11650)) of
+ s11660 =>
+ (case ((sep_matches_prefix s11660)) of
+ Some ((_, s11670)) =>
+ (case ((string_drop s11660 s11670)) of
+ s11680 =>
+ (case ((creg_name_matches_prefix s11680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s11690)) =>
+ (case ((string_drop s11680 s11690)) of
+ s11700 =>
+ (case ((sep_matches_prefix s11700)) of
+ Some ((_, s11710)) =>
+ (case ((string_drop s11700 s11710)) of
+ s11720 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11720 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__810, s11730)) =>
+ if (((((subrange_vec_dec v__810 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__810 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__810 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s11720 s11730) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1147_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1147 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1147 s11480 = (
+ (let s11490 = s11480 in
+ if ((string_startswith s11490 (''c.addi4spn''))) then
+ (case ((string_drop s11490 ((string_length (''c.addi4spn''))))) of
+ s11500 =>
+ (case ((spc_matches_prefix0 s11500)) of
+ Some ((_, s11510)) =>
+ (case ((string_drop s11500 s11510)) of
+ s11520 =>
+ (case ((creg_name_matches_prefix s11520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11530)) =>
+ (case ((string_drop s11520 s11530)) of
+ s11540 =>
+ (case ((sep_matches_prefix s11540)) of
+ Some ((_, s11550)) =>
+ (case ((string_drop s11540 s11550)) of
+ s11560 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11560 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__812, s11570)) =>
+ if (((((subrange_vec_dec v__812 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__812 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__812 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let p00 = (string_drop s11560 s11570) in
+ if (((p00 = ('''')))) then Some (rdc, nzimm) else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1123_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1123 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1123 s11250 = (
+ (case ((amo_mnemonic_matches_prefix s11250)) of
+ Some ((op1, s11260)) =>
+ (let s11270 = (string_drop s11250 s11260) in
+ if ((string_startswith s11270 (''.''))) then
+ (case ((string_drop s11270 ((string_length (''.''))))) of
+ s11280 =>
+ (case ((size_mnemonic_matches_prefix s11280)) of
+ Some ((width, s11290)) =>
+ (case ((string_drop s11280 s11290)) of
+ s11300 =>
+ (case ((maybe_aq_matches_prefix s11300)) of
+ Some ((aq, s11310)) =>
+ (case ((string_drop s11300 s11310)) of
+ s11320 =>
+ (case ((maybe_rl_matches_prefix s11320)) of
+ Some ((rl, s11330)) =>
+ (case ((string_drop s11320 s11330)) of
+ s11340 =>
+ (case ((spc_matches_prefix0 s11340)) of
+ Some ((_, s11350)) =>
+ (case ((string_drop s11340 s11350)) of
+ s11360 =>
+ (case ((reg_name_matches_prefix s11360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s11370)) =>
+ (case ((string_drop s11360 s11370)) of
+ s11380 =>
+ (case ((sep_matches_prefix s11380)) of
+ Some ((_, s11390)) =>
+ (case ((string_drop s11380 s11390)) of
+ s11400 =>
+ (case ((reg_name_matches_prefix s11400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s11410)) =>
+ (case ((string_drop s11400 s11410)) of
+ s11420 =>
+ (case ((sep_matches_prefix s11420)) of
+ Some ((_, s11430)) =>
+ (case ((string_drop s11420 s11430)) of
+ s11440 =>
+ (case ((reg_name_matches_prefix s11440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s11450)) =>
+ (let p00 = (string_drop s11440 s11450) in
+ if (((p00 = ('''')))) then Some (op1, width, aq, rl, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s11250 :: " string "
+
+
+\<comment> \<open>\<open>val _s1101_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1101 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1101 s11020 = (
+ (let s11030 = s11020 in
+ if ((string_startswith s11030 (''sc.''))) then
+ (case ((string_drop s11030 ((string_length (''sc.''))))) of
+ s11040 =>
+ (case ((size_mnemonic_matches_prefix s11040)) of
+ Some ((size1, s11050)) =>
+ (case ((string_drop s11040 s11050)) of
+ s11060 =>
+ (case ((maybe_aq_matches_prefix s11060)) of
+ Some ((aq, s11070)) =>
+ (case ((string_drop s11060 s11070)) of
+ s11080 =>
+ (case ((maybe_rl_matches_prefix s11080)) of
+ Some ((rl, s11090)) =>
+ (case ((string_drop s11080 s11090)) of
+ s11100 =>
+ (case ((spc_matches_prefix0 s11100)) of
+ Some ((_, s11110)) =>
+ (case ((string_drop s11100 s11110)) of
+ s11120 =>
+ (case ((reg_name_matches_prefix s11120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s11130)) =>
+ (case ((string_drop s11120 s11130)) of
+ s11140 =>
+ (case ((sep_matches_prefix s11140)) of
+ Some ((_, s11150)) =>
+ (case ((string_drop s11140 s11150)) of
+ s11160 =>
+ (case ((reg_name_matches_prefix s11160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s11170)) =>
+ (case ((string_drop s11160 s11170)) of
+ s11180 =>
+ (case ((sep_matches_prefix s11180)) of
+ Some ((_, s11190)) =>
+ (case ((string_drop s11180 s11190)) of
+ s11200 =>
+ (case ((reg_name_matches_prefix s11200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s11210)) =>
+ (let p00 = (string_drop s11200 s11210) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11020 :: " string "
+
+
+\<comment> \<open>\<open>val _s1083_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1083 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word)option " where
+ " s1083 s10840 = (
+ (let s10850 = s10840 in
+ if ((string_startswith s10850 (''lr.''))) then
+ (case ((string_drop s10850 ((string_length (''lr.''))))) of
+ s10860 =>
+ (case ((size_mnemonic_matches_prefix s10860)) of
+ Some ((size1, s10870)) =>
+ (case ((string_drop s10860 s10870)) of
+ s10880 =>
+ (case ((maybe_aq_matches_prefix s10880)) of
+ Some ((aq, s10890)) =>
+ (case ((string_drop s10880 s10890)) of
+ s10900 =>
+ (case ((maybe_rl_matches_prefix s10900)) of
+ Some ((rl, s10910)) =>
+ (case ((string_drop s10900 s10910)) of
+ s10920 =>
+ (case ((spc_matches_prefix0 s10920)) of
+ Some ((_, s10930)) =>
+ (case ((string_drop s10920 s10930)) of
+ s10940 =>
+ (case ((reg_name_matches_prefix s10940 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10950)) =>
+ (case ((string_drop s10940 s10950)) of
+ s10960 =>
+ (case ((sep_matches_prefix s10960)) of
+ Some ((_, s10970)) =>
+ (case ((string_drop s10960 s10970)) of
+ s10980 =>
+ (case ((reg_name_matches_prefix s10980 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10990)) =>
+ (let p00 = (string_drop s10980 s10990) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10840 :: " string "
+
+
+\<comment> \<open>\<open>val _s1071_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1071 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1071 s10720 = (
+ (let s10730 = s10720 in
+ if ((string_startswith s10730 (''sfence.vma''))) then
+ (case ((string_drop s10730 ((string_length (''sfence.vma''))))) of
+ s10740 =>
+ (case ((spc_matches_prefix0 s10740)) of
+ Some ((_, s10750)) =>
+ (case ((string_drop s10740 s10750)) of
+ s10760 =>
+ (case ((reg_name_matches_prefix s10760 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10770)) =>
+ (case ((string_drop s10760 s10770)) of
+ s10780 =>
+ (case ((sep_matches_prefix s10780)) of
+ Some ((_, s10790)) =>
+ (case ((string_drop s10780 s10790)) of
+ s10800 =>
+ (case ((reg_name_matches_prefix s10800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s10810)) =>
+ (let p00 = (string_drop s10800 s10810) in
+ if (((p00 = ('''')))) then Some (rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10720 :: " string "
+
+
+\<comment> \<open>\<open>val _s1059_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1059 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1059 s10600 = (
+ (let s10610 = s10600 in
+ if ((string_startswith s10610 (''fence.tso''))) then
+ (case ((string_drop s10610 ((string_length (''fence.tso''))))) of
+ s10620 =>
+ (case ((spc_matches_prefix0 s10620)) of
+ Some ((_, s10630)) =>
+ (case ((string_drop s10620 s10630)) of
+ s10640 =>
+ (case ((fence_bits_matches_prefix s10640 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s10650)) =>
+ (case ((string_drop s10640 s10650)) of
+ s10660 =>
+ (case ((sep_matches_prefix s10660)) of
+ Some ((_, s10670)) =>
+ (case ((string_drop s10660 s10670)) of
+ s10680 =>
+ (case ((fence_bits_matches_prefix s10680 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s10690)) =>
+ (let p00 = (string_drop s10680 s10690) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1047_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1047 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1047 s10480 = (
+ (let s10490 = s10480 in
+ if ((string_startswith s10490 (''fence''))) then
+ (case ((string_drop s10490 ((string_length (''fence''))))) of
+ s10500 =>
+ (case ((spc_matches_prefix0 s10500)) of
+ Some ((_, s10510)) =>
+ (case ((string_drop s10500 s10510)) of
+ s10520 =>
+ (case ((fence_bits_matches_prefix s10520 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s10530)) =>
+ (case ((string_drop s10520 s10530)) of
+ s10540 =>
+ (case ((sep_matches_prefix s10540)) of
+ Some ((_, s10550)) =>
+ (case ((string_drop s10540 s10550)) of
+ s10560 =>
+ (case ((fence_bits_matches_prefix s10560 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s10570)) =>
+ (let p00 = (string_drop s10560 s10570) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1030_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1030 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1030 s10320 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s10320)) of
+ Some ((op1, s10330)) =>
+ (case ((string_drop s10320 s10330)) of
+ s10340 =>
+ (case ((spc_matches_prefix0 s10340)) of
+ Some ((_, s10350)) =>
+ (case ((string_drop s10340 s10350)) of
+ s10360 =>
+ (case ((reg_name_matches_prefix s10360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10370)) =>
+ (case ((string_drop s10360 s10370)) of
+ s10380 =>
+ (case ((sep_matches_prefix s10380)) of
+ Some ((_, s10390)) =>
+ (case ((string_drop s10380 s10390)) of
+ s10400 =>
+ (case ((reg_name_matches_prefix s10400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10410)) =>
+ (case ((string_drop s10400 s10410)) of
+ s10420 =>
+ (case ((sep_matches_prefix s10420)) of
+ Some ((_, s10430)) =>
+ (case ((string_drop s10420 s10430)) of
+ s10440 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s10440 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s10450)) =>
+ (let p00 = (string_drop s10440 s10450) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s10320 :: " string "
+
+
+\<comment> \<open>\<open>val _s1013_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1013 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1013 s10150 = (
+ (case ((rtypew_mnemonic_matches_prefix s10150)) of
+ Some ((op1, s10160)) =>
+ (case ((string_drop s10150 s10160)) of
+ s10170 =>
+ (case ((spc_matches_prefix0 s10170)) of
+ Some ((_, s10180)) =>
+ (case ((string_drop s10170 s10180)) of
+ s10190 =>
+ (case ((reg_name_matches_prefix s10190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10200)) =>
+ (case ((string_drop s10190 s10200)) of
+ s10210 =>
+ (case ((sep_matches_prefix s10210)) of
+ Some ((_, s10220)) =>
+ (case ((string_drop s10210 s10220)) of
+ s10230 =>
+ (case ((reg_name_matches_prefix s10230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10240)) =>
+ (case ((string_drop s10230 s10240)) of
+ s10250 =>
+ (case ((sep_matches_prefix s10250)) of
+ Some ((_, s10260)) =>
+ (case ((string_drop s10250 s10260)) of
+ s10270 =>
+ (case ((reg_name_matches_prefix s10270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s10280)) =>
+ (let p00 = (string_drop s10270 s10280) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s10150 :: " string "
+
+
+\<comment> \<open>\<open>val _s996_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s996 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s996 s9980 = (
+ (case ((shiftw_mnemonic_matches_prefix s9980)) of
+ Some ((op1, s9990)) =>
+ (case ((string_drop s9980 s9990)) of
+ s10000 =>
+ (case ((spc_matches_prefix0 s10000)) of
+ Some ((_, s10010)) =>
+ (case ((string_drop s10000 s10010)) of
+ s10020 =>
+ (case ((reg_name_matches_prefix s10020 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10030)) =>
+ (case ((string_drop s10020 s10030)) of
+ s10040 =>
+ (case ((sep_matches_prefix s10040)) of
+ Some ((_, s10050)) =>
+ (case ((string_drop s10040 s10050)) of
+ s10060 =>
+ (case ((reg_name_matches_prefix s10060 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10070)) =>
+ (case ((string_drop s10060 s10070)) of
+ s10080 =>
+ (case ((sep_matches_prefix s10080)) of
+ Some ((_, s10090)) =>
+ (case ((string_drop s10080 s10090)) of
+ s10100 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s10100 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s10110)) =>
+ (let p00 = (string_drop s10100 s10110) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s9980 :: " string "
+
+
+\<comment> \<open>\<open>val _s980_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s980 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s980 s9810 = (
+ (let s9820 = s9810 in
+ if ((string_startswith s9820 (''addiw''))) then
+ (case ((string_drop s9820 ((string_length (''addiw''))))) of
+ s9830 =>
+ (case ((spc_matches_prefix0 s9830)) of
+ Some ((_, s9840)) =>
+ (case ((string_drop s9830 s9840)) of
+ s9850 =>
+ (case ((reg_name_matches_prefix s9850 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9860)) =>
+ (case ((string_drop s9850 s9860)) of
+ s9870 =>
+ (case ((sep_matches_prefix s9870)) of
+ Some ((_, s9880)) =>
+ (case ((string_drop s9870 s9880)) of
+ s9890 =>
+ (case ((reg_name_matches_prefix s9890 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9900)) =>
+ (case ((string_drop s9890 s9900)) of
+ s9910 =>
+ (case ((sep_matches_prefix s9910)) of
+ Some ((_, s9920)) =>
+ (case ((string_drop s9910 s9920)) of
+ s9930 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9930 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9940)) =>
+ (let p00 = (string_drop s9930 s9940) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9810 :: " string "
+
+
+\<comment> \<open>\<open>val _s952_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s952 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s952 s9530 = (
+ (let s9540 = s9530 in
+ if ((string_startswith s9540 (''s''))) then
+ (case ((string_drop s9540 ((string_length (''s''))))) of
+ s9550 =>
+ (case ((size_mnemonic_matches_prefix s9550)) of
+ Some ((size1, s9560)) =>
+ (case ((string_drop s9550 s9560)) of
+ s9570 =>
+ (case ((maybe_aq_matches_prefix s9570)) of
+ Some ((aq, s9580)) =>
+ (case ((string_drop s9570 s9580)) of
+ s9590 =>
+ (case ((maybe_rl_matches_prefix s9590)) of
+ Some ((rl, s9600)) =>
+ (case ((string_drop s9590 s9600)) of
+ s9610 =>
+ (case ((spc_matches_prefix0 s9610)) of
+ Some ((_, s9620)) =>
+ (case ((string_drop s9610 s9620)) of
+ s9630 =>
+ (case ((reg_name_matches_prefix s9630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s9640)) =>
+ (case ((string_drop s9630 s9640)) of
+ s9650 =>
+ (case ((sep_matches_prefix s9650)) of
+ Some ((_, s9660)) =>
+ (case ((string_drop s9650 s9660)) of
+ s9670 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9670 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9680)) =>
+ (case ((string_drop s9670 s9680)) of
+ s9690 =>
+ (case ((opt_spc_matches_prefix0 s9690)) of
+ Some ((_, s9700)) =>
+ (let s9710 = (string_drop s9690 s9700) in
+ if ((string_startswith s9710 (''(''))) then
+ (case ((string_drop s9710 ((string_length (''(''))))) of
+ s9720 =>
+ (case ((opt_spc_matches_prefix0 s9720)) of
+ Some ((_, s9730)) =>
+ (case ((string_drop s9720 s9730)) of
+ s9740 =>
+ (case ((reg_name_matches_prefix s9740 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9750)) =>
+ (case ((string_drop s9740 s9750)) of
+ s9760 =>
+ (case ((opt_spc_matches_prefix0 s9760)) of
+ Some ((_, s9770)) =>
+ (let s9780 = (string_drop s9760 s9770) in
+ if ((string_startswith s9780 ('')''))) then
+ (let p00 = (string_drop s9780 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rs2, imm, rs1) else
+ None) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9530 :: " string "
+
+
+\<comment> \<open>\<open>val _s922_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s922 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s922 s9230 = (
+ (let s9240 = s9230 in
+ if ((string_startswith s9240 (''l''))) then
+ (case ((string_drop s9240 ((string_length (''l''))))) of
+ s9250 =>
+ (case ((size_mnemonic_matches_prefix s9250)) of
+ Some ((size1, s9260)) =>
+ (case ((string_drop s9250 s9260)) of
+ s9270 =>
+ (case ((maybe_u_matches_prefix s9270)) of
+ Some ((is_unsigned, s9280)) =>
+ (case ((string_drop s9270 s9280)) of
+ s9290 =>
+ (case ((maybe_aq_matches_prefix s9290)) of
+ Some ((aq, s9300)) =>
+ (case ((string_drop s9290 s9300)) of
+ s9310 =>
+ (case ((maybe_rl_matches_prefix s9310)) of
+ Some ((rl, s9320)) =>
+ (case ((string_drop s9310 s9320)) of
+ s9330 =>
+ (case ((spc_matches_prefix0 s9330)) of
+ Some ((_, s9340)) =>
+ (case ((string_drop s9330 s9340)) of
+ s9350 =>
+ (case ((reg_name_matches_prefix s9350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9360)) =>
+ (case ((string_drop s9350 s9360)) of
+ s9370 =>
+ (case ((sep_matches_prefix s9370)) of
+ Some ((_, s9380)) =>
+ (case ((string_drop s9370 s9380)) of
+ s9390 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9390 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9400)) =>
+ (case ((string_drop s9390 s9400)) of
+ s9410 =>
+ (case ((opt_spc_matches_prefix0 s9410)) of
+ Some ((_, s9420)) =>
+ (let s9430 = (string_drop s9410 s9420) in
+ if ((string_startswith s9430 (''(''))) then
+ (case ((string_drop s9430 ((string_length (''(''))))) of
+ s9440 =>
+ (case ((opt_spc_matches_prefix0 s9440)) of
+ Some ((_, s9450)) =>
+ (case ((string_drop s9440 s9450)) of
+ s9460 =>
+ (case ((reg_name_matches_prefix s9460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9470)) =>
+ (case ((string_drop s9460 s9470)) of
+ s9480 =>
+ (case ((opt_spc_matches_prefix0 s9480)) of
+ Some ((_, s9490)) =>
+ (let s9500 = (string_drop s9480 s9490) in
+ if ((string_startswith s9500 ('')''))) then
+ (let p00 = (string_drop s9500 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1) else None) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9230 :: " string "
+
+
+\<comment> \<open>\<open>val _s905_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s905 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s905 s9070 = (
+ (case ((rtype_mnemonic_matches_prefix s9070)) of
+ Some ((op1, s9080)) =>
+ (case ((string_drop s9070 s9080)) of
+ s9090 =>
+ (case ((spc_matches_prefix0 s9090)) of
+ Some ((_, s9100)) =>
+ (case ((string_drop s9090 s9100)) of
+ s9110 =>
+ (case ((reg_name_matches_prefix s9110 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9120)) =>
+ (case ((string_drop s9110 s9120)) of
+ s9130 =>
+ (case ((sep_matches_prefix s9130)) of
+ Some ((_, s9140)) =>
+ (case ((string_drop s9130 s9140)) of
+ s9150 =>
+ (case ((reg_name_matches_prefix s9150 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9160)) =>
+ (case ((string_drop s9150 s9160)) of
+ s9170 =>
+ (case ((sep_matches_prefix s9170)) of
+ Some ((_, s9180)) =>
+ (case ((string_drop s9170 s9180)) of
+ s9190 =>
+ (case ((reg_name_matches_prefix s9190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s9200)) =>
+ (let p00 = (string_drop s9190 s9200) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s9070 :: " string "
+
+
+\<comment> \<open>\<open>val _s888_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))\<close>\<close>
+
+definition s888 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word)option " where
+ " s888 s8900 = (
+ (case ((shiftiop_mnemonic_matches_prefix s8900)) of
+ Some ((op1, s8910)) =>
+ (case ((string_drop s8900 s8910)) of
+ s8920 =>
+ (case ((spc_matches_prefix0 s8920)) of
+ Some ((_, s8930)) =>
+ (case ((string_drop s8920 s8930)) of
+ s8940 =>
+ (case ((reg_name_matches_prefix s8940 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8950)) =>
+ (case ((string_drop s8940 s8950)) of
+ s8960 =>
+ (case ((sep_matches_prefix s8960)) of
+ Some ((_, s8970)) =>
+ (case ((string_drop s8960 s8970)) of
+ s8980 =>
+ (case ((reg_name_matches_prefix s8980 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8990)) =>
+ (case ((string_drop s8980 s8990)) of
+ s9000 =>
+ (case ((sep_matches_prefix s9000)) of
+ Some ((_, s9010)) =>
+ (case ((string_drop s9000 s9010)) of
+ s9020 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9020 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s9030)) =>
+ (let p00 = (string_drop s9020 s9030) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8900 :: " string "
+
+
+\<comment> \<open>\<open>val _s871_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s871 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s871 s8730 = (
+ (case ((itype_mnemonic_matches_prefix s8730)) of
+ Some ((op1, s8740)) =>
+ (case ((string_drop s8730 s8740)) of
+ s8750 =>
+ (case ((spc_matches_prefix0 s8750)) of
+ Some ((_, s8760)) =>
+ (case ((string_drop s8750 s8760)) of
+ s8770 =>
+ (case ((reg_name_matches_prefix s8770 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8780)) =>
+ (case ((string_drop s8770 s8780)) of
+ s8790 =>
+ (case ((sep_matches_prefix s8790)) of
+ Some ((_, s8800)) =>
+ (case ((string_drop s8790 s8800)) of
+ s8810 =>
+ (case ((reg_name_matches_prefix s8810 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8820)) =>
+ (case ((string_drop s8810 s8820)) of
+ s8830 =>
+ (case ((sep_matches_prefix s8830)) of
+ Some ((_, s8840)) =>
+ (case ((string_drop s8830 s8840)) of
+ s8850 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8850 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s8860)) =>
+ (let p00 = (string_drop s8850 s8860) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8730 :: " string "
+
+
+\<comment> \<open>\<open>val _s854_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))\<close>\<close>
+
+definition s854 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word)option " where
+ " s854 s8560 = (
+ (case ((btype_mnemonic_matches_prefix s8560)) of
+ Some ((op1, s8570)) =>
+ (case ((string_drop s8560 s8570)) of
+ s8580 =>
+ (case ((spc_matches_prefix0 s8580)) of
+ Some ((_, s8590)) =>
+ (case ((string_drop s8580 s8590)) of
+ s8600 =>
+ (case ((reg_name_matches_prefix s8600 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8610)) =>
+ (case ((string_drop s8600 s8610)) of
+ s8620 =>
+ (case ((sep_matches_prefix s8620)) of
+ Some ((_, s8630)) =>
+ (case ((string_drop s8620 s8630)) of
+ s8640 =>
+ (case ((reg_name_matches_prefix s8640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s8650)) =>
+ (case ((string_drop s8640 s8650)) of
+ s8660 =>
+ (case ((sep_matches_prefix s8660)) of
+ Some ((_, s8670)) =>
+ (case ((string_drop s8660 s8670)) of
+ s8680 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8680 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s8690)) =>
+ (let p00 = (string_drop s8680 s8690) in
+ if (((p00 = ('''')))) then Some (op1, rs1, rs2, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8560 :: " string "
+
+
+\<comment> \<open>\<open>val _s838_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s838 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s838 s8390 = (
+ (let s8400 = s8390 in
+ if ((string_startswith s8400 (''jalr''))) then
+ (case ((string_drop s8400 ((string_length (''jalr''))))) of
+ s8410 =>
+ (case ((spc_matches_prefix0 s8410)) of
+ Some ((_, s8420)) =>
+ (case ((string_drop s8410 s8420)) of
+ s8430 =>
+ (case ((reg_name_matches_prefix s8430 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8440)) =>
+ (case ((string_drop s8430 s8440)) of
+ s8450 =>
+ (case ((sep_matches_prefix s8450)) of
+ Some ((_, s8460)) =>
+ (case ((string_drop s8450 s8460)) of
+ s8470 =>
+ (case ((reg_name_matches_prefix s8470 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8480)) =>
+ (case ((string_drop s8470 s8480)) of
+ s8490 =>
+ (case ((sep_matches_prefix s8490)) of
+ Some ((_, s8500)) =>
+ (case ((string_drop s8490 s8500)) of
+ s8510 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8510 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s8520)) =>
+ (let p00 = (string_drop s8510 s8520) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s8390 :: " string "
+
+
+\<comment> \<open>\<open>val _s826_ : string -> maybe ((mword ty5 * mword ty21))\<close>\<close>
+
+definition s826 :: " string \<Rightarrow>((5)Word.word*(21)Word.word)option " where
+ " s826 s8270 = (
+ (let s8280 = s8270 in
+ if ((string_startswith s8280 (''jal''))) then
+ (case ((string_drop s8280 ((string_length (''jal''))))) of
+ s8290 =>
+ (case ((spc_matches_prefix0 s8290)) of
+ Some ((_, s8300)) =>
+ (case ((string_drop s8290 s8300)) of
+ s8310 =>
+ (case ((reg_name_matches_prefix s8310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8320)) =>
+ (case ((string_drop s8310 s8320)) of
+ s8330 =>
+ (case ((sep_matches_prefix s8330)) of
+ Some ((_, s8340)) =>
+ (case ((string_drop s8330 s8340)) of
+ s8350 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8350 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s8360)) =>
+ (let p00 = (string_drop s8350 s8360) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s8270 :: " string "
+
+
+\<comment> \<open>\<open>val _s813_ : string -> maybe ((uop * mword ty5 * mword ty20))\<close>\<close>
+
+definition s813 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word)option " where
+ " s813 s8150 = (
+ (case ((utype_mnemonic_matches_prefix s8150)) of
+ Some ((op1, s8160)) =>
+ (case ((string_drop s8150 s8160)) of
+ s8170 =>
+ (case ((spc_matches_prefix0 s8170)) of
+ Some ((_, s8180)) =>
+ (case ((string_drop s8170 s8180)) of
+ s8190 =>
+ (case ((reg_name_matches_prefix s8190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8200)) =>
+ (case ((string_drop s8190 s8200)) of
+ s8210 =>
+ (case ((sep_matches_prefix s8210)) of
+ Some ((_, s8220)) =>
+ (case ((string_drop s8210 s8220)) of
+ s8230 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8230 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s8240)) =>
+ (let p00 = (string_drop s8230 s8240) in
+ if (((p00 = ('''')))) then Some (op1, rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8150 :: " string "
+
+
+definition assembly_backwards :: " string \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " assembly_backwards arg1 = (
+ (let s8250 = arg1 in
+ if ((case ((s813 s8250 :: ((uop * 5 Word.word * 20 Word.word))option)) of
+ Some ((op1, rd, imm)) => True
+ | _ => False
+ )) then (case (s813 s8250 :: (( uop * 5 Word.word * 20 Word.word)) option) of
+ (Some ((op1, rd, imm))) =>
+ return (UTYPE (imm, rd, op1))
+ )
+ else if ((case ((s826 s8250 :: (( 5 Word.word * 21 Word.word))option)) of
+ Some ((rd, imm)) => True
+ | _ => False
+ )) then (case (s826 s8250 :: (( 5 Word.word * 21 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (RISCV_JAL (imm, rd))
+ )
+ else if ((case ((s838 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => True
+ | _ => False
+ )) then (case (s838 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ return (RISCV_JALR (imm, rs1, rd))
+ )
+ else if ((case ((s854 s8250 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word))option)) of
+ Some ((op1, rs1, rs2, imm)) => True
+ | _ => False
+ )) then (case
+ (s854 s8250 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word)) option) of
+ (Some ((op1, rs1, rs2, imm))) =>
+ return (BTYPE (imm, rs2, rs1, op1))
+ )
+ else if ((case ((s871 s8250 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, imm)) => True
+ | _ => False
+ )) then (case
+ (s871 s8250 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, imm))) =>
+ return (ITYPE (imm, rs1, rd, op1))
+ )
+ else if ((case ((s888 s8250 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => True
+ | _ => False
+ )) then (case
+ (s888 s8250 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTIOP (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s905 s8250 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s905 s8250 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ return (RTYPE (rs2, rs1, rd, op1))
+ )
+ else if ((case ((s922 s8250
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s922 s8250
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ return (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl))
+ )
+ else if ((case ((s952 s8250
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s952 s8250 :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1))) =>
+ return (STORE (imm, rs2, rs1, size1, aq, rl))
+ )
+ else if ((case ((s980 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s980 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ return (ADDIW (imm, rs1, rd))
+ )
+ else if ((case ((s996 s8250 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s996 s8250 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTW (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s1013 s8250 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1013 s8250 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ return (RTYPEW (rs2, rs1, rd, op1))
+ )
+ else if ((case ((s1030 s8250 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1030 s8250 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTIWOP (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s1047 s8250 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1047 s8250 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ return (FENCE (pred, succ))
+ )
+ else if ((case ((s1059 s8250 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1059 s8250 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ return (FENCE_TSO (pred, succ))
+ )
+ else if (((s8250 = (''fence.i'')))) then return (FENCEI () )
+ else if (((s8250 = (''ecall'')))) then return (ECALL () )
+ else if (((s8250 = (''mret'')))) then return (MRET () )
+ else if (((s8250 = (''sret'')))) then return (SRET () )
+ else if (((s8250 = (''ebreak'')))) then return (EBREAK () )
+ else if (((s8250 = (''wfi'')))) then return (WFI () )
+ else if ((case ((s1071 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rs1, rs2)) => True
+ | _ => False
+ )) then (case (s1071 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rs1, rs2))) =>
+ return (SFENCE_VMA (rs1, rs2))
+ )
+ else if ((case ((s1083 s8250 :: ((word_width * bool * bool * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1083 s8250 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1))) =>
+ return (LOADRES (aq, rl, rs1, size1, rd))
+ )
+ else if ((case ((s1101 s8250
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1101 s8250 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2))) =>
+ return (STORECON (aq, rl, rs2, rs1, size1, rd))
+ )
+ else if ((case ((s1123 s8250
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1123 s8250
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2))) =>
+ return (AMO (op1, aq, rl, rs2, rs1, width, rd))
+ )
+ else if (((s8250 = (''c.nop'')))) then return (C_NOP () )
+ else if ((case ((s1147 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rdc, nzimm)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s1147 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rdc, nzimm))) =>
+ return (C_ADDI4SPN (rdc, nzimm))
+ )
+ else if ((case ((s1159 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => True
+ | _ => False
+ )) then (case (s1159 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ return (C_LW (uimm, rsc, rdc))
+ )
+ else if ((case ((s1175 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1175 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ return (C_LD (uimm, rsc, rdc))
+ )
+ else if ((case ((s1191 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => True
+ | _ => False
+ )) then (case
+ (s1191 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ return (C_SW (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1207 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1207 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ return (C_SD (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1223 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, nzi)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1223 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, nzi))) =>
+ return (C_ADDI (nzi, rsd))
+ )
+ else if ((case ((s1235 s8250 :: ( 11 Word.word)option)) of
+ Some (imm) => ((( 32 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s1235 s8250 :: ( 11 Word.word) option) of
+ (Some (imm)) =>
+ return (C_JAL imm)
+ )
+ else if ((case ((s1243 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1243 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ return (C_ADDIW (imm, rsd))
+ )
+ else if ((case ((s1255 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1255 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (C_LI (imm, rd))
+ )
+ else if ((case ((s1267 s8250 :: ( 6 Word.word)option)) of
+ Some (imm) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1267 s8250 :: ( 6 Word.word) option) of
+ (Some (imm)) =>
+ return (C_ADDI16SP imm)
+ )
+ else if ((case ((s1275 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s1275 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (C_LUI (imm, rd))
+ )
+ else if ((case ((s1287 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1287 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SRLI (shamt, rsd))
+ )
+ else if ((case ((s1299 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1299 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SRAI (shamt, rsd))
+ )
+ else if ((case ((s1311 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => True
+ | _ => False
+ )) then (case (s1311 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ return (C_ANDI (imm, rsd))
+ )
+ else if ((case ((s1323 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1323 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_SUB (rsd, rs2))
+ )
+ else if ((case ((s1335 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1335 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_XOR (rsd, rs2))
+ )
+ else if ((case ((s1347 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1347 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_OR (rsd, rs2))
+ )
+ else if ((case ((s1359 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1359 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_AND (rsd, rs2))
+ )
+ else if ((case ((s1371 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1371 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_SUBW (rsd, rs2))
+ )
+ else if ((case ((s1383 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1383 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_ADDW (rsd, rs2))
+ )
+ else if ((case ((s1395 s8250 :: ( 11 Word.word)option)) of
+ Some (imm) => True
+ | _ => False
+ )) then (case (s1395 s8250 :: ( 11 Word.word) option) of
+ (Some (imm)) =>
+ return (C_J imm)
+ )
+ else if ((case ((s1403 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s1403 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ return (C_BEQZ (imm, rs))
+ )
+ else if ((case ((s1415 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s1415 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ return (C_BNEZ (imm, rs))
+ )
+ else if ((case ((s1427 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1427 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SLLI (shamt, rsd))
+ )
+ else if ((case ((s1439 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1439 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_LWSP (uimm, rd))
+ )
+ else if ((case ((s1451 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s1451 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_LDSP (uimm, rd))
+ )
+ else if ((case ((s1463 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => True
+ | _ => False
+ )) then (case (s1463 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_SWSP (uimm, rd))
+ )
+ else if ((case ((s1475 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rs2, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1475 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rs2, uimm))) =>
+ return (C_SDSP (uimm, rs2))
+ )
+ else if ((case ((s1487 s8250 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1487 s8250 :: ( 5 Word.word) option) of
+ (Some (rs1)) =>
+ return (C_JR rs1)
+ )
+ else if ((case ((s1495 s8250 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1495 s8250 :: ( 5 Word.word) option) of
+ (Some (rs1)) =>
+ return (C_JALR rs1)
+ )
+ else if ((case ((s1503 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1503 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs2))) =>
+ return (C_MV (rd, rs2))
+ )
+ else if (((s8250 = (''c.ebreak'')))) then return (C_EBREAK () )
+ else if ((case ((s1515 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1515 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_ADD (rsd, rs2))
+ )
+ else if ((case ((s1527 s8250
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1527 s8250 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2))) =>
+ return (MUL (rs2, rs1, rd, high, signed1, signed2))
+ )
+ else if ((case ((s1544 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1544 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (DIV (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1562 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1562 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (REM (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1580 s8250 :: (( 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1580 s8250 :: (( 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs1, rs2))) =>
+ return (MULW (rs2, rs1, rd))
+ )
+ else if ((case ((s1596 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1596 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (DIVW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1615 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1615 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (REMW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1634 s8250 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s1634 s8250 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ return (CSR (csr, rs1, rd, True, op1))
+ )
+ else if ((case ((s1652 s8250 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s1652 s8250 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ return (CSR (csr, rs1, rd, False, op1))
+ )
+ else if (((s8250 = (''uret'')))) then return (URET () )
+ else if ((case ((s1669 s8250 :: ( 32 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s1669 s8250 :: ( 32 Word.word) option) of
+ (Some (s)) =>
+ return (ILLEGAL s)
+ )
+ else if ((case ((s1677 s8250 :: ( 16 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s1677 s8250 :: ( 16 Word.word) option) of
+ (Some (s)) =>
+ return (C_ILLEGAL s)
+ )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val assembly_forwards_matches : ast -> bool\<close>\<close>
+
+fun assembly_forwards_matches :: " ast \<Rightarrow> bool " where
+ " assembly_forwards_matches (UTYPE ((imm, rd, op1))) = ( True )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RISCV_JAL ((imm, rd))) = ( True )"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RISCV_JALR ((imm, rs1, rd))) = ( True )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (BTYPE ((imm, rs2, rs1, op1))) = ( True )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" assembly_forwards_matches (ITYPE ((imm, rs1, rd, op1))) = ( True )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTIOP ((shamt, rs1, rd, op1))) = ( True )"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RTYPE ((rs2, rs1, rd, op1))) = ( True )"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl))) = ( True )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (STORE ((imm, rs2, rs1, size1, aq, rl))) = ( True )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (ADDIW ((imm, rs1, rd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTW ((shamt, rs1, rd, op1))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RTYPEW ((rs2, rs1, rd, op1))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, op1))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (FENCE ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards_matches (FENCE_TSO ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards_matches (FENCEI (_)) = ( True )"
+|" assembly_forwards_matches (ECALL (_)) = ( True )"
+|" assembly_forwards_matches (MRET (_)) = ( True )"
+|" assembly_forwards_matches (SRET (_)) = ( True )"
+|" assembly_forwards_matches (EBREAK (_)) = ( True )"
+|" assembly_forwards_matches (WFI (_)) = ( True )"
+|" assembly_forwards_matches (SFENCE_VMA ((rs1, rs2))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (LOADRES ((aq, rl, rs1, size1, rd))) = ( True )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (STORECON ((aq, rl, rs2, rs1, size1, rd))) = ( True )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = ( True )"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" assembly_forwards_matches (C_NOP (_)) = ( True )"
+|" assembly_forwards_matches (C_ADDI4SPN ((rdc, nzimm))) = (
+ if (((nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then True else False )"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_LW ((uimm, rsc, rdc))) = ( True )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_LD ((uimm, rsc, rdc))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_SW ((uimm, rsc1, rsc2))) = ( True )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards_matches (C_SD ((uimm, rsc1, rsc2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards_matches (C_ADDI ((nzi, rsd))) = (
+ if ((((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" assembly_forwards_matches (C_JAL (imm)) = ( if ((((( 32 :: int)::ii) = (( 32 :: int)::ii)))) then True else False )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards_matches (C_ADDIW ((imm, rsd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_LI ((imm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_ADDI16SP (imm)) = (
+ if (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_LUI ((imm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then
+ True
+ else False )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SRLI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_SRAI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_ANDI ((imm, rsd))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_SUB ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_XOR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_OR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_AND ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_SUBW ((rsd, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_ADDW ((rsd, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_J (imm)) = ( True )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards_matches (C_BEQZ ((imm, rs))) = ( True )"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards_matches (C_BNEZ ((imm, rs))) = ( True )"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards_matches (C_SLLI ((shamt, rsd))) = (
+ if ((((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_LWSP ((uimm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_LDSP ((uimm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SWSP ((uimm, rd))) = ( True )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SDSP ((uimm, rs2))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards_matches (C_JR (rs1)) = ( if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_EBREAK (_)) = ( True )"
+|" assembly_forwards_matches (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards_matches (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( True )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (DIV ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (REM ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (MULW ((rs2, rs1, rd))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (DIVW ((rs2, rs1, rd, s))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (REMW ((rs2, rs1, rd, s))) = ( if ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (CSR ((csr, rs1, rd, True, op1))) = ( True )"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards_matches (CSR ((csr, rs1, rd, False, op1))) = ( True )"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards_matches (URET (_)) = ( True )"
+|" assembly_forwards_matches (ILLEGAL (s)) = ( True )"
+ for s :: "(32)Word.word "
+|" assembly_forwards_matches (C_ILLEGAL (s)) = ( True )"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val assembly_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s2549_ : string -> maybe (mword ty16)\<close>\<close>
+
+definition s2549 :: " string \<Rightarrow>((16)Word.word)option " where
+ " s2549 s25500 = (
+ (let s25510 = s25500 in
+ if ((string_startswith s25510 (''c.illegal''))) then
+ (case ((string_drop s25510 ((string_length (''c.illegal''))))) of
+ s25520 =>
+ (case ((spc_matches_prefix0 s25520)) of
+ Some ((_, s25530)) =>
+ (case ((string_drop s25520 s25530)) of
+ s25540 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25540 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s25550)) =>
+ (let p00 = (string_drop s25540 s25550) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25500 :: " string "
+
+
+\<comment> \<open>\<open>val _s2541_ : string -> maybe (mword ty32)\<close>\<close>
+
+definition s2541 :: " string \<Rightarrow>((32)Word.word)option " where
+ " s2541 s25420 = (
+ (let s25430 = s25420 in
+ if ((string_startswith s25430 (''illegal''))) then
+ (case ((string_drop s25430 ((string_length (''illegal''))))) of
+ s25440 =>
+ (case ((spc_matches_prefix0 s25440)) of
+ Some ((_, s25450)) =>
+ (case ((string_drop s25440 s25450)) of
+ s25460 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25460 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s25470)) =>
+ (let p00 = (string_drop s25460 s25470) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25420 :: " string "
+
+
+\<comment> \<open>\<open>val _s2524_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s2524 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s2524 s25260 = (
+ (case ((csr_mnemonic_matches_prefix s25260)) of
+ Some ((op1, s25270)) =>
+ (case ((string_drop s25260 s25270)) of
+ s25280 =>
+ (case ((spc_matches_prefix0 s25280)) of
+ Some ((_, s25290)) =>
+ (case ((string_drop s25280 s25290)) of
+ s25300 =>
+ (case ((reg_name_matches_prefix s25300 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25310)) =>
+ (case ((string_drop s25300 s25310)) of
+ s25320 =>
+ (case ((sep_matches_prefix s25320)) of
+ Some ((_, s25330)) =>
+ (case ((string_drop s25320 s25330)) of
+ s25340 =>
+ (case ((reg_name_matches_prefix s25340 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25350)) =>
+ (case ((string_drop s25340 s25350)) of
+ s25360 =>
+ (case ((sep_matches_prefix s25360)) of
+ Some ((_, s25370)) =>
+ (case ((string_drop s25360 s25370)) of
+ s25380 =>
+ (case ((csr_name_map_matches_prefix s25380
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s25390)) =>
+ (let p00 = (string_drop s25380 s25390) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s25260 :: " string "
+
+
+\<comment> \<open>\<open>val _s2506_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s2506 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s2506 s25080 = (
+ (case ((csr_mnemonic_matches_prefix s25080)) of
+ Some ((op1, s25090)) =>
+ (let s25100 = (string_drop s25080 s25090) in
+ if ((string_startswith s25100 (''i''))) then
+ (case ((string_drop s25100 ((string_length (''i''))))) of
+ s25110 =>
+ (case ((spc_matches_prefix0 s25110)) of
+ Some ((_, s25120)) =>
+ (case ((string_drop s25110 s25120)) of
+ s25130 =>
+ (case ((reg_name_matches_prefix s25130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25140)) =>
+ (case ((string_drop s25130 s25140)) of
+ s25150 =>
+ (case ((sep_matches_prefix s25150)) of
+ Some ((_, s25160)) =>
+ (case ((string_drop s25150 s25160)) of
+ s25170 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25180)) =>
+ (case ((string_drop s25170 s25180)) of
+ s25190 =>
+ (case ((sep_matches_prefix s25190)) of
+ Some ((_, s25200)) =>
+ (case ((string_drop s25190 s25200)) of
+ s25210 =>
+ (case ((csr_name_map_matches_prefix s25210
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s25220)) =>
+ (let p00 = (string_drop s25210 s25220) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s25080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2487_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2487 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2487 s24880 = (
+ (let s24890 = s24880 in
+ if ((string_startswith s24890 (''rem''))) then
+ (case ((string_drop s24890 ((string_length (''rem''))))) of
+ s24900 =>
+ (case ((maybe_not_u_matches_prefix s24900)) of
+ Some ((s, s24910)) =>
+ (let s24920 = (string_drop s24900 s24910) in
+ if ((string_startswith s24920 (''w''))) then
+ (case ((string_drop s24920 ((string_length (''w''))))) of
+ s24930 =>
+ (case ((spc_matches_prefix0 s24930)) of
+ Some ((_, s24940)) =>
+ (case ((string_drop s24930 s24940)) of
+ s24950 =>
+ (case ((reg_name_matches_prefix s24950 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24960)) =>
+ (case ((string_drop s24950 s24960)) of
+ s24970 =>
+ (case ((sep_matches_prefix s24970)) of
+ Some ((_, s24980)) =>
+ (case ((string_drop s24970 s24980)) of
+ s24990 =>
+ (case ((reg_name_matches_prefix s24990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25000)) =>
+ (case ((string_drop s24990 s25000)) of
+ s25010 =>
+ (case ((sep_matches_prefix s25010)) of
+ Some ((_, s25020)) =>
+ (case ((string_drop s25010 s25020)) of
+ s25030 =>
+ (case ((reg_name_matches_prefix s25030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s25040)) =>
+ (let p00 = (string_drop s25030 s25040) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s24880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2468_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2468 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2468 s24690 = (
+ (let s24700 = s24690 in
+ if ((string_startswith s24700 (''div''))) then
+ (case ((string_drop s24700 ((string_length (''div''))))) of
+ s24710 =>
+ (case ((maybe_not_u_matches_prefix s24710)) of
+ Some ((s, s24720)) =>
+ (let s24730 = (string_drop s24710 s24720) in
+ if ((string_startswith s24730 (''w''))) then
+ (case ((string_drop s24730 ((string_length (''w''))))) of
+ s24740 =>
+ (case ((spc_matches_prefix0 s24740)) of
+ Some ((_, s24750)) =>
+ (case ((string_drop s24740 s24750)) of
+ s24760 =>
+ (case ((reg_name_matches_prefix s24760 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24770)) =>
+ (case ((string_drop s24760 s24770)) of
+ s24780 =>
+ (case ((sep_matches_prefix s24780)) of
+ Some ((_, s24790)) =>
+ (case ((string_drop s24780 s24790)) of
+ s24800 =>
+ (case ((reg_name_matches_prefix s24800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24810)) =>
+ (case ((string_drop s24800 s24810)) of
+ s24820 =>
+ (case ((sep_matches_prefix s24820)) of
+ Some ((_, s24830)) =>
+ (case ((string_drop s24820 s24830)) of
+ s24840 =>
+ (case ((reg_name_matches_prefix s24840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24850)) =>
+ (let p00 = (string_drop s24840 s24850) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s24690 :: " string "
+
+
+\<comment> \<open>\<open>val _s2452_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2452 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2452 s24530 = (
+ (let s24540 = s24530 in
+ if ((string_startswith s24540 (''mulw''))) then
+ (case ((string_drop s24540 ((string_length (''mulw''))))) of
+ s24550 =>
+ (case ((spc_matches_prefix0 s24550)) of
+ Some ((_, s24560)) =>
+ (case ((string_drop s24550 s24560)) of
+ s24570 =>
+ (case ((reg_name_matches_prefix s24570 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24580)) =>
+ (case ((string_drop s24570 s24580)) of
+ s24590 =>
+ (case ((sep_matches_prefix s24590)) of
+ Some ((_, s24600)) =>
+ (case ((string_drop s24590 s24600)) of
+ s24610 =>
+ (case ((reg_name_matches_prefix s24610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24620)) =>
+ (case ((string_drop s24610 s24620)) of
+ s24630 =>
+ (case ((sep_matches_prefix s24630)) of
+ Some ((_, s24640)) =>
+ (case ((string_drop s24630 s24640)) of
+ s24650 =>
+ (case ((reg_name_matches_prefix s24650 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24660)) =>
+ (let p00 = (string_drop s24650 s24660) in
+ if (((p00 = ('''')))) then Some (rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24530 :: " string "
+
+
+\<comment> \<open>\<open>val _s2434_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2434 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2434 s24350 = (
+ (let s24360 = s24350 in
+ if ((string_startswith s24360 (''rem''))) then
+ (case ((string_drop s24360 ((string_length (''rem''))))) of
+ s24370 =>
+ (case ((maybe_not_u_matches_prefix s24370)) of
+ Some ((s, s24380)) =>
+ (case ((string_drop s24370 s24380)) of
+ s24390 =>
+ (case ((spc_matches_prefix0 s24390)) of
+ Some ((_, s24400)) =>
+ (case ((string_drop s24390 s24400)) of
+ s24410 =>
+ (case ((reg_name_matches_prefix s24410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24420)) =>
+ (case ((string_drop s24410 s24420)) of
+ s24430 =>
+ (case ((sep_matches_prefix s24430)) of
+ Some ((_, s24440)) =>
+ (case ((string_drop s24430 s24440)) of
+ s24450 =>
+ (case ((reg_name_matches_prefix s24450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24460)) =>
+ (case ((string_drop s24450 s24460)) of
+ s24470 =>
+ (case ((sep_matches_prefix s24470)) of
+ Some ((_, s24480)) =>
+ (case ((string_drop s24470 s24480)) of
+ s24490 =>
+ (case ((reg_name_matches_prefix s24490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24500)) =>
+ (let p00 = (string_drop s24490 s24500) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24350 :: " string "
+
+
+\<comment> \<open>\<open>val _s2416_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2416 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2416 s24170 = (
+ (let s24180 = s24170 in
+ if ((string_startswith s24180 (''div''))) then
+ (case ((string_drop s24180 ((string_length (''div''))))) of
+ s24190 =>
+ (case ((maybe_not_u_matches_prefix s24190)) of
+ Some ((s, s24200)) =>
+ (case ((string_drop s24190 s24200)) of
+ s24210 =>
+ (case ((spc_matches_prefix0 s24210)) of
+ Some ((_, s24220)) =>
+ (case ((string_drop s24210 s24220)) of
+ s24230 =>
+ (case ((reg_name_matches_prefix s24230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24240)) =>
+ (case ((string_drop s24230 s24240)) of
+ s24250 =>
+ (case ((sep_matches_prefix s24250)) of
+ Some ((_, s24260)) =>
+ (case ((string_drop s24250 s24260)) of
+ s24270 =>
+ (case ((reg_name_matches_prefix s24270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24280)) =>
+ (case ((string_drop s24270 s24280)) of
+ s24290 =>
+ (case ((sep_matches_prefix s24290)) of
+ Some ((_, s24300)) =>
+ (case ((string_drop s24290 s24300)) of
+ s24310 =>
+ (case ((reg_name_matches_prefix s24310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24320)) =>
+ (let p00 = (string_drop s24310 s24320) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24170 :: " string "
+
+
+\<comment> \<open>\<open>val _s2399_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2399 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2399 s24010 = (
+ (case ((mul_mnemonic_matches_prefix s24010)) of
+ Some (((high, signed1, signed2), s24020)) =>
+ (case ((string_drop s24010 s24020)) of
+ s24030 =>
+ (case ((spc_matches_prefix0 s24030)) of
+ Some ((_, s24040)) =>
+ (case ((string_drop s24030 s24040)) of
+ s24050 =>
+ (case ((reg_name_matches_prefix s24050 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24060)) =>
+ (case ((string_drop s24050 s24060)) of
+ s24070 =>
+ (case ((sep_matches_prefix s24070)) of
+ Some ((_, s24080)) =>
+ (case ((string_drop s24070 s24080)) of
+ s24090 =>
+ (case ((reg_name_matches_prefix s24090 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24100)) =>
+ (case ((string_drop s24090 s24100)) of
+ s24110 =>
+ (case ((sep_matches_prefix s24110)) of
+ Some ((_, s24120)) =>
+ (case ((string_drop s24110 s24120)) of
+ s24130 =>
+ (case ((reg_name_matches_prefix s24130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24140)) =>
+ (let p00 = (string_drop s24130 s24140) in
+ if (((p00 = ('''')))) then Some (high, signed1, signed2, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s24010 :: " string "
+
+
+\<comment> \<open>\<open>val _s2387_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s2387 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s2387 s23880 = (
+ (let s23890 = s23880 in
+ if ((string_startswith s23890 (''c.add''))) then
+ (case ((string_drop s23890 ((string_length (''c.add''))))) of
+ s23900 =>
+ (case ((spc_matches_prefix0 s23900)) of
+ Some ((_, s23910)) =>
+ (case ((string_drop s23900 s23910)) of
+ s23920 =>
+ (case ((reg_name_matches_prefix s23920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s23930)) =>
+ (case ((string_drop s23920 s23930)) of
+ s23940 =>
+ (case ((sep_matches_prefix s23940)) of
+ Some ((_, s23950)) =>
+ (case ((string_drop s23940 s23950)) of
+ s23960 =>
+ (case ((reg_name_matches_prefix s23960 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23970)) =>
+ (let p00 = (string_drop s23960 s23970) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2375_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s2375 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s2375 s23760 = (
+ (let s23770 = s23760 in
+ if ((string_startswith s23770 (''c.mv''))) then
+ (case ((string_drop s23770 ((string_length (''c.mv''))))) of
+ s23780 =>
+ (case ((spc_matches_prefix0 s23780)) of
+ Some ((_, s23790)) =>
+ (case ((string_drop s23780 s23790)) of
+ s23800 =>
+ (case ((reg_name_matches_prefix s23800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23810)) =>
+ (case ((string_drop s23800 s23810)) of
+ s23820 =>
+ (case ((sep_matches_prefix s23820)) of
+ Some ((_, s23830)) =>
+ (case ((string_drop s23820 s23830)) of
+ s23840 =>
+ (case ((reg_name_matches_prefix s23840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23850)) =>
+ (let p00 = (string_drop s23840 s23850) in
+ if (((p00 = ('''')))) then Some (rd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2367_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s2367 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s2367 s23680 = (
+ (let s23690 = s23680 in
+ if ((string_startswith s23690 (''c.jalr''))) then
+ (case ((string_drop s23690 ((string_length (''c.jalr''))))) of
+ s23700 =>
+ (case ((spc_matches_prefix0 s23700)) of
+ Some ((_, s23710)) =>
+ (case ((string_drop s23700 s23710)) of
+ s23720 =>
+ (case ((reg_name_matches_prefix s23720 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s23730)) =>
+ (let p00 = (string_drop s23720 s23730) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23680 :: " string "
+
+
+\<comment> \<open>\<open>val _s2359_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s2359 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s2359 s23600 = (
+ (let s23610 = s23600 in
+ if ((string_startswith s23610 (''c.jr''))) then
+ (case ((string_drop s23610 ((string_length (''c.jr''))))) of
+ s23620 =>
+ (case ((spc_matches_prefix0 s23620)) of
+ Some ((_, s23630)) =>
+ (case ((string_drop s23620 s23630)) of
+ s23640 =>
+ (case ((reg_name_matches_prefix s23640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s23650)) =>
+ (let p00 = (string_drop s23640 s23650) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23600 :: " string "
+
+
+\<comment> \<open>\<open>val _s2347_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2347 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2347 s23480 = (
+ (let s23490 = s23480 in
+ if ((string_startswith s23490 (''c.sdsp''))) then
+ (case ((string_drop s23490 ((string_length (''c.sdsp''))))) of
+ s23500 =>
+ (case ((spc_matches_prefix0 s23500)) of
+ Some ((_, s23510)) =>
+ (case ((string_drop s23500 s23510)) of
+ s23520 =>
+ (case ((reg_name_matches_prefix s23520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23530)) =>
+ (case ((string_drop s23520 s23530)) of
+ s23540 =>
+ (case ((sep_matches_prefix s23540)) of
+ Some ((_, s23550)) =>
+ (case ((string_drop s23540 s23550)) of
+ s23560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23560 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23570)) =>
+ (let p00 = (string_drop s23560 s23570) in
+ if (((p00 = ('''')))) then Some (rs2, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2335_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2335 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2335 s23360 = (
+ (let s23370 = s23360 in
+ if ((string_startswith s23370 (''c.swsp''))) then
+ (case ((string_drop s23370 ((string_length (''c.swsp''))))) of
+ s23380 =>
+ (case ((spc_matches_prefix0 s23380)) of
+ Some ((_, s23390)) =>
+ (case ((string_drop s23380 s23390)) of
+ s23400 =>
+ (case ((reg_name_matches_prefix s23400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23410)) =>
+ (case ((string_drop s23400 s23410)) of
+ s23420 =>
+ (case ((sep_matches_prefix s23420)) of
+ Some ((_, s23430)) =>
+ (case ((string_drop s23420 s23430)) of
+ s23440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23440 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23450)) =>
+ (let p00 = (string_drop s23440 s23450) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23360 :: " string "
+
+
+\<comment> \<open>\<open>val _s2323_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2323 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2323 s23240 = (
+ (let s23250 = s23240 in
+ if ((string_startswith s23250 (''c.ldsp''))) then
+ (case ((string_drop s23250 ((string_length (''c.ldsp''))))) of
+ s23260 =>
+ (case ((spc_matches_prefix0 s23260)) of
+ Some ((_, s23270)) =>
+ (case ((string_drop s23260 s23270)) of
+ s23280 =>
+ (case ((reg_name_matches_prefix s23280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23290)) =>
+ (case ((string_drop s23280 s23290)) of
+ s23300 =>
+ (case ((sep_matches_prefix s23300)) of
+ Some ((_, s23310)) =>
+ (case ((string_drop s23300 s23310)) of
+ s23320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23320 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23330)) =>
+ (let p00 = (string_drop s23320 s23330) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23240 :: " string "
+
+
+\<comment> \<open>\<open>val _s2311_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2311 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2311 s23120 = (
+ (let s23130 = s23120 in
+ if ((string_startswith s23130 (''c.lwsp''))) then
+ (case ((string_drop s23130 ((string_length (''c.lwsp''))))) of
+ s23140 =>
+ (case ((spc_matches_prefix0 s23140)) of
+ Some ((_, s23150)) =>
+ (case ((string_drop s23140 s23150)) of
+ s23160 =>
+ (case ((reg_name_matches_prefix s23160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23170)) =>
+ (case ((string_drop s23160 s23170)) of
+ s23180 =>
+ (case ((sep_matches_prefix s23180)) of
+ Some ((_, s23190)) =>
+ (case ((string_drop s23180 s23190)) of
+ s23200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23200 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23210)) =>
+ (let p00 = (string_drop s23200 s23210) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23120 :: " string "
+
+
+\<comment> \<open>\<open>val _s2299_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2299 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2299 s23000 = (
+ (let s23010 = s23000 in
+ if ((string_startswith s23010 (''c.slli''))) then
+ (case ((string_drop s23010 ((string_length (''c.slli''))))) of
+ s23020 =>
+ (case ((spc_matches_prefix0 s23020)) of
+ Some ((_, s23030)) =>
+ (case ((string_drop s23020 s23030)) of
+ s23040 =>
+ (case ((reg_name_matches_prefix s23040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s23050)) =>
+ (case ((string_drop s23040 s23050)) of
+ s23060 =>
+ (case ((sep_matches_prefix s23060)) of
+ Some ((_, s23070)) =>
+ (case ((string_drop s23060 s23070)) of
+ s23080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s23090)) =>
+ (let p00 = (string_drop s23080 s23090) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23000 :: " string "
+
+
+\<comment> \<open>\<open>val _s2287_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2287 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2287 s22880 = (
+ (let s22890 = s22880 in
+ if ((string_startswith s22890 (''c.bnez''))) then
+ (case ((string_drop s22890 ((string_length (''c.bnez''))))) of
+ s22900 =>
+ (case ((spc_matches_prefix0 s22900)) of
+ Some ((_, s22910)) =>
+ (case ((string_drop s22900 s22910)) of
+ s22920 =>
+ (case ((creg_name_matches_prefix s22920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s22930)) =>
+ (case ((string_drop s22920 s22930)) of
+ s22940 =>
+ (case ((sep_matches_prefix s22940)) of
+ Some ((_, s22950)) =>
+ (case ((string_drop s22940 s22950)) of
+ s22960 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22960 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s22970)) =>
+ (let p00 = (string_drop s22960 s22970) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2275_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2275 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2275 s22760 = (
+ (let s22770 = s22760 in
+ if ((string_startswith s22770 (''c.beqz''))) then
+ (case ((string_drop s22770 ((string_length (''c.beqz''))))) of
+ s22780 =>
+ (case ((spc_matches_prefix0 s22780)) of
+ Some ((_, s22790)) =>
+ (case ((string_drop s22780 s22790)) of
+ s22800 =>
+ (case ((creg_name_matches_prefix s22800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s22810)) =>
+ (case ((string_drop s22800 s22810)) of
+ s22820 =>
+ (case ((sep_matches_prefix s22820)) of
+ Some ((_, s22830)) =>
+ (case ((string_drop s22820 s22830)) of
+ s22840 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22840 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s22850)) =>
+ (let p00 = (string_drop s22840 s22850) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2267_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s2267 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s2267 s22680 = (
+ (let s22690 = s22680 in
+ if ((string_startswith s22690 (''c.j''))) then
+ (case ((string_drop s22690 ((string_length (''c.j''))))) of
+ s22700 =>
+ (case ((spc_matches_prefix0 s22700)) of
+ Some ((_, s22710)) =>
+ (case ((string_drop s22700 s22710)) of
+ s22720 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22720 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s22730)) =>
+ (let p00 = (string_drop s22720 s22730) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22680 :: " string "
+
+
+\<comment> \<open>\<open>val _s2255_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2255 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2255 s22560 = (
+ (let s22570 = s22560 in
+ if ((string_startswith s22570 (''c.addw''))) then
+ (case ((string_drop s22570 ((string_length (''c.addw''))))) of
+ s22580 =>
+ (case ((spc_matches_prefix0 s22580)) of
+ Some ((_, s22590)) =>
+ (case ((string_drop s22580 s22590)) of
+ s22600 =>
+ (case ((creg_name_matches_prefix s22600 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22610)) =>
+ (case ((string_drop s22600 s22610)) of
+ s22620 =>
+ (case ((sep_matches_prefix s22620)) of
+ Some ((_, s22630)) =>
+ (case ((string_drop s22620 s22630)) of
+ s22640 =>
+ (case ((creg_name_matches_prefix s22640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22650)) =>
+ (let p00 = (string_drop s22640 s22650) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22560 :: " string "
+
+
+\<comment> \<open>\<open>val _s2243_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2243 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2243 s22440 = (
+ (let s22450 = s22440 in
+ if ((string_startswith s22450 (''c.subw''))) then
+ (case ((string_drop s22450 ((string_length (''c.subw''))))) of
+ s22460 =>
+ (case ((spc_matches_prefix0 s22460)) of
+ Some ((_, s22470)) =>
+ (case ((string_drop s22460 s22470)) of
+ s22480 =>
+ (case ((creg_name_matches_prefix s22480 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22490)) =>
+ (case ((string_drop s22480 s22490)) of
+ s22500 =>
+ (case ((sep_matches_prefix s22500)) of
+ Some ((_, s22510)) =>
+ (case ((string_drop s22500 s22510)) of
+ s22520 =>
+ (case ((creg_name_matches_prefix s22520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22530)) =>
+ (let p00 = (string_drop s22520 s22530) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22440 :: " string "
+
+
+\<comment> \<open>\<open>val _s2231_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2231 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2231 s22320 = (
+ (let s22330 = s22320 in
+ if ((string_startswith s22330 (''c.and''))) then
+ (case ((string_drop s22330 ((string_length (''c.and''))))) of
+ s22340 =>
+ (case ((spc_matches_prefix0 s22340)) of
+ Some ((_, s22350)) =>
+ (case ((string_drop s22340 s22350)) of
+ s22360 =>
+ (case ((creg_name_matches_prefix s22360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22370)) =>
+ (case ((string_drop s22360 s22370)) of
+ s22380 =>
+ (case ((sep_matches_prefix s22380)) of
+ Some ((_, s22390)) =>
+ (case ((string_drop s22380 s22390)) of
+ s22400 =>
+ (case ((creg_name_matches_prefix s22400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22410)) =>
+ (let p00 = (string_drop s22400 s22410) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2219_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2219 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2219 s22200 = (
+ (let s22210 = s22200 in
+ if ((string_startswith s22210 (''c.or''))) then
+ (case ((string_drop s22210 ((string_length (''c.or''))))) of
+ s22220 =>
+ (case ((spc_matches_prefix0 s22220)) of
+ Some ((_, s22230)) =>
+ (case ((string_drop s22220 s22230)) of
+ s22240 =>
+ (case ((creg_name_matches_prefix s22240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22250)) =>
+ (case ((string_drop s22240 s22250)) of
+ s22260 =>
+ (case ((sep_matches_prefix s22260)) of
+ Some ((_, s22270)) =>
+ (case ((string_drop s22260 s22270)) of
+ s22280 =>
+ (case ((creg_name_matches_prefix s22280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22290)) =>
+ (let p00 = (string_drop s22280 s22290) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2207_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2207 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2207 s22080 = (
+ (let s22090 = s22080 in
+ if ((string_startswith s22090 (''c.xor''))) then
+ (case ((string_drop s22090 ((string_length (''c.xor''))))) of
+ s22100 =>
+ (case ((spc_matches_prefix0 s22100)) of
+ Some ((_, s22110)) =>
+ (case ((string_drop s22100 s22110)) of
+ s22120 =>
+ (case ((creg_name_matches_prefix s22120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22130)) =>
+ (case ((string_drop s22120 s22130)) of
+ s22140 =>
+ (case ((sep_matches_prefix s22140)) of
+ Some ((_, s22150)) =>
+ (case ((string_drop s22140 s22150)) of
+ s22160 =>
+ (case ((creg_name_matches_prefix s22160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22170)) =>
+ (let p00 = (string_drop s22160 s22170) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2195_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2195 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2195 s21960 = (
+ (let s21970 = s21960 in
+ if ((string_startswith s21970 (''c.sub''))) then
+ (case ((string_drop s21970 ((string_length (''c.sub''))))) of
+ s21980 =>
+ (case ((spc_matches_prefix0 s21980)) of
+ Some ((_, s21990)) =>
+ (case ((string_drop s21980 s21990)) of
+ s22000 =>
+ (case ((creg_name_matches_prefix s22000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22010)) =>
+ (case ((string_drop s22000 s22010)) of
+ s22020 =>
+ (case ((sep_matches_prefix s22020)) of
+ Some ((_, s22030)) =>
+ (case ((string_drop s22020 s22030)) of
+ s22040 =>
+ (case ((creg_name_matches_prefix s22040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22050)) =>
+ (let p00 = (string_drop s22040 s22050) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2183_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2183 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2183 s21840 = (
+ (let s21850 = s21840 in
+ if ((string_startswith s21850 (''c.andi''))) then
+ (case ((string_drop s21850 ((string_length (''c.andi''))))) of
+ s21860 =>
+ (case ((spc_matches_prefix0 s21860)) of
+ Some ((_, s21870)) =>
+ (case ((string_drop s21860 s21870)) of
+ s21880 =>
+ (case ((creg_name_matches_prefix s21880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21890)) =>
+ (case ((string_drop s21880 s21890)) of
+ s21900 =>
+ (case ((sep_matches_prefix s21900)) of
+ Some ((_, s21910)) =>
+ (case ((string_drop s21900 s21910)) of
+ s21920 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21920 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21930)) =>
+ (let p00 = (string_drop s21920 s21930) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21840 :: " string "
+
+
+\<comment> \<open>\<open>val _s2171_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2171 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2171 s21720 = (
+ (let s21730 = s21720 in
+ if ((string_startswith s21730 (''c.srai''))) then
+ (case ((string_drop s21730 ((string_length (''c.srai''))))) of
+ s21740 =>
+ (case ((spc_matches_prefix0 s21740)) of
+ Some ((_, s21750)) =>
+ (case ((string_drop s21740 s21750)) of
+ s21760 =>
+ (case ((creg_name_matches_prefix s21760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21770)) =>
+ (case ((string_drop s21760 s21770)) of
+ s21780 =>
+ (case ((sep_matches_prefix s21780)) of
+ Some ((_, s21790)) =>
+ (case ((string_drop s21780 s21790)) of
+ s21800 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21800 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s21810)) =>
+ (let p00 = (string_drop s21800 s21810) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21720 :: " string "
+
+
+\<comment> \<open>\<open>val _s2159_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2159 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2159 s21600 = (
+ (let s21610 = s21600 in
+ if ((string_startswith s21610 (''c.srli''))) then
+ (case ((string_drop s21610 ((string_length (''c.srli''))))) of
+ s21620 =>
+ (case ((spc_matches_prefix0 s21620)) of
+ Some ((_, s21630)) =>
+ (case ((string_drop s21620 s21630)) of
+ s21640 =>
+ (case ((creg_name_matches_prefix s21640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21650)) =>
+ (case ((string_drop s21640 s21650)) of
+ s21660 =>
+ (case ((sep_matches_prefix s21660)) of
+ Some ((_, s21670)) =>
+ (case ((string_drop s21660 s21670)) of
+ s21680 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21680 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s21690)) =>
+ (let p00 = (string_drop s21680 s21690) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21600 :: " string "
+
+
+\<comment> \<open>\<open>val _s2147_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2147 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2147 s21480 = (
+ (let s21490 = s21480 in
+ if ((string_startswith s21490 (''c.lui''))) then
+ (case ((string_drop s21490 ((string_length (''c.lui''))))) of
+ s21500 =>
+ (case ((spc_matches_prefix0 s21500)) of
+ Some ((_, s21510)) =>
+ (case ((string_drop s21500 s21510)) of
+ s21520 =>
+ (case ((reg_name_matches_prefix s21520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s21530)) =>
+ (case ((string_drop s21520 s21530)) of
+ s21540 =>
+ (case ((sep_matches_prefix s21540)) of
+ Some ((_, s21550)) =>
+ (case ((string_drop s21540 s21550)) of
+ s21560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21560 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21570)) =>
+ (let p00 = (string_drop s21560 s21570) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2139_ : string -> maybe (mword ty6)\<close>\<close>
+
+definition s2139 :: " string \<Rightarrow>((6)Word.word)option " where
+ " s2139 s21400 = (
+ (let s21410 = s21400 in
+ if ((string_startswith s21410 (''c.addi16sp''))) then
+ (case ((string_drop s21410 ((string_length (''c.addi16sp''))))) of
+ s21420 =>
+ (case ((spc_matches_prefix0 s21420)) of
+ Some ((_, s21430)) =>
+ (case ((string_drop s21420 s21430)) of
+ s21440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21440 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21450)) =>
+ (let p00 = (string_drop s21440 s21450) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21400 :: " string "
+
+
+\<comment> \<open>\<open>val _s2127_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2127 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2127 s21280 = (
+ (let s21290 = s21280 in
+ if ((string_startswith s21290 (''c.li''))) then
+ (case ((string_drop s21290 ((string_length (''c.li''))))) of
+ s21300 =>
+ (case ((spc_matches_prefix0 s21300)) of
+ Some ((_, s21310)) =>
+ (case ((string_drop s21300 s21310)) of
+ s21320 =>
+ (case ((reg_name_matches_prefix s21320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s21330)) =>
+ (case ((string_drop s21320 s21330)) of
+ s21340 =>
+ (case ((sep_matches_prefix s21340)) of
+ Some ((_, s21350)) =>
+ (case ((string_drop s21340 s21350)) of
+ s21360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21360 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21370)) =>
+ (let p00 = (string_drop s21360 s21370) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21280 :: " string "
+
+
+\<comment> \<open>\<open>val _s2115_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2115 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2115 s21160 = (
+ (let s21170 = s21160 in
+ if ((string_startswith s21170 (''c.addiw''))) then
+ (case ((string_drop s21170 ((string_length (''c.addiw''))))) of
+ s21180 =>
+ (case ((spc_matches_prefix0 s21180)) of
+ Some ((_, s21190)) =>
+ (case ((string_drop s21180 s21190)) of
+ s21200 =>
+ (case ((reg_name_matches_prefix s21200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s21210)) =>
+ (case ((string_drop s21200 s21210)) of
+ s21220 =>
+ (case ((sep_matches_prefix s21220)) of
+ Some ((_, s21230)) =>
+ (case ((string_drop s21220 s21230)) of
+ s21240 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21240 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21250)) =>
+ (let p00 = (string_drop s21240 s21250) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2107_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s2107 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s2107 s21080 = (
+ (let s21090 = s21080 in
+ if ((string_startswith s21090 (''c.jal''))) then
+ (case ((string_drop s21090 ((string_length (''c.jal''))))) of
+ s21100 =>
+ (case ((spc_matches_prefix0 s21100)) of
+ Some ((_, s21110)) =>
+ (case ((string_drop s21100 s21110)) of
+ s21120 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21120 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__814, s21130)) =>
+ if (((((subrange_vec_dec v__814 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__814
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__814
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let p00 = (string_drop s21120 s21130) in
+ if (((p00 = ('''')))) then Some imm else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2095_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2095 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2095 s20960 = (
+ (let s20970 = s20960 in
+ if ((string_startswith s20970 (''c.addi''))) then
+ (case ((string_drop s20970 ((string_length (''c.addi''))))) of
+ s20980 =>
+ (case ((spc_matches_prefix0 s20980)) of
+ Some ((_, s20990)) =>
+ (case ((string_drop s20980 s20990)) of
+ s21000 =>
+ (case ((reg_name_matches_prefix s21000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s21010)) =>
+ (case ((string_drop s21000 s21010)) of
+ s21020 =>
+ (case ((sep_matches_prefix s21020)) of
+ Some ((_, s21030)) =>
+ (case ((string_drop s21020 s21030)) of
+ s21040 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21040 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s21050)) =>
+ (let p00 = (string_drop s21040 s21050) in
+ if (((p00 = ('''')))) then Some (rsd, nzi) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2079_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2079 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2079 s20800 = (
+ (let s20810 = s20800 in
+ if ((string_startswith s20810 (''c.sd''))) then
+ (case ((string_drop s20810 ((string_length (''c.sd''))))) of
+ s20820 =>
+ (case ((spc_matches_prefix0 s20820)) of
+ Some ((_, s20830)) =>
+ (case ((string_drop s20820 s20830)) of
+ s20840 =>
+ (case ((creg_name_matches_prefix s20840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s20850)) =>
+ (case ((string_drop s20840 s20850)) of
+ s20860 =>
+ (case ((sep_matches_prefix s20860)) of
+ Some ((_, s20870)) =>
+ (case ((string_drop s20860 s20870)) of
+ s20880 =>
+ (case ((creg_name_matches_prefix s20880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s20890)) =>
+ (case ((string_drop s20880 s20890)) of
+ s20900 =>
+ (case ((sep_matches_prefix s20900)) of
+ Some ((_, s20910)) =>
+ (case ((string_drop s20900 s20910)) of
+ s20920 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20920 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__816, s20930)) =>
+ if (((((subrange_vec_dec v__816 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__816 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__816 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20920 s20930) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20800 :: " string "
+
+
+\<comment> \<open>\<open>val _s2063_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2063 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2063 s20640 = (
+ (let s20650 = s20640 in
+ if ((string_startswith s20650 (''c.sw''))) then
+ (case ((string_drop s20650 ((string_length (''c.sw''))))) of
+ s20660 =>
+ (case ((spc_matches_prefix0 s20660)) of
+ Some ((_, s20670)) =>
+ (case ((string_drop s20660 s20670)) of
+ s20680 =>
+ (case ((creg_name_matches_prefix s20680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s20690)) =>
+ (case ((string_drop s20680 s20690)) of
+ s20700 =>
+ (case ((sep_matches_prefix s20700)) of
+ Some ((_, s20710)) =>
+ (case ((string_drop s20700 s20710)) of
+ s20720 =>
+ (case ((creg_name_matches_prefix s20720 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s20730)) =>
+ (case ((string_drop s20720 s20730)) of
+ s20740 =>
+ (case ((sep_matches_prefix s20740)) of
+ Some ((_, s20750)) =>
+ (case ((string_drop s20740 s20750)) of
+ s20760 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20760 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__818, s20770)) =>
+ if (((((subrange_vec_dec v__818 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__818 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__818 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20760 s20770) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20640 :: " string "
+
+
+\<comment> \<open>\<open>val _s2047_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2047 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2047 s20480 = (
+ (let s20490 = s20480 in
+ if ((string_startswith s20490 (''c.ld''))) then
+ (case ((string_drop s20490 ((string_length (''c.ld''))))) of
+ s20500 =>
+ (case ((spc_matches_prefix0 s20500)) of
+ Some ((_, s20510)) =>
+ (case ((string_drop s20500 s20510)) of
+ s20520 =>
+ (case ((creg_name_matches_prefix s20520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20530)) =>
+ (case ((string_drop s20520 s20530)) of
+ s20540 =>
+ (case ((sep_matches_prefix s20540)) of
+ Some ((_, s20550)) =>
+ (case ((string_drop s20540 s20550)) of
+ s20560 =>
+ (case ((creg_name_matches_prefix s20560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s20570)) =>
+ (case ((string_drop s20560 s20570)) of
+ s20580 =>
+ (case ((sep_matches_prefix s20580)) of
+ Some ((_, s20590)) =>
+ (case ((string_drop s20580 s20590)) of
+ s20600 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20600 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__820, s20610)) =>
+ if (((((subrange_vec_dec v__820 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__820 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__820 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20600 s20610) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2031_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2031 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2031 s20320 = (
+ (let s20330 = s20320 in
+ if ((string_startswith s20330 (''c.lw''))) then
+ (case ((string_drop s20330 ((string_length (''c.lw''))))) of
+ s20340 =>
+ (case ((spc_matches_prefix0 s20340)) of
+ Some ((_, s20350)) =>
+ (case ((string_drop s20340 s20350)) of
+ s20360 =>
+ (case ((creg_name_matches_prefix s20360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20370)) =>
+ (case ((string_drop s20360 s20370)) of
+ s20380 =>
+ (case ((sep_matches_prefix s20380)) of
+ Some ((_, s20390)) =>
+ (case ((string_drop s20380 s20390)) of
+ s20400 =>
+ (case ((creg_name_matches_prefix s20400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s20410)) =>
+ (case ((string_drop s20400 s20410)) of
+ s20420 =>
+ (case ((sep_matches_prefix s20420)) of
+ Some ((_, s20430)) =>
+ (case ((string_drop s20420 s20430)) of
+ s20440 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20440 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__822, s20450)) =>
+ if (((((subrange_vec_dec v__822 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__822 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__822 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20440 s20450) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2019_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2019 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2019 s20200 = (
+ (let s20210 = s20200 in
+ if ((string_startswith s20210 (''c.addi4spn''))) then
+ (case ((string_drop s20210 ((string_length (''c.addi4spn''))))) of
+ s20220 =>
+ (case ((spc_matches_prefix0 s20220)) of
+ Some ((_, s20230)) =>
+ (case ((string_drop s20220 s20230)) of
+ s20240 =>
+ (case ((creg_name_matches_prefix s20240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20250)) =>
+ (case ((string_drop s20240 s20250)) of
+ s20260 =>
+ (case ((sep_matches_prefix s20260)) of
+ Some ((_, s20270)) =>
+ (case ((string_drop s20260 s20270)) of
+ s20280 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20280 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__824, s20290)) =>
+ if (((((subrange_vec_dec v__824 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__824 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__824 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let p00 = (string_drop s20280 s20290) in
+ if (((p00 = ('''')))) then Some (rdc, nzimm) else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20200 :: " string "
+
+
+\<comment> \<open>\<open>val _s1995_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1995 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1995 s19970 = (
+ (case ((amo_mnemonic_matches_prefix s19970)) of
+ Some ((op1, s19980)) =>
+ (let s19990 = (string_drop s19970 s19980) in
+ if ((string_startswith s19990 (''.''))) then
+ (case ((string_drop s19990 ((string_length (''.''))))) of
+ s20000 =>
+ (case ((size_mnemonic_matches_prefix s20000)) of
+ Some ((width, s20010)) =>
+ (case ((string_drop s20000 s20010)) of
+ s20020 =>
+ (case ((maybe_aq_matches_prefix s20020)) of
+ Some ((aq, s20030)) =>
+ (case ((string_drop s20020 s20030)) of
+ s20040 =>
+ (case ((maybe_rl_matches_prefix s20040)) of
+ Some ((rl, s20050)) =>
+ (case ((string_drop s20040 s20050)) of
+ s20060 =>
+ (case ((spc_matches_prefix0 s20060)) of
+ Some ((_, s20070)) =>
+ (case ((string_drop s20060 s20070)) of
+ s20080 =>
+ (case ((reg_name_matches_prefix s20080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s20090)) =>
+ (case ((string_drop s20080 s20090)) of
+ s20100 =>
+ (case ((sep_matches_prefix s20100)) of
+ Some ((_, s20110)) =>
+ (case ((string_drop s20100 s20110)) of
+ s20120 =>
+ (case ((reg_name_matches_prefix s20120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s20130)) =>
+ (case ((string_drop s20120 s20130)) of
+ s20140 =>
+ (case ((sep_matches_prefix s20140)) of
+ Some ((_, s20150)) =>
+ (case ((string_drop s20140 s20150)) of
+ s20160 =>
+ (case ((reg_name_matches_prefix s20160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s20170)) =>
+ (let p00 = (string_drop s20160 s20170) in
+ if (((p00 = ('''')))) then Some (op1, width, aq, rl, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s19970 :: " string "
+
+
+\<comment> \<open>\<open>val _s1973_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1973 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1973 s19740 = (
+ (let s19750 = s19740 in
+ if ((string_startswith s19750 (''sc.''))) then
+ (case ((string_drop s19750 ((string_length (''sc.''))))) of
+ s19760 =>
+ (case ((size_mnemonic_matches_prefix s19760)) of
+ Some ((size1, s19770)) =>
+ (case ((string_drop s19760 s19770)) of
+ s19780 =>
+ (case ((maybe_aq_matches_prefix s19780)) of
+ Some ((aq, s19790)) =>
+ (case ((string_drop s19780 s19790)) of
+ s19800 =>
+ (case ((maybe_rl_matches_prefix s19800)) of
+ Some ((rl, s19810)) =>
+ (case ((string_drop s19800 s19810)) of
+ s19820 =>
+ (case ((spc_matches_prefix0 s19820)) of
+ Some ((_, s19830)) =>
+ (case ((string_drop s19820 s19830)) of
+ s19840 =>
+ (case ((reg_name_matches_prefix s19840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19850)) =>
+ (case ((string_drop s19840 s19850)) of
+ s19860 =>
+ (case ((sep_matches_prefix s19860)) of
+ Some ((_, s19870)) =>
+ (case ((string_drop s19860 s19870)) of
+ s19880 =>
+ (case ((reg_name_matches_prefix s19880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19890)) =>
+ (case ((string_drop s19880 s19890)) of
+ s19900 =>
+ (case ((sep_matches_prefix s19900)) of
+ Some ((_, s19910)) =>
+ (case ((string_drop s19900 s19910)) of
+ s19920 =>
+ (case ((reg_name_matches_prefix s19920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19930)) =>
+ (let p00 = (string_drop s19920 s19930) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19740 :: " string "
+
+
+\<comment> \<open>\<open>val _s1955_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1955 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word)option " where
+ " s1955 s19560 = (
+ (let s19570 = s19560 in
+ if ((string_startswith s19570 (''lr.''))) then
+ (case ((string_drop s19570 ((string_length (''lr.''))))) of
+ s19580 =>
+ (case ((size_mnemonic_matches_prefix s19580)) of
+ Some ((size1, s19590)) =>
+ (case ((string_drop s19580 s19590)) of
+ s19600 =>
+ (case ((maybe_aq_matches_prefix s19600)) of
+ Some ((aq, s19610)) =>
+ (case ((string_drop s19600 s19610)) of
+ s19620 =>
+ (case ((maybe_rl_matches_prefix s19620)) of
+ Some ((rl, s19630)) =>
+ (case ((string_drop s19620 s19630)) of
+ s19640 =>
+ (case ((spc_matches_prefix0 s19640)) of
+ Some ((_, s19650)) =>
+ (case ((string_drop s19640 s19650)) of
+ s19660 =>
+ (case ((reg_name_matches_prefix s19660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19670)) =>
+ (case ((string_drop s19660 s19670)) of
+ s19680 =>
+ (case ((sep_matches_prefix s19680)) of
+ Some ((_, s19690)) =>
+ (case ((string_drop s19680 s19690)) of
+ s19700 =>
+ (case ((reg_name_matches_prefix s19700 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19710)) =>
+ (let p00 = (string_drop s19700 s19710) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19560 :: " string "
+
+
+\<comment> \<open>\<open>val _s1943_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1943 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1943 s19440 = (
+ (let s19450 = s19440 in
+ if ((string_startswith s19450 (''sfence.vma''))) then
+ (case ((string_drop s19450 ((string_length (''sfence.vma''))))) of
+ s19460 =>
+ (case ((spc_matches_prefix0 s19460)) of
+ Some ((_, s19470)) =>
+ (case ((string_drop s19460 s19470)) of
+ s19480 =>
+ (case ((reg_name_matches_prefix s19480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19490)) =>
+ (case ((string_drop s19480 s19490)) of
+ s19500 =>
+ (case ((sep_matches_prefix s19500)) of
+ Some ((_, s19510)) =>
+ (case ((string_drop s19500 s19510)) of
+ s19520 =>
+ (case ((reg_name_matches_prefix s19520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19530)) =>
+ (let p00 = (string_drop s19520 s19530) in
+ if (((p00 = ('''')))) then Some (rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19440 :: " string "
+
+
+\<comment> \<open>\<open>val _s1931_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1931 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1931 s19320 = (
+ (let s19330 = s19320 in
+ if ((string_startswith s19330 (''fence.tso''))) then
+ (case ((string_drop s19330 ((string_length (''fence.tso''))))) of
+ s19340 =>
+ (case ((spc_matches_prefix0 s19340)) of
+ Some ((_, s19350)) =>
+ (case ((string_drop s19340 s19350)) of
+ s19360 =>
+ (case ((fence_bits_matches_prefix s19360 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s19370)) =>
+ (case ((string_drop s19360 s19370)) of
+ s19380 =>
+ (case ((sep_matches_prefix s19380)) of
+ Some ((_, s19390)) =>
+ (case ((string_drop s19380 s19390)) of
+ s19400 =>
+ (case ((fence_bits_matches_prefix s19400 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s19410)) =>
+ (let p00 = (string_drop s19400 s19410) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19320 :: " string "
+
+
+\<comment> \<open>\<open>val _s1919_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1919 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1919 s19200 = (
+ (let s19210 = s19200 in
+ if ((string_startswith s19210 (''fence''))) then
+ (case ((string_drop s19210 ((string_length (''fence''))))) of
+ s19220 =>
+ (case ((spc_matches_prefix0 s19220)) of
+ Some ((_, s19230)) =>
+ (case ((string_drop s19220 s19230)) of
+ s19240 =>
+ (case ((fence_bits_matches_prefix s19240 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s19250)) =>
+ (case ((string_drop s19240 s19250)) of
+ s19260 =>
+ (case ((sep_matches_prefix s19260)) of
+ Some ((_, s19270)) =>
+ (case ((string_drop s19260 s19270)) of
+ s19280 =>
+ (case ((fence_bits_matches_prefix s19280 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s19290)) =>
+ (let p00 = (string_drop s19280 s19290) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19200 :: " string "
+
+
+\<comment> \<open>\<open>val _s1902_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1902 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1902 s19040 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s19040)) of
+ Some ((op1, s19050)) =>
+ (case ((string_drop s19040 s19050)) of
+ s19060 =>
+ (case ((spc_matches_prefix0 s19060)) of
+ Some ((_, s19070)) =>
+ (case ((string_drop s19060 s19070)) of
+ s19080 =>
+ (case ((reg_name_matches_prefix s19080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19090)) =>
+ (case ((string_drop s19080 s19090)) of
+ s19100 =>
+ (case ((sep_matches_prefix s19100)) of
+ Some ((_, s19110)) =>
+ (case ((string_drop s19100 s19110)) of
+ s19120 =>
+ (case ((reg_name_matches_prefix s19120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19130)) =>
+ (case ((string_drop s19120 s19130)) of
+ s19140 =>
+ (case ((sep_matches_prefix s19140)) of
+ Some ((_, s19150)) =>
+ (case ((string_drop s19140 s19150)) of
+ s19160 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s19160 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s19170)) =>
+ (let p00 = (string_drop s19160 s19170) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s19040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1885_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1885 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1885 s18870 = (
+ (case ((rtypew_mnemonic_matches_prefix s18870)) of
+ Some ((op1, s18880)) =>
+ (case ((string_drop s18870 s18880)) of
+ s18890 =>
+ (case ((spc_matches_prefix0 s18890)) of
+ Some ((_, s18900)) =>
+ (case ((string_drop s18890 s18900)) of
+ s18910 =>
+ (case ((reg_name_matches_prefix s18910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18920)) =>
+ (case ((string_drop s18910 s18920)) of
+ s18930 =>
+ (case ((sep_matches_prefix s18930)) of
+ Some ((_, s18940)) =>
+ (case ((string_drop s18930 s18940)) of
+ s18950 =>
+ (case ((reg_name_matches_prefix s18950 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18960)) =>
+ (case ((string_drop s18950 s18960)) of
+ s18970 =>
+ (case ((sep_matches_prefix s18970)) of
+ Some ((_, s18980)) =>
+ (case ((string_drop s18970 s18980)) of
+ s18990 =>
+ (case ((reg_name_matches_prefix s18990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19000)) =>
+ (let p00 = (string_drop s18990 s19000) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s18870 :: " string "
+
+
+\<comment> \<open>\<open>val _s1868_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1868 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1868 s18700 = (
+ (case ((shiftw_mnemonic_matches_prefix s18700)) of
+ Some ((op1, s18710)) =>
+ (case ((string_drop s18700 s18710)) of
+ s18720 =>
+ (case ((spc_matches_prefix0 s18720)) of
+ Some ((_, s18730)) =>
+ (case ((string_drop s18720 s18730)) of
+ s18740 =>
+ (case ((reg_name_matches_prefix s18740 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18750)) =>
+ (case ((string_drop s18740 s18750)) of
+ s18760 =>
+ (case ((sep_matches_prefix s18760)) of
+ Some ((_, s18770)) =>
+ (case ((string_drop s18760 s18770)) of
+ s18780 =>
+ (case ((reg_name_matches_prefix s18780 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18790)) =>
+ (case ((string_drop s18780 s18790)) of
+ s18800 =>
+ (case ((sep_matches_prefix s18800)) of
+ Some ((_, s18810)) =>
+ (case ((string_drop s18800 s18810)) of
+ s18820 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18820 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s18830)) =>
+ (let p00 = (string_drop s18820 s18830) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s18700 :: " string "
+
+
+\<comment> \<open>\<open>val _s1852_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1852 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1852 s18530 = (
+ (let s18540 = s18530 in
+ if ((string_startswith s18540 (''addiw''))) then
+ (case ((string_drop s18540 ((string_length (''addiw''))))) of
+ s18550 =>
+ (case ((spc_matches_prefix0 s18550)) of
+ Some ((_, s18560)) =>
+ (case ((string_drop s18550 s18560)) of
+ s18570 =>
+ (case ((reg_name_matches_prefix s18570 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18580)) =>
+ (case ((string_drop s18570 s18580)) of
+ s18590 =>
+ (case ((sep_matches_prefix s18590)) of
+ Some ((_, s18600)) =>
+ (case ((string_drop s18590 s18600)) of
+ s18610 =>
+ (case ((reg_name_matches_prefix s18610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18620)) =>
+ (case ((string_drop s18610 s18620)) of
+ s18630 =>
+ (case ((sep_matches_prefix s18630)) of
+ Some ((_, s18640)) =>
+ (case ((string_drop s18630 s18640)) of
+ s18650 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18650 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18660)) =>
+ (let p00 = (string_drop s18650 s18660) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s18530 :: " string "
+
+
+\<comment> \<open>\<open>val _s1824_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s1824 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s1824 s18250 = (
+ (let s18260 = s18250 in
+ if ((string_startswith s18260 (''s''))) then
+ (case ((string_drop s18260 ((string_length (''s''))))) of
+ s18270 =>
+ (case ((size_mnemonic_matches_prefix s18270)) of
+ Some ((size1, s18280)) =>
+ (case ((string_drop s18270 s18280)) of
+ s18290 =>
+ (case ((maybe_aq_matches_prefix s18290)) of
+ Some ((aq, s18300)) =>
+ (case ((string_drop s18290 s18300)) of
+ s18310 =>
+ (case ((maybe_rl_matches_prefix s18310)) of
+ Some ((rl, s18320)) =>
+ (case ((string_drop s18310 s18320)) of
+ s18330 =>
+ (case ((spc_matches_prefix0 s18330)) of
+ Some ((_, s18340)) =>
+ (case ((string_drop s18330 s18340)) of
+ s18350 =>
+ (case ((reg_name_matches_prefix s18350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s18360)) =>
+ (case ((string_drop s18350 s18360)) of
+ s18370 =>
+ (case ((sep_matches_prefix s18370)) of
+ Some ((_, s18380)) =>
+ (case ((string_drop s18370 s18380)) of
+ s18390 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18390 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18400)) =>
+ (case ((string_drop s18390 s18400)) of
+ s18410 =>
+ (case ((opt_spc_matches_prefix0 s18410)) of
+ Some ((_, s18420)) =>
+ (let s18430 = (string_drop s18410 s18420) in
+ if ((string_startswith s18430 (''(''))) then
+ (case ((string_drop s18430 ((string_length (''(''))))) of
+ s18440 =>
+ (case ((opt_spc_matches_prefix0 s18440)) of
+ Some ((_, s18450)) =>
+ (case ((string_drop s18440 s18450)) of
+ s18460 =>
+ (case ((reg_name_matches_prefix s18460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18470)) =>
+ (case ((string_drop s18460 s18470)) of
+ s18480 =>
+ (case ((opt_spc_matches_prefix0 s18480)) of
+ Some ((_, s18490)) =>
+ (let s18500 = (string_drop s18480 s18490) in
+ if ((string_startswith s18500 ('')''))) then
+ (let p00 = (string_drop s18500 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rs2, imm, rs1) else
+ None) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s18250 :: " string "
+
+
+\<comment> \<open>\<open>val _s1794_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s1794 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s1794 s17950 = (
+ (let s17960 = s17950 in
+ if ((string_startswith s17960 (''l''))) then
+ (case ((string_drop s17960 ((string_length (''l''))))) of
+ s17970 =>
+ (case ((size_mnemonic_matches_prefix s17970)) of
+ Some ((size1, s17980)) =>
+ (case ((string_drop s17970 s17980)) of
+ s17990 =>
+ (case ((maybe_u_matches_prefix s17990)) of
+ Some ((is_unsigned, s18000)) =>
+ (case ((string_drop s17990 s18000)) of
+ s18010 =>
+ (case ((maybe_aq_matches_prefix s18010)) of
+ Some ((aq, s18020)) =>
+ (case ((string_drop s18010 s18020)) of
+ s18030 =>
+ (case ((maybe_rl_matches_prefix s18030)) of
+ Some ((rl, s18040)) =>
+ (case ((string_drop s18030 s18040)) of
+ s18050 =>
+ (case ((spc_matches_prefix0 s18050)) of
+ Some ((_, s18060)) =>
+ (case ((string_drop s18050 s18060)) of
+ s18070 =>
+ (case ((reg_name_matches_prefix s18070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18080)) =>
+ (case ((string_drop s18070 s18080)) of
+ s18090 =>
+ (case ((sep_matches_prefix s18090)) of
+ Some ((_, s18100)) =>
+ (case ((string_drop s18090 s18100)) of
+ s18110 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18110 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18120)) =>
+ (case ((string_drop s18110 s18120)) of
+ s18130 =>
+ (case ((opt_spc_matches_prefix0 s18130)) of
+ Some ((_, s18140)) =>
+ (let s18150 = (string_drop s18130 s18140) in
+ if ((string_startswith s18150 (''(''))) then
+ (case ((string_drop s18150 ((string_length (''(''))))) of
+ s18160 =>
+ (case ((opt_spc_matches_prefix0 s18160)) of
+ Some ((_, s18170)) =>
+ (case ((string_drop s18160 s18170)) of
+ s18180 =>
+ (case ((reg_name_matches_prefix s18180 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18190)) =>
+ (case ((string_drop s18180 s18190)) of
+ s18200 =>
+ (case ((opt_spc_matches_prefix0 s18200)) of
+ Some ((_, s18210)) =>
+ (let s18220 = (string_drop s18200 s18210) in
+ if ((string_startswith s18220 ('')''))) then
+ (let p00 = (string_drop s18220 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1) else None) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s17950 :: " string "
+
+
+\<comment> \<open>\<open>val _s1777_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1777 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1777 s17790 = (
+ (case ((rtype_mnemonic_matches_prefix s17790)) of
+ Some ((op1, s17800)) =>
+ (case ((string_drop s17790 s17800)) of
+ s17810 =>
+ (case ((spc_matches_prefix0 s17810)) of
+ Some ((_, s17820)) =>
+ (case ((string_drop s17810 s17820)) of
+ s17830 =>
+ (case ((reg_name_matches_prefix s17830 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17840)) =>
+ (case ((string_drop s17830 s17840)) of
+ s17850 =>
+ (case ((sep_matches_prefix s17850)) of
+ Some ((_, s17860)) =>
+ (case ((string_drop s17850 s17860)) of
+ s17870 =>
+ (case ((reg_name_matches_prefix s17870 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17880)) =>
+ (case ((string_drop s17870 s17880)) of
+ s17890 =>
+ (case ((sep_matches_prefix s17890)) of
+ Some ((_, s17900)) =>
+ (case ((string_drop s17890 s17900)) of
+ s17910 =>
+ (case ((reg_name_matches_prefix s17910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s17920)) =>
+ (let p00 = (string_drop s17910 s17920) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17790 :: " string "
+
+
+\<comment> \<open>\<open>val _s1760_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))\<close>\<close>
+
+definition s1760 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word)option " where
+ " s1760 s17620 = (
+ (case ((shiftiop_mnemonic_matches_prefix s17620)) of
+ Some ((op1, s17630)) =>
+ (case ((string_drop s17620 s17630)) of
+ s17640 =>
+ (case ((spc_matches_prefix0 s17640)) of
+ Some ((_, s17650)) =>
+ (case ((string_drop s17640 s17650)) of
+ s17660 =>
+ (case ((reg_name_matches_prefix s17660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17670)) =>
+ (case ((string_drop s17660 s17670)) of
+ s17680 =>
+ (case ((sep_matches_prefix s17680)) of
+ Some ((_, s17690)) =>
+ (case ((string_drop s17680 s17690)) of
+ s17700 =>
+ (case ((reg_name_matches_prefix s17700 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17710)) =>
+ (case ((string_drop s17700 s17710)) of
+ s17720 =>
+ (case ((sep_matches_prefix s17720)) of
+ Some ((_, s17730)) =>
+ (case ((string_drop s17720 s17730)) of
+ s17740 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17740 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s17750)) =>
+ (let p00 = (string_drop s17740 s17750) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17620 :: " string "
+
+
+\<comment> \<open>\<open>val _s1743_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1743 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1743 s17450 = (
+ (case ((itype_mnemonic_matches_prefix s17450)) of
+ Some ((op1, s17460)) =>
+ (case ((string_drop s17450 s17460)) of
+ s17470 =>
+ (case ((spc_matches_prefix0 s17470)) of
+ Some ((_, s17480)) =>
+ (case ((string_drop s17470 s17480)) of
+ s17490 =>
+ (case ((reg_name_matches_prefix s17490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17500)) =>
+ (case ((string_drop s17490 s17500)) of
+ s17510 =>
+ (case ((sep_matches_prefix s17510)) of
+ Some ((_, s17520)) =>
+ (case ((string_drop s17510 s17520)) of
+ s17530 =>
+ (case ((reg_name_matches_prefix s17530 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17540)) =>
+ (case ((string_drop s17530 s17540)) of
+ s17550 =>
+ (case ((sep_matches_prefix s17550)) of
+ Some ((_, s17560)) =>
+ (case ((string_drop s17550 s17560)) of
+ s17570 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17570 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s17580)) =>
+ (let p00 = (string_drop s17570 s17580) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17450 :: " string "
+
+
+\<comment> \<open>\<open>val _s1726_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))\<close>\<close>
+
+definition s1726 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word)option " where
+ " s1726 s17280 = (
+ (case ((btype_mnemonic_matches_prefix s17280)) of
+ Some ((op1, s17290)) =>
+ (case ((string_drop s17280 s17290)) of
+ s17300 =>
+ (case ((spc_matches_prefix0 s17300)) of
+ Some ((_, s17310)) =>
+ (case ((string_drop s17300 s17310)) of
+ s17320 =>
+ (case ((reg_name_matches_prefix s17320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17330)) =>
+ (case ((string_drop s17320 s17330)) of
+ s17340 =>
+ (case ((sep_matches_prefix s17340)) of
+ Some ((_, s17350)) =>
+ (case ((string_drop s17340 s17350)) of
+ s17360 =>
+ (case ((reg_name_matches_prefix s17360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s17370)) =>
+ (case ((string_drop s17360 s17370)) of
+ s17380 =>
+ (case ((sep_matches_prefix s17380)) of
+ Some ((_, s17390)) =>
+ (case ((string_drop s17380 s17390)) of
+ s17400 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17400 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s17410)) =>
+ (let p00 = (string_drop s17400 s17410) in
+ if (((p00 = ('''')))) then Some (op1, rs1, rs2, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17280 :: " string "
+
+
+\<comment> \<open>\<open>val _s1710_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1710 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1710 s17110 = (
+ (let s17120 = s17110 in
+ if ((string_startswith s17120 (''jalr''))) then
+ (case ((string_drop s17120 ((string_length (''jalr''))))) of
+ s17130 =>
+ (case ((spc_matches_prefix0 s17130)) of
+ Some ((_, s17140)) =>
+ (case ((string_drop s17130 s17140)) of
+ s17150 =>
+ (case ((reg_name_matches_prefix s17150 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17160)) =>
+ (case ((string_drop s17150 s17160)) of
+ s17170 =>
+ (case ((sep_matches_prefix s17170)) of
+ Some ((_, s17180)) =>
+ (case ((string_drop s17170 s17180)) of
+ s17190 =>
+ (case ((reg_name_matches_prefix s17190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17200)) =>
+ (case ((string_drop s17190 s17200)) of
+ s17210 =>
+ (case ((sep_matches_prefix s17210)) of
+ Some ((_, s17220)) =>
+ (case ((string_drop s17210 s17220)) of
+ s17230 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17230 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s17240)) =>
+ (let p00 = (string_drop s17230 s17240) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s17110 :: " string "
+
+
+\<comment> \<open>\<open>val _s1698_ : string -> maybe ((mword ty5 * mword ty21))\<close>\<close>
+
+definition s1698 :: " string \<Rightarrow>((5)Word.word*(21)Word.word)option " where
+ " s1698 s16990 = (
+ (let s17000 = s16990 in
+ if ((string_startswith s17000 (''jal''))) then
+ (case ((string_drop s17000 ((string_length (''jal''))))) of
+ s17010 =>
+ (case ((spc_matches_prefix0 s17010)) of
+ Some ((_, s17020)) =>
+ (case ((string_drop s17010 s17020)) of
+ s17030 =>
+ (case ((reg_name_matches_prefix s17030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17040)) =>
+ (case ((string_drop s17030 s17040)) of
+ s17050 =>
+ (case ((sep_matches_prefix s17050)) of
+ Some ((_, s17060)) =>
+ (case ((string_drop s17050 s17060)) of
+ s17070 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17070 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s17080)) =>
+ (let p00 = (string_drop s17070 s17080) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16990 :: " string "
+
+
+\<comment> \<open>\<open>val _s1685_ : string -> maybe ((uop * mword ty5 * mword ty20))\<close>\<close>
+
+definition s1685 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word)option " where
+ " s1685 s16870 = (
+ (case ((utype_mnemonic_matches_prefix s16870)) of
+ Some ((op1, s16880)) =>
+ (case ((string_drop s16870 s16880)) of
+ s16890 =>
+ (case ((spc_matches_prefix0 s16890)) of
+ Some ((_, s16900)) =>
+ (case ((string_drop s16890 s16900)) of
+ s16910 =>
+ (case ((reg_name_matches_prefix s16910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16920)) =>
+ (case ((string_drop s16910 s16920)) of
+ s16930 =>
+ (case ((sep_matches_prefix s16930)) of
+ Some ((_, s16940)) =>
+ (case ((string_drop s16930 s16940)) of
+ s16950 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16950 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s16960)) =>
+ (let p00 = (string_drop s16950 s16960) in
+ if (((p00 = ('''')))) then Some (op1, rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s16870 :: " string "
+
+
+definition assembly_backwards_matches :: " string \<Rightarrow> bool " where
+ " assembly_backwards_matches arg1 = (
+ (let s16970 = arg1 in
+ if ((case ((s1685 s16970 :: ((uop * 5 Word.word * 20 Word.word))option)) of
+ Some ((op1, rd, imm)) => True
+ | _ => False
+ )) then (case (s1685 s16970 :: (( uop * 5 Word.word * 20 Word.word)) option) of
+ (Some ((op1, rd, imm))) =>
+ True
+ )
+ else if ((case ((s1698 s16970 :: (( 5 Word.word * 21 Word.word))option)) of
+ Some ((rd, imm)) => True
+ | _ => False
+ )) then (case (s1698 s16970 :: (( 5 Word.word * 21 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s1710 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => True
+ | _ => False
+ )) then (case (s1710 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1726 s16970 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word))option)) of
+ Some ((op1, rs1, rs2, imm)) => True
+ | _ => False
+ )) then (case
+ (s1726 s16970 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word)) option) of
+ (Some ((op1, rs1, rs2, imm))) =>
+ True
+ )
+ else if ((case ((s1743 s16970 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, imm)) => True
+ | _ => False
+ )) then (case
+ (s1743 s16970 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1760 s16970 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => True
+ | _ => False
+ )) then (case
+ (s1760 s16970 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1777 s16970 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1777 s16970 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1794 s16970
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1794 s16970
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ True
+ )
+ else if ((case ((s1824 s16970
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1824 s16970 :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1))) =>
+ True
+ )
+ else if ((case ((s1852 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1852 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1868 s16970 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1868 s16970 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1885 s16970 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1885 s16970 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1902 s16970 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1902 s16970 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1919 s16970 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1919 s16970 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ True
+ )
+ else if ((case ((s1931 s16970 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1931 s16970 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ True
+ )
+ else if (((s16970 = (''fence.i'')))) then True
+ else if (((s16970 = (''ecall'')))) then True
+ else if (((s16970 = (''mret'')))) then True
+ else if (((s16970 = (''sret'')))) then True
+ else if (((s16970 = (''ebreak'')))) then True
+ else if (((s16970 = (''wfi'')))) then True
+ else if ((case ((s1943 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rs1, rs2)) => True
+ | _ => False
+ )) then (case (s1943 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1955 s16970 :: ((word_width * bool * bool * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1955 s16970 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1))) =>
+ True
+ )
+ else if ((case ((s1973 s16970
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1973 s16970 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1995 s16970
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1995 s16970
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2))) =>
+ True
+ )
+ else if (((s16970 = (''c.nop'')))) then True
+ else if ((case ((s2019 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rdc, nzimm)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s2019 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rdc, nzimm))) =>
+ True
+ )
+ else if ((case ((s2031 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => True
+ | _ => False
+ )) then (case
+ (s2031 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ True
+ )
+ else if ((case ((s2047 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2047 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ True
+ )
+ else if ((case ((s2063 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => True
+ | _ => False
+ )) then (case
+ (s2063 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ True
+ )
+ else if ((case ((s2079 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2079 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ True
+ )
+ else if ((case ((s2095 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, nzi)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2095 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, nzi))) =>
+ True
+ )
+ else if ((case ((s2107 s16970 :: ( 11 Word.word)option)) of
+ Some (imm) => ((( 32 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s2107 s16970 :: ( 11 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2115 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2115 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ True
+ )
+ else if ((case ((s2127 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2127 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s2139 s16970 :: ( 6 Word.word)option)) of
+ Some (imm) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2139 s16970 :: ( 6 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2147 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s2147 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s2159 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2159 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2171 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2171 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2183 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => True
+ | _ => False
+ )) then (case (s2183 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ True
+ )
+ else if ((case ((s2195 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2195 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2207 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2207 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2219 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2219 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2231 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2231 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2243 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2243 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2255 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2255 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2267 s16970 :: ( 11 Word.word)option)) of
+ Some (imm) => True
+ | _ => False
+ )) then (case (s2267 s16970 :: ( 11 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2275 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s2275 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ True
+ )
+ else if ((case ((s2287 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s2287 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ True
+ )
+ else if ((case ((s2299 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2299 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2311 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2311 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2323 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s2323 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2335 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => True
+ | _ => False
+ )) then (case (s2335 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2347 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rs2, uimm)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2347 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rs2, uimm))) =>
+ True
+ )
+ else if ((case ((s2359 s16970 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2359 s16970 :: ( 5 Word.word) option) of (Some (rs1)) => True )
+ else if ((case ((s2367 s16970 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2367 s16970 :: ( 5 Word.word) option) of (Some (rs1)) => True )
+ else if ((case ((s2375 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2375 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs2))) =>
+ True
+ )
+ else if (((s16970 = (''c.ebreak'')))) then True
+ else if ((case ((s2387 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2387 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2399 s16970
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2399 s16970 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2416 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2416 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2434 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2434 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2452 s16970 :: (( 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2452 s16970 :: (( 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2468 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2468 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2487 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2487 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2506 s16970 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s2506 s16970 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ True
+ )
+ else if ((case ((s2524 s16970 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s2524 s16970 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ True
+ )
+ else if (((s16970 = (''uret'')))) then True
+ else if ((case ((s2541 s16970 :: ( 32 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s2541 s16970 :: ( 32 Word.word) option) of (Some (s)) => True )
+ else if ((case ((s2549 s16970 :: ( 16 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s2549 s16970 :: ( 16 Word.word) option) of (Some (s)) => True )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val assembly_matches_prefix : string -> maybe ((ast * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s3457_ : string -> maybe ((mword ty16 * string))\<close>\<close>
+
+definition s3457 :: " string \<Rightarrow>((16)Word.word*string)option " where
+ " s3457 s34580 = (
+ (let s34590 = s34580 in
+ if ((string_startswith s34590 (''c.illegal''))) then
+ (case ((string_drop s34590 ((string_length (''c.illegal''))))) of
+ s34600 =>
+ (case ((spc_matches_prefix0 s34600)) of
+ Some ((_, s34610)) =>
+ (case ((string_drop s34600 s34610)) of
+ s34620 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34620 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s34630)) =>
+ (case ((string_drop s34620 s34630)) of s2 => Some (s, s2) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s34580 :: " string "
+
+
+\<comment> \<open>\<open>val _s3449_ : string -> maybe ((mword ty32 * string))\<close>\<close>
+
+definition s3449 :: " string \<Rightarrow>((32)Word.word*string)option " where
+ " s3449 s34500 = (
+ (let s34510 = s34500 in
+ if ((string_startswith s34510 (''illegal''))) then
+ (case ((string_drop s34510 ((string_length (''illegal''))))) of
+ s34520 =>
+ (case ((spc_matches_prefix0 s34520)) of
+ Some ((_, s34530)) =>
+ (case ((string_drop s34520 s34530)) of
+ s34540 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34540 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s34550)) =>
+ (case ((string_drop s34540 s34550)) of s2 => Some (s, s2) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s34500 :: " string "
+
+
+\<comment> \<open>\<open>val _s3445_ : string -> maybe string\<close>\<close>
+
+definition s3445 :: " string \<Rightarrow>(string)option " where
+ " s3445 s34460 = (
+ (let s34470 = s34460 in
+ if ((string_startswith s34470 (''uret''))) then
+ (case ((string_drop s34470 ((string_length (''uret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s34460 :: " string "
+
+
+\<comment> \<open>\<open>val _s3428_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s3428 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s3428 s34300 = (
+ (case ((csr_mnemonic_matches_prefix s34300)) of
+ Some ((op1, s34310)) =>
+ (case ((string_drop s34300 s34310)) of
+ s34320 =>
+ (case ((spc_matches_prefix0 s34320)) of
+ Some ((_, s34330)) =>
+ (case ((string_drop s34320 s34330)) of
+ s34340 =>
+ (case ((reg_name_matches_prefix s34340 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34350)) =>
+ (case ((string_drop s34340 s34350)) of
+ s34360 =>
+ (case ((sep_matches_prefix s34360)) of
+ Some ((_, s34370)) =>
+ (case ((string_drop s34360 s34370)) of
+ s34380 =>
+ (case ((reg_name_matches_prefix s34380 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34390)) =>
+ (case ((string_drop s34380 s34390)) of
+ s34400 =>
+ (case ((sep_matches_prefix s34400)) of
+ Some ((_, s34410)) =>
+ (case ((string_drop s34400 s34410)) of
+ s34420 =>
+ (case ((csr_name_map_matches_prefix s34420
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s34430)) =>
+ (case ((string_drop s34420 s34430)) of
+ s1 => Some (op1, rd, rs1, csr, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s34300 :: " string "
+
+
+\<comment> \<open>\<open>val _s3410_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s3410 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s3410 s34120 = (
+ (case ((csr_mnemonic_matches_prefix s34120)) of
+ Some ((op1, s34130)) =>
+ (let s34140 = (string_drop s34120 s34130) in
+ if ((string_startswith s34140 (''i''))) then
+ (case ((string_drop s34140 ((string_length (''i''))))) of
+ s34150 =>
+ (case ((spc_matches_prefix0 s34150)) of
+ Some ((_, s34160)) =>
+ (case ((string_drop s34150 s34160)) of
+ s34170 =>
+ (case ((reg_name_matches_prefix s34170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34180)) =>
+ (case ((string_drop s34170 s34180)) of
+ s34190 =>
+ (case ((sep_matches_prefix s34190)) of
+ Some ((_, s34200)) =>
+ (case ((string_drop s34190 s34200)) of
+ s34210 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34210 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34220)) =>
+ (case ((string_drop s34210 s34220)) of
+ s34230 =>
+ (case ((sep_matches_prefix s34230)) of
+ Some ((_, s34240)) =>
+ (case ((string_drop s34230 s34240)) of
+ s34250 =>
+ (case ((csr_name_map_matches_prefix s34250
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s34260)) =>
+ (case ((string_drop s34250 s34260)) of
+ s1 => Some (op1, rd, rs1, csr, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s34120 :: " string "
+
+
+\<comment> \<open>\<open>val _s3391_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3391 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3391 s33920 = (
+ (let s33930 = s33920 in
+ if ((string_startswith s33930 (''rem''))) then
+ (case ((string_drop s33930 ((string_length (''rem''))))) of
+ s33940 =>
+ (case ((maybe_not_u_matches_prefix s33940)) of
+ Some ((s, s33950)) =>
+ (let s33960 = (string_drop s33940 s33950) in
+ if ((string_startswith s33960 (''w''))) then
+ (case ((string_drop s33960 ((string_length (''w''))))) of
+ s33970 =>
+ (case ((spc_matches_prefix0 s33970)) of
+ Some ((_, s33980)) =>
+ (case ((string_drop s33970 s33980)) of
+ s33990 =>
+ (case ((reg_name_matches_prefix s33990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34000)) =>
+ (case ((string_drop s33990 s34000)) of
+ s34010 =>
+ (case ((sep_matches_prefix s34010)) of
+ Some ((_, s34020)) =>
+ (case ((string_drop s34010 s34020)) of
+ s34030 =>
+ (case ((reg_name_matches_prefix s34030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34040)) =>
+ (case ((string_drop s34030 s34040)) of
+ s34050 =>
+ (case ((sep_matches_prefix s34050)) of
+ Some ((_, s34060)) =>
+ (case ((string_drop s34050 s34060)) of
+ s34070 =>
+ (case ((reg_name_matches_prefix s34070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s34080)) =>
+ (case ((string_drop s34070 s34080)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s33920 :: " string "
+
+
+\<comment> \<open>\<open>val _s3372_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3372 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3372 s33730 = (
+ (let s33740 = s33730 in
+ if ((string_startswith s33740 (''div''))) then
+ (case ((string_drop s33740 ((string_length (''div''))))) of
+ s33750 =>
+ (case ((maybe_not_u_matches_prefix s33750)) of
+ Some ((s, s33760)) =>
+ (let s33770 = (string_drop s33750 s33760) in
+ if ((string_startswith s33770 (''w''))) then
+ (case ((string_drop s33770 ((string_length (''w''))))) of
+ s33780 =>
+ (case ((spc_matches_prefix0 s33780)) of
+ Some ((_, s33790)) =>
+ (case ((string_drop s33780 s33790)) of
+ s33800 =>
+ (case ((reg_name_matches_prefix s33800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33810)) =>
+ (case ((string_drop s33800 s33810)) of
+ s33820 =>
+ (case ((sep_matches_prefix s33820)) of
+ Some ((_, s33830)) =>
+ (case ((string_drop s33820 s33830)) of
+ s33840 =>
+ (case ((reg_name_matches_prefix s33840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33850)) =>
+ (case ((string_drop s33840 s33850)) of
+ s33860 =>
+ (case ((sep_matches_prefix s33860)) of
+ Some ((_, s33870)) =>
+ (case ((string_drop s33860 s33870)) of
+ s33880 =>
+ (case ((reg_name_matches_prefix s33880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33890)) =>
+ (case ((string_drop s33880 s33890)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s33730 :: " string "
+
+
+\<comment> \<open>\<open>val _s3356_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3356 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3356 s33570 = (
+ (let s33580 = s33570 in
+ if ((string_startswith s33580 (''mulw''))) then
+ (case ((string_drop s33580 ((string_length (''mulw''))))) of
+ s33590 =>
+ (case ((spc_matches_prefix0 s33590)) of
+ Some ((_, s33600)) =>
+ (case ((string_drop s33590 s33600)) of
+ s33610 =>
+ (case ((reg_name_matches_prefix s33610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33620)) =>
+ (case ((string_drop s33610 s33620)) of
+ s33630 =>
+ (case ((sep_matches_prefix s33630)) of
+ Some ((_, s33640)) =>
+ (case ((string_drop s33630 s33640)) of
+ s33650 =>
+ (case ((reg_name_matches_prefix s33650 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33660)) =>
+ (case ((string_drop s33650 s33660)) of
+ s33670 =>
+ (case ((sep_matches_prefix s33670)) of
+ Some ((_, s33680)) =>
+ (case ((string_drop s33670 s33680)) of
+ s33690 =>
+ (case ((reg_name_matches_prefix s33690 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33700)) =>
+ (case ((string_drop s33690 s33700)) of s1 => Some (rd, rs1, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33570 :: " string "
+
+
+\<comment> \<open>\<open>val _s3338_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3338 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3338 s33390 = (
+ (let s33400 = s33390 in
+ if ((string_startswith s33400 (''rem''))) then
+ (case ((string_drop s33400 ((string_length (''rem''))))) of
+ s33410 =>
+ (case ((maybe_not_u_matches_prefix s33410)) of
+ Some ((s, s33420)) =>
+ (case ((string_drop s33410 s33420)) of
+ s33430 =>
+ (case ((spc_matches_prefix0 s33430)) of
+ Some ((_, s33440)) =>
+ (case ((string_drop s33430 s33440)) of
+ s33450 =>
+ (case ((reg_name_matches_prefix s33450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33460)) =>
+ (case ((string_drop s33450 s33460)) of
+ s33470 =>
+ (case ((sep_matches_prefix s33470)) of
+ Some ((_, s33480)) =>
+ (case ((string_drop s33470 s33480)) of
+ s33490 =>
+ (case ((reg_name_matches_prefix s33490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33500)) =>
+ (case ((string_drop s33490 s33500)) of
+ s33510 =>
+ (case ((sep_matches_prefix s33510)) of
+ Some ((_, s33520)) =>
+ (case ((string_drop s33510 s33520)) of
+ s33530 =>
+ (case ((reg_name_matches_prefix s33530 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33540)) =>
+ (case ((string_drop s33530 s33540)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33390 :: " string "
+
+
+\<comment> \<open>\<open>val _s3320_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3320 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3320 s33210 = (
+ (let s33220 = s33210 in
+ if ((string_startswith s33220 (''div''))) then
+ (case ((string_drop s33220 ((string_length (''div''))))) of
+ s33230 =>
+ (case ((maybe_not_u_matches_prefix s33230)) of
+ Some ((s, s33240)) =>
+ (case ((string_drop s33230 s33240)) of
+ s33250 =>
+ (case ((spc_matches_prefix0 s33250)) of
+ Some ((_, s33260)) =>
+ (case ((string_drop s33250 s33260)) of
+ s33270 =>
+ (case ((reg_name_matches_prefix s33270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33280)) =>
+ (case ((string_drop s33270 s33280)) of
+ s33290 =>
+ (case ((sep_matches_prefix s33290)) of
+ Some ((_, s33300)) =>
+ (case ((string_drop s33290 s33300)) of
+ s33310 =>
+ (case ((reg_name_matches_prefix s33310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33320)) =>
+ (case ((string_drop s33310 s33320)) of
+ s33330 =>
+ (case ((sep_matches_prefix s33330)) of
+ Some ((_, s33340)) =>
+ (case ((string_drop s33330 s33340)) of
+ s33350 =>
+ (case ((reg_name_matches_prefix s33350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33360)) =>
+ (case ((string_drop s33350 s33360)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33210 :: " string "
+
+
+\<comment> \<open>\<open>val _s3303_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3303 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3303 s33050 = (
+ (case ((mul_mnemonic_matches_prefix s33050)) of
+ Some (((high, signed1, signed2), s33060)) =>
+ (case ((string_drop s33050 s33060)) of
+ s33070 =>
+ (case ((spc_matches_prefix0 s33070)) of
+ Some ((_, s33080)) =>
+ (case ((string_drop s33070 s33080)) of
+ s33090 =>
+ (case ((reg_name_matches_prefix s33090 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33100)) =>
+ (case ((string_drop s33090 s33100)) of
+ s33110 =>
+ (case ((sep_matches_prefix s33110)) of
+ Some ((_, s33120)) =>
+ (case ((string_drop s33110 s33120)) of
+ s33130 =>
+ (case ((reg_name_matches_prefix s33130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33140)) =>
+ (case ((string_drop s33130 s33140)) of
+ s33150 =>
+ (case ((sep_matches_prefix s33150)) of
+ Some ((_, s33160)) =>
+ (case ((string_drop s33150 s33160)) of
+ s33170 =>
+ (case ((reg_name_matches_prefix s33170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33180)) =>
+ (case ((string_drop s33170 s33180)) of
+ s1 => Some (high, signed1, signed2, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s33050 :: " string "
+
+
+\<comment> \<open>\<open>val _s3291_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3291 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s3291 s32920 = (
+ (let s32930 = s32920 in
+ if ((string_startswith s32930 (''c.add''))) then
+ (case ((string_drop s32930 ((string_length (''c.add''))))) of
+ s32940 =>
+ (case ((spc_matches_prefix0 s32940)) of
+ Some ((_, s32950)) =>
+ (case ((string_drop s32940 s32950)) of
+ s32960 =>
+ (case ((reg_name_matches_prefix s32960 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s32970)) =>
+ (case ((string_drop s32960 s32970)) of
+ s32980 =>
+ (case ((sep_matches_prefix s32980)) of
+ Some ((_, s32990)) =>
+ (case ((string_drop s32980 s32990)) of
+ s33000 =>
+ (case ((reg_name_matches_prefix s33000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33010)) =>
+ (case ((string_drop s33000 s33010)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32920 :: " string "
+
+
+\<comment> \<open>\<open>val _s3287_ : string -> maybe string\<close>\<close>
+
+definition s3287 :: " string \<Rightarrow>(string)option " where
+ " s3287 s32880 = (
+ (let s32890 = s32880 in
+ if ((string_startswith s32890 (''c.ebreak''))) then
+ (case ((string_drop s32890 ((string_length (''c.ebreak''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s32880 :: " string "
+
+
+\<comment> \<open>\<open>val _s3275_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3275 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s3275 s32760 = (
+ (let s32770 = s32760 in
+ if ((string_startswith s32770 (''c.mv''))) then
+ (case ((string_drop s32770 ((string_length (''c.mv''))))) of
+ s32780 =>
+ (case ((spc_matches_prefix0 s32780)) of
+ Some ((_, s32790)) =>
+ (case ((string_drop s32780 s32790)) of
+ s32800 =>
+ (case ((reg_name_matches_prefix s32800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32810)) =>
+ (case ((string_drop s32800 s32810)) of
+ s32820 =>
+ (case ((sep_matches_prefix s32820)) of
+ Some ((_, s32830)) =>
+ (case ((string_drop s32820 s32830)) of
+ s32840 =>
+ (case ((reg_name_matches_prefix s32840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s32850)) =>
+ (case ((string_drop s32840 s32850)) of s1 => Some (rd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32760 :: " string "
+
+
+\<comment> \<open>\<open>val _s3267_ : string -> maybe ((mword ty5 * string))\<close>\<close>
+
+definition s3267 :: " string \<Rightarrow>((5)Word.word*string)option " where
+ " s3267 s32680 = (
+ (let s32690 = s32680 in
+ if ((string_startswith s32690 (''c.jalr''))) then
+ (case ((string_drop s32690 ((string_length (''c.jalr''))))) of
+ s32700 =>
+ (case ((spc_matches_prefix0 s32700)) of
+ Some ((_, s32710)) =>
+ (case ((string_drop s32700 s32710)) of
+ s32720 =>
+ (case ((reg_name_matches_prefix s32720 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s32730)) =>
+ (case ((string_drop s32720 s32730)) of s1 => Some (rs1, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32680 :: " string "
+
+
+\<comment> \<open>\<open>val _s3259_ : string -> maybe ((mword ty5 * string))\<close>\<close>
+
+definition s3259 :: " string \<Rightarrow>((5)Word.word*string)option " where
+ " s3259 s32600 = (
+ (let s32610 = s32600 in
+ if ((string_startswith s32610 (''c.jr''))) then
+ (case ((string_drop s32610 ((string_length (''c.jr''))))) of
+ s32620 =>
+ (case ((spc_matches_prefix0 s32620)) of
+ Some ((_, s32630)) =>
+ (case ((string_drop s32620 s32630)) of
+ s32640 =>
+ (case ((reg_name_matches_prefix s32640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s32650)) =>
+ (case ((string_drop s32640 s32650)) of s1 => Some (rs1, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32600 :: " string "
+
+
+\<comment> \<open>\<open>val _s3247_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3247 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3247 s32480 = (
+ (let s32490 = s32480 in
+ if ((string_startswith s32490 (''c.sdsp''))) then
+ (case ((string_drop s32490 ((string_length (''c.sdsp''))))) of
+ s32500 =>
+ (case ((spc_matches_prefix0 s32500)) of
+ Some ((_, s32510)) =>
+ (case ((string_drop s32500 s32510)) of
+ s32520 =>
+ (case ((reg_name_matches_prefix s32520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s32530)) =>
+ (case ((string_drop s32520 s32530)) of
+ s32540 =>
+ (case ((sep_matches_prefix s32540)) of
+ Some ((_, s32550)) =>
+ (case ((string_drop s32540 s32550)) of
+ s32560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32560 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32570)) =>
+ (case ((string_drop s32560 s32570)) of s1 => Some (rs2, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32480 :: " string "
+
+
+\<comment> \<open>\<open>val _s3235_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3235 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3235 s32360 = (
+ (let s32370 = s32360 in
+ if ((string_startswith s32370 (''c.swsp''))) then
+ (case ((string_drop s32370 ((string_length (''c.swsp''))))) of
+ s32380 =>
+ (case ((spc_matches_prefix0 s32380)) of
+ Some ((_, s32390)) =>
+ (case ((string_drop s32380 s32390)) of
+ s32400 =>
+ (case ((reg_name_matches_prefix s32400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32410)) =>
+ (case ((string_drop s32400 s32410)) of
+ s32420 =>
+ (case ((sep_matches_prefix s32420)) of
+ Some ((_, s32430)) =>
+ (case ((string_drop s32420 s32430)) of
+ s32440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32440 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32450)) =>
+ (case ((string_drop s32440 s32450)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32360 :: " string "
+
+
+\<comment> \<open>\<open>val _s3223_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3223 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3223 s32240 = (
+ (let s32250 = s32240 in
+ if ((string_startswith s32250 (''c.ldsp''))) then
+ (case ((string_drop s32250 ((string_length (''c.ldsp''))))) of
+ s32260 =>
+ (case ((spc_matches_prefix0 s32260)) of
+ Some ((_, s32270)) =>
+ (case ((string_drop s32260 s32270)) of
+ s32280 =>
+ (case ((reg_name_matches_prefix s32280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32290)) =>
+ (case ((string_drop s32280 s32290)) of
+ s32300 =>
+ (case ((sep_matches_prefix s32300)) of
+ Some ((_, s32310)) =>
+ (case ((string_drop s32300 s32310)) of
+ s32320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32320 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32330)) =>
+ (case ((string_drop s32320 s32330)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32240 :: " string "
+
+
+\<comment> \<open>\<open>val _s3211_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3211 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3211 s32120 = (
+ (let s32130 = s32120 in
+ if ((string_startswith s32130 (''c.lwsp''))) then
+ (case ((string_drop s32130 ((string_length (''c.lwsp''))))) of
+ s32140 =>
+ (case ((spc_matches_prefix0 s32140)) of
+ Some ((_, s32150)) =>
+ (case ((string_drop s32140 s32150)) of
+ s32160 =>
+ (case ((reg_name_matches_prefix s32160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32170)) =>
+ (case ((string_drop s32160 s32170)) of
+ s32180 =>
+ (case ((sep_matches_prefix s32180)) of
+ Some ((_, s32190)) =>
+ (case ((string_drop s32180 s32190)) of
+ s32200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32200 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32210)) =>
+ (case ((string_drop s32200 s32210)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32120 :: " string "
+
+
+\<comment> \<open>\<open>val _s3199_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3199 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3199 s32000 = (
+ (let s32010 = s32000 in
+ if ((string_startswith s32010 (''c.slli''))) then
+ (case ((string_drop s32010 ((string_length (''c.slli''))))) of
+ s32020 =>
+ (case ((spc_matches_prefix0 s32020)) of
+ Some ((_, s32030)) =>
+ (case ((string_drop s32020 s32030)) of
+ s32040 =>
+ (case ((reg_name_matches_prefix s32040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s32050)) =>
+ (case ((string_drop s32040 s32050)) of
+ s32060 =>
+ (case ((sep_matches_prefix s32060)) of
+ Some ((_, s32070)) =>
+ (case ((string_drop s32060 s32070)) of
+ s32080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s32090)) =>
+ (case ((string_drop s32080 s32090)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32000 :: " string "
+
+
+\<comment> \<open>\<open>val _s3187_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s3187 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s3187 s31880 = (
+ (let s31890 = s31880 in
+ if ((string_startswith s31890 (''c.bnez''))) then
+ (case ((string_drop s31890 ((string_length (''c.bnez''))))) of
+ s31900 =>
+ (case ((spc_matches_prefix0 s31900)) of
+ Some ((_, s31910)) =>
+ (case ((string_drop s31900 s31910)) of
+ s31920 =>
+ (case ((creg_name_matches_prefix s31920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s31930)) =>
+ (case ((string_drop s31920 s31930)) of
+ s31940 =>
+ (case ((sep_matches_prefix s31940)) of
+ Some ((_, s31950)) =>
+ (case ((string_drop s31940 s31950)) of
+ s31960 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31960 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s31970)) =>
+ (case ((string_drop s31960 s31970)) of s1 => Some (rs, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31880 :: " string "
+
+
+\<comment> \<open>\<open>val _s3175_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s3175 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s3175 s31760 = (
+ (let s31770 = s31760 in
+ if ((string_startswith s31770 (''c.beqz''))) then
+ (case ((string_drop s31770 ((string_length (''c.beqz''))))) of
+ s31780 =>
+ (case ((spc_matches_prefix0 s31780)) of
+ Some ((_, s31790)) =>
+ (case ((string_drop s31780 s31790)) of
+ s31800 =>
+ (case ((creg_name_matches_prefix s31800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s31810)) =>
+ (case ((string_drop s31800 s31810)) of
+ s31820 =>
+ (case ((sep_matches_prefix s31820)) of
+ Some ((_, s31830)) =>
+ (case ((string_drop s31820 s31830)) of
+ s31840 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31840 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s31850)) =>
+ (case ((string_drop s31840 s31850)) of s1 => Some (rs, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31760 :: " string "
+
+
+\<comment> \<open>\<open>val _s3167_ : string -> maybe ((mword ty11 * string))\<close>\<close>
+
+definition s3167 :: " string \<Rightarrow>((11)Word.word*string)option " where
+ " s3167 s31680 = (
+ (let s31690 = s31680 in
+ if ((string_startswith s31690 (''c.j''))) then
+ (case ((string_drop s31690 ((string_length (''c.j''))))) of
+ s31700 =>
+ (case ((spc_matches_prefix0 s31700)) of
+ Some ((_, s31710)) =>
+ (case ((string_drop s31700 s31710)) of
+ s31720 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31720 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s31730)) =>
+ (case ((string_drop s31720 s31730)) of s1 => Some (imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31680 :: " string "
+
+
+\<comment> \<open>\<open>val _s3155_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3155 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3155 s31560 = (
+ (let s31570 = s31560 in
+ if ((string_startswith s31570 (''c.addw''))) then
+ (case ((string_drop s31570 ((string_length (''c.addw''))))) of
+ s31580 =>
+ (case ((spc_matches_prefix0 s31580)) of
+ Some ((_, s31590)) =>
+ (case ((string_drop s31580 s31590)) of
+ s31600 =>
+ (case ((creg_name_matches_prefix s31600 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31610)) =>
+ (case ((string_drop s31600 s31610)) of
+ s31620 =>
+ (case ((sep_matches_prefix s31620)) of
+ Some ((_, s31630)) =>
+ (case ((string_drop s31620 s31630)) of
+ s31640 =>
+ (case ((creg_name_matches_prefix s31640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31650)) =>
+ (case ((string_drop s31640 s31650)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31560 :: " string "
+
+
+\<comment> \<open>\<open>val _s3143_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3143 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3143 s31440 = (
+ (let s31450 = s31440 in
+ if ((string_startswith s31450 (''c.subw''))) then
+ (case ((string_drop s31450 ((string_length (''c.subw''))))) of
+ s31460 =>
+ (case ((spc_matches_prefix0 s31460)) of
+ Some ((_, s31470)) =>
+ (case ((string_drop s31460 s31470)) of
+ s31480 =>
+ (case ((creg_name_matches_prefix s31480 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31490)) =>
+ (case ((string_drop s31480 s31490)) of
+ s31500 =>
+ (case ((sep_matches_prefix s31500)) of
+ Some ((_, s31510)) =>
+ (case ((string_drop s31500 s31510)) of
+ s31520 =>
+ (case ((creg_name_matches_prefix s31520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31530)) =>
+ (case ((string_drop s31520 s31530)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31440 :: " string "
+
+
+\<comment> \<open>\<open>val _s3131_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3131 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3131 s31320 = (
+ (let s31330 = s31320 in
+ if ((string_startswith s31330 (''c.and''))) then
+ (case ((string_drop s31330 ((string_length (''c.and''))))) of
+ s31340 =>
+ (case ((spc_matches_prefix0 s31340)) of
+ Some ((_, s31350)) =>
+ (case ((string_drop s31340 s31350)) of
+ s31360 =>
+ (case ((creg_name_matches_prefix s31360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31370)) =>
+ (case ((string_drop s31360 s31370)) of
+ s31380 =>
+ (case ((sep_matches_prefix s31380)) of
+ Some ((_, s31390)) =>
+ (case ((string_drop s31380 s31390)) of
+ s31400 =>
+ (case ((creg_name_matches_prefix s31400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31410)) =>
+ (case ((string_drop s31400 s31410)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31320 :: " string "
+
+
+\<comment> \<open>\<open>val _s3119_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3119 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3119 s31200 = (
+ (let s31210 = s31200 in
+ if ((string_startswith s31210 (''c.or''))) then
+ (case ((string_drop s31210 ((string_length (''c.or''))))) of
+ s31220 =>
+ (case ((spc_matches_prefix0 s31220)) of
+ Some ((_, s31230)) =>
+ (case ((string_drop s31220 s31230)) of
+ s31240 =>
+ (case ((creg_name_matches_prefix s31240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31250)) =>
+ (case ((string_drop s31240 s31250)) of
+ s31260 =>
+ (case ((sep_matches_prefix s31260)) of
+ Some ((_, s31270)) =>
+ (case ((string_drop s31260 s31270)) of
+ s31280 =>
+ (case ((creg_name_matches_prefix s31280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31290)) =>
+ (case ((string_drop s31280 s31290)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31200 :: " string "
+
+
+\<comment> \<open>\<open>val _s3107_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3107 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3107 s31080 = (
+ (let s31090 = s31080 in
+ if ((string_startswith s31090 (''c.xor''))) then
+ (case ((string_drop s31090 ((string_length (''c.xor''))))) of
+ s31100 =>
+ (case ((spc_matches_prefix0 s31100)) of
+ Some ((_, s31110)) =>
+ (case ((string_drop s31100 s31110)) of
+ s31120 =>
+ (case ((creg_name_matches_prefix s31120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31130)) =>
+ (case ((string_drop s31120 s31130)) of
+ s31140 =>
+ (case ((sep_matches_prefix s31140)) of
+ Some ((_, s31150)) =>
+ (case ((string_drop s31140 s31150)) of
+ s31160 =>
+ (case ((creg_name_matches_prefix s31160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31170)) =>
+ (case ((string_drop s31160 s31170)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31080 :: " string "
+
+
+\<comment> \<open>\<open>val _s3095_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3095 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3095 s30960 = (
+ (let s30970 = s30960 in
+ if ((string_startswith s30970 (''c.sub''))) then
+ (case ((string_drop s30970 ((string_length (''c.sub''))))) of
+ s30980 =>
+ (case ((spc_matches_prefix0 s30980)) of
+ Some ((_, s30990)) =>
+ (case ((string_drop s30980 s30990)) of
+ s31000 =>
+ (case ((creg_name_matches_prefix s31000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31010)) =>
+ (case ((string_drop s31000 s31010)) of
+ s31020 =>
+ (case ((sep_matches_prefix s31020)) of
+ Some ((_, s31030)) =>
+ (case ((string_drop s31020 s31030)) of
+ s31040 =>
+ (case ((creg_name_matches_prefix s31040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31050)) =>
+ (case ((string_drop s31040 s31050)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30960 :: " string "
+
+
+\<comment> \<open>\<open>val _s3083_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3083 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3083 s30840 = (
+ (let s30850 = s30840 in
+ if ((string_startswith s30850 (''c.andi''))) then
+ (case ((string_drop s30850 ((string_length (''c.andi''))))) of
+ s30860 =>
+ (case ((spc_matches_prefix0 s30860)) of
+ Some ((_, s30870)) =>
+ (case ((string_drop s30860 s30870)) of
+ s30880 =>
+ (case ((creg_name_matches_prefix s30880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30890)) =>
+ (case ((string_drop s30880 s30890)) of
+ s30900 =>
+ (case ((sep_matches_prefix s30900)) of
+ Some ((_, s30910)) =>
+ (case ((string_drop s30900 s30910)) of
+ s30920 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30920 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30930)) =>
+ (case ((string_drop s30920 s30930)) of s1 => Some (rsd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30840 :: " string "
+
+
+\<comment> \<open>\<open>val _s3071_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3071 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3071 s30720 = (
+ (let s30730 = s30720 in
+ if ((string_startswith s30730 (''c.srai''))) then
+ (case ((string_drop s30730 ((string_length (''c.srai''))))) of
+ s30740 =>
+ (case ((spc_matches_prefix0 s30740)) of
+ Some ((_, s30750)) =>
+ (case ((string_drop s30740 s30750)) of
+ s30760 =>
+ (case ((creg_name_matches_prefix s30760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30770)) =>
+ (case ((string_drop s30760 s30770)) of
+ s30780 =>
+ (case ((sep_matches_prefix s30780)) of
+ Some ((_, s30790)) =>
+ (case ((string_drop s30780 s30790)) of
+ s30800 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30800 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s30810)) =>
+ (case ((string_drop s30800 s30810)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30720 :: " string "
+
+
+\<comment> \<open>\<open>val _s3059_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3059 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3059 s30600 = (
+ (let s30610 = s30600 in
+ if ((string_startswith s30610 (''c.srli''))) then
+ (case ((string_drop s30610 ((string_length (''c.srli''))))) of
+ s30620 =>
+ (case ((spc_matches_prefix0 s30620)) of
+ Some ((_, s30630)) =>
+ (case ((string_drop s30620 s30630)) of
+ s30640 =>
+ (case ((creg_name_matches_prefix s30640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30650)) =>
+ (case ((string_drop s30640 s30650)) of
+ s30660 =>
+ (case ((sep_matches_prefix s30660)) of
+ Some ((_, s30670)) =>
+ (case ((string_drop s30660 s30670)) of
+ s30680 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30680 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s30690)) =>
+ (case ((string_drop s30680 s30690)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30600 :: " string "
+
+
+\<comment> \<open>\<open>val _s3047_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3047 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3047 s30480 = (
+ (let s30490 = s30480 in
+ if ((string_startswith s30490 (''c.lui''))) then
+ (case ((string_drop s30490 ((string_length (''c.lui''))))) of
+ s30500 =>
+ (case ((spc_matches_prefix0 s30500)) of
+ Some ((_, s30510)) =>
+ (case ((string_drop s30500 s30510)) of
+ s30520 =>
+ (case ((reg_name_matches_prefix s30520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s30530)) =>
+ (case ((string_drop s30520 s30530)) of
+ s30540 =>
+ (case ((sep_matches_prefix s30540)) of
+ Some ((_, s30550)) =>
+ (case ((string_drop s30540 s30550)) of
+ s30560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30560 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30570)) =>
+ (case ((string_drop s30560 s30570)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30480 :: " string "
+
+
+\<comment> \<open>\<open>val _s3039_ : string -> maybe ((mword ty6 * string))\<close>\<close>
+
+definition s3039 :: " string \<Rightarrow>((6)Word.word*string)option " where
+ " s3039 s30400 = (
+ (let s30410 = s30400 in
+ if ((string_startswith s30410 (''c.addi16sp''))) then
+ (case ((string_drop s30410 ((string_length (''c.addi16sp''))))) of
+ s30420 =>
+ (case ((spc_matches_prefix0 s30420)) of
+ Some ((_, s30430)) =>
+ (case ((string_drop s30420 s30430)) of
+ s30440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30440 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30450)) =>
+ (case ((string_drop s30440 s30450)) of s1 => Some (imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30400 :: " string "
+
+
+\<comment> \<open>\<open>val _s3027_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3027 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3027 s30280 = (
+ (let s30290 = s30280 in
+ if ((string_startswith s30290 (''c.li''))) then
+ (case ((string_drop s30290 ((string_length (''c.li''))))) of
+ s30300 =>
+ (case ((spc_matches_prefix0 s30300)) of
+ Some ((_, s30310)) =>
+ (case ((string_drop s30300 s30310)) of
+ s30320 =>
+ (case ((reg_name_matches_prefix s30320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s30330)) =>
+ (case ((string_drop s30320 s30330)) of
+ s30340 =>
+ (case ((sep_matches_prefix s30340)) of
+ Some ((_, s30350)) =>
+ (case ((string_drop s30340 s30350)) of
+ s30360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30360 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30370)) =>
+ (case ((string_drop s30360 s30370)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30280 :: " string "
+
+
+\<comment> \<open>\<open>val _s3015_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3015 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3015 s30160 = (
+ (let s30170 = s30160 in
+ if ((string_startswith s30170 (''c.addiw''))) then
+ (case ((string_drop s30170 ((string_length (''c.addiw''))))) of
+ s30180 =>
+ (case ((spc_matches_prefix0 s30180)) of
+ Some ((_, s30190)) =>
+ (case ((string_drop s30180 s30190)) of
+ s30200 =>
+ (case ((reg_name_matches_prefix s30200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s30210)) =>
+ (case ((string_drop s30200 s30210)) of
+ s30220 =>
+ (case ((sep_matches_prefix s30220)) of
+ Some ((_, s30230)) =>
+ (case ((string_drop s30220 s30230)) of
+ s30240 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30240 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30250)) =>
+ (case ((string_drop s30240 s30250)) of s1 => Some (rsd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30160 :: " string "
+
+
+\<comment> \<open>\<open>val _s3007_ : string -> maybe ((mword ty11 * string))\<close>\<close>
+
+definition s3007 :: " string \<Rightarrow>((11)Word.word*string)option " where
+ " s3007 s30080 = (
+ (let s30090 = s30080 in
+ if ((string_startswith s30090 (''c.jal''))) then
+ (case ((string_drop s30090 ((string_length (''c.jal''))))) of
+ s30100 =>
+ (case ((spc_matches_prefix0 s30100)) of
+ Some ((_, s30110)) =>
+ (case ((string_drop s30100 s30110)) of
+ s30120 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30120 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__826, s30130)) =>
+ if (((((subrange_vec_dec v__826 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__826
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__826
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (case ((string_drop s30120 s30130)) of s1 => Some (imm, s1) ))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2995_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s2995 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s2995 s29960 = (
+ (let s29970 = s29960 in
+ if ((string_startswith s29970 (''c.addi''))) then
+ (case ((string_drop s29970 ((string_length (''c.addi''))))) of
+ s29980 =>
+ (case ((spc_matches_prefix0 s29980)) of
+ Some ((_, s29990)) =>
+ (case ((string_drop s29980 s29990)) of
+ s30000 =>
+ (case ((reg_name_matches_prefix s30000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s30010)) =>
+ (case ((string_drop s30000 s30010)) of
+ s30020 =>
+ (case ((sep_matches_prefix s30020)) of
+ Some ((_, s30030)) =>
+ (case ((string_drop s30020 s30030)) of
+ s30040 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30040 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s30050)) =>
+ (case ((string_drop s30040 s30050)) of s1 => Some (rsd, nzi, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2979_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2979 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2979 s29800 = (
+ (let s29810 = s29800 in
+ if ((string_startswith s29810 (''c.sd''))) then
+ (case ((string_drop s29810 ((string_length (''c.sd''))))) of
+ s29820 =>
+ (case ((spc_matches_prefix0 s29820)) of
+ Some ((_, s29830)) =>
+ (case ((string_drop s29820 s29830)) of
+ s29840 =>
+ (case ((creg_name_matches_prefix s29840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s29850)) =>
+ (case ((string_drop s29840 s29850)) of
+ s29860 =>
+ (case ((sep_matches_prefix s29860)) of
+ Some ((_, s29870)) =>
+ (case ((string_drop s29860 s29870)) of
+ s29880 =>
+ (case ((creg_name_matches_prefix s29880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s29890)) =>
+ (case ((string_drop s29880 s29890)) of
+ s29900 =>
+ (case ((sep_matches_prefix s29900)) of
+ Some ((_, s29910)) =>
+ (case ((string_drop s29900 s29910)) of
+ s29920 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29920 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__828, s29930)) =>
+ if (((((subrange_vec_dec v__828 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__828 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__828 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29920 s29930)) of
+ s1 => Some (rsc1, rsc2, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29800 :: " string "
+
+
+\<comment> \<open>\<open>val _s2963_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2963 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2963 s29640 = (
+ (let s29650 = s29640 in
+ if ((string_startswith s29650 (''c.sw''))) then
+ (case ((string_drop s29650 ((string_length (''c.sw''))))) of
+ s29660 =>
+ (case ((spc_matches_prefix0 s29660)) of
+ Some ((_, s29670)) =>
+ (case ((string_drop s29660 s29670)) of
+ s29680 =>
+ (case ((creg_name_matches_prefix s29680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s29690)) =>
+ (case ((string_drop s29680 s29690)) of
+ s29700 =>
+ (case ((sep_matches_prefix s29700)) of
+ Some ((_, s29710)) =>
+ (case ((string_drop s29700 s29710)) of
+ s29720 =>
+ (case ((creg_name_matches_prefix s29720 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s29730)) =>
+ (case ((string_drop s29720 s29730)) of
+ s29740 =>
+ (case ((sep_matches_prefix s29740)) of
+ Some ((_, s29750)) =>
+ (case ((string_drop s29740 s29750)) of
+ s29760 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29760 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__830, s29770)) =>
+ if (((((subrange_vec_dec v__830 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__830 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__830 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29760 s29770)) of
+ s1 => Some (rsc1, rsc2, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29640 :: " string "
+
+
+\<comment> \<open>\<open>val _s2947_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2947 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2947 s29480 = (
+ (let s29490 = s29480 in
+ if ((string_startswith s29490 (''c.ld''))) then
+ (case ((string_drop s29490 ((string_length (''c.ld''))))) of
+ s29500 =>
+ (case ((spc_matches_prefix0 s29500)) of
+ Some ((_, s29510)) =>
+ (case ((string_drop s29500 s29510)) of
+ s29520 =>
+ (case ((creg_name_matches_prefix s29520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29530)) =>
+ (case ((string_drop s29520 s29530)) of
+ s29540 =>
+ (case ((sep_matches_prefix s29540)) of
+ Some ((_, s29550)) =>
+ (case ((string_drop s29540 s29550)) of
+ s29560 =>
+ (case ((creg_name_matches_prefix s29560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s29570)) =>
+ (case ((string_drop s29560 s29570)) of
+ s29580 =>
+ (case ((sep_matches_prefix s29580)) of
+ Some ((_, s29590)) =>
+ (case ((string_drop s29580 s29590)) of
+ s29600 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29600 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__832, s29610)) =>
+ if (((((subrange_vec_dec v__832 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__832 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__832 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29600 s29610)) of
+ s1 => Some (rdc, rsc, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2931_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2931 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2931 s29320 = (
+ (let s29330 = s29320 in
+ if ((string_startswith s29330 (''c.lw''))) then
+ (case ((string_drop s29330 ((string_length (''c.lw''))))) of
+ s29340 =>
+ (case ((spc_matches_prefix0 s29340)) of
+ Some ((_, s29350)) =>
+ (case ((string_drop s29340 s29350)) of
+ s29360 =>
+ (case ((creg_name_matches_prefix s29360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29370)) =>
+ (case ((string_drop s29360 s29370)) of
+ s29380 =>
+ (case ((sep_matches_prefix s29380)) of
+ Some ((_, s29390)) =>
+ (case ((string_drop s29380 s29390)) of
+ s29400 =>
+ (case ((creg_name_matches_prefix s29400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s29410)) =>
+ (case ((string_drop s29400 s29410)) of
+ s29420 =>
+ (case ((sep_matches_prefix s29420)) of
+ Some ((_, s29430)) =>
+ (case ((string_drop s29420 s29430)) of
+ s29440 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29440 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__834, s29450)) =>
+ if (((((subrange_vec_dec v__834 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__834 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__834 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29440 s29450)) of
+ s1 => Some (rdc, rsc, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2919_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s2919 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s2919 s29200 = (
+ (let s29210 = s29200 in
+ if ((string_startswith s29210 (''c.addi4spn''))) then
+ (case ((string_drop s29210 ((string_length (''c.addi4spn''))))) of
+ s29220 =>
+ (case ((spc_matches_prefix0 s29220)) of
+ Some ((_, s29230)) =>
+ (case ((string_drop s29220 s29230)) of
+ s29240 =>
+ (case ((creg_name_matches_prefix s29240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29250)) =>
+ (case ((string_drop s29240 s29250)) of
+ s29260 =>
+ (case ((sep_matches_prefix s29260)) of
+ Some ((_, s29270)) =>
+ (case ((string_drop s29260 s29270)) of
+ s29280 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29280 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__836, s29290)) =>
+ if (((((subrange_vec_dec v__836 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__836 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__836 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (case ((string_drop s29280 s29290)) of s1 => Some (rdc, nzimm, s1) )))
+ else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2915_ : string -> maybe string\<close>\<close>
+
+definition s2915 :: " string \<Rightarrow>(string)option " where
+ " s2915 s29160 = (
+ (let s29170 = s29160 in
+ if ((string_startswith s29170 (''c.nop''))) then
+ (case ((string_drop s29170 ((string_length (''c.nop''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s29160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2891_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2891 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2891 s28930 = (
+ (case ((amo_mnemonic_matches_prefix s28930)) of
+ Some ((op1, s28940)) =>
+ (let s28950 = (string_drop s28930 s28940) in
+ if ((string_startswith s28950 (''.''))) then
+ (case ((string_drop s28950 ((string_length (''.''))))) of
+ s28960 =>
+ (case ((size_mnemonic_matches_prefix s28960)) of
+ Some ((width, s28970)) =>
+ (case ((string_drop s28960 s28970)) of
+ s28980 =>
+ (case ((maybe_aq_matches_prefix s28980)) of
+ Some ((aq, s28990)) =>
+ (case ((string_drop s28980 s28990)) of
+ s29000 =>
+ (case ((maybe_rl_matches_prefix s29000)) of
+ Some ((rl, s29010)) =>
+ (case ((string_drop s29000 s29010)) of
+ s29020 =>
+ (case ((spc_matches_prefix0 s29020)) of
+ Some ((_, s29030)) =>
+ (case ((string_drop s29020 s29030)) of
+ s29040 =>
+ (case ((reg_name_matches_prefix s29040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s29050)) =>
+ (case ((string_drop s29040 s29050)) of
+ s29060 =>
+ (case ((sep_matches_prefix s29060)) of
+ Some ((_, s29070)) =>
+ (case ((string_drop s29060 s29070)) of
+ s29080 =>
+ (case ((reg_name_matches_prefix s29080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s29090)) =>
+ (case ((string_drop s29080 s29090)) of
+ s29100 =>
+ (case ((sep_matches_prefix s29100)) of
+ Some ((_, s29110)) =>
+ (case ((string_drop s29100 s29110)) of
+ s29120 =>
+ (case ((reg_name_matches_prefix s29120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s29130)) =>
+ (case ((string_drop s29120 s29130)) of
+ s1 =>
+ Some (op1, width, aq, rl, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s28930 :: " string "
+
+
+\<comment> \<open>\<open>val _s2869_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2869 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2869 s28700 = (
+ (let s28710 = s28700 in
+ if ((string_startswith s28710 (''sc.''))) then
+ (case ((string_drop s28710 ((string_length (''sc.''))))) of
+ s28720 =>
+ (case ((size_mnemonic_matches_prefix s28720)) of
+ Some ((size1, s28730)) =>
+ (case ((string_drop s28720 s28730)) of
+ s28740 =>
+ (case ((maybe_aq_matches_prefix s28740)) of
+ Some ((aq, s28750)) =>
+ (case ((string_drop s28740 s28750)) of
+ s28760 =>
+ (case ((maybe_rl_matches_prefix s28760)) of
+ Some ((rl, s28770)) =>
+ (case ((string_drop s28760 s28770)) of
+ s28780 =>
+ (case ((spc_matches_prefix0 s28780)) of
+ Some ((_, s28790)) =>
+ (case ((string_drop s28780 s28790)) of
+ s28800 =>
+ (case ((reg_name_matches_prefix s28800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s28810)) =>
+ (case ((string_drop s28800 s28810)) of
+ s28820 =>
+ (case ((sep_matches_prefix s28820)) of
+ Some ((_, s28830)) =>
+ (case ((string_drop s28820 s28830)) of
+ s28840 =>
+ (case ((reg_name_matches_prefix s28840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28850)) =>
+ (case ((string_drop s28840 s28850)) of
+ s28860 =>
+ (case ((sep_matches_prefix s28860)) of
+ Some ((_, s28870)) =>
+ (case ((string_drop s28860 s28870)) of
+ s28880 =>
+ (case ((reg_name_matches_prefix s28880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s28890)) =>
+ (case ((string_drop s28880 s28890)) of
+ s1 =>
+ Some (size1, aq, rl, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28700 :: " string "
+
+
+\<comment> \<open>\<open>val _s2851_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2851 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*string)option " where
+ " s2851 s28520 = (
+ (let s28530 = s28520 in
+ if ((string_startswith s28530 (''lr.''))) then
+ (case ((string_drop s28530 ((string_length (''lr.''))))) of
+ s28540 =>
+ (case ((size_mnemonic_matches_prefix s28540)) of
+ Some ((size1, s28550)) =>
+ (case ((string_drop s28540 s28550)) of
+ s28560 =>
+ (case ((maybe_aq_matches_prefix s28560)) of
+ Some ((aq, s28570)) =>
+ (case ((string_drop s28560 s28570)) of
+ s28580 =>
+ (case ((maybe_rl_matches_prefix s28580)) of
+ Some ((rl, s28590)) =>
+ (case ((string_drop s28580 s28590)) of
+ s28600 =>
+ (case ((spc_matches_prefix0 s28600)) of
+ Some ((_, s28610)) =>
+ (case ((string_drop s28600 s28610)) of
+ s28620 =>
+ (case ((reg_name_matches_prefix s28620 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s28630)) =>
+ (case ((string_drop s28620 s28630)) of
+ s28640 =>
+ (case ((sep_matches_prefix s28640)) of
+ Some ((_, s28650)) =>
+ (case ((string_drop s28640 s28650)) of
+ s28660 =>
+ (case ((reg_name_matches_prefix s28660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28670)) =>
+ (case ((string_drop s28660 s28670)) of
+ s1 => Some (size1, aq, rl, rd, rs1, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28520 :: " string "
+
+
+\<comment> \<open>\<open>val _s2839_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2839 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s2839 s28400 = (
+ (let s28410 = s28400 in
+ if ((string_startswith s28410 (''sfence.vma''))) then
+ (case ((string_drop s28410 ((string_length (''sfence.vma''))))) of
+ s28420 =>
+ (case ((spc_matches_prefix0 s28420)) of
+ Some ((_, s28430)) =>
+ (case ((string_drop s28420 s28430)) of
+ s28440 =>
+ (case ((reg_name_matches_prefix s28440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28450)) =>
+ (case ((string_drop s28440 s28450)) of
+ s28460 =>
+ (case ((sep_matches_prefix s28460)) of
+ Some ((_, s28470)) =>
+ (case ((string_drop s28460 s28470)) of
+ s28480 =>
+ (case ((reg_name_matches_prefix s28480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s28490)) =>
+ (case ((string_drop s28480 s28490)) of s1 => Some (rs1, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28400 :: " string "
+
+
+\<comment> \<open>\<open>val _s2835_ : string -> maybe string\<close>\<close>
+
+definition s2835 :: " string \<Rightarrow>(string)option " where
+ " s2835 s28360 = (
+ (let s28370 = s28360 in
+ if ((string_startswith s28370 (''wfi''))) then
+ (case ((string_drop s28370 ((string_length (''wfi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28360 :: " string "
+
+
+\<comment> \<open>\<open>val _s2831_ : string -> maybe string\<close>\<close>
+
+definition s2831 :: " string \<Rightarrow>(string)option " where
+ " s2831 s28320 = (
+ (let s28330 = s28320 in
+ if ((string_startswith s28330 (''ebreak''))) then
+ (case ((string_drop s28330 ((string_length (''ebreak''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2827_ : string -> maybe string\<close>\<close>
+
+definition s2827 :: " string \<Rightarrow>(string)option " where
+ " s2827 s28280 = (
+ (let s28290 = s28280 in
+ if ((string_startswith s28290 (''sret''))) then
+ (case ((string_drop s28290 ((string_length (''sret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28280 :: " string "
+
+
+\<comment> \<open>\<open>val _s2823_ : string -> maybe string\<close>\<close>
+
+definition s2823 :: " string \<Rightarrow>(string)option " where
+ " s2823 s28240 = (
+ (let s28250 = s28240 in
+ if ((string_startswith s28250 (''mret''))) then
+ (case ((string_drop s28250 ((string_length (''mret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28240 :: " string "
+
+
+\<comment> \<open>\<open>val _s2819_ : string -> maybe string\<close>\<close>
+
+definition s2819 :: " string \<Rightarrow>(string)option " where
+ " s2819 s28200 = (
+ (let s28210 = s28200 in
+ if ((string_startswith s28210 (''ecall''))) then
+ (case ((string_drop s28210 ((string_length (''ecall''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2815_ : string -> maybe string\<close>\<close>
+
+definition s2815 :: " string \<Rightarrow>(string)option " where
+ " s2815 s28160 = (
+ (let s28170 = s28160 in
+ if ((string_startswith s28170 (''fence.i''))) then
+ (case ((string_drop s28170 ((string_length (''fence.i''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2803_ : string -> maybe ((mword ty4 * mword ty4 * string))\<close>\<close>
+
+definition s2803 :: " string \<Rightarrow>((4)Word.word*(4)Word.word*string)option " where
+ " s2803 s28040 = (
+ (let s28050 = s28040 in
+ if ((string_startswith s28050 (''fence.tso''))) then
+ (case ((string_drop s28050 ((string_length (''fence.tso''))))) of
+ s28060 =>
+ (case ((spc_matches_prefix0 s28060)) of
+ Some ((_, s28070)) =>
+ (case ((string_drop s28060 s28070)) of
+ s28080 =>
+ (case ((fence_bits_matches_prefix s28080 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s28090)) =>
+ (case ((string_drop s28080 s28090)) of
+ s28100 =>
+ (case ((sep_matches_prefix s28100)) of
+ Some ((_, s28110)) =>
+ (case ((string_drop s28100 s28110)) of
+ s28120 =>
+ (case ((fence_bits_matches_prefix s28120 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s28130)) =>
+ (case ((string_drop s28120 s28130)) of s1 => Some (pred, succ, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28040 :: " string "
+
+
+\<comment> \<open>\<open>val _s2791_ : string -> maybe ((mword ty4 * mword ty4 * string))\<close>\<close>
+
+definition s2791 :: " string \<Rightarrow>((4)Word.word*(4)Word.word*string)option " where
+ " s2791 s27920 = (
+ (let s27930 = s27920 in
+ if ((string_startswith s27930 (''fence''))) then
+ (case ((string_drop s27930 ((string_length (''fence''))))) of
+ s27940 =>
+ (case ((spc_matches_prefix0 s27940)) of
+ Some ((_, s27950)) =>
+ (case ((string_drop s27940 s27950)) of
+ s27960 =>
+ (case ((fence_bits_matches_prefix s27960 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s27970)) =>
+ (case ((string_drop s27960 s27970)) of
+ s27980 =>
+ (case ((sep_matches_prefix s27980)) of
+ Some ((_, s27990)) =>
+ (case ((string_drop s27980 s27990)) of
+ s28000 =>
+ (case ((fence_bits_matches_prefix s28000 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s28010)) =>
+ (case ((string_drop s28000 s28010)) of s1 => Some (pred, succ, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s27920 :: " string "
+
+
+\<comment> \<open>\<open>val _s2774_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2774 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2774 s27760 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s27760)) of
+ Some ((op1, s27770)) =>
+ (case ((string_drop s27760 s27770)) of
+ s27780 =>
+ (case ((spc_matches_prefix0 s27780)) of
+ Some ((_, s27790)) =>
+ (case ((string_drop s27780 s27790)) of
+ s27800 =>
+ (case ((reg_name_matches_prefix s27800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27810)) =>
+ (case ((string_drop s27800 s27810)) of
+ s27820 =>
+ (case ((sep_matches_prefix s27820)) of
+ Some ((_, s27830)) =>
+ (case ((string_drop s27820 s27830)) of
+ s27840 =>
+ (case ((reg_name_matches_prefix s27840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27850)) =>
+ (case ((string_drop s27840 s27850)) of
+ s27860 =>
+ (case ((sep_matches_prefix s27860)) of
+ Some ((_, s27870)) =>
+ (case ((string_drop s27860 s27870)) of
+ s27880 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27880 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s27890)) =>
+ (case ((string_drop s27880 s27890)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2757_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2757 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2757 s27590 = (
+ (case ((rtypew_mnemonic_matches_prefix s27590)) of
+ Some ((op1, s27600)) =>
+ (case ((string_drop s27590 s27600)) of
+ s27610 =>
+ (case ((spc_matches_prefix0 s27610)) of
+ Some ((_, s27620)) =>
+ (case ((string_drop s27610 s27620)) of
+ s27630 =>
+ (case ((reg_name_matches_prefix s27630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27640)) =>
+ (case ((string_drop s27630 s27640)) of
+ s27650 =>
+ (case ((sep_matches_prefix s27650)) of
+ Some ((_, s27660)) =>
+ (case ((string_drop s27650 s27660)) of
+ s27670 =>
+ (case ((reg_name_matches_prefix s27670 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27680)) =>
+ (case ((string_drop s27670 s27680)) of
+ s27690 =>
+ (case ((sep_matches_prefix s27690)) of
+ Some ((_, s27700)) =>
+ (case ((string_drop s27690 s27700)) of
+ s27710 =>
+ (case ((reg_name_matches_prefix s27710 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s27720)) =>
+ (case ((string_drop s27710 s27720)) of
+ s1 => Some (op1, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27590 :: " string "
+
+
+\<comment> \<open>\<open>val _s2740_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2740 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2740 s27420 = (
+ (case ((shiftw_mnemonic_matches_prefix s27420)) of
+ Some ((op1, s27430)) =>
+ (case ((string_drop s27420 s27430)) of
+ s27440 =>
+ (case ((spc_matches_prefix0 s27440)) of
+ Some ((_, s27450)) =>
+ (case ((string_drop s27440 s27450)) of
+ s27460 =>
+ (case ((reg_name_matches_prefix s27460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27470)) =>
+ (case ((string_drop s27460 s27470)) of
+ s27480 =>
+ (case ((sep_matches_prefix s27480)) of
+ Some ((_, s27490)) =>
+ (case ((string_drop s27480 s27490)) of
+ s27500 =>
+ (case ((reg_name_matches_prefix s27500 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27510)) =>
+ (case ((string_drop s27500 s27510)) of
+ s27520 =>
+ (case ((sep_matches_prefix s27520)) of
+ Some ((_, s27530)) =>
+ (case ((string_drop s27520 s27530)) of
+ s27540 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27540 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s27550)) =>
+ (case ((string_drop s27540 s27550)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27420 :: " string "
+
+
+\<comment> \<open>\<open>val _s2724_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2724 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2724 s27250 = (
+ (let s27260 = s27250 in
+ if ((string_startswith s27260 (''addiw''))) then
+ (case ((string_drop s27260 ((string_length (''addiw''))))) of
+ s27270 =>
+ (case ((spc_matches_prefix0 s27270)) of
+ Some ((_, s27280)) =>
+ (case ((string_drop s27270 s27280)) of
+ s27290 =>
+ (case ((reg_name_matches_prefix s27290 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27300)) =>
+ (case ((string_drop s27290 s27300)) of
+ s27310 =>
+ (case ((sep_matches_prefix s27310)) of
+ Some ((_, s27320)) =>
+ (case ((string_drop s27310 s27320)) of
+ s27330 =>
+ (case ((reg_name_matches_prefix s27330 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27340)) =>
+ (case ((string_drop s27330 s27340)) of
+ s27350 =>
+ (case ((sep_matches_prefix s27350)) of
+ Some ((_, s27360)) =>
+ (case ((string_drop s27350 s27360)) of
+ s27370 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27370 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s27380)) =>
+ (case ((string_drop s27370 s27380)) of s1 => Some (rd, rs1, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s27250 :: " string "
+
+
+\<comment> \<open>\<open>val _s2696_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))\<close>\<close>
+
+definition s2696 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word*string)option " where
+ " s2696 s26970 = (
+ (let s26980 = s26970 in
+ if ((string_startswith s26980 (''s''))) then
+ (case ((string_drop s26980 ((string_length (''s''))))) of
+ s26990 =>
+ (case ((size_mnemonic_matches_prefix s26990)) of
+ Some ((size1, s27000)) =>
+ (case ((string_drop s26990 s27000)) of
+ s27010 =>
+ (case ((maybe_aq_matches_prefix s27010)) of
+ Some ((aq, s27020)) =>
+ (case ((string_drop s27010 s27020)) of
+ s27030 =>
+ (case ((maybe_rl_matches_prefix s27030)) of
+ Some ((rl, s27040)) =>
+ (case ((string_drop s27030 s27040)) of
+ s27050 =>
+ (case ((spc_matches_prefix0 s27050)) of
+ Some ((_, s27060)) =>
+ (case ((string_drop s27050 s27060)) of
+ s27070 =>
+ (case ((reg_name_matches_prefix s27070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s27080)) =>
+ (case ((string_drop s27070 s27080)) of
+ s27090 =>
+ (case ((sep_matches_prefix s27090)) of
+ Some ((_, s27100)) =>
+ (case ((string_drop s27090 s27100)) of
+ s27110 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27110 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s27120)) =>
+ (case ((string_drop s27110 s27120)) of
+ s27130 =>
+ (case ((opt_spc_matches_prefix0 s27130)) of
+ Some ((_, s27140)) =>
+ (let s27150 = (string_drop s27130 s27140) in
+ if ((string_startswith s27150 (''(''))) then
+ (case ((string_drop s27150 ((string_length (''(''))))) of
+ s27160 =>
+ (case ((opt_spc_matches_prefix0 s27160)) of
+ Some ((_, s27170)) =>
+ (case ((string_drop s27160 s27170)) of
+ s27180 =>
+ (case ((reg_name_matches_prefix s27180 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27190)) =>
+ (case ((string_drop s27180 s27190)) of
+ s27200 =>
+ (case ((opt_spc_matches_prefix0 s27200)) of
+ Some ((_, s27210)) =>
+ (let s27220 = (string_drop s27200 s27210) in
+ if ((string_startswith s27220 ('')''))) then
+ (case ((string_drop s27220 ((string_length ('')''))))) of
+ s1 =>
+ Some (size1, aq, rl, rs2, imm, rs1, s1)
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s26970 :: " string "
+
+
+\<comment> \<open>\<open>val _s2666_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))\<close>\<close>
+
+definition s2666 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word*string)option " where
+ " s2666 s26670 = (
+ (let s26680 = s26670 in
+ if ((string_startswith s26680 (''l''))) then
+ (case ((string_drop s26680 ((string_length (''l''))))) of
+ s26690 =>
+ (case ((size_mnemonic_matches_prefix s26690)) of
+ Some ((size1, s26700)) =>
+ (case ((string_drop s26690 s26700)) of
+ s26710 =>
+ (case ((maybe_u_matches_prefix s26710)) of
+ Some ((is_unsigned, s26720)) =>
+ (case ((string_drop s26710 s26720)) of
+ s26730 =>
+ (case ((maybe_aq_matches_prefix s26730)) of
+ Some ((aq, s26740)) =>
+ (case ((string_drop s26730 s26740)) of
+ s26750 =>
+ (case ((maybe_rl_matches_prefix s26750)) of
+ Some ((rl, s26760)) =>
+ (case ((string_drop s26750 s26760)) of
+ s26770 =>
+ (case ((spc_matches_prefix0 s26770)) of
+ Some ((_, s26780)) =>
+ (case ((string_drop s26770 s26780)) of
+ s26790 =>
+ (case ((reg_name_matches_prefix s26790 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26800)) =>
+ (case ((string_drop s26790 s26800)) of
+ s26810 =>
+ (case ((sep_matches_prefix s26810)) of
+ Some ((_, s26820)) =>
+ (case ((string_drop s26810 s26820)) of
+ s26830 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26830 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s26840)) =>
+ (case ((string_drop s26830 s26840)) of
+ s26850 =>
+ (case ((opt_spc_matches_prefix0 s26850)) of
+ Some ((_, s26860)) =>
+ (let s26870 = (string_drop s26850 s26860) in
+ if ((string_startswith s26870 (''(''))) then
+ (case ((string_drop s26870 ((string_length (''(''))))) of
+ s26880 =>
+ (case ((opt_spc_matches_prefix0 s26880)) of
+ Some ((_, s26890)) =>
+ (case ((string_drop s26880 s26890)) of
+ s26900 =>
+ (case ((reg_name_matches_prefix s26900 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26910)) =>
+ (case ((string_drop s26900 s26910)) of
+ s26920 =>
+ (case ((opt_spc_matches_prefix0 s26920)) of
+ Some ((_, s26930)) =>
+ (let s26940 = (string_drop s26920 s26930) in
+ if ((string_startswith s26940 ('')''))) then
+ (case ((string_drop s26940 ((string_length ('')''))))) of
+ s1 =>
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1, s1)
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s26670 :: " string "
+
+
+\<comment> \<open>\<open>val _s2649_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2649 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2649 s26510 = (
+ (case ((rtype_mnemonic_matches_prefix s26510)) of
+ Some ((op1, s26520)) =>
+ (case ((string_drop s26510 s26520)) of
+ s26530 =>
+ (case ((spc_matches_prefix0 s26530)) of
+ Some ((_, s26540)) =>
+ (case ((string_drop s26530 s26540)) of
+ s26550 =>
+ (case ((reg_name_matches_prefix s26550 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26560)) =>
+ (case ((string_drop s26550 s26560)) of
+ s26570 =>
+ (case ((sep_matches_prefix s26570)) of
+ Some ((_, s26580)) =>
+ (case ((string_drop s26570 s26580)) of
+ s26590 =>
+ (case ((reg_name_matches_prefix s26590 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26600)) =>
+ (case ((string_drop s26590 s26600)) of
+ s26610 =>
+ (case ((sep_matches_prefix s26610)) of
+ Some ((_, s26620)) =>
+ (case ((string_drop s26610 s26620)) of
+ s26630 =>
+ (case ((reg_name_matches_prefix s26630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s26640)) =>
+ (case ((string_drop s26630 s26640)) of
+ s1 => Some (op1, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26510 :: " string "
+
+
+\<comment> \<open>\<open>val _s2632_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s2632 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word*string)option " where
+ " s2632 s26340 = (
+ (case ((shiftiop_mnemonic_matches_prefix s26340)) of
+ Some ((op1, s26350)) =>
+ (case ((string_drop s26340 s26350)) of
+ s26360 =>
+ (case ((spc_matches_prefix0 s26360)) of
+ Some ((_, s26370)) =>
+ (case ((string_drop s26360 s26370)) of
+ s26380 =>
+ (case ((reg_name_matches_prefix s26380 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26390)) =>
+ (case ((string_drop s26380 s26390)) of
+ s26400 =>
+ (case ((sep_matches_prefix s26400)) of
+ Some ((_, s26410)) =>
+ (case ((string_drop s26400 s26410)) of
+ s26420 =>
+ (case ((reg_name_matches_prefix s26420 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26430)) =>
+ (case ((string_drop s26420 s26430)) of
+ s26440 =>
+ (case ((sep_matches_prefix s26440)) of
+ Some ((_, s26450)) =>
+ (case ((string_drop s26440 s26450)) of
+ s26460 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26460 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s26470)) =>
+ (case ((string_drop s26460 s26470)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26340 :: " string "
+
+
+\<comment> \<open>\<open>val _s2615_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2615 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2615 s26170 = (
+ (case ((itype_mnemonic_matches_prefix s26170)) of
+ Some ((op1, s26180)) =>
+ (case ((string_drop s26170 s26180)) of
+ s26190 =>
+ (case ((spc_matches_prefix0 s26190)) of
+ Some ((_, s26200)) =>
+ (case ((string_drop s26190 s26200)) of
+ s26210 =>
+ (case ((reg_name_matches_prefix s26210 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26220)) =>
+ (case ((string_drop s26210 s26220)) of
+ s26230 =>
+ (case ((sep_matches_prefix s26230)) of
+ Some ((_, s26240)) =>
+ (case ((string_drop s26230 s26240)) of
+ s26250 =>
+ (case ((reg_name_matches_prefix s26250 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26260)) =>
+ (case ((string_drop s26250 s26260)) of
+ s26270 =>
+ (case ((sep_matches_prefix s26270)) of
+ Some ((_, s26280)) =>
+ (case ((string_drop s26270 s26280)) of
+ s26290 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26290 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s26300)) =>
+ (case ((string_drop s26290 s26300)) of
+ s1 => Some (op1, rd, rs1, imm, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26170 :: " string "
+
+
+\<comment> \<open>\<open>val _s2598_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13 * string))\<close>\<close>
+
+definition s2598 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word*string)option " where
+ " s2598 s26000 = (
+ (case ((btype_mnemonic_matches_prefix s26000)) of
+ Some ((op1, s26010)) =>
+ (case ((string_drop s26000 s26010)) of
+ s26020 =>
+ (case ((spc_matches_prefix0 s26020)) of
+ Some ((_, s26030)) =>
+ (case ((string_drop s26020 s26030)) of
+ s26040 =>
+ (case ((reg_name_matches_prefix s26040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26050)) =>
+ (case ((string_drop s26040 s26050)) of
+ s26060 =>
+ (case ((sep_matches_prefix s26060)) of
+ Some ((_, s26070)) =>
+ (case ((string_drop s26060 s26070)) of
+ s26080 =>
+ (case ((reg_name_matches_prefix s26080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s26090)) =>
+ (case ((string_drop s26080 s26090)) of
+ s26100 =>
+ (case ((sep_matches_prefix s26100)) of
+ Some ((_, s26110)) =>
+ (case ((string_drop s26100 s26110)) of
+ s26120 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26120 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s26130)) =>
+ (case ((string_drop s26120 s26130)) of
+ s1 => Some (op1, rs1, rs2, imm, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26000 :: " string "
+
+
+\<comment> \<open>\<open>val _s2582_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2582 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2582 s25830 = (
+ (let s25840 = s25830 in
+ if ((string_startswith s25840 (''jalr''))) then
+ (case ((string_drop s25840 ((string_length (''jalr''))))) of
+ s25850 =>
+ (case ((spc_matches_prefix0 s25850)) of
+ Some ((_, s25860)) =>
+ (case ((string_drop s25850 s25860)) of
+ s25870 =>
+ (case ((reg_name_matches_prefix s25870 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25880)) =>
+ (case ((string_drop s25870 s25880)) of
+ s25890 =>
+ (case ((sep_matches_prefix s25890)) of
+ Some ((_, s25900)) =>
+ (case ((string_drop s25890 s25900)) of
+ s25910 =>
+ (case ((reg_name_matches_prefix s25910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25920)) =>
+ (case ((string_drop s25910 s25920)) of
+ s25930 =>
+ (case ((sep_matches_prefix s25930)) of
+ Some ((_, s25940)) =>
+ (case ((string_drop s25930 s25940)) of
+ s25950 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25950 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s25960)) =>
+ (case ((string_drop s25950 s25960)) of s1 => Some (rd, rs1, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25830 :: " string "
+
+
+\<comment> \<open>\<open>val _s2570_ : string -> maybe ((mword ty5 * mword ty21 * string))\<close>\<close>
+
+definition s2570 :: " string \<Rightarrow>((5)Word.word*(21)Word.word*string)option " where
+ " s2570 s25710 = (
+ (let s25720 = s25710 in
+ if ((string_startswith s25720 (''jal''))) then
+ (case ((string_drop s25720 ((string_length (''jal''))))) of
+ s25730 =>
+ (case ((spc_matches_prefix0 s25730)) of
+ Some ((_, s25740)) =>
+ (case ((string_drop s25730 s25740)) of
+ s25750 =>
+ (case ((reg_name_matches_prefix s25750 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25760)) =>
+ (case ((string_drop s25750 s25760)) of
+ s25770 =>
+ (case ((sep_matches_prefix s25770)) of
+ Some ((_, s25780)) =>
+ (case ((string_drop s25770 s25780)) of
+ s25790 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25790 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s25800)) =>
+ (case ((string_drop s25790 s25800)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25710 :: " string "
+
+
+\<comment> \<open>\<open>val _s2557_ : string -> maybe ((uop * mword ty5 * mword ty20 * string))\<close>\<close>
+
+definition s2557 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word*string)option " where
+ " s2557 s25590 = (
+ (case ((utype_mnemonic_matches_prefix s25590)) of
+ Some ((op1, s25600)) =>
+ (case ((string_drop s25590 s25600)) of
+ s25610 =>
+ (case ((spc_matches_prefix0 s25610)) of
+ Some ((_, s25620)) =>
+ (case ((string_drop s25610 s25620)) of
+ s25630 =>
+ (case ((reg_name_matches_prefix s25630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25640)) =>
+ (case ((string_drop s25630 s25640)) of
+ s25650 =>
+ (case ((sep_matches_prefix s25650)) of
+ Some ((_, s25660)) =>
+ (case ((string_drop s25650 s25660)) of
+ s25670 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25670 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s25680)) =>
+ (case ((string_drop s25670 s25680)) of s1 => Some (op1, rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s25590 :: " string "
+
+
+definition assembly_matches_prefix :: " string \<Rightarrow>(ast*int)option " where
+ " assembly_matches_prefix arg1 = (
+ (let s25690 = arg1 in
+ if ((case ((s2557 s25690 :: ((uop * 5 Word.word * 20 Word.word * string))option)) of
+ Some ((op1, rd, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2557 s25690 :: (( uop * 5 Word.word * 20 Word.word * string)) option) of
+ (Some ((op1, rd, imm, s1))) =>
+ Some (UTYPE (imm, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2570 s25690 :: (( 5 Word.word * 21 Word.word * string))option)) of
+ Some ((rd, imm, s1)) => True
+ | _ => False
+ )) then (case (s2570 s25690 :: (( 5 Word.word * 21 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (RISCV_JAL (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2582 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((rd, rs1, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2582 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((rd, rs1, imm, s1))) =>
+ Some
+ (RISCV_JALR (imm, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2598 s25690 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word * string))option)) of
+ Some ((op1, rs1, rs2, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2598 s25690 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word * string)) option) of
+ (Some ((op1, rs1, rs2, imm, s1))) =>
+ Some
+ (BTYPE (imm, rs2, rs1, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2615 s25690 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2615 s25690 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, imm, s1))) =>
+ Some
+ (ITYPE (imm, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2632 s25690 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => True
+ | _ => False
+ )) then (case
+ (s2632 s25690 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTIOP (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2649 s25690 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2649 s25690 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, rs2, s1))) =>
+ Some
+ (RTYPE (rs2, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2666 s25690
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2666 s25690
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1, s1))) =>
+ Some
+ (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2696 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2696 s25690
+ :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1, s1))) =>
+ Some
+ (STORE (imm, rs2, rs1, size1, aq, rl),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2724 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((rd, rs1, imm, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2724 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((rd, rs1, imm, s1))) =>
+ Some (ADDIW (imm, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2740 s25690 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2740 s25690 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTW (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2757 s25690 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, rs2, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2757 s25690 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, rs2, s1))) =>
+ Some
+ (RTYPEW (rs2, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2774 s25690 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2774 s25690 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTIWOP (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2791 s25690 :: (( 4 Word.word * 4 Word.word * string))option)) of
+ Some ((pred, succ, s1)) => True
+ | _ => False
+ )) then (case (s2791 s25690 :: (( 4 Word.word * 4 Word.word * string)) option) of
+ (Some ((pred, succ, s1))) =>
+ Some (FENCE (pred, succ), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2803 s25690 :: (( 4 Word.word * 4 Word.word * string))option)) of
+ Some ((pred, succ, s1)) => True
+ | _ => False
+ )) then (case (s2803 s25690 :: (( 4 Word.word * 4 Word.word * string)) option) of
+ (Some ((pred, succ, s1))) =>
+ Some (FENCE_TSO (pred, succ), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2815 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2815 s25690 of
+ (Some (s1)) =>
+ Some (FENCEI () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2819 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2819 s25690 of
+ (Some (s1)) =>
+ Some (ECALL () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2823 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2823 s25690 of
+ (Some (s1)) =>
+ Some (MRET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2827 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2827 s25690 of
+ (Some (s1)) =>
+ Some (SRET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2831 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2831 s25690 of
+ (Some (s1)) =>
+ Some (EBREAK () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2835 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2835 s25690 of
+ (Some (s1)) =>
+ Some (WFI () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2839 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case (s2839 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rs1, rs2, s1))) =>
+ Some (SFENCE_VMA (rs1, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2851 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rd, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2851 s25690 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rd, rs1, s1))) =>
+ Some
+ (LOADRES (aq, rl, rs1, size1, rd), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2869 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2869 s25690
+ :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2, s1))) =>
+ Some
+ (STORECON (aq, rl, rs2, rs1, size1, rd),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2891 s25690
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2891 s25690
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2, s1))) =>
+ Some
+ (AMO (op1, aq, rl, rs2, rs1, width, rd),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2915 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2915 s25690 of
+ (Some (s1)) =>
+ Some (C_NOP () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2919 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rdc, nzimm, s1)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s2919 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rdc, nzimm, s1))) =>
+ Some
+ (C_ADDI4SPN (rdc, nzimm), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2931 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rdc, rsc, uimm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2931 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rdc, rsc, uimm, s1))) =>
+ Some (C_LW (uimm, rsc, rdc), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2947 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rdc, rsc, uimm, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2947 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rdc, rsc, uimm, s1))) =>
+ Some (C_LD (uimm, rsc, rdc), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2963 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rsc1, rsc2, uimm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2963 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsc1, rsc2, uimm, s1))) =>
+ Some
+ (C_SW (uimm, rsc1, rsc2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2979 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rsc1, rsc2, uimm, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2979 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsc1, rsc2, uimm, s1))) =>
+ Some
+ (C_SD (uimm, rsc1, rsc2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2995 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, nzi, s1)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2995 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, nzi, s1))) =>
+ Some (C_ADDI (nzi, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3007 s25690 :: (( 11 Word.word * string))option)) of
+ Some ((imm, s1)) => ((( 32 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s3007 s25690 :: (( 11 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_JAL imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3015 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, imm, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3015 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, imm, s1))) =>
+ Some (C_ADDIW (imm, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3027 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, imm, s1)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3027 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (C_LI (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3039 s25690 :: (( 6 Word.word * string))option)) of
+ Some ((imm, s1)) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3039 s25690 :: (( 6 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_ADDI16SP imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3047 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, imm, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s3047 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (C_LUI (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3059 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3059 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SRLI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3071 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3071 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SRAI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3083 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, imm, s1)) => True
+ | _ => False
+ )) then (case (s3083 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, imm, s1))) =>
+ Some (C_ANDI (imm, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3095 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3095 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_SUB (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3107 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3107 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_XOR (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3119 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3119 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_OR (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3131 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3131 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_AND (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3143 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3143 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_SUBW (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3155 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3155 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_ADDW (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3167 s25690 :: (( 11 Word.word * string))option)) of
+ Some ((imm, s1)) => True
+ | _ => False
+ )) then (case (s3167 s25690 :: (( 11 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_J imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3175 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rs, imm, s1)) => True
+ | _ => False
+ )) then (case (s3175 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rs, imm, s1))) =>
+ Some (C_BEQZ (imm, rs), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3187 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rs, imm, s1)) => True
+ | _ => False
+ )) then (case (s3187 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rs, imm, s1))) =>
+ Some (C_BNEZ (imm, rs), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3199 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3199 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SLLI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3211 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3211 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_LWSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3223 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 32 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s3223 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_LDSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3235 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) => True
+ | _ => False
+ )) then (case (s3235 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_SWSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3247 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rs2, uimm, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3247 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rs2, uimm, s1))) =>
+ Some (C_SDSP (uimm, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3259 s25690 :: (( 5 Word.word * string))option)) of
+ Some ((rs1, s1)) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3259 s25690 :: (( 5 Word.word * string)) option) of
+ (Some ((rs1, s1))) =>
+ Some (C_JR rs1, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3267 s25690 :: (( 5 Word.word * string))option)) of
+ Some ((rs1, s1)) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3267 s25690 :: (( 5 Word.word * string)) option) of
+ (Some ((rs1, s1))) =>
+ Some (C_JALR rs1, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3275 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rd, rs2, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3275 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rd, rs2, s1))) =>
+ Some (C_MV (rd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3287 s25690)) of Some (s1) => True | _ => False )) then
+ (case s3287 s25690 of
+ (Some (s1)) =>
+ Some (C_EBREAK () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3291 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3291 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_ADD (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3303 s25690
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s3303 s25690 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2, s1))) =>
+ Some
+ (MUL (rs2, rs1, rd, high, signed1, signed2),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3320 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => True
+ | _ => False
+ )) then (case
+ (s3320 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (DIV (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3338 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => True
+ | _ => False
+ )) then (case
+ (s3338 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (REM (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3356 s25690 :: (( 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rd, rs1, rs2, s1)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3356 s25690 :: (( 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rd, rs1, rs2, s1))) =>
+ Some (MULW (rs2, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3372 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3372 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (DIVW (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3391 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => ((( 32 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3391 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (REMW (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3410 s25690 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, csr, s1)) => True
+ | _ => False
+ )) then (case
+ (s3410 s25690 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, csr, s1))) =>
+ Some
+ (CSR (csr, rs1, rd, True, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s3428 s25690 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, csr, s1)) => True
+ | _ => False
+ )) then (case
+ (s3428 s25690 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, csr, s1))) =>
+ Some
+ (CSR (csr, rs1, rd, False, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s3445 s25690)) of Some (s1) => True | _ => False )) then
+ (case s3445 s25690 of
+ (Some (s1)) =>
+ Some (URET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3449 s25690 :: (( 32 Word.word * string))option)) of
+ Some ((s, s2)) => True
+ | _ => False
+ )) then (case (s3449 s25690 :: (( 32 Word.word * string)) option) of
+ (Some ((s, s2))) =>
+ Some (ILLEGAL s, ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3457 s25690 :: (( 16 Word.word * string))option)) of
+ Some ((s, s2)) => True
+ | _ => False
+ )) then (case (s3457 s25690 :: (( 16 Word.word * string)) option) of
+ (Some ((s, s2))) =>
+ Some (C_ILLEGAL s, ((string_length arg1)) - ((string_length s2)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+definition print_insn :: " ast \<Rightarrow>((register_value),(string),(exception))monad " where
+ " print_insn insn = ( assembly_forwards insn )"
+ for insn :: " ast "
+
+
+\<comment> \<open>\<open>val decode : mword ty32 -> M ast\<close>\<close>
+
+definition decode :: "(32)Word.word \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " decode bv = ( encdec_backwards bv )"
+ for bv :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val decodeCompressed : mword ty16 -> ast\<close>\<close>
+
+definition decodeCompressed :: "(16)Word.word \<Rightarrow> ast " where
+ " decodeCompressed bv = ( encdec_compressed_backwards bv )"
+ for bv :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val ext_init : unit -> unit\<close>\<close>
+
+definition ext_init :: " unit \<Rightarrow> unit " where
+ " ext_init _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_fetch_hook : FetchResult -> FetchResult\<close>\<close>
+
+definition ext_fetch_hook :: " FetchResult \<Rightarrow> FetchResult " where
+ " ext_fetch_hook f = ( f )"
+ for f :: " FetchResult "
+
+
+\<comment> \<open>\<open>val ext_pre_step_hook : unit -> unit\<close>\<close>
+
+definition ext_pre_step_hook :: " unit \<Rightarrow> unit " where
+ " ext_pre_step_hook _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_post_step_hook : unit -> unit\<close>\<close>
+
+definition ext_post_step_hook :: " unit \<Rightarrow> unit " where
+ " ext_post_step_hook _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_post_decode_hook : ast -> M ast\<close>\<close>
+
+definition ext_post_decode_hook :: " ast \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " ext_post_decode_hook x = ( return x )"
+ for x :: " ast "
+
+
+\<comment> \<open>\<open>val isRVC : mword ty16 -> bool\<close>\<close>
+
+definition isRVC :: "(16)Word.word \<Rightarrow> bool " where
+ " isRVC h = (
+ \<not> (((((subrange_vec_dec h (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))"
+ for h :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val fetch : unit -> M FetchResult\<close>\<close>
+
+definition fetch :: " unit \<Rightarrow>((register_value),(FetchResult),(exception))monad " where
+ " fetch _ = (
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) .
+ (case ((ext_fetch_check_pc w__0 w__1)) of
+ Ext_FetchAddr_Error (e) => return (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc) =>
+ or_boolM
+ (return (((((cast_unit_vec0 ((access_vec_dec use_pc (( 0 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))
+ (and_boolM
+ (return (((((cast_unit_vec0 ((access_vec_dec use_pc (( 1 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))
+ (haveRVC () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) .
+ return (F_Error (E_Fetch_Addr_Align, w__5)))
+ else
+ (translateAddr use_pc Execute :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__6 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__6 of
+ TR_Failure (e) =>
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) .
+ return (F_Error (e, w__7)))
+ | TR_Address (ppclo) =>
+ (mem_read Execute ppclo (( 2 :: int)::ii) False False False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__8 :: ( 16 Word.word)
+ MemoryOpResult) .
+ (case w__8 of
+ MemException (e) =>
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) .
+ return (F_Error (E_Fetch_Access_Fault, w__9)))
+ | MemValue (ilo) =>
+ if ((isRVC ilo)) then return (F_RVC ilo)
+ else
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) .
+ (let (PC_hi :: xlenbits) = ((add_vec_int w__10 (( 2 :: int)::ii) :: 32 Word.word)) in
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 Word.word) .
+ (case ((ext_fetch_check_pc w__11 PC_hi)) of
+ Ext_FetchAddr_Error (e) => return (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc_hi) =>
+ (translateAddr use_pc_hi Execute :: ( (( 32 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__12 :: (( 32 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__12 of
+ TR_Failure (e) => return (F_Error (e, PC_hi))
+ | TR_Address (ppchi) =>
+ (mem_read Execute ppchi (( 2 :: int)::ii) False False False
+ :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__13 :: ( 16 Word.word)
+ MemoryOpResult) .
+ return ((case w__13 of
+ MemException (e) => F_Error (E_Fetch_Access_Fault, PC_hi)
+ | MemValue (ihi) => F_Base ((concat_vec ihi ilo :: 32 Word.word))
+ )))
+ ))
+ ))))
+ ))
+ )))
+ ))))"
+
+
+\<comment> \<open>\<open>val step : ii -> M bool\<close>\<close>
+
+definition step :: " int \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " step step_no = (
+ (let (_ :: unit) = (ext_pre_step_hook () ) in
+ (write_reg minstret_written_ref False \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__0 :: Privilege) .
+ dispatchInterrupt w__0 \<bind> (\<lambda> (w__1 :: ((InterruptType * Privilege))option) .
+ (case w__1 of
+ Some ((intr, priv)) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_instr () )) then
+ print_bits0 (''Handling interrupt: '') ((interruptType_to_bits intr :: 8 Word.word))
+ else () ) in
+ handle_interrupt intr priv \<then> return (RETIRE_FAIL, False))
+ | None =>
+ fetch () \<bind> (\<lambda> (w__2 :: FetchResult) .
+ (let (f :: FetchResult) = (ext_fetch_hook w__2) in
+ (case f of
+ F_Ext_Error (e) =>
+ (let (_ :: unit) = (ext_handle_fetch_check_error e) in
+ return (RETIRE_FAIL, False))
+ | F_Error ((e, addr)) => handle_mem_exception addr e \<then> return (RETIRE_FAIL, False)
+ | F_RVC (h) =>
+ (let ast = (decodeCompressed h) in
+ ((if ((get_config_print_instr () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__3 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) .
+ print_insn ast \<bind> (\<lambda> (w__5 :: string) .
+ return ((print_dbg
+ (((@) (''['')
+ (((@) ((stringFromInteger step_no))
+ (((@) (''] ['')
+ (((@) ((privLevel_to_str w__3))
+ (((@) ('']: '')
+ (((@) ((string_of_bits w__4))
+ (((@) ('' ('')
+ (((@) ((string_of_bits h))
+ (((@) ('') '') w__5)))))))))))))))))))))))
+ else return () ) \<then>
+ haveRVC () ) \<bind> (\<lambda> (w__6 :: bool) .
+ if w__6 then
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) .
+ (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii) :: 32 Word.word)) \<then>
+ ext_post_decode_hook ast) \<bind> (\<lambda> (w__8 :: ast) .
+ execute w__8 \<bind> (\<lambda> (w__9 :: Retired) . return (w__9, True))))
+ else handle_illegal () \<then> return (RETIRE_FAIL, True)))
+ | F_Base (w) =>
+ decode w \<bind> (\<lambda> ast .
+ ((if ((get_config_print_instr () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__11 :: Privilege) .
+ (read_reg PC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) .
+ print_insn ast \<bind> (\<lambda> (w__13 :: string) .
+ return ((print_dbg
+ (((@) (''['')
+ (((@) ((stringFromInteger step_no))
+ (((@) (''] ['')
+ (((@) ((privLevel_to_str w__11))
+ (((@) ('']: '')
+ (((@) ((string_of_bits w__12))
+ (((@) ('' ('')
+ (((@) ((string_of_bits w))
+ (((@) ('') '') w__13)))))))))))))))))))))))
+ else return () ) \<then>
+ (read_reg PC_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 Word.word) .
+ (write_reg nextPC_ref ((add_vec_int w__14 (( 4 :: int)::ii) :: 32 Word.word)) \<then>
+ ext_post_decode_hook ast) \<bind> (\<lambda> (w__15 :: ast) .
+ execute w__15 \<bind> (\<lambda> (w__16 :: Retired) . return (w__16, True)))))
+ )))
+ ) \<bind> (\<lambda> varstup . (let ((retired :: Retired), (stepped :: bool)) = varstup in
+ (tick_pc () \<then>
+ (case retired of RETIRE_SUCCESS => retire_instruction () | RETIRE_FAIL => return () )) \<then>
+ ((let (_ :: unit) = (ext_post_step_hook () ) in
+ return stepped))))))))"
+ for step_no :: " int "
+
+
+\<comment> \<open>\<open>val loop : unit -> M unit\<close>\<close>
+
+definition loop :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " loop _ = (
+ (let insns_per_tick = (plat_insns_per_tick () ) in
+ (let (i :: ii) = ((( 0 :: int)::ii)) in
+ (let (step_no :: ii) = ((( 0 :: int)::ii)) in
+ (whileM (i, step_no)
+ (\<lambda> varstup . (let (i, step_no) = varstup in
+ read_reg htif_done_ref \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0)))))
+ (\<lambda> varstup . (let (i, step_no) = varstup in
+ step step_no \<bind> (\<lambda> stepped .
+ (let (step_no :: ii) = (if stepped then step_no + (( 1 :: int)::ii) else step_no) in
+ read_reg htif_done_ref \<bind> (\<lambda> (w__1 :: bool) .
+ (if w__1 then
+ (read_reg htif_exit_code_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let exit_val = (Word.uint w__2) in
+ return ((let _ =
+ (if (((exit_val = (( 0 :: int)::ii)))) then print_endline (''SUCCESS'')
+ else print_int (''FAILURE: '') exit_val) in
+ i))))
+ else
+ (let i = (i + (( 1 :: int)::ii)) in
+ if (((i = insns_per_tick))) then (tick_clock () \<then> tick_platform () ) \<then> return (( 0 :: int)::ii)
+ else return i)) \<bind> (\<lambda> (i :: ii) .
+ return (i, step_no)))))))) \<bind> (\<lambda> varstup . (let ((i :: ii), (step_no :: ii)) = varstup in
+ return () ))))))"
+
+
+\<comment> \<open>\<open>val init_model : unit -> M unit\<close>\<close>
+
+definition init_model :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_model _ = (
+ ((init_platform () \<then>
+ init_sys () ) \<then>
+ init_vmem () ) \<then>
+ ((let (_ :: unit) = (ext_init () ) in
+ ext_init_regs () )))"
+
+
+
+end
diff --git a/prover_snapshots/isabelle/RV32/RiscvAuxiliary.thy b/prover_snapshots/isabelle/RV32/RiscvAuxiliary.thy
new file mode 100644
index 0000000..b560b60
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/RiscvAuxiliary.thy
@@ -0,0 +1,35 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV32/riscv.lem\<close>.\<close>
+
+theory "RiscvAuxiliary"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+ "Riscv_types"
+ "Riscv_extras"
+ "Riscv"
+
+begin
+
+
+\<comment> \<open>\<open>**************************************************\<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> Termination Proofs \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open>**************************************************\<close>\<close>
+
+termination n_leading_spaces0 by lexicographic_order
+
+termination walk32 by lexicographic_order
+
+termination execute by lexicographic_order
+
+
+
+end
diff --git a/prover_snapshots/isabelle/RV32/Riscv_extras.thy b/prover_snapshots/isabelle/RV32/Riscv_extras.thy
new file mode 100644
index 0000000..3b3515c
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/Riscv_extras.thy
@@ -0,0 +1,362 @@
+chapter \<open>Generated by Lem from \<open>handwritten_support/riscv_extras.lem\<close>.\<close>
+
+theory "Riscv_extras"
+
+imports
+ Main
+ "LEM.Lem_pervasives"
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+
+type_synonym 'a bitvector =" ( 'a::len)Word.word "
+
+definition MEM_fence_rw_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_rw _ = ( barrier Barrier_RISCV_rw_rw )"
+
+definition MEM_fence_r_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_rw _ = ( barrier Barrier_RISCV_r_rw )"
+
+definition MEM_fence_r_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_r _ = ( barrier Barrier_RISCV_r_r )"
+
+definition MEM_fence_rw_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_w _ = ( barrier Barrier_RISCV_rw_w )"
+
+definition MEM_fence_w_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_w _ = ( barrier Barrier_RISCV_w_w )"
+
+definition MEM_fence_w_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_rw _ = ( barrier Barrier_RISCV_w_rw )"
+
+definition MEM_fence_rw_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_r _ = ( barrier Barrier_RISCV_rw_r )"
+
+definition MEM_fence_r_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_w _ = ( barrier Barrier_RISCV_r_w )"
+
+definition MEM_fence_w_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_r _ = ( barrier Barrier_RISCV_w_r )"
+
+definition MEM_fence_tso :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_tso _ = ( barrier Barrier_RISCV_tso )"
+
+definition MEM_fence_i :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_i _ = ( barrier Barrier_RISCV_i )"
+
+
+\<comment> \<open>\<open>val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+
+definition MEMea :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_strong_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_conditional addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_conditional_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "
+ where
+ " MEMea_conditional_strong_release addr size1
+ = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+
+\<comment> \<open>\<open>val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+
+definition MEMr :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_strong_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved_strong_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+
+definition MEMw :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_strong_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_strong_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional_strong_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional_strong_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit\<close>\<close>
+definition load_reservation :: "('a::len)Word.word \<Rightarrow> unit " where
+ " load_reservation addr = ( () )"
+ for addr :: "('a::len)Word.word "
+
+
+definition speculate_conditional_success :: " unit \<Rightarrow>('b,(bool),'a)monad " where
+ " speculate_conditional_success _ = ( excl_result () )"
+
+
+definition match_reservation :: " 'a \<Rightarrow> bool " where
+ " match_reservation _ = ( True )"
+
+definition cancel_reservation :: " unit \<Rightarrow> unit " where
+ " cancel_reservation _ = ( () )"
+
+
+\<comment> \<open>\<open>val sys_enable_writable_misa : unit -> bool\<close>\<close>
+definition sys_enable_writable_misa :: " unit \<Rightarrow> bool " where
+ " sys_enable_writable_misa _ = ( True )"
+
+
+\<comment> \<open>\<open>val sys_enable_rvc : unit -> bool\<close>\<close>
+definition sys_enable_rvc :: " unit \<Rightarrow> bool " where
+ " sys_enable_rvc _ = ( True )"
+
+
+\<comment> \<open>\<open>val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_ram_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_ram_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_ram_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_ram_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_rom_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_rom_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_rom_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_rom_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_clint_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_clint_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_clint_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_clint_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_enable_dirty_update : unit -> bool\<close>\<close>
+definition plat_enable_dirty_update :: " unit \<Rightarrow> bool " where
+ " plat_enable_dirty_update _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_enable_misaligned_access : unit -> bool\<close>\<close>
+definition plat_enable_misaligned_access :: " unit \<Rightarrow> bool " where
+ " plat_enable_misaligned_access _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_enable_pmp : unit -> bool\<close>\<close>
+definition plat_enable_pmp :: " unit \<Rightarrow> bool " where
+ " plat_enable_pmp _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_mtval_has_illegal_inst_bits : unit -> bool\<close>\<close>
+definition plat_mtval_has_illegal_inst_bits :: " unit \<Rightarrow> bool " where
+ " plat_mtval_has_illegal_inst_bits _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_insns_per_tick : unit -> integer\<close>\<close>
+definition plat_insns_per_tick :: " unit \<Rightarrow> int " where
+ " plat_insns_per_tick _ = (( 1 :: int))"
+
+
+\<comment> \<open>\<open>val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_htif_tohost :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_htif_tohost _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit\<close>\<close>
+definition plat_term_write :: "('a::len)Word.word \<Rightarrow> unit " where
+ " plat_term_write _ = ( () )"
+
+
+\<comment> \<open>\<open>val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_term_read :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_term_read _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a\<close>\<close>
+definition shift_bits_right :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " shift_bits_right v m = ( shiftr v (Word.uint m))"
+ for v :: "('a::len)Word.word "
+ and m :: "('b::len)Word.word "
+
+\<comment> \<open>\<open>val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a\<close>\<close>
+definition shift_bits_left :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " shift_bits_left v m = ( shiftl v (Word.uint m))"
+ for v :: "('a::len)Word.word "
+ and m :: "('b::len)Word.word "
+
+
+\<comment> \<open>\<open>val print_string : string -> string -> unit\<close>\<close>
+definition print_string :: " string \<Rightarrow> string \<Rightarrow> unit " where
+ " print_string msg s = ( () )"
+ for msg :: " string "
+ and s :: " string "
+ \<comment> \<open>\<open> print_endline (msg ^ s) \<close>\<close>
+
+\<comment> \<open>\<open>val prerr_string : string -> string -> unit\<close>\<close>
+definition prerr_string :: " string \<Rightarrow> string \<Rightarrow> unit " where
+ " prerr_string msg s = ( prerr_endline (msg @ s))"
+ for msg :: " string "
+ and s :: " string "
+
+
+\<comment> \<open>\<open>val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit\<close>\<close>
+definition prerr_bits :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where
+ " prerr_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))"
+ for msg :: " string "
+ and bs :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit\<close>\<close>
+definition print_bits0 :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where
+ " print_bits0 msg bs = ( () )"
+ for msg :: " string "
+ and bs :: "('a::len)Word.word "
+ \<comment> \<open>\<open> print_endline (msg ^ (show_bitlist (bits_of bs))) \<close>\<close>
+
+\<comment> \<open>\<open>val print_dbg : string -> unit\<close>\<close>
+definition print_dbg :: " string \<Rightarrow> unit " where
+ " print_dbg msg = ( () )"
+ for msg :: " string "
+
+end
diff --git a/prover_snapshots/isabelle/RV32/Riscv_lemmas.thy b/prover_snapshots/isabelle/RV32/Riscv_lemmas.thy
new file mode 100644
index 0000000..d30ef2d
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/Riscv_lemmas.thy
@@ -0,0 +1,983 @@
+theory Riscv_lemmas
+ imports
+ Sail.Sail2_values_lemmas
+ Sail.Sail2_state_lemmas
+ Riscv
+begin
+
+abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)"
+
+lemmas register_defs = get_regval_def set_regval_def satp_ref_def tlb32_ref_def
+ htif_exit_code_ref_def htif_done_ref_def htif_tohost_ref_def mtimecmp_ref_def utval_ref_def
+ ucause_ref_def uepc_ref_def uscratch_ref_def utvec_ref_def pmpaddr15_ref_def pmpaddr14_ref_def
+ pmpaddr13_ref_def pmpaddr12_ref_def pmpaddr11_ref_def pmpaddr10_ref_def pmpaddr9_ref_def
+ pmpaddr8_ref_def pmpaddr7_ref_def pmpaddr6_ref_def pmpaddr5_ref_def pmpaddr4_ref_def
+ pmpaddr3_ref_def pmpaddr2_ref_def pmpaddr1_ref_def pmpaddr0_ref_def pmp15cfg_ref_def
+ pmp14cfg_ref_def pmp13cfg_ref_def pmp12cfg_ref_def pmp11cfg_ref_def pmp10cfg_ref_def
+ pmp9cfg_ref_def pmp8cfg_ref_def pmp7cfg_ref_def pmp6cfg_ref_def pmp5cfg_ref_def pmp4cfg_ref_def
+ pmp3cfg_ref_def pmp2cfg_ref_def pmp1cfg_ref_def pmp0cfg_ref_def tselect_ref_def stval_ref_def
+ scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def sideleg_ref_def sedeleg_ref_def
+ mhartid_ref_def marchid_ref_def mimpid_ref_def mvendorid_ref_def minstret_written_ref_def
+ minstret_ref_def mtime_ref_def mcycle_ref_def scounteren_ref_def mcounteren_ref_def
+ mscratch_ref_def mtval_ref_def mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def
+ mideleg_ref_def mie_ref_def mip_ref_def mstatus_ref_def misa_ref_def cur_inst_ref_def
+ cur_privilege_ref_def x31_ref_def x30_ref_def x29_ref_def x28_ref_def x27_ref_def x26_ref_def
+ x25_ref_def x24_ref_def x23_ref_def x22_ref_def x21_ref_def x20_ref_def x19_ref_def x18_ref_def
+ x17_ref_def x16_ref_def x15_ref_def x14_ref_def x13_ref_def x12_ref_def x11_ref_def x10_ref_def
+ x9_ref_def x8_ref_def x7_ref_def x6_ref_def x5_ref_def x4_ref_def x3_ref_def x2_ref_def x1_ref_def
+ Xs_ref_def instbits_ref_def nextPC_ref_def PC_ref_def
+
+lemma regval_Counteren[simp]:
+ "Counteren_of_regval (regval_of_Counteren v) = Some v"
+ by (auto simp: regval_of_Counteren_def)
+
+lemma regval_Mcause[simp]:
+ "Mcause_of_regval (regval_of_Mcause v) = Some v"
+ by (auto simp: regval_of_Mcause_def)
+
+lemma regval_Medeleg[simp]:
+ "Medeleg_of_regval (regval_of_Medeleg v) = Some v"
+ by (auto simp: regval_of_Medeleg_def)
+
+lemma regval_Minterrupts[simp]:
+ "Minterrupts_of_regval (regval_of_Minterrupts v) = Some v"
+ by (auto simp: regval_of_Minterrupts_def)
+
+lemma regval_Misa[simp]:
+ "Misa_of_regval (regval_of_Misa v) = Some v"
+ by (auto simp: regval_of_Misa_def)
+
+lemma regval_Mstatus[simp]:
+ "Mstatus_of_regval (regval_of_Mstatus v) = Some v"
+ by (auto simp: regval_of_Mstatus_def)
+
+lemma regval_Mtvec[simp]:
+ "Mtvec_of_regval (regval_of_Mtvec v) = Some v"
+ by (auto simp: regval_of_Mtvec_def)
+
+lemma regval_Pmpcfg_ent[simp]:
+ "Pmpcfg_ent_of_regval (regval_of_Pmpcfg_ent v) = Some v"
+ by (auto simp: regval_of_Pmpcfg_ent_def)
+
+lemma regval_Privilege[simp]:
+ "Privilege_of_regval (regval_of_Privilege v) = Some v"
+ by (auto simp: regval_of_Privilege_def)
+
+lemma regval_Sedeleg[simp]:
+ "Sedeleg_of_regval (regval_of_Sedeleg v) = Some v"
+ by (auto simp: regval_of_Sedeleg_def)
+
+lemma regval_Sinterrupts[simp]:
+ "Sinterrupts_of_regval (regval_of_Sinterrupts v) = Some v"
+ by (auto simp: regval_of_Sinterrupts_def)
+
+lemma regval_TLB_Entry_9_32_34_32[simp]:
+ "TLB_Entry_9_32_34_32_of_regval (regval_of_TLB_Entry_9_32_34_32 v) = Some v"
+ by (auto simp: regval_of_TLB_Entry_9_32_34_32_def)
+
+lemma regval_bool[simp]:
+ "bool_of_regval (regval_of_bool v) = Some v"
+ by (auto simp: regval_of_bool_def)
+
+lemma regval_vector_32_dec_bit[simp]:
+ "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v"
+ by (auto simp: regval_of_vector_32_dec_bit_def)
+
+lemma regval_vector_64_dec_bit[simp]:
+ "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v"
+ by (auto simp: regval_of_vector_64_dec_bit_def)
+
+lemma vector_of_rv_rv_of_vector[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v"
+proof -
+ from assms have "of_rv \<circ> rv_of = Some" by auto
+ then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)
+qed
+
+lemma option_of_rv_rv_of_option[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v"
+ using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def)
+
+lemma list_of_rv_rv_of_list[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v"
+proof -
+ from assms have "of_rv \<circ> rv_of = Some" by auto
+ with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)
+qed
+
+lemma liftS_read_reg_satp[liftState_simp]:
+ "\<lbrakk>read_reg satp_ref\<rbrakk>\<^sub>S = readS (satp \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_satp[liftState_simp]:
+ "\<lbrakk>write_reg satp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (satp_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tlb32[liftState_simp]:
+ "\<lbrakk>read_reg tlb32_ref\<rbrakk>\<^sub>S = readS (tlb32 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tlb32[liftState_simp]:
+ "\<lbrakk>write_reg tlb32_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tlb32_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_exit_code[liftState_simp]:
+ "\<lbrakk>read_reg htif_exit_code_ref\<rbrakk>\<^sub>S = readS (htif_exit_code \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_exit_code[liftState_simp]:
+ "\<lbrakk>write_reg htif_exit_code_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_exit_code_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_done[liftState_simp]:
+ "\<lbrakk>read_reg htif_done_ref\<rbrakk>\<^sub>S = readS (htif_done \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_done[liftState_simp]:
+ "\<lbrakk>write_reg htif_done_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_done_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_tohost[liftState_simp]:
+ "\<lbrakk>read_reg htif_tohost_ref\<rbrakk>\<^sub>S = readS (htif_tohost \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_tohost[liftState_simp]:
+ "\<lbrakk>write_reg htif_tohost_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_tohost_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtimecmp[liftState_simp]:
+ "\<lbrakk>read_reg mtimecmp_ref\<rbrakk>\<^sub>S = readS (mtimecmp \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtimecmp[liftState_simp]:
+ "\<lbrakk>write_reg mtimecmp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtimecmp_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_utval[liftState_simp]:
+ "\<lbrakk>read_reg utval_ref\<rbrakk>\<^sub>S = readS (utval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_utval[liftState_simp]:
+ "\<lbrakk>write_reg utval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (utval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_ucause[liftState_simp]:
+ "\<lbrakk>read_reg ucause_ref\<rbrakk>\<^sub>S = readS (ucause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_ucause[liftState_simp]:
+ "\<lbrakk>write_reg ucause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ucause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_uepc[liftState_simp]:
+ "\<lbrakk>read_reg uepc_ref\<rbrakk>\<^sub>S = readS (uepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_uepc[liftState_simp]:
+ "\<lbrakk>write_reg uepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (uepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_uscratch[liftState_simp]:
+ "\<lbrakk>read_reg uscratch_ref\<rbrakk>\<^sub>S = readS (uscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_uscratch[liftState_simp]:
+ "\<lbrakk>write_reg uscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (uscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_utvec[liftState_simp]:
+ "\<lbrakk>read_reg utvec_ref\<rbrakk>\<^sub>S = readS (utvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_utvec[liftState_simp]:
+ "\<lbrakk>write_reg utvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (utvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr15[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr15_ref\<rbrakk>\<^sub>S = readS (pmpaddr15 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr15[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr15_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr14[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr14_ref\<rbrakk>\<^sub>S = readS (pmpaddr14 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr14[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr14_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr13[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr13_ref\<rbrakk>\<^sub>S = readS (pmpaddr13 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr13[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr13_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr12[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr12_ref\<rbrakk>\<^sub>S = readS (pmpaddr12 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr12[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr12_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr11[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr11_ref\<rbrakk>\<^sub>S = readS (pmpaddr11 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr11[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr11_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr10[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr10_ref\<rbrakk>\<^sub>S = readS (pmpaddr10 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr10[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr10_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr9[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr9_ref\<rbrakk>\<^sub>S = readS (pmpaddr9 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr9[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr9_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr8[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr8_ref\<rbrakk>\<^sub>S = readS (pmpaddr8 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr8[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr8_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr7[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr7_ref\<rbrakk>\<^sub>S = readS (pmpaddr7 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr7[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr7_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr6[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr6_ref\<rbrakk>\<^sub>S = readS (pmpaddr6 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr6[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr6_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr5[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr5_ref\<rbrakk>\<^sub>S = readS (pmpaddr5 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr5[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr5_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr4[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr4_ref\<rbrakk>\<^sub>S = readS (pmpaddr4 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr4[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr4_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr3[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr3_ref\<rbrakk>\<^sub>S = readS (pmpaddr3 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr3[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr3_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr2[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr2_ref\<rbrakk>\<^sub>S = readS (pmpaddr2 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr2[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr2_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr1[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr1_ref\<rbrakk>\<^sub>S = readS (pmpaddr1 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr1[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr1_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr0[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr0_ref\<rbrakk>\<^sub>S = readS (pmpaddr0 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr0[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp15cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp15cfg_ref\<rbrakk>\<^sub>S = readS (pmp15cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp15cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp15cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp15cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp14cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp14cfg_ref\<rbrakk>\<^sub>S = readS (pmp14cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp14cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp14cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp14cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp13cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp13cfg_ref\<rbrakk>\<^sub>S = readS (pmp13cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp13cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp13cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp13cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp12cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp12cfg_ref\<rbrakk>\<^sub>S = readS (pmp12cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp12cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp12cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp12cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp11cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp11cfg_ref\<rbrakk>\<^sub>S = readS (pmp11cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp11cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp11cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp11cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp10cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp10cfg_ref\<rbrakk>\<^sub>S = readS (pmp10cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp10cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp10cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp10cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp9cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp9cfg_ref\<rbrakk>\<^sub>S = readS (pmp9cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp9cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp9cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp9cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp8cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp8cfg_ref\<rbrakk>\<^sub>S = readS (pmp8cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp8cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp8cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp8cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp7cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp7cfg_ref\<rbrakk>\<^sub>S = readS (pmp7cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp7cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp7cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp7cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp6cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp6cfg_ref\<rbrakk>\<^sub>S = readS (pmp6cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp6cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp6cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp6cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp5cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp5cfg_ref\<rbrakk>\<^sub>S = readS (pmp5cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp5cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp5cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp5cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp4cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp4cfg_ref\<rbrakk>\<^sub>S = readS (pmp4cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp4cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp4cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp4cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp3cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp3cfg_ref\<rbrakk>\<^sub>S = readS (pmp3cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp3cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp3cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp3cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp2cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp2cfg_ref\<rbrakk>\<^sub>S = readS (pmp2cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp2cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp2cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp2cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp1cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp1cfg_ref\<rbrakk>\<^sub>S = readS (pmp1cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp1cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp1cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp1cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp0cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp0cfg_ref\<rbrakk>\<^sub>S = readS (pmp0cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp0cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp0cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp0cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tselect[liftState_simp]:
+ "\<lbrakk>read_reg tselect_ref\<rbrakk>\<^sub>S = readS (tselect \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tselect[liftState_simp]:
+ "\<lbrakk>write_reg tselect_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tselect_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stval[liftState_simp]:
+ "\<lbrakk>read_reg stval_ref\<rbrakk>\<^sub>S = readS (stval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stval[liftState_simp]:
+ "\<lbrakk>write_reg stval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scause[liftState_simp]:
+ "\<lbrakk>read_reg scause_ref\<rbrakk>\<^sub>S = readS (scause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scause[liftState_simp]:
+ "\<lbrakk>write_reg scause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sepc[liftState_simp]:
+ "\<lbrakk>read_reg sepc_ref\<rbrakk>\<^sub>S = readS (sepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sepc[liftState_simp]:
+ "\<lbrakk>write_reg sepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sscratch[liftState_simp]:
+ "\<lbrakk>read_reg sscratch_ref\<rbrakk>\<^sub>S = readS (sscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sscratch[liftState_simp]:
+ "\<lbrakk>write_reg sscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stvec[liftState_simp]:
+ "\<lbrakk>read_reg stvec_ref\<rbrakk>\<^sub>S = readS (stvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stvec[liftState_simp]:
+ "\<lbrakk>write_reg stvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sideleg[liftState_simp]:
+ "\<lbrakk>read_reg sideleg_ref\<rbrakk>\<^sub>S = readS (sideleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sideleg[liftState_simp]:
+ "\<lbrakk>write_reg sideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sideleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sedeleg[liftState_simp]:
+ "\<lbrakk>read_reg sedeleg_ref\<rbrakk>\<^sub>S = readS (sedeleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sedeleg[liftState_simp]:
+ "\<lbrakk>write_reg sedeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mhartid[liftState_simp]:
+ "\<lbrakk>read_reg mhartid_ref\<rbrakk>\<^sub>S = readS (mhartid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mhartid[liftState_simp]:
+ "\<lbrakk>write_reg mhartid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mhartid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_marchid[liftState_simp]:
+ "\<lbrakk>read_reg marchid_ref\<rbrakk>\<^sub>S = readS (marchid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_marchid[liftState_simp]:
+ "\<lbrakk>write_reg marchid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (marchid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mimpid[liftState_simp]:
+ "\<lbrakk>read_reg mimpid_ref\<rbrakk>\<^sub>S = readS (mimpid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mimpid[liftState_simp]:
+ "\<lbrakk>write_reg mimpid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mimpid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mvendorid[liftState_simp]:
+ "\<lbrakk>read_reg mvendorid_ref\<rbrakk>\<^sub>S = readS (mvendorid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mvendorid[liftState_simp]:
+ "\<lbrakk>write_reg mvendorid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret_written[liftState_simp]:
+ "\<lbrakk>read_reg minstret_written_ref\<rbrakk>\<^sub>S = readS (minstret_written \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret_written[liftState_simp]:
+ "\<lbrakk>write_reg minstret_written_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_written_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret[liftState_simp]:
+ "\<lbrakk>read_reg minstret_ref\<rbrakk>\<^sub>S = readS (minstret \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret[liftState_simp]:
+ "\<lbrakk>write_reg minstret_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtime[liftState_simp]:
+ "\<lbrakk>read_reg mtime_ref\<rbrakk>\<^sub>S = readS (mtime \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtime[liftState_simp]:
+ "\<lbrakk>write_reg mtime_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtime_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcycle[liftState_simp]:
+ "\<lbrakk>read_reg mcycle_ref\<rbrakk>\<^sub>S = readS (mcycle \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcycle[liftState_simp]:
+ "\<lbrakk>write_reg mcycle_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcycle_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scounteren[liftState_simp]:
+ "\<lbrakk>read_reg scounteren_ref\<rbrakk>\<^sub>S = readS (scounteren \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scounteren[liftState_simp]:
+ "\<lbrakk>write_reg scounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scounteren_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcounteren[liftState_simp]:
+ "\<lbrakk>read_reg mcounteren_ref\<rbrakk>\<^sub>S = readS (mcounteren \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcounteren[liftState_simp]:
+ "\<lbrakk>write_reg mcounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcounteren_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mscratch[liftState_simp]:
+ "\<lbrakk>read_reg mscratch_ref\<rbrakk>\<^sub>S = readS (mscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mscratch[liftState_simp]:
+ "\<lbrakk>write_reg mscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtval[liftState_simp]:
+ "\<lbrakk>read_reg mtval_ref\<rbrakk>\<^sub>S = readS (mtval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtval[liftState_simp]:
+ "\<lbrakk>write_reg mtval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mepc[liftState_simp]:
+ "\<lbrakk>read_reg mepc_ref\<rbrakk>\<^sub>S = readS (mepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mepc[liftState_simp]:
+ "\<lbrakk>write_reg mepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcause[liftState_simp]:
+ "\<lbrakk>read_reg mcause_ref\<rbrakk>\<^sub>S = readS (mcause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcause[liftState_simp]:
+ "\<lbrakk>write_reg mcause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtvec[liftState_simp]:
+ "\<lbrakk>read_reg mtvec_ref\<rbrakk>\<^sub>S = readS (mtvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtvec[liftState_simp]:
+ "\<lbrakk>write_reg mtvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_medeleg[liftState_simp]:
+ "\<lbrakk>read_reg medeleg_ref\<rbrakk>\<^sub>S = readS (medeleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_medeleg[liftState_simp]:
+ "\<lbrakk>write_reg medeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (medeleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mideleg[liftState_simp]:
+ "\<lbrakk>read_reg mideleg_ref\<rbrakk>\<^sub>S = readS (mideleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mideleg[liftState_simp]:
+ "\<lbrakk>write_reg mideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mideleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mie[liftState_simp]:
+ "\<lbrakk>read_reg mie_ref\<rbrakk>\<^sub>S = readS (mie \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mie[liftState_simp]:
+ "\<lbrakk>write_reg mie_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mie_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mip[liftState_simp]:
+ "\<lbrakk>read_reg mip_ref\<rbrakk>\<^sub>S = readS (mip \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mip[liftState_simp]:
+ "\<lbrakk>write_reg mip_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mip_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mstatus[liftState_simp]:
+ "\<lbrakk>read_reg mstatus_ref\<rbrakk>\<^sub>S = readS (mstatus \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mstatus[liftState_simp]:
+ "\<lbrakk>write_reg mstatus_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mstatus_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_misa[liftState_simp]:
+ "\<lbrakk>read_reg misa_ref\<rbrakk>\<^sub>S = readS (misa \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_misa[liftState_simp]:
+ "\<lbrakk>write_reg misa_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (misa_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_inst[liftState_simp]:
+ "\<lbrakk>read_reg cur_inst_ref\<rbrakk>\<^sub>S = readS (cur_inst \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_cur_inst[liftState_simp]:
+ "\<lbrakk>write_reg cur_inst_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_privilege[liftState_simp]:
+ "\<lbrakk>read_reg cur_privilege_ref\<rbrakk>\<^sub>S = readS (cur_privilege \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_cur_privilege[liftState_simp]:
+ "\<lbrakk>write_reg cur_privilege_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x31[liftState_simp]:
+ "\<lbrakk>read_reg x31_ref\<rbrakk>\<^sub>S = readS (x31 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x31[liftState_simp]:
+ "\<lbrakk>write_reg x31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x31_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x30[liftState_simp]:
+ "\<lbrakk>read_reg x30_ref\<rbrakk>\<^sub>S = readS (x30 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x30[liftState_simp]:
+ "\<lbrakk>write_reg x30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x30_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x29[liftState_simp]:
+ "\<lbrakk>read_reg x29_ref\<rbrakk>\<^sub>S = readS (x29 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x29[liftState_simp]:
+ "\<lbrakk>write_reg x29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x29_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x28[liftState_simp]:
+ "\<lbrakk>read_reg x28_ref\<rbrakk>\<^sub>S = readS (x28 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x28[liftState_simp]:
+ "\<lbrakk>write_reg x28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x28_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x27[liftState_simp]:
+ "\<lbrakk>read_reg x27_ref\<rbrakk>\<^sub>S = readS (x27 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x27[liftState_simp]:
+ "\<lbrakk>write_reg x27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x27_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x26[liftState_simp]:
+ "\<lbrakk>read_reg x26_ref\<rbrakk>\<^sub>S = readS (x26 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x26[liftState_simp]:
+ "\<lbrakk>write_reg x26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x26_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x25[liftState_simp]:
+ "\<lbrakk>read_reg x25_ref\<rbrakk>\<^sub>S = readS (x25 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x25[liftState_simp]:
+ "\<lbrakk>write_reg x25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x25_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x24[liftState_simp]:
+ "\<lbrakk>read_reg x24_ref\<rbrakk>\<^sub>S = readS (x24 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x24[liftState_simp]:
+ "\<lbrakk>write_reg x24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x24_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x23[liftState_simp]:
+ "\<lbrakk>read_reg x23_ref\<rbrakk>\<^sub>S = readS (x23 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x23[liftState_simp]:
+ "\<lbrakk>write_reg x23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x23_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x22[liftState_simp]:
+ "\<lbrakk>read_reg x22_ref\<rbrakk>\<^sub>S = readS (x22 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x22[liftState_simp]:
+ "\<lbrakk>write_reg x22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x22_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x21[liftState_simp]:
+ "\<lbrakk>read_reg x21_ref\<rbrakk>\<^sub>S = readS (x21 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x21[liftState_simp]:
+ "\<lbrakk>write_reg x21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x21_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x20[liftState_simp]:
+ "\<lbrakk>read_reg x20_ref\<rbrakk>\<^sub>S = readS (x20 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x20[liftState_simp]:
+ "\<lbrakk>write_reg x20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x20_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x19[liftState_simp]:
+ "\<lbrakk>read_reg x19_ref\<rbrakk>\<^sub>S = readS (x19 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x19[liftState_simp]:
+ "\<lbrakk>write_reg x19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x19_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x18[liftState_simp]:
+ "\<lbrakk>read_reg x18_ref\<rbrakk>\<^sub>S = readS (x18 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x18[liftState_simp]:
+ "\<lbrakk>write_reg x18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x18_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x17[liftState_simp]:
+ "\<lbrakk>read_reg x17_ref\<rbrakk>\<^sub>S = readS (x17 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x17[liftState_simp]:
+ "\<lbrakk>write_reg x17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x17_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x16[liftState_simp]:
+ "\<lbrakk>read_reg x16_ref\<rbrakk>\<^sub>S = readS (x16 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x16[liftState_simp]:
+ "\<lbrakk>write_reg x16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x16_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x15[liftState_simp]:
+ "\<lbrakk>read_reg x15_ref\<rbrakk>\<^sub>S = readS (x15 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x15[liftState_simp]:
+ "\<lbrakk>write_reg x15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x15_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x14[liftState_simp]:
+ "\<lbrakk>read_reg x14_ref\<rbrakk>\<^sub>S = readS (x14 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x14[liftState_simp]:
+ "\<lbrakk>write_reg x14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x14_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x13[liftState_simp]:
+ "\<lbrakk>read_reg x13_ref\<rbrakk>\<^sub>S = readS (x13 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x13[liftState_simp]:
+ "\<lbrakk>write_reg x13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x13_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x12[liftState_simp]:
+ "\<lbrakk>read_reg x12_ref\<rbrakk>\<^sub>S = readS (x12 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x12[liftState_simp]:
+ "\<lbrakk>write_reg x12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x12_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x11[liftState_simp]:
+ "\<lbrakk>read_reg x11_ref\<rbrakk>\<^sub>S = readS (x11 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x11[liftState_simp]:
+ "\<lbrakk>write_reg x11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x11_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x10[liftState_simp]:
+ "\<lbrakk>read_reg x10_ref\<rbrakk>\<^sub>S = readS (x10 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x10[liftState_simp]:
+ "\<lbrakk>write_reg x10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x10_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x9[liftState_simp]:
+ "\<lbrakk>read_reg x9_ref\<rbrakk>\<^sub>S = readS (x9 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x9[liftState_simp]:
+ "\<lbrakk>write_reg x9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x9_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x8[liftState_simp]:
+ "\<lbrakk>read_reg x8_ref\<rbrakk>\<^sub>S = readS (x8 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x8[liftState_simp]:
+ "\<lbrakk>write_reg x8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x8_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x7[liftState_simp]:
+ "\<lbrakk>read_reg x7_ref\<rbrakk>\<^sub>S = readS (x7 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x7[liftState_simp]:
+ "\<lbrakk>write_reg x7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x7_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x6[liftState_simp]:
+ "\<lbrakk>read_reg x6_ref\<rbrakk>\<^sub>S = readS (x6 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x6[liftState_simp]:
+ "\<lbrakk>write_reg x6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x6_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x5[liftState_simp]:
+ "\<lbrakk>read_reg x5_ref\<rbrakk>\<^sub>S = readS (x5 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x5[liftState_simp]:
+ "\<lbrakk>write_reg x5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x5_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x4[liftState_simp]:
+ "\<lbrakk>read_reg x4_ref\<rbrakk>\<^sub>S = readS (x4 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x4[liftState_simp]:
+ "\<lbrakk>write_reg x4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x4_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x3[liftState_simp]:
+ "\<lbrakk>read_reg x3_ref\<rbrakk>\<^sub>S = readS (x3 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x3[liftState_simp]:
+ "\<lbrakk>write_reg x3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x3_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x2[liftState_simp]:
+ "\<lbrakk>read_reg x2_ref\<rbrakk>\<^sub>S = readS (x2 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x2[liftState_simp]:
+ "\<lbrakk>write_reg x2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x2_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x1[liftState_simp]:
+ "\<lbrakk>read_reg x1_ref\<rbrakk>\<^sub>S = readS (x1 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x1[liftState_simp]:
+ "\<lbrakk>write_reg x1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x1_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_Xs[liftState_simp]:
+ "\<lbrakk>read_reg Xs_ref\<rbrakk>\<^sub>S = readS (Xs \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_Xs[liftState_simp]:
+ "\<lbrakk>write_reg Xs_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Xs_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_instbits[liftState_simp]:
+ "\<lbrakk>read_reg instbits_ref\<rbrakk>\<^sub>S = readS (instbits \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_instbits[liftState_simp]:
+ "\<lbrakk>write_reg instbits_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (instbits_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_nextPC[liftState_simp]:
+ "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_nextPC[liftState_simp]:
+ "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_PC[liftState_simp]:
+ "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_PC[liftState_simp]:
+ "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+end
diff --git a/prover_snapshots/isabelle/RV32/Riscv_types.thy b/prover_snapshots/isabelle/RV32/Riscv_types.thy
new file mode 100644
index 0000000..4cd10d7
--- /dev/null
+++ b/prover_snapshots/isabelle/RV32/Riscv_types.thy
@@ -0,0 +1,2304 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV32/riscv_types.lem\<close>.\<close>
+
+theory "Riscv_types"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+
+begin
+
+\<comment> \<open>\<open>Generated by Sail from riscv.\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_string\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+
+
+type_synonym 'n bits =" ( 'n::len)Word.word "
+
+datatype regfp =
+ RFull " (string)"
+ | RSlice " ((string * ii * ii))"
+ | RSliceBit " ((string * ii))"
+ | RField " ((string * string))"
+
+
+
+type_synonym regfps =" regfp list "
+
+datatype niafp =
+ NIAFP_successor " (unit)"
+ | NIAFP_concrete_address " ( 64 bits)"
+ | NIAFP_indirect_address " (unit)"
+
+
+
+type_synonym niafps =" niafp list "
+
+datatype diafp = DIAFP_none " (unit)" | DIAFP_concrete " ( 64 bits)" | DIAFP_reg " (regfp)"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+type_synonym xlenbits =" 32 bits "
+
+type_synonym mem_meta =" unit "
+
+
+
+type_synonym half =" 16 bits "
+
+type_synonym word0 =" 32 bits "
+
+type_synonym regidx =" 5 bits "
+
+type_synonym cregidx =" 3 bits "
+
+type_synonym csreg =" 12 bits "
+
+type_synonym 'n regno =" int "
+
+type_synonym opcode =" 7 bits "
+
+type_synonym imm12 =" 12 bits "
+
+type_synonym imm20 =" 20 bits "
+
+type_synonym amo =" 1 bits "
+
+datatype Architecture = RV32 | RV64 | RV128
+
+
+
+type_synonym arch_xlen =" 2 bits "
+
+type_synonym priv_level =" 2 bits "
+
+datatype Privilege = User | Supervisor | Machine
+
+
+
+datatype amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU
+
+
+
+datatype bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU
+
+
+
+datatype csrop = CSRRW | CSRRS | CSRRC
+
+
+
+datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI
+
+
+
+datatype rop =
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND
+
+
+
+datatype ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW
+
+
+
+datatype sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI
+
+
+
+datatype sopw = RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW
+
+
+
+datatype uop = RISCV_LUI | RISCV_AUIPC
+
+
+
+datatype word_width = BYTE | HALF | WORD | DOUBLE
+
+
+
+datatype (plugins only: size) ast =
+ UTYPE " (( 20 bits * regidx * uop))"
+ | RISCV_JAL " (( 21 bits * regidx))"
+ | RISCV_JALR " (( 12 bits * regidx * regidx))"
+ | BTYPE " (( 13 bits * regidx * regidx * bop))"
+ | ITYPE " (( 12 bits * regidx * regidx * iop))"
+ | SHIFTIOP " (( 6 bits * regidx * regidx * sop))"
+ | RTYPE " ((regidx * regidx * regidx * rop))"
+ | LOAD " (( 12 bits * regidx * regidx * bool * word_width * bool * bool))"
+ | STORE " (( 12 bits * regidx * regidx * word_width * bool * bool))"
+ | ADDIW " (( 12 bits * regidx * regidx))"
+ | SHIFTW " (( 5 bits * regidx * regidx * sop))"
+ | RTYPEW " ((regidx * regidx * regidx * ropw))"
+ | SHIFTIWOP " (( 5 bits * regidx * regidx * sopw))"
+ | FENCE " (( 4 bits * 4 bits))"
+ | FENCE_TSO " (( 4 bits * 4 bits))"
+ | FENCEI " (unit)"
+ | ECALL " (unit)"
+ | MRET " (unit)"
+ | SRET " (unit)"
+ | EBREAK " (unit)"
+ | WFI " (unit)"
+ | SFENCE_VMA " ((regidx * regidx))"
+ | LOADRES " ((bool * bool * regidx * word_width * regidx))"
+ | STORECON " ((bool * bool * regidx * regidx * word_width * regidx))"
+ | AMO " ((amoop * bool * bool * regidx * regidx * word_width * regidx))"
+ | C_NOP " (unit)"
+ | C_ADDI4SPN " ((cregidx * 8 bits))"
+ | C_LW " (( 5 bits * cregidx * cregidx))"
+ | C_LD " (( 5 bits * cregidx * cregidx))"
+ | C_SW " (( 5 bits * cregidx * cregidx))"
+ | C_SD " (( 5 bits * cregidx * cregidx))"
+ | C_ADDI " (( 6 bits * regidx))"
+ | C_JAL " ( 11 bits)"
+ | C_ADDIW " (( 6 bits * regidx))"
+ | C_LI " (( 6 bits * regidx))"
+ | C_ADDI16SP " ( 6 bits)"
+ | C_LUI " (( 6 bits * regidx))"
+ | C_SRLI " (( 6 bits * cregidx))"
+ | C_SRAI " (( 6 bits * cregidx))"
+ | C_ANDI " (( 6 bits * cregidx))"
+ | C_SUB " ((cregidx * cregidx))"
+ | C_XOR " ((cregidx * cregidx))"
+ | C_OR " ((cregidx * cregidx))"
+ | C_AND " ((cregidx * cregidx))"
+ | C_SUBW " ((cregidx * cregidx))"
+ | C_ADDW " ((cregidx * cregidx))"
+ | C_J " ( 11 bits)"
+ | C_BEQZ " (( 8 bits * cregidx))"
+ | C_BNEZ " (( 8 bits * cregidx))"
+ | C_SLLI " (( 6 bits * regidx))"
+ | C_LWSP " (( 6 bits * regidx))"
+ | C_LDSP " (( 6 bits * regidx))"
+ | C_SWSP " (( 6 bits * regidx))"
+ | C_SDSP " (( 6 bits * regidx))"
+ | C_JR " (regidx)"
+ | C_JALR " (regidx)"
+ | C_MV " ((regidx * regidx))"
+ | C_EBREAK " (unit)"
+ | C_ADD " ((regidx * regidx))"
+ | MUL " ((regidx * regidx * regidx * bool * bool * bool))"
+ | DIV " ((regidx * regidx * regidx * bool))"
+ | REM " ((regidx * regidx * regidx * bool))"
+ | MULW " ((regidx * regidx * regidx))"
+ | DIVW " ((regidx * regidx * regidx * bool))"
+ | REMW " ((regidx * regidx * regidx * bool))"
+ | CSR " (( 12 bits * regidx * regidx * bool * csrop))"
+ | URET " (unit)"
+ | ILLEGAL " (word0)"
+ | C_ILLEGAL " (half)"
+
+
+
+datatype Retired = RETIRE_SUCCESS | RETIRE_FAIL
+
+
+
+datatype AccessType = Read | Write | ReadWrite | Execute
+
+
+
+type_synonym exc_code =" 8 bits "
+
+datatype InterruptType =
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External
+
+
+
+datatype ExceptionType =
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI
+
+
+
+datatype exception = Error_not_implemented " (string)" | Error_internal_error " (unit)"
+
+
+
+type_synonym tv_mode =" 2 bits "
+
+datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved
+
+
+
+type_synonym ext_status =" 2 bits "
+
+datatype ExtStatus = Off | Initial | Clean | Dirty
+
+
+
+type_synonym satp_mode =" 4 bits "
+
+datatype SATPMode = Sbare | Sv32 | Sv39 | Sv48
+
+
+
+type_synonym csrRW =" 2 bits "
+
+type_synonym regtype =" xlenbits "
+
+record Misa =
+ Misa_Misa_chunk_0 ::" 32 Word.word "
+
+
+
+record SV48_PTE =
+ SV48_PTE_SV48_PTE_chunk_0 ::" 64 Word.word "
+
+
+
+record PTE_Bits =
+ PTE_Bits_PTE_Bits_chunk_0 ::" 8 Word.word "
+
+
+
+record Pmpcfg_ent =
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 ::" 8 Word.word "
+
+
+
+record Mstatus =
+ Mstatus_Mstatus_chunk_0 ::" 32 Word.word "
+
+
+
+record Sstatus =
+ Sstatus_Sstatus_chunk_0 ::" 32 Word.word "
+
+
+
+record Ustatus =
+ Ustatus_Ustatus_chunk_0 ::" 32 Word.word "
+
+
+
+record Minterrupts =
+ Minterrupts_Minterrupts_chunk_0 ::" 32 Word.word "
+
+
+
+record Sinterrupts =
+ Sinterrupts_Sinterrupts_chunk_0 ::" 32 Word.word "
+
+
+
+record Uinterrupts =
+ Uinterrupts_Uinterrupts_chunk_0 ::" 32 Word.word "
+
+
+
+record Medeleg =
+ Medeleg_Medeleg_chunk_0 ::" 32 Word.word "
+
+
+
+record Sedeleg =
+ Sedeleg_Sedeleg_chunk_0 ::" 32 Word.word "
+
+
+
+record Mtvec =
+ Mtvec_Mtvec_chunk_0 ::" 32 Word.word "
+
+
+
+record Satp32 =
+ Satp32_Satp32_chunk_0 ::" 32 Word.word "
+
+
+
+record Mcause =
+ Mcause_Mcause_chunk_0 ::" 32 Word.word "
+
+
+
+record Counteren =
+ Counteren_Counteren_chunk_0 ::" 32 Word.word "
+
+
+
+record Satp64 =
+ Satp64_Satp64_chunk_0 ::" 64 Word.word "
+
+
+
+datatype PmpAddrMatchType = OFF | TOR | NA4 | NAPOT
+
+
+
+type_synonym pmp_addr_range =" ((xlenbits * xlenbits))option "
+
+datatype pmpAddrMatch = PMP_NoMatch | PMP_PartialMatch | PMP_Match
+
+
+
+datatype pmpMatch = PMP_Success | PMP_Continue | PMP_Fail
+
+
+
+datatype 'a Ext_FetchAddr_Check = Ext_FetchAddr_OK " (xlenbits)" | Ext_FetchAddr_Error " ('a)"
+
+
+
+datatype 'a Ext_ControlAddr_Check = Ext_ControlAddr_OK " (xlenbits)" | Ext_ControlAddr_Error " ('a)"
+
+
+
+datatype 'a Ext_DataAddr_Check = Ext_DataAddr_OK " (xlenbits)" | Ext_DataAddr_Error " ('a)"
+
+
+
+type_synonym ext_fetch_addr_error =" unit "
+
+type_synonym ext_control_addr_error =" unit "
+
+type_synonym ext_data_addr_error =" unit "
+
+type_synonym ext_exception =" unit "
+
+record sync_exception =
+
+ sync_exception_trap ::" ExceptionType "
+
+ sync_exception_excinfo ::" xlenbits option "
+
+ sync_exception_ext_exception ::" ext_exception option "
+
+
+
+datatype interrupt_set =
+ Ints_Pending " (xlenbits)" | Ints_Delegated " (xlenbits)" | Ints_Empty " (unit)"
+
+
+
+datatype ctl_result =
+ CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL_MRET " (unit)" | CTL_URET " (unit)"
+
+
+
+datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)"
+
+
+
+record htif_cmd =
+ htif_cmd_htif_cmd_chunk_0 ::" 64 Word.word "
+
+
+
+type_synonym pteAttribs =" 8 bits "
+
+datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update
+
+
+
+type_synonym vaddr32 =" 32 bits "
+
+type_synonym paddr32 =" 34 bits "
+
+type_synonym pte32 =" 32 bits "
+
+type_synonym asid32 =" 9 bits "
+
+record SV32_Vaddr =
+ SV32_Vaddr_SV32_Vaddr_chunk_0 ::" 32 Word.word "
+
+
+
+record SV48_Vaddr =
+ SV48_Vaddr_SV48_Vaddr_chunk_0 ::" 48 Word.word "
+
+
+
+record SV48_Paddr =
+ SV48_Paddr_SV48_Paddr_chunk_0 ::" 56 Word.word "
+
+
+
+record SV32_Paddr =
+ SV32_Paddr_SV32_Paddr_chunk_0 ::" 34 Word.word "
+
+
+
+record SV32_PTE =
+ SV32_PTE_SV32_PTE_chunk_0 ::" 32 Word.word "
+
+
+
+type_synonym paddr64 =" 56 bits "
+
+type_synonym pte64 =" 64 bits "
+
+type_synonym asid64 =" 16 bits "
+
+type_synonym vaddr39 =" 39 bits "
+
+record SV39_Vaddr =
+ SV39_Vaddr_SV39_Vaddr_chunk_0 ::" 39 Word.word "
+
+
+
+record SV39_Paddr =
+ SV39_Paddr_SV39_Paddr_chunk_0 ::" 56 Word.word "
+
+
+
+record SV39_PTE =
+ SV39_PTE_SV39_PTE_chunk_0 ::" 64 Word.word "
+
+
+
+type_synonym vaddr48 =" 48 bits "
+
+type_synonym pte48 =" 64 bits "
+
+datatype( 'paddr, 'pte) PTW_Result =
+ PTW_Success " (('paddr * 'pte * 'paddr * ii * bool))" | PTW_Failure " (PTW_Error)"
+
+
+
+datatype( 'paddr, 'failure) TR_Result = TR_Address " ('paddr)" | TR_Failure " ('failure)"
+
+
+
+record (overloaded) ( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry =
+
+ TLB_Entry_asid ::" 'asidlen bits "
+
+ TLB_Entry_global ::" bool "
+
+ TLB_Entry_vAddr ::" 'valen bits "
+
+ TLB_Entry_pAddr ::" 'palen bits "
+
+ TLB_Entry_vMatchMask ::" 'valen bits "
+
+ TLB_Entry_vAddrMask ::" 'valen bits "
+
+ TLB_Entry_pte ::" 'ptelen bits "
+
+ TLB_Entry_pteAddr ::" 'palen bits "
+
+ TLB_Entry_age ::" 64 bits "
+
+
+
+type_synonym TLB32_Entry =" (9, 32, 34, 32) TLB_Entry "
+
+datatype FetchResult =
+ F_Ext_Error " (ext_fetch_addr_error)"
+ | F_Base " (word0)"
+ | F_RVC " (half)"
+ | F_Error " ((ExceptionType * xlenbits))"
+
+
+
+datatype register_value =
+ Regval_vector " ((ii * bool * register_value list))"
+ | Regval_list " ( register_value list)"
+ | Regval_option " ( register_value option)"
+ | Regval_Counteren " (Counteren)"
+ | Regval_Mcause " (Mcause)"
+ | Regval_Medeleg " (Medeleg)"
+ | Regval_Minterrupts " (Minterrupts)"
+ | Regval_Misa " (Misa)"
+ | Regval_Mstatus " (Mstatus)"
+ | Regval_Mtvec " (Mtvec)"
+ | Regval_Pmpcfg_ent " (Pmpcfg_ent)"
+ | Regval_Privilege " (Privilege)"
+ | Regval_Sedeleg " (Sedeleg)"
+ | Regval_Sinterrupts " (Sinterrupts)"
+ | Regval_TLB_Entry_9_32_34_32 " ( (9, 32, 34, 32)TLB_Entry)"
+ | Regval_bool " (bool)"
+ | Regval_vector_32_dec_bit " ( 32 Word.word)"
+ | Regval_vector_64_dec_bit " ( 64 Word.word)"
+
+
+
+record regstate =
+
+ satp ::" 32 Word.word "
+
+ tlb32 ::" ( (9, 32, 34, 32)TLB_Entry)option "
+
+ htif_exit_code ::" 64 Word.word "
+
+ htif_done ::" bool "
+
+ htif_tohost ::" 64 Word.word "
+
+ mtimecmp ::" 64 Word.word "
+
+ utval ::" 32 Word.word "
+
+ ucause ::" Mcause "
+
+ uepc ::" 32 Word.word "
+
+ uscratch ::" 32 Word.word "
+
+ utvec ::" Mtvec "
+
+ pmpaddr15 ::" 32 Word.word "
+
+ pmpaddr14 ::" 32 Word.word "
+
+ pmpaddr13 ::" 32 Word.word "
+
+ pmpaddr12 ::" 32 Word.word "
+
+ pmpaddr11 ::" 32 Word.word "
+
+ pmpaddr10 ::" 32 Word.word "
+
+ pmpaddr9 ::" 32 Word.word "
+
+ pmpaddr8 ::" 32 Word.word "
+
+ pmpaddr7 ::" 32 Word.word "
+
+ pmpaddr6 ::" 32 Word.word "
+
+ pmpaddr5 ::" 32 Word.word "
+
+ pmpaddr4 ::" 32 Word.word "
+
+ pmpaddr3 ::" 32 Word.word "
+
+ pmpaddr2 ::" 32 Word.word "
+
+ pmpaddr1 ::" 32 Word.word "
+
+ pmpaddr0 ::" 32 Word.word "
+
+ pmp15cfg ::" Pmpcfg_ent "
+
+ pmp14cfg ::" Pmpcfg_ent "
+
+ pmp13cfg ::" Pmpcfg_ent "
+
+ pmp12cfg ::" Pmpcfg_ent "
+
+ pmp11cfg ::" Pmpcfg_ent "
+
+ pmp10cfg ::" Pmpcfg_ent "
+
+ pmp9cfg ::" Pmpcfg_ent "
+
+ pmp8cfg ::" Pmpcfg_ent "
+
+ pmp7cfg ::" Pmpcfg_ent "
+
+ pmp6cfg ::" Pmpcfg_ent "
+
+ pmp5cfg ::" Pmpcfg_ent "
+
+ pmp4cfg ::" Pmpcfg_ent "
+
+ pmp3cfg ::" Pmpcfg_ent "
+
+ pmp2cfg ::" Pmpcfg_ent "
+
+ pmp1cfg ::" Pmpcfg_ent "
+
+ pmp0cfg ::" Pmpcfg_ent "
+
+ tselect ::" 32 Word.word "
+
+ stval ::" 32 Word.word "
+
+ scause ::" Mcause "
+
+ sepc ::" 32 Word.word "
+
+ sscratch ::" 32 Word.word "
+
+ stvec ::" Mtvec "
+
+ sideleg ::" Sinterrupts "
+
+ sedeleg ::" Sedeleg "
+
+ mhartid ::" 32 Word.word "
+
+ marchid ::" 32 Word.word "
+
+ mimpid ::" 32 Word.word "
+
+ mvendorid ::" 32 Word.word "
+
+ minstret_written ::" bool "
+
+ minstret ::" 64 Word.word "
+
+ mtime ::" 64 Word.word "
+
+ mcycle ::" 64 Word.word "
+
+ scounteren ::" Counteren "
+
+ mcounteren ::" Counteren "
+
+ mscratch ::" 32 Word.word "
+
+ mtval ::" 32 Word.word "
+
+ mepc ::" 32 Word.word "
+
+ mcause ::" Mcause "
+
+ mtvec ::" Mtvec "
+
+ medeleg ::" Medeleg "
+
+ mideleg ::" Minterrupts "
+
+ mie ::" Minterrupts "
+
+ mip ::" Minterrupts "
+
+ mstatus ::" Mstatus "
+
+ misa ::" Misa "
+
+ cur_inst ::" 32 Word.word "
+
+ cur_privilege ::" Privilege "
+
+ x31 ::" 32 Word.word "
+
+ x30 ::" 32 Word.word "
+
+ x29 ::" 32 Word.word "
+
+ x28 ::" 32 Word.word "
+
+ x27 ::" 32 Word.word "
+
+ x26 ::" 32 Word.word "
+
+ x25 ::" 32 Word.word "
+
+ x24 ::" 32 Word.word "
+
+ x23 ::" 32 Word.word "
+
+ x22 ::" 32 Word.word "
+
+ x21 ::" 32 Word.word "
+
+ x20 ::" 32 Word.word "
+
+ x19 ::" 32 Word.word "
+
+ x18 ::" 32 Word.word "
+
+ x17 ::" 32 Word.word "
+
+ x16 ::" 32 Word.word "
+
+ x15 ::" 32 Word.word "
+
+ x14 ::" 32 Word.word "
+
+ x13 ::" 32 Word.word "
+
+ x12 ::" 32 Word.word "
+
+ x11 ::" 32 Word.word "
+
+ x10 ::" 32 Word.word "
+
+ x9 ::" 32 Word.word "
+
+ x8 ::" 32 Word.word "
+
+ x7 ::" 32 Word.word "
+
+ x6 ::" 32 Word.word "
+
+ x5 ::" 32 Word.word "
+
+ x4 ::" 32 Word.word "
+
+ x3 ::" 32 Word.word "
+
+ x2 ::" 32 Word.word "
+
+ x1 ::" 32 Word.word "
+
+ Xs ::" ( 32 Word.word) list "
+
+ instbits ::" 32 Word.word "
+
+ nextPC ::" 32 Word.word "
+
+ PC ::" 32 Word.word "
+
+
+
+
+
+\<comment> \<open>\<open>val Counteren_of_regval : register_value -> maybe Counteren\<close>\<close>
+
+fun Counteren_of_regval :: " register_value \<Rightarrow>(Counteren)option " where
+ " Counteren_of_regval (Regval_Counteren (v)) = ( Some v )"
+ for v :: " Counteren "
+|" Counteren_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Counteren : Counteren -> register_value\<close>\<close>
+
+definition regval_of_Counteren :: " Counteren \<Rightarrow> register_value " where
+ " regval_of_Counteren v = ( Regval_Counteren v )"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val Mcause_of_regval : register_value -> maybe Mcause\<close>\<close>
+
+fun Mcause_of_regval :: " register_value \<Rightarrow>(Mcause)option " where
+ " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )"
+ for v :: " Mcause "
+|" Mcause_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mcause : Mcause -> register_value\<close>\<close>
+
+definition regval_of_Mcause :: " Mcause \<Rightarrow> register_value " where
+ " regval_of_Mcause v = ( Regval_Mcause v )"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val Medeleg_of_regval : register_value -> maybe Medeleg\<close>\<close>
+
+fun Medeleg_of_regval :: " register_value \<Rightarrow>(Medeleg)option " where
+ " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )"
+ for v :: " Medeleg "
+|" Medeleg_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Medeleg : Medeleg -> register_value\<close>\<close>
+
+definition regval_of_Medeleg :: " Medeleg \<Rightarrow> register_value " where
+ " regval_of_Medeleg v = ( Regval_Medeleg v )"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val Minterrupts_of_regval : register_value -> maybe Minterrupts\<close>\<close>
+
+fun Minterrupts_of_regval :: " register_value \<Rightarrow>(Minterrupts)option " where
+ " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )"
+ for v :: " Minterrupts "
+|" Minterrupts_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Minterrupts : Minterrupts -> register_value\<close>\<close>
+
+definition regval_of_Minterrupts :: " Minterrupts \<Rightarrow> register_value " where
+ " regval_of_Minterrupts v = ( Regval_Minterrupts v )"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val Misa_of_regval : register_value -> maybe Misa\<close>\<close>
+
+fun Misa_of_regval :: " register_value \<Rightarrow>(Misa)option " where
+ " Misa_of_regval (Regval_Misa (v)) = ( Some v )"
+ for v :: " Misa "
+|" Misa_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Misa : Misa -> register_value\<close>\<close>
+
+definition regval_of_Misa :: " Misa \<Rightarrow> register_value " where
+ " regval_of_Misa v = ( Regval_Misa v )"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val Mstatus_of_regval : register_value -> maybe Mstatus\<close>\<close>
+
+fun Mstatus_of_regval :: " register_value \<Rightarrow>(Mstatus)option " where
+ " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )"
+ for v :: " Mstatus "
+|" Mstatus_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mstatus : Mstatus -> register_value\<close>\<close>
+
+definition regval_of_Mstatus :: " Mstatus \<Rightarrow> register_value " where
+ " regval_of_Mstatus v = ( Regval_Mstatus v )"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val Mtvec_of_regval : register_value -> maybe Mtvec\<close>\<close>
+
+fun Mtvec_of_regval :: " register_value \<Rightarrow>(Mtvec)option " where
+ " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )"
+ for v :: " Mtvec "
+|" Mtvec_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mtvec : Mtvec -> register_value\<close>\<close>
+
+definition regval_of_Mtvec :: " Mtvec \<Rightarrow> register_value " where
+ " regval_of_Mtvec v = ( Regval_Mtvec v )"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val Pmpcfg_ent_of_regval : register_value -> maybe Pmpcfg_ent\<close>\<close>
+
+fun Pmpcfg_ent_of_regval :: " register_value \<Rightarrow>(Pmpcfg_ent)option " where
+ " Pmpcfg_ent_of_regval (Regval_Pmpcfg_ent (v)) = ( Some v )"
+ for v :: " Pmpcfg_ent "
+|" Pmpcfg_ent_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Pmpcfg_ent : Pmpcfg_ent -> register_value\<close>\<close>
+
+definition regval_of_Pmpcfg_ent :: " Pmpcfg_ent \<Rightarrow> register_value " where
+ " regval_of_Pmpcfg_ent v = ( Regval_Pmpcfg_ent v )"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val Privilege_of_regval : register_value -> maybe Privilege\<close>\<close>
+
+fun Privilege_of_regval :: " register_value \<Rightarrow>(Privilege)option " where
+ " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )"
+ for v :: " Privilege "
+|" Privilege_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Privilege : Privilege -> register_value\<close>\<close>
+
+definition regval_of_Privilege :: " Privilege \<Rightarrow> register_value " where
+ " regval_of_Privilege v = ( Regval_Privilege v )"
+ for v :: " Privilege "
+
+
+\<comment> \<open>\<open>val Sedeleg_of_regval : register_value -> maybe Sedeleg\<close>\<close>
+
+fun Sedeleg_of_regval :: " register_value \<Rightarrow>(Sedeleg)option " where
+ " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )"
+ for v :: " Sedeleg "
+|" Sedeleg_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Sedeleg : Sedeleg -> register_value\<close>\<close>
+
+definition regval_of_Sedeleg :: " Sedeleg \<Rightarrow> register_value " where
+ " regval_of_Sedeleg v = ( Regval_Sedeleg v )"
+ for v :: " Sedeleg "
+
+
+\<comment> \<open>\<open>val Sinterrupts_of_regval : register_value -> maybe Sinterrupts\<close>\<close>
+
+fun Sinterrupts_of_regval :: " register_value \<Rightarrow>(Sinterrupts)option " where
+ " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )"
+ for v :: " Sinterrupts "
+|" Sinterrupts_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Sinterrupts : Sinterrupts -> register_value\<close>\<close>
+
+definition regval_of_Sinterrupts :: " Sinterrupts \<Rightarrow> register_value " where
+ " regval_of_Sinterrupts v = ( Regval_Sinterrupts v )"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val TLB_Entry_9_32_34_32_of_regval : register_value -> maybe (TLB_Entry ty9 ty32 ty34 ty32)\<close>\<close>
+
+fun TLB_Entry_9_32_34_32_of_regval :: " register_value \<Rightarrow>(((9),(32),(34),(32))TLB_Entry)option " where
+ " TLB_Entry_9_32_34_32_of_regval (Regval_TLB_Entry_9_32_34_32 (v)) = ( Some v )"
+ for v :: "((9),(32),(34),(32))TLB_Entry "
+|" TLB_Entry_9_32_34_32_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_TLB_Entry_9_32_34_32 : TLB_Entry ty9 ty32 ty34 ty32 -> register_value\<close>\<close>
+
+definition regval_of_TLB_Entry_9_32_34_32 :: "((9),(32),(34),(32))TLB_Entry \<Rightarrow> register_value " where
+ " regval_of_TLB_Entry_9_32_34_32 v = ( Regval_TLB_Entry_9_32_34_32 v )"
+ for v :: "((9),(32),(34),(32))TLB_Entry "
+
+
+\<comment> \<open>\<open>val bool_of_regval : register_value -> maybe bool\<close>\<close>
+
+fun bool_of_regval :: " register_value \<Rightarrow>(bool)option " where
+ " bool_of_regval (Regval_bool (v)) = ( Some v )"
+ for v :: " bool "
+|" bool_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_bool : bool -> register_value\<close>\<close>
+
+definition regval_of_bool :: " bool \<Rightarrow> register_value " where
+ " regval_of_bool v = ( Regval_bool v )"
+ for v :: " bool "
+
+
+\<comment> \<open>\<open>val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)\<close>\<close>
+
+fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where
+ " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )"
+ for v :: "(32)Word.word "
+|" vector_32_dec_bit_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_vector_32_dec_bit : mword ty32 -> register_value\<close>\<close>
+
+definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register_value " where
+ " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)\<close>\<close>
+
+fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where
+ " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
+ for v :: "(64)Word.word "
+|" vector_64_dec_bit_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_vector_64_dec_bit : mword ty64 -> register_value\<close>\<close>
+
+definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where
+ " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )"
+ for v :: "(64)Word.word "
+
+
+
+
+\<comment> \<open>\<open>val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)\<close>\<close>
+definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where
+ " vector_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_vector (_, _, v) => just_list (List.map of_regval1 v)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value\<close>\<close>
+definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where
+ " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and size1 :: " int "
+ and is_inc :: " bool "
+ and xs :: " 'a list "
+
+
+\<comment> \<open>\<open>val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)\<close>\<close>
+definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where
+ " list_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_list v => just_list (List.map of_regval1 v)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value\<close>\<close>
+definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where
+ " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and xs :: " 'a list "
+
+
+\<comment> \<open>\<open>val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)\<close>\<close>
+definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where
+ " option_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_option v => Some (Option.bind v of_regval1)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value\<close>\<close>
+definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where
+ " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and v :: " 'a option "
+
+
+
+definition satp_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " satp_ref = ( (|
+ name = (''satp''),
+ read_from = (\<lambda> s . (satp s)),
+ write_to = (\<lambda> v s . (( s (| satp := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition tlb32_ref :: "((regstate),(register_value),((((9),(32),(34),(32))TLB_Entry)option))register_ref " where
+ " tlb32_ref = ( (|
+ name = (''tlb32''),
+ read_from = (\<lambda> s . (tlb32 s)),
+ write_to = (\<lambda> v s . (( s (| tlb32 := v |)))),
+ of_regval = (\<lambda> v . option_of_regval (\<lambda> v . TLB_Entry_9_32_34_32_of_regval v) v),
+ regval_of = (\<lambda> v . regval_of_option (\<lambda> v . regval_of_TLB_Entry_9_32_34_32 v) v) |) )"
+
+
+definition htif_exit_code_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " htif_exit_code_ref = ( (|
+ name = (''htif_exit_code''),
+ read_from = (\<lambda> s . (htif_exit_code s)),
+ write_to = (\<lambda> v s . (( s (| htif_exit_code := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition htif_done_ref :: "((regstate),(register_value),(bool))register_ref " where
+ " htif_done_ref = ( (|
+ name = (''htif_done''),
+ read_from = (\<lambda> s . (htif_done s)),
+ write_to = (\<lambda> v s . (( s (| htif_done := v |)))),
+ of_regval = (\<lambda> v . bool_of_regval v),
+ regval_of = (\<lambda> v . regval_of_bool v) |) )"
+
+
+definition htif_tohost_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " htif_tohost_ref = ( (|
+ name = (''htif_tohost''),
+ read_from = (\<lambda> s . (htif_tohost s)),
+ write_to = (\<lambda> v s . (( s (| htif_tohost := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtimecmp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mtimecmp_ref = ( (|
+ name = (''mtimecmp''),
+ read_from = (\<lambda> s . (mtimecmp s)),
+ write_to = (\<lambda> v s . (( s (| mtimecmp := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition utval_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " utval_ref = ( (|
+ name = (''utval''),
+ read_from = (\<lambda> s . (utval s)),
+ write_to = (\<lambda> v s . (( s (| utval := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition ucause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " ucause_ref = ( (|
+ name = (''ucause''),
+ read_from = (\<lambda> s . (ucause s)),
+ write_to = (\<lambda> v s . (( s (| ucause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition uepc_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " uepc_ref = ( (|
+ name = (''uepc''),
+ read_from = (\<lambda> s . (uepc s)),
+ write_to = (\<lambda> v s . (( s (| uepc := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition uscratch_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " uscratch_ref = ( (|
+ name = (''uscratch''),
+ read_from = (\<lambda> s . (uscratch s)),
+ write_to = (\<lambda> v s . (( s (| uscratch := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition utvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " utvec_ref = ( (|
+ name = (''utvec''),
+ read_from = (\<lambda> s . (utvec s)),
+ write_to = (\<lambda> v s . (( s (| utvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition pmpaddr15_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr15_ref = ( (|
+ name = (''pmpaddr15''),
+ read_from = (\<lambda> s . (pmpaddr15 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr15 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr14_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr14_ref = ( (|
+ name = (''pmpaddr14''),
+ read_from = (\<lambda> s . (pmpaddr14 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr14 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr13_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr13_ref = ( (|
+ name = (''pmpaddr13''),
+ read_from = (\<lambda> s . (pmpaddr13 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr13 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr12_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr12_ref = ( (|
+ name = (''pmpaddr12''),
+ read_from = (\<lambda> s . (pmpaddr12 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr12 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr11_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr11_ref = ( (|
+ name = (''pmpaddr11''),
+ read_from = (\<lambda> s . (pmpaddr11 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr11 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr10_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr10_ref = ( (|
+ name = (''pmpaddr10''),
+ read_from = (\<lambda> s . (pmpaddr10 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr10 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr9_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr9_ref = ( (|
+ name = (''pmpaddr9''),
+ read_from = (\<lambda> s . (pmpaddr9 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr9 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr8_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr8_ref = ( (|
+ name = (''pmpaddr8''),
+ read_from = (\<lambda> s . (pmpaddr8 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr8 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr7_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr7_ref = ( (|
+ name = (''pmpaddr7''),
+ read_from = (\<lambda> s . (pmpaddr7 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr7 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr6_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr6_ref = ( (|
+ name = (''pmpaddr6''),
+ read_from = (\<lambda> s . (pmpaddr6 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr6 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr5_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr5_ref = ( (|
+ name = (''pmpaddr5''),
+ read_from = (\<lambda> s . (pmpaddr5 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr5 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr4_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr4_ref = ( (|
+ name = (''pmpaddr4''),
+ read_from = (\<lambda> s . (pmpaddr4 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr4 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr3_ref = ( (|
+ name = (''pmpaddr3''),
+ read_from = (\<lambda> s . (pmpaddr3 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr3 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr2_ref = ( (|
+ name = (''pmpaddr2''),
+ read_from = (\<lambda> s . (pmpaddr2 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr2 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr1_ref = ( (|
+ name = (''pmpaddr1''),
+ read_from = (\<lambda> s . (pmpaddr1 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr1 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmpaddr0_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " pmpaddr0_ref = ( (|
+ name = (''pmpaddr0''),
+ read_from = (\<lambda> s . (pmpaddr0 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr0 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition pmp15cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp15cfg_ref = ( (|
+ name = (''pmp15cfg''),
+ read_from = (\<lambda> s . (pmp15cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp15cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp14cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp14cfg_ref = ( (|
+ name = (''pmp14cfg''),
+ read_from = (\<lambda> s . (pmp14cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp14cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp13cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp13cfg_ref = ( (|
+ name = (''pmp13cfg''),
+ read_from = (\<lambda> s . (pmp13cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp13cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp12cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp12cfg_ref = ( (|
+ name = (''pmp12cfg''),
+ read_from = (\<lambda> s . (pmp12cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp12cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp11cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp11cfg_ref = ( (|
+ name = (''pmp11cfg''),
+ read_from = (\<lambda> s . (pmp11cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp11cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp10cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp10cfg_ref = ( (|
+ name = (''pmp10cfg''),
+ read_from = (\<lambda> s . (pmp10cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp10cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp9cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp9cfg_ref = ( (|
+ name = (''pmp9cfg''),
+ read_from = (\<lambda> s . (pmp9cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp9cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp8cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp8cfg_ref = ( (|
+ name = (''pmp8cfg''),
+ read_from = (\<lambda> s . (pmp8cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp8cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp7cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp7cfg_ref = ( (|
+ name = (''pmp7cfg''),
+ read_from = (\<lambda> s . (pmp7cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp7cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp6cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp6cfg_ref = ( (|
+ name = (''pmp6cfg''),
+ read_from = (\<lambda> s . (pmp6cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp6cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp5cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp5cfg_ref = ( (|
+ name = (''pmp5cfg''),
+ read_from = (\<lambda> s . (pmp5cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp5cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp4cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp4cfg_ref = ( (|
+ name = (''pmp4cfg''),
+ read_from = (\<lambda> s . (pmp4cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp4cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp3cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp3cfg_ref = ( (|
+ name = (''pmp3cfg''),
+ read_from = (\<lambda> s . (pmp3cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp3cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp2cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp2cfg_ref = ( (|
+ name = (''pmp2cfg''),
+ read_from = (\<lambda> s . (pmp2cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp2cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp1cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp1cfg_ref = ( (|
+ name = (''pmp1cfg''),
+ read_from = (\<lambda> s . (pmp1cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp1cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp0cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp0cfg_ref = ( (|
+ name = (''pmp0cfg''),
+ read_from = (\<lambda> s . (pmp0cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp0cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition tselect_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " tselect_ref = ( (|
+ name = (''tselect''),
+ read_from = (\<lambda> s . (tselect s)),
+ write_to = (\<lambda> v s . (( s (| tselect := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition stval_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " stval_ref = ( (|
+ name = (''stval''),
+ read_from = (\<lambda> s . (stval s)),
+ write_to = (\<lambda> v s . (( s (| stval := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition scause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " scause_ref = ( (|
+ name = (''scause''),
+ read_from = (\<lambda> s . (scause s)),
+ write_to = (\<lambda> v s . (( s (| scause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition sepc_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " sepc_ref = ( (|
+ name = (''sepc''),
+ read_from = (\<lambda> s . (sepc s)),
+ write_to = (\<lambda> v s . (( s (| sepc := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition sscratch_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " sscratch_ref = ( (|
+ name = (''sscratch''),
+ read_from = (\<lambda> s . (sscratch s)),
+ write_to = (\<lambda> v s . (( s (| sscratch := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition stvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " stvec_ref = ( (|
+ name = (''stvec''),
+ read_from = (\<lambda> s . (stvec s)),
+ write_to = (\<lambda> v s . (( s (| stvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition sideleg_ref :: "((regstate),(register_value),(Sinterrupts))register_ref " where
+ " sideleg_ref = ( (|
+ name = (''sideleg''),
+ read_from = (\<lambda> s . (sideleg s)),
+ write_to = (\<lambda> v s . (( s (| sideleg := v |)))),
+ of_regval = (\<lambda> v . Sinterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Sinterrupts v) |) )"
+
+
+definition sedeleg_ref :: "((regstate),(register_value),(Sedeleg))register_ref " where
+ " sedeleg_ref = ( (|
+ name = (''sedeleg''),
+ read_from = (\<lambda> s . (sedeleg s)),
+ write_to = (\<lambda> v s . (( s (| sedeleg := v |)))),
+ of_regval = (\<lambda> v . Sedeleg_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Sedeleg v) |) )"
+
+
+definition mhartid_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mhartid_ref = ( (|
+ name = (''mhartid''),
+ read_from = (\<lambda> s . (mhartid s)),
+ write_to = (\<lambda> v s . (( s (| mhartid := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition marchid_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " marchid_ref = ( (|
+ name = (''marchid''),
+ read_from = (\<lambda> s . (marchid s)),
+ write_to = (\<lambda> v s . (( s (| marchid := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition mimpid_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mimpid_ref = ( (|
+ name = (''mimpid''),
+ read_from = (\<lambda> s . (mimpid s)),
+ write_to = (\<lambda> v s . (( s (| mimpid := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition mvendorid_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mvendorid_ref = ( (|
+ name = (''mvendorid''),
+ read_from = (\<lambda> s . (mvendorid s)),
+ write_to = (\<lambda> v s . (( s (| mvendorid := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition minstret_written_ref :: "((regstate),(register_value),(bool))register_ref " where
+ " minstret_written_ref = ( (|
+ name = (''minstret_written''),
+ read_from = (\<lambda> s . (minstret_written s)),
+ write_to = (\<lambda> v s . (( s (| minstret_written := v |)))),
+ of_regval = (\<lambda> v . bool_of_regval v),
+ regval_of = (\<lambda> v . regval_of_bool v) |) )"
+
+
+definition minstret_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " minstret_ref = ( (|
+ name = (''minstret''),
+ read_from = (\<lambda> s . (minstret s)),
+ write_to = (\<lambda> v s . (( s (| minstret := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtime_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mtime_ref = ( (|
+ name = (''mtime''),
+ read_from = (\<lambda> s . (mtime s)),
+ write_to = (\<lambda> v s . (( s (| mtime := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mcycle_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mcycle_ref = ( (|
+ name = (''mcycle''),
+ read_from = (\<lambda> s . (mcycle s)),
+ write_to = (\<lambda> v s . (( s (| mcycle := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition scounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where
+ " scounteren_ref = ( (|
+ name = (''scounteren''),
+ read_from = (\<lambda> s . (scounteren s)),
+ write_to = (\<lambda> v s . (( s (| scounteren := v |)))),
+ of_regval = (\<lambda> v . Counteren_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Counteren v) |) )"
+
+
+definition mcounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where
+ " mcounteren_ref = ( (|
+ name = (''mcounteren''),
+ read_from = (\<lambda> s . (mcounteren s)),
+ write_to = (\<lambda> v s . (( s (| mcounteren := v |)))),
+ of_regval = (\<lambda> v . Counteren_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Counteren v) |) )"
+
+
+definition mscratch_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mscratch_ref = ( (|
+ name = (''mscratch''),
+ read_from = (\<lambda> s . (mscratch s)),
+ write_to = (\<lambda> v s . (( s (| mscratch := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition mtval_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mtval_ref = ( (|
+ name = (''mtval''),
+ read_from = (\<lambda> s . (mtval s)),
+ write_to = (\<lambda> v s . (( s (| mtval := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition mepc_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mepc_ref = ( (|
+ name = (''mepc''),
+ read_from = (\<lambda> s . (mepc s)),
+ write_to = (\<lambda> v s . (( s (| mepc := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition mcause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " mcause_ref = ( (|
+ name = (''mcause''),
+ read_from = (\<lambda> s . (mcause s)),
+ write_to = (\<lambda> v s . (( s (| mcause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition mtvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " mtvec_ref = ( (|
+ name = (''mtvec''),
+ read_from = (\<lambda> s . (mtvec s)),
+ write_to = (\<lambda> v s . (( s (| mtvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition medeleg_ref :: "((regstate),(register_value),(Medeleg))register_ref " where
+ " medeleg_ref = ( (|
+ name = (''medeleg''),
+ read_from = (\<lambda> s . (medeleg s)),
+ write_to = (\<lambda> v s . (( s (| medeleg := v |)))),
+ of_regval = (\<lambda> v . Medeleg_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Medeleg v) |) )"
+
+
+definition mideleg_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mideleg_ref = ( (|
+ name = (''mideleg''),
+ read_from = (\<lambda> s . (mideleg s)),
+ write_to = (\<lambda> v s . (( s (| mideleg := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mie_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mie_ref = ( (|
+ name = (''mie''),
+ read_from = (\<lambda> s . (mie s)),
+ write_to = (\<lambda> v s . (( s (| mie := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mip_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mip_ref = ( (|
+ name = (''mip''),
+ read_from = (\<lambda> s . (mip s)),
+ write_to = (\<lambda> v s . (( s (| mip := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mstatus_ref :: "((regstate),(register_value),(Mstatus))register_ref " where
+ " mstatus_ref = ( (|
+ name = (''mstatus''),
+ read_from = (\<lambda> s . (mstatus s)),
+ write_to = (\<lambda> v s . (( s (| mstatus := v |)))),
+ of_regval = (\<lambda> v . Mstatus_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mstatus v) |) )"
+
+
+definition misa_ref :: "((regstate),(register_value),(Misa))register_ref " where
+ " misa_ref = ( (|
+ name = (''misa''),
+ read_from = (\<lambda> s . (misa s)),
+ write_to = (\<lambda> v s . (( s (| misa := v |)))),
+ of_regval = (\<lambda> v . Misa_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Misa v) |) )"
+
+
+definition cur_inst_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " cur_inst_ref = ( (|
+ name = (''cur_inst''),
+ read_from = (\<lambda> s . (cur_inst s)),
+ write_to = (\<lambda> v s . (( s (| cur_inst := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition cur_privilege_ref :: "((regstate),(register_value),(Privilege))register_ref " where
+ " cur_privilege_ref = ( (|
+ name = (''cur_privilege''),
+ read_from = (\<lambda> s . (cur_privilege s)),
+ write_to = (\<lambda> v s . (( s (| cur_privilege := v |)))),
+ of_regval = (\<lambda> v . Privilege_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Privilege v) |) )"
+
+
+definition x31_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x31_ref = ( (|
+ name = (''x31''),
+ read_from = (\<lambda> s . (x31 s)),
+ write_to = (\<lambda> v s . (( s (| x31 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x30_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x30_ref = ( (|
+ name = (''x30''),
+ read_from = (\<lambda> s . (x30 s)),
+ write_to = (\<lambda> v s . (( s (| x30 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x29_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x29_ref = ( (|
+ name = (''x29''),
+ read_from = (\<lambda> s . (x29 s)),
+ write_to = (\<lambda> v s . (( s (| x29 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x28_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x28_ref = ( (|
+ name = (''x28''),
+ read_from = (\<lambda> s . (x28 s)),
+ write_to = (\<lambda> v s . (( s (| x28 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x27_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x27_ref = ( (|
+ name = (''x27''),
+ read_from = (\<lambda> s . (x27 s)),
+ write_to = (\<lambda> v s . (( s (| x27 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x26_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x26_ref = ( (|
+ name = (''x26''),
+ read_from = (\<lambda> s . (x26 s)),
+ write_to = (\<lambda> v s . (( s (| x26 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x25_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x25_ref = ( (|
+ name = (''x25''),
+ read_from = (\<lambda> s . (x25 s)),
+ write_to = (\<lambda> v s . (( s (| x25 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x24_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x24_ref = ( (|
+ name = (''x24''),
+ read_from = (\<lambda> s . (x24 s)),
+ write_to = (\<lambda> v s . (( s (| x24 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x23_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x23_ref = ( (|
+ name = (''x23''),
+ read_from = (\<lambda> s . (x23 s)),
+ write_to = (\<lambda> v s . (( s (| x23 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x22_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x22_ref = ( (|
+ name = (''x22''),
+ read_from = (\<lambda> s . (x22 s)),
+ write_to = (\<lambda> v s . (( s (| x22 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x21_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x21_ref = ( (|
+ name = (''x21''),
+ read_from = (\<lambda> s . (x21 s)),
+ write_to = (\<lambda> v s . (( s (| x21 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x20_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x20_ref = ( (|
+ name = (''x20''),
+ read_from = (\<lambda> s . (x20 s)),
+ write_to = (\<lambda> v s . (( s (| x20 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x19_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x19_ref = ( (|
+ name = (''x19''),
+ read_from = (\<lambda> s . (x19 s)),
+ write_to = (\<lambda> v s . (( s (| x19 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x18_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x18_ref = ( (|
+ name = (''x18''),
+ read_from = (\<lambda> s . (x18 s)),
+ write_to = (\<lambda> v s . (( s (| x18 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x17_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x17_ref = ( (|
+ name = (''x17''),
+ read_from = (\<lambda> s . (x17 s)),
+ write_to = (\<lambda> v s . (( s (| x17 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x16_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x16_ref = ( (|
+ name = (''x16''),
+ read_from = (\<lambda> s . (x16 s)),
+ write_to = (\<lambda> v s . (( s (| x16 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x15_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x15_ref = ( (|
+ name = (''x15''),
+ read_from = (\<lambda> s . (x15 s)),
+ write_to = (\<lambda> v s . (( s (| x15 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x14_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x14_ref = ( (|
+ name = (''x14''),
+ read_from = (\<lambda> s . (x14 s)),
+ write_to = (\<lambda> v s . (( s (| x14 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x13_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x13_ref = ( (|
+ name = (''x13''),
+ read_from = (\<lambda> s . (x13 s)),
+ write_to = (\<lambda> v s . (( s (| x13 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x12_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x12_ref = ( (|
+ name = (''x12''),
+ read_from = (\<lambda> s . (x12 s)),
+ write_to = (\<lambda> v s . (( s (| x12 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x11_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x11_ref = ( (|
+ name = (''x11''),
+ read_from = (\<lambda> s . (x11 s)),
+ write_to = (\<lambda> v s . (( s (| x11 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x10_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x10_ref = ( (|
+ name = (''x10''),
+ read_from = (\<lambda> s . (x10 s)),
+ write_to = (\<lambda> v s . (( s (| x10 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x9_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x9_ref = ( (|
+ name = (''x9''),
+ read_from = (\<lambda> s . (x9 s)),
+ write_to = (\<lambda> v s . (( s (| x9 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x8_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x8_ref = ( (|
+ name = (''x8''),
+ read_from = (\<lambda> s . (x8 s)),
+ write_to = (\<lambda> v s . (( s (| x8 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x7_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x7_ref = ( (|
+ name = (''x7''),
+ read_from = (\<lambda> s . (x7 s)),
+ write_to = (\<lambda> v s . (( s (| x7 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x6_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x6_ref = ( (|
+ name = (''x6''),
+ read_from = (\<lambda> s . (x6 s)),
+ write_to = (\<lambda> v s . (( s (| x6 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x5_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x5_ref = ( (|
+ name = (''x5''),
+ read_from = (\<lambda> s . (x5 s)),
+ write_to = (\<lambda> v s . (( s (| x5 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x4_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x4_ref = ( (|
+ name = (''x4''),
+ read_from = (\<lambda> s . (x4 s)),
+ write_to = (\<lambda> v s . (( s (| x4 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x3_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x3_ref = ( (|
+ name = (''x3''),
+ read_from = (\<lambda> s . (x3 s)),
+ write_to = (\<lambda> v s . (( s (| x3 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x2_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x2_ref = ( (|
+ name = (''x2''),
+ read_from = (\<lambda> s . (x2 s)),
+ write_to = (\<lambda> v s . (( s (| x2 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition x1_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " x1_ref = ( (|
+ name = (''x1''),
+ read_from = (\<lambda> s . (x1 s)),
+ write_to = (\<lambda> v s . (( s (| x1 := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition Xs_ref :: "((regstate),(register_value),(((32)Word.word)list))register_ref " where
+ " Xs_ref = ( (|
+ name = (''Xs''),
+ read_from = (\<lambda> s . (Xs s)),
+ write_to = (\<lambda> v s . (( s (| Xs := v |)))),
+ of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_32_dec_bit_of_regval v) v),
+ regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_32_dec_bit v)(( 32 :: int)) False v) |) )"
+
+
+definition instbits_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " instbits_ref = ( (|
+ name = (''instbits''),
+ read_from = (\<lambda> s . (instbits s)),
+ write_to = (\<lambda> v s . (( s (| instbits := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition nextPC_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " nextPC_ref = ( (|
+ name = (''nextPC''),
+ read_from = (\<lambda> s . (nextPC s)),
+ write_to = (\<lambda> v s . (( s (| nextPC := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition PC_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " PC_ref = ( (|
+ name = (''PC''),
+ read_from = (\<lambda> s . (PC s)),
+ write_to = (\<lambda> v s . (( s (| PC := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+\<comment> \<open>\<open>val get_regval : string -> regstate -> maybe register_value\<close>\<close>
+definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where
+ " get_regval reg_name s = (
+ if reg_name = (''satp'') then Some ((regval_of satp_ref) ((read_from satp_ref) s)) else
+ if reg_name = (''tlb32'') then Some ((regval_of tlb32_ref) ((read_from tlb32_ref) s)) else
+ if reg_name = (''htif_exit_code'') then Some ((regval_of htif_exit_code_ref) ((read_from htif_exit_code_ref) s)) else
+ if reg_name = (''htif_done'') then Some ((regval_of htif_done_ref) ((read_from htif_done_ref) s)) else
+ if reg_name = (''htif_tohost'') then Some ((regval_of htif_tohost_ref) ((read_from htif_tohost_ref) s)) else
+ if reg_name = (''mtimecmp'') then Some ((regval_of mtimecmp_ref) ((read_from mtimecmp_ref) s)) else
+ if reg_name = (''utval'') then Some ((regval_of utval_ref) ((read_from utval_ref) s)) else
+ if reg_name = (''ucause'') then Some ((regval_of ucause_ref) ((read_from ucause_ref) s)) else
+ if reg_name = (''uepc'') then Some ((regval_of uepc_ref) ((read_from uepc_ref) s)) else
+ if reg_name = (''uscratch'') then Some ((regval_of uscratch_ref) ((read_from uscratch_ref) s)) else
+ if reg_name = (''utvec'') then Some ((regval_of utvec_ref) ((read_from utvec_ref) s)) else
+ if reg_name = (''pmpaddr15'') then Some ((regval_of pmpaddr15_ref) ((read_from pmpaddr15_ref) s)) else
+ if reg_name = (''pmpaddr14'') then Some ((regval_of pmpaddr14_ref) ((read_from pmpaddr14_ref) s)) else
+ if reg_name = (''pmpaddr13'') then Some ((regval_of pmpaddr13_ref) ((read_from pmpaddr13_ref) s)) else
+ if reg_name = (''pmpaddr12'') then Some ((regval_of pmpaddr12_ref) ((read_from pmpaddr12_ref) s)) else
+ if reg_name = (''pmpaddr11'') then Some ((regval_of pmpaddr11_ref) ((read_from pmpaddr11_ref) s)) else
+ if reg_name = (''pmpaddr10'') then Some ((regval_of pmpaddr10_ref) ((read_from pmpaddr10_ref) s)) else
+ if reg_name = (''pmpaddr9'') then Some ((regval_of pmpaddr9_ref) ((read_from pmpaddr9_ref) s)) else
+ if reg_name = (''pmpaddr8'') then Some ((regval_of pmpaddr8_ref) ((read_from pmpaddr8_ref) s)) else
+ if reg_name = (''pmpaddr7'') then Some ((regval_of pmpaddr7_ref) ((read_from pmpaddr7_ref) s)) else
+ if reg_name = (''pmpaddr6'') then Some ((regval_of pmpaddr6_ref) ((read_from pmpaddr6_ref) s)) else
+ if reg_name = (''pmpaddr5'') then Some ((regval_of pmpaddr5_ref) ((read_from pmpaddr5_ref) s)) else
+ if reg_name = (''pmpaddr4'') then Some ((regval_of pmpaddr4_ref) ((read_from pmpaddr4_ref) s)) else
+ if reg_name = (''pmpaddr3'') then Some ((regval_of pmpaddr3_ref) ((read_from pmpaddr3_ref) s)) else
+ if reg_name = (''pmpaddr2'') then Some ((regval_of pmpaddr2_ref) ((read_from pmpaddr2_ref) s)) else
+ if reg_name = (''pmpaddr1'') then Some ((regval_of pmpaddr1_ref) ((read_from pmpaddr1_ref) s)) else
+ if reg_name = (''pmpaddr0'') then Some ((regval_of pmpaddr0_ref) ((read_from pmpaddr0_ref) s)) else
+ if reg_name = (''pmp15cfg'') then Some ((regval_of pmp15cfg_ref) ((read_from pmp15cfg_ref) s)) else
+ if reg_name = (''pmp14cfg'') then Some ((regval_of pmp14cfg_ref) ((read_from pmp14cfg_ref) s)) else
+ if reg_name = (''pmp13cfg'') then Some ((regval_of pmp13cfg_ref) ((read_from pmp13cfg_ref) s)) else
+ if reg_name = (''pmp12cfg'') then Some ((regval_of pmp12cfg_ref) ((read_from pmp12cfg_ref) s)) else
+ if reg_name = (''pmp11cfg'') then Some ((regval_of pmp11cfg_ref) ((read_from pmp11cfg_ref) s)) else
+ if reg_name = (''pmp10cfg'') then Some ((regval_of pmp10cfg_ref) ((read_from pmp10cfg_ref) s)) else
+ if reg_name = (''pmp9cfg'') then Some ((regval_of pmp9cfg_ref) ((read_from pmp9cfg_ref) s)) else
+ if reg_name = (''pmp8cfg'') then Some ((regval_of pmp8cfg_ref) ((read_from pmp8cfg_ref) s)) else
+ if reg_name = (''pmp7cfg'') then Some ((regval_of pmp7cfg_ref) ((read_from pmp7cfg_ref) s)) else
+ if reg_name = (''pmp6cfg'') then Some ((regval_of pmp6cfg_ref) ((read_from pmp6cfg_ref) s)) else
+ if reg_name = (''pmp5cfg'') then Some ((regval_of pmp5cfg_ref) ((read_from pmp5cfg_ref) s)) else
+ if reg_name = (''pmp4cfg'') then Some ((regval_of pmp4cfg_ref) ((read_from pmp4cfg_ref) s)) else
+ if reg_name = (''pmp3cfg'') then Some ((regval_of pmp3cfg_ref) ((read_from pmp3cfg_ref) s)) else
+ if reg_name = (''pmp2cfg'') then Some ((regval_of pmp2cfg_ref) ((read_from pmp2cfg_ref) s)) else
+ if reg_name = (''pmp1cfg'') then Some ((regval_of pmp1cfg_ref) ((read_from pmp1cfg_ref) s)) else
+ if reg_name = (''pmp0cfg'') then Some ((regval_of pmp0cfg_ref) ((read_from pmp0cfg_ref) s)) else
+ if reg_name = (''tselect'') then Some ((regval_of tselect_ref) ((read_from tselect_ref) s)) else
+ if reg_name = (''stval'') then Some ((regval_of stval_ref) ((read_from stval_ref) s)) else
+ if reg_name = (''scause'') then Some ((regval_of scause_ref) ((read_from scause_ref) s)) else
+ if reg_name = (''sepc'') then Some ((regval_of sepc_ref) ((read_from sepc_ref) s)) else
+ if reg_name = (''sscratch'') then Some ((regval_of sscratch_ref) ((read_from sscratch_ref) s)) else
+ if reg_name = (''stvec'') then Some ((regval_of stvec_ref) ((read_from stvec_ref) s)) else
+ if reg_name = (''sideleg'') then Some ((regval_of sideleg_ref) ((read_from sideleg_ref) s)) else
+ if reg_name = (''sedeleg'') then Some ((regval_of sedeleg_ref) ((read_from sedeleg_ref) s)) else
+ if reg_name = (''mhartid'') then Some ((regval_of mhartid_ref) ((read_from mhartid_ref) s)) else
+ if reg_name = (''marchid'') then Some ((regval_of marchid_ref) ((read_from marchid_ref) s)) else
+ if reg_name = (''mimpid'') then Some ((regval_of mimpid_ref) ((read_from mimpid_ref) s)) else
+ if reg_name = (''mvendorid'') then Some ((regval_of mvendorid_ref) ((read_from mvendorid_ref) s)) else
+ if reg_name = (''minstret_written'') then Some ((regval_of minstret_written_ref) ((read_from minstret_written_ref) s)) else
+ if reg_name = (''minstret'') then Some ((regval_of minstret_ref) ((read_from minstret_ref) s)) else
+ if reg_name = (''mtime'') then Some ((regval_of mtime_ref) ((read_from mtime_ref) s)) else
+ if reg_name = (''mcycle'') then Some ((regval_of mcycle_ref) ((read_from mcycle_ref) s)) else
+ if reg_name = (''scounteren'') then Some ((regval_of scounteren_ref) ((read_from scounteren_ref) s)) else
+ if reg_name = (''mcounteren'') then Some ((regval_of mcounteren_ref) ((read_from mcounteren_ref) s)) else
+ if reg_name = (''mscratch'') then Some ((regval_of mscratch_ref) ((read_from mscratch_ref) s)) else
+ if reg_name = (''mtval'') then Some ((regval_of mtval_ref) ((read_from mtval_ref) s)) else
+ if reg_name = (''mepc'') then Some ((regval_of mepc_ref) ((read_from mepc_ref) s)) else
+ if reg_name = (''mcause'') then Some ((regval_of mcause_ref) ((read_from mcause_ref) s)) else
+ if reg_name = (''mtvec'') then Some ((regval_of mtvec_ref) ((read_from mtvec_ref) s)) else
+ if reg_name = (''medeleg'') then Some ((regval_of medeleg_ref) ((read_from medeleg_ref) s)) else
+ if reg_name = (''mideleg'') then Some ((regval_of mideleg_ref) ((read_from mideleg_ref) s)) else
+ if reg_name = (''mie'') then Some ((regval_of mie_ref) ((read_from mie_ref) s)) else
+ if reg_name = (''mip'') then Some ((regval_of mip_ref) ((read_from mip_ref) s)) else
+ if reg_name = (''mstatus'') then Some ((regval_of mstatus_ref) ((read_from mstatus_ref) s)) else
+ if reg_name = (''misa'') then Some ((regval_of misa_ref) ((read_from misa_ref) s)) else
+ if reg_name = (''cur_inst'') then Some ((regval_of cur_inst_ref) ((read_from cur_inst_ref) s)) else
+ if reg_name = (''cur_privilege'') then Some ((regval_of cur_privilege_ref) ((read_from cur_privilege_ref) s)) else
+ if reg_name = (''x31'') then Some ((regval_of x31_ref) ((read_from x31_ref) s)) else
+ if reg_name = (''x30'') then Some ((regval_of x30_ref) ((read_from x30_ref) s)) else
+ if reg_name = (''x29'') then Some ((regval_of x29_ref) ((read_from x29_ref) s)) else
+ if reg_name = (''x28'') then Some ((regval_of x28_ref) ((read_from x28_ref) s)) else
+ if reg_name = (''x27'') then Some ((regval_of x27_ref) ((read_from x27_ref) s)) else
+ if reg_name = (''x26'') then Some ((regval_of x26_ref) ((read_from x26_ref) s)) else
+ if reg_name = (''x25'') then Some ((regval_of x25_ref) ((read_from x25_ref) s)) else
+ if reg_name = (''x24'') then Some ((regval_of x24_ref) ((read_from x24_ref) s)) else
+ if reg_name = (''x23'') then Some ((regval_of x23_ref) ((read_from x23_ref) s)) else
+ if reg_name = (''x22'') then Some ((regval_of x22_ref) ((read_from x22_ref) s)) else
+ if reg_name = (''x21'') then Some ((regval_of x21_ref) ((read_from x21_ref) s)) else
+ if reg_name = (''x20'') then Some ((regval_of x20_ref) ((read_from x20_ref) s)) else
+ if reg_name = (''x19'') then Some ((regval_of x19_ref) ((read_from x19_ref) s)) else
+ if reg_name = (''x18'') then Some ((regval_of x18_ref) ((read_from x18_ref) s)) else
+ if reg_name = (''x17'') then Some ((regval_of x17_ref) ((read_from x17_ref) s)) else
+ if reg_name = (''x16'') then Some ((regval_of x16_ref) ((read_from x16_ref) s)) else
+ if reg_name = (''x15'') then Some ((regval_of x15_ref) ((read_from x15_ref) s)) else
+ if reg_name = (''x14'') then Some ((regval_of x14_ref) ((read_from x14_ref) s)) else
+ if reg_name = (''x13'') then Some ((regval_of x13_ref) ((read_from x13_ref) s)) else
+ if reg_name = (''x12'') then Some ((regval_of x12_ref) ((read_from x12_ref) s)) else
+ if reg_name = (''x11'') then Some ((regval_of x11_ref) ((read_from x11_ref) s)) else
+ if reg_name = (''x10'') then Some ((regval_of x10_ref) ((read_from x10_ref) s)) else
+ if reg_name = (''x9'') then Some ((regval_of x9_ref) ((read_from x9_ref) s)) else
+ if reg_name = (''x8'') then Some ((regval_of x8_ref) ((read_from x8_ref) s)) else
+ if reg_name = (''x7'') then Some ((regval_of x7_ref) ((read_from x7_ref) s)) else
+ if reg_name = (''x6'') then Some ((regval_of x6_ref) ((read_from x6_ref) s)) else
+ if reg_name = (''x5'') then Some ((regval_of x5_ref) ((read_from x5_ref) s)) else
+ if reg_name = (''x4'') then Some ((regval_of x4_ref) ((read_from x4_ref) s)) else
+ if reg_name = (''x3'') then Some ((regval_of x3_ref) ((read_from x3_ref) s)) else
+ if reg_name = (''x2'') then Some ((regval_of x2_ref) ((read_from x2_ref) s)) else
+ if reg_name = (''x1'') then Some ((regval_of x1_ref) ((read_from x1_ref) s)) else
+ if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else
+ if reg_name = (''instbits'') then Some ((regval_of instbits_ref) ((read_from instbits_ref) s)) else
+ if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else
+ if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else
+ None )"
+ for reg_name :: " string "
+ and s :: " regstate "
+
+
+\<comment> \<open>\<open>val set_regval : string -> register_value -> regstate -> maybe regstate\<close>\<close>
+definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where
+ " set_regval reg_name v s = (
+ if reg_name = (''satp'') then map_option (\<lambda> v . (write_to satp_ref) v s) ((of_regval satp_ref) v) else
+ if reg_name = (''tlb32'') then map_option (\<lambda> v . (write_to tlb32_ref) v s) ((of_regval tlb32_ref) v) else
+ if reg_name = (''htif_exit_code'') then map_option (\<lambda> v . (write_to htif_exit_code_ref) v s) ((of_regval htif_exit_code_ref) v) else
+ if reg_name = (''htif_done'') then map_option (\<lambda> v . (write_to htif_done_ref) v s) ((of_regval htif_done_ref) v) else
+ if reg_name = (''htif_tohost'') then map_option (\<lambda> v . (write_to htif_tohost_ref) v s) ((of_regval htif_tohost_ref) v) else
+ if reg_name = (''mtimecmp'') then map_option (\<lambda> v . (write_to mtimecmp_ref) v s) ((of_regval mtimecmp_ref) v) else
+ if reg_name = (''utval'') then map_option (\<lambda> v . (write_to utval_ref) v s) ((of_regval utval_ref) v) else
+ if reg_name = (''ucause'') then map_option (\<lambda> v . (write_to ucause_ref) v s) ((of_regval ucause_ref) v) else
+ if reg_name = (''uepc'') then map_option (\<lambda> v . (write_to uepc_ref) v s) ((of_regval uepc_ref) v) else
+ if reg_name = (''uscratch'') then map_option (\<lambda> v . (write_to uscratch_ref) v s) ((of_regval uscratch_ref) v) else
+ if reg_name = (''utvec'') then map_option (\<lambda> v . (write_to utvec_ref) v s) ((of_regval utvec_ref) v) else
+ if reg_name = (''pmpaddr15'') then map_option (\<lambda> v . (write_to pmpaddr15_ref) v s) ((of_regval pmpaddr15_ref) v) else
+ if reg_name = (''pmpaddr14'') then map_option (\<lambda> v . (write_to pmpaddr14_ref) v s) ((of_regval pmpaddr14_ref) v) else
+ if reg_name = (''pmpaddr13'') then map_option (\<lambda> v . (write_to pmpaddr13_ref) v s) ((of_regval pmpaddr13_ref) v) else
+ if reg_name = (''pmpaddr12'') then map_option (\<lambda> v . (write_to pmpaddr12_ref) v s) ((of_regval pmpaddr12_ref) v) else
+ if reg_name = (''pmpaddr11'') then map_option (\<lambda> v . (write_to pmpaddr11_ref) v s) ((of_regval pmpaddr11_ref) v) else
+ if reg_name = (''pmpaddr10'') then map_option (\<lambda> v . (write_to pmpaddr10_ref) v s) ((of_regval pmpaddr10_ref) v) else
+ if reg_name = (''pmpaddr9'') then map_option (\<lambda> v . (write_to pmpaddr9_ref) v s) ((of_regval pmpaddr9_ref) v) else
+ if reg_name = (''pmpaddr8'') then map_option (\<lambda> v . (write_to pmpaddr8_ref) v s) ((of_regval pmpaddr8_ref) v) else
+ if reg_name = (''pmpaddr7'') then map_option (\<lambda> v . (write_to pmpaddr7_ref) v s) ((of_regval pmpaddr7_ref) v) else
+ if reg_name = (''pmpaddr6'') then map_option (\<lambda> v . (write_to pmpaddr6_ref) v s) ((of_regval pmpaddr6_ref) v) else
+ if reg_name = (''pmpaddr5'') then map_option (\<lambda> v . (write_to pmpaddr5_ref) v s) ((of_regval pmpaddr5_ref) v) else
+ if reg_name = (''pmpaddr4'') then map_option (\<lambda> v . (write_to pmpaddr4_ref) v s) ((of_regval pmpaddr4_ref) v) else
+ if reg_name = (''pmpaddr3'') then map_option (\<lambda> v . (write_to pmpaddr3_ref) v s) ((of_regval pmpaddr3_ref) v) else
+ if reg_name = (''pmpaddr2'') then map_option (\<lambda> v . (write_to pmpaddr2_ref) v s) ((of_regval pmpaddr2_ref) v) else
+ if reg_name = (''pmpaddr1'') then map_option (\<lambda> v . (write_to pmpaddr1_ref) v s) ((of_regval pmpaddr1_ref) v) else
+ if reg_name = (''pmpaddr0'') then map_option (\<lambda> v . (write_to pmpaddr0_ref) v s) ((of_regval pmpaddr0_ref) v) else
+ if reg_name = (''pmp15cfg'') then map_option (\<lambda> v . (write_to pmp15cfg_ref) v s) ((of_regval pmp15cfg_ref) v) else
+ if reg_name = (''pmp14cfg'') then map_option (\<lambda> v . (write_to pmp14cfg_ref) v s) ((of_regval pmp14cfg_ref) v) else
+ if reg_name = (''pmp13cfg'') then map_option (\<lambda> v . (write_to pmp13cfg_ref) v s) ((of_regval pmp13cfg_ref) v) else
+ if reg_name = (''pmp12cfg'') then map_option (\<lambda> v . (write_to pmp12cfg_ref) v s) ((of_regval pmp12cfg_ref) v) else
+ if reg_name = (''pmp11cfg'') then map_option (\<lambda> v . (write_to pmp11cfg_ref) v s) ((of_regval pmp11cfg_ref) v) else
+ if reg_name = (''pmp10cfg'') then map_option (\<lambda> v . (write_to pmp10cfg_ref) v s) ((of_regval pmp10cfg_ref) v) else
+ if reg_name = (''pmp9cfg'') then map_option (\<lambda> v . (write_to pmp9cfg_ref) v s) ((of_regval pmp9cfg_ref) v) else
+ if reg_name = (''pmp8cfg'') then map_option (\<lambda> v . (write_to pmp8cfg_ref) v s) ((of_regval pmp8cfg_ref) v) else
+ if reg_name = (''pmp7cfg'') then map_option (\<lambda> v . (write_to pmp7cfg_ref) v s) ((of_regval pmp7cfg_ref) v) else
+ if reg_name = (''pmp6cfg'') then map_option (\<lambda> v . (write_to pmp6cfg_ref) v s) ((of_regval pmp6cfg_ref) v) else
+ if reg_name = (''pmp5cfg'') then map_option (\<lambda> v . (write_to pmp5cfg_ref) v s) ((of_regval pmp5cfg_ref) v) else
+ if reg_name = (''pmp4cfg'') then map_option (\<lambda> v . (write_to pmp4cfg_ref) v s) ((of_regval pmp4cfg_ref) v) else
+ if reg_name = (''pmp3cfg'') then map_option (\<lambda> v . (write_to pmp3cfg_ref) v s) ((of_regval pmp3cfg_ref) v) else
+ if reg_name = (''pmp2cfg'') then map_option (\<lambda> v . (write_to pmp2cfg_ref) v s) ((of_regval pmp2cfg_ref) v) else
+ if reg_name = (''pmp1cfg'') then map_option (\<lambda> v . (write_to pmp1cfg_ref) v s) ((of_regval pmp1cfg_ref) v) else
+ if reg_name = (''pmp0cfg'') then map_option (\<lambda> v . (write_to pmp0cfg_ref) v s) ((of_regval pmp0cfg_ref) v) else
+ if reg_name = (''tselect'') then map_option (\<lambda> v . (write_to tselect_ref) v s) ((of_regval tselect_ref) v) else
+ if reg_name = (''stval'') then map_option (\<lambda> v . (write_to stval_ref) v s) ((of_regval stval_ref) v) else
+ if reg_name = (''scause'') then map_option (\<lambda> v . (write_to scause_ref) v s) ((of_regval scause_ref) v) else
+ if reg_name = (''sepc'') then map_option (\<lambda> v . (write_to sepc_ref) v s) ((of_regval sepc_ref) v) else
+ if reg_name = (''sscratch'') then map_option (\<lambda> v . (write_to sscratch_ref) v s) ((of_regval sscratch_ref) v) else
+ if reg_name = (''stvec'') then map_option (\<lambda> v . (write_to stvec_ref) v s) ((of_regval stvec_ref) v) else
+ if reg_name = (''sideleg'') then map_option (\<lambda> v . (write_to sideleg_ref) v s) ((of_regval sideleg_ref) v) else
+ if reg_name = (''sedeleg'') then map_option (\<lambda> v . (write_to sedeleg_ref) v s) ((of_regval sedeleg_ref) v) else
+ if reg_name = (''mhartid'') then map_option (\<lambda> v . (write_to mhartid_ref) v s) ((of_regval mhartid_ref) v) else
+ if reg_name = (''marchid'') then map_option (\<lambda> v . (write_to marchid_ref) v s) ((of_regval marchid_ref) v) else
+ if reg_name = (''mimpid'') then map_option (\<lambda> v . (write_to mimpid_ref) v s) ((of_regval mimpid_ref) v) else
+ if reg_name = (''mvendorid'') then map_option (\<lambda> v . (write_to mvendorid_ref) v s) ((of_regval mvendorid_ref) v) else
+ if reg_name = (''minstret_written'') then map_option (\<lambda> v . (write_to minstret_written_ref) v s) ((of_regval minstret_written_ref) v) else
+ if reg_name = (''minstret'') then map_option (\<lambda> v . (write_to minstret_ref) v s) ((of_regval minstret_ref) v) else
+ if reg_name = (''mtime'') then map_option (\<lambda> v . (write_to mtime_ref) v s) ((of_regval mtime_ref) v) else
+ if reg_name = (''mcycle'') then map_option (\<lambda> v . (write_to mcycle_ref) v s) ((of_regval mcycle_ref) v) else
+ if reg_name = (''scounteren'') then map_option (\<lambda> v . (write_to scounteren_ref) v s) ((of_regval scounteren_ref) v) else
+ if reg_name = (''mcounteren'') then map_option (\<lambda> v . (write_to mcounteren_ref) v s) ((of_regval mcounteren_ref) v) else
+ if reg_name = (''mscratch'') then map_option (\<lambda> v . (write_to mscratch_ref) v s) ((of_regval mscratch_ref) v) else
+ if reg_name = (''mtval'') then map_option (\<lambda> v . (write_to mtval_ref) v s) ((of_regval mtval_ref) v) else
+ if reg_name = (''mepc'') then map_option (\<lambda> v . (write_to mepc_ref) v s) ((of_regval mepc_ref) v) else
+ if reg_name = (''mcause'') then map_option (\<lambda> v . (write_to mcause_ref) v s) ((of_regval mcause_ref) v) else
+ if reg_name = (''mtvec'') then map_option (\<lambda> v . (write_to mtvec_ref) v s) ((of_regval mtvec_ref) v) else
+ if reg_name = (''medeleg'') then map_option (\<lambda> v . (write_to medeleg_ref) v s) ((of_regval medeleg_ref) v) else
+ if reg_name = (''mideleg'') then map_option (\<lambda> v . (write_to mideleg_ref) v s) ((of_regval mideleg_ref) v) else
+ if reg_name = (''mie'') then map_option (\<lambda> v . (write_to mie_ref) v s) ((of_regval mie_ref) v) else
+ if reg_name = (''mip'') then map_option (\<lambda> v . (write_to mip_ref) v s) ((of_regval mip_ref) v) else
+ if reg_name = (''mstatus'') then map_option (\<lambda> v . (write_to mstatus_ref) v s) ((of_regval mstatus_ref) v) else
+ if reg_name = (''misa'') then map_option (\<lambda> v . (write_to misa_ref) v s) ((of_regval misa_ref) v) else
+ if reg_name = (''cur_inst'') then map_option (\<lambda> v . (write_to cur_inst_ref) v s) ((of_regval cur_inst_ref) v) else
+ if reg_name = (''cur_privilege'') then map_option (\<lambda> v . (write_to cur_privilege_ref) v s) ((of_regval cur_privilege_ref) v) else
+ if reg_name = (''x31'') then map_option (\<lambda> v . (write_to x31_ref) v s) ((of_regval x31_ref) v) else
+ if reg_name = (''x30'') then map_option (\<lambda> v . (write_to x30_ref) v s) ((of_regval x30_ref) v) else
+ if reg_name = (''x29'') then map_option (\<lambda> v . (write_to x29_ref) v s) ((of_regval x29_ref) v) else
+ if reg_name = (''x28'') then map_option (\<lambda> v . (write_to x28_ref) v s) ((of_regval x28_ref) v) else
+ if reg_name = (''x27'') then map_option (\<lambda> v . (write_to x27_ref) v s) ((of_regval x27_ref) v) else
+ if reg_name = (''x26'') then map_option (\<lambda> v . (write_to x26_ref) v s) ((of_regval x26_ref) v) else
+ if reg_name = (''x25'') then map_option (\<lambda> v . (write_to x25_ref) v s) ((of_regval x25_ref) v) else
+ if reg_name = (''x24'') then map_option (\<lambda> v . (write_to x24_ref) v s) ((of_regval x24_ref) v) else
+ if reg_name = (''x23'') then map_option (\<lambda> v . (write_to x23_ref) v s) ((of_regval x23_ref) v) else
+ if reg_name = (''x22'') then map_option (\<lambda> v . (write_to x22_ref) v s) ((of_regval x22_ref) v) else
+ if reg_name = (''x21'') then map_option (\<lambda> v . (write_to x21_ref) v s) ((of_regval x21_ref) v) else
+ if reg_name = (''x20'') then map_option (\<lambda> v . (write_to x20_ref) v s) ((of_regval x20_ref) v) else
+ if reg_name = (''x19'') then map_option (\<lambda> v . (write_to x19_ref) v s) ((of_regval x19_ref) v) else
+ if reg_name = (''x18'') then map_option (\<lambda> v . (write_to x18_ref) v s) ((of_regval x18_ref) v) else
+ if reg_name = (''x17'') then map_option (\<lambda> v . (write_to x17_ref) v s) ((of_regval x17_ref) v) else
+ if reg_name = (''x16'') then map_option (\<lambda> v . (write_to x16_ref) v s) ((of_regval x16_ref) v) else
+ if reg_name = (''x15'') then map_option (\<lambda> v . (write_to x15_ref) v s) ((of_regval x15_ref) v) else
+ if reg_name = (''x14'') then map_option (\<lambda> v . (write_to x14_ref) v s) ((of_regval x14_ref) v) else
+ if reg_name = (''x13'') then map_option (\<lambda> v . (write_to x13_ref) v s) ((of_regval x13_ref) v) else
+ if reg_name = (''x12'') then map_option (\<lambda> v . (write_to x12_ref) v s) ((of_regval x12_ref) v) else
+ if reg_name = (''x11'') then map_option (\<lambda> v . (write_to x11_ref) v s) ((of_regval x11_ref) v) else
+ if reg_name = (''x10'') then map_option (\<lambda> v . (write_to x10_ref) v s) ((of_regval x10_ref) v) else
+ if reg_name = (''x9'') then map_option (\<lambda> v . (write_to x9_ref) v s) ((of_regval x9_ref) v) else
+ if reg_name = (''x8'') then map_option (\<lambda> v . (write_to x8_ref) v s) ((of_regval x8_ref) v) else
+ if reg_name = (''x7'') then map_option (\<lambda> v . (write_to x7_ref) v s) ((of_regval x7_ref) v) else
+ if reg_name = (''x6'') then map_option (\<lambda> v . (write_to x6_ref) v s) ((of_regval x6_ref) v) else
+ if reg_name = (''x5'') then map_option (\<lambda> v . (write_to x5_ref) v s) ((of_regval x5_ref) v) else
+ if reg_name = (''x4'') then map_option (\<lambda> v . (write_to x4_ref) v s) ((of_regval x4_ref) v) else
+ if reg_name = (''x3'') then map_option (\<lambda> v . (write_to x3_ref) v s) ((of_regval x3_ref) v) else
+ if reg_name = (''x2'') then map_option (\<lambda> v . (write_to x2_ref) v s) ((of_regval x2_ref) v) else
+ if reg_name = (''x1'') then map_option (\<lambda> v . (write_to x1_ref) v s) ((of_regval x1_ref) v) else
+ if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else
+ if reg_name = (''instbits'') then map_option (\<lambda> v . (write_to instbits_ref) v s) ((of_regval instbits_ref) v) else
+ if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else
+ if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else
+ None )"
+ for reg_name :: " string "
+ and v :: " register_value "
+ and s :: " regstate "
+
+
+definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where
+ " register_accessors = ( (get_regval, set_regval))"
+
+
+
+type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR "
+type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad "
+end
diff --git a/prover_snapshots/isabelle/RV64/ROOT b/prover_snapshots/isabelle/RV64/ROOT
new file mode 100644
index 0000000..4e3b8bf
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/ROOT
@@ -0,0 +1,4 @@
+session "Sail-RV64" = "Sail" +
+ options [document = false]
+ theories
+ "Riscv_lemmas"
diff --git a/prover_snapshots/isabelle/RV64/Riscv.thy b/prover_snapshots/isabelle/RV64/Riscv.thy
new file mode 100644
index 0000000..f1d11fe
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/Riscv.thy
@@ -0,0 +1,37028 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV64/riscv.lem\<close>.\<close>
+
+theory "Riscv"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+ "Riscv_types"
+ "Riscv_extras"
+
+begin
+
+\<comment> \<open>\<open>Generated by Sail from riscv.\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_string\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+\<comment> \<open>\<open>open import Riscv_types\<close>\<close>
+\<comment> \<open>\<open>open import Riscv_extras\<close>\<close>
+
+\<comment> \<open>\<open>val is_none : forall 'a. maybe 'a -> bool\<close>\<close>
+
+fun is_none :: " 'a option \<Rightarrow> bool " where
+ " is_none (Some (_)) = ( False )"
+|" is_none None = ( True )"
+
+
+\<comment> \<open>\<open>val is_some : forall 'a. maybe 'a -> bool\<close>\<close>
+
+fun is_some :: " 'a option \<Rightarrow> bool " where
+ " is_some (Some (_)) = ( True )"
+|" is_some None = ( False )"
+
+
+\<comment> \<open>\<open>val eq_unit : unit -> unit -> bool\<close>\<close>
+
+definition eq_unit :: " unit \<Rightarrow> unit \<Rightarrow> bool " where
+ " eq_unit _ _ = ( True )"
+
+
+
+
+\<comment> \<open>\<open>val neq_bool : bool -> bool -> bool\<close>\<close>
+
+definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where
+ " neq_bool x y = ( \<not> (((x = y))))"
+ for x :: " bool "
+ and y :: " bool "
+
+
+\<comment> \<open>\<open>val __id : integer -> integer\<close>\<close>
+
+definition id0 :: " int \<Rightarrow> int " where
+ " id0 x = ( x )"
+ for x :: " int "
+
+
+\<comment> \<open>\<open>val concat_str_bits : forall 'n. Size 'n => string -> mword 'n -> string\<close>\<close>
+
+definition concat_str_bits :: " string \<Rightarrow>('n::len)Word.word \<Rightarrow> string " where
+ " concat_str_bits str x = ( (@) str ((string_of_bits x)))"
+ for str :: " string "
+ and x :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val concat_str_dec : string -> ii -> string\<close>\<close>
+
+definition concat_str_dec :: " string \<Rightarrow> int \<Rightarrow> string " where
+ " concat_str_dec str x = ( (@) str ((dec_str x)))"
+ for str :: " string "
+ and x :: " int "
+
+
+
+
+\<comment> \<open>\<open>val sail_mask : forall 'len 'v. Size 'len, Size 'v => integer -> mword 'v -> mword 'len\<close>\<close>
+
+definition sail_mask :: " int \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word " where
+ " sail_mask len v = (
+ if ((len \<le> ((int (size v))))) then (vector_truncate v len :: ( 'len::len)Word.word)
+ else (zero_extend v len :: ( 'len::len)Word.word))"
+ for len :: " int "
+ and v :: "('v::len)Word.word "
+
+
+\<comment> \<open>\<open>val sail_ones : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition sail_ones :: " int \<Rightarrow>('n::len)Word.word " where
+ " sail_ones n = ( (not_vec ((zeros n :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val slice_mask : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n\<close>\<close>
+
+definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where
+ " slice_mask n i l = (
+ if ((l \<ge> n)) then (shiftl ((sail_ones n :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)
+ else
+ (let one = ((sail_mask n (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in
+ (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))"
+ for n :: " int "
+ and i :: " int "
+ and l :: " int "
+
+
+\<comment> \<open>\<open>val read_kind_of_num : integer -> read_kind\<close>\<close>
+
+definition read_kind_of_num :: " int \<Rightarrow> read_kind " where
+ " read_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Read_plain
+ else if (((p00 = (( 1 :: int)::ii)))) then Read_reserve
+ else if (((p00 = (( 2 :: int)::ii)))) then Read_acquire
+ else if (((p00 = (( 3 :: int)::ii)))) then Read_exclusive
+ else if (((p00 = (( 4 :: int)::ii)))) then Read_exclusive_acquire
+ else if (((p00 = (( 5 :: int)::ii)))) then Read_stream
+ else if (((p00 = (( 6 :: int)::ii)))) then Read_RISCV_acquire
+ else if (((p00 = (( 7 :: int)::ii)))) then Read_RISCV_strong_acquire
+ else if (((p00 = (( 8 :: int)::ii)))) then Read_RISCV_reserved
+ else if (((p00 = (( 9 :: int)::ii)))) then Read_RISCV_reserved_acquire
+ else if (((p00 = (( 10 :: int)::ii)))) then Read_RISCV_reserved_strong_acquire
+ else Read_X86_locked))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_read_kind : read_kind -> integer\<close>\<close>
+
+fun num_of_read_kind :: " read_kind \<Rightarrow> int " where
+ " num_of_read_kind Read_plain = ( (( 0 :: int)::ii))"
+|" num_of_read_kind Read_reserve = ( (( 1 :: int)::ii))"
+|" num_of_read_kind Read_acquire = ( (( 2 :: int)::ii))"
+|" num_of_read_kind Read_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_read_kind Read_exclusive_acquire = ( (( 4 :: int)::ii))"
+|" num_of_read_kind Read_stream = ( (( 5 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_acquire = ( (( 6 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_strong_acquire = ( (( 7 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved = ( (( 8 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_acquire = ( (( 9 :: int)::ii))"
+|" num_of_read_kind Read_RISCV_reserved_strong_acquire = ( (( 10 :: int)::ii))"
+|" num_of_read_kind Read_X86_locked = ( (( 11 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val write_kind_of_num : integer -> write_kind\<close>\<close>
+
+definition write_kind_of_num :: " int \<Rightarrow> write_kind " where
+ " write_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Write_plain
+ else if (((p00 = (( 1 :: int)::ii)))) then Write_conditional
+ else if (((p00 = (( 2 :: int)::ii)))) then Write_release
+ else if (((p00 = (( 3 :: int)::ii)))) then Write_exclusive
+ else if (((p00 = (( 4 :: int)::ii)))) then Write_exclusive_release
+ else if (((p00 = (( 5 :: int)::ii)))) then Write_RISCV_release
+ else if (((p00 = (( 6 :: int)::ii)))) then Write_RISCV_strong_release
+ else if (((p00 = (( 7 :: int)::ii)))) then Write_RISCV_conditional
+ else if (((p00 = (( 8 :: int)::ii)))) then Write_RISCV_conditional_release
+ else if (((p00 = (( 9 :: int)::ii)))) then Write_RISCV_conditional_strong_release
+ else Write_X86_locked))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_write_kind : write_kind -> integer\<close>\<close>
+
+fun num_of_write_kind :: " write_kind \<Rightarrow> int " where
+ " num_of_write_kind Write_plain = ( (( 0 :: int)::ii))"
+|" num_of_write_kind Write_conditional = ( (( 1 :: int)::ii))"
+|" num_of_write_kind Write_release = ( (( 2 :: int)::ii))"
+|" num_of_write_kind Write_exclusive = ( (( 3 :: int)::ii))"
+|" num_of_write_kind Write_exclusive_release = ( (( 4 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_release = ( (( 5 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_strong_release = ( (( 6 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional = ( (( 7 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_release = ( (( 8 :: int)::ii))"
+|" num_of_write_kind Write_RISCV_conditional_strong_release = ( (( 9 :: int)::ii))"
+|" num_of_write_kind Write_X86_locked = ( (( 10 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val barrier_kind_of_num : integer -> barrier_kind\<close>\<close>
+
+definition barrier_kind_of_num :: " int \<Rightarrow> barrier_kind " where
+ " barrier_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Barrier_Sync
+ else if (((p00 = (( 1 :: int)::ii)))) then Barrier_LwSync
+ else if (((p00 = (( 2 :: int)::ii)))) then Barrier_Eieio
+ else if (((p00 = (( 3 :: int)::ii)))) then Barrier_Isync
+ else if (((p00 = (( 4 :: int)::ii)))) then Barrier_DMB
+ else if (((p00 = (( 5 :: int)::ii)))) then Barrier_DMB_ST
+ else if (((p00 = (( 6 :: int)::ii)))) then Barrier_DMB_LD
+ else if (((p00 = (( 7 :: int)::ii)))) then Barrier_DSB
+ else if (((p00 = (( 8 :: int)::ii)))) then Barrier_DSB_ST
+ else if (((p00 = (( 9 :: int)::ii)))) then Barrier_DSB_LD
+ else if (((p00 = (( 10 :: int)::ii)))) then Barrier_ISB
+ else if (((p00 = (( 11 :: int)::ii)))) then Barrier_MIPS_SYNC
+ else if (((p00 = (( 12 :: int)::ii)))) then Barrier_RISCV_rw_rw
+ else if (((p00 = (( 13 :: int)::ii)))) then Barrier_RISCV_r_rw
+ else if (((p00 = (( 14 :: int)::ii)))) then Barrier_RISCV_r_r
+ else if (((p00 = (( 15 :: int)::ii)))) then Barrier_RISCV_rw_w
+ else if (((p00 = (( 16 :: int)::ii)))) then Barrier_RISCV_w_w
+ else if (((p00 = (( 17 :: int)::ii)))) then Barrier_RISCV_w_rw
+ else if (((p00 = (( 18 :: int)::ii)))) then Barrier_RISCV_rw_r
+ else if (((p00 = (( 19 :: int)::ii)))) then Barrier_RISCV_r_w
+ else if (((p00 = (( 20 :: int)::ii)))) then Barrier_RISCV_w_r
+ else if (((p00 = (( 21 :: int)::ii)))) then Barrier_RISCV_tso
+ else if (((p00 = (( 22 :: int)::ii)))) then Barrier_RISCV_i
+ else Barrier_x86_MFENCE))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_barrier_kind : barrier_kind -> integer\<close>\<close>
+
+fun num_of_barrier_kind :: " barrier_kind \<Rightarrow> int " where
+ " num_of_barrier_kind Barrier_Sync = ( (( 0 :: int)::ii))"
+|" num_of_barrier_kind Barrier_LwSync = ( (( 1 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Eieio = ( (( 2 :: int)::ii))"
+|" num_of_barrier_kind Barrier_Isync = ( (( 3 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB = ( (( 4 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_ST = ( (( 5 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DMB_LD = ( (( 6 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB = ( (( 7 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_ST = ( (( 8 :: int)::ii))"
+|" num_of_barrier_kind Barrier_DSB_LD = ( (( 9 :: int)::ii))"
+|" num_of_barrier_kind Barrier_ISB = ( (( 10 :: int)::ii))"
+|" num_of_barrier_kind Barrier_MIPS_SYNC = ( (( 11 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_rw = ( (( 12 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_rw = ( (( 13 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_r = ( (( 14 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_w = ( (( 15 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_w = ( (( 16 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_rw = ( (( 17 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_rw_r = ( (( 18 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_r_w = ( (( 19 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_w_r = ( (( 20 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_tso = ( (( 21 :: int)::ii))"
+|" num_of_barrier_kind Barrier_RISCV_i = ( (( 22 :: int)::ii))"
+|" num_of_barrier_kind Barrier_x86_MFENCE = ( (( 23 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val trans_kind_of_num : integer -> trans_kind\<close>\<close>
+
+definition trans_kind_of_num :: " int \<Rightarrow> trans_kind " where
+ " trans_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Transaction_start
+ else if (((p00 = (( 1 :: int)::ii)))) then Transaction_commit
+ else Transaction_abort))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_trans_kind : trans_kind -> integer\<close>\<close>
+
+fun num_of_trans_kind :: " trans_kind \<Rightarrow> int " where
+ " num_of_trans_kind Transaction_start = ( (( 0 :: int)::ii))"
+|" num_of_trans_kind Transaction_commit = ( (( 1 :: int)::ii))"
+|" num_of_trans_kind Transaction_abort = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val cache_op_kind_of_num : integer -> cache_op_kind\<close>\<close>
+
+definition cache_op_kind_of_num :: " int \<Rightarrow> cache_op_kind " where
+ " cache_op_kind_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Cache_op_D_IVAC
+ else if (((p00 = (( 1 :: int)::ii)))) then Cache_op_D_ISW
+ else if (((p00 = (( 2 :: int)::ii)))) then Cache_op_D_CSW
+ else if (((p00 = (( 3 :: int)::ii)))) then Cache_op_D_CISW
+ else if (((p00 = (( 4 :: int)::ii)))) then Cache_op_D_ZVA
+ else if (((p00 = (( 5 :: int)::ii)))) then Cache_op_D_CVAC
+ else if (((p00 = (( 6 :: int)::ii)))) then Cache_op_D_CVAU
+ else if (((p00 = (( 7 :: int)::ii)))) then Cache_op_D_CIVAC
+ else if (((p00 = (( 8 :: int)::ii)))) then Cache_op_I_IALLUIS
+ else if (((p00 = (( 9 :: int)::ii)))) then Cache_op_I_IALLU
+ else Cache_op_I_IVAU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_cache_op_kind : cache_op_kind -> integer\<close>\<close>
+
+fun num_of_cache_op_kind :: " cache_op_kind \<Rightarrow> int " where
+ " num_of_cache_op_kind Cache_op_D_IVAC = ( (( 0 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_ISW = ( (( 1 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CSW = ( (( 2 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CISW = ( (( 3 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_ZVA = ( (( 4 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CVAC = ( (( 5 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CVAU = ( (( 6 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_D_CIVAC = ( (( 7 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IALLUIS = ( (( 8 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IALLU = ( (( 9 :: int)::ii))"
+|" num_of_cache_op_kind Cache_op_I_IVAU = ( (( 10 :: int)::ii))"
+
+
+
+
+
+
+\<comment> \<open>\<open>val cast_unit_vec : bitU -> mword ty1\<close>\<close>
+
+fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where
+ " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))"
+|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val get_config_print_instr : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_reg : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_mem : unit -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val get_config_print_platform : unit -> bool\<close>\<close>
+
+definition get_config_print_instr :: " unit \<Rightarrow> bool " where
+ " get_config_print_instr _ = ( False )"
+
+
+definition get_config_print_reg :: " unit \<Rightarrow> bool " where
+ " get_config_print_reg _ = ( False )"
+
+
+definition get_config_print_mem :: " unit \<Rightarrow> bool " where
+ " get_config_print_mem _ = ( False )"
+
+
+definition get_config_print_platform :: " unit \<Rightarrow> bool " where
+ " get_config_print_platform _ = ( False )"
+
+
+\<comment> \<open>\<open>val EXTS : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm\<close>\<close>
+
+\<comment> \<open>\<open>val EXTZ : forall 'm 'n. Size 'm, Size 'n => integer -> mword 'n -> mword 'm\<close>\<close>
+
+definition EXTS :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
+ " EXTS m v = ( (sign_extend v m :: ( 'm::len)Word.word))"
+ for m :: " int "
+ and v :: "('n::len)Word.word "
+
+
+definition EXTZ :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where
+ " EXTZ m v = ( (zero_extend v m :: ( 'm::len)Word.word))"
+ for m :: " int "
+ and v :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val zeros_implicit : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition zeros_implicit :: " int \<Rightarrow>('n::len)Word.word " where
+ " zeros_implicit n = ( (zeros n :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val ones : forall 'n. Size 'n => integer -> mword 'n\<close>\<close>
+
+definition ones :: " int \<Rightarrow>('n::len)Word.word " where
+ " ones n = ( (sail_ones n :: ( 'n::len)Word.word))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val bool_to_bits : bool -> mword ty1\<close>\<close>
+
+definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))"
+ for x :: " bool "
+
+
+\<comment> \<open>\<open>val bit_to_bool : bitU -> bool\<close>\<close>
+
+fun bit_to_bool :: " bitU \<Rightarrow> bool " where
+ " bit_to_bool B1 = ( True )"
+|" bit_to_bool B0 = ( False )"
+
+
+\<comment> \<open>\<open>val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l\<close>\<close>
+
+definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where
+ " to_bits l n = ( (get_slice_int l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))"
+ for l :: " int "
+ and n :: " int "
+
+
+\<comment> \<open>\<open>val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool\<close>\<close>
+
+definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+definition zopz0zIzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where
+ " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))"
+ for x :: "('n::len)Word.word "
+ and y :: "('n::len)Word.word "
+
+
+\<comment> \<open>\<open>val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64\<close>\<close>
+
+definition shift_right_arith64 :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word " where
+ " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = (
+ (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in
+ (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))"
+ for v :: "(64)Word.word "
+ and shift :: "(6)Word.word "
+
+
+\<comment> \<open>\<open>val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32\<close>\<close>
+
+definition shift_right_arith32 :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word " where
+ " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = (
+ (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in
+ (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))"
+ for v :: "(32)Word.word "
+ and shift :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val n_leading_spaces : string -> ii\<close>\<close>
+
+function (sequential,domintros) n_leading_spaces0 :: " string \<Rightarrow> int " where
+ " n_leading_spaces0 s = (
+ (let p00 = s in
+ if (((p00 = ('''')))) then (( 0 :: int)::ii)
+ else
+ (let p00 = (string_take s (( 1 :: int)::ii)) in
+ if (((p00 = ('' '')))) then (( 1 :: int)::ii) + ((n_leading_spaces0 ((string_drop s (( 1 :: int)::ii)))))
+ else (( 0 :: int)::ii))))"
+ for s :: " string "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val spc_forwards : unit -> string\<close>\<close>
+
+definition spc_forwards :: " unit \<Rightarrow> string " where
+ " spc_forwards _ = ( ('' ''))"
+
+
+\<comment> \<open>\<open>val spc_backwards : string -> unit\<close>\<close>
+
+definition spc_backwards :: " string \<Rightarrow> unit " where
+ " spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition spc_matches_prefix0 :: " string \<Rightarrow>(unit*int)option " where
+ " spc_matches_prefix0 s = (
+ (let n = (n_leading_spaces0 s) in
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then None
+ else Some (() , n))))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val opt_spc_forwards : unit -> string\<close>\<close>
+
+definition opt_spc_forwards :: " unit \<Rightarrow> string " where
+ " opt_spc_forwards _ = ( (''''))"
+
+
+\<comment> \<open>\<open>val opt_spc_backwards : string -> unit\<close>\<close>
+
+definition opt_spc_backwards :: " string \<Rightarrow> unit " where
+ " opt_spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val opt_spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition opt_spc_matches_prefix0 :: " string \<Rightarrow>(unit*int)option " where
+ " opt_spc_matches_prefix0 s = ( Some (() , n_leading_spaces0 s))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val def_spc_forwards : unit -> string\<close>\<close>
+
+definition def_spc_forwards :: " unit \<Rightarrow> string " where
+ " def_spc_forwards _ = ( ('' ''))"
+
+
+\<comment> \<open>\<open>val def_spc_backwards : string -> unit\<close>\<close>
+
+definition def_spc_backwards :: " string \<Rightarrow> unit " where
+ " def_spc_backwards s = ( () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val def_spc_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+definition def_spc_matches_prefix :: " string \<Rightarrow>(unit*ii)option " where
+ " def_spc_matches_prefix s = ( opt_spc_matches_prefix0 s )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_1_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition hex_bits_1_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " hex_bits_1_forwards_matches bv = ( True )"
+ for bv :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_1_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_1_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_1_backwards_matches s = (
+ if ((case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 1 Word.word * ii))option)) of
+ Some ((g__51, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_1_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition hex_bits_1_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " hex_bits_1_backwards s = (
+ (case ((hex_bits_1_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 1 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 49:2 - 51:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_2_forwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition hex_bits_2_forwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " hex_bits_2_forwards_matches bv = ( True )"
+ for bv :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_2_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_2_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_2_backwards_matches s = (
+ if ((case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 2 Word.word * ii))option)) of
+ Some ((g__50, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_2_backwards : string -> M (mword ty2)\<close>\<close>
+
+definition hex_bits_2_backwards :: " string \<Rightarrow>((register_value),((2)Word.word),(exception))monad " where
+ " hex_bits_2_backwards s = (
+ (case ((hex_bits_2_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 2 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 68:2 - 70:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_3_forwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition hex_bits_3_forwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " hex_bits_3_forwards_matches bv = ( True )"
+ for bv :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_3_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_3_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_3_backwards_matches s = (
+ if ((case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 3 Word.word * ii))option)) of
+ Some ((g__49, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_3_backwards : string -> M (mword ty3)\<close>\<close>
+
+definition hex_bits_3_backwards :: " string \<Rightarrow>((register_value),((3)Word.word),(exception))monad " where
+ " hex_bits_3_backwards s = (
+ (case ((hex_bits_3_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 3 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 87:2 - 89:3'') \<then> exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_4_forwards_matches : mword ty4 -> bool\<close>\<close>
+
+definition hex_bits_4_forwards_matches :: "(4)Word.word \<Rightarrow> bool " where
+ " hex_bits_4_forwards_matches bv = ( True )"
+ for bv :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_4_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_4_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_4_backwards_matches s = (
+ if ((case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 4 Word.word * ii))option)) of
+ Some ((g__48, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_4_backwards : string -> M (mword ty4)\<close>\<close>
+
+definition hex_bits_4_backwards :: " string \<Rightarrow>((register_value),((4)Word.word),(exception))monad " where
+ " hex_bits_4_backwards s = (
+ (case ((hex_bits_4_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 4 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 106:2 - 108:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_5_forwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition hex_bits_5_forwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " hex_bits_5_forwards_matches bv = ( True )"
+ for bv :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_5_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_5_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_5_backwards_matches s = (
+ if ((case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 5 Word.word * ii))option)) of
+ Some ((g__47, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_5_backwards : string -> M (mword ty5)\<close>\<close>
+
+definition hex_bits_5_backwards :: " string \<Rightarrow>((register_value),((5)Word.word),(exception))monad " where
+ " hex_bits_5_backwards s = (
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 5 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 125:2 - 127:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_6_forwards_matches : mword ty6 -> bool\<close>\<close>
+
+definition hex_bits_6_forwards_matches :: "(6)Word.word \<Rightarrow> bool " where
+ " hex_bits_6_forwards_matches bv = ( True )"
+ for bv :: "(6)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_6_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_6_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_6_backwards_matches s = (
+ if ((case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 6 Word.word * ii))option)) of
+ Some ((g__46, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_6_backwards : string -> M (mword ty6)\<close>\<close>
+
+definition hex_bits_6_backwards :: " string \<Rightarrow>((register_value),((6)Word.word),(exception))monad " where
+ " hex_bits_6_backwards s = (
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 6 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 144:2 - 146:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_7_forwards_matches : mword ty7 -> bool\<close>\<close>
+
+definition hex_bits_7_forwards_matches :: "(7)Word.word \<Rightarrow> bool " where
+ " hex_bits_7_forwards_matches bv = ( True )"
+ for bv :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_7_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_7_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_7_backwards_matches s = (
+ if ((case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 7 Word.word * ii))option)) of
+ Some ((g__45, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_7_backwards : string -> M (mword ty7)\<close>\<close>
+
+definition hex_bits_7_backwards :: " string \<Rightarrow>((register_value),((7)Word.word),(exception))monad " where
+ " hex_bits_7_backwards s = (
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 7 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 163:2 - 165:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_8_forwards_matches : mword ty8 -> bool\<close>\<close>
+
+definition hex_bits_8_forwards_matches :: "(8)Word.word \<Rightarrow> bool " where
+ " hex_bits_8_forwards_matches bv = ( True )"
+ for bv :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_8_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_8_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_8_backwards_matches s = (
+ if ((case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 8 Word.word * ii))option)) of
+ Some ((g__44, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_8_backwards : string -> M (mword ty8)\<close>\<close>
+
+definition hex_bits_8_backwards :: " string \<Rightarrow>((register_value),((8)Word.word),(exception))monad " where
+ " hex_bits_8_backwards s = (
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 8 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 182:2 - 184:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_9_forwards_matches : mword ty9 -> bool\<close>\<close>
+
+definition hex_bits_9_forwards_matches :: "(9)Word.word \<Rightarrow> bool " where
+ " hex_bits_9_forwards_matches bv = ( True )"
+ for bv :: "(9)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_9_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_9_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_9_backwards_matches s = (
+ if ((case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 9 Word.word * ii))option)) of
+ Some ((g__43, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_9_backwards : string -> M (mword ty9)\<close>\<close>
+
+definition hex_bits_9_backwards :: " string \<Rightarrow>((register_value),((9)Word.word),(exception))monad " where
+ " hex_bits_9_backwards s = (
+ (case ((hex_bits_9_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 9 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 201:2 - 203:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_10_forwards_matches : mword ty10 -> bool\<close>\<close>
+
+definition hex_bits_10_forwards_matches :: "(10)Word.word \<Rightarrow> bool " where
+ " hex_bits_10_forwards_matches bv = ( True )"
+ for bv :: "(10)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_10_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_10_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_10_backwards_matches s = (
+ if ((case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 10 Word.word * ii))option)) of
+ Some ((g__42, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_10_backwards : string -> M (mword ty10)\<close>\<close>
+
+definition hex_bits_10_backwards :: " string \<Rightarrow>((register_value),((10)Word.word),(exception))monad " where
+ " hex_bits_10_backwards s = (
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 10 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 220:2 - 222:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_11_forwards_matches : mword ty11 -> bool\<close>\<close>
+
+definition hex_bits_11_forwards_matches :: "(11)Word.word \<Rightarrow> bool " where
+ " hex_bits_11_forwards_matches bv = ( True )"
+ for bv :: "(11)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_11_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_11_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_11_backwards_matches s = (
+ if ((case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 11 Word.word * ii))option)) of
+ Some ((g__41, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_11_backwards : string -> M (mword ty11)\<close>\<close>
+
+definition hex_bits_11_backwards :: " string \<Rightarrow>((register_value),((11)Word.word),(exception))monad " where
+ " hex_bits_11_backwards s = (
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 11 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 239:2 - 241:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_12_forwards_matches : mword ty12 -> bool\<close>\<close>
+
+definition hex_bits_12_forwards_matches :: "(12)Word.word \<Rightarrow> bool " where
+ " hex_bits_12_forwards_matches bv = ( True )"
+ for bv :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_12_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_12_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_12_backwards_matches s = (
+ if ((case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 12 Word.word * ii))option)) of
+ Some ((g__40, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_12_backwards : string -> M (mword ty12)\<close>\<close>
+
+definition hex_bits_12_backwards :: " string \<Rightarrow>((register_value),((12)Word.word),(exception))monad " where
+ " hex_bits_12_backwards s = (
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 12 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 258:2 - 260:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_13_forwards_matches : mword ty13 -> bool\<close>\<close>
+
+definition hex_bits_13_forwards_matches :: "(13)Word.word \<Rightarrow> bool " where
+ " hex_bits_13_forwards_matches bv = ( True )"
+ for bv :: "(13)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_13_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_13_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_13_backwards_matches s = (
+ if ((case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 13 Word.word * ii))option)) of
+ Some ((g__39, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_13_backwards : string -> M (mword ty13)\<close>\<close>
+
+definition hex_bits_13_backwards :: " string \<Rightarrow>((register_value),((13)Word.word),(exception))monad " where
+ " hex_bits_13_backwards s = (
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 13 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 277:2 - 279:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_14_forwards_matches : mword ty14 -> bool\<close>\<close>
+
+definition hex_bits_14_forwards_matches :: "(14)Word.word \<Rightarrow> bool " where
+ " hex_bits_14_forwards_matches bv = ( True )"
+ for bv :: "(14)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_14_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_14_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_14_backwards_matches s = (
+ if ((case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 14 Word.word * ii))option)) of
+ Some ((g__38, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_14_backwards : string -> M (mword ty14)\<close>\<close>
+
+definition hex_bits_14_backwards :: " string \<Rightarrow>((register_value),((14)Word.word),(exception))monad " where
+ " hex_bits_14_backwards s = (
+ (case ((hex_bits_14_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 14 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 296:2 - 298:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_15_forwards_matches : mword ty15 -> bool\<close>\<close>
+
+definition hex_bits_15_forwards_matches :: "(15)Word.word \<Rightarrow> bool " where
+ " hex_bits_15_forwards_matches bv = ( True )"
+ for bv :: "(15)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_15_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_15_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_15_backwards_matches s = (
+ if ((case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 15 Word.word * ii))option)) of
+ Some ((g__37, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_15_backwards : string -> M (mword ty15)\<close>\<close>
+
+definition hex_bits_15_backwards :: " string \<Rightarrow>((register_value),((15)Word.word),(exception))monad " where
+ " hex_bits_15_backwards s = (
+ (case ((hex_bits_15_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 15 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 315:2 - 317:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_16_forwards_matches : mword ty16 -> bool\<close>\<close>
+
+definition hex_bits_16_forwards_matches :: "(16)Word.word \<Rightarrow> bool " where
+ " hex_bits_16_forwards_matches bv = ( True )"
+ for bv :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_16_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_16_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_16_backwards_matches s = (
+ if ((case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 16 Word.word * ii))option)) of
+ Some ((g__36, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_16_backwards : string -> M (mword ty16)\<close>\<close>
+
+definition hex_bits_16_backwards :: " string \<Rightarrow>((register_value),((16)Word.word),(exception))monad " where
+ " hex_bits_16_backwards s = (
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 16 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 334:2 - 336:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_17_forwards_matches : mword ty17 -> bool\<close>\<close>
+
+definition hex_bits_17_forwards_matches :: "(17)Word.word \<Rightarrow> bool " where
+ " hex_bits_17_forwards_matches bv = ( True )"
+ for bv :: "(17)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_17_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_17_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_17_backwards_matches s = (
+ if ((case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 17 Word.word * ii))option)) of
+ Some ((g__35, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_17_backwards : string -> M (mword ty17)\<close>\<close>
+
+definition hex_bits_17_backwards :: " string \<Rightarrow>((register_value),((17)Word.word),(exception))monad " where
+ " hex_bits_17_backwards s = (
+ (case ((hex_bits_17_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 17 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 353:2 - 355:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_18_forwards_matches : mword ty18 -> bool\<close>\<close>
+
+definition hex_bits_18_forwards_matches :: "(18)Word.word \<Rightarrow> bool " where
+ " hex_bits_18_forwards_matches bv = ( True )"
+ for bv :: "(18)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_18_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_18_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_18_backwards_matches s = (
+ if ((case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 18 Word.word * ii))option)) of
+ Some ((g__34, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_18_backwards : string -> M (mword ty18)\<close>\<close>
+
+definition hex_bits_18_backwards :: " string \<Rightarrow>((register_value),((18)Word.word),(exception))monad " where
+ " hex_bits_18_backwards s = (
+ (case ((hex_bits_18_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 18 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 372:2 - 374:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_19_forwards_matches : mword ty19 -> bool\<close>\<close>
+
+definition hex_bits_19_forwards_matches :: "(19)Word.word \<Rightarrow> bool " where
+ " hex_bits_19_forwards_matches bv = ( True )"
+ for bv :: "(19)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_19_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_19_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_19_backwards_matches s = (
+ if ((case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 19 Word.word * ii))option)) of
+ Some ((g__33, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_19_backwards : string -> M (mword ty19)\<close>\<close>
+
+definition hex_bits_19_backwards :: " string \<Rightarrow>((register_value),((19)Word.word),(exception))monad " where
+ " hex_bits_19_backwards s = (
+ (case ((hex_bits_19_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 19 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 391:2 - 393:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_20_forwards_matches : mword ty20 -> bool\<close>\<close>
+
+definition hex_bits_20_forwards_matches :: "(20)Word.word \<Rightarrow> bool " where
+ " hex_bits_20_forwards_matches bv = ( True )"
+ for bv :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_20_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_20_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_20_backwards_matches s = (
+ if ((case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 20 Word.word * ii))option)) of
+ Some ((g__32, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_20_backwards : string -> M (mword ty20)\<close>\<close>
+
+definition hex_bits_20_backwards :: " string \<Rightarrow>((register_value),((20)Word.word),(exception))monad " where
+ " hex_bits_20_backwards s = (
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 20 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 410:2 - 412:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_21_forwards_matches : mword ty21 -> bool\<close>\<close>
+
+definition hex_bits_21_forwards_matches :: "(21)Word.word \<Rightarrow> bool " where
+ " hex_bits_21_forwards_matches bv = ( True )"
+ for bv :: "(21)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_21_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_21_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_21_backwards_matches s = (
+ if ((case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 21 Word.word * ii))option)) of
+ Some ((g__31, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_21_backwards : string -> M (mword ty21)\<close>\<close>
+
+definition hex_bits_21_backwards :: " string \<Rightarrow>((register_value),((21)Word.word),(exception))monad " where
+ " hex_bits_21_backwards s = (
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 21 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 429:2 - 431:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_22_forwards_matches : mword ty22 -> bool\<close>\<close>
+
+definition hex_bits_22_forwards_matches :: "(22)Word.word \<Rightarrow> bool " where
+ " hex_bits_22_forwards_matches bv = ( True )"
+ for bv :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_22_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_22_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_22_backwards_matches s = (
+ if ((case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 22 Word.word * ii))option)) of
+ Some ((g__30, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_22_backwards : string -> M (mword ty22)\<close>\<close>
+
+definition hex_bits_22_backwards :: " string \<Rightarrow>((register_value),((22)Word.word),(exception))monad " where
+ " hex_bits_22_backwards s = (
+ (case ((hex_bits_22_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 22 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 448:2 - 450:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_23_forwards_matches : mword ty23 -> bool\<close>\<close>
+
+definition hex_bits_23_forwards_matches :: "(23)Word.word \<Rightarrow> bool " where
+ " hex_bits_23_forwards_matches bv = ( True )"
+ for bv :: "(23)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_23_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_23_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_23_backwards_matches s = (
+ if ((case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 23 Word.word * ii))option)) of
+ Some ((g__29, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_23_backwards : string -> M (mword ty23)\<close>\<close>
+
+definition hex_bits_23_backwards :: " string \<Rightarrow>((register_value),((23)Word.word),(exception))monad " where
+ " hex_bits_23_backwards s = (
+ (case ((hex_bits_23_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 23 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 467:2 - 469:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_24_forwards_matches : mword ty24 -> bool\<close>\<close>
+
+definition hex_bits_24_forwards_matches :: "(24)Word.word \<Rightarrow> bool " where
+ " hex_bits_24_forwards_matches bv = ( True )"
+ for bv :: "(24)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_24_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_24_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_24_backwards_matches s = (
+ if ((case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 24 Word.word * ii))option)) of
+ Some ((g__28, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_24_backwards : string -> M (mword ty24)\<close>\<close>
+
+definition hex_bits_24_backwards :: " string \<Rightarrow>((register_value),((24)Word.word),(exception))monad " where
+ " hex_bits_24_backwards s = (
+ (case ((hex_bits_24_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 24 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 486:2 - 488:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_25_forwards_matches : mword ty25 -> bool\<close>\<close>
+
+definition hex_bits_25_forwards_matches :: "(25)Word.word \<Rightarrow> bool " where
+ " hex_bits_25_forwards_matches bv = ( True )"
+ for bv :: "(25)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_25_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_25_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_25_backwards_matches s = (
+ if ((case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 25 Word.word * ii))option)) of
+ Some ((g__27, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_25_backwards : string -> M (mword ty25)\<close>\<close>
+
+definition hex_bits_25_backwards :: " string \<Rightarrow>((register_value),((25)Word.word),(exception))monad " where
+ " hex_bits_25_backwards s = (
+ (case ((hex_bits_25_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 25 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 505:2 - 507:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_26_forwards_matches : mword ty26 -> bool\<close>\<close>
+
+definition hex_bits_26_forwards_matches :: "(26)Word.word \<Rightarrow> bool " where
+ " hex_bits_26_forwards_matches bv = ( True )"
+ for bv :: "(26)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_26_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_26_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_26_backwards_matches s = (
+ if ((case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 26 Word.word * ii))option)) of
+ Some ((g__26, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_26_backwards : string -> M (mword ty26)\<close>\<close>
+
+definition hex_bits_26_backwards :: " string \<Rightarrow>((register_value),((26)Word.word),(exception))monad " where
+ " hex_bits_26_backwards s = (
+ (case ((hex_bits_26_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 26 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 524:2 - 526:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_27_forwards_matches : mword ty27 -> bool\<close>\<close>
+
+definition hex_bits_27_forwards_matches :: "(27)Word.word \<Rightarrow> bool " where
+ " hex_bits_27_forwards_matches bv = ( True )"
+ for bv :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_27_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_27_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_27_backwards_matches s = (
+ if ((case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 27 Word.word * ii))option)) of
+ Some ((g__25, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_27_backwards : string -> M (mword ty27)\<close>\<close>
+
+definition hex_bits_27_backwards :: " string \<Rightarrow>((register_value),((27)Word.word),(exception))monad " where
+ " hex_bits_27_backwards s = (
+ (case ((hex_bits_27_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 27 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 543:2 - 545:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_28_forwards_matches : mword ty28 -> bool\<close>\<close>
+
+definition hex_bits_28_forwards_matches :: "(28)Word.word \<Rightarrow> bool " where
+ " hex_bits_28_forwards_matches bv = ( True )"
+ for bv :: "(28)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_28_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_28_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_28_backwards_matches s = (
+ if ((case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 28 Word.word * ii))option)) of
+ Some ((g__24, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_28_backwards : string -> M (mword ty28)\<close>\<close>
+
+definition hex_bits_28_backwards :: " string \<Rightarrow>((register_value),((28)Word.word),(exception))monad " where
+ " hex_bits_28_backwards s = (
+ (case ((hex_bits_28_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 28 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 562:2 - 564:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_29_forwards_matches : mword ty29 -> bool\<close>\<close>
+
+definition hex_bits_29_forwards_matches :: "(29)Word.word \<Rightarrow> bool " where
+ " hex_bits_29_forwards_matches bv = ( True )"
+ for bv :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_29_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_29_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_29_backwards_matches s = (
+ if ((case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 29 Word.word * ii))option)) of
+ Some ((g__23, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_29_backwards : string -> M (mword ty29)\<close>\<close>
+
+definition hex_bits_29_backwards :: " string \<Rightarrow>((register_value),((29)Word.word),(exception))monad " where
+ " hex_bits_29_backwards s = (
+ (case ((hex_bits_29_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 29 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 581:2 - 583:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_30_forwards_matches : mword ty30 -> bool\<close>\<close>
+
+definition hex_bits_30_forwards_matches :: "(30)Word.word \<Rightarrow> bool " where
+ " hex_bits_30_forwards_matches bv = ( True )"
+ for bv :: "(30)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_30_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_30_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_30_backwards_matches s = (
+ if ((case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 30 Word.word * ii))option)) of
+ Some ((g__22, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_30_backwards : string -> M (mword ty30)\<close>\<close>
+
+definition hex_bits_30_backwards :: " string \<Rightarrow>((register_value),((30)Word.word),(exception))monad " where
+ " hex_bits_30_backwards s = (
+ (case ((hex_bits_30_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 30 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 600:2 - 602:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_31_forwards_matches : mword ty31 -> bool\<close>\<close>
+
+definition hex_bits_31_forwards_matches :: "(31)Word.word \<Rightarrow> bool " where
+ " hex_bits_31_forwards_matches bv = ( True )"
+ for bv :: "(31)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_31_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_31_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_31_backwards_matches s = (
+ if ((case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 31 Word.word * ii))option)) of
+ Some ((g__21, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_31_backwards : string -> M (mword ty31)\<close>\<close>
+
+definition hex_bits_31_backwards :: " string \<Rightarrow>((register_value),((31)Word.word),(exception))monad " where
+ " hex_bits_31_backwards s = (
+ (case ((hex_bits_31_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 31 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 619:2 - 621:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_32_forwards_matches : mword ty32 -> bool\<close>\<close>
+
+definition hex_bits_32_forwards_matches :: "(32)Word.word \<Rightarrow> bool " where
+ " hex_bits_32_forwards_matches bv = ( True )"
+ for bv :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_32_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_32_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_32_backwards_matches s = (
+ if ((case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 32 Word.word * ii))option)) of
+ Some ((g__20, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_32_backwards : string -> M (mword ty32)\<close>\<close>
+
+definition hex_bits_32_backwards :: " string \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " hex_bits_32_backwards s = (
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 32 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 638:2 - 640:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_33_forwards_matches : mword ty33 -> bool\<close>\<close>
+
+definition hex_bits_33_forwards_matches :: "(33)Word.word \<Rightarrow> bool " where
+ " hex_bits_33_forwards_matches bv = ( True )"
+ for bv :: "(33)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_33_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_33_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_33_backwards_matches s = (
+ if ((case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 33 Word.word * ii))option)) of
+ Some ((g__19, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_33_backwards : string -> M (mword ty33)\<close>\<close>
+
+definition hex_bits_33_backwards :: " string \<Rightarrow>((register_value),((33)Word.word),(exception))monad " where
+ " hex_bits_33_backwards s = (
+ (case ((hex_bits_33_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 33 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 657:2 - 659:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_48_forwards_matches : mword ty48 -> bool\<close>\<close>
+
+definition hex_bits_48_forwards_matches :: "(48)Word.word \<Rightarrow> bool " where
+ " hex_bits_48_forwards_matches bv = ( True )"
+ for bv :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_48_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_48_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_48_backwards_matches s = (
+ if ((case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 48 Word.word * ii))option)) of
+ Some ((g__18, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_48_backwards : string -> M (mword ty48)\<close>\<close>
+
+definition hex_bits_48_backwards :: " string \<Rightarrow>((register_value),((48)Word.word),(exception))monad " where
+ " hex_bits_48_backwards s = (
+ (case ((hex_bits_48_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 48 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 676:2 - 678:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_64_forwards_matches : mword ty64 -> bool\<close>\<close>
+
+definition hex_bits_64_forwards_matches :: "(64)Word.word \<Rightarrow> bool " where
+ " hex_bits_64_forwards_matches bv = ( True )"
+ for bv :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val hex_bits_64_backwards_matches : string -> bool\<close>\<close>
+
+definition hex_bits_64_backwards_matches :: " string \<Rightarrow> bool " where
+ " hex_bits_64_backwards_matches s = (
+ if ((case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 64 Word.word * ii))option)) of
+ Some ((g__17, n)) => if (((n = ((string_length s))))) then True else False
+ | _ => False
+ )) then
+ True
+ else False )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val hex_bits_64_backwards : string -> M (mword ty64)\<close>\<close>
+
+definition hex_bits_64_backwards :: " string \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " hex_bits_64_backwards s = (
+ (case ((hex_bits_64_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict s :: (( 64 Word.word * ii))option)) of
+ Some ((bv, n)) =>
+ if (((n = ((string_length s))))) then return bv
+ else
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3'') \<then>
+ exit0 ()
+ | _ =>
+ assert_exp False (''Pattern match failure at model/prelude_mapping.sail 695:2 - 697:3'') \<then>
+ exit0 ()
+ ))"
+ for s :: " string "
+
+
+definition default_meta :: " unit " where
+ " default_meta = ( () )"
+
+
+\<comment> \<open>\<open>val __WriteRAM_Meta : mword ty64 -> integer -> unit -> M unit\<close>\<close>
+
+definition WriteRAM_Meta :: "(64)Word.word \<Rightarrow> int \<Rightarrow> unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " WriteRAM_Meta addr width meta = ( return () )"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val __ReadRAM_Meta : mword ty64 -> integer -> M unit\<close>\<close>
+
+definition ReadRAM_Meta :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ReadRAM_Meta addr width = ( return () )"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val write_ram : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M bool\<close>\<close>
+
+definition write_ram :: " write_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " write_ram wk addr width data meta = (
+ write_mem instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 64 :: int)::ii) addr width data \<bind> (\<lambda> (ret :: bool) .
+ (if ret then WriteRAM_Meta addr width meta else return () ) \<then> return ret))"
+ for wk :: " write_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val write_ram_ea : write_kind -> mword ty64 -> integer -> M unit\<close>\<close>
+
+definition write_ram_ea :: " write_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " write_ram_ea wk addr width = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict wk (( 64 :: int)::ii) addr width )"
+ for wk :: " write_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val read_ram : forall 'int8_times_n. Size 'int8_times_n => read_kind -> mword ty64 -> integer -> M (mword 'int8_times_n)\<close>\<close>
+
+definition read_ram :: " read_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('int8_times_n::len)Word.word),(exception))monad " where
+ " read_ram rk addr width = ( (read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rk (( 64 :: int)::ii) addr width :: (( 'int8_times_n::len)Word.word) M))"
+ for rk :: " read_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val __TraceMemoryWrite : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit\<close>\<close>
+
+\<comment> \<open>\<open>val __TraceMemoryRead : forall 'm 'int8_times_n. Size 'm, Size 'int8_times_n => integer -> mword 'm -> mword 'int8_times_n -> unit\<close>\<close>
+
+definition xlen_val :: " int " where
+ " xlen_val = ( (( 64 :: int)::ii))"
+
+
+definition xlen_max_unsigned :: " int " where
+ " xlen_max_unsigned = ( ((pow2 (( 64 :: int)::ii))) - (( 1 :: int)::ii))"
+
+
+definition xlen_max_signed :: " int " where
+ " xlen_max_signed = ( ((pow2 (((( 64 :: int)::ii) - (( 1 :: int)::ii))))) - (( 1 :: int)::ii))"
+
+
+definition xlen_min_signed :: " int " where
+ " xlen_min_signed = ( (( 0 :: int)::ii) - ((pow2 (((( 64 :: int)::ii) - (( 1 :: int)::ii))))))"
+
+
+\<comment> \<open>\<open>val regidx_to_regno : mword ty5 -> integer\<close>\<close>
+
+definition regidx_to_regno :: "(5)Word.word \<Rightarrow> int " where
+ " regidx_to_regno b = (
+ (let r = (Word.uint b) in
+ r))"
+ for b :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val creg2reg_idx : mword ty3 -> mword ty5\<close>\<close>
+
+definition creg2reg_idx :: "(3)Word.word \<Rightarrow>(5)Word.word " where
+ " creg2reg_idx creg = ( (concat_vec (vec_of_bits [B0,B1] :: 2 Word.word) creg :: 5 Word.word))"
+ for creg :: "(3)Word.word "
+
+
+definition zreg :: "(5)Word.word " where
+ " zreg = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))"
+
+
+definition ra :: "(5)Word.word " where
+ " ra = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))"
+
+
+definition sp :: "(5)Word.word " where
+ " sp = ( (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))"
+
+
+\<comment> \<open>\<open>val Architecture_of_num : integer -> Architecture\<close>\<close>
+
+definition Architecture_of_num :: " int \<Rightarrow> Architecture " where
+ " Architecture_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RV32
+ else if (((p00 = (( 1 :: int)::ii)))) then RV64
+ else RV128))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Architecture : Architecture -> integer\<close>\<close>
+
+fun num_of_Architecture :: " Architecture \<Rightarrow> int " where
+ " num_of_Architecture RV32 = ( (( 0 :: int)::ii))"
+|" num_of_Architecture RV64 = ( (( 1 :: int)::ii))"
+|" num_of_Architecture RV128 = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val architecture : mword ty2 -> maybe Architecture\<close>\<close>
+
+definition architecture :: "(2)Word.word \<Rightarrow>(Architecture)option " where
+ " architecture a = (
+ (let b__0 = a in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Some RV32
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Some RV64
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then Some RV128
+ else None))"
+ for a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val arch_to_bits : Architecture -> mword ty2\<close>\<close>
+
+fun arch_to_bits :: " Architecture \<Rightarrow>(2)Word.word " where
+ " arch_to_bits RV32 = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" arch_to_bits RV64 = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" arch_to_bits RV128 = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val Privilege_of_num : integer -> Privilege\<close>\<close>
+
+definition Privilege_of_num :: " int \<Rightarrow> Privilege " where
+ " Privilege_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then User
+ else if (((p00 = (( 1 :: int)::ii)))) then Supervisor
+ else Machine))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Privilege : Privilege -> integer\<close>\<close>
+
+fun num_of_Privilege :: " Privilege \<Rightarrow> int " where
+ " num_of_Privilege User = ( (( 0 :: int)::ii))"
+|" num_of_Privilege Supervisor = ( (( 1 :: int)::ii))"
+|" num_of_Privilege Machine = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val privLevel_to_bits : Privilege -> mword ty2\<close>\<close>
+
+fun privLevel_to_bits :: " Privilege \<Rightarrow>(2)Word.word " where
+ " privLevel_to_bits User = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" privLevel_to_bits Supervisor = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" privLevel_to_bits Machine = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val privLevel_of_bits : mword ty2 -> M Privilege\<close>\<close>
+
+definition privLevel_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " privLevel_of_bits p = (
+ (let b__0 = p in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return User
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return Supervisor
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return Machine
+ else assert_exp False (''Pattern match failure at model/riscv_types.sail 78:2 - 82:3'') \<then> exit0 () ))"
+ for p :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val privLevel_to_str : Privilege -> string\<close>\<close>
+
+fun privLevel_to_str :: " Privilege \<Rightarrow> string " where
+ " privLevel_to_str User = ( (''U''))"
+|" privLevel_to_str Supervisor = ( (''S''))"
+|" privLevel_to_str Machine = ( (''M''))"
+
+
+\<comment> \<open>\<open>val print_insn : ast -> M string\<close>\<close>
+
+\<comment> \<open>\<open>val Retired_of_num : integer -> Retired\<close>\<close>
+
+definition Retired_of_num :: " int \<Rightarrow> Retired " where
+ " Retired_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RETIRE_SUCCESS
+ else RETIRE_FAIL))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_Retired : Retired -> integer\<close>\<close>
+
+fun num_of_Retired :: " Retired \<Rightarrow> int " where
+ " num_of_Retired RETIRE_SUCCESS = ( (( 0 :: int)::ii))"
+|" num_of_Retired RETIRE_FAIL = ( (( 1 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val AccessType_of_num : integer -> AccessType\<close>\<close>
+
+definition AccessType_of_num :: " int \<Rightarrow> AccessType " where
+ " AccessType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Read
+ else if (((p00 = (( 1 :: int)::ii)))) then Write
+ else if (((p00 = (( 2 :: int)::ii)))) then ReadWrite
+ else Execute))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_AccessType : AccessType -> integer\<close>\<close>
+
+fun num_of_AccessType :: " AccessType \<Rightarrow> int " where
+ " num_of_AccessType Read = ( (( 0 :: int)::ii))"
+|" num_of_AccessType Write = ( (( 1 :: int)::ii))"
+|" num_of_AccessType ReadWrite = ( (( 2 :: int)::ii))"
+|" num_of_AccessType Execute = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val accessType_to_str : AccessType -> string\<close>\<close>
+
+fun accessType_to_str :: " AccessType \<Rightarrow> string " where
+ " accessType_to_str Read = ( (''R''))"
+|" accessType_to_str Write = ( (''W''))"
+|" accessType_to_str ReadWrite = ( (''RW''))"
+|" accessType_to_str Execute = ( (''X''))"
+
+
+\<comment> \<open>\<open>val word_width_of_num : integer -> word_width\<close>\<close>
+
+definition word_width_of_num :: " int \<Rightarrow> word_width " where
+ " word_width_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then BYTE
+ else if (((p00 = (( 1 :: int)::ii)))) then HALF
+ else if (((p00 = (( 2 :: int)::ii)))) then WORD
+ else DOUBLE))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_word_width : word_width -> integer\<close>\<close>
+
+fun num_of_word_width :: " word_width \<Rightarrow> int " where
+ " num_of_word_width BYTE = ( (( 0 :: int)::ii))"
+|" num_of_word_width HALF = ( (( 1 :: int)::ii))"
+|" num_of_word_width WORD = ( (( 2 :: int)::ii))"
+|" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val InterruptType_of_num : integer -> InterruptType\<close>\<close>
+
+definition InterruptType_of_num :: " int \<Rightarrow> InterruptType " where
+ " InterruptType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then I_U_Software
+ else if (((p00 = (( 1 :: int)::ii)))) then I_S_Software
+ else if (((p00 = (( 2 :: int)::ii)))) then I_M_Software
+ else if (((p00 = (( 3 :: int)::ii)))) then I_U_Timer
+ else if (((p00 = (( 4 :: int)::ii)))) then I_S_Timer
+ else if (((p00 = (( 5 :: int)::ii)))) then I_M_Timer
+ else if (((p00 = (( 6 :: int)::ii)))) then I_U_External
+ else if (((p00 = (( 7 :: int)::ii)))) then I_S_External
+ else I_M_External))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_InterruptType : InterruptType -> integer\<close>\<close>
+
+fun num_of_InterruptType :: " InterruptType \<Rightarrow> int " where
+ " num_of_InterruptType I_U_Software = ( (( 0 :: int)::ii))"
+|" num_of_InterruptType I_S_Software = ( (( 1 :: int)::ii))"
+|" num_of_InterruptType I_M_Software = ( (( 2 :: int)::ii))"
+|" num_of_InterruptType I_U_Timer = ( (( 3 :: int)::ii))"
+|" num_of_InterruptType I_S_Timer = ( (( 4 :: int)::ii))"
+|" num_of_InterruptType I_M_Timer = ( (( 5 :: int)::ii))"
+|" num_of_InterruptType I_U_External = ( (( 6 :: int)::ii))"
+|" num_of_InterruptType I_S_External = ( (( 7 :: int)::ii))"
+|" num_of_InterruptType I_M_External = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val interruptType_to_bits : InterruptType -> mword ty8\<close>\<close>
+
+fun interruptType_to_bits :: " InterruptType \<Rightarrow>(8)Word.word " where
+ " interruptType_to_bits I_U_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_Software = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_U_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_Timer = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_U_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))"
+|" interruptType_to_bits I_S_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))"
+|" interruptType_to_bits I_M_External = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word))"
+
+
+\<comment> \<open>\<open>val ExceptionType_of_num : integer -> ExceptionType\<close>\<close>
+
+definition ExceptionType_of_num :: " int \<Rightarrow> ExceptionType " where
+ " ExceptionType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align
+ else if (((p00 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault
+ else if (((p00 = (( 2 :: int)::ii)))) then E_Illegal_Instr
+ else if (((p00 = (( 3 :: int)::ii)))) then E_Breakpoint
+ else if (((p00 = (( 4 :: int)::ii)))) then E_Load_Addr_Align
+ else if (((p00 = (( 5 :: int)::ii)))) then E_Load_Access_Fault
+ else if (((p00 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align
+ else if (((p00 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault
+ else if (((p00 = (( 8 :: int)::ii)))) then E_U_EnvCall
+ else if (((p00 = (( 9 :: int)::ii)))) then E_S_EnvCall
+ else if (((p00 = (( 10 :: int)::ii)))) then E_Reserved_10
+ else if (((p00 = (( 11 :: int)::ii)))) then E_M_EnvCall
+ else if (((p00 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault
+ else if (((p00 = (( 13 :: int)::ii)))) then E_Load_Page_Fault
+ else if (((p00 = (( 14 :: int)::ii)))) then E_Reserved_14
+ else if (((p00 = (( 15 :: int)::ii)))) then E_SAMO_Page_Fault
+ else E_CHERI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ExceptionType : ExceptionType -> integer\<close>\<close>
+
+fun num_of_ExceptionType :: " ExceptionType \<Rightarrow> int " where
+ " num_of_ExceptionType E_Fetch_Addr_Align = ( (( 0 :: int)::ii))"
+|" num_of_ExceptionType E_Fetch_Access_Fault = ( (( 1 :: int)::ii))"
+|" num_of_ExceptionType E_Illegal_Instr = ( (( 2 :: int)::ii))"
+|" num_of_ExceptionType E_Breakpoint = ( (( 3 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Addr_Align = ( (( 4 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Access_Fault = ( (( 5 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Addr_Align = ( (( 6 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Access_Fault = ( (( 7 :: int)::ii))"
+|" num_of_ExceptionType E_U_EnvCall = ( (( 8 :: int)::ii))"
+|" num_of_ExceptionType E_S_EnvCall = ( (( 9 :: int)::ii))"
+|" num_of_ExceptionType E_Reserved_10 = ( (( 10 :: int)::ii))"
+|" num_of_ExceptionType E_M_EnvCall = ( (( 11 :: int)::ii))"
+|" num_of_ExceptionType E_Fetch_Page_Fault = ( (( 12 :: int)::ii))"
+|" num_of_ExceptionType E_Load_Page_Fault = ( (( 13 :: int)::ii))"
+|" num_of_ExceptionType E_Reserved_14 = ( (( 14 :: int)::ii))"
+|" num_of_ExceptionType E_SAMO_Page_Fault = ( (( 15 :: int)::ii))"
+|" num_of_ExceptionType E_CHERI = ( (( 16 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val exceptionType_to_bits : ExceptionType -> mword ty8\<close>\<close>
+
+fun exceptionType_to_bits :: " ExceptionType \<Rightarrow>(8)Word.word " where
+ " exceptionType_to_bits E_Fetch_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Fetch_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Illegal_Instr = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Breakpoint = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Access_Fault = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_U_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_S_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Reserved_10 = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_M_EnvCall = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Fetch_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_Load_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_Reserved_14 = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B0] :: 8 Word.word))"
+|" exceptionType_to_bits E_SAMO_Page_Fault = ( (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1] :: 8 Word.word))"
+|" exceptionType_to_bits E_CHERI = ( (vec_of_bits [B0,B0,B1,B0,B0,B0,B0,B0] :: 8 Word.word))"
+
+
+\<comment> \<open>\<open>val exceptionType_to_str : ExceptionType -> string\<close>\<close>
+
+fun exceptionType_to_str :: " ExceptionType \<Rightarrow> string " where
+ " exceptionType_to_str E_Fetch_Addr_Align = ( (''misaligned-fetch''))"
+|" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))"
+|" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))"
+|" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))"
+|" exceptionType_to_str E_Load_Addr_Align = ( (''misaligned-load''))"
+|" exceptionType_to_str E_Load_Access_Fault = ( (''load-access-fault''))"
+|" exceptionType_to_str E_SAMO_Addr_Align = ( (''misaliged-store/amo''))"
+|" exceptionType_to_str E_SAMO_Access_Fault = ( (''store/amo-access-fault''))"
+|" exceptionType_to_str E_U_EnvCall = ( (''u-call''))"
+|" exceptionType_to_str E_S_EnvCall = ( (''s-call''))"
+|" exceptionType_to_str E_Reserved_10 = ( (''reserved-0''))"
+|" exceptionType_to_str E_M_EnvCall = ( (''m-call''))"
+|" exceptionType_to_str E_Fetch_Page_Fault = ( (''fetch-page-fault''))"
+|" exceptionType_to_str E_Load_Page_Fault = ( (''load-page-fault''))"
+|" exceptionType_to_str E_Reserved_14 = ( (''reserved-1''))"
+|" exceptionType_to_str E_SAMO_Page_Fault = ( (''store/amo-page-fault''))"
+|" exceptionType_to_str E_CHERI = ( (''CHERI''))"
+
+
+\<comment> \<open>\<open>val not_implemented : forall 'a. string -> M 'a\<close>\<close>
+
+definition not_implemented :: " string \<Rightarrow>((register_value),'a,(exception))monad " where
+ " not_implemented message = ( throw (Error_not_implemented message))"
+ for message :: " string "
+
+
+\<comment> \<open>\<open>val internal_error : forall 'a. string -> M 'a\<close>\<close>
+
+definition internal_error :: " string \<Rightarrow>((register_value),'a,(exception))monad " where
+ " internal_error s = ( assert_exp False s \<then> exit0 () )"
+ for s :: " string "
+
+
+\<comment> \<open>\<open>val TrapVectorMode_of_num : integer -> TrapVectorMode\<close>\<close>
+
+definition TrapVectorMode_of_num :: " int \<Rightarrow> TrapVectorMode " where
+ " TrapVectorMode_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then TV_Direct
+ else if (((p00 = (( 1 :: int)::ii)))) then TV_Vector
+ else TV_Reserved))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_TrapVectorMode : TrapVectorMode -> integer\<close>\<close>
+
+fun num_of_TrapVectorMode :: " TrapVectorMode \<Rightarrow> int " where
+ " num_of_TrapVectorMode TV_Direct = ( (( 0 :: int)::ii))"
+|" num_of_TrapVectorMode TV_Vector = ( (( 1 :: int)::ii))"
+|" num_of_TrapVectorMode TV_Reserved = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode\<close>\<close>
+
+definition trapVectorMode_of_bits :: "(2)Word.word \<Rightarrow> TrapVectorMode " where
+ " trapVectorMode_of_bits m = (
+ (let b__0 = m in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then TV_Direct
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then TV_Vector
+ else TV_Reserved))"
+ for m :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val ExtStatus_of_num : integer -> ExtStatus\<close>\<close>
+
+definition ExtStatus_of_num :: " int \<Rightarrow> ExtStatus " where
+ " ExtStatus_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Off
+ else if (((p00 = (( 1 :: int)::ii)))) then Initial
+ else if (((p00 = (( 2 :: int)::ii)))) then Clean
+ else Dirty))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ExtStatus : ExtStatus -> integer\<close>\<close>
+
+fun num_of_ExtStatus :: " ExtStatus \<Rightarrow> int " where
+ " num_of_ExtStatus Off = ( (( 0 :: int)::ii))"
+|" num_of_ExtStatus Initial = ( (( 1 :: int)::ii))"
+|" num_of_ExtStatus Clean = ( (( 2 :: int)::ii))"
+|" num_of_ExtStatus Dirty = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val extStatus_to_bits : ExtStatus -> mword ty2\<close>\<close>
+
+fun extStatus_to_bits :: " ExtStatus \<Rightarrow>(2)Word.word " where
+ " extStatus_to_bits Off = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" extStatus_to_bits Initial = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" extStatus_to_bits Clean = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" extStatus_to_bits Dirty = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val extStatus_of_bits : mword ty2 -> M ExtStatus\<close>\<close>
+
+definition extStatus_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(ExtStatus),(exception))monad " where
+ " extStatus_of_bits e = (
+ (let b__0 = e in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return Off
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return Initial
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return Clean
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return Dirty
+ else assert_exp False (''Pattern match failure at model/riscv_types.sail 264:2 - 269:3'') \<then> exit0 () ))"
+ for e :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val SATPMode_of_num : integer -> SATPMode\<close>\<close>
+
+definition SATPMode_of_num :: " int \<Rightarrow> SATPMode " where
+ " SATPMode_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then Sbare
+ else if (((p00 = (( 1 :: int)::ii)))) then Sv32
+ else if (((p00 = (( 2 :: int)::ii)))) then Sv39
+ else Sv48))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_SATPMode : SATPMode -> integer\<close>\<close>
+
+fun num_of_SATPMode :: " SATPMode \<Rightarrow> int " where
+ " num_of_SATPMode Sbare = ( (( 0 :: int)::ii))"
+|" num_of_SATPMode Sv32 = ( (( 1 :: int)::ii))"
+|" num_of_SATPMode Sv39 = ( (( 2 :: int)::ii))"
+|" num_of_SATPMode Sv48 = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val satp64Mode_of_bits : Architecture -> mword ty4 -> maybe SATPMode\<close>\<close>
+
+definition satp64Mode_of_bits :: " Architecture \<Rightarrow>(4)Word.word \<Rightarrow>(SATPMode)option " where
+ " satp64Mode_of_bits (g__16 :: Architecture) (b__0 :: satp_mode) = (
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then Some Sbare
+ else
+ (case (g__16, b__0) of
+ (RV32, b__0) =>
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then Some Sv32
+ else (case (RV32, b__0) of (_, _) => None )
+ | (RV64, b__0) =>
+ if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then Some Sv39
+ else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then Some Sv48
+ else (case (RV64, b__0) of (_, _) => None )
+ | (_, _) => None
+ ))"
+ for g__16 :: " Architecture "
+ and b__0 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val uop_of_num : integer -> uop\<close>\<close>
+
+definition uop_of_num :: " int \<Rightarrow> uop " where
+ " uop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_LUI
+ else RISCV_AUIPC))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_uop : uop -> integer\<close>\<close>
+
+fun num_of_uop :: " uop \<Rightarrow> int " where
+ " num_of_uop RISCV_LUI = ( (( 0 :: int)::ii))"
+|" num_of_uop RISCV_AUIPC = ( (( 1 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val bop_of_num : integer -> bop\<close>\<close>
+
+definition bop_of_num :: " int \<Rightarrow> bop " where
+ " bop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_BEQ
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_BNE
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_BLT
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_BGE
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_BLTU
+ else RISCV_BGEU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_bop : bop -> integer\<close>\<close>
+
+fun num_of_bop :: " bop \<Rightarrow> int " where
+ " num_of_bop RISCV_BEQ = ( (( 0 :: int)::ii))"
+|" num_of_bop RISCV_BNE = ( (( 1 :: int)::ii))"
+|" num_of_bop RISCV_BLT = ( (( 2 :: int)::ii))"
+|" num_of_bop RISCV_BGE = ( (( 3 :: int)::ii))"
+|" num_of_bop RISCV_BLTU = ( (( 4 :: int)::ii))"
+|" num_of_bop RISCV_BGEU = ( (( 5 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val iop_of_num : integer -> iop\<close>\<close>
+
+definition iop_of_num :: " int \<Rightarrow> iop " where
+ " iop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDI
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SLTI
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLTIU
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_XORI
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_ORI
+ else RISCV_ANDI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_iop : iop -> integer\<close>\<close>
+
+fun num_of_iop :: " iop \<Rightarrow> int " where
+ " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))"
+|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))"
+|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))"
+|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))"
+|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))"
+|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sop_of_num : integer -> sop\<close>\<close>
+
+definition sop_of_num :: " int \<Rightarrow> sop " where
+ " sop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLI
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLI
+ else RISCV_SRAI))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_sop : sop -> integer\<close>\<close>
+
+fun num_of_sop :: " sop \<Rightarrow> int " where
+ " num_of_sop RISCV_SLLI = ( (( 0 :: int)::ii))"
+|" num_of_sop RISCV_SRLI = ( (( 1 :: int)::ii))"
+|" num_of_sop RISCV_SRAI = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val rop_of_num : integer -> rop\<close>\<close>
+
+definition rop_of_num :: " int \<Rightarrow> rop " where
+ " rop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADD
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUB
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLL
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SLT
+ else if (((p00 = (( 4 :: int)::ii)))) then RISCV_SLTU
+ else if (((p00 = (( 5 :: int)::ii)))) then RISCV_XOR
+ else if (((p00 = (( 6 :: int)::ii)))) then RISCV_SRL
+ else if (((p00 = (( 7 :: int)::ii)))) then RISCV_SRA
+ else if (((p00 = (( 8 :: int)::ii)))) then RISCV_OR
+ else RISCV_AND))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_rop : rop -> integer\<close>\<close>
+
+fun num_of_rop :: " rop \<Rightarrow> int " where
+ " num_of_rop RISCV_ADD = ( (( 0 :: int)::ii))"
+|" num_of_rop RISCV_SUB = ( (( 1 :: int)::ii))"
+|" num_of_rop RISCV_SLL = ( (( 2 :: int)::ii))"
+|" num_of_rop RISCV_SLT = ( (( 3 :: int)::ii))"
+|" num_of_rop RISCV_SLTU = ( (( 4 :: int)::ii))"
+|" num_of_rop RISCV_XOR = ( (( 5 :: int)::ii))"
+|" num_of_rop RISCV_SRL = ( (( 6 :: int)::ii))"
+|" num_of_rop RISCV_SRA = ( (( 7 :: int)::ii))"
+|" num_of_rop RISCV_OR = ( (( 8 :: int)::ii))"
+|" num_of_rop RISCV_AND = ( (( 9 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val ropw_of_num : integer -> ropw\<close>\<close>
+
+definition ropw_of_num :: " int \<Rightarrow> ropw " where
+ " ropw_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDW
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUBW
+ else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLLW
+ else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SRLW
+ else RISCV_SRAW))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_ropw : ropw -> integer\<close>\<close>
+
+fun num_of_ropw :: " ropw \<Rightarrow> int " where
+ " num_of_ropw RISCV_ADDW = ( (( 0 :: int)::ii))"
+|" num_of_ropw RISCV_SUBW = ( (( 1 :: int)::ii))"
+|" num_of_ropw RISCV_SLLW = ( (( 2 :: int)::ii))"
+|" num_of_ropw RISCV_SRLW = ( (( 3 :: int)::ii))"
+|" num_of_ropw RISCV_SRAW = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sopw_of_num : integer -> sopw\<close>\<close>
+
+definition sopw_of_num :: " int \<Rightarrow> sopw " where
+ " sopw_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLIW
+ else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLIW
+ else RISCV_SRAIW))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_sopw : sopw -> integer\<close>\<close>
+
+fun num_of_sopw :: " sopw \<Rightarrow> int " where
+ " num_of_sopw RISCV_SLLIW = ( (( 0 :: int)::ii))"
+|" num_of_sopw RISCV_SRLIW = ( (( 1 :: int)::ii))"
+|" num_of_sopw RISCV_SRAIW = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val amoop_of_num : integer -> amoop\<close>\<close>
+
+definition amoop_of_num :: " int \<Rightarrow> amoop " where
+ " amoop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then AMOSWAP
+ else if (((p00 = (( 1 :: int)::ii)))) then AMOADD
+ else if (((p00 = (( 2 :: int)::ii)))) then AMOXOR
+ else if (((p00 = (( 3 :: int)::ii)))) then AMOAND
+ else if (((p00 = (( 4 :: int)::ii)))) then AMOOR
+ else if (((p00 = (( 5 :: int)::ii)))) then AMOMIN
+ else if (((p00 = (( 6 :: int)::ii)))) then AMOMAX
+ else if (((p00 = (( 7 :: int)::ii)))) then AMOMINU
+ else AMOMAXU))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_amoop : amoop -> integer\<close>\<close>
+
+fun num_of_amoop :: " amoop \<Rightarrow> int " where
+ " num_of_amoop AMOSWAP = ( (( 0 :: int)::ii))"
+|" num_of_amoop AMOADD = ( (( 1 :: int)::ii))"
+|" num_of_amoop AMOXOR = ( (( 2 :: int)::ii))"
+|" num_of_amoop AMOAND = ( (( 3 :: int)::ii))"
+|" num_of_amoop AMOOR = ( (( 4 :: int)::ii))"
+|" num_of_amoop AMOMIN = ( (( 5 :: int)::ii))"
+|" num_of_amoop AMOMAX = ( (( 6 :: int)::ii))"
+|" num_of_amoop AMOMINU = ( (( 7 :: int)::ii))"
+|" num_of_amoop AMOMAXU = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val csrop_of_num : integer -> csrop\<close>\<close>
+
+definition csrop_of_num :: " int \<Rightarrow> csrop " where
+ " csrop_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then CSRRW
+ else if (((p00 = (( 1 :: int)::ii)))) then CSRRS
+ else CSRRC))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_csrop : csrop -> integer\<close>\<close>
+
+fun num_of_csrop :: " csrop \<Rightarrow> int " where
+ " num_of_csrop CSRRW = ( (( 0 :: int)::ii))"
+|" num_of_csrop CSRRS = ( (( 1 :: int)::ii))"
+|" num_of_csrop CSRRC = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val sep_forwards : unit -> string\<close>\<close>
+
+definition sep_forwards :: " unit \<Rightarrow> string " where
+ " sep_forwards _ = (
+ string_append ((opt_spc_forwards () ))
+ ((string_append ('','') ((string_append ((def_spc_forwards () )) (''''))))))"
+
+
+\<comment> \<open>\<open>val sep_backwards : string -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _s0_ : string -> maybe unit\<close>\<close>
+
+definition s0 :: " string \<Rightarrow>(unit)option " where
+ " s0 s20 = (
+ (case ((opt_spc_matches_prefix0 s20)) of
+ Some ((_, s30)) =>
+ (let s41 = (string_drop s20 s30) in
+ if ((string_startswith s41 ('',''))) then
+ (case ((string_drop s41 ((string_length ('',''))))) of
+ s50 =>
+ (case ((def_spc_matches_prefix s50)) of
+ Some ((_, s61)) =>
+ (let p00 = (string_drop s50 s61) in
+ if (((p00 = ('''')))) then Some () else None)
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s20 :: " string "
+
+
+definition sep_backwards :: " string \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " sep_backwards arg1 = (
+ (let s70 = arg1 in
+ if ((case ((s0 s70)) of Some (_) => True | _ => False )) then
+ (case s0 s70 of (Some (_)) => return () )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val sep_forwards_matches : unit -> bool\<close>\<close>
+
+definition sep_forwards_matches :: " unit \<Rightarrow> bool " where
+ " sep_forwards_matches _ = ( True )"
+
+
+\<comment> \<open>\<open>val sep_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s8_ : string -> maybe unit\<close>\<close>
+
+definition s8 :: " string \<Rightarrow>(unit)option " where
+ " s8 s101 = (
+ (case ((opt_spc_matches_prefix0 s101)) of
+ Some ((_, s110)) =>
+ (let s121 = (string_drop s101 s110) in
+ if ((string_startswith s121 ('',''))) then
+ (case ((string_drop s121 ((string_length ('',''))))) of
+ s130 =>
+ (case ((def_spc_matches_prefix s130)) of
+ Some ((_, s141)) =>
+ (let p00 = (string_drop s130 s141) in
+ if (((p00 = ('''')))) then Some () else None)
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s101 :: " string "
+
+
+definition sep_backwards_matches :: " string \<Rightarrow> bool " where
+ " sep_backwards_matches arg1 = (
+ (let s150 = arg1 in
+ if ((case ((s8 s150)) of Some (_) => True | _ => False )) then
+ (case s8 s150 of (Some (_)) => True )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val sep_matches_prefix : string -> maybe ((unit * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s16_ : string -> maybe string\<close>\<close>
+
+definition s16 :: " string \<Rightarrow>(string)option " where
+ " s16 s181 = (
+ (case ((opt_spc_matches_prefix0 s181)) of
+ Some ((_, s190)) =>
+ (let s201 = (string_drop s181 s190) in
+ if ((string_startswith s201 ('',''))) then
+ (case ((string_drop s201 ((string_length ('',''))))) of
+ s210 =>
+ (case ((def_spc_matches_prefix s210)) of
+ Some ((_, s221)) =>
+ (case ((string_drop s210 s221)) of s1 => Some s1 )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s181 :: " string "
+
+
+definition sep_matches_prefix :: " string \<Rightarrow>(unit*int)option " where
+ " sep_matches_prefix arg1 = (
+ (let s230 = arg1 in
+ if ((case ((s16 s230)) of Some (s1) => True | _ => False )) then
+ (case s16 s230 of
+ (Some (s1)) =>
+ Some (() , ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bool_bits_forwards : bool -> mword ty1\<close>\<close>
+
+fun bool_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_bits_forwards True = ( (vec_of_bits [B1] :: 1 Word.word))"
+|" bool_bits_forwards False = ( (vec_of_bits [B0] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val bool_bits_backwards : mword ty1 -> M bool\<close>\<close>
+
+definition bool_bits_backwards :: "(1)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " bool_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_bits_forwards_matches : bool -> bool\<close>\<close>
+
+fun bool_bits_forwards_matches :: " bool \<Rightarrow> bool " where
+ " bool_bits_forwards_matches True = ( True )"
+|" bool_bits_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val bool_bits_backwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bool_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bool_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_not_bits_forwards : bool -> mword ty1\<close>\<close>
+
+fun bool_not_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where
+ " bool_not_bits_forwards True = ( (vec_of_bits [B0] :: 1 Word.word))"
+|" bool_not_bits_forwards False = ( (vec_of_bits [B1] :: 1 Word.word))"
+
+
+\<comment> \<open>\<open>val bool_not_bits_backwards : mword ty1 -> M bool\<close>\<close>
+
+definition bool_not_bits_backwards :: "(1)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " bool_not_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return True
+ else if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bool_not_bits_forwards_matches : bool -> bool\<close>\<close>
+
+fun bool_not_bits_forwards_matches :: " bool \<Rightarrow> bool " where
+ " bool_not_bits_forwards_matches True = ( True )"
+|" bool_not_bits_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val bool_not_bits_backwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bool_not_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bool_not_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val size_bits_forwards : word_width -> mword ty2\<close>\<close>
+
+fun size_bits_forwards :: " word_width \<Rightarrow>(2)Word.word " where
+ " size_bits_forwards BYTE = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" size_bits_forwards HALF = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" size_bits_forwards WORD = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" size_bits_forwards DOUBLE = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val size_bits_backwards : mword ty2 -> M word_width\<close>\<close>
+
+definition size_bits_backwards :: "(2)Word.word \<Rightarrow>((register_value),(word_width),(exception))monad " where
+ " size_bits_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return BYTE
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return HALF
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return WORD
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return DOUBLE
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val size_bits_forwards_matches : word_width -> bool\<close>\<close>
+
+fun size_bits_forwards_matches :: " word_width \<Rightarrow> bool " where
+ " size_bits_forwards_matches BYTE = ( True )"
+|" size_bits_forwards_matches HALF = ( True )"
+|" size_bits_forwards_matches WORD = ( True )"
+|" size_bits_forwards_matches DOUBLE = ( True )"
+
+
+\<comment> \<open>\<open>val size_bits_backwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition size_bits_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " size_bits_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True
+ else False))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val size_mnemonic_forwards : word_width -> string\<close>\<close>
+
+fun size_mnemonic_forwards :: " word_width \<Rightarrow> string " where
+ " size_mnemonic_forwards BYTE = ( (''b''))"
+|" size_mnemonic_forwards HALF = ( (''h''))"
+|" size_mnemonic_forwards WORD = ( (''w''))"
+|" size_mnemonic_forwards DOUBLE = ( (''d''))"
+
+
+\<comment> \<open>\<open>val size_mnemonic_backwards : string -> M word_width\<close>\<close>
+
+definition size_mnemonic_backwards :: " string \<Rightarrow>((register_value),(word_width),(exception))monad " where
+ " size_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''b'')))) then return BYTE
+ else if (((p00 = (''h'')))) then return HALF
+ else if (((p00 = (''w'')))) then return WORD
+ else if (((p00 = (''d'')))) then return DOUBLE
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val size_mnemonic_forwards_matches : word_width -> bool\<close>\<close>
+
+fun size_mnemonic_forwards_matches :: " word_width \<Rightarrow> bool " where
+ " size_mnemonic_forwards_matches BYTE = ( True )"
+|" size_mnemonic_forwards_matches HALF = ( True )"
+|" size_mnemonic_forwards_matches WORD = ( True )"
+|" size_mnemonic_forwards_matches DOUBLE = ( True )"
+
+
+\<comment> \<open>\<open>val size_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition size_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " size_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''b'')))) then True
+ else if (((p00 = (''h'')))) then True
+ else if (((p00 = (''w'')))) then True
+ else if (((p00 = (''d'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s36_ : string -> maybe string\<close>\<close>
+
+definition s36 :: " string \<Rightarrow>(string)option " where
+ " s36 s370 = (
+ (let s381 = s370 in
+ if ((string_startswith s381 (''d''))) then
+ (case ((string_drop s381 ((string_length (''d''))))) of s1 => Some s1 )
+ else None))"
+ for s370 :: " string "
+
+
+\<comment> \<open>\<open>val _s32_ : string -> maybe string\<close>\<close>
+
+definition s32 :: " string \<Rightarrow>(string)option " where
+ " s32 s330 = (
+ (let s341 = s330 in
+ if ((string_startswith s341 (''w''))) then
+ (case ((string_drop s341 ((string_length (''w''))))) of s1 => Some s1 )
+ else None))"
+ for s330 :: " string "
+
+
+\<comment> \<open>\<open>val _s28_ : string -> maybe string\<close>\<close>
+
+definition s28 :: " string \<Rightarrow>(string)option " where
+ " s28 s290 = (
+ (let s301 = s290 in
+ if ((string_startswith s301 (''h''))) then
+ (case ((string_drop s301 ((string_length (''h''))))) of s1 => Some s1 )
+ else None))"
+ for s290 :: " string "
+
+
+\<comment> \<open>\<open>val _s24_ : string -> maybe string\<close>\<close>
+
+definition s24 :: " string \<Rightarrow>(string)option " where
+ " s24 s250 = (
+ (let s261 = s250 in
+ if ((string_startswith s261 (''b''))) then
+ (case ((string_drop s261 ((string_length (''b''))))) of s1 => Some s1 )
+ else None))"
+ for s250 :: " string "
+
+
+definition size_mnemonic_matches_prefix :: " string \<Rightarrow>(word_width*int)option " where
+ " size_mnemonic_matches_prefix arg1 = (
+ (let s270 = arg1 in
+ if ((case ((s24 s270)) of Some (s1) => True | _ => False )) then
+ (case s24 s270 of
+ (Some (s1)) =>
+ Some (BYTE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s28 s270)) of Some (s1) => True | _ => False )) then
+ (case s28 s270 of
+ (Some (s1)) =>
+ Some (HALF, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s32 s270)) of Some (s1) => True | _ => False )) then
+ (case s32 s270 of
+ (Some (s1)) =>
+ Some (WORD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s36 s270)) of Some (s1) => True | _ => False )) then
+ (case s36 s270 of
+ (Some (s1)) =>
+ Some (DOUBLE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val word_width_bytes : word_width -> integer\<close>\<close>
+
+fun word_width_bytes :: " word_width \<Rightarrow> int " where
+ " word_width_bytes BYTE = ( (( 1 :: int)::ii))"
+|" word_width_bytes HALF = ( (( 2 :: int)::ii))"
+|" word_width_bytes WORD = ( (( 4 :: int)::ii))"
+|" word_width_bytes DOUBLE = ( (( 8 :: int)::ii))"
+
+
+definition zero_reg :: "(64)Word.word " where
+ " zero_reg = ( (EXTZ (( 64 :: int)::ii) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 64 Word.word))"
+
+
+\<comment> \<open>\<open>val RegStr : mword ty64 -> string\<close>\<close>
+
+definition RegStr :: "(64)Word.word \<Rightarrow> string " where
+ " RegStr r = ( string_of_bits r )"
+ for r :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val regval_from_reg : mword ty64 -> mword ty64\<close>\<close>
+
+definition regval_from_reg :: "(64)Word.word \<Rightarrow>(64)Word.word " where
+ " regval_from_reg r = ( r )"
+ for r :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val regval_into_reg : mword ty64 -> mword ty64\<close>\<close>
+
+definition regval_into_reg :: "(64)Word.word \<Rightarrow>(64)Word.word " where
+ " regval_into_reg v = ( v )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val rX : integer -> M (mword ty64)\<close>\<close>
+
+definition rX :: " int \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " rX r = (
+ (let p00 = r in
+ (if (((p00 = (( 0 :: int)::ii)))) then return zero_reg
+ else if (((p00 = (( 1 :: int)::ii)))) then (read_reg x1_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 2 :: int)::ii)))) then (read_reg x2_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 3 :: int)::ii)))) then (read_reg x3_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 4 :: int)::ii)))) then (read_reg x4_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 5 :: int)::ii)))) then (read_reg x5_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 6 :: int)::ii)))) then (read_reg x6_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 7 :: int)::ii)))) then (read_reg x7_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 8 :: int)::ii)))) then (read_reg x8_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 9 :: int)::ii)))) then (read_reg x9_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 10 :: int)::ii)))) then (read_reg x10_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 11 :: int)::ii)))) then (read_reg x11_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 12 :: int)::ii)))) then (read_reg x12_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 13 :: int)::ii)))) then (read_reg x13_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 14 :: int)::ii)))) then (read_reg x14_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 15 :: int)::ii)))) then (read_reg x15_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 16 :: int)::ii)))) then (read_reg x16_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 17 :: int)::ii)))) then (read_reg x17_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 18 :: int)::ii)))) then (read_reg x18_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 19 :: int)::ii)))) then (read_reg x19_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 20 :: int)::ii)))) then (read_reg x20_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 21 :: int)::ii)))) then (read_reg x21_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 22 :: int)::ii)))) then (read_reg x22_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 23 :: int)::ii)))) then (read_reg x23_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 24 :: int)::ii)))) then (read_reg x24_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 25 :: int)::ii)))) then (read_reg x25_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 26 :: int)::ii)))) then (read_reg x26_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 27 :: int)::ii)))) then (read_reg x27_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 28 :: int)::ii)))) then (read_reg x28_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 29 :: int)::ii)))) then (read_reg x29_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 30 :: int)::ii)))) then (read_reg x30_ref :: ( 64 Word.word) M)
+ else if (((p00 = (( 31 :: int)::ii)))) then (read_reg x31_ref :: ( 64 Word.word) M)
+ else assert_exp False (''invalid register number'') \<then> exit0 () ) \<bind> (\<lambda> (v :: regtype) .
+ return ((regval_from_reg v :: 64 Word.word)))))"
+ for r :: " int "
+
+
+\<comment> \<open>\<open>val rvfi_wX : integer -> mword ty64 -> unit\<close>\<close>
+
+definition rvfi_wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow> unit " where
+ " rvfi_wX r v = ( () )"
+ for r :: " int "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val wX : integer -> mword ty64 -> M unit\<close>\<close>
+
+definition wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " wX r in_v = (
+ (let v = ((regval_into_reg in_v :: 64 Word.word)) in
+ (let p00 = r in
+ (if (((p00 = (( 0 :: int)::ii)))) then return ()
+ else if (((p00 = (( 1 :: int)::ii)))) then write_reg x1_ref v
+ else if (((p00 = (( 2 :: int)::ii)))) then write_reg x2_ref v
+ else if (((p00 = (( 3 :: int)::ii)))) then write_reg x3_ref v
+ else if (((p00 = (( 4 :: int)::ii)))) then write_reg x4_ref v
+ else if (((p00 = (( 5 :: int)::ii)))) then write_reg x5_ref v
+ else if (((p00 = (( 6 :: int)::ii)))) then write_reg x6_ref v
+ else if (((p00 = (( 7 :: int)::ii)))) then write_reg x7_ref v
+ else if (((p00 = (( 8 :: int)::ii)))) then write_reg x8_ref v
+ else if (((p00 = (( 9 :: int)::ii)))) then write_reg x9_ref v
+ else if (((p00 = (( 10 :: int)::ii)))) then write_reg x10_ref v
+ else if (((p00 = (( 11 :: int)::ii)))) then write_reg x11_ref v
+ else if (((p00 = (( 12 :: int)::ii)))) then write_reg x12_ref v
+ else if (((p00 = (( 13 :: int)::ii)))) then write_reg x13_ref v
+ else if (((p00 = (( 14 :: int)::ii)))) then write_reg x14_ref v
+ else if (((p00 = (( 15 :: int)::ii)))) then write_reg x15_ref v
+ else if (((p00 = (( 16 :: int)::ii)))) then write_reg x16_ref v
+ else if (((p00 = (( 17 :: int)::ii)))) then write_reg x17_ref v
+ else if (((p00 = (( 18 :: int)::ii)))) then write_reg x18_ref v
+ else if (((p00 = (( 19 :: int)::ii)))) then write_reg x19_ref v
+ else if (((p00 = (( 20 :: int)::ii)))) then write_reg x20_ref v
+ else if (((p00 = (( 21 :: int)::ii)))) then write_reg x21_ref v
+ else if (((p00 = (( 22 :: int)::ii)))) then write_reg x22_ref v
+ else if (((p00 = (( 23 :: int)::ii)))) then write_reg x23_ref v
+ else if (((p00 = (( 24 :: int)::ii)))) then write_reg x24_ref v
+ else if (((p00 = (( 25 :: int)::ii)))) then write_reg x25_ref v
+ else if (((p00 = (( 26 :: int)::ii)))) then write_reg x26_ref v
+ else if (((p00 = (( 27 :: int)::ii)))) then write_reg x27_ref v
+ else if (((p00 = (( 28 :: int)::ii)))) then write_reg x28_ref v
+ else if (((p00 = (( 29 :: int)::ii)))) then write_reg x29_ref v
+ else if (((p00 = (( 30 :: int)::ii)))) then write_reg x30_ref v
+ else if (((p00 = (( 31 :: int)::ii)))) then write_reg x31_ref v
+ else assert_exp False (''invalid register number'') \<then> exit0 () ) \<then>
+ return (if (((r \<noteq> (( 0 :: int)::ii)))) then
+ (let (_ :: unit) = (rvfi_wX r in_v) in
+ if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''x'')
+ (((@) ((stringFromInteger r)) (((@) ('' <- '') ((RegStr v))))))))
+ else () )
+ else () ))))"
+ for r :: " int "
+ and in_v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_abi : mword ty5 -> M string\<close>\<close>
+
+definition reg_name_abi :: "(5)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " reg_name_abi r = (
+ (let b__0 = r in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ return (''zero'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''ra'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''sp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''gp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''tp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''fp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''a0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''a1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''a2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''a3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''a4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''a5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''a6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''a7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''s4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''s5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''s6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''s7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''s8'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s9'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s10'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s11'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''t3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t6'')
+ else assert_exp False (''Pattern match failure at model/riscv_regs.sail 149:2 - 182:3'') \<then> exit0 () ))"
+ for r :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_forwards : mword ty5 -> M string\<close>\<close>
+
+definition reg_name_forwards :: "(5)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " reg_name_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ return (''zero'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''ra'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''sp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''gp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''tp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''fp'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''a0'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''a1'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''a2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''a3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''a4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''a5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''a6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''a7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s2'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''s4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''s5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''s6'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''s7'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return (''s8'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ return (''s9'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ return (''s10'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ return (''s11'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return (''t3'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ return (''t4'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ return (''t5'')
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ return (''t6'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_backwards : string -> M (mword ty5)\<close>\<close>
+
+definition reg_name_backwards :: " string \<Rightarrow>((register_value),((5)Word.word),(exception))monad " where
+ " reg_name_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''zero'')))) then return (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''ra'')))) then return (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''sp'')))) then return (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''gp'')))) then return (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''tp'')))) then return (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''t0'')))) then return (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''t1'')))) then return (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''t2'')))) then return (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''fp'')))) then return (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s1'')))) then return (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''a0'')))) then return (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''a1'')))) then return (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''a2'')))) then return (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''a3'')))) then return (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''a4'')))) then return (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''a5'')))) then return (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''a6'')))) then return (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''a7'')))) then return (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s2'')))) then return (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s3'')))) then return (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''s4'')))) then return (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s5'')))) then return (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s6'')))) then return (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s7'')))) then return (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''s8'')))) then return (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''s9'')))) then return (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''s10'')))) then return (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''s11'')))) then return (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)
+ else if (((p00 = (''t3'')))) then return (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)
+ else if (((p00 = (''t4'')))) then return (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)
+ else if (((p00 = (''t5'')))) then return (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)
+ else if (((p00 = (''t6'')))) then return (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val reg_name_forwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition reg_name_forwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " reg_name_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))
+ then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then
+ True
+ else False))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val reg_name_backwards_matches : string -> bool\<close>\<close>
+
+definition reg_name_backwards_matches :: " string \<Rightarrow> bool " where
+ " reg_name_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''zero'')))) then True
+ else if (((p00 = (''ra'')))) then True
+ else if (((p00 = (''sp'')))) then True
+ else if (((p00 = (''gp'')))) then True
+ else if (((p00 = (''tp'')))) then True
+ else if (((p00 = (''t0'')))) then True
+ else if (((p00 = (''t1'')))) then True
+ else if (((p00 = (''t2'')))) then True
+ else if (((p00 = (''fp'')))) then True
+ else if (((p00 = (''s1'')))) then True
+ else if (((p00 = (''a0'')))) then True
+ else if (((p00 = (''a1'')))) then True
+ else if (((p00 = (''a2'')))) then True
+ else if (((p00 = (''a3'')))) then True
+ else if (((p00 = (''a4'')))) then True
+ else if (((p00 = (''a5'')))) then True
+ else if (((p00 = (''a6'')))) then True
+ else if (((p00 = (''a7'')))) then True
+ else if (((p00 = (''s2'')))) then True
+ else if (((p00 = (''s3'')))) then True
+ else if (((p00 = (''s4'')))) then True
+ else if (((p00 = (''s5'')))) then True
+ else if (((p00 = (''s6'')))) then True
+ else if (((p00 = (''s7'')))) then True
+ else if (((p00 = (''s8'')))) then True
+ else if (((p00 = (''s9'')))) then True
+ else if (((p00 = (''s10'')))) then True
+ else if (((p00 = (''s11'')))) then True
+ else if (((p00 = (''t3'')))) then True
+ else if (((p00 = (''t4'')))) then True
+ else if (((p00 = (''t5'')))) then True
+ else if (((p00 = (''t6'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s164_ : string -> maybe string\<close>\<close>
+
+definition s164 :: " string \<Rightarrow>(string)option " where
+ " s164 s1650 = (
+ (let s1660 = s1650 in
+ if ((string_startswith s1660 (''t6''))) then
+ (case ((string_drop s1660 ((string_length (''t6''))))) of s1 => Some s1 )
+ else None))"
+ for s1650 :: " string "
+
+
+\<comment> \<open>\<open>val _s160_ : string -> maybe string\<close>\<close>
+
+definition s160 :: " string \<Rightarrow>(string)option " where
+ " s160 s1610 = (
+ (let s1620 = s1610 in
+ if ((string_startswith s1620 (''t5''))) then
+ (case ((string_drop s1620 ((string_length (''t5''))))) of s1 => Some s1 )
+ else None))"
+ for s1610 :: " string "
+
+
+\<comment> \<open>\<open>val _s156_ : string -> maybe string\<close>\<close>
+
+definition s156 :: " string \<Rightarrow>(string)option " where
+ " s156 s1570 = (
+ (let s1581 = s1570 in
+ if ((string_startswith s1581 (''t4''))) then
+ (case ((string_drop s1581 ((string_length (''t4''))))) of s1 => Some s1 )
+ else None))"
+ for s1570 :: " string "
+
+
+\<comment> \<open>\<open>val _s152_ : string -> maybe string\<close>\<close>
+
+definition s152 :: " string \<Rightarrow>(string)option " where
+ " s152 s1530 = (
+ (let s1540 = s1530 in
+ if ((string_startswith s1540 (''t3''))) then
+ (case ((string_drop s1540 ((string_length (''t3''))))) of s1 => Some s1 )
+ else None))"
+ for s1530 :: " string "
+
+
+\<comment> \<open>\<open>val _s148_ : string -> maybe string\<close>\<close>
+
+definition s148 :: " string \<Rightarrow>(string)option " where
+ " s148 s1490 = (
+ (let s1500 = s1490 in
+ if ((string_startswith s1500 (''s11''))) then
+ (case ((string_drop s1500 ((string_length (''s11''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s1490 :: " string "
+
+
+\<comment> \<open>\<open>val _s144_ : string -> maybe string\<close>\<close>
+
+definition s144 :: " string \<Rightarrow>(string)option " where
+ " s144 s1450 = (
+ (let s1460 = s1450 in
+ if ((string_startswith s1460 (''s10''))) then
+ (case ((string_drop s1460 ((string_length (''s10''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s1450 :: " string "
+
+
+\<comment> \<open>\<open>val _s140_ : string -> maybe string\<close>\<close>
+
+definition s140 :: " string \<Rightarrow>(string)option " where
+ " s140 s1410 = (
+ (let s1420 = s1410 in
+ if ((string_startswith s1420 (''s9''))) then
+ (case ((string_drop s1420 ((string_length (''s9''))))) of s1 => Some s1 )
+ else None))"
+ for s1410 :: " string "
+
+
+\<comment> \<open>\<open>val _s136_ : string -> maybe string\<close>\<close>
+
+definition s136 :: " string \<Rightarrow>(string)option " where
+ " s136 s1370 = (
+ (let s1380 = s1370 in
+ if ((string_startswith s1380 (''s8''))) then
+ (case ((string_drop s1380 ((string_length (''s8''))))) of s1 => Some s1 )
+ else None))"
+ for s1370 :: " string "
+
+
+\<comment> \<open>\<open>val _s132_ : string -> maybe string\<close>\<close>
+
+definition s132 :: " string \<Rightarrow>(string)option " where
+ " s132 s1330 = (
+ (let s1340 = s1330 in
+ if ((string_startswith s1340 (''s7''))) then
+ (case ((string_drop s1340 ((string_length (''s7''))))) of s1 => Some s1 )
+ else None))"
+ for s1330 :: " string "
+
+
+\<comment> \<open>\<open>val _s128_ : string -> maybe string\<close>\<close>
+
+definition s128 :: " string \<Rightarrow>(string)option " where
+ " s128 s1290 = (
+ (let s1300 = s1290 in
+ if ((string_startswith s1300 (''s6''))) then
+ (case ((string_drop s1300 ((string_length (''s6''))))) of s1 => Some s1 )
+ else None))"
+ for s1290 :: " string "
+
+
+\<comment> \<open>\<open>val _s124_ : string -> maybe string\<close>\<close>
+
+definition s124 :: " string \<Rightarrow>(string)option " where
+ " s124 s1250 = (
+ (let s1260 = s1250 in
+ if ((string_startswith s1260 (''s5''))) then
+ (case ((string_drop s1260 ((string_length (''s5''))))) of s1 => Some s1 )
+ else None))"
+ for s1250 :: " string "
+
+
+\<comment> \<open>\<open>val _s120_ : string -> maybe string\<close>\<close>
+
+definition s120 :: " string \<Rightarrow>(string)option " where
+ " s120 s1210 = (
+ (let s1220 = s1210 in
+ if ((string_startswith s1220 (''s4''))) then
+ (case ((string_drop s1220 ((string_length (''s4''))))) of s1 => Some s1 )
+ else None))"
+ for s1210 :: " string "
+
+
+\<comment> \<open>\<open>val _s116_ : string -> maybe string\<close>\<close>
+
+definition s116 :: " string \<Rightarrow>(string)option " where
+ " s116 s1170 = (
+ (let s1180 = s1170 in
+ if ((string_startswith s1180 (''s3''))) then
+ (case ((string_drop s1180 ((string_length (''s3''))))) of s1 => Some s1 )
+ else None))"
+ for s1170 :: " string "
+
+
+\<comment> \<open>\<open>val _s112_ : string -> maybe string\<close>\<close>
+
+definition s112 :: " string \<Rightarrow>(string)option " where
+ " s112 s1130 = (
+ (let s1140 = s1130 in
+ if ((string_startswith s1140 (''s2''))) then
+ (case ((string_drop s1140 ((string_length (''s2''))))) of s1 => Some s1 )
+ else None))"
+ for s1130 :: " string "
+
+
+\<comment> \<open>\<open>val _s108_ : string -> maybe string\<close>\<close>
+
+definition s108 :: " string \<Rightarrow>(string)option " where
+ " s108 s1090 = (
+ (let s1100 = s1090 in
+ if ((string_startswith s1100 (''a7''))) then
+ (case ((string_drop s1100 ((string_length (''a7''))))) of s1 => Some s1 )
+ else None))"
+ for s1090 :: " string "
+
+
+\<comment> \<open>\<open>val _s104_ : string -> maybe string\<close>\<close>
+
+definition s104 :: " string \<Rightarrow>(string)option " where
+ " s104 s1050 = (
+ (let s1060 = s1050 in
+ if ((string_startswith s1060 (''a6''))) then
+ (case ((string_drop s1060 ((string_length (''a6''))))) of s1 => Some s1 )
+ else None))"
+ for s1050 :: " string "
+
+
+\<comment> \<open>\<open>val _s100_ : string -> maybe string\<close>\<close>
+
+definition s100 :: " string \<Rightarrow>(string)option " where
+ " s100 s1010 = (
+ (let s1020 = s1010 in
+ if ((string_startswith s1020 (''a5''))) then
+ (case ((string_drop s1020 ((string_length (''a5''))))) of s1 => Some s1 )
+ else None))"
+ for s1010 :: " string "
+
+
+\<comment> \<open>\<open>val _s96_ : string -> maybe string\<close>\<close>
+
+definition s96 :: " string \<Rightarrow>(string)option " where
+ " s96 s970 = (
+ (let s981 = s970 in
+ if ((string_startswith s981 (''a4''))) then
+ (case ((string_drop s981 ((string_length (''a4''))))) of s1 => Some s1 )
+ else None))"
+ for s970 :: " string "
+
+
+\<comment> \<open>\<open>val _s92_ : string -> maybe string\<close>\<close>
+
+definition s92 :: " string \<Rightarrow>(string)option " where
+ " s92 s930 = (
+ (let s940 = s930 in
+ if ((string_startswith s940 (''a3''))) then
+ (case ((string_drop s940 ((string_length (''a3''))))) of s1 => Some s1 )
+ else None))"
+ for s930 :: " string "
+
+
+\<comment> \<open>\<open>val _s88_ : string -> maybe string\<close>\<close>
+
+definition s88 :: " string \<Rightarrow>(string)option " where
+ " s88 s890 = (
+ (let s900 = s890 in
+ if ((string_startswith s900 (''a2''))) then
+ (case ((string_drop s900 ((string_length (''a2''))))) of s1 => Some s1 )
+ else None))"
+ for s890 :: " string "
+
+
+\<comment> \<open>\<open>val _s84_ : string -> maybe string\<close>\<close>
+
+definition s84 :: " string \<Rightarrow>(string)option " where
+ " s84 s850 = (
+ (let s860 = s850 in
+ if ((string_startswith s860 (''a1''))) then
+ (case ((string_drop s860 ((string_length (''a1''))))) of s1 => Some s1 )
+ else None))"
+ for s850 :: " string "
+
+
+\<comment> \<open>\<open>val _s80_ : string -> maybe string\<close>\<close>
+
+definition s80 :: " string \<Rightarrow>(string)option " where
+ " s80 s810 = (
+ (let s820 = s810 in
+ if ((string_startswith s820 (''a0''))) then
+ (case ((string_drop s820 ((string_length (''a0''))))) of s1 => Some s1 )
+ else None))"
+ for s810 :: " string "
+
+
+\<comment> \<open>\<open>val _s76_ : string -> maybe string\<close>\<close>
+
+definition s76 :: " string \<Rightarrow>(string)option " where
+ " s76 s770 = (
+ (let s780 = s770 in
+ if ((string_startswith s780 (''s1''))) then
+ (case ((string_drop s780 ((string_length (''s1''))))) of s1 => Some s1 )
+ else None))"
+ for s770 :: " string "
+
+
+\<comment> \<open>\<open>val _s72_ : string -> maybe string\<close>\<close>
+
+definition s72 :: " string \<Rightarrow>(string)option " where
+ " s72 s730 = (
+ (let s740 = s730 in
+ if ((string_startswith s740 (''fp''))) then
+ (case ((string_drop s740 ((string_length (''fp''))))) of s1 => Some s1 )
+ else None))"
+ for s730 :: " string "
+
+
+\<comment> \<open>\<open>val _s68_ : string -> maybe string\<close>\<close>
+
+definition s68 :: " string \<Rightarrow>(string)option " where
+ " s68 s690 = (
+ (let s701 = s690 in
+ if ((string_startswith s701 (''t2''))) then
+ (case ((string_drop s701 ((string_length (''t2''))))) of s1 => Some s1 )
+ else None))"
+ for s690 :: " string "
+
+
+\<comment> \<open>\<open>val _s64_ : string -> maybe string\<close>\<close>
+
+definition s64 :: " string \<Rightarrow>(string)option " where
+ " s64 s650 = (
+ (let s661 = s650 in
+ if ((string_startswith s661 (''t1''))) then
+ (case ((string_drop s661 ((string_length (''t1''))))) of s1 => Some s1 )
+ else None))"
+ for s650 :: " string "
+
+
+\<comment> \<open>\<open>val _s60_ : string -> maybe string\<close>\<close>
+
+definition s60 :: " string \<Rightarrow>(string)option " where
+ " s60 s610 = (
+ (let s621 = s610 in
+ if ((string_startswith s621 (''t0''))) then
+ (case ((string_drop s621 ((string_length (''t0''))))) of s1 => Some s1 )
+ else None))"
+ for s610 :: " string "
+
+
+\<comment> \<open>\<open>val _s56_ : string -> maybe string\<close>\<close>
+
+definition s56 :: " string \<Rightarrow>(string)option " where
+ " s56 s570 = (
+ (let s581 = s570 in
+ if ((string_startswith s581 (''tp''))) then
+ (case ((string_drop s581 ((string_length (''tp''))))) of s1 => Some s1 )
+ else None))"
+ for s570 :: " string "
+
+
+\<comment> \<open>\<open>val _s52_ : string -> maybe string\<close>\<close>
+
+definition s52 :: " string \<Rightarrow>(string)option " where
+ " s52 s530 = (
+ (let s541 = s530 in
+ if ((string_startswith s541 (''gp''))) then
+ (case ((string_drop s541 ((string_length (''gp''))))) of s1 => Some s1 )
+ else None))"
+ for s530 :: " string "
+
+
+\<comment> \<open>\<open>val _s48_ : string -> maybe string\<close>\<close>
+
+definition s48 :: " string \<Rightarrow>(string)option " where
+ " s48 s490 = (
+ (let s501 = s490 in
+ if ((string_startswith s501 (''sp''))) then
+ (case ((string_drop s501 ((string_length (''sp''))))) of s1 => Some s1 )
+ else None))"
+ for s490 :: " string "
+
+
+\<comment> \<open>\<open>val _s44_ : string -> maybe string\<close>\<close>
+
+definition s44 :: " string \<Rightarrow>(string)option " where
+ " s44 s450 = (
+ (let s461 = s450 in
+ if ((string_startswith s461 (''ra''))) then
+ (case ((string_drop s461 ((string_length (''ra''))))) of s1 => Some s1 )
+ else None))"
+ for s450 :: " string "
+
+
+\<comment> \<open>\<open>val _s40_ : string -> maybe string\<close>\<close>
+
+definition s40 :: " string \<Rightarrow>(string)option " where
+ " s40 s410 = (
+ (let s421 = s410 in
+ if ((string_startswith s421 (''zero''))) then
+ (case ((string_drop s421 ((string_length (''zero''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s410 :: " string "
+
+
+definition reg_name_matches_prefix :: " string \<Rightarrow>((5)Word.word*int)option " where
+ " reg_name_matches_prefix arg1 = (
+ (let s430 = arg1 in
+ if ((case ((s40 s430)) of Some (s1) => True | _ => False )) then
+ (case s40 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s44 s430)) of Some (s1) => True | _ => False )) then
+ (case s44 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s48 s430)) of Some (s1) => True | _ => False )) then
+ (case s48 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s52 s430)) of Some (s1) => True | _ => False )) then
+ (case s52 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s56 s430)) of Some (s1) => True | _ => False )) then
+ (case s56 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s60 s430)) of Some (s1) => True | _ => False )) then
+ (case s60 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s64 s430)) of Some (s1) => True | _ => False )) then
+ (case s64 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s68 s430)) of Some (s1) => True | _ => False )) then
+ (case s68 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s72 s430)) of Some (s1) => True | _ => False )) then
+ (case s72 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s76 s430)) of Some (s1) => True | _ => False )) then
+ (case s76 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s80 s430)) of Some (s1) => True | _ => False )) then
+ (case s80 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s84 s430)) of Some (s1) => True | _ => False )) then
+ (case s84 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s88 s430)) of Some (s1) => True | _ => False )) then
+ (case s88 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s92 s430)) of Some (s1) => True | _ => False )) then
+ (case s92 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s96 s430)) of Some (s1) => True | _ => False )) then
+ (case s96 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s100 s430)) of Some (s1) => True | _ => False )) then
+ (case s100 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s104 s430)) of Some (s1) => True | _ => False )) then
+ (case s104 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s108 s430)) of Some (s1) => True | _ => False )) then
+ (case s108 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s112 s430)) of Some (s1) => True | _ => False )) then
+ (case s112 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s116 s430)) of Some (s1) => True | _ => False )) then
+ (case s116 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s120 s430)) of Some (s1) => True | _ => False )) then
+ (case s120 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s124 s430)) of Some (s1) => True | _ => False )) then
+ (case s124 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s128 s430)) of Some (s1) => True | _ => False )) then
+ (case s128 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s132 s430)) of Some (s1) => True | _ => False )) then
+ (case s132 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s136 s430)) of Some (s1) => True | _ => False )) then
+ (case s136 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s140 s430)) of Some (s1) => True | _ => False )) then
+ (case s140 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s144 s430)) of Some (s1) => True | _ => False )) then
+ (case s144 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s148 s430)) of Some (s1) => True | _ => False )) then
+ (case s148 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s152 s430)) of Some (s1) => True | _ => False )) then
+ (case s152 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s156 s430)) of Some (s1) => True | _ => False )) then
+ (case s156 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s160 s430)) of Some (s1) => True | _ => False )) then
+ (case s160 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s164 s430)) of Some (s1) => True | _ => False )) then
+ (case s164 s430 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_forwards : mword ty3 -> M string\<close>\<close>
+
+definition creg_name_forwards :: "(3)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " creg_name_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return (''s0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return (''s1'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return (''a0'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return (''a1'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return (''a2'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return (''a3'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return (''a4'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return (''a5'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val creg_name_backwards : string -> M (mword ty3)\<close>\<close>
+
+definition creg_name_backwards :: " string \<Rightarrow>((register_value),((3)Word.word),(exception))monad " where
+ " creg_name_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''s0'')))) then return (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ else if (((p00 = (''s1'')))) then return (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ else if (((p00 = (''a0'')))) then return (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ else if (((p00 = (''a1'')))) then return (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ else if (((p00 = (''a2'')))) then return (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ else if (((p00 = (''a3'')))) then return (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ else if (((p00 = (''a4'')))) then return (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ else if (((p00 = (''a5'')))) then return (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_forwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition creg_name_forwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " creg_name_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val creg_name_backwards_matches : string -> bool\<close>\<close>
+
+definition creg_name_backwards_matches :: " string \<Rightarrow> bool " where
+ " creg_name_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''s0'')))) then True
+ else if (((p00 = (''s1'')))) then True
+ else if (((p00 = (''a0'')))) then True
+ else if (((p00 = (''a1'')))) then True
+ else if (((p00 = (''a2'')))) then True
+ else if (((p00 = (''a3'')))) then True
+ else if (((p00 = (''a4'')))) then True
+ else if (((p00 = (''a5'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val creg_name_matches_prefix : string -> maybe ((mword ty3 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s196_ : string -> maybe string\<close>\<close>
+
+definition s196 :: " string \<Rightarrow>(string)option " where
+ " s196 s1970 = (
+ (let s1980 = s1970 in
+ if ((string_startswith s1980 (''a5''))) then
+ (case ((string_drop s1980 ((string_length (''a5''))))) of s1 => Some s1 )
+ else None))"
+ for s1970 :: " string "
+
+
+\<comment> \<open>\<open>val _s192_ : string -> maybe string\<close>\<close>
+
+definition s192 :: " string \<Rightarrow>(string)option " where
+ " s192 s1930 = (
+ (let s1940 = s1930 in
+ if ((string_startswith s1940 (''a4''))) then
+ (case ((string_drop s1940 ((string_length (''a4''))))) of s1 => Some s1 )
+ else None))"
+ for s1930 :: " string "
+
+
+\<comment> \<open>\<open>val _s188_ : string -> maybe string\<close>\<close>
+
+definition s188 :: " string \<Rightarrow>(string)option " where
+ " s188 s1890 = (
+ (let s1900 = s1890 in
+ if ((string_startswith s1900 (''a3''))) then
+ (case ((string_drop s1900 ((string_length (''a3''))))) of s1 => Some s1 )
+ else None))"
+ for s1890 :: " string "
+
+
+\<comment> \<open>\<open>val _s184_ : string -> maybe string\<close>\<close>
+
+definition s184 :: " string \<Rightarrow>(string)option " where
+ " s184 s1850 = (
+ (let s1860 = s1850 in
+ if ((string_startswith s1860 (''a2''))) then
+ (case ((string_drop s1860 ((string_length (''a2''))))) of s1 => Some s1 )
+ else None))"
+ for s1850 :: " string "
+
+
+\<comment> \<open>\<open>val _s180_ : string -> maybe string\<close>\<close>
+
+definition s180 :: " string \<Rightarrow>(string)option " where
+ " s180 s1810 = (
+ (let s1820 = s1810 in
+ if ((string_startswith s1820 (''a1''))) then
+ (case ((string_drop s1820 ((string_length (''a1''))))) of s1 => Some s1 )
+ else None))"
+ for s1810 :: " string "
+
+
+\<comment> \<open>\<open>val _s176_ : string -> maybe string\<close>\<close>
+
+definition s176 :: " string \<Rightarrow>(string)option " where
+ " s176 s1770 = (
+ (let s1780 = s1770 in
+ if ((string_startswith s1780 (''a0''))) then
+ (case ((string_drop s1780 ((string_length (''a0''))))) of s1 => Some s1 )
+ else None))"
+ for s1770 :: " string "
+
+
+\<comment> \<open>\<open>val _s172_ : string -> maybe string\<close>\<close>
+
+definition s172 :: " string \<Rightarrow>(string)option " where
+ " s172 s1730 = (
+ (let s1740 = s1730 in
+ if ((string_startswith s1740 (''s1''))) then
+ (case ((string_drop s1740 ((string_length (''s1''))))) of s1 => Some s1 )
+ else None))"
+ for s1730 :: " string "
+
+
+\<comment> \<open>\<open>val _s168_ : string -> maybe string\<close>\<close>
+
+definition s168 :: " string \<Rightarrow>(string)option " where
+ " s168 s1690 = (
+ (let s1700 = s1690 in
+ if ((string_startswith s1700 (''s0''))) then
+ (case ((string_drop s1700 ((string_length (''s0''))))) of s1 => Some s1 )
+ else None))"
+ for s1690 :: " string "
+
+
+definition creg_name_matches_prefix :: " string \<Rightarrow>((3)Word.word*int)option " where
+ " creg_name_matches_prefix arg1 = (
+ (let s1711 = arg1 in
+ if ((case ((s168 s1711)) of Some (s1) => True | _ => False )) then
+ (case s168 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s172 s1711)) of Some (s1) => True | _ => False )) then
+ (case s172 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s176 s1711)) of Some (s1) => True | _ => False )) then
+ (case s176 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s180 s1711)) of Some (s1) => True | _ => False )) then
+ (case s180 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s184 s1711)) of Some (s1) => True | _ => False )) then
+ (case s184 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s188 s1711)) of Some (s1) => True | _ => False )) then
+ (case s188 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s192 s1711)) of Some (s1) => True | _ => False )) then
+ (case s192 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s196 s1711)) of Some (s1) => True | _ => False )) then
+ (case s196 s1711 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1] :: 3 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val init_base_regs : unit -> M unit\<close>\<close>
+
+definition init_base_regs :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_base_regs _ = (
+ (((((((((((((((((((((((((((((write_reg x1_ref zero_reg \<then>
+ write_reg x2_ref zero_reg) \<then>
+ write_reg x3_ref zero_reg) \<then>
+ write_reg x4_ref zero_reg) \<then>
+ write_reg x5_ref zero_reg) \<then>
+ write_reg x6_ref zero_reg) \<then>
+ write_reg x7_ref zero_reg) \<then>
+ write_reg x8_ref zero_reg) \<then>
+ write_reg x9_ref zero_reg) \<then>
+ write_reg x10_ref zero_reg) \<then>
+ write_reg x11_ref zero_reg) \<then>
+ write_reg x12_ref zero_reg) \<then>
+ write_reg x13_ref zero_reg) \<then>
+ write_reg x14_ref zero_reg) \<then>
+ write_reg x15_ref zero_reg) \<then>
+ write_reg x16_ref zero_reg) \<then>
+ write_reg x17_ref zero_reg) \<then>
+ write_reg x18_ref zero_reg) \<then>
+ write_reg x19_ref zero_reg) \<then>
+ write_reg x20_ref zero_reg) \<then>
+ write_reg x21_ref zero_reg) \<then>
+ write_reg x22_ref zero_reg) \<then>
+ write_reg x23_ref zero_reg) \<then>
+ write_reg x24_ref zero_reg) \<then>
+ write_reg x25_ref zero_reg) \<then>
+ write_reg x26_ref zero_reg) \<then>
+ write_reg x27_ref zero_reg) \<then>
+ write_reg x28_ref zero_reg) \<then>
+ write_reg x29_ref zero_reg) \<then> write_reg x30_ref zero_reg) \<then> write_reg x31_ref zero_reg )"
+
+
+\<comment> \<open>\<open>
+ Retrieves the architectural PC value. This is not necessarily the value
+ found in the PC register as extensions may choose to override this function.
+ The value in the PC register is the absolute virtual address of the instruction
+ to fetch.
+ \<close>\<close>
+\<comment> \<open>\<open>val get_arch_pc : unit -> M (mword ty64)\<close>\<close>
+
+definition get_arch_pc :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_arch_pc _ = ( (read_reg PC_ref :: ( 64 Word.word) M))"
+
+
+\<comment> \<open>\<open>val get_next_pc : unit -> M (mword ty64)\<close>\<close>
+
+definition get_next_pc :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_next_pc _ = ( (read_reg nextPC_ref :: ( 64 Word.word) M))"
+
+
+\<comment> \<open>\<open>val set_next_pc : mword ty64 -> M unit\<close>\<close>
+
+definition set_next_pc :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_next_pc pc = ( write_reg nextPC_ref pc )"
+ for pc :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val tick_pc : unit -> M unit\<close>\<close>
+
+definition tick_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_pc _ = (
+ (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . write_reg PC_ref w__0))"
+
+
+\<comment> \<open>\<open>val Mk_Misa : mword ty64 -> Misa\<close>\<close>
+
+definition Mk_Misa :: "(64)Word.word \<Rightarrow> Misa " where
+ " Mk_Misa v = ( (| Misa_Misa_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_bits : Misa -> mword ty64\<close>\<close>
+
+definition get_Misa_bits :: " Misa \<Rightarrow>(64)Word.word " where
+ " get_Misa_bits v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Misa_bits :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_bits : Misa -> mword ty64 -> Misa\<close>\<close>
+
+definition update_Misa_bits :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa " where
+ " update_Misa_bits v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_bits : SV48_PTE -> mword ty64 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_bits : SV48_PTE -> mword ty64\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_bits : register_ref regstate register_value SV48_PTE -> mword ty64 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_MXL : Misa -> mword ty2\<close>\<close>
+
+definition get_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word " where
+ " get_Misa_MXL v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Misa_MXL :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_MXL r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 63 :: int)::ii) (( 62 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_MXL : Misa -> mword ty2 -> Misa\<close>\<close>
+
+definition update_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa " where
+ " update_Misa_MXL v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_Z : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Z :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Z v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Z :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Z r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 25 :: int)::ii) (( 25 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Z : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Z :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Z v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_Y : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Y :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Y v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Y :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Y r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 24 :: int)::ii) (( 24 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Y : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Y :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Y v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_X : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_X :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_X v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_X :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_X : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_X v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_X : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_W : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_W :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_W v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_W :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_W : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_W v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_W : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_V : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_V :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_V v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_V :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_V r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_V : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_V v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_V : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_U : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_U :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_U v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_U :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_U r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_U : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_U v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_U : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_T : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_T :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_T v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_T :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_T r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_T : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_T :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_T v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_S : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_S :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_S v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_S :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_S r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_S : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_S :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_S v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_R : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_R :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_R v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_R :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_R : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_R v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_R : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_Q : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_Q :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_Q v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_Q :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_Q r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 16 :: int)::ii) (( 16 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_Q : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_Q :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_Q v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_P : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_P :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_P v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_P :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_P r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_P : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_P :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_P v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_O : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_O :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_O v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_O :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_O r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 14 :: int)::ii) (( 14 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_O : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_O :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_O v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_N : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_N :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_N v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_N :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_N r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_N : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_N :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_N v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_M : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_M :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_M v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_M :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_M r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_M : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_M :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_M v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_L : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_L :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_L v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_L :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_L r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_L : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_L :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_L v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_L : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_L : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_K : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_K :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_K v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_K :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_K r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_K : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_K :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_K v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_J : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_J :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_J v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_J :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_J r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_J : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_J :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_J v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_I : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_I :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_I v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_I :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_I r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_I : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_I :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_I v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_H : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_H :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_H v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_H :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_H r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_H : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_H :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_H v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_G : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_G :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_G v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_G :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_G r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_G : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_G v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_G : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_F : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_F :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_F v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_F :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_F r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_F : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_F :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_F v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_E : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_E :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_E v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_E :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_E r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_E : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_E :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_E v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_D : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_D :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_D v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_D :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_D r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_D : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_D v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_D : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Misa_C : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_C :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_C v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_C :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_C r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_C : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_C :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_C v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_B : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_B :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_B v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_B :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_B r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_B : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_B :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_B v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Misa_A : Misa -> mword ty1\<close>\<close>
+
+definition get_Misa_A :: " Misa \<Rightarrow>(1)Word.word " where
+ " get_Misa_A v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Misa_A :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Misa_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Misa))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Misa_A : Misa -> mword ty1 -> Misa\<close>\<close>
+
+definition update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where
+ " update_Misa_A v x = (
+ (v (|
+ Misa_Misa_chunk_0 :=
+ ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Misa "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits\<close>\<close>
+
+\<comment> \<open>\<open>val _get_PTE_Bits_A : PTE_Bits -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_misa : Misa -> mword ty64 -> M Misa\<close>\<close>
+
+definition legalize_misa :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Misa),(exception))monad " where
+ " legalize_misa (m :: Misa) (v :: xlenbits) = (
+ if ((sys_enable_writable_misa () )) then
+ (let v = (Mk_Misa v) in
+ and_boolM
+ (return (((((get_Misa_C v :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))))
+ ((read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return (((((bit_to_bool ((access_vec_dec w__0 (( 1 :: int)::ii))))) = True))))) \<bind> (\<lambda> (w__1 :: bool) .
+ return (if w__1 then m
+ else update_Misa_C m ((get_Misa_C v :: 1 Word.word)))))
+ else return m )"
+ for m :: " Misa "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val haveAtomics : unit -> M bool\<close>\<close>
+
+definition haveAtomics :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveAtomics _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_A w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveRVC : unit -> M bool\<close>\<close>
+
+definition haveRVC :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveRVC _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveMulDiv : unit -> M bool\<close>\<close>
+
+definition haveMulDiv :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveMulDiv _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_M w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveSupMode : unit -> M bool\<close>\<close>
+
+definition haveSupMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveSupMode _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_S w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveUsrMode : unit -> M bool\<close>\<close>
+
+definition haveUsrMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveUsrMode _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_U w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val haveNExt : unit -> M bool\<close>\<close>
+
+definition haveNExt :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " haveNExt _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_N w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+
+
+\<comment> \<open>\<open>val Mk_Mstatus : mword ty64 -> Mstatus\<close>\<close>
+
+definition Mk_Mstatus :: "(64)Word.word \<Rightarrow> Mstatus " where
+ " Mk_Mstatus v = (
+ (| Mstatus_Mstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_bits : Mstatus -> mword ty64\<close>\<close>
+
+definition get_Mstatus_bits :: " Mstatus \<Rightarrow>(64)Word.word " where
+ " get_Mstatus_bits v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Mstatus_bits :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_bits :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_bits v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SD : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SD v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SD :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SD r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SD v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SD : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_TSR : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TSR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TSR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TSR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TSR v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_TW : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TW v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TW :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TW v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_TVM : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_TVM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_TVM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_TVM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_TVM v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_MXR : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MXR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MXR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MXR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MXR v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_MXR : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_SUM : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SUM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SUM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SUM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SUM v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SUM : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPRV : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MPRV v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPRV :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPRV r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPRV v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_XS : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_XS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_XS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_XS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_XS v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_XS : Sstatus -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_FS : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_FS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_FS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_FS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_FS v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_FS : Sstatus -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPP : Mstatus -> mword ty2\<close>\<close>
+
+definition get_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_Mstatus_MPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 12 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPP v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SPP : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SPP v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SPP : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SPIE : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_UPIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_UPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_UPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_UPIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_UPIE : Ustatus -> mword ty1 -> Ustatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Ustatus_UPIE : Ustatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Ustatus_UPIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_MIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_MIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_MIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_MIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_MIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mstatus_SIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_SIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_SIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_SIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_SIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sstatus_SIE : Sstatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Mstatus_UIE : Mstatus -> mword ty1\<close>\<close>
+
+definition get_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word " where
+ " get_Mstatus_UIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mstatus_UIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mstatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus\<close>\<close>
+
+definition update_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where
+ " update_Mstatus_UIE v x = (
+ (v (|
+ Mstatus_Mstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_UIE : Ustatus -> mword ty1 -> Ustatus\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Ustatus_UIE : Ustatus -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Ustatus_UIE : register_ref regstate register_value Ustatus -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val effectivePrivilege : Mstatus -> Privilege -> M Privilege\<close>\<close>
+
+definition effectivePrivilege :: " Mstatus \<Rightarrow> Privilege \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " effectivePrivilege (m :: Mstatus) (priv :: Privilege) = (
+ if (((((get_Mstatus_MPRV m :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__0 :: 2 Word.word)))
+ else read_reg cur_privilege_ref )"
+ for m :: " Mstatus "
+ and priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val get_mstatus_SXL : Mstatus -> mword ty2\<close>\<close>
+
+definition get_mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_mstatus_SXL m = (
+ (subrange_vec_dec ((get_Mstatus_bits m :: 64 Word.word)) (( 35 :: int)::ii) (( 34 :: int)::ii) :: 2 Word.word))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val set_mstatus_SXL : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition set_mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " set_mstatus_SXL (m :: Mstatus) (a :: arch_xlen) = (
+ (let m =
+ ((update_subrange_vec_dec ((get_Mstatus_bits m :: 64 Word.word)) (( 35 :: int)::ii) (( 34 :: int)::ii) a :: 64 Word.word)) in
+ Mk_Mstatus m))"
+ for m :: " Mstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val get_mstatus_UXL : Mstatus -> mword ty2\<close>\<close>
+
+definition get_mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word " where
+ " get_mstatus_UXL m = (
+ (subrange_vec_dec ((get_Mstatus_bits m :: 64 Word.word)) (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val set_mstatus_UXL : Mstatus -> mword ty2 -> Mstatus\<close>\<close>
+
+definition set_mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where
+ " set_mstatus_UXL (m :: Mstatus) (a :: arch_xlen) = (
+ (let m =
+ ((update_subrange_vec_dec ((get_Mstatus_bits m :: 64 Word.word)) (( 33 :: int)::ii) (( 32 :: int)::ii) a :: 64 Word.word)) in
+ Mk_Mstatus m))"
+ for m :: " Mstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mstatus : Mstatus -> mword ty64 -> M Mstatus\<close>\<close>
+
+definition legalize_mstatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_mstatus (o1 :: Mstatus) (v :: xlenbits) = (
+ (let (m :: Mstatus) = (Mk_Mstatus v) in
+ (let m = (update_Mstatus_XS m ((extStatus_to_bits Off :: 2 Word.word))) in
+ or_boolM
+ (extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: ExtStatus) .
+ return (((((extStatus_to_bits w__0 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))
+ (extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)) \<bind> (\<lambda> (w__1 :: ExtStatus) .
+ return (((((extStatus_to_bits w__1 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))))) \<bind> (\<lambda> (w__2 :: bool) .
+ (let m = (update_Mstatus_SD m ((bool_to_bits w__2 :: 1 Word.word))) in
+ (let m = (set_mstatus_SXL m ((get_mstatus_SXL o1 :: 2 Word.word))) in
+ (let m = (set_mstatus_UXL m ((get_mstatus_UXL o1 :: 2 Word.word))) in
+ (let m = (update_Mstatus_UPIE m ((bool_to_bits False :: 1 Word.word))) in
+ (let m = (update_Mstatus_UIE m ((bool_to_bits False :: 1 Word.word))) in
+ return m)))))))))"
+ for o1 :: " Mstatus "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val cur_Architecture : unit -> M Architecture\<close>\<close>
+
+definition cur_Architecture :: " unit \<Rightarrow>((register_value),(Architecture),(exception))monad " where
+ " cur_Architecture _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ Machine =>
+ read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) . return ((get_Misa_MXL w__1 :: 2 Word.word)))
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . return ((get_mstatus_SXL w__2 :: 2 Word.word)))
+ | User =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) . return ((get_mstatus_UXL w__3 :: 2 Word.word)))
+ ) \<bind> (\<lambda> (a :: arch_xlen) .
+ (case ((architecture a)) of
+ Some (a) => return a
+ | None => internal_error (''Invalid current architecture'')
+ ))))"
+
+
+\<comment> \<open>\<open>val in32BitMode : unit -> M bool\<close>\<close>
+
+definition in32BitMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " in32BitMode _ = ( cur_Architecture () \<bind> (\<lambda> (w__0 :: Architecture) . return (((w__0 = RV32)))))"
+
+
+\<comment> \<open>\<open>val Mk_Minterrupts : mword ty64 -> Minterrupts\<close>\<close>
+
+definition Mk_Minterrupts :: "(64)Word.word \<Rightarrow> Minterrupts " where
+ " Mk_Minterrupts v = (
+ (| Minterrupts_Minterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_bits : Minterrupts -> mword ty64\<close>\<close>
+
+definition get_Minterrupts_bits :: " Minterrupts \<Rightarrow>(64)Word.word " where
+ " get_Minterrupts_bits v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Minterrupts_bits :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_bits :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_bits v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_MEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_SEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_SEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_SEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_SEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_SEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_UEI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_UEI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_UEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_UEI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_UEI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_UEI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_UEI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_MTI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MTI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MTI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_STI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_STI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_STI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_STI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_STI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_STI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_UTI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_UTI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_UTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_UTI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_UTI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_UTI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_UTI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_MSI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_MSI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_MSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_MSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_MSI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Minterrupts_SSI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_SSI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_SSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_SSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_SSI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Minterrupts_USI : Minterrupts -> mword ty1\<close>\<close>
+
+definition get_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word " where
+ " get_Minterrupts_USI v = (
+ (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Minterrupts_USI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Minterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Minterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts\<close>\<close>
+
+definition update_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where
+ " update_Minterrupts_USI v x = (
+ (v (|
+ Minterrupts_Minterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Minterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_USI : Uinterrupts -> mword ty1 -> Uinterrupts\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Uinterrupts_USI : Uinterrupts -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Uinterrupts_USI : register_ref regstate register_value Uinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_mip : Minterrupts -> mword ty64 -> M Minterrupts\<close>\<close>
+
+definition legalize_mip :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_mip (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let v = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))) in
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v :: 1 Word.word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v :: 1 Word.word))))
+ else m)))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mie : Minterrupts -> mword ty64 -> M Minterrupts\<close>\<close>
+
+definition legalize_mie :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_mie (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let v = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))) in
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m = (update_Minterrupts_UEI m ((get_Minterrupts_UEI v :: 1 Word.word))) in
+ (let m = (update_Minterrupts_UTI m ((get_Minterrupts_UTI v :: 1 Word.word))) in
+ update_Minterrupts_USI m ((get_Minterrupts_USI v :: 1 Word.word))))
+ else m))))))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mideleg : Minterrupts -> mword ty64 -> Minterrupts\<close>\<close>
+
+definition legalize_mideleg :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where
+ " legalize_mideleg (o1 :: Minterrupts) (v :: xlenbits) = (
+ (let m = (Mk_Minterrupts v) in
+ (let m = (update_Minterrupts_MEI m ((bool_to_bits False :: 1 Word.word))) in
+ (let m = (update_Minterrupts_MTI m ((bool_to_bits False :: 1 Word.word))) in
+ update_Minterrupts_MSI m ((bool_to_bits False :: 1 Word.word))))))"
+ for o1 :: " Minterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Medeleg : mword ty64 -> Medeleg\<close>\<close>
+
+definition Mk_Medeleg :: "(64)Word.word \<Rightarrow> Medeleg " where
+ " Mk_Medeleg v = (
+ (| Medeleg_Medeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_bits : Medeleg -> mword ty64\<close>\<close>
+
+definition get_Medeleg_bits :: " Medeleg \<Rightarrow>(64)Word.word " where
+ " get_Medeleg_bits v = ( (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Medeleg_bits :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_bits :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_bits v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Page_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Page_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Page_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_MEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_MEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_MEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_MEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_MEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_SEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Medeleg_UEnvCall : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_UEnvCall v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_UEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_UEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_UEnvCall v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_SAMO_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_SAMO_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_SAMO_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Load_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Load_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Load_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Load_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Breakpoint : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Breakpoint v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Breakpoint :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Breakpoint r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Breakpoint v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Illegal_Instr v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Illegal_Instr :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Illegal_Instr r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Illegal_Instr v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Access_Fault v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Access_Fault v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1\<close>\<close>
+
+definition get_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where
+ " get_Medeleg_Fetch_Addr_Align v = (
+ (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Medeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Medeleg_Fetch_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Medeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg\<close>\<close>
+
+definition update_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where
+ " update_Medeleg_Fetch_Addr_Align v x = (
+ (v (|
+ Medeleg_Medeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Medeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_medeleg : Medeleg -> mword ty64 -> Medeleg\<close>\<close>
+
+definition legalize_medeleg :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarrow> Medeleg " where
+ " legalize_medeleg (o1 :: Medeleg) (v :: xlenbits) = (
+ (let m = (Mk_Medeleg v) in
+ update_Medeleg_MEnvCall m ((bool_to_bits False :: 1 Word.word))))"
+ for o1 :: " Medeleg "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Mtvec : mword ty64 -> Mtvec\<close>\<close>
+
+definition Mk_Mtvec :: "(64)Word.word \<Rightarrow> Mtvec " where
+ " Mk_Mtvec v = ( (| Mtvec_Mtvec_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_bits : Mtvec -> mword ty64\<close>\<close>
+
+definition get_Mtvec_bits :: " Mtvec \<Rightarrow>(64)Word.word " where
+ " get_Mtvec_bits v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Mtvec_bits :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_bits :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_bits v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_Base : Mtvec -> mword ty62\<close>\<close>
+
+definition get_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word " where
+ " get_Mtvec_Base v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit\<close>\<close>
+
+definition set_Mtvec_Base :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(62)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_Base r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 63 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(62)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_Base v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(62)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mtvec_Mode : Mtvec -> mword ty2\<close>\<close>
+
+definition get_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word " where
+ " get_Mtvec_Mode v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Mtvec_Mode :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mtvec_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 1 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mtvec))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec\<close>\<close>
+
+definition update_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec " where
+ " update_Mtvec_Mode v x = (
+ (v (|
+ Mtvec_Mtvec_chunk_0 :=
+ ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mtvec "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_Mode : Satp32 -> mword ty1 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_Mode : Satp32 -> mword ty1\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_Mode : register_ref regstate register_value Satp32 -> mword ty1 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_tvec : Mtvec -> mword ty64 -> Mtvec\<close>\<close>
+
+definition legalize_tvec :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mtvec " where
+ " legalize_tvec (o1 :: Mtvec) (v :: xlenbits) = (
+ (let v = (Mk_Mtvec v) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v :: 2 Word.word)))) of
+ TV_Direct => v
+ | TV_Vector => v
+ | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 :: 2 Word.word))
+ )))"
+ for o1 :: " Mtvec "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Mcause : mword ty64 -> Mcause\<close>\<close>
+
+definition Mk_Mcause :: "(64)Word.word \<Rightarrow> Mcause " where
+ " Mk_Mcause v = ( (| Mcause_Mcause_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_bits : Mcause -> mword ty64\<close>\<close>
+
+definition get_Mcause_bits :: " Mcause \<Rightarrow>(64)Word.word " where
+ " get_Mcause_bits v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Mcause_bits :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause\<close>\<close>
+
+definition update_Mcause_bits :: " Mcause \<Rightarrow>(64)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_bits v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_IsInterrupt : Mcause -> mword ty1\<close>\<close>
+
+definition get_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word " where
+ " get_Mcause_IsInterrupt v = (
+ (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Mcause_IsInterrupt :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_IsInterrupt r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause\<close>\<close>
+
+definition update_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_IsInterrupt v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Mcause_Cause : Mcause -> mword ty63\<close>\<close>
+
+definition get_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word " where
+ " get_Mcause_Cause v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit\<close>\<close>
+
+definition set_Mcause_Cause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(63)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Mcause_Cause r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 62 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Mcause))register_ref "
+ and v :: "(63)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause\<close>\<close>
+
+definition update_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause " where
+ " update_Mcause_Cause v x = (
+ (v (|
+ Mcause_Mcause_chunk_0 :=
+ ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 62 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Mcause "
+ and x :: "(63)Word.word "
+
+
+\<comment> \<open>\<open>val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)\<close>\<close>
+
+definition tvec_addr :: " Mtvec \<Rightarrow> Mcause \<Rightarrow>((64)Word.word)option " where
+ " tvec_addr (m :: Mtvec) (c :: Mcause) = (
+ (let (base :: xlenbits) =
+ ((concat_vec ((get_Mtvec_Base m :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 64 Word.word)) in
+ (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m :: 2 Word.word)))) of
+ TV_Direct => Some base
+ | TV_Vector =>
+ if (((((get_Mcause_IsInterrupt c :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some ((add_vec base
+ ((shiftl ((EXTZ (( 64 :: int)::ii) ((get_Mcause_Cause c :: 63 Word.word)) :: 64 Word.word))
+ (( 2 :: int)::ii)
+ :: 64 Word.word))
+ :: 64 Word.word))
+ else Some base
+ | TV_Reserved => None
+ )))"
+ for m :: " Mtvec "
+ and c :: " Mcause "
+
+
+\<comment> \<open>\<open>val legalize_xepc : mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition legalize_xepc :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " legalize_xepc v = (
+ or_boolM (return ((sys_enable_writable_misa () )))
+ (read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) \<bind> (\<lambda> (w__1 ::
+ bool) .
+ return (if w__1 then (update_vec_dec v (( 0 :: int)::ii) B0 :: 64 Word.word)
+ else
+ (and_vec v ((EXTS (( 64 :: int)::ii) (vec_of_bits [B1,B0,B0] :: 3 Word.word) :: 64 Word.word))
+ :: 64 Word.word))))"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pc_alignment_mask : unit -> M (mword ty64)\<close>\<close>
+
+definition pc_alignment_mask :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " pc_alignment_mask _ = (
+ read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) .
+ return ((not_vec
+ ((EXTZ (( 64 :: int)::ii)
+ (if (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ (vec_of_bits [B0,B0] :: 2 Word.word)
+ else (vec_of_bits [B1,B0] :: 2 Word.word))
+ :: 64 Word.word))
+ :: 64 Word.word))))"
+
+
+\<comment> \<open>\<open>val Mk_Counteren : mword ty32 -> Counteren\<close>\<close>
+
+definition Mk_Counteren :: "(32)Word.word \<Rightarrow> Counteren " where
+ " Mk_Counteren v = (
+ (| Counteren_Counteren_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_bits : Counteren -> mword ty32\<close>\<close>
+
+definition get_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word " where
+ " get_Counteren_bits v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Counteren_bits :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren\<close>\<close>
+
+definition update_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_bits v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_HPM : Counteren -> mword ty29\<close>\<close>
+
+definition get_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word " where
+ " get_Counteren_HPM v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii) :: 29 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit\<close>\<close>
+
+definition set_Counteren_HPM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(29)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_HPM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren\<close>\<close>
+
+definition update_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_HPM v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(29)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_IR : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_IR v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_IR :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_IR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_IR v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_TM : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_TM v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_TM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_TM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_TM v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Counteren_CY : Counteren -> mword ty1\<close>\<close>
+
+definition get_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word " where
+ " get_Counteren_CY v = (
+ (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Counteren_CY :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Counteren_CY r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Counteren))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren\<close>\<close>
+
+definition update_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where
+ " update_Counteren_CY v x = (
+ (v (|
+ Counteren_Counteren_chunk_0 :=
+ ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Counteren "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_mcounteren : Counteren -> mword ty64 -> Counteren\<close>\<close>
+
+definition legalize_mcounteren :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren " where
+ " legalize_mcounteren (c :: Counteren) (v :: xlenbits) = (
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in
+ (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))"
+ for c :: " Counteren "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_scounteren : Counteren -> mword ty64 -> Counteren\<close>\<close>
+
+definition legalize_scounteren :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren " where
+ " legalize_scounteren (c :: Counteren) (v :: xlenbits) = (
+ (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in
+ (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in
+ update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))"
+ for c :: " Counteren "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val retire_instruction : unit -> M unit\<close>\<close>
+
+definition retire_instruction :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " retire_instruction _ = (
+ read_reg minstret_written_ref \<bind> (\<lambda> (w__0 :: bool) .
+ if (((w__0 = True))) then write_reg minstret_written_ref False
+ else
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg minstret_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)))))"
+
+
+\<comment> \<open>\<open>val Mk_Sstatus : mword ty64 -> Sstatus\<close>\<close>
+
+definition Mk_Sstatus :: "(64)Word.word \<Rightarrow> Sstatus " where
+ " Mk_Sstatus v = (
+ (| Sstatus_Sstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_bits : Sstatus -> mword ty64\<close>\<close>
+
+definition get_Sstatus_bits :: " Sstatus \<Rightarrow>(64)Word.word " where
+ " get_Sstatus_bits v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Sstatus_bits :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_bits :: " Sstatus \<Rightarrow>(64)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_bits v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(64)Word.word "
+
+
+definition get_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SD v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SD :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SD r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SD v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_MXR v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_MXR :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_MXR r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_MXR v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SUM v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SUM :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SUM r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SUM v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_Sstatus_XS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_XS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_XS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_XS v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(2)Word.word "
+
+
+definition get_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_Sstatus_FS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_FS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_FS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_FS v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(2)Word.word "
+
+
+definition get_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SPP v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SPP :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SPP r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SPP v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SPIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_UPIE : Sstatus -> mword ty1\<close>\<close>
+
+definition get_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_UPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sstatus_UPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_UPIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_SIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+definition set_Sstatus_SIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_SIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_SIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sstatus_UIE : Sstatus -> mword ty1\<close>\<close>
+
+definition get_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word " where
+ " get_Sstatus_UIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sstatus "
+
+
+\<comment> \<open>\<open>val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sstatus_UIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sstatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sstatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus\<close>\<close>
+
+definition update_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where
+ " update_Sstatus_UIE v x = (
+ (v (|
+ Sstatus_Sstatus_chunk_0 :=
+ ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sstatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val get_sstatus_UXL : Sstatus -> mword ty2\<close>\<close>
+
+definition get_sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word " where
+ " get_sstatus_UXL s = (
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s :: 64 Word.word))) in
+ (get_mstatus_UXL m :: 2 Word.word)))"
+ for s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val set_sstatus_UXL : Sstatus -> mword ty2 -> Sstatus\<close>\<close>
+
+definition set_sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where
+ " set_sstatus_UXL (s :: Sstatus) (a :: arch_xlen) = (
+ (let m = (Mk_Mstatus ((get_Sstatus_bits s :: 64 Word.word))) in
+ (let m = (set_mstatus_UXL m a) in
+ Mk_Sstatus ((get_Mstatus_bits m :: 64 Word.word)))))"
+ for s :: " Sstatus "
+ and a :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val lower_mstatus : Mstatus -> Sstatus\<close>\<close>
+
+definition lower_mstatus :: " Mstatus \<Rightarrow> Sstatus " where
+ " lower_mstatus m = (
+ (let s = (Mk_Sstatus ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let s = (update_Sstatus_SD s ((get_Mstatus_SD m :: 1 Word.word))) in
+ (let s = (set_sstatus_UXL s ((get_mstatus_UXL m :: 2 Word.word))) in
+ (let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m :: 1 Word.word))) in
+ (let s = (update_Sstatus_XS s ((get_Mstatus_XS m :: 2 Word.word))) in
+ (let s = (update_Sstatus_FS s ((get_Mstatus_FS m :: 2 Word.word))) in
+ (let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m :: 1 Word.word))) in
+ (let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m :: 1 Word.word))) in
+ (let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m :: 1 Word.word))) in
+ update_Sstatus_UIE s ((get_Mstatus_UIE m :: 1 Word.word))))))))))))))"
+ for m :: " Mstatus "
+
+
+\<comment> \<open>\<open>val lift_sstatus : Mstatus -> Sstatus -> M Mstatus\<close>\<close>
+
+definition lift_sstatus :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " lift_sstatus (m :: Mstatus) (s :: Sstatus) = (
+ (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s :: 1 Word.word))) in
+ (let m = (update_Mstatus_XS m ((get_Sstatus_XS s :: 2 Word.word))) in
+ (let m = (update_Mstatus_FS m ((get_Sstatus_FS s :: 2 Word.word))) in
+ or_boolM
+ (extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: ExtStatus) .
+ return (((((extStatus_to_bits w__0 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))
+ (extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)) \<bind> (\<lambda> (w__1 :: ExtStatus) .
+ return (((((extStatus_to_bits w__1 :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))))) \<bind> (\<lambda> (w__2 :: bool) .
+ (let m = (update_Mstatus_SD m ((bool_to_bits w__2 :: 1 Word.word))) in
+ (let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s :: 1 Word.word))) in
+ (let m = (update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word))) in
+ return m))))))))))))"
+ for m :: " Mstatus "
+ and s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val legalize_sstatus : Mstatus -> mword ty64 -> M Mstatus\<close>\<close>
+
+definition legalize_sstatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m ((Mk_Sstatus v)))"
+ for m :: " Mstatus "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Sedeleg : mword ty64 -> Sedeleg\<close>\<close>
+
+definition Mk_Sedeleg :: "(64)Word.word \<Rightarrow> Sedeleg " where
+ " Mk_Sedeleg v = (
+ (| Sedeleg_Sedeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sedeleg_bits : Sedeleg -> mword ty64\<close>\<close>
+
+definition get_Sedeleg_bits :: " Sedeleg \<Rightarrow>(64)Word.word " where
+ " get_Sedeleg_bits v = ( (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Sedeleg "
+
+
+\<comment> \<open>\<open>val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Sedeleg_bits :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg\<close>\<close>
+
+definition update_Sedeleg_bits :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_bits v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(64)Word.word "
+
+
+definition get_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_UEnvCall v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_UEnvCall :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_UEnvCall r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_UEnvCall v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_SAMO_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_SAMO_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_SAMO_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_SAMO_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_SAMO_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_SAMO_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Load_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Load_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Load_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Load_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Load_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Load_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Load_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Load_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Breakpoint v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Breakpoint :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Breakpoint r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Breakpoint v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Illegal_Instr v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Illegal_Instr :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Illegal_Instr r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Illegal_Instr v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Fetch_Access_Fault v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Fetch_Access_Fault r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Fetch_Access_Fault v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+definition get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where
+ " get_Sedeleg_Fetch_Addr_Align v = (
+ (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sedeleg "
+
+
+definition set_Sedeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sedeleg_Fetch_Addr_Align r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sedeleg))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where
+ " update_Sedeleg_Fetch_Addr_Align v x = (
+ (v (|
+ Sedeleg_Sedeleg_chunk_0 :=
+ ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sedeleg "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg\<close>\<close>
+
+definition legalize_sedeleg :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarrow> Sedeleg " where
+ " legalize_sedeleg (s :: Sedeleg) (v :: xlenbits) = (
+ Mk_Sedeleg ((EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word)) :: 64 Word.word)))"
+ for s :: " Sedeleg "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Sinterrupts : mword ty64 -> Sinterrupts\<close>\<close>
+
+definition Mk_Sinterrupts :: "(64)Word.word \<Rightarrow> Sinterrupts " where
+ " Mk_Sinterrupts v = (
+ (| Sinterrupts_Sinterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_bits : Sinterrupts -> mword ty64\<close>\<close>
+
+definition get_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(64)Word.word " where
+ " get_Sinterrupts_bits v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_bits :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_bits v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(64)Word.word "
+
+
+definition get_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_SEI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_SEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_SEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_SEI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_UEI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_UEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_UEI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_STI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_STI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_STI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_STI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_UTI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_UTI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_UTI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_SSI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+definition set_Sinterrupts_SSI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_SSI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_SSI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Sinterrupts_USI : Sinterrupts -> mword ty1\<close>\<close>
+
+definition get_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Sinterrupts_USI v = (
+ (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Sinterrupts_USI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Sinterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Sinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts\<close>\<close>
+
+definition update_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where
+ " update_Sinterrupts_USI v x = (
+ (v (|
+ Sinterrupts_Sinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Sinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts\<close>\<close>
+
+definition lower_mip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where
+ " lower_mip (m :: Minterrupts) (d :: Minterrupts) = (
+ (let (s :: Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word)))))))))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts\<close>\<close>
+
+definition lower_mie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where
+ " lower_mie (m :: Minterrupts) (d :: Minterrupts) = (
+ (let (s :: Sinterrupts) =
+ (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SEI s
+ ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_STI s
+ ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_SSI s
+ ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UEI s
+ ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let s =
+ (update_Sinterrupts_UTI s
+ ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Sinterrupts_USI s
+ ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word)))))))))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts\<close>\<close>
+
+definition lift_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " lift_sip (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = (
+ (let (m :: Minterrupts) = o1 in
+ (let m =
+ (update_Minterrupts_SSI m
+ ((and_vec ((get_Sinterrupts_SSI s :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ haveNExt () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m =
+ (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word))
+ else m) in
+ if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word))
+ else m)
+ else m)))))"
+ for o1 :: " Minterrupts "
+ and d :: " Minterrupts "
+ and s :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_sip : Minterrupts -> Minterrupts -> mword ty64 -> M Minterrupts\<close>\<close>
+
+definition legalize_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
+ lift_sip m d ((Mk_Sinterrupts v)))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> M Minterrupts\<close>\<close>
+
+definition lift_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " lift_sie (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = (
+ (let (m :: Minterrupts) = o1 in
+ (let m =
+ (if (((((get_Minterrupts_SEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_SEI m ((get_Sinterrupts_SEI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_STI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_STI m ((get_Sinterrupts_STI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_SSI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_SSI m ((get_Sinterrupts_SSI s :: 1 Word.word))
+ else m) in
+ haveNExt () \<bind> (\<lambda> (w__0 :: bool) .
+ return (if w__0 then
+ (let m =
+ (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word))
+ else m) in
+ (let m =
+ (if (((((get_Minterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Minterrupts_UTI m ((get_Sinterrupts_UTI s :: 1 Word.word))
+ else m) in
+ if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word))
+ else m))
+ else m)))))))"
+ for o1 :: " Minterrupts "
+ and d :: " Minterrupts "
+ and s :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_sie : Minterrupts -> Minterrupts -> mword ty64 -> M Minterrupts\<close>\<close>
+
+definition legalize_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Minterrupts),(exception))monad " where
+ " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = (
+ lift_sie m d ((Mk_Sinterrupts v)))"
+ for m :: " Minterrupts "
+ and d :: " Minterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Satp64 : mword ty64 -> Satp64\<close>\<close>
+
+definition Mk_Satp64 :: "(64)Word.word \<Rightarrow> Satp64 " where
+ " Mk_Satp64 v = ( (| Satp64_Satp64_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_bits : Satp64 -> mword ty64\<close>\<close>
+
+definition get_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word " where
+ " get_Satp64_bits v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Satp64_bits :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64\<close>\<close>
+
+definition update_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_bits v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_Mode : Satp64 -> mword ty4\<close>\<close>
+
+definition get_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word " where
+ " get_Satp64_Mode v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit\<close>\<close>
+
+definition set_Satp64_Mode :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 60 :: int)::ii)
+ ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64\<close>\<close>
+
+definition update_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_Mode v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii)
+ ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp64_Asid : Satp64 -> mword ty16\<close>\<close>
+
+definition get_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word " where
+ " get_Satp64_Asid v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit\<close>\<close>
+
+definition set_Satp64_Asid :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_Asid r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 59 :: int)::ii) (( 44 :: int)::ii)
+ ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64\<close>\<close>
+
+definition update_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_Asid v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii)
+ ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_Asid : Satp32 -> mword ty9 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_Asid : Satp32 -> mword ty9\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_Asid : register_ref regstate register_value Satp32 -> mword ty9 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp64_PPN : Satp64 -> mword ty44\<close>\<close>
+
+definition get_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word " where
+ " get_Satp64_PPN v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))"
+ for v :: " Satp64 "
+
+
+\<comment> \<open>\<open>val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit\<close>\<close>
+
+definition set_Satp64_PPN :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp64_PPN r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 43 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp64))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64\<close>\<close>
+
+definition update_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 " where
+ " update_Satp64_PPN v x = (
+ (v (|
+ Satp64_Satp64_chunk_0 :=
+ ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Satp64 "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_PPN : Satp32 -> mword ty22 -> Satp32\<close>\<close>
+
+\<comment> \<open>\<open>val _get_Satp32_PPN : Satp32 -> mword ty22\<close>\<close>
+
+\<comment> \<open>\<open>val _set_Satp32_PPN : register_ref regstate register_value Satp32 -> mword ty22 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val legalize_satp64 : Architecture -> mword ty64 -> mword ty64 -> mword ty64\<close>\<close>
+
+definition legalize_satp64 :: " Architecture \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word " where
+ " legalize_satp64 (a :: Architecture) (o1 :: 64 bits) (v :: 64 bits) = (
+ (let s = (Mk_Satp64 v) in
+ (case ((satp64Mode_of_bits a ((get_Satp64_Mode s :: 4 Word.word)))) of
+ None => o1
+ | Some (Sv32) => o1
+ | Some (_) => (get_Satp64_bits s :: 64 Word.word)
+ )))"
+ for a :: " Architecture "
+ and o1 :: "(64)Word.word "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Satp32 : mword ty32 -> Satp32\<close>\<close>
+
+definition Mk_Satp32 :: "(32)Word.word \<Rightarrow> Satp32 " where
+ " Mk_Satp32 v = ( (| Satp32_Satp32_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Satp32_bits : Satp32 -> mword ty32\<close>\<close>
+
+definition get_Satp32_bits :: " Satp32 \<Rightarrow>(32)Word.word " where
+ " get_Satp32_bits v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " Satp32 "
+
+
+\<comment> \<open>\<open>val _set_Satp32_bits : register_ref regstate register_value Satp32 -> mword ty32 -> M unit\<close>\<close>
+
+definition set_Satp32_bits :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Satp32_bits : Satp32 -> mword ty32 -> Satp32\<close>\<close>
+
+definition update_Satp32_bits :: " Satp32 \<Rightarrow>(32)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_bits v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(32)Word.word "
+
+
+definition get_Satp32_Mode :: " Satp32 \<Rightarrow>(1)Word.word " where
+ " get_Satp32_Mode v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_Mode :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_Mode r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Satp32_Mode :: " Satp32 \<Rightarrow>(1)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_Mode v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(1)Word.word "
+
+
+definition get_Satp32_Asid :: " Satp32 \<Rightarrow>(9)Word.word " where
+ " get_Satp32_Asid v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 30 :: int)::ii) (( 22 :: int)::ii) :: 9 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_Asid :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(9)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_Asid r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 30 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(9)Word.word "
+
+
+definition update_Satp32_Asid :: " Satp32 \<Rightarrow>(9)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_Asid v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 30 :: int)::ii) (( 22 :: int)::ii)
+ ((subrange_vec_dec x (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(9)Word.word "
+
+
+definition get_Satp32_PPN :: " Satp32 \<Rightarrow>(22)Word.word " where
+ " get_Satp32_PPN v = ( (subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))"
+ for v :: " Satp32 "
+
+
+definition set_Satp32_PPN :: "((regstate),(register_value),(Satp32))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Satp32_PPN r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 r) (( 21 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Satp32))register_ref "
+ and v :: "(22)Word.word "
+
+
+definition update_Satp32_PPN :: " Satp32 \<Rightarrow>(22)Word.word \<Rightarrow> Satp32 " where
+ " update_Satp32_PPN v x = (
+ (v (|
+ Satp32_Satp32_chunk_0 :=
+ ((update_subrange_vec_dec(Satp32_Satp32_chunk_0 v) (( 21 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " Satp32 "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val legalize_satp32 : Architecture -> mword ty32 -> mword ty32 -> mword ty32\<close>\<close>
+
+definition legalize_satp32 :: " Architecture \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>(32)Word.word " where
+ " legalize_satp32 (a :: Architecture) (o1 :: 32 bits) (v :: 32 bits) = ( v )"
+ for a :: " Architecture "
+ and o1 :: "(32)Word.word "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val PmpAddrMatchType_of_num : integer -> PmpAddrMatchType\<close>\<close>
+
+definition PmpAddrMatchType_of_num :: " int \<Rightarrow> PmpAddrMatchType " where
+ " PmpAddrMatchType_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then OFF
+ else if (((p00 = (( 1 :: int)::ii)))) then TOR
+ else if (((p00 = (( 2 :: int)::ii)))) then NA4
+ else NAPOT))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_PmpAddrMatchType : PmpAddrMatchType -> integer\<close>\<close>
+
+fun num_of_PmpAddrMatchType :: " PmpAddrMatchType \<Rightarrow> int " where
+ " num_of_PmpAddrMatchType OFF = ( (( 0 :: int)::ii))"
+|" num_of_PmpAddrMatchType TOR = ( (( 1 :: int)::ii))"
+|" num_of_PmpAddrMatchType NA4 = ( (( 2 :: int)::ii))"
+|" num_of_PmpAddrMatchType NAPOT = ( (( 3 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpAddrMatchType_of_bits : mword ty2 -> M PmpAddrMatchType\<close>\<close>
+
+definition pmpAddrMatchType_of_bits :: "(2)Word.word \<Rightarrow>((register_value),(PmpAddrMatchType),(exception))monad " where
+ " pmpAddrMatchType_of_bits bs = (
+ (let b__0 = bs in
+ if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return OFF
+ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return TOR
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return NA4
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return NAPOT
+ else assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 7:2 - 12:3'') \<then> exit0 () ))"
+ for bs :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val pmpAddrMatchType_to_bits : PmpAddrMatchType -> mword ty2\<close>\<close>
+
+fun pmpAddrMatchType_to_bits :: " PmpAddrMatchType \<Rightarrow>(2)Word.word " where
+ " pmpAddrMatchType_to_bits OFF = ( (vec_of_bits [B0,B0] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits TOR = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits NA4 = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" pmpAddrMatchType_to_bits NAPOT = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val Mk_Pmpcfg_ent : mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition Mk_Pmpcfg_ent :: "(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " Mk_Pmpcfg_ent v = (
+ (| Pmpcfg_ent_Pmpcfg_ent_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) |) )"
+ for v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8\<close>\<close>
+
+definition get_Pmpcfg_ent_bits :: " Pmpcfg_ent \<Rightarrow>(8)Word.word " where
+ " get_Pmpcfg_ent_bits v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_bits : register_ref regstate register_value Pmpcfg_ent -> mword ty8 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_bits :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_bits : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_bits :: " Pmpcfg_ent \<Rightarrow>(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_bits v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(8)Word.word "
+
+
+definition get_Pmpcfg_ent_L :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_L v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+definition set_Pmpcfg_ent_L :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_L r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Pmpcfg_ent_L :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_L v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2\<close>\<close>
+
+definition get_Pmpcfg_ent_A :: " Pmpcfg_ent \<Rightarrow>(2)Word.word " where
+ " get_Pmpcfg_ent_A v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_A : register_ref regstate register_value Pmpcfg_ent -> mword ty2 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_A :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 4 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_A : Pmpcfg_ent -> mword ty2 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_A :: " Pmpcfg_ent \<Rightarrow>(2)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_A v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_X :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_X v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_X : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_X :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_X : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_X :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_X v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_W :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_W v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_W : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_W :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_W : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_W :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_W v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1\<close>\<close>
+
+definition get_Pmpcfg_ent_R :: " Pmpcfg_ent \<Rightarrow>(1)Word.word " where
+ " get_Pmpcfg_ent_R v = (
+ (subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val _set_Pmpcfg_ent_R : register_ref regstate register_value Pmpcfg_ent -> mword ty1 -> M unit\<close>\<close>
+
+definition set_Pmpcfg_ent_R :: "((regstate),(register_value),(Pmpcfg_ent))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Pmpcfg_ent_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref "
+ and v :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Pmpcfg_ent_R : Pmpcfg_ent -> mword ty1 -> Pmpcfg_ent\<close>\<close>
+
+definition update_Pmpcfg_ent_R :: " Pmpcfg_ent \<Rightarrow>(1)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " update_Pmpcfg_ent_R v x = (
+ (v (|
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 :=
+ ((update_subrange_vec_dec(Pmpcfg_ent_Pmpcfg_ent_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " Pmpcfg_ent "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val pmpReadCfgReg : integer -> M (mword ty64)\<close>\<close>
+
+definition pmpReadCfgReg :: " int \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " pmpReadCfgReg n = (
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__0 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__1 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__2 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__3 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__4 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__5 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__6 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__7 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))
+ :: 40 Word.word))
+ :: 48 Word.word))
+ :: 56 Word.word))
+ :: 64 Word.word))))))))))
+ else if (((p00 = (( 2 :: int)::ii)))) then
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ return ((concat_vec ((get_Pmpcfg_ent_bits w__8 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__9 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__10 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__11 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__12 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__13 :: 8 Word.word))
+ ((concat_vec ((get_Pmpcfg_ent_bits w__14 :: 8 Word.word))
+ ((get_Pmpcfg_ent_bits w__15 :: 8 Word.word))
+ :: 16 Word.word))
+ :: 24 Word.word))
+ :: 32 Word.word))
+ :: 40 Word.word))
+ :: 48 Word.word))
+ :: 56 Word.word))
+ :: 64 Word.word))))))))))
+ else assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 75:2 - 85:8'') \<then> exit0 () ))"
+ for n :: " int "
+
+
+\<comment> \<open>\<open>val pmpWriteCfg : Pmpcfg_ent -> mword ty8 -> Pmpcfg_ent\<close>\<close>
+
+definition pmpWriteCfg :: " Pmpcfg_ent \<Rightarrow>(8)Word.word \<Rightarrow> Pmpcfg_ent " where
+ " pmpWriteCfg (cfg :: Pmpcfg_ent) (v :: 8 bits) = (
+ if (((((get_Pmpcfg_ent_L cfg :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then cfg
+ else Mk_Pmpcfg_ent v )"
+ for cfg :: " Pmpcfg_ent "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val pmpWriteCfgReg : integer -> mword ty64 -> M unit\<close>\<close>
+
+definition pmpWriteCfgReg :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " pmpWriteCfgReg n v = (
+ (let p00 = n in
+ if (((p00 = (( 0 :: int)::ii)))) then
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (write_reg pmp0cfg_ref ((pmpWriteCfg w__0 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp1cfg_ref) \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ (write_reg pmp1cfg_ref ((pmpWriteCfg w__1 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp2cfg_ref) \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ (write_reg pmp2cfg_ref ((pmpWriteCfg w__2 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp3cfg_ref) \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ (write_reg pmp3cfg_ref ((pmpWriteCfg w__3 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp4cfg_ref) \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ (write_reg pmp4cfg_ref ((pmpWriteCfg w__4 ((subrange_vec_dec v (( 39 :: int)::ii) (( 32 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp5cfg_ref) \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ (write_reg pmp5cfg_ref ((pmpWriteCfg w__5 ((subrange_vec_dec v (( 47 :: int)::ii) (( 40 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp6cfg_ref) \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ (write_reg pmp6cfg_ref ((pmpWriteCfg w__6 ((subrange_vec_dec v (( 55 :: int)::ii) (( 48 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp7cfg_ref) \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ write_reg pmp7cfg_ref ((pmpWriteCfg w__7 ((subrange_vec_dec v (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))))))))))))
+ else if (((p00 = (( 2 :: int)::ii)))) then
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ (let pmp8cfg8 = (pmpWriteCfg w__8 ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))) in
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ (let pmp9cfg9 = (pmpWriteCfg w__9 ((subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) in
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ (write_reg
+ pmp10cfg_ref
+ ((pmpWriteCfg w__10 ((subrange_vec_dec v (( 23 :: int)::ii) (( 16 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp11cfg_ref) \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ (write_reg
+ pmp11cfg_ref
+ ((pmpWriteCfg w__11 ((subrange_vec_dec v (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp12cfg_ref) \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ (write_reg
+ pmp12cfg_ref
+ ((pmpWriteCfg w__12 ((subrange_vec_dec v (( 39 :: int)::ii) (( 32 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp13cfg_ref) \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ (write_reg
+ pmp13cfg_ref
+ ((pmpWriteCfg w__13 ((subrange_vec_dec v (( 47 :: int)::ii) (( 40 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp14cfg_ref) \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ (write_reg
+ pmp14cfg_ref
+ ((pmpWriteCfg w__14 ((subrange_vec_dec v (( 55 :: int)::ii) (( 48 :: int)::ii) :: 8 Word.word)))) \<then>
+ read_reg pmp15cfg_ref) \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ write_reg
+ pmp15cfg_ref
+ ((pmpWriteCfg w__15 ((subrange_vec_dec v (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))))))))))))))
+ else
+ assert_exp False (''Pattern match failure at model/riscv_pmp_regs.sail 94:2 - 137:8'') \<then> exit0 () ))"
+ for n :: " int "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pmpWriteAddr : Pmpcfg_ent -> mword ty64 -> mword ty64 -> mword ty64\<close>\<close>
+
+definition pmpWriteAddr :: " Pmpcfg_ent \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word " where
+ " pmpWriteAddr (cfg :: Pmpcfg_ent) (reg :: xlenbits) (v :: xlenbits) = (
+ if (((((get_Pmpcfg_ent_L cfg :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then reg
+ else (EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 53 :: int)::ii) (( 0 :: int)::ii) :: 54 Word.word)) :: 64 Word.word))"
+ for cfg :: " Pmpcfg_ent "
+ and reg :: "(64)Word.word "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pmpAddrRange : Pmpcfg_ent -> mword ty64 -> mword ty64 -> M (maybe ((mword ty64 * mword ty64)))\<close>\<close>
+
+definition pmpAddrRange :: " Pmpcfg_ent \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(((64)Word.word*(64)Word.word)option),(exception))monad " where
+ " pmpAddrRange (cfg :: Pmpcfg_ent) (pmpaddr :: xlenbits) (prev_pmpaddr :: xlenbits) = (
+ pmpAddrMatchType_of_bits ((get_Pmpcfg_ent_A cfg :: 2 Word.word)) \<bind> (\<lambda> (w__0 :: PmpAddrMatchType) .
+ return ((case w__0 of
+ OFF => None
+ | TOR => Some ((shiftl prev_pmpaddr (( 2 :: int)::ii) :: 64 Word.word), (shiftl pmpaddr (( 2 :: int)::ii) :: 64 Word.word))
+ | NA4 =>
+ (let lo = ((shiftl pmpaddr (( 2 :: int)::ii) :: 64 Word.word)) in
+ Some (lo, (add_vec_int lo (( 4 :: int)::ii) :: 64 Word.word)))
+ | NAPOT =>
+ (let mask1 = ((xor_vec pmpaddr ((add_vec_int pmpaddr (( 1 :: int)::ii) :: 64 Word.word)) :: 64 Word.word)) in
+ (let lo = ((and_vec pmpaddr ((not_vec mask1 :: 64 Word.word)) :: 64 Word.word)) in
+ (let len = ((add_vec_int mask1 (( 1 :: int)::ii) :: 64 Word.word)) in
+ Some ((shiftl lo (( 2 :: int)::ii) :: 64 Word.word),
+ (shiftl ((add_vec lo len :: 64 Word.word)) (( 2 :: int)::ii) :: 64 Word.word)))))
+ ))))"
+ for cfg :: " Pmpcfg_ent "
+ and pmpaddr :: "(64)Word.word "
+ and prev_pmpaddr :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pmpCheckRWX : Pmpcfg_ent -> AccessType -> bool\<close>\<close>
+
+fun pmpCheckRWX :: " Pmpcfg_ent \<Rightarrow> AccessType \<Rightarrow> bool " where
+ " pmpCheckRWX ent Read = ( (((get_Pmpcfg_ent_R ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent Write = ( (((get_Pmpcfg_ent_W ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent ReadWrite = (
+ ((((((get_Pmpcfg_ent_R ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_Pmpcfg_ent_W ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))"
+ for ent :: " Pmpcfg_ent "
+|" pmpCheckRWX ent Execute = ( (((get_Pmpcfg_ent_X ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))"
+ for ent :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val pmpCheckPerms : Pmpcfg_ent -> AccessType -> Privilege -> bool\<close>\<close>
+
+fun pmpCheckPerms :: " Pmpcfg_ent \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool " where
+ " pmpCheckPerms ent acc1 Machine = (
+ if (((((get_Pmpcfg_ent_L ent :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ pmpCheckRWX ent acc1
+ else True )"
+ for ent :: " Pmpcfg_ent "
+ and acc1 :: " AccessType "
+|" pmpCheckPerms ent acc1 _ = ( pmpCheckRWX ent acc1 )"
+ for ent :: " Pmpcfg_ent "
+ and acc1 :: " AccessType "
+
+
+\<comment> \<open>\<open>val pmpAddrMatch_of_num : integer -> pmpAddrMatch\<close>\<close>
+
+definition pmpAddrMatch_of_num :: " int \<Rightarrow> pmpAddrMatch " where
+ " pmpAddrMatch_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PMP_NoMatch
+ else if (((p00 = (( 1 :: int)::ii)))) then PMP_PartialMatch
+ else PMP_Match))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_pmpAddrMatch : pmpAddrMatch -> integer\<close>\<close>
+
+fun num_of_pmpAddrMatch :: " pmpAddrMatch \<Rightarrow> int " where
+ " num_of_pmpAddrMatch PMP_NoMatch = ( (( 0 :: int)::ii))"
+|" num_of_pmpAddrMatch PMP_PartialMatch = ( (( 1 :: int)::ii))"
+|" num_of_pmpAddrMatch PMP_Match = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpMatchAddr : mword ty64 -> mword ty64 -> maybe ((mword ty64 * mword ty64)) -> pmpAddrMatch\<close>\<close>
+
+fun pmpMatchAddr :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(xlenbits*xlenbits)option \<Rightarrow> pmpAddrMatch " where
+ " pmpMatchAddr (addr :: xlenbits) (width :: xlenbits) (None :: pmp_addr_range) = ( PMP_NoMatch )"
+ for addr :: "(64)Word.word "
+ and width :: "(64)Word.word "
+|" pmpMatchAddr (addr :: xlenbits) (width :: xlenbits) ((Some ((lo, hi))) :: pmp_addr_range) = (
+ if ((zopz0zI_u hi lo)) then PMP_NoMatch
+ else if (((((zopz0zI_u ((add_vec addr width :: 64 Word.word)) lo)) \<or> ((zopz0zI_u hi addr)))))
+ then
+ PMP_NoMatch
+ else if (((((zopz0zIzJ_u lo addr)) \<and> ((zopz0zIzJ_u ((add_vec addr width :: 64 Word.word)) hi))))) then
+ PMP_Match
+ else PMP_PartialMatch )"
+ for addr :: "(64)Word.word "
+ and width :: "(64)Word.word "
+ and hi :: "(64)Word.word "
+ and lo :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pmpMatch_of_num : integer -> pmpMatch\<close>\<close>
+
+definition pmpMatch_of_num :: " int \<Rightarrow> pmpMatch " where
+ " pmpMatch_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PMP_Success
+ else if (((p00 = (( 1 :: int)::ii)))) then PMP_Continue
+ else PMP_Fail))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_pmpMatch : pmpMatch -> integer\<close>\<close>
+
+fun num_of_pmpMatch :: " pmpMatch \<Rightarrow> int " where
+ " num_of_pmpMatch PMP_Success = ( (( 0 :: int)::ii))"
+|" num_of_pmpMatch PMP_Continue = ( (( 1 :: int)::ii))"
+|" num_of_pmpMatch PMP_Fail = ( (( 2 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val pmpMatchEntry : mword ty64 -> mword ty64 -> AccessType -> Privilege -> Pmpcfg_ent -> mword ty64 -> mword ty64 -> M pmpMatch\<close>\<close>
+
+definition pmpMatchEntry :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> Pmpcfg_ent \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(pmpMatch),(exception))monad " where
+ " pmpMatchEntry (addr :: xlenbits) (width :: xlenbits) (acc1 :: AccessType) (priv :: Privilege) (ent ::
+ Pmpcfg_ent) (pmpaddr :: xlenbits) (prev_pmpaddr :: xlenbits) = (
+ (pmpAddrRange ent pmpaddr prev_pmpaddr :: ( (( 64 Word.word * 64 Word.word))option) M) \<bind> (\<lambda> rng .
+ return ((case ((pmpMatchAddr addr width rng)) of
+ PMP_NoMatch => PMP_Continue
+ | PMP_PartialMatch => PMP_Fail
+ | PMP_Match => if ((pmpCheckPerms ent acc1 priv)) then PMP_Success else PMP_Fail
+ ))))"
+ for addr :: "(64)Word.word "
+ and width :: "(64)Word.word "
+ and acc1 :: " AccessType "
+ and priv :: " Privilege "
+ and ent :: " Pmpcfg_ent "
+ and pmpaddr :: "(64)Word.word "
+ and prev_pmpaddr :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val pmpCheck : mword ty64 -> integer -> AccessType -> Privilege -> M (maybe ExceptionType)\<close>\<close>
+
+definition pmpCheck :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow>((register_value),((ExceptionType)option),(exception))monad " where
+ " pmpCheck (addr :: xlenbits) (width :: int) (acc1 :: AccessType) (priv :: Privilege) = (
+ (let (width :: xlenbits) = ((to_bits (( 64 :: int)::ii) width :: 64 Word.word)) in
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (read_reg pmpaddr0_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__0 w__1 ((zeros_implicit (( 64 :: int)::ii) :: 64 Word.word)) \<bind> (\<lambda> (w__2 ::
+ pmpMatch) .
+ (case w__2 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ (read_reg pmpaddr1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) .
+ (read_reg pmpaddr0_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__3 w__4 w__5 \<bind> (\<lambda> (w__6 :: pmpMatch) .
+ (case w__6 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ (read_reg pmpaddr2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) .
+ (read_reg pmpaddr1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__7 w__8 w__9 \<bind> (\<lambda> (w__10 :: pmpMatch) .
+ (case w__10 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ (read_reg pmpaddr3_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ (read_reg pmpaddr2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__11 w__12 w__13 \<bind> (\<lambda> (w__14 :: pmpMatch) .
+ (case w__14 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ (read_reg pmpaddr4_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: 64 Word.word) .
+ (read_reg pmpaddr3_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__15 w__16 w__17 \<bind> (\<lambda> (w__18 :: pmpMatch) .
+ (case w__18 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__19 :: Pmpcfg_ent) .
+ (read_reg pmpaddr5_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__20 :: 64 Word.word) .
+ (read_reg pmpaddr4_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__21 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__19 w__20 w__21 \<bind> (\<lambda> (w__22 :: pmpMatch) .
+ (case w__22 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__23 :: Pmpcfg_ent) .
+ (read_reg pmpaddr6_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 Word.word) .
+ (read_reg pmpaddr5_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__25 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__23 w__24 w__25 \<bind> (\<lambda> (w__26 :: pmpMatch) .
+ (case w__26 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__27 :: Pmpcfg_ent) .
+ (read_reg pmpaddr7_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 Word.word) .
+ (read_reg pmpaddr6_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__29 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__27 w__28 w__29 \<bind> (\<lambda> (w__30 ::
+ pmpMatch) .
+ (case w__30 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__31 :: Pmpcfg_ent) .
+ (read_reg pmpaddr8_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__32 :: 64 Word.word) .
+ (read_reg pmpaddr7_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__33 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__31 w__32 w__33 \<bind> (\<lambda> (w__34 ::
+ pmpMatch) .
+ (case w__34 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__35 :: Pmpcfg_ent) .
+ (read_reg pmpaddr9_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 :: 64 Word.word) .
+ (read_reg pmpaddr8_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__35 w__36 w__37 \<bind> (\<lambda> (w__38 ::
+ pmpMatch) .
+ (case w__38 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__39 :: Pmpcfg_ent) .
+ (read_reg pmpaddr10_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__40 ::
+ 64 Word.word) .
+ (read_reg pmpaddr9_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__41 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__39 w__40 w__41 \<bind> (\<lambda> (w__42 ::
+ pmpMatch) .
+ (case w__42 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__43 :: Pmpcfg_ent) .
+ (read_reg pmpaddr11_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__44 ::
+ 64 Word.word) .
+ (read_reg pmpaddr10_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__45 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__43 w__44 w__45 \<bind> (\<lambda> (w__46 ::
+ pmpMatch) .
+ (case w__46 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__47 :: Pmpcfg_ent) .
+ (read_reg pmpaddr12_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__48 ::
+ 64 Word.word) .
+ (read_reg pmpaddr11_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__49 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__47 w__48 w__49 \<bind> (\<lambda> (w__50 ::
+ pmpMatch) .
+ (case w__50 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__51 :: Pmpcfg_ent) .
+ (read_reg pmpaddr13_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__52 ::
+ 64 Word.word) .
+ (read_reg pmpaddr12_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__53 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__51 w__52 w__53 \<bind> (\<lambda> (w__54 ::
+ pmpMatch) .
+ (case w__54 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__55 :: Pmpcfg_ent) .
+ (read_reg pmpaddr14_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__56 ::
+ 64 Word.word) .
+ (read_reg pmpaddr13_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__57 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__55 w__56 w__57 \<bind> (\<lambda> (w__58 ::
+ pmpMatch) .
+ (case w__58 of
+ PMP_Success => return True
+ | PMP_Fail => return False
+ | PMP_Continue =>
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__59 :: Pmpcfg_ent) .
+ (read_reg pmpaddr15_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 ::
+ 64 Word.word) .
+ (read_reg pmpaddr14_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__61 ::
+ 64 Word.word) .
+ pmpMatchEntry addr width acc1 priv w__59 w__60 w__61 \<bind> (\<lambda> (w__62 ::
+ pmpMatch) .
+ return ((case w__62 of
+ PMP_Success => True
+ | PMP_Fail => False
+ | PMP_Continue =>
+ (case priv of
+ Machine => True
+ | _ => False
+ )
+ ))))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ )))))
+ ) \<bind> (\<lambda> (check' :: bool) .
+ return (if check' then None
+ else
+ (case acc1 of
+ Read => Some E_Load_Access_Fault
+ | Write => Some E_SAMO_Access_Fault
+ | ReadWrite => Some E_SAMO_Access_Fault
+ | Execute => Some E_Fetch_Access_Fault
+ ))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and acc1 :: " AccessType "
+ and priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val init_pmp : unit -> M unit\<close>\<close>
+
+definition init_pmp :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_pmp _ = (
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__0 :: Pmpcfg_ent) .
+ (write_reg pmp0cfg_ref ((update_Pmpcfg_ent_A w__0 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp1cfg_ref) \<bind> (\<lambda> (w__1 :: Pmpcfg_ent) .
+ (write_reg pmp1cfg_ref ((update_Pmpcfg_ent_A w__1 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp2cfg_ref) \<bind> (\<lambda> (w__2 :: Pmpcfg_ent) .
+ (write_reg pmp2cfg_ref ((update_Pmpcfg_ent_A w__2 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp3cfg_ref) \<bind> (\<lambda> (w__3 :: Pmpcfg_ent) .
+ (write_reg pmp3cfg_ref ((update_Pmpcfg_ent_A w__3 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp4cfg_ref) \<bind> (\<lambda> (w__4 :: Pmpcfg_ent) .
+ (write_reg pmp4cfg_ref ((update_Pmpcfg_ent_A w__4 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp5cfg_ref) \<bind> (\<lambda> (w__5 :: Pmpcfg_ent) .
+ (write_reg pmp5cfg_ref ((update_Pmpcfg_ent_A w__5 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp6cfg_ref) \<bind> (\<lambda> (w__6 :: Pmpcfg_ent) .
+ (write_reg pmp6cfg_ref ((update_Pmpcfg_ent_A w__6 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp7cfg_ref) \<bind> (\<lambda> (w__7 :: Pmpcfg_ent) .
+ (write_reg pmp7cfg_ref ((update_Pmpcfg_ent_A w__7 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp8cfg_ref) \<bind> (\<lambda> (w__8 :: Pmpcfg_ent) .
+ (write_reg pmp8cfg_ref ((update_Pmpcfg_ent_A w__8 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp9cfg_ref) \<bind> (\<lambda> (w__9 :: Pmpcfg_ent) .
+ (write_reg pmp9cfg_ref ((update_Pmpcfg_ent_A w__9 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp10cfg_ref) \<bind> (\<lambda> (w__10 :: Pmpcfg_ent) .
+ (write_reg
+ pmp10cfg_ref
+ ((update_Pmpcfg_ent_A w__10 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp11cfg_ref) \<bind> (\<lambda> (w__11 :: Pmpcfg_ent) .
+ (write_reg
+ pmp11cfg_ref
+ ((update_Pmpcfg_ent_A w__11 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp12cfg_ref) \<bind> (\<lambda> (w__12 :: Pmpcfg_ent) .
+ (write_reg
+ pmp12cfg_ref
+ ((update_Pmpcfg_ent_A w__12 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp13cfg_ref) \<bind> (\<lambda> (w__13 :: Pmpcfg_ent) .
+ (write_reg
+ pmp13cfg_ref
+ ((update_Pmpcfg_ent_A w__13 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp14cfg_ref) \<bind> (\<lambda> (w__14 :: Pmpcfg_ent) .
+ (write_reg
+ pmp14cfg_ref
+ ((update_Pmpcfg_ent_A w__14 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))) \<then>
+ read_reg pmp15cfg_ref) \<bind> (\<lambda> (w__15 :: Pmpcfg_ent) .
+ write_reg
+ pmp15cfg_ref
+ ((update_Pmpcfg_ent_A w__15 ((pmpAddrMatchType_to_bits OFF :: 2 Word.word)))))))))))))))))))))"
+
+
+\<comment> \<open>\<open>val ext_init_regs : unit -> M unit\<close>\<close>
+
+definition ext_init_regs :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ext_init_regs _ = ( return () )"
+
+
+\<comment> \<open>\<open>
+This function is called after above when running rvfi and allows the model
+to be initialised differently (e.g. CHERI cap regs are initialised
+to omnipotent instead of null).
+ \<close>\<close>
+\<comment> \<open>\<open>val ext_rvfi_init : unit -> M unit\<close>\<close>
+
+definition ext_rvfi_init :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " ext_rvfi_init _ = ( return () )"
+
+
+\<comment> \<open>\<open>val ext_fetch_check_pc : mword ty64 -> mword ty64 -> Ext_FetchAddr_Check unit\<close>\<close>
+
+definition ext_fetch_check_pc :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(unit)Ext_FetchAddr_Check " where
+ " ext_fetch_check_pc (start_pc :: xlenbits) (pc :: xlenbits) = ( Ext_FetchAddr_OK pc )"
+ for start_pc :: "(64)Word.word "
+ and pc :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val ext_handle_fetch_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_fetch_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_fetch_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val ext_control_check_addr : mword ty64 -> Ext_ControlAddr_Check unit\<close>\<close>
+
+definition ext_control_check_addr :: "(64)Word.word \<Rightarrow>(unit)Ext_ControlAddr_Check " where
+ " ext_control_check_addr pc = ( Ext_ControlAddr_OK pc )"
+ for pc :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val ext_control_check_pc : mword ty64 -> Ext_ControlAddr_Check unit\<close>\<close>
+
+definition ext_control_check_pc :: "(64)Word.word \<Rightarrow>(unit)Ext_ControlAddr_Check " where
+ " ext_control_check_pc pc = ( Ext_ControlAddr_OK pc )"
+ for pc :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val ext_handle_control_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_control_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_control_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val ext_data_get_addr : mword ty5 -> mword ty64 -> AccessType -> word_width -> M (Ext_DataAddr_Check unit)\<close>\<close>
+
+definition ext_data_get_addr :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> AccessType \<Rightarrow> word_width \<Rightarrow>((register_value),((unit)Ext_DataAddr_Check),(exception))monad " where
+ " ext_data_get_addr (base :: regidx) (offset :: xlenbits) (acc1 :: AccessType) (width :: word_width) = (
+ (rX ((regidx_to_regno base)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let addr = ((add_vec w__0 offset :: 64 Word.word)) in
+ return (Ext_DataAddr_OK addr))))"
+ for base :: "(5)Word.word "
+ and offset :: "(64)Word.word "
+ and acc1 :: " AccessType "
+ and width :: " word_width "
+
+
+\<comment> \<open>\<open>val ext_handle_data_check_error : unit -> unit\<close>\<close>
+
+definition ext_handle_data_check_error :: " unit \<Rightarrow> unit " where
+ " ext_handle_data_check_error err = ( () )"
+ for err :: " unit "
+
+
+\<comment> \<open>\<open>val csr_name : mword ty12 -> string\<close>\<close>
+
+definition csr_name :: "(12)Word.word \<Rightarrow> string " where
+ " csr_name csr = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''ustatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''uie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''utvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''uscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''uepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''ucause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''utval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''uip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''fflags'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''frm'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''fcsr'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''cycle'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''time'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''instret'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''cycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''timeh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''instreth'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''sstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''sedeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''sideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''sie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''stvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (''scounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''sscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''sepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''scause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''stval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''sip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''satp'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''mvendorid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''marchid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mimpid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mhartid'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''misa'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''medeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (''mtvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (''mcounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (''mepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''mcause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (''mtval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (''mip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''pmpcfg0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''pmpaddr0'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mcycle'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''minstret'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''mcycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (''minstreth'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (''tselect'')
+ else (''UNKNOWN'')))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_forwards : mword ty12 -> M string\<close>\<close>
+
+definition csr_name_map_forwards :: "(12)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " csr_name_map_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''ustatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''uie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''utvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''uscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''uepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''ucause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''utval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''uip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''fflags'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''frm'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''fcsr'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''cycle'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''time'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''instret'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''cycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''timeh'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''instreth'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''sstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''sedeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''sideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''sie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''stvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''scounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''sscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''sepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''scause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''stval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''sip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''satp'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''mvendorid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''marchid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mimpid'')
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mhartid'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mstatus'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''misa'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''medeleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mideleg'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mie'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''mtvec'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''mcounteren'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mscratch'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''mepc'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''mcause'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''mtval'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''mip'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpcfg0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpcfg1'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpcfg2'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpcfg3'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr0'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr1'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr2'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr3'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr4'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr5'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr6'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr7'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr8'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr9'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr10'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr11'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ return (''pmpaddr12'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ return (''pmpaddr13'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ return (''pmpaddr14'')
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ return (''pmpaddr15'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mcycle'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''minstret'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''mcycleh'')
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''minstreth'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (''tselect'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (''tdata1'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (''tdata2'')
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (''tdata3'')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_backwards : string -> M (mword ty12)\<close>\<close>
+
+definition csr_name_map_backwards :: " string \<Rightarrow>((register_value),((12)Word.word),(exception))monad " where
+ " csr_name_map_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''ustatus'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''uie'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''utvec'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''uscratch'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''uepc'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''ucause'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''utval'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''uip'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''fflags'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''frm'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''fcsr'')))) then
+ return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''cycle'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''time'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''instret'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''cycleh'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''timeh'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''instreth'')))) then
+ return (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sstatus'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''sedeleg'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sideleg'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''sie'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''stvec'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''scounteren'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''sscratch'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''sepc'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''scause'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''stval'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''sip'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''satp'')))) then
+ return (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mvendorid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''marchid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mimpid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mhartid'')))) then
+ return (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mstatus'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''misa'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''medeleg'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mideleg'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mie'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mtvec'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''mcounteren'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mscratch'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''mepc'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''mcause'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mtval'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mip'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg0'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg1'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg2'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpcfg3'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr0'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr1'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr2'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr3'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr4'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr5'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr6'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr7'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr8'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr9'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr10'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr11'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr12'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr13'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr14'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''pmpaddr15'')))) then
+ return (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)
+ else if (((p00 = (''mcycle'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''minstret'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''mcycleh'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''minstreth'')))) then
+ return (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''tselect'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)
+ else if (((p00 = (''tdata1'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)
+ else if (((p00 = (''tdata2'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)
+ else if (((p00 = (''tdata3'')))) then
+ return (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_name_map_forwards_matches : mword ty12 -> bool\<close>\<close>
+
+definition csr_name_map_forwards_matches :: "(12)Word.word \<Rightarrow> bool " where
+ " csr_name_map_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ True
+ else False))"
+ for arg1 :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csr_name_map_backwards_matches : string -> bool\<close>\<close>
+
+definition csr_name_map_backwards_matches :: " string \<Rightarrow> bool " where
+ " csr_name_map_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''ustatus'')))) then True
+ else if (((p00 = (''uie'')))) then True
+ else if (((p00 = (''utvec'')))) then True
+ else if (((p00 = (''uscratch'')))) then True
+ else if (((p00 = (''uepc'')))) then True
+ else if (((p00 = (''ucause'')))) then True
+ else if (((p00 = (''utval'')))) then True
+ else if (((p00 = (''uip'')))) then True
+ else if (((p00 = (''fflags'')))) then True
+ else if (((p00 = (''frm'')))) then True
+ else if (((p00 = (''fcsr'')))) then True
+ else if (((p00 = (''cycle'')))) then True
+ else if (((p00 = (''time'')))) then True
+ else if (((p00 = (''instret'')))) then True
+ else if (((p00 = (''cycleh'')))) then True
+ else if (((p00 = (''timeh'')))) then True
+ else if (((p00 = (''instreth'')))) then True
+ else if (((p00 = (''sstatus'')))) then True
+ else if (((p00 = (''sedeleg'')))) then True
+ else if (((p00 = (''sideleg'')))) then True
+ else if (((p00 = (''sie'')))) then True
+ else if (((p00 = (''stvec'')))) then True
+ else if (((p00 = (''scounteren'')))) then True
+ else if (((p00 = (''sscratch'')))) then True
+ else if (((p00 = (''sepc'')))) then True
+ else if (((p00 = (''scause'')))) then True
+ else if (((p00 = (''stval'')))) then True
+ else if (((p00 = (''sip'')))) then True
+ else if (((p00 = (''satp'')))) then True
+ else if (((p00 = (''mvendorid'')))) then True
+ else if (((p00 = (''marchid'')))) then True
+ else if (((p00 = (''mimpid'')))) then True
+ else if (((p00 = (''mhartid'')))) then True
+ else if (((p00 = (''mstatus'')))) then True
+ else if (((p00 = (''misa'')))) then True
+ else if (((p00 = (''medeleg'')))) then True
+ else if (((p00 = (''mideleg'')))) then True
+ else if (((p00 = (''mie'')))) then True
+ else if (((p00 = (''mtvec'')))) then True
+ else if (((p00 = (''mcounteren'')))) then True
+ else if (((p00 = (''mscratch'')))) then True
+ else if (((p00 = (''mepc'')))) then True
+ else if (((p00 = (''mcause'')))) then True
+ else if (((p00 = (''mtval'')))) then True
+ else if (((p00 = (''mip'')))) then True
+ else if (((p00 = (''pmpcfg0'')))) then True
+ else if (((p00 = (''pmpcfg1'')))) then True
+ else if (((p00 = (''pmpcfg2'')))) then True
+ else if (((p00 = (''pmpcfg3'')))) then True
+ else if (((p00 = (''pmpaddr0'')))) then True
+ else if (((p00 = (''pmpaddr1'')))) then True
+ else if (((p00 = (''pmpaddr2'')))) then True
+ else if (((p00 = (''pmpaddr3'')))) then True
+ else if (((p00 = (''pmpaddr4'')))) then True
+ else if (((p00 = (''pmpaddr5'')))) then True
+ else if (((p00 = (''pmpaddr6'')))) then True
+ else if (((p00 = (''pmpaddr7'')))) then True
+ else if (((p00 = (''pmpaddr8'')))) then True
+ else if (((p00 = (''pmpaddr9'')))) then True
+ else if (((p00 = (''pmpaddr10'')))) then True
+ else if (((p00 = (''pmpaddr11'')))) then True
+ else if (((p00 = (''pmpaddr12'')))) then True
+ else if (((p00 = (''pmpaddr13'')))) then True
+ else if (((p00 = (''pmpaddr14'')))) then True
+ else if (((p00 = (''pmpaddr15'')))) then True
+ else if (((p00 = (''mcycle'')))) then True
+ else if (((p00 = (''minstret'')))) then True
+ else if (((p00 = (''mcycleh'')))) then True
+ else if (((p00 = (''minstreth'')))) then True
+ else if (((p00 = (''tselect'')))) then True
+ else if (((p00 = (''tdata1'')))) then True
+ else if (((p00 = (''tdata2'')))) then True
+ else if (((p00 = (''tdata3'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s488_ : string -> maybe string\<close>\<close>
+
+definition s488 :: " string \<Rightarrow>(string)option " where
+ " s488 s4890 = (
+ (let s4900 = s4890 in
+ if ((string_startswith s4900 (''tdata3''))) then
+ (case ((string_drop s4900 ((string_length (''tdata3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4890 :: " string "
+
+
+\<comment> \<open>\<open>val _s484_ : string -> maybe string\<close>\<close>
+
+definition s484 :: " string \<Rightarrow>(string)option " where
+ " s484 s4850 = (
+ (let s4860 = s4850 in
+ if ((string_startswith s4860 (''tdata2''))) then
+ (case ((string_drop s4860 ((string_length (''tdata2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4850 :: " string "
+
+
+\<comment> \<open>\<open>val _s480_ : string -> maybe string\<close>\<close>
+
+definition s480 :: " string \<Rightarrow>(string)option " where
+ " s480 s4810 = (
+ (let s4820 = s4810 in
+ if ((string_startswith s4820 (''tdata1''))) then
+ (case ((string_drop s4820 ((string_length (''tdata1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4810 :: " string "
+
+
+\<comment> \<open>\<open>val _s476_ : string -> maybe string\<close>\<close>
+
+definition s476 :: " string \<Rightarrow>(string)option " where
+ " s476 s4770 = (
+ (let s4780 = s4770 in
+ if ((string_startswith s4780 (''tselect''))) then
+ (case ((string_drop s4780 ((string_length (''tselect''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4770 :: " string "
+
+
+\<comment> \<open>\<open>val _s472_ : string -> maybe string\<close>\<close>
+
+definition s472 :: " string \<Rightarrow>(string)option " where
+ " s472 s4730 = (
+ (let s4740 = s4730 in
+ if ((string_startswith s4740 (''minstreth''))) then
+ (case ((string_drop s4740 ((string_length (''minstreth''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4730 :: " string "
+
+
+\<comment> \<open>\<open>val _s468_ : string -> maybe string\<close>\<close>
+
+definition s468 :: " string \<Rightarrow>(string)option " where
+ " s468 s4690 = (
+ (let s4700 = s4690 in
+ if ((string_startswith s4700 (''mcycleh''))) then
+ (case ((string_drop s4700 ((string_length (''mcycleh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4690 :: " string "
+
+
+\<comment> \<open>\<open>val _s464_ : string -> maybe string\<close>\<close>
+
+definition s464 :: " string \<Rightarrow>(string)option " where
+ " s464 s4650 = (
+ (let s4660 = s4650 in
+ if ((string_startswith s4660 (''minstret''))) then
+ (case ((string_drop s4660 ((string_length (''minstret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4650 :: " string "
+
+
+\<comment> \<open>\<open>val _s460_ : string -> maybe string\<close>\<close>
+
+definition s460 :: " string \<Rightarrow>(string)option " where
+ " s460 s4610 = (
+ (let s4620 = s4610 in
+ if ((string_startswith s4620 (''mcycle''))) then
+ (case ((string_drop s4620 ((string_length (''mcycle''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4610 :: " string "
+
+
+\<comment> \<open>\<open>val _s456_ : string -> maybe string\<close>\<close>
+
+definition s456 :: " string \<Rightarrow>(string)option " where
+ " s456 s4570 = (
+ (let s4580 = s4570 in
+ if ((string_startswith s4580 (''pmpaddr15''))) then
+ (case ((string_drop s4580 ((string_length (''pmpaddr15''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4570 :: " string "
+
+
+\<comment> \<open>\<open>val _s452_ : string -> maybe string\<close>\<close>
+
+definition s452 :: " string \<Rightarrow>(string)option " where
+ " s452 s4530 = (
+ (let s4540 = s4530 in
+ if ((string_startswith s4540 (''pmpaddr14''))) then
+ (case ((string_drop s4540 ((string_length (''pmpaddr14''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4530 :: " string "
+
+
+\<comment> \<open>\<open>val _s448_ : string -> maybe string\<close>\<close>
+
+definition s448 :: " string \<Rightarrow>(string)option " where
+ " s448 s4490 = (
+ (let s4500 = s4490 in
+ if ((string_startswith s4500 (''pmpaddr13''))) then
+ (case ((string_drop s4500 ((string_length (''pmpaddr13''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4490 :: " string "
+
+
+\<comment> \<open>\<open>val _s444_ : string -> maybe string\<close>\<close>
+
+definition s444 :: " string \<Rightarrow>(string)option " where
+ " s444 s4450 = (
+ (let s4460 = s4450 in
+ if ((string_startswith s4460 (''pmpaddr12''))) then
+ (case ((string_drop s4460 ((string_length (''pmpaddr12''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4450 :: " string "
+
+
+\<comment> \<open>\<open>val _s440_ : string -> maybe string\<close>\<close>
+
+definition s440 :: " string \<Rightarrow>(string)option " where
+ " s440 s4410 = (
+ (let s4420 = s4410 in
+ if ((string_startswith s4420 (''pmpaddr11''))) then
+ (case ((string_drop s4420 ((string_length (''pmpaddr11''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4410 :: " string "
+
+
+\<comment> \<open>\<open>val _s436_ : string -> maybe string\<close>\<close>
+
+definition s436 :: " string \<Rightarrow>(string)option " where
+ " s436 s4370 = (
+ (let s4380 = s4370 in
+ if ((string_startswith s4380 (''pmpaddr10''))) then
+ (case ((string_drop s4380 ((string_length (''pmpaddr10''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4370 :: " string "
+
+
+\<comment> \<open>\<open>val _s432_ : string -> maybe string\<close>\<close>
+
+definition s432 :: " string \<Rightarrow>(string)option " where
+ " s432 s4330 = (
+ (let s4340 = s4330 in
+ if ((string_startswith s4340 (''pmpaddr9''))) then
+ (case ((string_drop s4340 ((string_length (''pmpaddr9''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4330 :: " string "
+
+
+\<comment> \<open>\<open>val _s428_ : string -> maybe string\<close>\<close>
+
+definition s428 :: " string \<Rightarrow>(string)option " where
+ " s428 s4290 = (
+ (let s4300 = s4290 in
+ if ((string_startswith s4300 (''pmpaddr8''))) then
+ (case ((string_drop s4300 ((string_length (''pmpaddr8''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4290 :: " string "
+
+
+\<comment> \<open>\<open>val _s424_ : string -> maybe string\<close>\<close>
+
+definition s424 :: " string \<Rightarrow>(string)option " where
+ " s424 s4250 = (
+ (let s4260 = s4250 in
+ if ((string_startswith s4260 (''pmpaddr7''))) then
+ (case ((string_drop s4260 ((string_length (''pmpaddr7''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4250 :: " string "
+
+
+\<comment> \<open>\<open>val _s420_ : string -> maybe string\<close>\<close>
+
+definition s420 :: " string \<Rightarrow>(string)option " where
+ " s420 s4210 = (
+ (let s4220 = s4210 in
+ if ((string_startswith s4220 (''pmpaddr6''))) then
+ (case ((string_drop s4220 ((string_length (''pmpaddr6''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4210 :: " string "
+
+
+\<comment> \<open>\<open>val _s416_ : string -> maybe string\<close>\<close>
+
+definition s416 :: " string \<Rightarrow>(string)option " where
+ " s416 s4170 = (
+ (let s4180 = s4170 in
+ if ((string_startswith s4180 (''pmpaddr5''))) then
+ (case ((string_drop s4180 ((string_length (''pmpaddr5''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4170 :: " string "
+
+
+\<comment> \<open>\<open>val _s412_ : string -> maybe string\<close>\<close>
+
+definition s412 :: " string \<Rightarrow>(string)option " where
+ " s412 s4130 = (
+ (let s4140 = s4130 in
+ if ((string_startswith s4140 (''pmpaddr4''))) then
+ (case ((string_drop s4140 ((string_length (''pmpaddr4''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4130 :: " string "
+
+
+\<comment> \<open>\<open>val _s408_ : string -> maybe string\<close>\<close>
+
+definition s408 :: " string \<Rightarrow>(string)option " where
+ " s408 s4090 = (
+ (let s4100 = s4090 in
+ if ((string_startswith s4100 (''pmpaddr3''))) then
+ (case ((string_drop s4100 ((string_length (''pmpaddr3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4090 :: " string "
+
+
+\<comment> \<open>\<open>val _s404_ : string -> maybe string\<close>\<close>
+
+definition s404 :: " string \<Rightarrow>(string)option " where
+ " s404 s4050 = (
+ (let s4060 = s4050 in
+ if ((string_startswith s4060 (''pmpaddr2''))) then
+ (case ((string_drop s4060 ((string_length (''pmpaddr2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4050 :: " string "
+
+
+\<comment> \<open>\<open>val _s400_ : string -> maybe string\<close>\<close>
+
+definition s400 :: " string \<Rightarrow>(string)option " where
+ " s400 s4010 = (
+ (let s4020 = s4010 in
+ if ((string_startswith s4020 (''pmpaddr1''))) then
+ (case ((string_drop s4020 ((string_length (''pmpaddr1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4010 :: " string "
+
+
+\<comment> \<open>\<open>val _s396_ : string -> maybe string\<close>\<close>
+
+definition s396 :: " string \<Rightarrow>(string)option " where
+ " s396 s3970 = (
+ (let s3980 = s3970 in
+ if ((string_startswith s3980 (''pmpaddr0''))) then
+ (case ((string_drop s3980 ((string_length (''pmpaddr0''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3970 :: " string "
+
+
+\<comment> \<open>\<open>val _s392_ : string -> maybe string\<close>\<close>
+
+definition s392 :: " string \<Rightarrow>(string)option " where
+ " s392 s3930 = (
+ (let s3940 = s3930 in
+ if ((string_startswith s3940 (''pmpcfg3''))) then
+ (case ((string_drop s3940 ((string_length (''pmpcfg3''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3930 :: " string "
+
+
+\<comment> \<open>\<open>val _s388_ : string -> maybe string\<close>\<close>
+
+definition s388 :: " string \<Rightarrow>(string)option " where
+ " s388 s3890 = (
+ (let s3900 = s3890 in
+ if ((string_startswith s3900 (''pmpcfg2''))) then
+ (case ((string_drop s3900 ((string_length (''pmpcfg2''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3890 :: " string "
+
+
+\<comment> \<open>\<open>val _s384_ : string -> maybe string\<close>\<close>
+
+definition s384 :: " string \<Rightarrow>(string)option " where
+ " s384 s3850 = (
+ (let s3860 = s3850 in
+ if ((string_startswith s3860 (''pmpcfg1''))) then
+ (case ((string_drop s3860 ((string_length (''pmpcfg1''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3850 :: " string "
+
+
+\<comment> \<open>\<open>val _s380_ : string -> maybe string\<close>\<close>
+
+definition s380 :: " string \<Rightarrow>(string)option " where
+ " s380 s3810 = (
+ (let s3820 = s3810 in
+ if ((string_startswith s3820 (''pmpcfg0''))) then
+ (case ((string_drop s3820 ((string_length (''pmpcfg0''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3810 :: " string "
+
+
+\<comment> \<open>\<open>val _s376_ : string -> maybe string\<close>\<close>
+
+definition s376 :: " string \<Rightarrow>(string)option " where
+ " s376 s3770 = (
+ (let s3780 = s3770 in
+ if ((string_startswith s3780 (''mip''))) then
+ (case ((string_drop s3780 ((string_length (''mip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3770 :: " string "
+
+
+\<comment> \<open>\<open>val _s372_ : string -> maybe string\<close>\<close>
+
+definition s372 :: " string \<Rightarrow>(string)option " where
+ " s372 s3730 = (
+ (let s3740 = s3730 in
+ if ((string_startswith s3740 (''mtval''))) then
+ (case ((string_drop s3740 ((string_length (''mtval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3730 :: " string "
+
+
+\<comment> \<open>\<open>val _s368_ : string -> maybe string\<close>\<close>
+
+definition s368 :: " string \<Rightarrow>(string)option " where
+ " s368 s3690 = (
+ (let s3700 = s3690 in
+ if ((string_startswith s3700 (''mcause''))) then
+ (case ((string_drop s3700 ((string_length (''mcause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3690 :: " string "
+
+
+\<comment> \<open>\<open>val _s364_ : string -> maybe string\<close>\<close>
+
+definition s364 :: " string \<Rightarrow>(string)option " where
+ " s364 s3650 = (
+ (let s3660 = s3650 in
+ if ((string_startswith s3660 (''mepc''))) then
+ (case ((string_drop s3660 ((string_length (''mepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3650 :: " string "
+
+
+\<comment> \<open>\<open>val _s360_ : string -> maybe string\<close>\<close>
+
+definition s360 :: " string \<Rightarrow>(string)option " where
+ " s360 s3610 = (
+ (let s3620 = s3610 in
+ if ((string_startswith s3620 (''mscratch''))) then
+ (case ((string_drop s3620 ((string_length (''mscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3610 :: " string "
+
+
+\<comment> \<open>\<open>val _s356_ : string -> maybe string\<close>\<close>
+
+definition s356 :: " string \<Rightarrow>(string)option " where
+ " s356 s3570 = (
+ (let s3580 = s3570 in
+ if ((string_startswith s3580 (''mcounteren''))) then
+ (case ((string_drop s3580 ((string_length (''mcounteren''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3570 :: " string "
+
+
+\<comment> \<open>\<open>val _s352_ : string -> maybe string\<close>\<close>
+
+definition s352 :: " string \<Rightarrow>(string)option " where
+ " s352 s3530 = (
+ (let s3540 = s3530 in
+ if ((string_startswith s3540 (''mtvec''))) then
+ (case ((string_drop s3540 ((string_length (''mtvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3530 :: " string "
+
+
+\<comment> \<open>\<open>val _s348_ : string -> maybe string\<close>\<close>
+
+definition s348 :: " string \<Rightarrow>(string)option " where
+ " s348 s3490 = (
+ (let s3500 = s3490 in
+ if ((string_startswith s3500 (''mie''))) then
+ (case ((string_drop s3500 ((string_length (''mie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3490 :: " string "
+
+
+\<comment> \<open>\<open>val _s344_ : string -> maybe string\<close>\<close>
+
+definition s344 :: " string \<Rightarrow>(string)option " where
+ " s344 s3450 = (
+ (let s3460 = s3450 in
+ if ((string_startswith s3460 (''mideleg''))) then
+ (case ((string_drop s3460 ((string_length (''mideleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3450 :: " string "
+
+
+\<comment> \<open>\<open>val _s340_ : string -> maybe string\<close>\<close>
+
+definition s340 :: " string \<Rightarrow>(string)option " where
+ " s340 s3411 = (
+ (let s3420 = s3411 in
+ if ((string_startswith s3420 (''medeleg''))) then
+ (case ((string_drop s3420 ((string_length (''medeleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3411 :: " string "
+
+
+\<comment> \<open>\<open>val _s336_ : string -> maybe string\<close>\<close>
+
+definition s336 :: " string \<Rightarrow>(string)option " where
+ " s336 s3370 = (
+ (let s3380 = s3370 in
+ if ((string_startswith s3380 (''misa''))) then
+ (case ((string_drop s3380 ((string_length (''misa''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3370 :: " string "
+
+
+\<comment> \<open>\<open>val _s332_ : string -> maybe string\<close>\<close>
+
+definition s332 :: " string \<Rightarrow>(string)option " where
+ " s332 s3330 = (
+ (let s3340 = s3330 in
+ if ((string_startswith s3340 (''mstatus''))) then
+ (case ((string_drop s3340 ((string_length (''mstatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3330 :: " string "
+
+
+\<comment> \<open>\<open>val _s328_ : string -> maybe string\<close>\<close>
+
+definition s328 :: " string \<Rightarrow>(string)option " where
+ " s328 s3290 = (
+ (let s3300 = s3290 in
+ if ((string_startswith s3300 (''mhartid''))) then
+ (case ((string_drop s3300 ((string_length (''mhartid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3290 :: " string "
+
+
+\<comment> \<open>\<open>val _s324_ : string -> maybe string\<close>\<close>
+
+definition s324 :: " string \<Rightarrow>(string)option " where
+ " s324 s3250 = (
+ (let s3260 = s3250 in
+ if ((string_startswith s3260 (''mimpid''))) then
+ (case ((string_drop s3260 ((string_length (''mimpid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3250 :: " string "
+
+
+\<comment> \<open>\<open>val _s320_ : string -> maybe string\<close>\<close>
+
+definition s320 :: " string \<Rightarrow>(string)option " where
+ " s320 s3210 = (
+ (let s3220 = s3210 in
+ if ((string_startswith s3220 (''marchid''))) then
+ (case ((string_drop s3220 ((string_length (''marchid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3210 :: " string "
+
+
+\<comment> \<open>\<open>val _s316_ : string -> maybe string\<close>\<close>
+
+definition s316 :: " string \<Rightarrow>(string)option " where
+ " s316 s3170 = (
+ (let s3180 = s3170 in
+ if ((string_startswith s3180 (''mvendorid''))) then
+ (case ((string_drop s3180 ((string_length (''mvendorid''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3170 :: " string "
+
+
+\<comment> \<open>\<open>val _s312_ : string -> maybe string\<close>\<close>
+
+definition s312 :: " string \<Rightarrow>(string)option " where
+ " s312 s3130 = (
+ (let s3140 = s3130 in
+ if ((string_startswith s3140 (''satp''))) then
+ (case ((string_drop s3140 ((string_length (''satp''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3130 :: " string "
+
+
+\<comment> \<open>\<open>val _s308_ : string -> maybe string\<close>\<close>
+
+definition s308 :: " string \<Rightarrow>(string)option " where
+ " s308 s3090 = (
+ (let s3100 = s3090 in
+ if ((string_startswith s3100 (''sip''))) then
+ (case ((string_drop s3100 ((string_length (''sip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3090 :: " string "
+
+
+\<comment> \<open>\<open>val _s304_ : string -> maybe string\<close>\<close>
+
+definition s304 :: " string \<Rightarrow>(string)option " where
+ " s304 s3050 = (
+ (let s3060 = s3050 in
+ if ((string_startswith s3060 (''stval''))) then
+ (case ((string_drop s3060 ((string_length (''stval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3050 :: " string "
+
+
+\<comment> \<open>\<open>val _s300_ : string -> maybe string\<close>\<close>
+
+definition s300 :: " string \<Rightarrow>(string)option " where
+ " s300 s3010 = (
+ (let s3020 = s3010 in
+ if ((string_startswith s3020 (''scause''))) then
+ (case ((string_drop s3020 ((string_length (''scause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s3010 :: " string "
+
+
+\<comment> \<open>\<open>val _s296_ : string -> maybe string\<close>\<close>
+
+definition s296 :: " string \<Rightarrow>(string)option " where
+ " s296 s2970 = (
+ (let s2980 = s2970 in
+ if ((string_startswith s2980 (''sepc''))) then
+ (case ((string_drop s2980 ((string_length (''sepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2970 :: " string "
+
+
+\<comment> \<open>\<open>val _s292_ : string -> maybe string\<close>\<close>
+
+definition s292 :: " string \<Rightarrow>(string)option " where
+ " s292 s2930 = (
+ (let s2940 = s2930 in
+ if ((string_startswith s2940 (''sscratch''))) then
+ (case ((string_drop s2940 ((string_length (''sscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2930 :: " string "
+
+
+\<comment> \<open>\<open>val _s288_ : string -> maybe string\<close>\<close>
+
+definition s288 :: " string \<Rightarrow>(string)option " where
+ " s288 s2890 = (
+ (let s2900 = s2890 in
+ if ((string_startswith s2900 (''scounteren''))) then
+ (case ((string_drop s2900 ((string_length (''scounteren''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2890 :: " string "
+
+
+\<comment> \<open>\<open>val _s284_ : string -> maybe string\<close>\<close>
+
+definition s284 :: " string \<Rightarrow>(string)option " where
+ " s284 s2850 = (
+ (let s2860 = s2850 in
+ if ((string_startswith s2860 (''stvec''))) then
+ (case ((string_drop s2860 ((string_length (''stvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2850 :: " string "
+
+
+\<comment> \<open>\<open>val _s280_ : string -> maybe string\<close>\<close>
+
+definition s280 :: " string \<Rightarrow>(string)option " where
+ " s280 s2810 = (
+ (let s2820 = s2810 in
+ if ((string_startswith s2820 (''sie''))) then
+ (case ((string_drop s2820 ((string_length (''sie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2810 :: " string "
+
+
+\<comment> \<open>\<open>val _s276_ : string -> maybe string\<close>\<close>
+
+definition s276 :: " string \<Rightarrow>(string)option " where
+ " s276 s2770 = (
+ (let s2780 = s2770 in
+ if ((string_startswith s2780 (''sideleg''))) then
+ (case ((string_drop s2780 ((string_length (''sideleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2770 :: " string "
+
+
+\<comment> \<open>\<open>val _s272_ : string -> maybe string\<close>\<close>
+
+definition s272 :: " string \<Rightarrow>(string)option " where
+ " s272 s2730 = (
+ (let s2741 = s2730 in
+ if ((string_startswith s2741 (''sedeleg''))) then
+ (case ((string_drop s2741 ((string_length (''sedeleg''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2730 :: " string "
+
+
+\<comment> \<open>\<open>val _s268_ : string -> maybe string\<close>\<close>
+
+definition s268 :: " string \<Rightarrow>(string)option " where
+ " s268 s2690 = (
+ (let s2700 = s2690 in
+ if ((string_startswith s2700 (''sstatus''))) then
+ (case ((string_drop s2700 ((string_length (''sstatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2690 :: " string "
+
+
+\<comment> \<open>\<open>val _s264_ : string -> maybe string\<close>\<close>
+
+definition s264 :: " string \<Rightarrow>(string)option " where
+ " s264 s2650 = (
+ (let s2660 = s2650 in
+ if ((string_startswith s2660 (''instreth''))) then
+ (case ((string_drop s2660 ((string_length (''instreth''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2650 :: " string "
+
+
+\<comment> \<open>\<open>val _s260_ : string -> maybe string\<close>\<close>
+
+definition s260 :: " string \<Rightarrow>(string)option " where
+ " s260 s2610 = (
+ (let s2620 = s2610 in
+ if ((string_startswith s2620 (''timeh''))) then
+ (case ((string_drop s2620 ((string_length (''timeh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2610 :: " string "
+
+
+\<comment> \<open>\<open>val _s256_ : string -> maybe string\<close>\<close>
+
+definition s256 :: " string \<Rightarrow>(string)option " where
+ " s256 s2571 = (
+ (let s2580 = s2571 in
+ if ((string_startswith s2580 (''cycleh''))) then
+ (case ((string_drop s2580 ((string_length (''cycleh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2571 :: " string "
+
+
+\<comment> \<open>\<open>val _s252_ : string -> maybe string\<close>\<close>
+
+definition s252 :: " string \<Rightarrow>(string)option " where
+ " s252 s2530 = (
+ (let s2540 = s2530 in
+ if ((string_startswith s2540 (''instret''))) then
+ (case ((string_drop s2540 ((string_length (''instret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2530 :: " string "
+
+
+\<comment> \<open>\<open>val _s248_ : string -> maybe string\<close>\<close>
+
+definition s248 :: " string \<Rightarrow>(string)option " where
+ " s248 s2490 = (
+ (let s2500 = s2490 in
+ if ((string_startswith s2500 (''time''))) then
+ (case ((string_drop s2500 ((string_length (''time''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2490 :: " string "
+
+
+\<comment> \<open>\<open>val _s244_ : string -> maybe string\<close>\<close>
+
+definition s244 :: " string \<Rightarrow>(string)option " where
+ " s244 s2450 = (
+ (let s2460 = s2450 in
+ if ((string_startswith s2460 (''cycle''))) then
+ (case ((string_drop s2460 ((string_length (''cycle''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2450 :: " string "
+
+
+\<comment> \<open>\<open>val _s240_ : string -> maybe string\<close>\<close>
+
+definition s240 :: " string \<Rightarrow>(string)option " where
+ " s240 s2410 = (
+ (let s2420 = s2410 in
+ if ((string_startswith s2420 (''fcsr''))) then
+ (case ((string_drop s2420 ((string_length (''fcsr''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2410 :: " string "
+
+
+\<comment> \<open>\<open>val _s236_ : string -> maybe string\<close>\<close>
+
+definition s236 :: " string \<Rightarrow>(string)option " where
+ " s236 s2370 = (
+ (let s2380 = s2370 in
+ if ((string_startswith s2380 (''frm''))) then
+ (case ((string_drop s2380 ((string_length (''frm''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2370 :: " string "
+
+
+\<comment> \<open>\<open>val _s232_ : string -> maybe string\<close>\<close>
+
+definition s232 :: " string \<Rightarrow>(string)option " where
+ " s232 s2330 = (
+ (let s2340 = s2330 in
+ if ((string_startswith s2340 (''fflags''))) then
+ (case ((string_drop s2340 ((string_length (''fflags''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2330 :: " string "
+
+
+\<comment> \<open>\<open>val _s228_ : string -> maybe string\<close>\<close>
+
+definition s228 :: " string \<Rightarrow>(string)option " where
+ " s228 s2290 = (
+ (let s2300 = s2290 in
+ if ((string_startswith s2300 (''uip''))) then
+ (case ((string_drop s2300 ((string_length (''uip''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2290 :: " string "
+
+
+\<comment> \<open>\<open>val _s224_ : string -> maybe string\<close>\<close>
+
+definition s224 :: " string \<Rightarrow>(string)option " where
+ " s224 s2250 = (
+ (let s2260 = s2250 in
+ if ((string_startswith s2260 (''utval''))) then
+ (case ((string_drop s2260 ((string_length (''utval''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2250 :: " string "
+
+
+\<comment> \<open>\<open>val _s220_ : string -> maybe string\<close>\<close>
+
+definition s220 :: " string \<Rightarrow>(string)option " where
+ " s220 s2210 = (
+ (let s2220 = s2210 in
+ if ((string_startswith s2220 (''ucause''))) then
+ (case ((string_drop s2220 ((string_length (''ucause''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2210 :: " string "
+
+
+\<comment> \<open>\<open>val _s216_ : string -> maybe string\<close>\<close>
+
+definition s216 :: " string \<Rightarrow>(string)option " where
+ " s216 s2170 = (
+ (let s2180 = s2170 in
+ if ((string_startswith s2180 (''uepc''))) then
+ (case ((string_drop s2180 ((string_length (''uepc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2170 :: " string "
+
+
+\<comment> \<open>\<open>val _s212_ : string -> maybe string\<close>\<close>
+
+definition s212 :: " string \<Rightarrow>(string)option " where
+ " s212 s2130 = (
+ (let s2140 = s2130 in
+ if ((string_startswith s2140 (''uscratch''))) then
+ (case ((string_drop s2140 ((string_length (''uscratch''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2130 :: " string "
+
+
+\<comment> \<open>\<open>val _s208_ : string -> maybe string\<close>\<close>
+
+definition s208 :: " string \<Rightarrow>(string)option " where
+ " s208 s2090 = (
+ (let s2100 = s2090 in
+ if ((string_startswith s2100 (''utvec''))) then
+ (case ((string_drop s2100 ((string_length (''utvec''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2090 :: " string "
+
+
+\<comment> \<open>\<open>val _s204_ : string -> maybe string\<close>\<close>
+
+definition s204 :: " string \<Rightarrow>(string)option " where
+ " s204 s2050 = (
+ (let s2060 = s2050 in
+ if ((string_startswith s2060 (''uie''))) then
+ (case ((string_drop s2060 ((string_length (''uie''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2050 :: " string "
+
+
+\<comment> \<open>\<open>val _s200_ : string -> maybe string\<close>\<close>
+
+definition s200 :: " string \<Rightarrow>(string)option " where
+ " s200 s2010 = (
+ (let s2020 = s2010 in
+ if ((string_startswith s2020 (''ustatus''))) then
+ (case ((string_drop s2020 ((string_length (''ustatus''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s2010 :: " string "
+
+
+definition csr_name_map_matches_prefix :: " string \<Rightarrow>((12)Word.word*int)option " where
+ " csr_name_map_matches_prefix arg1 = (
+ (let s2030 = arg1 in
+ if ((case ((s200 s2030)) of Some (s1) => True | _ => False )) then
+ (case s200 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s204 s2030)) of Some (s1) => True | _ => False )) then
+ (case s204 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s208 s2030)) of Some (s1) => True | _ => False )) then
+ (case s208 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s212 s2030)) of Some (s1) => True | _ => False )) then
+ (case s212 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s216 s2030)) of Some (s1) => True | _ => False )) then
+ (case s216 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s220 s2030)) of Some (s1) => True | _ => False )) then
+ (case s220 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s224 s2030)) of Some (s1) => True | _ => False )) then
+ (case s224 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s228 s2030)) of Some (s1) => True | _ => False )) then
+ (case s228 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s232 s2030)) of Some (s1) => True | _ => False )) then
+ (case s232 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s236 s2030)) of Some (s1) => True | _ => False )) then
+ (case s236 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s240 s2030)) of Some (s1) => True | _ => False )) then
+ (case s240 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s244 s2030)) of Some (s1) => True | _ => False )) then
+ (case s244 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s248 s2030)) of Some (s1) => True | _ => False )) then
+ (case s248 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s252 s2030)) of Some (s1) => True | _ => False )) then
+ (case s252 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s256 s2030)) of Some (s1) => True | _ => False )) then
+ (case s256 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s260 s2030)) of Some (s1) => True | _ => False )) then
+ (case s260 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s264 s2030)) of Some (s1) => True | _ => False )) then
+ (case s264 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s268 s2030)) of Some (s1) => True | _ => False )) then
+ (case s268 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s272 s2030)) of Some (s1) => True | _ => False )) then
+ (case s272 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s276 s2030)) of Some (s1) => True | _ => False )) then
+ (case s276 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s280 s2030)) of Some (s1) => True | _ => False )) then
+ (case s280 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s284 s2030)) of Some (s1) => True | _ => False )) then
+ (case s284 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s288 s2030)) of Some (s1) => True | _ => False )) then
+ (case s288 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s292 s2030)) of Some (s1) => True | _ => False )) then
+ (case s292 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s296 s2030)) of Some (s1) => True | _ => False )) then
+ (case s296 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s300 s2030)) of Some (s1) => True | _ => False )) then
+ (case s300 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s304 s2030)) of Some (s1) => True | _ => False )) then
+ (case s304 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s308 s2030)) of Some (s1) => True | _ => False )) then
+ (case s308 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s312 s2030)) of Some (s1) => True | _ => False )) then
+ (case s312 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s316 s2030)) of Some (s1) => True | _ => False )) then
+ (case s316 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s320 s2030)) of Some (s1) => True | _ => False )) then
+ (case s320 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s324 s2030)) of Some (s1) => True | _ => False )) then
+ (case s324 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s328 s2030)) of Some (s1) => True | _ => False )) then
+ (case s328 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s332 s2030)) of Some (s1) => True | _ => False )) then
+ (case s332 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s336 s2030)) of Some (s1) => True | _ => False )) then
+ (case s336 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s340 s2030)) of Some (s1) => True | _ => False )) then
+ (case s340 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s344 s2030)) of Some (s1) => True | _ => False )) then
+ (case s344 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s348 s2030)) of Some (s1) => True | _ => False )) then
+ (case s348 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s352 s2030)) of Some (s1) => True | _ => False )) then
+ (case s352 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s356 s2030)) of Some (s1) => True | _ => False )) then
+ (case s356 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s360 s2030)) of Some (s1) => True | _ => False )) then
+ (case s360 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s364 s2030)) of Some (s1) => True | _ => False )) then
+ (case s364 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s368 s2030)) of Some (s1) => True | _ => False )) then
+ (case s368 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s372 s2030)) of Some (s1) => True | _ => False )) then
+ (case s372 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s376 s2030)) of Some (s1) => True | _ => False )) then
+ (case s376 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s380 s2030)) of Some (s1) => True | _ => False )) then
+ (case s380 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s384 s2030)) of Some (s1) => True | _ => False )) then
+ (case s384 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s388 s2030)) of Some (s1) => True | _ => False )) then
+ (case s388 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s392 s2030)) of Some (s1) => True | _ => False )) then
+ (case s392 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s396 s2030)) of Some (s1) => True | _ => False )) then
+ (case s396 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s400 s2030)) of Some (s1) => True | _ => False )) then
+ (case s400 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s404 s2030)) of Some (s1) => True | _ => False )) then
+ (case s404 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s408 s2030)) of Some (s1) => True | _ => False )) then
+ (case s408 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s412 s2030)) of Some (s1) => True | _ => False )) then
+ (case s412 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s416 s2030)) of Some (s1) => True | _ => False )) then
+ (case s416 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s420 s2030)) of Some (s1) => True | _ => False )) then
+ (case s420 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s424 s2030)) of Some (s1) => True | _ => False )) then
+ (case s424 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s428 s2030)) of Some (s1) => True | _ => False )) then
+ (case s428 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s432 s2030)) of Some (s1) => True | _ => False )) then
+ (case s432 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s436 s2030)) of Some (s1) => True | _ => False )) then
+ (case s436 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s440 s2030)) of Some (s1) => True | _ => False )) then
+ (case s440 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s444 s2030)) of Some (s1) => True | _ => False )) then
+ (case s444 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s448 s2030)) of Some (s1) => True | _ => False )) then
+ (case s448 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s452 s2030)) of Some (s1) => True | _ => False )) then
+ (case s452 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s456 s2030)) of Some (s1) => True | _ => False )) then
+ (case s456 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s460 s2030)) of Some (s1) => True | _ => False )) then
+ (case s460 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s464 s2030)) of Some (s1) => True | _ => False )) then
+ (case s464 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s468 s2030)) of Some (s1) => True | _ => False )) then
+ (case s468 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s472 s2030)) of Some (s1) => True | _ => False )) then
+ (case s472 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s476 s2030)) of Some (s1) => True | _ => False )) then
+ (case s476 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s480 s2030)) of Some (s1) => True | _ => False )) then
+ (case s480 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s484 s2030)) of Some (s1) => True | _ => False )) then
+ (case s484 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s488 s2030)) of Some (s1) => True | _ => False )) then
+ (case s488 s2030 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val Mk_Ustatus : mword ty64 -> Ustatus\<close>\<close>
+
+definition Mk_Ustatus :: "(64)Word.word \<Rightarrow> Ustatus " where
+ " Mk_Ustatus v = (
+ (| Ustatus_Ustatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Ustatus_bits : Ustatus -> mword ty64\<close>\<close>
+
+definition get_Ustatus_bits :: " Ustatus \<Rightarrow>(64)Word.word " where
+ " get_Ustatus_bits v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Ustatus "
+
+
+\<comment> \<open>\<open>val _set_Ustatus_bits : register_ref regstate register_value Ustatus -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Ustatus_bits :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Ustatus_bits : Ustatus -> mword ty64 -> Ustatus\<close>\<close>
+
+definition update_Ustatus_bits :: " Ustatus \<Rightarrow>(64)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_bits v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(64)Word.word "
+
+
+definition get_Ustatus_UPIE :: " Ustatus \<Rightarrow>(1)Word.word " where
+ " get_Ustatus_UPIE v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Ustatus "
+
+
+definition set_Ustatus_UPIE :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_UPIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Ustatus_UPIE :: " Ustatus \<Rightarrow>(1)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_UPIE v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(1)Word.word "
+
+
+definition get_Ustatus_UIE :: " Ustatus \<Rightarrow>(1)Word.word " where
+ " get_Ustatus_UIE v = ( (subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Ustatus "
+
+
+definition set_Ustatus_UIE :: "((regstate),(register_value),(Ustatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Ustatus_UIE r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Ustatus))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Ustatus_UIE :: " Ustatus \<Rightarrow>(1)Word.word \<Rightarrow> Ustatus " where
+ " update_Ustatus_UIE v x = (
+ (v (|
+ Ustatus_Ustatus_chunk_0 :=
+ ((update_subrange_vec_dec(Ustatus_Ustatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Ustatus "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_sstatus : Sstatus -> Ustatus\<close>\<close>
+
+definition lower_sstatus :: " Sstatus \<Rightarrow> Ustatus " where
+ " lower_sstatus s = (
+ (let u = (Mk_Ustatus ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let u = (update_Ustatus_UPIE u ((get_Sstatus_UPIE s :: 1 Word.word))) in
+ update_Ustatus_UIE u ((get_Sstatus_UIE s :: 1 Word.word)))))"
+ for s :: " Sstatus "
+
+
+\<comment> \<open>\<open>val lift_ustatus : Sstatus -> Ustatus -> Sstatus\<close>\<close>
+
+definition lift_ustatus :: " Sstatus \<Rightarrow> Ustatus \<Rightarrow> Sstatus " where
+ " lift_ustatus (s :: Sstatus) (u :: Ustatus) = (
+ (let s = (update_Sstatus_UPIE s ((get_Ustatus_UPIE u :: 1 Word.word))) in
+ update_Sstatus_UIE s ((get_Ustatus_UIE u :: 1 Word.word))))"
+ for s :: " Sstatus "
+ and u :: " Ustatus "
+
+
+\<comment> \<open>\<open>val legalize_ustatus : Mstatus -> mword ty64 -> M Mstatus\<close>\<close>
+
+definition legalize_ustatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Mstatus),(exception))monad " where
+ " legalize_ustatus (m :: Mstatus) (v :: xlenbits) = (
+ (let u = (Mk_Ustatus v) in
+ (let s = (lower_mstatus m) in
+ (let s = (lift_ustatus s u) in
+ lift_sstatus m s))))"
+ for m :: " Mstatus "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_Uinterrupts : mword ty64 -> Uinterrupts\<close>\<close>
+
+definition Mk_Uinterrupts :: "(64)Word.word \<Rightarrow> Uinterrupts " where
+ " Mk_Uinterrupts v = (
+ (| Uinterrupts_Uinterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_Uinterrupts_bits : Uinterrupts -> mword ty64\<close>\<close>
+
+definition get_Uinterrupts_bits :: " Uinterrupts \<Rightarrow>(64)Word.word " where
+ " get_Uinterrupts_bits v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val _set_Uinterrupts_bits : register_ref regstate register_value Uinterrupts -> mword ty64 -> M unit\<close>\<close>
+
+definition set_Uinterrupts_bits :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_Uinterrupts_bits : Uinterrupts -> mword ty64 -> Uinterrupts\<close>\<close>
+
+definition update_Uinterrupts_bits :: " Uinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_bits v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(64)Word.word "
+
+
+definition get_Uinterrupts_UEI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_UEI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_UEI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_UEI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_UEI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_UEI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Uinterrupts_UTI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_UTI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_UTI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_UTI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_UTI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_UTI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+definition get_Uinterrupts_USI :: " Uinterrupts \<Rightarrow>(1)Word.word " where
+ " get_Uinterrupts_USI v = (
+ (subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " Uinterrupts "
+
+
+definition set_Uinterrupts_USI :: "((regstate),(register_value),(Uinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_Uinterrupts_USI r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(Uinterrupts))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_Uinterrupts_USI :: " Uinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Uinterrupts " where
+ " update_Uinterrupts_USI v x = (
+ (v (|
+ Uinterrupts_Uinterrupts_chunk_0 :=
+ ((update_subrange_vec_dec(Uinterrupts_Uinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " Uinterrupts "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val lower_sip : Sinterrupts -> Sinterrupts -> Uinterrupts\<close>\<close>
+
+definition lower_sip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts " where
+ " lower_sip (s :: Sinterrupts) (d :: Sinterrupts) = (
+ (let (u :: Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s :: 1 Word.word)) ((get_Sinterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s :: 1 Word.word)) ((get_Sinterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s :: 1 Word.word)) ((get_Sinterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word))))))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val lower_sie : Sinterrupts -> Sinterrupts -> Uinterrupts\<close>\<close>
+
+definition lower_sie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts " where
+ " lower_sie (s :: Sinterrupts) (d :: Sinterrupts) = (
+ (let (u :: Uinterrupts) =
+ (Mk_Uinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UEI u
+ ((and_vec ((get_Sinterrupts_UEI s :: 1 Word.word)) ((get_Sinterrupts_UEI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ (let u =
+ (update_Uinterrupts_UTI u
+ ((and_vec ((get_Sinterrupts_UTI s :: 1 Word.word)) ((get_Sinterrupts_UTI d :: 1 Word.word))
+ :: 1 Word.word))) in
+ update_Uinterrupts_USI u
+ ((and_vec ((get_Sinterrupts_USI s :: 1 Word.word)) ((get_Sinterrupts_USI d :: 1 Word.word))
+ :: 1 Word.word))))))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val lift_uip : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts\<close>\<close>
+
+definition lift_uip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts \<Rightarrow> Sinterrupts " where
+ " lift_uip (o1 :: Sinterrupts) (d :: Sinterrupts) (u :: Uinterrupts) = (
+ (let (s :: Sinterrupts) = o1 in
+ if (((((get_Sinterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u :: 1 Word.word))
+ else s))"
+ for o1 :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and u :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_uip : Sinterrupts -> Sinterrupts -> mword ty64 -> Sinterrupts\<close>\<close>
+
+definition legalize_uip :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Sinterrupts " where
+ " legalize_uip (s :: Sinterrupts) (d :: Sinterrupts) (v :: xlenbits) = (
+ lift_uip s d ((Mk_Uinterrupts v)))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val lift_uie : Sinterrupts -> Sinterrupts -> Uinterrupts -> Sinterrupts\<close>\<close>
+
+definition lift_uie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Uinterrupts \<Rightarrow> Sinterrupts " where
+ " lift_uie (o1 :: Sinterrupts) (d :: Sinterrupts) (u :: Uinterrupts) = (
+ (let (s :: Sinterrupts) = o1 in
+ (let s =
+ (if (((((get_Sinterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_UEI s ((get_Uinterrupts_UEI u :: 1 Word.word))
+ else s) in
+ (let s =
+ (if (((((get_Sinterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_UTI s ((get_Uinterrupts_UTI u :: 1 Word.word))
+ else s) in
+ if (((((get_Sinterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ update_Sinterrupts_USI s ((get_Uinterrupts_USI u :: 1 Word.word))
+ else s))))"
+ for o1 :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and u :: " Uinterrupts "
+
+
+\<comment> \<open>\<open>val legalize_uie : Sinterrupts -> Sinterrupts -> mword ty64 -> Sinterrupts\<close>\<close>
+
+definition legalize_uie :: " Sinterrupts \<Rightarrow> Sinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Sinterrupts " where
+ " legalize_uie (s :: Sinterrupts) (d :: Sinterrupts) (v :: xlenbits) = (
+ lift_uie s d ((Mk_Uinterrupts v)))"
+ for s :: " Sinterrupts "
+ and d :: " Sinterrupts "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val handle_trap_extension : Privilege -> mword ty64 -> maybe unit -> unit\<close>\<close>
+
+definition handle_trap_extension :: " Privilege \<Rightarrow>(64)Word.word \<Rightarrow>(unit)option \<Rightarrow> unit " where
+ " handle_trap_extension (p :: Privilege) (pc :: xlenbits) (u :: unit option) = ( () )"
+ for p :: " Privilege "
+ and pc :: "(64)Word.word "
+ and u :: "(unit)option "
+
+
+\<comment> \<open>\<open>val prepare_trap_vector : Privilege -> Mcause -> M (mword ty64)\<close>\<close>
+
+definition prepare_trap_vector :: " Privilege \<Rightarrow> Mcause \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " prepare_trap_vector (p :: Privilege) (cause :: Mcause) = (
+ (case p of
+ Machine => read_reg mtvec_ref
+ | Supervisor => read_reg stvec_ref
+ | User => read_reg utvec_ref
+ ) \<bind> (\<lambda> (tvec :: Mtvec) .
+ (case ((tvec_addr tvec cause :: ( 64 Word.word)option)) of
+ Some (epc) => return epc
+ | None => (internal_error (''Invalid tvec mode'') :: ( 64 Word.word) M)
+ )))"
+ for p :: " Privilege "
+ and cause :: " Mcause "
+
+
+\<comment> \<open>\<open>val get_xret_target : Privilege -> M (mword ty64)\<close>\<close>
+
+fun get_xret_target :: " Privilege \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_xret_target Machine = ( (read_reg mepc_ref :: ( 64 Word.word) M))"
+|" get_xret_target Supervisor = ( (read_reg sepc_ref :: ( 64 Word.word) M))"
+|" get_xret_target User = ( (read_reg uepc_ref :: ( 64 Word.word) M))"
+
+
+\<comment> \<open>\<open>val set_xret_target : Privilege -> mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition set_xret_target :: " Privilege \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " set_xret_target p value1 = (
+ (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> target .
+ (case p of
+ Machine => write_reg mepc_ref target
+ | Supervisor => write_reg sepc_ref target
+ | User => write_reg uepc_ref target
+ ) \<then>
+ return target))"
+ for p :: " Privilege "
+ and value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val prepare_xret_target : Privilege -> M (mword ty64)\<close>\<close>
+
+definition prepare_xret_target :: " Privilege \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " prepare_xret_target p = ( (get_xret_target p :: ( 64 Word.word) M))"
+ for p :: " Privilege "
+
+
+\<comment> \<open>\<open>val get_mtvec : unit -> M (mword ty64)\<close>\<close>
+
+definition get_mtvec :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_mtvec _ = (
+ read_reg mtvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 64 Word.word))))"
+
+
+\<comment> \<open>\<open>val get_stvec : unit -> M (mword ty64)\<close>\<close>
+
+definition get_stvec :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_stvec _ = (
+ read_reg stvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 64 Word.word))))"
+
+
+\<comment> \<open>\<open>val get_utvec : unit -> M (mword ty64)\<close>\<close>
+
+definition get_utvec :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " get_utvec _ = (
+ read_reg utvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) . return ((get_Mtvec_bits w__0 :: 64 Word.word))))"
+
+
+\<comment> \<open>\<open>val set_mtvec : mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition set_mtvec :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " set_mtvec value1 = (
+ read_reg mtvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg mtvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg mtvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 64 Word.word)))))"
+ for value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val set_stvec : mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition set_stvec :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " set_stvec value1 = (
+ read_reg stvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg stvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg stvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 64 Word.word)))))"
+ for value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val set_utvec : mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition set_utvec :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " set_utvec value1 = (
+ read_reg utvec_ref \<bind> (\<lambda> (w__0 :: Mtvec) .
+ (write_reg utvec_ref ((legalize_tvec w__0 value1)) \<then>
+ read_reg utvec_ref) \<bind> (\<lambda> (w__1 :: Mtvec) . return ((get_Mtvec_bits w__1 :: 64 Word.word)))))"
+ for value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val is_NExt_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition is_NExt_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " is_NExt_CSR_defined (csr :: 12 bits) (p :: Privilege) = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ haveUsrMode ()
+ else return False))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val read_NExt_CSR : mword ty12 -> M (maybe (mword ty64))\<close>\<close>
+
+definition read_NExt_CSR :: "(12)Word.word \<Rightarrow>((register_value),(((64)Word.word)option),(exception))monad " where
+ " read_NExt_CSR csr = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ return (Some ((get_Ustatus_bits ((lower_sstatus ((lower_mstatus w__0)))) :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__2 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__3 :: Sinterrupts) .
+ return (Some ((get_Uinterrupts_bits ((lower_sie ((lower_mie w__1 w__2)) w__3)) :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_utvec () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . return (Some w__4))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg uscratch_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) . return (Some w__5))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target User :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ return (Some ((and_vec w__6 w__7 :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg ucause_ref \<bind> (\<lambda> (w__8 :: Mcause) .
+ return (Some ((get_Mcause_bits w__8 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg utval_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . return (Some w__9))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__10 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__11 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__12 :: Sinterrupts) .
+ return (Some ((get_Uinterrupts_bits ((lower_sip ((lower_mip w__10 w__11)) w__12))
+ :: 64 Word.word))))))
+ else return None))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val write_NExt_CSR : mword ty12 -> mword ty64 -> M bool\<close>\<close>
+
+definition write_NExt_CSR :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " write_NExt_CSR (csr :: csreg) (value1 :: xlenbits) = (
+ (let b__0 = csr in
+ (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ legalize_ustatus w__0 value1 \<bind> (\<lambda> (w__1 :: Mstatus) .
+ (write_reg mstatus_ref w__1 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__2 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__3 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__4 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__5 :: Sinterrupts) .
+ (let sie = (legalize_uie ((lower_mie w__3 w__4)) w__5 value1) in
+ read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) .
+ lift_sie w__6 w__7 sie \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ (write_reg mie_ref w__8 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__9 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__9 :: 64 Word.word)))))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_utvec value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) . return (Some w__10))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg uscratch_ref value1 \<then>
+ (read_reg uscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__11 :: 64 Word.word) . return (Some w__11))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target User value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ return (Some w__12))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits ucause_ref value1 \<then>
+ read_reg ucause_ref) \<bind> (\<lambda> (w__13 :: Mcause) .
+ return (Some ((get_Mcause_bits w__13 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg utval_ref value1 \<then>
+ (read_reg utval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) . return (Some w__14))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__15 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) .
+ (let sip = (legalize_uip ((lower_mip w__15 w__16)) w__17 value1) in
+ read_reg mip_ref \<bind> (\<lambda> (w__18 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__19 :: Minterrupts) .
+ lift_sip w__18 w__19 sip \<bind> (\<lambda> (w__20 :: Minterrupts) .
+ (write_reg mip_ref w__20 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__21 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__21 :: 64 Word.word)))))))))))
+ else return None) \<bind> (\<lambda> (res :: xlenbits option) .
+ return ((case res of
+ Some (v) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr))
+ (((@) ('' <- '')
+ (((@) ((string_of_bits v))
+ (((@) ('' (input: '') (((@) ((string_of_bits value1)) ('')'')))))))))))))
+ else () ) in
+ True)
+ | None => False
+ )))))"
+ for csr :: "(12)Word.word "
+ and value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val ext_is_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition ext_is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " ext_is_CSR_defined (csr :: csreg) (p :: Privilege) = ( is_NExt_CSR_defined csr p )"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val ext_read_CSR : mword ty12 -> M (maybe (mword ty64))\<close>\<close>
+
+definition ext_read_CSR :: "(12)Word.word \<Rightarrow>((register_value),(((64)Word.word)option),(exception))monad " where
+ " ext_read_CSR csr = ( (read_NExt_CSR csr :: ( ( 64 Word.word)option) M))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val ext_write_CSR : mword ty12 -> mword ty64 -> M bool\<close>\<close>
+
+definition ext_write_CSR :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " ext_write_CSR (csr :: csreg) (value1 :: xlenbits) = ( write_NExt_CSR csr value1 )"
+ for csr :: "(12)Word.word "
+ and value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val csrAccess : mword ty12 -> mword ty2\<close>\<close>
+
+definition csrAccess :: "(12)Word.word \<Rightarrow>(2)Word.word " where
+ " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val csrPriv : mword ty12 -> mword ty2\<close>\<close>
+
+definition csrPriv :: "(12)Word.word \<Rightarrow>(2)Word.word " where
+ " csrPriv csr = ( (subrange_vec_dec csr (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val is_CSR_defined : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " is_CSR_defined (csr :: csreg) (p :: Privilege) = (
+ (let b__0 = csr in
+ if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM ((haveSupMode () ))
+ (return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ return ((((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) \<and> ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))))))
+ else ext_is_CSR_defined csr p))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool\<close>\<close>
+
+definition check_CSR_access :: "(2)Word.word \<Rightarrow>(2)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool " where
+ " check_CSR_access csrrw csrpr p isWrite = (
+ (((\<not> ((((((isWrite = True))) \<and> (((csrrw = (vec_of_bits [B1,B1] :: 2 Word.word))))))))) \<and> ((zopz0zKzJ_u ((privLevel_to_bits p :: 2 Word.word)) csrpr))))"
+ for csrrw :: "(2)Word.word "
+ and csrpr :: "(2)Word.word "
+ and p :: " Privilege "
+ and isWrite :: " bool "
+
+
+\<comment> \<open>\<open>val check_TVM_SATP : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition check_TVM_SATP :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_TVM_SATP (csr :: csreg) (p :: Privilege) = (
+ and_boolM
+ (return (((csr = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))))
+ (and_boolM
+ (return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ return (((((get_Mstatus_TVM w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> (w__2 ::
+ bool) .
+ return ((\<not> w__2))))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_Counteren : mword ty12 -> Privilege -> M bool\<close>\<close>
+
+definition check_Counteren :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_Counteren (csr :: csreg) (p :: Privilege) = (
+ (case (csr, p) of
+ (b__0, Supervisor) =>
+ if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__0 :: Counteren) .
+ return (((((get_Counteren_CY w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__1 :: Counteren) .
+ return (((((get_Counteren_TM w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__2 :: Counteren) .
+ return (((((get_Counteren_IR w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))
+ else
+ return ((case (b__0, Supervisor) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True
+ ))
+ | (b__3, User) =>
+ if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__6 :: Counteren) .
+ return (((((get_Counteren_CY w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__7 :: bool) . return ((\<not> w__7))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__8 :: Counteren) .
+ return (((((get_Counteren_CY w__8 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__11 :: Counteren) .
+ return (((((get_Counteren_TM w__11 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__12 :: bool) . return ((\<not> w__12))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__13 :: Counteren) .
+ return (((((get_Counteren_TM w__13 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ and_boolM
+ (read_reg mcounteren_ref \<bind> (\<lambda> (w__16 :: Counteren) .
+ return (((((get_Counteren_IR w__16 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))
+ (or_boolM (haveSupMode () \<bind> (\<lambda> (w__17 :: bool) . return ((\<not> w__17))))
+ (read_reg scounteren_ref \<bind> (\<lambda> (w__18 :: Counteren) .
+ return (((((get_Counteren_IR w__18 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))
+ else
+ return ((case (b__3, User) of
+ (_, _) =>
+ if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True
+ ))
+ | (_, _) =>
+ return (if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)
+ csr)) \<and> ((zopz0zIzJ_u csr
+ (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then
+ False
+ else True)
+ ))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val check_CSR : mword ty12 -> Privilege -> bool -> M bool\<close>\<close>
+
+definition check_CSR :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " check_CSR (csr :: csreg) (p :: Privilege) (isWrite :: bool) = (
+ and_boolM ((is_CSR_defined csr p))
+ (and_boolM
+ (return ((check_CSR_access ((csrAccess csr :: 2 Word.word)) ((csrPriv csr :: 2 Word.word)) p
+ isWrite))) (and_boolM ((check_TVM_SATP csr p)) ((check_Counteren csr p)))))"
+ for csr :: "(12)Word.word "
+ and p :: " Privilege "
+ and isWrite :: " bool "
+
+
+\<comment> \<open>\<open>val exception_delegatee : ExceptionType -> Privilege -> M Privilege\<close>\<close>
+
+definition exception_delegatee :: " ExceptionType \<Rightarrow> Privilege \<Rightarrow>((register_value),(Privilege),(exception))monad " where
+ " exception_delegatee (e :: ExceptionType) (p :: Privilege) = (
+ (let idx = (num_of_ExceptionType e) in
+ read_reg medeleg_ref \<bind> (\<lambda> (w__0 :: Medeleg) .
+ (let super = (access_vec_dec ((get_Medeleg_bits w__0 :: 64 Word.word)) idx) in
+ haveSupMode () \<bind> (\<lambda> (w__1 :: bool) .
+ (if w__1 then
+ and_boolM (return ((bit_to_bool super)))
+ (and_boolM ((haveNExt () ))
+ (read_reg sedeleg_ref \<bind> (\<lambda> (w__3 :: Sedeleg) .
+ return ((bit_to_bool ((access_vec_dec ((get_Sedeleg_bits w__3 :: 64 Word.word)) idx)))))))
+ else and_boolM (return ((bit_to_bool super))) ((haveNExt () ))) \<bind> (\<lambda> user .
+ and_boolM ((haveUsrMode () )) (return user) \<bind> (\<lambda> w__9 .
+ (if w__9 then return User
+ else
+ and_boolM ((haveSupMode () )) (return ((bit_to_bool super))) \<bind> (\<lambda> (w__11 :: bool) .
+ return (if w__11 then Supervisor
+ else Machine))) \<bind> (\<lambda> deleg .
+ return (if ((zopz0zI_u ((privLevel_to_bits deleg :: 2 Word.word))
+ ((privLevel_to_bits p :: 2 Word.word)))) then
+ p
+ else deleg)))))))))"
+ for e :: " ExceptionType "
+ and p :: " Privilege "
+
+
+\<comment> \<open>\<open>val findPendingInterrupt : mword ty64 -> maybe InterruptType\<close>\<close>
+
+definition findPendingInterrupt :: "(64)Word.word \<Rightarrow>(InterruptType)option " where
+ " findPendingInterrupt ip = (
+ (let ip = (Mk_Minterrupts ip) in
+ if (((((get_Minterrupts_MEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ Some I_M_External
+ else if (((((get_Minterrupts_MSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_M_Software
+ else if (((((get_Minterrupts_MTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_M_Timer
+ else if (((((get_Minterrupts_SEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_External
+ else if (((((get_Minterrupts_SSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_Software
+ else if (((((get_Minterrupts_STI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_S_Timer
+ else if (((((get_Minterrupts_UEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_External
+ else if (((((get_Minterrupts_USI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_Software
+ else if (((((get_Minterrupts_UTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Some I_U_Timer
+ else None))"
+ for ip :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val processPending : Minterrupts -> Minterrupts -> mword ty64 -> bool -> interrupt_set\<close>\<close>
+
+definition processPending :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> bool \<Rightarrow> interrupt_set " where
+ " processPending (xip :: Minterrupts) (xie :: Minterrupts) (xideleg :: xlenbits) (priv_enabled :: bool) = (
+ (let effective_pend =
+ ((and_vec ((get_Minterrupts_bits xip :: 64 Word.word))
+ ((and_vec ((get_Minterrupts_bits xie :: 64 Word.word)) ((not_vec xideleg :: 64 Word.word))
+ :: 64 Word.word))
+ :: 64 Word.word)) in
+ (let effective_delg = ((and_vec ((get_Minterrupts_bits xip :: 64 Word.word)) xideleg :: 64 Word.word)) in
+ if (((priv_enabled \<and> (((effective_pend \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))))))))
+ then
+ Ints_Pending effective_pend
+ else if (((effective_delg \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))
+ then
+ Ints_Delegated effective_delg
+ else Ints_Empty () )))"
+ for xip :: " Minterrupts "
+ and xie :: " Minterrupts "
+ and xideleg :: "(64)Word.word "
+ and priv_enabled :: " bool "
+
+
+\<comment> \<open>\<open>val getPendingSet : Privilege -> M (maybe ((mword ty64 * Privilege)))\<close>\<close>
+
+definition getPendingSet :: " Privilege \<Rightarrow>((register_value),(((64)Word.word*Privilege)option),(exception))monad " where
+ " getPendingSet priv = (
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ (assert_exp w__0 (''no user mode: M/U or M/S/U system required'') \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__2 :: Minterrupts) .
+ (let effective_pending =
+ ((and_vec ((get_Minterrupts_bits w__1 :: 64 Word.word))
+ ((get_Minterrupts_bits w__2 :: 64 Word.word))
+ :: 64 Word.word)) in
+ if (((effective_pending = ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))
+ then
+ return None
+ else
+ or_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) \<noteq> ((privLevel_to_bits Machine :: 2 Word.word))))))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) .
+ return (((((get_Mstatus_MIE w__3 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> mIE .
+ and_boolM ((haveSupMode () ))
+ (or_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__6 :: Mstatus) .
+ return (((((get_Mstatus_SIE w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))) \<bind> (\<lambda> sIE .
+ and_boolM ((haveNExt () ))
+ (and_boolM
+ (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) .
+ return (((((get_Mstatus_UIE w__10 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> uIE .
+ read_reg mip_ref \<bind> (\<lambda> (w__12 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__13 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__14 :: Minterrupts) .
+ (case ((processPending w__12 w__13 ((get_Minterrupts_bits w__14 :: 64 Word.word)) mIE)) of
+ Ints_Empty (_) => return None
+ | Ints_Pending (p) =>
+ (let r = (p, Machine) in
+ return (Some r))
+ | Ints_Delegated (d) =>
+ haveSupMode () \<bind> (\<lambda> (w__15 :: bool) .
+ if ((\<not> w__15)) then
+ return (if uIE then
+ (let r = (d, User) in
+ Some r)
+ else None)
+ else
+ read_reg mie_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) .
+ return ((case ((processPending ((Mk_Minterrupts d)) w__16
+ ((get_Sinterrupts_bits w__17 :: 64 Word.word)) sIE)) of
+ Ints_Empty (_) => None
+ | Ints_Pending (p) =>
+ (let r = (p, Supervisor) in
+ Some r)
+ | Ints_Delegated (d) =>
+ if uIE then
+ (let r = (d, User) in
+ Some r)
+ else None
+ )))))
+ ))))))))))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val dispatchInterrupt : Privilege -> M (maybe ((InterruptType * Privilege)))\<close>\<close>
+
+definition dispatchInterrupt :: " Privilege \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad " where
+ " dispatchInterrupt priv = (
+ or_boolM (haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0))))
+ (and_boolM (haveSupMode () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1))))
+ (haveNExt () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (assert_exp (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) (''invalid current privilege'') \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__5 :: Minterrupts) .
+ read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) .
+ (let enabled_pending =
+ ((and_vec ((get_Minterrupts_bits w__5 :: 64 Word.word))
+ ((get_Minterrupts_bits w__6 :: 64 Word.word))
+ :: 64 Word.word)) in
+ return ((case ((findPendingInterrupt enabled_pending)) of
+ Some (i) =>
+ (let r = (i, Machine) in
+ Some r)
+ | None => None
+ )))))
+ else
+ (getPendingSet priv :: ( (( 64 Word.word * Privilege))option) M) \<bind> (\<lambda> (w__7 ::
+ (( 64 Word.word * Privilege))option) .
+ return ((case w__7 of
+ None => None
+ | Some ((ip, p)) =>
+ (case ((findPendingInterrupt ip)) of
+ None => None
+ | Some (i) =>
+ (let r = (i, p) in
+ Some r)
+ )
+ )))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val tval : maybe (mword ty64) -> mword ty64\<close>\<close>
+
+fun tval :: "((64)Word.word)option \<Rightarrow>(64)Word.word " where
+ " tval (Some (e)) = ( e )"
+ for e :: "(64)Word.word "
+|" tval None = ( (EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))"
+
+
+\<comment> \<open>\<open>val rvfi_trap : unit -> unit\<close>\<close>
+
+definition rvfi_trap :: " unit \<Rightarrow> unit " where
+ " rvfi_trap _ = ( () )"
+
+
+\<comment> \<open>\<open>val trap_handler : Privilege -> bool -> mword ty8 -> mword ty64 -> maybe (mword ty64) -> maybe unit -> M (mword ty64)\<close>\<close>
+
+definition trap_handler :: " Privilege \<Rightarrow> bool \<Rightarrow>(8)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(xlenbits)option \<Rightarrow>(ext_exception)option \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " trap_handler (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info ::
+ xlenbits option) (ext :: ext_exception option) = (
+ (let (_ :: unit) = (rvfi_trap () ) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''handling '')
+ (((@) (if intr then (''int#'') else (''exc#''))
+ (((@) ((string_of_bits c))
+ (((@) ('' at priv '')
+ (((@) ((privLevel_to_str del_priv))
+ (((@) ('' with tval '')
+ ((string_of_bits ((tval info :: 64 Word.word))))))))))))))))
+ else () ) in
+ (let (_ :: unit) = (cancel_reservation () ) in
+ (case del_priv of
+ Machine =>
+ ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr :: 1 Word.word)) \<then>
+ set_Mcause_Cause mcause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__0 :: Mstatus) .
+ ((set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 :: 1 Word.word)) \<then>
+ set_Mstatus_MIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__1 :: Privilege) .
+ (((set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 :: 2 Word.word)) \<then>
+ write_reg mtval_ref ((tval info :: 64 Word.word))) \<then>
+ write_reg mepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__2 :: 64 Word.word)))))))))
+ else return () ) \<then>
+ read_reg mcause_ref) \<bind> (\<lambda> (w__3 :: Mcause) .
+ (prepare_trap_vector del_priv w__3 :: ( 64 Word.word) M))))))
+ | Supervisor =>
+ haveSupMode () \<bind> (\<lambda> (w__5 :: bool) .
+ (((assert_exp w__5 (''no supervisor mode present for delegation'') \<then>
+ set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr :: 1 Word.word))) \<then>
+ set_Mcause_Cause scause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) .
+ ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 :: 1 Word.word)) \<then>
+ set_Mstatus_SIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) .
+ (case w__7 of
+ User => return ((bool_to_bits False :: 1 Word.word))
+ | Supervisor => return ((bool_to_bits True :: 1 Word.word))
+ | Machine => (internal_error (''invalid privilege for s-mode trap'') :: ( 1 Word.word) M)
+ ) \<bind> (\<lambda> (w__9 :: 1 Word.word) .
+ (((set_Mstatus_SPP mstatus_ref w__9 \<then>
+ write_reg stval_ref ((tval info :: 64 Word.word))) \<then>
+ write_reg sepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__10 :: 64 Word.word)))))))))
+ else return () ) \<then>
+ read_reg scause_ref) \<bind> (\<lambda> (w__11 :: Mcause) .
+ (prepare_trap_vector del_priv w__11 :: ( 64 Word.word) M))))))))
+ | User =>
+ haveUsrMode () \<bind> (\<lambda> (w__13 :: bool) .
+ (((assert_exp w__13 (''no user mode present for delegation'') \<then>
+ set_Mcause_IsInterrupt ucause_ref ((bool_to_bits intr :: 1 Word.word))) \<then>
+ set_Mcause_Cause ucause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__14 :: Mstatus) .
+ ((((set_Mstatus_UPIE mstatus_ref ((get_Mstatus_UIE w__14 :: 1 Word.word)) \<then>
+ set_Mstatus_UIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ write_reg utval_ref ((tval info :: 64 Word.word))) \<then>
+ write_reg uepc_ref pc) \<then>
+ write_reg cur_privilege_ref del_priv) \<then>
+ ((let (_ :: unit) = (handle_trap_extension del_priv pc ext) in
+ ((if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__15 :: 64 Word.word)))))))))
+ else return () ) \<then>
+ read_reg ucause_ref) \<bind> (\<lambda> (w__16 :: Mcause) .
+ (prepare_trap_vector del_priv w__16 :: ( 64 Word.word) M))))))
+ )))))"
+ for del_priv :: " Privilege "
+ and intr :: " bool "
+ and c :: "(8)Word.word "
+ and pc :: "(64)Word.word "
+ and info :: "(xlenbits)option "
+ and ext :: "(ext_exception)option "
+
+
+\<comment> \<open>\<open>val exception_handler : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)\<close>\<close>
+
+definition exception_handler :: " Privilege \<Rightarrow> ctl_result \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " exception_handler (cur_priv :: Privilege) (ctl :: ctl_result) (pc :: xlenbits) = (
+ (case (cur_priv, ctl) of
+ (_, CTL_TRAP (e)) =>
+ exception_delegatee(sync_exception_trap e) cur_priv \<bind> (\<lambda> del_priv .
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''trapping from '')
+ (((@) ((privLevel_to_str cur_priv))
+ (((@) ('' to '')
+ (((@) ((privLevel_to_str del_priv))
+ (((@) ('' to handle '')
+ ((exceptionType_to_str(sync_exception_trap e)))))))))))))
+ else () ) in
+ (trap_handler del_priv False ((exceptionType_to_bits(sync_exception_trap e) :: 8 Word.word)) pc(sync_exception_excinfo
+ e)(sync_exception_ext_exception e)
+ :: ( 64 Word.word) M)))
+ | (_, CTL_MRET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ ((set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 :: 1 Word.word)) \<then>
+ set_Mstatus_MPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word)) \<bind> (\<lambda> (w__3 :: Privilege) .
+ (write_reg cur_privilege_ref w__3 \<then>
+ haveUsrMode () ) \<bind> (\<lambda> (w__4 :: bool) .
+ ((set_Mstatus_MPP mstatus_ref
+ ((privLevel_to_bits (if w__4 then User else Machine) :: 2 Word.word)) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__5 :: 64 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__6 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__6)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target Machine :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) .
+ return ((and_vec w__7 w__8 :: 64 Word.word)))))))))))
+ | (_, CTL_SRET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__9 :: Mstatus) .
+ ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__9 :: 1 Word.word)) \<then>
+ set_Mstatus_SPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__10 :: Mstatus) .
+ (((write_reg
+ cur_privilege_ref
+ (if (((((get_Mstatus_SPP w__10 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))
+ then
+ Supervisor
+ else User) \<then>
+ set_Mstatus_SPP mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__11 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__11 :: 64 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__12 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__12)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target Supervisor :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 Word.word) .
+ return ((and_vec w__13 w__14 :: 64 Word.word)))))))))
+ | (_, CTL_URET (_)) =>
+ read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) .
+ ((((set_Mstatus_UIE mstatus_ref ((get_Mstatus_UPIE w__15 :: 1 Word.word)) \<then>
+ set_Mstatus_UPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ write_reg cur_privilege_ref User) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__16 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ ((string_of_bits ((get_Mstatus_bits w__16 :: 64 Word.word)))))))))
+ else return () )) \<then>
+ (if ((get_config_print_platform () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__17 :: Privilege) .
+ return ((print_dbg
+ (((@) (''ret-ing from '')
+ (((@) ((privLevel_to_str prev_priv))
+ (((@) ('' to '') ((privLevel_to_str w__17)))))))))))
+ else return () )) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ (prepare_xret_target User :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 Word.word) .
+ return ((and_vec w__18 w__19 :: 64 Word.word))))))))
+ ))"
+ for cur_priv :: " Privilege "
+ and ctl :: " ctl_result "
+ and pc :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val handle_mem_exception : mword ty64 -> ExceptionType -> M unit\<close>\<close>
+
+definition handle_mem_exception :: "(64)Word.word \<Rightarrow> ExceptionType \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_mem_exception (addr :: xlenbits) (e :: ExceptionType) = (
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap = e,
+ sync_exception_excinfo = (Some addr),
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (exception_handler w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ set_next_pc w__2)))))"
+ for addr :: "(64)Word.word "
+ and e :: " ExceptionType "
+
+
+\<comment> \<open>\<open>val handle_interrupt : InterruptType -> Privilege -> M unit\<close>\<close>
+
+definition handle_interrupt :: " InterruptType \<Rightarrow> Privilege \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_interrupt (i :: InterruptType) (del_priv :: Privilege) = (
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (trap_handler del_priv True ((interruptType_to_bits i :: 8 Word.word)) w__0 None None
+ :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ set_next_pc w__1)))"
+ for i :: " InterruptType "
+ and del_priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val init_sys : unit -> M unit\<close>\<close>
+
+definition init_sys :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_sys _ = (
+ (((((((((write_reg cur_privilege_ref Machine \<then>
+ write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Misa_MXL misa_ref ((arch_to_bits RV64 :: 2 Word.word))) \<then>
+ set_Misa_A misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_C misa_ref ((bool_to_bits ((sys_enable_rvc () )) :: 1 Word.word))) \<then>
+ set_Misa_I misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_M misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_U misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ set_Misa_S misa_ref ((bool_to_bits True :: 1 Word.word))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__0 :: Mstatus) .
+ read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) .
+ (write_reg mstatus_ref ((set_mstatus_SXL w__0 ((get_Misa_MXL w__1 :: 2 Word.word)))) \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ read_reg misa_ref \<bind> (\<lambda> (w__3 :: Misa) .
+ ((((((((((((((((write_reg mstatus_ref ((set_mstatus_UXL w__2 ((get_Misa_MXL w__3 :: 2 Word.word)))) \<then>
+ set_Mstatus_SD mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ set_Minterrupts_bits mip_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Minterrupts_bits mie_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Medeleg_bits medeleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Mtvec_bits mtvec_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Mcause_bits mcause_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mepc_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mtval_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mscratch_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mcycle_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg mtime_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ set_Counteren_bits mcounteren_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then>
+ write_reg minstret_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then>
+ write_reg minstret_written_ref False) \<then>
+ init_pmp () ) \<then>
+ (if ((get_config_print_reg () )) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ return ((print_dbg
+ (((@) (''CSR mstatus <- '')
+ (((@) ((string_of_bits ((get_Mstatus_bits w__4 :: 64 Word.word))))
+ (((@) ('' (input: '')
+ (((@)
+ ((string_of_bits
+ ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))))
+ ('')''))))))))))))
+ else return () ))))))"
+
+
+\<comment> \<open>\<open>val elf_tohost : unit -> ii\<close>\<close>
+
+\<comment> \<open>\<open>val elf_entry : unit -> ii\<close>\<close>
+
+
+
+\<comment> \<open>\<open>val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))\<close>\<close>
+
+definition phys_mem_segments :: " unit \<Rightarrow>((64)Word.word*(64)Word.word)list " where
+ " phys_mem_segments _ = (
+ ((plat_rom_base () :: 64 Word.word), (plat_rom_size () :: 64 Word.word)) #
+ (((plat_ram_base () :: 64 Word.word), (plat_ram_size () :: 64 Word.word)) # []))"
+
+
+\<comment> \<open>\<open>val within_phys_mem : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_phys_mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_phys_mem (addr :: xlenbits) (width :: int) = (
+ (let addr_int = (Word.uint addr) in
+ (let ram_base_int = (Word.uint ((plat_ram_base () :: 64 Word.word))) in
+ (let rom_base_int = (Word.uint ((plat_rom_base () :: 64 Word.word))) in
+ (let ram_size_int = (Word.uint ((plat_ram_size () :: 64 Word.word))) in
+ (let rom_size_int = (Word.uint ((plat_rom_size () :: 64 Word.word))) in
+ if (((((ram_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le> ((ram_base_int + ram_size_int)))))))
+ then
+ True
+ else if (((((rom_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le>
+ ((rom_base_int + rom_size_int))))))) then
+ True
+ else
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) (''within_phys_mem: '')
+ (((@) ((string_of_bits addr)) ('' not within phys-mem:'')))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_rom_base: '') ((string_of_bits ((plat_rom_base () :: 64 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_rom_size: '') ((string_of_bits ((plat_rom_size () :: 64 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_ram_base: '') ((string_of_bits ((plat_ram_base () :: 64 Word.word))))))) in
+ (let (_ :: unit) =
+ (print_dbg
+ (((@) ('' plat_ram_size: '') ((string_of_bits ((plat_ram_size () :: 64 Word.word))))))) in
+ False)))))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_clint : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_clint :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_clint (addr :: xlenbits) (width :: int) = (
+ (let addr_int = (Word.uint addr) in
+ (let clint_base_int = (Word.uint ((plat_clint_base () :: 64 Word.word))) in
+ (let clint_size_int = (Word.uint ((plat_clint_size () :: 64 Word.word))) in
+ (((clint_base_int \<le> addr_int)) \<and> ((((addr_int + ((id0 width)))) \<le> ((clint_base_int + clint_size_int)))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_htif_writable : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_htif_writable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_htif_writable (addr :: xlenbits) (width :: int) = (
+ ((((((plat_htif_tohost () :: 64 Word.word)) = addr))) \<or> ((((((((add_vec_int ((plat_htif_tohost () :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) = addr))) \<and> (((width = (( 4 :: int)::ii)))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_htif_readable : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_htif_readable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_htif_readable (addr :: xlenbits) (width :: int) = (
+ ((((((plat_htif_tohost () :: 64 Word.word)) = addr))) \<or> ((((((((add_vec_int ((plat_htif_tohost () :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) = addr))) \<and> (((width = (( 4 :: int)::ii)))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+definition MSIP_BASE :: "(64)Word.word " where
+ " MSIP_BASE = (
+ (EXTZ (( 64 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 20 Word.word)
+ :: 64 Word.word))"
+
+
+definition MTIMECMP_BASE :: "(64)Word.word " where
+ " MTIMECMP_BASE = (
+ (EXTZ (( 64 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 20 Word.word)
+ :: 64 Word.word))"
+
+
+definition MTIMECMP_BASE_HI :: "(64)Word.word " where
+ " MTIMECMP_BASE_HI = (
+ (EXTZ (( 64 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 20 Word.word)
+ :: 64 Word.word))"
+
+
+definition MTIME_BASE :: "(64)Word.word " where
+ " MTIME_BASE = (
+ (EXTZ (( 64 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0] :: 20 Word.word)
+ :: 64 Word.word))"
+
+
+definition MTIME_BASE_HI :: "(64)Word.word " where
+ " MTIME_BASE_HI = (
+ (EXTZ (( 64 :: int)::ii)
+ (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0] :: 20 Word.word)
+ :: 64 Word.word))"
+
+
+\<comment> \<open>\<open>val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition clint_load :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " clint_load addr width = (
+ (let addr = ((sub_vec addr ((plat_clint_base () :: 64 Word.word)) :: 64 Word.word)) in
+ if ((((((addr = MSIP_BASE))) \<and> ((((((((id0 width)) = (( 8 :: int)::ii)))) \<or> (((((id0 width)) = (( 4 :: int)::ii)))))))))) then
+ ((if ((get_config_print_platform () )) then
+ read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits ((get_Minterrupts_MSI w__0 :: 1 Word.word)))))))))))))
+ else return () ) \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__1 :: Minterrupts) .
+ return (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 :: 1 Word.word))
+ (((( 8 :: int)::ii) * ((id0 width))))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits
+ ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__3 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint<8>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__4)))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__5 (( 64 :: int)::ii) :: 64 Word.word)) :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint-hi<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '')
+ ((string_of_bits
+ ((subrange_vec_dec w__6 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))))))))))))
+ else return () ) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__7 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__8)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__9 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__9 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__10)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__11 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__11 (( 64 :: int)::ii) :: 64 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((addr = MTIME_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ ((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__12)))))))))))
+ else return () ) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__13 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__13 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['') (((@) ((string_of_bits addr)) (''] -> <not-mapped>'')))))
+ else () ) in
+ return (MemException E_Load_Access_Fault))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val clint_dispatch : unit -> M unit\<close>\<close>
+
+definition clint_dispatch :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " clint_dispatch _ = (
+ (((if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg (((@) (''clint::tick mtime <- '') ((string_of_bits w__0)))))))
+ else return () ) \<then>
+ set_Minterrupts_MTI mip_ref ((bool_to_bits False :: 1 Word.word))) \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ if ((zopz0zIzJ_u w__1 w__2)) then
+ (if ((get_config_print_platform () )) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return ((print_dbg (((@) ('' clint timer pending at mtime '') ((string_of_bits w__3)))))))
+ else return () ) \<then>
+ set_Minterrupts_MTI mip_ref ((bool_to_bits True :: 1 Word.word))
+ else return () )))"
+
+
+\<comment> \<open>\<open>val clint_store : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition clint_store :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " clint_store addr width data = (
+ (let addr = ((sub_vec addr ((plat_clint_base () :: 64 Word.word)) :: 64 Word.word)) in
+ if ((((((addr = MSIP_BASE))) \<and> ((((((((id0 width)) = (( 8 :: int)::ii)))) \<or> (((((id0 width)) = (( 4 :: int)::ii)))))))))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '')
+ (((@) ((string_of_bits data))
+ (((@) ('' (mip.MSI <- '')
+ (((@)
+ ((string_of_bits
+ ((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word))))
+ ('')'')))))))))))))
+ else () ) in
+ (set_Minterrupts_MSI mip_ref
+ ((bool_to_bits
+ (((((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word))))
+ :: 1 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 8 :: int)::ii))))))) then
+ (let (data :: 64 Word.word) = ((Word.ucast data :: 64 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<8>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (write_reg mtimecmp_ref ((zero_extend data (( 64 :: int)::ii) :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True)))
+ else if ((((((addr = MTIMECMP_BASE))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (write_reg
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) ((zero_extend data (( 32 :: int)::ii) :: 32 Word.word))
+ :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))))
+ else if ((((((addr = MTIMECMP_BASE_HI))) \<and> (((((id0 width)) = (( 4 :: int)::ii))))))) then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint<4>['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))
+ else () ) in
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (write_reg
+ mtimecmp_ref
+ ((update_subrange_vec_dec w__1 (( 63 :: int)::ii) (( 32 :: int)::ii) ((zero_extend data (( 32 :: int)::ii) :: 32 Word.word))
+ :: 64 Word.word)) \<then>
+ clint_dispatch () ) \<then> return (MemValue True))))
+ else
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''clint['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] <- '') (((@) ((string_of_bits data)) ('' (<unmapped>)'')))))))))
+ else () ) in
+ return (MemException E_SAMO_Access_Fault))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val tick_clock : unit -> M unit\<close>\<close>
+
+definition tick_clock :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_clock _ = (
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word)) \<then>
+ (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg mtime_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)) \<then> clint_dispatch () )))"
+
+
+\<comment> \<open>\<open>val Mk_htif_cmd : mword ty64 -> htif_cmd\<close>\<close>
+
+definition Mk_htif_cmd :: "(64)Word.word \<Rightarrow> htif_cmd " where
+ " Mk_htif_cmd v = (
+ (| htif_cmd_htif_cmd_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_bits : htif_cmd -> mword ty64\<close>\<close>
+
+definition get_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word " where
+ " get_htif_cmd_bits v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit\<close>\<close>
+
+definition set_htif_cmd_bits :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_bits v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_device : htif_cmd -> mword ty8\<close>\<close>
+
+definition get_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word " where
+ " get_htif_cmd_device v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit\<close>\<close>
+
+definition set_htif_cmd_device :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_device r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 56 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_device v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_cmd : htif_cmd -> mword ty8\<close>\<close>
+
+definition get_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word " where
+ " get_htif_cmd_cmd v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii) :: 8 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit\<close>\<close>
+
+definition set_htif_cmd_cmd :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_cmd r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 55 :: int)::ii) (( 48 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_cmd v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_htif_cmd_payload : htif_cmd -> mword ty48\<close>\<close>
+
+definition get_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word " where
+ " get_htif_cmd_payload v = (
+ (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))"
+ for v :: " htif_cmd "
+
+
+\<comment> \<open>\<open>val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit\<close>\<close>
+
+definition set_htif_cmd_payload :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_htif_cmd_payload r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(htif_cmd))register_ref "
+ and v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd\<close>\<close>
+
+definition update_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word \<Rightarrow> htif_cmd " where
+ " update_htif_cmd_payload v x = (
+ (v (|
+ htif_cmd_htif_cmd_chunk_0 :=
+ ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " htif_cmd "
+ and x :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val htif_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition htif_load :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " htif_load addr width = (
+ (if ((get_config_print_platform () )) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg
+ (((@) (''htif['')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits w__0)))))))))))
+ else return () ) \<then>
+ (if ((((((width = (( 8 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 64 Word.word)))))))) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ return (MemValue ((Word.ucast ((zero_extend w__1 (( 64 :: int)::ii) :: 64 Word.word)) :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 64 Word.word))))))))
+ then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((add_vec_int ((plat_htif_tohost () :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word))))))))
+ then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ return (MemValue ((Word.ucast
+ ((zero_extend ((subrange_vec_dec w__3 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))
+ (( 32 :: int)::ii)
+ :: 32 Word.word))
+ :: ( 'int8_times_n::len)Word.word))))
+ else return (MemException E_Load_Access_Fault)))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val htif_store : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition htif_store :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " htif_store addr width data = (
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif['')
+ (((@) ((string_of_bits addr)) (((@) (''] <- '') ((string_of_bits data))))))))
+ else () ) in
+ ((if (((width = (( 8 :: int)::ii)))) then
+ (let (data :: 64 Word.word) = ((Word.ucast data :: 64 Word.word)) in
+ write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) data :: 64 Word.word)))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((plat_htif_tohost () :: 64 Word.word))))))))
+ then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ write_reg htif_tohost_ref ((update_subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) data :: 64 Word.word))))
+ else if ((((((width = (( 4 :: int)::ii)))) \<and> (((addr = ((add_vec_int ((plat_htif_tohost () :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word))))))))
+ then
+ (let (data :: 32 Word.word) = ((Word.ucast data :: 32 Word.word)) in
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ write_reg htif_tohost_ref ((update_subrange_vec_dec w__1 (( 63 :: int)::ii) (( 32 :: int)::ii) data :: 64 Word.word))))
+ else write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) data :: 64 Word.word))) \<then>
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let cmd = (Mk_htif_cmd w__2) in
+ (let b__0 = ((get_htif_cmd_device cmd :: 8 Word.word)) in
+ (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif-syscall-proxy cmd: '')
+ ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))
+ else () ) in
+ if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 0 :: int)::ii)))
+ :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) then
+ write_reg htif_done_ref True \<then>
+ write_reg
+ htif_exit_code_ref
+ ((shiftr ((zero_extend ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 64 :: int)::ii) :: 64 Word.word))
+ (( 1 :: int)::ii)
+ :: 64 Word.word))
+ else return () )
+ else
+ return (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then
+ (let (_ :: unit) =
+ (if ((get_config_print_platform () )) then
+ print_dbg
+ (((@) (''htif-term cmd: '')
+ ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))
+ else () ) in
+ (let b__2 = ((get_htif_cmd_cmd cmd :: 8 Word.word)) in
+ if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then ()
+ else if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then
+ plat_term_write
+ ((subrange_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ :: 8 Word.word))
+ else print_endline (((@) (''Unknown term cmd: '') ((string_of_bits b__2))))))
+ else print_endline (((@) (''htif-???? cmd: '') ((string_of_bits data)))))) \<then>
+ return (MemValue True))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val htif_tick : unit -> M unit\<close>\<close>
+
+definition htif_tick :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " htif_tick _ = (
+ (if ((get_config_print_platform () )) then
+ (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((print_dbg (((@) (''htif::tick '') ((string_of_bits w__0)))))))
+ else return () ) \<then>
+ write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))"
+
+
+\<comment> \<open>\<open>val within_mmio_readable : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_mmio_readable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_mmio_readable (addr :: xlenbits) (width :: int) = (
+ (((within_clint addr width)) \<or> (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> ((id0 width)))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val within_mmio_writable : mword ty64 -> integer -> bool\<close>\<close>
+
+definition within_mmio_writable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " within_mmio_writable (addr :: xlenbits) (width :: int) = (
+ (((within_clint addr width)) \<or> (((((within_htif_writable addr width)) \<and> ((((id0 width)) \<le> (( 8 :: int)::ii))))))))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition mmio_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " mmio_read (addr :: xlenbits) (width :: int) = (
+ if ((within_clint addr width)) then (clint_load addr width )
+ else if (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> ((id0 width))))))) then
+ (htif_load addr width )
+ else return (MemException E_Load_Access_Fault))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val mmio_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mmio_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mmio_write (addr :: xlenbits) (width :: int) data = (
+ if ((within_clint addr width)) then clint_store addr width data
+ else if (((((within_htif_writable addr width)) \<and> ((((id0 width)) \<le> (( 8 :: int)::ii)))))) then
+ htif_store addr width data
+ else return (MemException E_SAMO_Access_Fault))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val init_platform : unit -> M unit\<close>\<close>
+
+definition init_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_platform _ = (
+ (write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) \<then>
+ write_reg htif_done_ref False) \<then>
+ write_reg htif_exit_code_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))"
+
+
+\<comment> \<open>\<open>val tick_platform : unit -> M unit\<close>\<close>
+
+definition tick_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " tick_platform _ = ( htif_tick () )"
+
+
+\<comment> \<open>\<open>val handle_illegal : unit -> M unit\<close>\<close>
+
+definition handle_illegal :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " handle_illegal _ = (
+ (if ((plat_mtval_has_illegal_inst_bits () )) then
+ (read_reg instbits_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . return (Some w__0))
+ else return None) \<bind> (\<lambda> info .
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap = E_Illegal_Instr,
+ sync_exception_excinfo = info,
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (exception_handler w__1 (CTL_TRAP t) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ set_next_pc w__3))))))"
+
+
+\<comment> \<open>\<open>val platform_wfi : unit -> M unit\<close>\<close>
+
+definition platform_wfi :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " platform_wfi _ = (
+ (let (_ :: unit) = (cancel_reservation () ) in
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ if ((zopz0zI_u w__0 w__1)) then
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (write_reg mtime_ref w__2 \<then>
+ (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ write_reg mcycle_ref w__3))
+ else return () ))))"
+
+
+\<comment> \<open>\<open>val is_aligned_addr : mword ty64 -> integer -> bool\<close>\<close>
+
+definition is_aligned_addr :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where
+ " is_aligned_addr (addr :: xlenbits) (width :: int) = (
+ (((((Word.uint addr)) mod width)) = (( 0 :: int)::ii)))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+
+
+\<comment> \<open>\<open>val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition phys_mem_read :: " AccessType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " phys_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ (case (aq, rl, res) of
+ (False, False, False) =>
+ (read_ram Read_plain addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__0))
+ | (True, False, False) =>
+ (read_ram Read_RISCV_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__1 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__1))
+ | (True, True, False) =>
+ (read_ram Read_RISCV_strong_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__2 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__2))
+ | (False, False, True) =>
+ (read_ram Read_RISCV_reserved addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__3 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__3))
+ | (True, False, True) =>
+ (read_ram Read_RISCV_reserved_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__4 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__4))
+ | (True, True, True) =>
+ (read_ram Read_RISCV_reserved_strong_acquire addr width :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__5 ::
+ ( 'int8_times_n::len)Word.word) .
+ return (Some w__5))
+ | (False, True, False) => return None
+ | (False, True, True) => return None
+ ) \<bind> (\<lambda> w__6 .
+ (let result = w__6 in
+ return ((case (t, result) of
+ (Execute, None) => MemException E_Fetch_Access_Fault
+ | (Read, None) => MemException E_Load_Access_Fault
+ | (_, None) => MemException E_SAMO_Access_Fault
+ | (_, Some (v)) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ (((@) (''mem['')
+ (((@) ((accessType_to_str t))
+ (((@) ('','')
+ (((@) ((string_of_bits addr))
+ (((@) (''] -> '') ((string_of_bits v))))))))))))
+ else () ) in
+ MemValue v)
+ )))))"
+ for t :: " AccessType "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition checked_mem_read :: " AccessType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " checked_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ if ((within_mmio_readable addr width)) then (mmio_read addr width )
+ else if ((within_phys_mem addr width)) then (phys_mem_read t addr width aq rl res )
+ else return (MemException E_Load_Access_Fault))"
+ for t :: " AccessType "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val pmp_mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition pmp_mem_read :: " AccessType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " pmp_mem_read (t :: AccessType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res ::
+ bool) = (
+ if ((\<not> ((plat_enable_pmp () )))) then (checked_mem_read t addr width aq rl res )
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ effectivePrivilege w__1 w__2 \<bind> (\<lambda> (w__3 :: Privilege) .
+ pmpCheck addr width t w__3 \<bind> (\<lambda> (w__4 :: ExceptionType option) .
+ (case w__4 of
+ None => (checked_mem_read t addr width aq rl res )
+ | Some (e) => return (MemException e)
+ ))))))"
+ for t :: " AccessType "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val rvfi_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> MemoryOpResult (mword 'int8_times_n) -> unit\<close>\<close>
+
+definition rvfi_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> unit " where
+ " rvfi_read addr width value1 = ( () )"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+
+
+\<comment> \<open>\<open>val mem_read : forall 'int8_times_n. Size 'int8_times_n => AccessType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))\<close>\<close>
+
+definition mem_read :: " AccessType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where
+ " mem_read typ1 addr width aq rl res = (
+ (if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_Load_Addr_Align)
+ else
+ (case (aq, rl, res) of
+ (False, True, False) => throw (Error_not_implemented (''load.rl''))
+ | (False, True, True) => throw (Error_not_implemented (''lr.rl''))
+ | (_, _, _) => (pmp_mem_read typ1 addr width aq rl res )
+ )) \<bind> (\<lambda> result .
+ (let (_ :: unit) = (rvfi_read addr width result) in
+ return result)))"
+ for typ1 :: " AccessType "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and res :: " bool "
+
+
+\<comment> \<open>\<open>val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)\<close>\<close>
+
+definition mem_write_ea :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where
+ " mem_write_ea addr width aq rl con = (
+ if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (False, False, False) => write_ram_ea Write_plain addr width \<then> return (MemValue () )
+ | (False, True, False) => write_ram_ea Write_RISCV_release addr width \<then> return (MemValue () )
+ | (False, False, True) =>
+ write_ram_ea Write_RISCV_conditional addr width \<then> return (MemValue () )
+ | (False, True, True) =>
+ write_ram_ea Write_RISCV_conditional_release addr width \<then> return (MemValue () )
+ | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+ | (True, True, False) =>
+ write_ram_ea Write_RISCV_strong_release addr width \<then> return (MemValue () )
+ | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+ | (True, True, True) =>
+ write_ram_ea Write_RISCV_conditional_strong_release addr width \<then> return (MemValue () )
+ ))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+\<comment> \<open>\<open>val rvfi_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> unit\<close>\<close>
+
+definition rvfi_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit " where
+ " rvfi_write addr width value1 = ( () )"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+
+
+\<comment> \<open>\<open>val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition phys_mem_write :: " write_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " phys_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ (let (_ :: unit) = (rvfi_write addr width data) in
+ write_ram wk addr width data meta \<bind> (\<lambda> (w__0 :: bool) .
+ (let result = (MemValue w__0) in
+ (let (_ :: unit) =
+ (if ((get_config_print_mem () )) then
+ print_dbg
+ (((@) (''mem['')
+ (((@) ((string_of_bits addr)) (((@) (''] <- '') ((string_of_bits data))))))))
+ else () ) in
+ return result)))))"
+ for wk :: " write_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition checked_mem_write :: " write_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " checked_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ if ((within_mmio_writable addr width)) then mmio_write addr width data
+ else if ((within_phys_mem addr width)) then phys_mem_write wk addr width data meta
+ else return (MemException E_SAMO_Access_Fault))"
+ for wk :: " write_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val pmp_mem_write : forall 'int8_times_n. Size 'int8_times_n => write_kind -> mword ty64 -> integer -> mword 'int8_times_n -> unit -> M (MemoryOpResult bool)\<close>\<close>
+
+definition pmp_mem_write :: " write_kind \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " pmp_mem_write (wk :: write_kind) (addr :: xlenbits) (width :: int) data (meta :: mem_meta) = (
+ if ((\<not> ((plat_enable_pmp () )))) then checked_mem_write wk addr width data meta
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ effectivePrivilege w__1 w__2 \<bind> (\<lambda> (w__3 :: Privilege) .
+ pmpCheck addr width Write w__3 \<bind> (\<lambda> (w__4 :: ExceptionType option) .
+ (case w__4 of
+ None => checked_mem_write wk addr width data meta
+ | Some (e) => return (MemException e)
+ ))))))"
+ for wk :: " write_kind "
+ and addr :: "(64)Word.word "
+ and width :: " int "
+ and data :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+
+
+\<comment> \<open>\<open>val mem_write_value_meta : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> unit -> bool -> bool -> bool -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mem_write_value_meta :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> unit \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mem_write_value_meta addr width value1 meta aq rl con = (
+ (let (_ :: unit) = (rvfi_write addr width value1) in
+ if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then
+ return (MemException E_SAMO_Addr_Align)
+ else
+ (case (aq, rl, con) of
+ (False, False, False) => pmp_mem_write Write_plain addr width value1 meta
+ | (False, True, False) => pmp_mem_write Write_RISCV_release addr width value1 meta
+ | (False, False, True) => pmp_mem_write Write_RISCV_conditional addr width value1 meta
+ | (False, True, True) => pmp_mem_write Write_RISCV_conditional_release addr width value1 meta
+ | (True, True, False) => pmp_mem_write Write_RISCV_strong_release addr width value1 meta
+ | (True, True, True) =>
+ pmp_mem_write Write_RISCV_conditional_strong_release addr width value1 meta
+ | (True, False, False) => throw (Error_not_implemented (''store.aq''))
+ | (True, False, True) => throw (Error_not_implemented (''sc.aq''))
+ )))"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+ and meta :: " unit "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+\<comment> \<open>\<open>val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult bool)\<close>\<close>
+
+definition mem_write_value :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((bool)MemoryOpResult),(exception))monad " where
+ " mem_write_value addr width value1 aq rl con = (
+ mem_write_value_meta addr width value1 default_meta aq rl con )"
+ for addr :: "(64)Word.word "
+ and width :: " int "
+ and value1 :: "('int8_times_n::len)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+ and con :: " bool "
+
+
+definition PAGESIZE_BITS :: " int " where
+ " PAGESIZE_BITS = ( (( 12 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_PTE_Bits : mword ty8 -> PTE_Bits\<close>\<close>
+
+definition Mk_PTE_Bits :: "(8)Word.word \<Rightarrow> PTE_Bits " where
+ " Mk_PTE_Bits v = (
+ (| PTE_Bits_PTE_Bits_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) |) )"
+ for v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _get_PTE_Bits_bits : PTE_Bits -> mword ty8\<close>\<close>
+
+definition get_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word " where
+ " get_PTE_Bits_bits v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " PTE_Bits "
+
+
+\<comment> \<open>\<open>val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit\<close>\<close>
+
+definition set_PTE_Bits_bits :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits\<close>\<close>
+
+definition update_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_bits v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(8)Word.word "
+
+
+definition get_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_D v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_D :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_D r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_D v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_A v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_A :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_A r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_A v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_G v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_G :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_G r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_G v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_U v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_U :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_U r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_U v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_X v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_X :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_X r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_X v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_W v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_W :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_W r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_W v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_R v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_R :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_R r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_R v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+definition get_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word " where
+ " get_PTE_Bits_V v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))"
+ for v :: " PTE_Bits "
+
+
+definition set_PTE_Bits_V :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_PTE_Bits_V r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(PTE_Bits))register_ref "
+ and v :: "(1)Word.word "
+
+
+definition update_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where
+ " update_PTE_Bits_V v x = (
+ (v (|
+ PTE_Bits_PTE_Bits_chunk_0 :=
+ ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))
+ :: 8 Word.word))|)))"
+ for v :: " PTE_Bits "
+ and x :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val isPTEPtr : mword ty8 -> bool\<close>\<close>
+
+definition isPTEPtr :: "(8)Word.word \<Rightarrow> bool " where
+ " isPTEPtr p = (
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))"
+ for p :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val isInvalidPTE : mword ty8 -> bool\<close>\<close>
+
+definition isInvalidPTE :: "(8)Word.word \<Rightarrow> bool " where
+ " isInvalidPTE p = (
+ (let a = (Mk_PTE_Bits p) in
+ ((((((get_PTE_Bits_V a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))"
+ for p :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool\<close>\<close>
+
+fun checkPTEPermission :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> PTE_Bits \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = (
+ return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p ::
+ PTE_Bits) = ( internal_error (''m-mode mem perm check''))"
+ for mxr :: " bool "
+ and do_sum :: " bool "
+ and p :: " PTE_Bits "
+
+
+\<comment> \<open>\<open>val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits\<close>\<close>
+
+definition update_PTE_Bits :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option " where
+ " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = (
+ (let update_d =
+ (((((((a = Write))) \<or> (((a = ReadWrite)))))) \<and> (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in
+ (let update_a = (((get_PTE_Bits_A p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))) in
+ if (((update_d \<or> update_a))) then
+ (let np = (update_PTE_Bits_A p ((bool_to_bits True :: 1 Word.word))) in
+ (let np = (if update_d then update_PTE_Bits_D np ((bool_to_bits True :: 1 Word.word)) else np) in
+ Some np))
+ else None)))"
+ for p :: " PTE_Bits "
+ and a :: " AccessType "
+
+
+\<comment> \<open>\<open>val PTW_Error_of_num : integer -> PTW_Error\<close>\<close>
+
+definition PTW_Error_of_num :: " int \<Rightarrow> PTW_Error " where
+ " PTW_Error_of_num arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (( 0 :: int)::ii)))) then PTW_Access
+ else if (((p00 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE
+ else if (((p00 = (( 2 :: int)::ii)))) then PTW_No_Permission
+ else if (((p00 = (( 3 :: int)::ii)))) then PTW_Misaligned
+ else PTW_PTE_Update))"
+ for arg1 :: " int "
+
+
+\<comment> \<open>\<open>val num_of_PTW_Error : PTW_Error -> integer\<close>\<close>
+
+fun num_of_PTW_Error :: " PTW_Error \<Rightarrow> int " where
+ " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))"
+|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))"
+|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))"
+|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))"
+|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val ptw_error_to_str : PTW_Error -> string\<close>\<close>
+
+fun ptw_error_to_str :: " PTW_Error \<Rightarrow> string " where
+ " ptw_error_to_str PTW_Access = ( (''mem-access-error''))"
+|" ptw_error_to_str PTW_Invalid_PTE = ( (''invalid-pte''))"
+|" ptw_error_to_str PTW_No_Permission = ( (''no-permission''))"
+|" ptw_error_to_str PTW_Misaligned = ( (''misaligned-superpage''))"
+|" ptw_error_to_str PTW_PTE_Update = ( (''pte-update-needed''))"
+
+
+\<comment> \<open>\<open>val translationException : AccessType -> PTW_Error -> ExceptionType\<close>\<close>
+
+fun translationException :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType " where
+ " translationException (ReadWrite :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )"
+|" translationException (ReadWrite :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )"
+|" translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )"
+|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )"
+|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )"
+|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )"
+|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )"
+ for Fetch :: " AccessType "
+|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )"
+ for Fetch :: " AccessType "
+
+
+\<comment> \<open>\<open>val curAsid32 : mword ty32 -> mword ty9\<close>\<close>
+
+definition curAsid32 :: "(32)Word.word \<Rightarrow>(9)Word.word " where
+ " curAsid32 satp1 = (
+ (let s = (Mk_Satp32 satp1) in
+ (get_Satp32_Asid s :: 9 Word.word)))"
+ for satp1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val curPTB32 : mword ty32 -> mword ty34\<close>\<close>
+
+definition curPTB32 :: "(32)Word.word \<Rightarrow>(34)Word.word " where
+ " curPTB32 satp1 = (
+ (let (s :: Satp32) = (Mk_Satp32 satp1) in
+ (shiftl ((EXTZ (( 34 :: int)::ii) ((get_Satp32_PPN s :: 22 Word.word)) :: 34 Word.word)) PAGESIZE_BITS
+ :: 34 Word.word)))"
+ for satp1 :: "(32)Word.word "
+
+
+definition SV32_LEVEL_BITS :: " int " where
+ " SV32_LEVEL_BITS = ( (( 10 :: int)::ii))"
+
+
+definition SV32_LEVELS :: " int " where
+ " SV32_LEVELS = ( (( 2 :: int)::ii))"
+
+
+definition PTE32_LOG_SIZE :: " int " where
+ " PTE32_LOG_SIZE = ( (( 2 :: int)::ii))"
+
+
+definition PTE32_SIZE :: " int " where
+ " PTE32_SIZE = ( (( 4 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV32_Vaddr : mword ty32 -> SV32_Vaddr\<close>\<close>
+
+definition Mk_SV32_Vaddr :: "(32)Word.word \<Rightarrow> SV32_Vaddr " where
+ " Mk_SV32_Vaddr v = (
+ (| SV32_Vaddr_SV32_Vaddr_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32\<close>\<close>
+
+definition get_SV32_Vaddr_bits :: " SV32_Vaddr \<Rightarrow>(32)Word.word " where
+ " get_SV32_Vaddr_bits v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_bits : register_ref regstate register_value SV32_Vaddr -> mword ty32 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_bits :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_bits : SV32_Vaddr -> mword ty32 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_bits :: " SV32_Vaddr \<Rightarrow>(32)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_bits v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20\<close>\<close>
+
+definition get_SV32_Vaddr_VPNi :: " SV32_Vaddr \<Rightarrow>(20)Word.word " where
+ " get_SV32_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_VPNi : register_ref regstate register_value SV32_Vaddr -> mword ty20 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_VPNi :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(20)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 31 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_VPNi : SV32_Vaddr -> mword ty20 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_VPNi :: " SV32_Vaddr \<Rightarrow>(20)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_VPNi v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 31 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(20)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27 -> SV48_Vaddr\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_VPNi : SV48_Vaddr -> mword ty27\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_VPNi : register_ref regstate register_value SV48_Vaddr -> mword ty27 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV32_Vaddr_PgOfs :: " SV32_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV32_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV32_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Vaddr_PgOfs : register_ref regstate register_value SV32_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV32_Vaddr_PgOfs :: "((regstate),(register_value),(SV32_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Vaddr_PgOfs : SV32_Vaddr -> mword ty12 -> SV32_Vaddr\<close>\<close>
+
+definition update_SV32_Vaddr_PgOfs :: " SV32_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV32_Vaddr " where
+ " update_SV32_Vaddr_PgOfs v x = (
+ (v (|
+ SV32_Vaddr_SV32_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Vaddr_SV32_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12 -> SV48_Paddr\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_PgOfs : SV48_Paddr -> mword ty12\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_PgOfs : register_ref regstate register_value SV48_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val Mk_SV32_Paddr : mword ty34 -> SV32_Paddr\<close>\<close>
+
+definition Mk_SV32_Paddr :: "(34)Word.word \<Rightarrow> SV32_Paddr " where
+ " Mk_SV32_Paddr v = (
+ (| SV32_Paddr_SV32_Paddr_chunk_0 = ((subrange_vec_dec v (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word)) |) )"
+ for v :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_bits : SV32_Paddr -> mword ty34\<close>\<close>
+
+definition get_SV32_Paddr_bits :: " SV32_Paddr \<Rightarrow>(34)Word.word " where
+ " get_SV32_Paddr_bits v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_bits : register_ref regstate register_value SV32_Paddr -> mword ty34 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_bits :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(34)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 33 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_bits : SV32_Paddr -> mword ty34 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_bits :: " SV32_Paddr \<Rightarrow>(34)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_bits v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 33 :: int)::ii) (( 0 :: int)::ii) :: 34 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(34)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22\<close>\<close>
+
+definition get_SV32_Paddr_PPNi :: " SV32_Paddr \<Rightarrow>(22)Word.word " where
+ " get_SV32_Paddr_PPNi v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 12 :: int)::ii) :: 22 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_PPNi : register_ref regstate register_value SV32_Paddr -> mword ty22 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_PPNi :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 33 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_PPNi : SV32_Paddr -> mword ty22 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_PPNi :: " SV32_Paddr \<Rightarrow>(22)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_PPNi v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 33 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_PPNi : SV48_PTE -> mword ty44 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_PPNi : SV48_PTE -> mword ty44\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_PPNi : register_ref regstate register_value SV48_PTE -> mword ty44 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12\<close>\<close>
+
+definition get_SV32_Paddr_PgOfs :: " SV32_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV32_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV32_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV32_Paddr_PgOfs : register_ref regstate register_value SV32_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV32_Paddr_PgOfs :: "((regstate),(register_value),(SV32_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 34 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_Paddr_PgOfs : SV32_Paddr -> mword ty12 -> SV32_Paddr\<close>\<close>
+
+definition update_SV32_Paddr_PgOfs :: " SV32_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV32_Paddr " where
+ " update_SV32_Paddr_PgOfs v x = (
+ (v (|
+ SV32_Paddr_SV32_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_Paddr_SV32_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 34 Word.word))|)))"
+ for v :: " SV32_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV32_PTE : mword ty32 -> SV32_PTE\<close>\<close>
+
+definition Mk_SV32_PTE :: "(32)Word.word \<Rightarrow> SV32_PTE " where
+ " Mk_SV32_PTE v = (
+ (| SV32_PTE_SV32_PTE_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_bits : SV32_PTE -> mword ty32\<close>\<close>
+
+definition get_SV32_PTE_bits :: " SV32_PTE \<Rightarrow>(32)Word.word " where
+ " get_SV32_PTE_bits v = (
+ (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_bits : register_ref regstate register_value SV32_PTE -> mword ty32 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_bits :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_bits : SV32_PTE -> mword ty32 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_bits :: " SV32_PTE \<Rightarrow>(32)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_bits v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_PPNi : SV32_PTE -> mword ty22\<close>\<close>
+
+definition get_SV32_PTE_PPNi :: " SV32_PTE \<Rightarrow>(22)Word.word " where
+ " get_SV32_PTE_PPNi v = (
+ (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 10 :: int)::ii) :: 22 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_PPNi : register_ref regstate register_value SV32_PTE -> mword ty22 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_PPNi :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(22)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 31 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_PPNi : SV32_PTE -> mword ty22 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_PPNi :: " SV32_PTE \<Rightarrow>(22)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_PPNi v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 31 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 21 :: int)::ii) (( 0 :: int)::ii) :: 22 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(22)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV32_PTE_RSW : SV32_PTE -> mword ty2\<close>\<close>
+
+definition get_SV32_PTE_RSW :: " SV32_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV32_PTE_RSW v = ( (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_RSW : register_ref regstate register_value SV32_PTE -> mword ty2 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_RSW :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_RSW : SV32_PTE -> mword ty2 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_RSW :: " SV32_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_RSW v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_RSW : SV48_PTE -> mword ty2 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_RSW : SV48_PTE -> mword ty2\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_RSW : register_ref regstate register_value SV48_PTE -> mword ty2 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV32_PTE_BITS : SV32_PTE -> mword ty8\<close>\<close>
+
+definition get_SV32_PTE_BITS :: " SV32_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV32_PTE_BITS v = ( (subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV32_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV32_PTE_BITS : register_ref regstate register_value SV32_PTE -> mword ty8 -> M unit\<close>\<close>
+
+definition set_SV32_PTE_BITS :: "((regstate),(register_value),(SV32_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV32_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 32 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV32_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV32_PTE_BITS : SV32_PTE -> mword ty8 -> SV32_PTE\<close>\<close>
+
+definition update_SV32_PTE_BITS :: " SV32_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV32_PTE " where
+ " update_SV32_PTE_BITS v x = (
+ (v (|
+ SV32_PTE_SV32_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV32_PTE_SV32_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 32 Word.word))|)))"
+ for v :: " SV32_PTE "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_PTE_BITS : SV48_PTE -> mword ty8 -> SV48_PTE\<close>\<close>
+
+\<comment> \<open>\<open>val _get_SV48_PTE_BITS : SV48_PTE -> mword ty8\<close>\<close>
+
+\<comment> \<open>\<open>val _set_SV48_PTE_BITS : register_ref regstate register_value SV48_PTE -> mword ty8 -> M unit\<close>\<close>
+
+\<comment> \<open>\<open>val curAsid64 : mword ty64 -> mword ty16\<close>\<close>
+
+definition curAsid64 :: "(64)Word.word \<Rightarrow>(16)Word.word " where
+ " curAsid64 satp1 = (
+ (let s = (Mk_Satp64 satp1) in
+ (get_Satp64_Asid s :: 16 Word.word)))"
+ for satp1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val curPTB64 : mword ty64 -> mword ty56\<close>\<close>
+
+definition curPTB64 :: "(64)Word.word \<Rightarrow>(56)Word.word " where
+ " curPTB64 satp1 = (
+ (let s = (Mk_Satp64 satp1) in
+ (shiftl ((EXTZ (( 56 :: int)::ii) ((get_Satp64_PPN s :: 44 Word.word)) :: 56 Word.word)) PAGESIZE_BITS
+ :: 56 Word.word)))"
+ for satp1 :: "(64)Word.word "
+
+
+definition SV39_LEVEL_BITS :: " int " where
+ " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))"
+
+
+definition SV39_LEVELS :: " int " where
+ " SV39_LEVELS = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_LOG_SIZE :: " int " where
+ " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))"
+
+
+definition PTE39_SIZE :: " int " where
+ " PTE39_SIZE = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr\<close>\<close>
+
+definition Mk_SV39_Vaddr :: "(39)Word.word \<Rightarrow> SV39_Vaddr " where
+ " Mk_SV39_Vaddr v = (
+ (| SV39_Vaddr_SV39_Vaddr_chunk_0 = ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) |) )"
+ for v :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39\<close>\<close>
+
+definition get_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word " where
+ " get_SV39_Vaddr_bits v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_bits :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_bits v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27\<close>\<close>
+
+definition get_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word " where
+ " get_SV39_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_VPNi :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_VPNi v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV39_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV39_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV39_Vaddr_PgOfs :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 39 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr\<close>\<close>
+
+definition update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr " where
+ " update_SV39_Vaddr_PgOfs v x = (
+ (v (|
+ SV39_Vaddr_SV39_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 39 Word.word))|)))"
+ for v :: " SV39_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr\<close>\<close>
+
+definition Mk_SV39_Paddr :: "(56)Word.word \<Rightarrow> SV39_Paddr " where
+ " Mk_SV39_Paddr v = (
+ (| SV39_Paddr_SV39_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) |) )"
+ for v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56\<close>\<close>
+
+definition get_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word " where
+ " get_SV39_Paddr_bits v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_bits :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_bits v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44\<close>\<close>
+
+definition get_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word " where
+ " get_SV39_Paddr_PPNi v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_PPNi :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_PPNi v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12\<close>\<close>
+
+definition get_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV39_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV39_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV39_Paddr_PgOfs :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr\<close>\<close>
+
+definition update_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr " where
+ " update_SV39_Paddr_PgOfs v x = (
+ (v (|
+ SV39_Paddr_SV39_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV39_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV39_PTE : mword ty64 -> SV39_PTE\<close>\<close>
+
+definition Mk_SV39_PTE :: "(64)Word.word \<Rightarrow> SV39_PTE " where
+ " Mk_SV39_PTE v = (
+ (| SV39_PTE_SV39_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_bits : SV39_PTE -> mword ty64\<close>\<close>
+
+definition get_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word " where
+ " get_SV39_PTE_bits v = (
+ (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_bits :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_bits v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44\<close>\<close>
+
+definition get_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word " where
+ " get_SV39_PTE_PPNi v = (
+ (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_PPNi :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_PPNi v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2\<close>\<close>
+
+definition get_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV39_PTE_RSW v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_RSW :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_RSW v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8\<close>\<close>
+
+definition get_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV39_PTE_BITS v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV39_PTE "
+
+
+\<comment> \<open>\<open>val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit\<close>\<close>
+
+definition set_SV39_PTE_BITS :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV39_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV39_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE\<close>\<close>
+
+definition update_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE " where
+ " update_SV39_PTE_BITS v x = (
+ (v (|
+ SV39_PTE_SV39_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV39_PTE "
+ and x :: "(8)Word.word "
+
+
+definition SV48_LEVEL_BITS :: " int " where
+ " SV48_LEVEL_BITS = ( (( 9 :: int)::ii))"
+
+
+definition SV48_LEVELS :: " int " where
+ " SV48_LEVELS = ( (( 4 :: int)::ii))"
+
+
+definition PTE48_LOG_SIZE :: " int " where
+ " PTE48_LOG_SIZE = ( (( 3 :: int)::ii))"
+
+
+definition PTE48_SIZE :: " int " where
+ " PTE48_SIZE = ( (( 8 :: int)::ii))"
+
+
+\<comment> \<open>\<open>val Mk_SV48_Vaddr : mword ty48 -> SV48_Vaddr\<close>\<close>
+
+definition Mk_SV48_Vaddr :: "(48)Word.word \<Rightarrow> SV48_Vaddr " where
+ " Mk_SV48_Vaddr v = (
+ (| SV48_Vaddr_SV48_Vaddr_chunk_0 = ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) |) )"
+ for v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48\<close>\<close>
+
+definition get_SV48_Vaddr_bits :: " SV48_Vaddr \<Rightarrow>(48)Word.word " where
+ " get_SV48_Vaddr_bits v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_bits : register_ref regstate register_value SV48_Vaddr -> mword ty48 -> M unit\<close>\<close>
+
+definition set_SV48_Vaddr_bits :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_bits : SV48_Vaddr -> mword ty48 -> SV48_Vaddr\<close>\<close>
+
+definition update_SV48_Vaddr_bits :: " SV48_Vaddr \<Rightarrow>(48)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_bits v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(48)Word.word "
+
+
+definition get_SV48_Vaddr_VPNi :: " SV48_Vaddr \<Rightarrow>(27)Word.word " where
+ " get_SV48_Vaddr_VPNi v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+definition set_SV48_Vaddr_VPNi :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_VPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(27)Word.word "
+
+
+definition update_SV48_Vaddr_VPNi :: " SV48_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_VPNi v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(27)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12\<close>\<close>
+
+definition get_SV48_Vaddr_PgOfs :: " SV48_Vaddr \<Rightarrow>(12)Word.word " where
+ " get_SV48_Vaddr_PgOfs v = (
+ (subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV48_Vaddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Vaddr_PgOfs : register_ref regstate register_value SV48_Vaddr -> mword ty12 -> M unit\<close>\<close>
+
+definition set_SV48_Vaddr_PgOfs :: "((regstate),(register_value),(SV48_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Vaddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 48 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Vaddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Vaddr_PgOfs : SV48_Vaddr -> mword ty12 -> SV48_Vaddr\<close>\<close>
+
+definition update_SV48_Vaddr_PgOfs :: " SV48_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV48_Vaddr " where
+ " update_SV48_Vaddr_PgOfs v x = (
+ (v (|
+ SV48_Vaddr_SV48_Vaddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Vaddr_SV48_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 48 Word.word))|)))"
+ for v :: " SV48_Vaddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV48_Paddr : mword ty56 -> SV48_Paddr\<close>\<close>
+
+definition Mk_SV48_Paddr :: "(56)Word.word \<Rightarrow> SV48_Paddr " where
+ " Mk_SV48_Paddr v = (
+ (| SV48_Paddr_SV48_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) |) )"
+ for v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_bits : SV48_Paddr -> mword ty56\<close>\<close>
+
+definition get_SV48_Paddr_bits :: " SV48_Paddr \<Rightarrow>(56)Word.word " where
+ " get_SV48_Paddr_bits v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_bits : register_ref regstate register_value SV48_Paddr -> mword ty56 -> M unit\<close>\<close>
+
+definition set_SV48_Paddr_bits :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_bits : SV48_Paddr -> mword ty56 -> SV48_Paddr\<close>\<close>
+
+definition update_SV48_Paddr_bits :: " SV48_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_bits v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(56)Word.word "
+
+
+\<comment> \<open>\<open>val _get_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44\<close>\<close>
+
+definition get_SV48_Paddr_PPNi :: " SV48_Paddr \<Rightarrow>(44)Word.word " where
+ " get_SV48_Paddr_PPNi v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+\<comment> \<open>\<open>val _set_SV48_Paddr_PPNi : register_ref regstate register_value SV48_Paddr -> mword ty44 -> M unit\<close>\<close>
+
+definition set_SV48_Paddr_PPNi :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(44)Word.word "
+
+
+\<comment> \<open>\<open>val _update_SV48_Paddr_PPNi : SV48_Paddr -> mword ty44 -> SV48_Paddr\<close>\<close>
+
+definition update_SV48_Paddr_PPNi :: " SV48_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_PPNi v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(44)Word.word "
+
+
+definition get_SV48_Paddr_PgOfs :: " SV48_Paddr \<Rightarrow>(12)Word.word " where
+ " get_SV48_Paddr_PgOfs v = (
+ (subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))"
+ for v :: " SV48_Paddr "
+
+
+definition set_SV48_Paddr_PgOfs :: "((regstate),(register_value),(SV48_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_Paddr_PgOfs r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_Paddr))register_ref "
+ and v :: "(12)Word.word "
+
+
+definition update_SV48_Paddr_PgOfs :: " SV48_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV48_Paddr " where
+ " update_SV48_Paddr_PgOfs v x = (
+ (v (|
+ SV48_Paddr_SV48_Paddr_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_Paddr_SV48_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))
+ :: 56 Word.word))|)))"
+ for v :: " SV48_Paddr "
+ and x :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val Mk_SV48_PTE : mword ty64 -> SV48_PTE\<close>\<close>
+
+definition Mk_SV48_PTE :: "(64)Word.word \<Rightarrow> SV48_PTE " where
+ " Mk_SV48_PTE v = (
+ (| SV48_PTE_SV48_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )"
+ for v :: "(64)Word.word "
+
+
+definition get_SV48_PTE_bits :: " SV48_PTE \<Rightarrow>(64)Word.word " where
+ " get_SV48_PTE_bits v = (
+ (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_bits :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_bits r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(64)Word.word "
+
+
+definition update_SV48_PTE_bits :: " SV48_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_bits v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(64)Word.word "
+
+
+definition get_SV48_PTE_PPNi :: " SV48_PTE \<Rightarrow>(44)Word.word " where
+ " get_SV48_PTE_PPNi v = (
+ (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_PPNi :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_PPNi r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(44)Word.word "
+
+
+definition update_SV48_PTE_PPNi :: " SV48_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_PPNi v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii)
+ ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(44)Word.word "
+
+
+definition get_SV48_PTE_RSW :: " SV48_PTE \<Rightarrow>(2)Word.word " where
+ " get_SV48_PTE_RSW v = ( (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_RSW :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_RSW r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(2)Word.word "
+
+
+definition update_SV48_PTE_RSW :: " SV48_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_RSW v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii)
+ ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(2)Word.word "
+
+
+definition get_SV48_PTE_BITS :: " SV48_PTE \<Rightarrow>(8)Word.word " where
+ " get_SV48_PTE_BITS v = ( (subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))"
+ for v :: " SV48_PTE "
+
+
+definition set_SV48_PTE_BITS :: "((regstate),(register_value),(SV48_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " set_SV48_PTE_BITS r_ref v = (
+ reg_deref r_ref \<bind> (\<lambda> r .
+ (let r =
+ ((r (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|))) in
+ write_reg r_ref r)))"
+ for r_ref :: "((regstate),(register_value),(SV48_PTE))register_ref "
+ and v :: "(8)Word.word "
+
+
+definition update_SV48_PTE_BITS :: " SV48_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV48_PTE " where
+ " update_SV48_PTE_BITS v x = (
+ (v (|
+ SV48_PTE_SV48_PTE_chunk_0 :=
+ ((update_subrange_vec_dec(SV48_PTE_SV48_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii)
+ ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))
+ :: 64 Word.word))|)))"
+ for v :: " SV48_PTE "
+ and x :: "(8)Word.word "
+
+
+\<comment> \<open>\<open>val make_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'palen, Size 'ptelen, Size 'valen => mword 'asidlen -> bool -> mword 'valen -> mword 'palen -> mword 'ptelen -> ii -> mword 'palen -> ii -> M (TLB_Entry 'asidlen 'valen 'palen 'ptelen)\<close>\<close>
+
+definition make_TLB_Entry :: "('asidlen::len)Word.word \<Rightarrow> bool \<Rightarrow>('valen::len)Word.word \<Rightarrow>('palen::len)Word.word \<Rightarrow>('ptelen::len)Word.word \<Rightarrow> int \<Rightarrow>('palen::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry),(exception))monad " where
+ " make_TLB_Entry asid global1 vAddr pAddr pte level pteAddr levelBitSize = (
+ (let (shift :: ii) = (PAGESIZE_BITS + ((level * levelBitSize))) in
+ (let vAddrMask =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec vAddr
+ ((xor_vec vAddr
+ ((EXTZ ((int (size vAddr))) (vec_of_bits [B1] :: 1 Word.word) :: ( 'valen::len)Word.word))
+ :: ( 'valen::len)Word.word))
+ :: ( 'valen::len)Word.word)) shift
+ :: ( 'valen::len)Word.word)) (( 1 :: int)::ii)
+ :: ( 'valen::len)Word.word)) in
+ (let vMatchMask = ((not_vec vAddrMask :: ( 'valen::len)Word.word)) in
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((| TLB_Entry_asid = asid,
+ TLB_Entry_global = global1,
+ TLB_Entry_vAddr = ((and_vec vAddr vMatchMask :: ( 'valen::len)Word.word)),
+ TLB_Entry_pAddr =
+ ((shiftl ((shiftr pAddr shift :: ( 'palen::len)Word.word)) shift :: ( 'palen::len)Word.word)),
+ TLB_Entry_vMatchMask = vMatchMask,
+ TLB_Entry_vAddrMask = vAddrMask,
+ TLB_Entry_pte = pte,
+ TLB_Entry_pteAddr = pteAddr,
+ TLB_Entry_age = w__0 |)))))))"
+ for asid :: "('asidlen::len)Word.word "
+ and global1 :: " bool "
+ and vAddr :: "('valen::len)Word.word "
+ and pAddr :: "('palen::len)Word.word "
+ and pte :: "('ptelen::len)Word.word "
+ and level :: " int "
+ and pteAddr :: "('palen::len)Word.word "
+ and levelBitSize :: " int "
+
+
+\<comment> \<open>\<open>val match_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> mword 'asidlen -> mword 'valen -> bool\<close>\<close>
+
+definition match_TLB_Entry :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry \<Rightarrow>('asidlen::len)Word.word \<Rightarrow>('valen::len)Word.word \<Rightarrow> bool " where
+ " match_TLB_Entry ent asid vaddr = (
+ (((((TLB_Entry_global ent) \<or> ((((TLB_Entry_asid ent) = asid)))))) \<and> ((((TLB_Entry_vAddr ent) = ((and_vec(TLB_Entry_vMatchMask ent) vaddr :: ( 'valen::len)Word.word)))))))"
+ for ent :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and asid :: "('asidlen::len)Word.word "
+ and vaddr :: "('valen::len)Word.word "
+
+
+\<comment> \<open>\<open>val flush_TLB_Entry : forall 'asidlen 'palen 'ptelen 'valen. Size 'asidlen, Size 'valen => TLB_Entry 'asidlen 'valen 'palen 'ptelen -> maybe (mword 'asidlen) -> maybe (mword 'valen) -> bool\<close>\<close>
+
+fun flush_TLB_Entry :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry \<Rightarrow>(('asidlen::len)Word.word)option \<Rightarrow>(('valen::len)Word.word)option \<Rightarrow> bool " where
+ " flush_TLB_Entry e None None = ( True )"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+|" flush_TLB_Entry e None (Some (a)) = (
+ ((TLB_Entry_vAddr e) = ((and_vec(TLB_Entry_vMatchMask e) a :: ( 'valen::len)Word.word))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and a :: "('valen::len)Word.word "
+|" flush_TLB_Entry e (Some (i)) None = ( (((((TLB_Entry_asid e) = i))) \<and> ((\<not>(TLB_Entry_global e)))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and i :: "('asidlen::len)Word.word "
+|" flush_TLB_Entry e (Some (i)) (Some (a)) = (
+ (((((TLB_Entry_asid e) = i))) \<and> (((((((TLB_Entry_vAddr e) = ((and_vec a(TLB_Entry_vMatchMask e) :: ( 'valen::len)Word.word))))) \<and> ((\<not>(TLB_Entry_global e))))))))"
+ for e :: "(('asidlen::len),('valen::len),('palen::len),('ptelen::len))TLB_Entry "
+ and i :: "('asidlen::len)Word.word "
+ and a :: "('valen::len)Word.word "
+
+
+\<comment> \<open>\<open>val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M (PTW_Result (mword ty56) SV39_PTE)\<close>\<close>
+
+function (sequential,domintros) walk39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),((((56)Word.word),(SV39_PTE))PTW_Result),(exception))monad " where
+ " walk39 vaddr ac priv mxr do_sum ptb level global1 = (
+ (let va = (Mk_SV39_Vaddr vaddr) in
+ (let (pt_ofs :: paddr64) =
+ ((shiftl
+ ((EXTZ (( 56 :: int)::ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV39_Vaddr_VPNi va :: 27 Word.word))
+ ((level * SV39_LEVEL_BITS))
+ :: 27 Word.word)) ((SV39_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii)
+ :: 9 Word.word))
+ :: 56 Word.word)) PTE39_LOG_SIZE
+ :: 56 Word.word)) in
+ (let pte_addr = ((add_vec ptb pt_ofs :: 56 Word.word)) in
+ (mem_read ac ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) False False False
+ :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => return (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ (let pte = (Mk_SV39_PTE v) in
+ (let pbits = ((get_SV39_PTE_BITS pte :: 8 Word.word)) in
+ (let pattr = (Mk_PTE_Bits pbits) in
+ (let is_global =
+ (global1 \<or> (((((get_PTE_Bits_G pattr :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) in
+ if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk39 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 56 :: int)::ii) ((get_SV39_PTE_PPNi pte :: 44 Word.word)) :: 56 Word.word))
+ PAGESIZE_BITS
+ :: 56 Word.word)) ((level - (( 1 :: int)::ii))) is_global
+ :: ( (( 56 Word.word), SV39_PTE)PTW_Result) M)
+ else
+ checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) .
+ return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 :: int)::ii))) then
+ (let mask1 =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word))
+ ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word))
+ ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 44 Word.word))
+ :: 44 Word.word))
+ :: 44 Word.word)) ((level * SV39_LEVEL_BITS))
+ :: 44 Word.word)) (( 1 :: int)::ii)
+ :: 44 Word.word)) in
+ if (((((and_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) mask1 :: 44 Word.word)) \<noteq> ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 44 Word.word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ (let ppn =
+ ((or_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word))
+ ((and_vec
+ ((EXTZ (( 44 :: int)::ii) ((get_SV39_Vaddr_VPNi va :: 27 Word.word)) :: 44 Word.word))
+ mask1
+ :: 44 Word.word))
+ :: 44 Word.word)) in
+ PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va :: 12 Word.word))
+ :: 56 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ else
+ PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word))
+ ((get_SV39_Vaddr_PgOfs va :: 12 Word.word))
+ :: 56 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))))))
+ ))))))"
+ for vaddr :: "(39)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and ptb :: "(56)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val lookup_TLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB_Entry ty16 ty39 ty56 ty64)))\<close>\<close>
+
+definition lookup_TLB39 :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),((int*((16),(39),(56),(64))TLB_Entry)option),(exception))monad " where
+ " lookup_TLB39 asid vaddr = (
+ read_reg tlb39_ref \<bind> (\<lambda> (w__0 :: ( (16, 39, 56, 64)TLB_Entry)option) .
+ return ((case w__0 of
+ None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((( 0 :: int)::ii), e) else None
+ ))))"
+ for asid :: "(16)Word.word "
+ and vaddr :: "(39)Word.word "
+
+
+\<comment> \<open>\<open>val add_to_TLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit\<close>\<close>
+
+definition add_to_TLB39 :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " add_to_TLB39 asid vAddr pAddr pte pteAddr level global1 = (
+ make_TLB_Entry asid global1 vAddr pAddr ((get_SV39_PTE_bits pte :: 64 Word.word)) level pteAddr
+ SV39_LEVEL_BITS \<bind> (\<lambda> (ent :: TLB39_Entry) .
+ write_reg tlb39_ref (Some ent)))"
+ for asid :: "(16)Word.word "
+ and vAddr :: "(39)Word.word "
+ and pAddr :: "(56)Word.word "
+ and pte :: " SV39_PTE "
+ and pteAddr :: "(56)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+
+
+\<comment> \<open>\<open>val write_TLB39 : ii -> TLB_Entry ty16 ty39 ty56 ty64 -> M unit\<close>\<close>
+
+definition write_TLB39 :: " int \<Rightarrow>((16),(39),(56),(64))TLB_Entry \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " write_TLB39 (idx :: ii) (ent :: TLB39_Entry) = ( write_reg tlb39_ref (Some ent))"
+ for idx :: " int "
+ and ent :: "((16),(39),(56),(64))TLB_Entry "
+
+
+\<comment> \<open>\<open>val flush_TLB39 : maybe (mword ty16) -> maybe (mword ty39) -> M unit\<close>\<close>
+
+definition flush_TLB39 :: "((16)Word.word)option \<Rightarrow>((39)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " flush_TLB39 asid addr = (
+ read_reg tlb39_ref \<bind> (\<lambda> (w__0 :: ( (16, 39, 56, 64)TLB_Entry)option) .
+ (case w__0 of
+ None => return ()
+ | Some (e) => if ((flush_TLB_Entry e asid addr)) then write_reg tlb39_ref None else return ()
+ )))"
+ for asid :: "((16)Word.word)option "
+ and addr :: "((39)Word.word)option "
+
+
+\<comment> \<open>\<open>val translate39 : mword ty16 -> mword ty56 -> mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty56) PTW_Error)\<close>\<close>
+
+definition translate39 :: "(16)Word.word \<Rightarrow>(56)Word.word \<Rightarrow>(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),((((56)Word.word),(PTW_Error))TR_Result),(exception))monad " where
+ " translate39 asid ptb vAddr ac priv mxr do_sum level = (
+ lookup_TLB39 asid vAddr \<bind> (\<lambda> (w__0 :: ((ii * (16, 39, 56, 64) TLB_Entry))option) .
+ (case w__0 of
+ Some ((idx, ent)) =>
+ (let pte = (Mk_SV39_PTE(TLB_Entry_pte ent)) in
+ (let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word))) in
+ checkPTEPermission ac priv mxr do_sum pteBits \<bind> (\<lambda> (w__1 :: bool) .
+ if ((\<not> w__1)) then return (TR_Failure PTW_No_Permission)
+ else
+ (case ((update_PTE_Bits pteBits ac)) of
+ None =>
+ return (TR_Address ((or_vec(TLB_Entry_pAddr ent)
+ ((EXTZ (( 56 :: int)::ii)
+ ((and_vec vAddr(TLB_Entry_vAddrMask ent) :: 39 Word.word))
+ :: 56 Word.word))
+ :: 56 Word.word)))
+ | Some (pbits) =>
+ if ((\<not> ((plat_enable_dirty_update () )))) then return (TR_Failure PTW_PTE_Update)
+ else
+ (let n_pte = (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in
+ (let (n_ent :: TLB39_Entry) = ent in
+ (let n_ent = ((n_ent (| TLB_Entry_pte := ((get_SV39_PTE_bits n_pte :: 64 Word.word))|))) in
+ (write_TLB39 idx n_ent \<then>
+ mem_write_value ((EXTZ (( 64 :: int)::ii)(TLB_Entry_pteAddr ent) :: 64 Word.word)) (( 8 :: int)::ii)
+ ((get_SV39_PTE_bits n_pte :: 64 Word.word)) False False False) \<bind> (\<lambda> (w__2 :: bool
+ MemoryOpResult) .
+ (case w__2 of
+ MemValue (_) => return ()
+ | MemException (e) => internal_error (''invalid physical address in TLB'')
+ ) \<then>
+ return (TR_Address ((or_vec(TLB_Entry_pAddr ent)
+ ((EXTZ (( 56 :: int)::ii)
+ ((and_vec vAddr(TLB_Entry_vAddrMask ent) :: 39 Word.word))
+ :: 56 Word.word))
+ :: 56 Word.word)))))))
+ ))))
+ | None =>
+ (walk39 vAddr ac priv mxr do_sum ptb level False :: ( (( 56 Word.word), SV39_PTE)PTW_Result) M) \<bind> (\<lambda> (w__6 :: (( 56 Word.word), SV39_PTE)
+ PTW_Result) .
+ (case w__6 of
+ PTW_Failure (f) => return (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global1)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word)))) ac)) of
+ None =>
+ add_to_TLB39 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR_Address pAddr)
+ | Some (pbits) =>
+ if ((\<not> ((plat_enable_dirty_update () )))) then return (TR_Failure PTW_PTE_Update)
+ else
+ (let (w_pte :: SV39_PTE) =
+ (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in
+ mem_write_value ((EXTZ (( 64 :: int)::ii) pteAddr :: 64 Word.word)) (( 8 :: int)::ii)
+ ((get_SV39_PTE_bits w_pte :: 64 Word.word)) False False False \<bind> (\<lambda> (w__7 :: bool
+ MemoryOpResult) .
+ (case w__7 of
+ MemValue (_) =>
+ add_to_TLB39 asid vAddr pAddr w_pte pteAddr level global1 \<then>
+ return (TR_Address pAddr)
+ | MemException (e) => return (TR_Failure PTW_Access)
+ )))
+ )
+ ))
+ )))"
+ for asid :: "(16)Word.word "
+ and ptb :: "(56)Word.word "
+ and vAddr :: "(39)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and level :: " int "
+
+
+\<comment> \<open>\<open>val init_vmem_sv39 : unit -> M unit\<close>\<close>
+
+definition init_vmem_sv39 :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_vmem_sv39 _ = ( write_reg tlb39_ref None )"
+
+
+\<comment> \<open>\<open>val walk48 : mword ty48 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M (PTW_Result (mword ty56) SV48_PTE)\<close>\<close>
+
+function (sequential,domintros) walk48 :: "(48)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),((((56)Word.word),(SV48_PTE))PTW_Result),(exception))monad " where
+ " walk48 vaddr ac priv mxr do_sum ptb level global1 = (
+ (let va = (Mk_SV48_Vaddr vaddr) in
+ (let (pt_ofs :: paddr64) =
+ ((shiftl
+ ((EXTZ (( 56 :: int)::ii)
+ ((subrange_vec_dec
+ ((shiftr ((get_SV48_Vaddr_VPNi va :: 27 Word.word))
+ ((level * SV48_LEVEL_BITS))
+ :: 27 Word.word)) ((SV48_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii)
+ :: 9 Word.word))
+ :: 56 Word.word)) PTE48_LOG_SIZE
+ :: 56 Word.word)) in
+ (let pte_addr = ((add_vec ptb pt_ofs :: 56 Word.word)) in
+ (mem_read ac ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) False False False
+ :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) .
+ (case w__0 of
+ MemException (_) => return (PTW_Failure PTW_Access)
+ | MemValue (v) =>
+ (let pte = (Mk_SV48_PTE v) in
+ (let pbits = ((get_SV48_PTE_BITS pte :: 8 Word.word)) in
+ (let pattr = (Mk_PTE_Bits pbits) in
+ (let is_global =
+ (global1 \<or> (((((get_PTE_Bits_G pattr :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) in
+ if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE)
+ else if ((isPTEPtr pbits)) then
+ if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE)
+ else
+ (walk48 vaddr ac priv mxr do_sum
+ ((shiftl ((EXTZ (( 56 :: int)::ii) ((get_SV48_PTE_PPNi pte :: 44 Word.word)) :: 56 Word.word))
+ PAGESIZE_BITS
+ :: 56 Word.word)) ((level - (( 1 :: int)::ii))) is_global
+ :: ( (( 56 Word.word), SV48_PTE)PTW_Result) M)
+ else
+ checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) .
+ return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission
+ else if ((level > (( 0 :: int)::ii))) then
+ (let mask1 =
+ ((sub_vec_int
+ ((shiftl
+ ((xor_vec ((get_SV48_PTE_PPNi pte :: 44 Word.word))
+ ((xor_vec ((get_SV48_PTE_PPNi pte :: 44 Word.word))
+ ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 44 Word.word))
+ :: 44 Word.word))
+ :: 44 Word.word)) ((level * SV48_LEVEL_BITS))
+ :: 44 Word.word)) (( 1 :: int)::ii)
+ :: 44 Word.word)) in
+ if (((((and_vec ((get_SV48_PTE_PPNi pte :: 44 Word.word)) mask1 :: 44 Word.word)) \<noteq> ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 44 Word.word))))) then
+ PTW_Failure PTW_Misaligned
+ else
+ (let ppn =
+ ((or_vec ((get_SV48_PTE_PPNi pte :: 44 Word.word))
+ ((and_vec
+ ((EXTZ (( 44 :: int)::ii) ((get_SV48_Vaddr_VPNi va :: 27 Word.word)) :: 44 Word.word))
+ mask1
+ :: 44 Word.word))
+ :: 44 Word.word)) in
+ PTW_Success ((concat_vec ppn ((get_SV48_Vaddr_PgOfs va :: 12 Word.word))
+ :: 56 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))
+ else
+ PTW_Success ((concat_vec ((get_SV48_PTE_PPNi pte :: 44 Word.word))
+ ((get_SV48_Vaddr_PgOfs va :: 12 Word.word))
+ :: 56 Word.word),
+ pte,
+ pte_addr,
+ level,
+ is_global)))))))
+ ))))))"
+ for vaddr :: "(48)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and ptb :: "(56)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val lookup_TLB48 : mword ty16 -> mword ty48 -> M (maybe ((ii * TLB_Entry ty16 ty48 ty56 ty64)))\<close>\<close>
+
+definition lookup_TLB48 :: "(16)Word.word \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),((int*((16),(48),(56),(64))TLB_Entry)option),(exception))monad " where
+ " lookup_TLB48 asid vaddr = (
+ read_reg tlb48_ref \<bind> (\<lambda> (w__0 :: ( (16, 48, 56, 64)TLB_Entry)option) .
+ return ((case w__0 of
+ None => None
+ | Some (e) => if ((match_TLB_Entry e asid vaddr)) then Some ((( 0 :: int)::ii), e) else None
+ ))))"
+ for asid :: "(16)Word.word "
+ and vaddr :: "(48)Word.word "
+
+
+\<comment> \<open>\<open>val add_to_TLB48 : mword ty16 -> mword ty48 -> mword ty56 -> SV48_PTE -> mword ty56 -> ii -> bool -> M unit\<close>\<close>
+
+definition add_to_TLB48 :: "(16)Word.word \<Rightarrow>(48)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV48_PTE \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " add_to_TLB48 asid vAddr pAddr pte pteAddr level global1 = (
+ make_TLB_Entry asid global1 vAddr pAddr ((get_SV48_PTE_bits pte :: 64 Word.word)) level pteAddr
+ SV48_LEVEL_BITS \<bind> (\<lambda> (ent :: TLB48_Entry) .
+ write_reg tlb48_ref (Some ent)))"
+ for asid :: "(16)Word.word "
+ and vAddr :: "(48)Word.word "
+ and pAddr :: "(56)Word.word "
+ and pte :: " SV48_PTE "
+ and pteAddr :: "(56)Word.word "
+ and level :: " int "
+ and global1 :: " bool "
+
+
+\<comment> \<open>\<open>val write_TLB48 : ii -> TLB_Entry ty16 ty48 ty56 ty64 -> M unit\<close>\<close>
+
+definition write_TLB48 :: " int \<Rightarrow>((16),(48),(56),(64))TLB_Entry \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " write_TLB48 (idx :: ii) (ent :: TLB48_Entry) = ( write_reg tlb48_ref (Some ent))"
+ for idx :: " int "
+ and ent :: "((16),(48),(56),(64))TLB_Entry "
+
+
+\<comment> \<open>\<open>val flush_TLB48 : maybe (mword ty16) -> maybe (mword ty48) -> M unit\<close>\<close>
+
+definition flush_TLB48 :: "((16)Word.word)option \<Rightarrow>((48)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " flush_TLB48 asid addr = (
+ read_reg tlb48_ref \<bind> (\<lambda> (w__0 :: ( (16, 48, 56, 64)TLB_Entry)option) .
+ (case w__0 of
+ None => return ()
+ | Some (e) => if ((flush_TLB_Entry e asid addr)) then write_reg tlb48_ref None else return ()
+ )))"
+ for asid :: "((16)Word.word)option "
+ and addr :: "((48)Word.word)option "
+
+
+\<comment> \<open>\<open>val translate48 : mword ty16 -> mword ty56 -> mword ty48 -> AccessType -> Privilege -> bool -> bool -> ii -> M (TR_Result (mword ty56) PTW_Error)\<close>\<close>
+
+definition translate48 :: "(16)Word.word \<Rightarrow>(56)Word.word \<Rightarrow>(48)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),((((56)Word.word),(PTW_Error))TR_Result),(exception))monad " where
+ " translate48 asid ptb vAddr ac priv mxr do_sum level = (
+ (walk48 vAddr ac priv mxr do_sum ptb level False :: ( (( 56 Word.word), SV48_PTE)PTW_Result) M) \<bind> (\<lambda> (w__0 :: (( 56 Word.word), SV48_PTE)
+ PTW_Result) .
+ (case w__0 of
+ PTW_Failure (f) => return (TR_Failure f)
+ | PTW_Success ((pAddr, pte, pteAddr, level, global1)) =>
+ (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV48_PTE_BITS pte :: 8 Word.word)))) ac)) of
+ None =>
+ add_to_TLB48 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR_Address pAddr)
+ | Some (pbits) =>
+ if ((\<not> ((plat_enable_dirty_update () )))) then return (TR_Failure PTW_PTE_Update)
+ else
+ (let (w_pte :: SV48_PTE) =
+ (update_SV48_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in
+ mem_write_value ((EXTZ (( 64 :: int)::ii) pteAddr :: 64 Word.word)) (( 8 :: int)::ii)
+ ((get_SV48_PTE_bits w_pte :: 64 Word.word)) False False False \<bind> (\<lambda> (w__1 :: bool
+ MemoryOpResult) .
+ (case w__1 of
+ MemValue (_) =>
+ add_to_TLB48 asid vAddr pAddr w_pte pteAddr level global1 \<then> return (TR_Address pAddr)
+ | MemException (e) => return (TR_Failure PTW_Access)
+ )))
+ )
+ )))"
+ for asid :: "(16)Word.word "
+ and ptb :: "(56)Word.word "
+ and vAddr :: "(48)Word.word "
+ and ac :: " AccessType "
+ and priv :: " Privilege "
+ and mxr :: " bool "
+ and do_sum :: " bool "
+ and level :: " int "
+
+
+\<comment> \<open>\<open>val init_vmem_sv48 : unit -> M unit\<close>\<close>
+
+definition init_vmem_sv48 :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_vmem_sv48 _ = ( write_reg tlb48_ref None )"
+
+
+\<comment> \<open>\<open>val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64\<close>\<close>
+
+definition legalize_satp :: " Architecture \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word " where
+ " legalize_satp (a :: Architecture) (o1 :: xlenbits) (v :: xlenbits) = (
+ (legalize_satp64 a o1 v :: 64 Word.word))"
+ for a :: " Architecture "
+ and o1 :: "(64)Word.word "
+ and v :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val translationMode : Privilege -> M SATPMode\<close>\<close>
+
+definition translationMode :: " Privilege \<Rightarrow>((register_value),(SATPMode),(exception))monad " where
+ " translationMode priv = (
+ if (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ then
+ return Sbare
+ else
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ (let arch = (architecture ((get_mstatus_SXL w__0 :: 2 Word.word))) in
+ (case arch of
+ Some (RV64) =>
+ (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let (mbits :: satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1)) :: 4 Word.word)) in
+ (case ((satp64Mode_of_bits RV64 mbits)) of
+ Some (m) => return m
+ | None => internal_error (''invalid RV64 translation mode in satp'')
+ )))
+ | Some (RV32) =>
+ (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) .
+ (let s = (Mk_Satp32 ((subrange_vec_dec w__4 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in
+ return (if (((((get_Satp32_Mode s :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))
+ then
+ Sbare
+ else Sv32)))
+ | _ => internal_error (''unsupported address translation arch'')
+ ))))"
+ for priv :: " Privilege "
+
+
+\<comment> \<open>\<open>val translateAddr : mword ty64 -> AccessType -> M (TR_Result (mword ty64) ExceptionType)\<close>\<close>
+
+definition translateAddr :: "(64)Word.word \<Rightarrow> AccessType \<Rightarrow>((register_value),((((64)Word.word),(ExceptionType))TR_Result),(exception))monad " where
+ " translateAddr vAddr ac = (
+ (case ac of
+ Execute => read_reg cur_privilege_ref
+ | _ =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) . effectivePrivilege w__1 w__2))
+ ) \<bind> (\<lambda> (effPriv :: Privilege) .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ (let (mxr :: bool) =
+ (((get_Mstatus_MXR w__4 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in
+ read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) .
+ (let (do_sum :: bool) =
+ (((get_Mstatus_SUM w__5 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in
+ translationMode effPriv \<bind> (\<lambda> (mode :: SATPMode) .
+ (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) .
+ (let asid = ((curAsid64 w__6 :: 16 Word.word)) in
+ (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ (let ptb = ((curPTB64 w__7 :: 56 Word.word)) in
+ (case mode of
+ Sbare => return (TR_Address vAddr)
+ | Sv39 =>
+ (translate39 asid ptb ((subrange_vec_dec vAddr (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) ac effPriv mxr
+ do_sum ((SV39_LEVELS - (( 1 :: int)::ii)))
+ :: ( (( 56 Word.word), PTW_Error)TR_Result) M) \<bind> (\<lambda> (w__8 :: (( 56 Word.word), PTW_Error) TR_Result) .
+ return ((case w__8 of
+ TR_Address (pa) => TR_Address ((EXTZ (( 64 :: int)::ii) pa :: 64 Word.word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | Sv48 =>
+ (translate48 asid ptb ((subrange_vec_dec vAddr (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) ac effPriv mxr
+ do_sum ((SV48_LEVELS - (( 1 :: int)::ii)))
+ :: ( (( 56 Word.word), PTW_Error)TR_Result) M) \<bind> (\<lambda> (w__9 :: (( 56 Word.word), PTW_Error) TR_Result) .
+ return ((case w__9 of
+ TR_Address (pa) => TR_Address ((EXTZ (( 64 :: int)::ii) pa :: 64 Word.word))
+ | TR_Failure (f) => TR_Failure ((translationException ac f))
+ )))
+ | _ =>
+ (internal_error (''unsupported address translation scheme'')
+ :: ( (( 64 Word.word), ExceptionType)TR_Result) M)
+ ))))))))))))"
+ for vAddr :: "(64)Word.word "
+ and ac :: " AccessType "
+
+
+\<comment> \<open>\<open>val flush_TLB : maybe (mword ty64) -> maybe (mword ty64) -> M unit\<close>\<close>
+
+definition flush_TLB :: "((64)Word.word)option \<Rightarrow>((64)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " flush_TLB asid_xlen addr_xlen = (
+ (let ((addr39 :: vaddr39 option), (addr48 :: vaddr48 option)) =
+ ((case addr_xlen of
+ None => (None, None)
+ | Some (a) =>
+ (Some ((subrange_vec_dec a (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)),
+ Some ((subrange_vec_dec a (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)))
+ )) in
+ (let (asid :: asid64 option) =
+ ((case asid_xlen of
+ None => None
+ | Some (a) => Some ((subrange_vec_dec a (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))
+ )) in
+ flush_TLB39 asid addr39 \<then> flush_TLB48 asid addr48)))"
+ for asid_xlen :: "((64)Word.word)option "
+ and addr_xlen :: "((64)Word.word)option "
+
+
+\<comment> \<open>\<open>val init_vmem : unit -> M unit\<close>\<close>
+
+definition init_vmem :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_vmem _ = ( init_vmem_sv39 () \<then> init_vmem_sv48 () )"
+
+
+\<comment> \<open>\<open>val execute : ast -> M Retired\<close>\<close>
+
+\<comment> \<open>\<open>val encdec_uop_forwards : uop -> mword ty7\<close>\<close>
+
+fun encdec_uop_forwards :: " uop \<Rightarrow>(7)Word.word " where
+ " encdec_uop_forwards RISCV_LUI = ( (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word))"
+|" encdec_uop_forwards RISCV_AUIPC = ( (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_uop_backwards : mword ty7 -> M uop\<close>\<close>
+
+definition encdec_uop_backwards :: "(7)Word.word \<Rightarrow>((register_value),(uop),(exception))monad " where
+ " encdec_uop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then return RISCV_LUI
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then return RISCV_AUIPC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_uop_forwards_matches : uop -> bool\<close>\<close>
+
+fun encdec_uop_forwards_matches :: " uop \<Rightarrow> bool " where
+ " encdec_uop_forwards_matches RISCV_LUI = ( True )"
+|" encdec_uop_forwards_matches RISCV_AUIPC = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_uop_backwards_matches : mword ty7 -> bool\<close>\<close>
+
+definition encdec_uop_backwards_matches :: "(7)Word.word \<Rightarrow> bool " where
+ " encdec_uop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True
+ else False))"
+ for arg1 :: "(7)Word.word "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_forwards : uop -> string\<close>\<close>
+
+fun utype_mnemonic_forwards :: " uop \<Rightarrow> string " where
+ " utype_mnemonic_forwards RISCV_LUI = ( (''lui''))"
+|" utype_mnemonic_forwards RISCV_AUIPC = ( (''auipc''))"
+
+
+\<comment> \<open>\<open>val utype_mnemonic_backwards : string -> M uop\<close>\<close>
+
+definition utype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(uop),(exception))monad " where
+ " utype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''lui'')))) then return RISCV_LUI
+ else if (((p00 = (''auipc'')))) then return RISCV_AUIPC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_forwards_matches : uop -> bool\<close>\<close>
+
+fun utype_mnemonic_forwards_matches :: " uop \<Rightarrow> bool " where
+ " utype_mnemonic_forwards_matches RISCV_LUI = ( True )"
+|" utype_mnemonic_forwards_matches RISCV_AUIPC = ( True )"
+
+
+\<comment> \<open>\<open>val utype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition utype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " utype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''lui'')))) then True
+ else if (((p00 = (''auipc'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s496_ : string -> maybe string\<close>\<close>
+
+definition s496 :: " string \<Rightarrow>(string)option " where
+ " s496 s4970 = (
+ (let s4980 = s4970 in
+ if ((string_startswith s4980 (''auipc''))) then
+ (case ((string_drop s4980 ((string_length (''auipc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4970 :: " string "
+
+
+\<comment> \<open>\<open>val _s492_ : string -> maybe string\<close>\<close>
+
+definition s492 :: " string \<Rightarrow>(string)option " where
+ " s492 s4930 = (
+ (let s4940 = s4930 in
+ if ((string_startswith s4940 (''lui''))) then
+ (case ((string_drop s4940 ((string_length (''lui''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s4930 :: " string "
+
+
+definition utype_mnemonic_matches_prefix :: " string \<Rightarrow>(uop*int)option " where
+ " utype_mnemonic_matches_prefix arg1 = (
+ (let s4950 = arg1 in
+ if ((case ((s492 s4950)) of Some (s1) => True | _ => False )) then
+ (case s492 s4950 of
+ (Some (s1)) =>
+ Some (RISCV_LUI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s496 s4950)) of Some (s1) => True | _ => False )) then
+ (case s496 s4950 of
+ (Some (s1)) =>
+ Some (RISCV_AUIPC, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_bop_forwards : bop -> mword ty3\<close>\<close>
+
+fun encdec_bop_forwards :: " bop \<Rightarrow>(3)Word.word " where
+ " encdec_bop_forwards RISCV_BEQ = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BNE = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BLT = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BGE = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BLTU = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))"
+|" encdec_bop_forwards RISCV_BGEU = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_bop_backwards : mword ty3 -> M bop\<close>\<close>
+
+definition encdec_bop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(bop),(exception))monad " where
+ " encdec_bop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return RISCV_BEQ
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return RISCV_BNE
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return RISCV_BLT
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_BGE
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return RISCV_BLTU
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return RISCV_BGEU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_bop_forwards_matches : bop -> bool\<close>\<close>
+
+fun encdec_bop_forwards_matches :: " bop \<Rightarrow> bool " where
+ " encdec_bop_forwards_matches RISCV_BEQ = ( True )"
+|" encdec_bop_forwards_matches RISCV_BNE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLT = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGE = ( True )"
+|" encdec_bop_forwards_matches RISCV_BLTU = ( True )"
+|" encdec_bop_forwards_matches RISCV_BGEU = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_bop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_bop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_bop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_forwards : bop -> string\<close>\<close>
+
+fun btype_mnemonic_forwards :: " bop \<Rightarrow> string " where
+ " btype_mnemonic_forwards RISCV_BEQ = ( (''beq''))"
+|" btype_mnemonic_forwards RISCV_BNE = ( (''bne''))"
+|" btype_mnemonic_forwards RISCV_BLT = ( (''blt''))"
+|" btype_mnemonic_forwards RISCV_BGE = ( (''bge''))"
+|" btype_mnemonic_forwards RISCV_BLTU = ( (''bltu''))"
+|" btype_mnemonic_forwards RISCV_BGEU = ( (''bgeu''))"
+
+
+\<comment> \<open>\<open>val btype_mnemonic_backwards : string -> M bop\<close>\<close>
+
+definition btype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(bop),(exception))monad " where
+ " btype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''beq'')))) then return RISCV_BEQ
+ else if (((p00 = (''bne'')))) then return RISCV_BNE
+ else if (((p00 = (''blt'')))) then return RISCV_BLT
+ else if (((p00 = (''bge'')))) then return RISCV_BGE
+ else if (((p00 = (''bltu'')))) then return RISCV_BLTU
+ else if (((p00 = (''bgeu'')))) then return RISCV_BGEU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_forwards_matches : bop -> bool\<close>\<close>
+
+fun btype_mnemonic_forwards_matches :: " bop \<Rightarrow> bool " where
+ " btype_mnemonic_forwards_matches RISCV_BEQ = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BNE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLT = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGE = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BLTU = ( True )"
+|" btype_mnemonic_forwards_matches RISCV_BGEU = ( True )"
+
+
+\<comment> \<open>\<open>val btype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition btype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " btype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''beq'')))) then True
+ else if (((p00 = (''bne'')))) then True
+ else if (((p00 = (''blt'')))) then True
+ else if (((p00 = (''bge'')))) then True
+ else if (((p00 = (''bltu'')))) then True
+ else if (((p00 = (''bgeu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s520_ : string -> maybe string\<close>\<close>
+
+definition s520 :: " string \<Rightarrow>(string)option " where
+ " s520 s5210 = (
+ (let s5220 = s5210 in
+ if ((string_startswith s5220 (''bgeu''))) then
+ (case ((string_drop s5220 ((string_length (''bgeu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5210 :: " string "
+
+
+\<comment> \<open>\<open>val _s516_ : string -> maybe string\<close>\<close>
+
+definition s516 :: " string \<Rightarrow>(string)option " where
+ " s516 s5170 = (
+ (let s5180 = s5170 in
+ if ((string_startswith s5180 (''bltu''))) then
+ (case ((string_drop s5180 ((string_length (''bltu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5170 :: " string "
+
+
+\<comment> \<open>\<open>val _s512_ : string -> maybe string\<close>\<close>
+
+definition s512 :: " string \<Rightarrow>(string)option " where
+ " s512 s5130 = (
+ (let s5140 = s5130 in
+ if ((string_startswith s5140 (''bge''))) then
+ (case ((string_drop s5140 ((string_length (''bge''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5130 :: " string "
+
+
+\<comment> \<open>\<open>val _s508_ : string -> maybe string\<close>\<close>
+
+definition s508 :: " string \<Rightarrow>(string)option " where
+ " s508 s5090 = (
+ (let s5100 = s5090 in
+ if ((string_startswith s5100 (''blt''))) then
+ (case ((string_drop s5100 ((string_length (''blt''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5090 :: " string "
+
+
+\<comment> \<open>\<open>val _s504_ : string -> maybe string\<close>\<close>
+
+definition s504 :: " string \<Rightarrow>(string)option " where
+ " s504 s5050 = (
+ (let s5060 = s5050 in
+ if ((string_startswith s5060 (''bne''))) then
+ (case ((string_drop s5060 ((string_length (''bne''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5050 :: " string "
+
+
+\<comment> \<open>\<open>val _s500_ : string -> maybe string\<close>\<close>
+
+definition s500 :: " string \<Rightarrow>(string)option " where
+ " s500 s5010 = (
+ (let s5020 = s5010 in
+ if ((string_startswith s5020 (''beq''))) then
+ (case ((string_drop s5020 ((string_length (''beq''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5010 :: " string "
+
+
+definition btype_mnemonic_matches_prefix :: " string \<Rightarrow>(bop*int)option " where
+ " btype_mnemonic_matches_prefix arg1 = (
+ (let s5030 = arg1 in
+ if ((case ((s500 s5030)) of Some (s1) => True | _ => False )) then
+ (case s500 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BEQ, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s504 s5030)) of Some (s1) => True | _ => False )) then
+ (case s504 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BNE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s508 s5030)) of Some (s1) => True | _ => False )) then
+ (case s508 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BLT, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s512 s5030)) of Some (s1) => True | _ => False )) then
+ (case s512 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BGE, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s516 s5030)) of Some (s1) => True | _ => False )) then
+ (case s516 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BLTU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s520 s5030)) of Some (s1) => True | _ => False )) then
+ (case s520 s5030 of
+ (Some (s1)) =>
+ Some (RISCV_BGEU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_iop_forwards : iop -> mword ty3\<close>\<close>
+
+fun encdec_iop_forwards :: " iop \<Rightarrow>(3)Word.word " where
+ " encdec_iop_forwards RISCV_ADDI = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTI = ( (vec_of_bits [B0,B1,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_SLTIU = ( (vec_of_bits [B0,B1,B1] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_ANDI = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_ORI = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))"
+|" encdec_iop_forwards RISCV_XORI = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_iop_backwards : mword ty3 -> M iop\<close>\<close>
+
+definition encdec_iop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(iop),(exception))monad " where
+ " encdec_iop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return RISCV_ADDI
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return RISCV_SLTI
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return RISCV_SLTIU
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then return RISCV_ANDI
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then return RISCV_ORI
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then return RISCV_XORI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_iop_forwards_matches : iop -> bool\<close>\<close>
+
+fun encdec_iop_forwards_matches :: " iop \<Rightarrow> bool " where
+ " encdec_iop_forwards_matches RISCV_ADDI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTI = ( True )"
+|" encdec_iop_forwards_matches RISCV_SLTIU = ( True )"
+|" encdec_iop_forwards_matches RISCV_ANDI = ( True )"
+|" encdec_iop_forwards_matches RISCV_ORI = ( True )"
+|" encdec_iop_forwards_matches RISCV_XORI = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_iop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_iop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_iop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_forwards : iop -> string\<close>\<close>
+
+fun itype_mnemonic_forwards :: " iop \<Rightarrow> string " where
+ " itype_mnemonic_forwards RISCV_ADDI = ( (''addi''))"
+|" itype_mnemonic_forwards RISCV_SLTI = ( (''slti''))"
+|" itype_mnemonic_forwards RISCV_SLTIU = ( (''sltiu''))"
+|" itype_mnemonic_forwards RISCV_XORI = ( (''xori''))"
+|" itype_mnemonic_forwards RISCV_ORI = ( (''ori''))"
+|" itype_mnemonic_forwards RISCV_ANDI = ( (''andi''))"
+
+
+\<comment> \<open>\<open>val itype_mnemonic_backwards : string -> M iop\<close>\<close>
+
+definition itype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(iop),(exception))monad " where
+ " itype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addi'')))) then return RISCV_ADDI
+ else if (((p00 = (''slti'')))) then return RISCV_SLTI
+ else if (((p00 = (''sltiu'')))) then return RISCV_SLTIU
+ else if (((p00 = (''xori'')))) then return RISCV_XORI
+ else if (((p00 = (''ori'')))) then return RISCV_ORI
+ else if (((p00 = (''andi'')))) then return RISCV_ANDI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_forwards_matches : iop -> bool\<close>\<close>
+
+fun itype_mnemonic_forwards_matches :: " iop \<Rightarrow> bool " where
+ " itype_mnemonic_forwards_matches RISCV_ADDI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_SLTIU = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_XORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ORI = ( True )"
+|" itype_mnemonic_forwards_matches RISCV_ANDI = ( True )"
+
+
+\<comment> \<open>\<open>val itype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition itype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " itype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addi'')))) then True
+ else if (((p00 = (''slti'')))) then True
+ else if (((p00 = (''sltiu'')))) then True
+ else if (((p00 = (''xori'')))) then True
+ else if (((p00 = (''ori'')))) then True
+ else if (((p00 = (''andi'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s544_ : string -> maybe string\<close>\<close>
+
+definition s544 :: " string \<Rightarrow>(string)option " where
+ " s544 s5450 = (
+ (let s5460 = s5450 in
+ if ((string_startswith s5460 (''andi''))) then
+ (case ((string_drop s5460 ((string_length (''andi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5450 :: " string "
+
+
+\<comment> \<open>\<open>val _s540_ : string -> maybe string\<close>\<close>
+
+definition s540 :: " string \<Rightarrow>(string)option " where
+ " s540 s5410 = (
+ (let s5420 = s5410 in
+ if ((string_startswith s5420 (''ori''))) then
+ (case ((string_drop s5420 ((string_length (''ori''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5410 :: " string "
+
+
+\<comment> \<open>\<open>val _s536_ : string -> maybe string\<close>\<close>
+
+definition s536 :: " string \<Rightarrow>(string)option " where
+ " s536 s5370 = (
+ (let s5380 = s5370 in
+ if ((string_startswith s5380 (''xori''))) then
+ (case ((string_drop s5380 ((string_length (''xori''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5370 :: " string "
+
+
+\<comment> \<open>\<open>val _s532_ : string -> maybe string\<close>\<close>
+
+definition s532 :: " string \<Rightarrow>(string)option " where
+ " s532 s5330 = (
+ (let s5340 = s5330 in
+ if ((string_startswith s5340 (''sltiu''))) then
+ (case ((string_drop s5340 ((string_length (''sltiu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5330 :: " string "
+
+
+\<comment> \<open>\<open>val _s528_ : string -> maybe string\<close>\<close>
+
+definition s528 :: " string \<Rightarrow>(string)option " where
+ " s528 s5290 = (
+ (let s5300 = s5290 in
+ if ((string_startswith s5300 (''slti''))) then
+ (case ((string_drop s5300 ((string_length (''slti''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5290 :: " string "
+
+
+\<comment> \<open>\<open>val _s524_ : string -> maybe string\<close>\<close>
+
+definition s524 :: " string \<Rightarrow>(string)option " where
+ " s524 s5250 = (
+ (let s5260 = s5250 in
+ if ((string_startswith s5260 (''addi''))) then
+ (case ((string_drop s5260 ((string_length (''addi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5250 :: " string "
+
+
+definition itype_mnemonic_matches_prefix :: " string \<Rightarrow>(iop*int)option " where
+ " itype_mnemonic_matches_prefix arg1 = (
+ (let s5270 = arg1 in
+ if ((case ((s524 s5270)) of Some (s1) => True | _ => False )) then
+ (case s524 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ADDI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s528 s5270)) of Some (s1) => True | _ => False )) then
+ (case s528 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_SLTI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s532 s5270)) of Some (s1) => True | _ => False )) then
+ (case s532 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_SLTIU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s536 s5270)) of Some (s1) => True | _ => False )) then
+ (case s536 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_XORI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s540 s5270)) of Some (s1) => True | _ => False )) then
+ (case s540 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ORI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s544 s5270)) of Some (s1) => True | _ => False )) then
+ (case s544 s5270 of
+ (Some (s1)) =>
+ Some (RISCV_ANDI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_sop_forwards : sop -> mword ty3\<close>\<close>
+
+fun encdec_sop_forwards :: " sop \<Rightarrow>(3)Word.word " where
+ " encdec_sop_forwards RISCV_SLLI = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_sop_forwards RISCV_SRLI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+|" encdec_sop_forwards RISCV_SRAI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_sop_backwards : mword ty3 -> M sop\<close>\<close>
+
+definition encdec_sop_backwards :: "(3)Word.word \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " encdec_sop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return RISCV_SLLI
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_SRLI
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_sop_forwards_matches : sop -> bool\<close>\<close>
+
+fun encdec_sop_forwards_matches :: " sop \<Rightarrow> bool " where
+ " encdec_sop_forwards_matches RISCV_SLLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRLI = ( True )"
+|" encdec_sop_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_sop_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_sop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_sop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_forwards : sop -> string\<close>\<close>
+
+fun shiftiop_mnemonic_forwards :: " sop \<Rightarrow> string " where
+ " shiftiop_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftiop_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_backwards : string -> M sop\<close>\<close>
+
+definition shiftiop_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " shiftiop_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then return RISCV_SLLI
+ else if (((p00 = (''srli'')))) then return RISCV_SRLI
+ else if (((p00 = (''srai'')))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_forwards_matches : sop -> bool\<close>\<close>
+
+fun shiftiop_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where
+ " shiftiop_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftiop_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftiop_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftiop_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then True
+ else if (((p00 = (''srli'')))) then True
+ else if (((p00 = (''srai'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s556_ : string -> maybe string\<close>\<close>
+
+definition s556 :: " string \<Rightarrow>(string)option " where
+ " s556 s5570 = (
+ (let s5580 = s5570 in
+ if ((string_startswith s5580 (''srai''))) then
+ (case ((string_drop s5580 ((string_length (''srai''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5570 :: " string "
+
+
+\<comment> \<open>\<open>val _s552_ : string -> maybe string\<close>\<close>
+
+definition s552 :: " string \<Rightarrow>(string)option " where
+ " s552 s5530 = (
+ (let s5540 = s5530 in
+ if ((string_startswith s5540 (''srli''))) then
+ (case ((string_drop s5540 ((string_length (''srli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5530 :: " string "
+
+
+\<comment> \<open>\<open>val _s548_ : string -> maybe string\<close>\<close>
+
+definition s548 :: " string \<Rightarrow>(string)option " where
+ " s548 s5490 = (
+ (let s5500 = s5490 in
+ if ((string_startswith s5500 (''slli''))) then
+ (case ((string_drop s5500 ((string_length (''slli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5490 :: " string "
+
+
+definition shiftiop_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where
+ " shiftiop_mnemonic_matches_prefix arg1 = (
+ (let s5510 = arg1 in
+ if ((case ((s548 s5510)) of Some (s1) => True | _ => False )) then
+ (case s548 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SLLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s552 s5510)) of Some (s1) => True | _ => False )) then
+ (case s552 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SRLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s556 s5510)) of Some (s1) => True | _ => False )) then
+ (case s556 s5510 of
+ (Some (s1)) =>
+ Some (RISCV_SRAI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_forwards : rop -> string\<close>\<close>
+
+fun rtype_mnemonic_forwards :: " rop \<Rightarrow> string " where
+ " rtype_mnemonic_forwards RISCV_ADD = ( (''add''))"
+|" rtype_mnemonic_forwards RISCV_SLT = ( (''slt''))"
+|" rtype_mnemonic_forwards RISCV_SLTU = ( (''sltu''))"
+|" rtype_mnemonic_forwards RISCV_AND = ( (''and''))"
+|" rtype_mnemonic_forwards RISCV_OR = ( (''or''))"
+|" rtype_mnemonic_forwards RISCV_XOR = ( (''xor''))"
+|" rtype_mnemonic_forwards RISCV_SLL = ( (''sll''))"
+|" rtype_mnemonic_forwards RISCV_SRL = ( (''srl''))"
+|" rtype_mnemonic_forwards RISCV_SUB = ( (''sub''))"
+|" rtype_mnemonic_forwards RISCV_SRA = ( (''sra''))"
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_backwards : string -> M rop\<close>\<close>
+
+definition rtype_mnemonic_backwards :: " string \<Rightarrow>((register_value),(rop),(exception))monad " where
+ " rtype_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''add'')))) then return RISCV_ADD
+ else if (((p00 = (''slt'')))) then return RISCV_SLT
+ else if (((p00 = (''sltu'')))) then return RISCV_SLTU
+ else if (((p00 = (''and'')))) then return RISCV_AND
+ else if (((p00 = (''or'')))) then return RISCV_OR
+ else if (((p00 = (''xor'')))) then return RISCV_XOR
+ else if (((p00 = (''sll'')))) then return RISCV_SLL
+ else if (((p00 = (''srl'')))) then return RISCV_SRL
+ else if (((p00 = (''sub'')))) then return RISCV_SUB
+ else if (((p00 = (''sra'')))) then return RISCV_SRA
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_forwards_matches : rop -> bool\<close>\<close>
+
+fun rtype_mnemonic_forwards_matches :: " rop \<Rightarrow> bool " where
+ " rtype_mnemonic_forwards_matches RISCV_ADD = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLT = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLTU = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_AND = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_OR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_XOR = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SLL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRL = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SUB = ( True )"
+|" rtype_mnemonic_forwards_matches RISCV_SRA = ( True )"
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition rtype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " rtype_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''add'')))) then True
+ else if (((p00 = (''slt'')))) then True
+ else if (((p00 = (''sltu'')))) then True
+ else if (((p00 = (''and'')))) then True
+ else if (((p00 = (''or'')))) then True
+ else if (((p00 = (''xor'')))) then True
+ else if (((p00 = (''sll'')))) then True
+ else if (((p00 = (''srl'')))) then True
+ else if (((p00 = (''sub'')))) then True
+ else if (((p00 = (''sra'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s596_ : string -> maybe string\<close>\<close>
+
+definition s596 :: " string \<Rightarrow>(string)option " where
+ " s596 s5970 = (
+ (let s5980 = s5970 in
+ if ((string_startswith s5980 (''sra''))) then
+ (case ((string_drop s5980 ((string_length (''sra''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5970 :: " string "
+
+
+\<comment> \<open>\<open>val _s592_ : string -> maybe string\<close>\<close>
+
+definition s592 :: " string \<Rightarrow>(string)option " where
+ " s592 s5930 = (
+ (let s5940 = s5930 in
+ if ((string_startswith s5940 (''sub''))) then
+ (case ((string_drop s5940 ((string_length (''sub''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5930 :: " string "
+
+
+\<comment> \<open>\<open>val _s588_ : string -> maybe string\<close>\<close>
+
+definition s588 :: " string \<Rightarrow>(string)option " where
+ " s588 s5890 = (
+ (let s5900 = s5890 in
+ if ((string_startswith s5900 (''srl''))) then
+ (case ((string_drop s5900 ((string_length (''srl''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5890 :: " string "
+
+
+\<comment> \<open>\<open>val _s584_ : string -> maybe string\<close>\<close>
+
+definition s584 :: " string \<Rightarrow>(string)option " where
+ " s584 s5850 = (
+ (let s5860 = s5850 in
+ if ((string_startswith s5860 (''sll''))) then
+ (case ((string_drop s5860 ((string_length (''sll''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5850 :: " string "
+
+
+\<comment> \<open>\<open>val _s580_ : string -> maybe string\<close>\<close>
+
+definition s580 :: " string \<Rightarrow>(string)option " where
+ " s580 s5810 = (
+ (let s5820 = s5810 in
+ if ((string_startswith s5820 (''xor''))) then
+ (case ((string_drop s5820 ((string_length (''xor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5810 :: " string "
+
+
+\<comment> \<open>\<open>val _s576_ : string -> maybe string\<close>\<close>
+
+definition s576 :: " string \<Rightarrow>(string)option " where
+ " s576 s5770 = (
+ (let s5780 = s5770 in
+ if ((string_startswith s5780 (''or''))) then
+ (case ((string_drop s5780 ((string_length (''or''))))) of s1 => Some s1 )
+ else None))"
+ for s5770 :: " string "
+
+
+\<comment> \<open>\<open>val _s572_ : string -> maybe string\<close>\<close>
+
+definition s572 :: " string \<Rightarrow>(string)option " where
+ " s572 s5730 = (
+ (let s5740 = s5730 in
+ if ((string_startswith s5740 (''and''))) then
+ (case ((string_drop s5740 ((string_length (''and''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5730 :: " string "
+
+
+\<comment> \<open>\<open>val _s568_ : string -> maybe string\<close>\<close>
+
+definition s568 :: " string \<Rightarrow>(string)option " where
+ " s568 s5690 = (
+ (let s5700 = s5690 in
+ if ((string_startswith s5700 (''sltu''))) then
+ (case ((string_drop s5700 ((string_length (''sltu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5690 :: " string "
+
+
+\<comment> \<open>\<open>val _s564_ : string -> maybe string\<close>\<close>
+
+definition s564 :: " string \<Rightarrow>(string)option " where
+ " s564 s5650 = (
+ (let s5660 = s5650 in
+ if ((string_startswith s5660 (''slt''))) then
+ (case ((string_drop s5660 ((string_length (''slt''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5650 :: " string "
+
+
+\<comment> \<open>\<open>val _s560_ : string -> maybe string\<close>\<close>
+
+definition s560 :: " string \<Rightarrow>(string)option " where
+ " s560 s5610 = (
+ (let s5620 = s5610 in
+ if ((string_startswith s5620 (''add''))) then
+ (case ((string_drop s5620 ((string_length (''add''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s5610 :: " string "
+
+
+definition rtype_mnemonic_matches_prefix :: " string \<Rightarrow>(rop*int)option " where
+ " rtype_mnemonic_matches_prefix arg1 = (
+ (let s5630 = arg1 in
+ if ((case ((s560 s5630)) of Some (s1) => True | _ => False )) then
+ (case s560 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_ADD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s564 s5630)) of Some (s1) => True | _ => False )) then
+ (case s564 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLT, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s568 s5630)) of Some (s1) => True | _ => False )) then
+ (case s568 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLTU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s572 s5630)) of Some (s1) => True | _ => False )) then
+ (case s572 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_AND, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s576 s5630)) of Some (s1) => True | _ => False )) then
+ (case s576 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_OR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s580 s5630)) of Some (s1) => True | _ => False )) then
+ (case s580 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_XOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s584 s5630)) of Some (s1) => True | _ => False )) then
+ (case s584 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SLL, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s588 s5630)) of Some (s1) => True | _ => False )) then
+ (case s588 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SRL, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s592 s5630)) of Some (s1) => True | _ => False )) then
+ (case s592 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SUB, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s596 s5630)) of Some (s1) => True | _ => False )) then
+ (case s596 s5630 of
+ (Some (s1)) =>
+ Some (RISCV_SRA, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val extend_value : forall 'int8_times_n. Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)\<close>\<close>
+
+fun extend_value :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow>((64)Word.word)MemoryOpResult " where
+ " extend_value is_unsigned (MemValue (v)) = (
+ MemValue (if is_unsigned then (EXTZ (( 64 :: int)::ii) v :: 64 Word.word)
+ else (EXTS (( 64 :: int)::ii) v :: 64 Word.word)))"
+ for is_unsigned :: " bool "
+ and v :: "('int8_times_n::len)Word.word "
+|" extend_value is_unsigned (MemException (e)) = ( MemException e )"
+ for is_unsigned :: " bool "
+ and e :: " ExceptionType "
+
+
+\<comment> \<open>\<open>val process_load : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired\<close>\<close>
+
+definition process_load :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " process_load rd addr value1 is_unsigned = (
+ (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of
+ MemValue (result) => wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ ))"
+ for rd :: "(5)Word.word "
+ and addr :: "(64)Word.word "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+ and is_unsigned :: " bool "
+
+
+\<comment> \<open>\<open>val check_misaligned : mword ty64 -> word_width -> bool\<close>\<close>
+
+definition check_misaligned :: "(64)Word.word \<Rightarrow> word_width \<Rightarrow> bool " where
+ " check_misaligned (vaddr :: xlenbits) (width :: word_width) = (
+ if ((plat_enable_misaligned_access () )) then False
+ else
+ (case width of
+ BYTE => False
+ | HALF => (((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True)
+ | WORD =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True))) \<or> (((((bit_to_bool ((access_vec_dec vaddr (( 1 :: int)::ii))))) = True))))
+ | DOUBLE =>
+ ((((((bit_to_bool ((access_vec_dec vaddr (( 0 :: int)::ii))))) = True))) \<or> ((((((((bit_to_bool ((access_vec_dec vaddr (( 1 :: int)::ii))))) = True))) \<or> (((((bit_to_bool ((access_vec_dec vaddr (( 2 :: int)::ii))))) = True)))))))
+ ))"
+ for vaddr :: "(64)Word.word "
+ and width :: " word_width "
+
+
+\<comment> \<open>\<open>val maybe_aq_forwards : bool -> string\<close>\<close>
+
+fun maybe_aq_forwards :: " bool \<Rightarrow> string " where
+ " maybe_aq_forwards True = ( (''.aq''))"
+|" maybe_aq_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_aq_backwards : string -> M bool\<close>\<close>
+
+definition maybe_aq_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_aq_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.aq'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_aq_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_aq_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_aq_forwards_matches True = ( True )"
+|" maybe_aq_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_aq_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_aq_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_aq_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.aq'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_aq_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s604_ : string -> maybe string\<close>\<close>
+
+definition s604 :: " string \<Rightarrow>(string)option " where
+ " s604 s6050 = (
+ (let s6060 = s6050 in
+ if ((string_startswith s6060 (''''))) then
+ (case ((string_drop s6060 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6050 :: " string "
+
+
+\<comment> \<open>\<open>val _s600_ : string -> maybe string\<close>\<close>
+
+definition s600 :: " string \<Rightarrow>(string)option " where
+ " s600 s6010 = (
+ (let s6020 = s6010 in
+ if ((string_startswith s6020 (''.aq''))) then
+ (case ((string_drop s6020 ((string_length (''.aq''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6010 :: " string "
+
+
+definition maybe_aq_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_aq_matches_prefix arg1 = (
+ (let s6030 = arg1 in
+ if ((case ((s600 s6030)) of Some (s1) => True | _ => False )) then
+ (case s600 s6030 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s604 s6030)) of Some (s1) => True | _ => False )) then
+ (case s604 s6030 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_forwards : bool -> string\<close>\<close>
+
+fun maybe_rl_forwards :: " bool \<Rightarrow> string " where
+ " maybe_rl_forwards True = ( (''.rl''))"
+|" maybe_rl_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_rl_backwards : string -> M bool\<close>\<close>
+
+definition maybe_rl_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_rl_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.rl'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_rl_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_rl_forwards_matches True = ( True )"
+|" maybe_rl_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_rl_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_rl_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_rl_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''.rl'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_rl_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s612_ : string -> maybe string\<close>\<close>
+
+definition s612 :: " string \<Rightarrow>(string)option " where
+ " s612 s6130 = (
+ (let s6140 = s6130 in
+ if ((string_startswith s6140 (''''))) then
+ (case ((string_drop s6140 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6130 :: " string "
+
+
+\<comment> \<open>\<open>val _s608_ : string -> maybe string\<close>\<close>
+
+definition s608 :: " string \<Rightarrow>(string)option " where
+ " s608 s6090 = (
+ (let s6100 = s6090 in
+ if ((string_startswith s6100 (''.rl''))) then
+ (case ((string_drop s6100 ((string_length (''.rl''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6090 :: " string "
+
+
+definition maybe_rl_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_rl_matches_prefix arg1 = (
+ (let s6110 = arg1 in
+ if ((case ((s608 s6110)) of Some (s1) => True | _ => False )) then
+ (case s608 s6110 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s612 s6110)) of Some (s1) => True | _ => False )) then
+ (case s612 s6110 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_forwards : bool -> string\<close>\<close>
+
+fun maybe_u_forwards :: " bool \<Rightarrow> string " where
+ " maybe_u_forwards True = ( (''u''))"
+|" maybe_u_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_u_backwards : string -> M bool\<close>\<close>
+
+definition maybe_u_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_u_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_u_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_u_forwards_matches True = ( True )"
+|" maybe_u_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_u_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_u_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_u_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_u_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s620_ : string -> maybe string\<close>\<close>
+
+definition s620 :: " string \<Rightarrow>(string)option " where
+ " s620 s6210 = (
+ (let s6220 = s6210 in
+ if ((string_startswith s6220 (''''))) then
+ (case ((string_drop s6220 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6210 :: " string "
+
+
+\<comment> \<open>\<open>val _s616_ : string -> maybe string\<close>\<close>
+
+definition s616 :: " string \<Rightarrow>(string)option " where
+ " s616 s6170 = (
+ (let s6180 = s6170 in
+ if ((string_startswith s6180 (''u''))) then
+ (case ((string_drop s6180 ((string_length (''u''))))) of s1 => Some s1 )
+ else None))"
+ for s6170 :: " string "
+
+
+definition maybe_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_u_matches_prefix arg1 = (
+ (let s6190 = arg1 in
+ if ((case ((s616 s6190)) of Some (s1) => True | _ => False )) then
+ (case s616 s6190 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s620 s6190)) of Some (s1) => True | _ => False )) then
+ (case s620 s6190 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_forwards : sop -> string\<close>\<close>
+
+fun shiftw_mnemonic_forwards :: " sop \<Rightarrow> string " where
+ " shiftw_mnemonic_forwards RISCV_SLLI = ( (''slli''))"
+|" shiftw_mnemonic_forwards RISCV_SRLI = ( (''srli''))"
+|" shiftw_mnemonic_forwards RISCV_SRAI = ( (''srai''))"
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_backwards : string -> M sop\<close>\<close>
+
+definition shiftw_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sop),(exception))monad " where
+ " shiftw_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then return RISCV_SLLI
+ else if (((p00 = (''srli'')))) then return RISCV_SRLI
+ else if (((p00 = (''srai'')))) then return RISCV_SRAI
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_forwards_matches : sop -> bool\<close>\<close>
+
+fun shiftw_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where
+ " shiftw_mnemonic_forwards_matches RISCV_SLLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRLI = ( True )"
+|" shiftw_mnemonic_forwards_matches RISCV_SRAI = ( True )"
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftw_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftw_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slli'')))) then True
+ else if (((p00 = (''srli'')))) then True
+ else if (((p00 = (''srai'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s632_ : string -> maybe string\<close>\<close>
+
+definition s632 :: " string \<Rightarrow>(string)option " where
+ " s632 s6330 = (
+ (let s6340 = s6330 in
+ if ((string_startswith s6340 (''srai''))) then
+ (case ((string_drop s6340 ((string_length (''srai''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6330 :: " string "
+
+
+\<comment> \<open>\<open>val _s628_ : string -> maybe string\<close>\<close>
+
+definition s628 :: " string \<Rightarrow>(string)option " where
+ " s628 s6290 = (
+ (let s6300 = s6290 in
+ if ((string_startswith s6300 (''srli''))) then
+ (case ((string_drop s6300 ((string_length (''srli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6290 :: " string "
+
+
+\<comment> \<open>\<open>val _s624_ : string -> maybe string\<close>\<close>
+
+definition s624 :: " string \<Rightarrow>(string)option " where
+ " s624 s6250 = (
+ (let s6260 = s6250 in
+ if ((string_startswith s6260 (''slli''))) then
+ (case ((string_drop s6260 ((string_length (''slli''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6250 :: " string "
+
+
+definition shiftw_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where
+ " shiftw_mnemonic_matches_prefix arg1 = (
+ (let s6270 = arg1 in
+ if ((case ((s624 s6270)) of Some (s1) => True | _ => False )) then
+ (case s624 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SLLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s628 s6270)) of Some (s1) => True | _ => False )) then
+ (case s628 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SRLI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s632 s6270)) of Some (s1) => True | _ => False )) then
+ (case s632 s6270 of
+ (Some (s1)) =>
+ Some (RISCV_SRAI, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_forwards : ropw -> string\<close>\<close>
+
+fun rtypew_mnemonic_forwards :: " ropw \<Rightarrow> string " where
+ " rtypew_mnemonic_forwards RISCV_ADDW = ( (''addw''))"
+|" rtypew_mnemonic_forwards RISCV_SUBW = ( (''subw''))"
+|" rtypew_mnemonic_forwards RISCV_SLLW = ( (''sllw''))"
+|" rtypew_mnemonic_forwards RISCV_SRLW = ( (''srlw''))"
+|" rtypew_mnemonic_forwards RISCV_SRAW = ( (''sraw''))"
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_backwards : string -> M ropw\<close>\<close>
+
+definition rtypew_mnemonic_backwards :: " string \<Rightarrow>((register_value),(ropw),(exception))monad " where
+ " rtypew_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addw'')))) then return RISCV_ADDW
+ else if (((p00 = (''subw'')))) then return RISCV_SUBW
+ else if (((p00 = (''sllw'')))) then return RISCV_SLLW
+ else if (((p00 = (''srlw'')))) then return RISCV_SRLW
+ else if (((p00 = (''sraw'')))) then return RISCV_SRAW
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_forwards_matches : ropw -> bool\<close>\<close>
+
+fun rtypew_mnemonic_forwards_matches :: " ropw \<Rightarrow> bool " where
+ " rtypew_mnemonic_forwards_matches RISCV_ADDW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SUBW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SLLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRLW = ( True )"
+|" rtypew_mnemonic_forwards_matches RISCV_SRAW = ( True )"
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition rtypew_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " rtypew_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''addw'')))) then True
+ else if (((p00 = (''subw'')))) then True
+ else if (((p00 = (''sllw'')))) then True
+ else if (((p00 = (''srlw'')))) then True
+ else if (((p00 = (''sraw'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s652_ : string -> maybe string\<close>\<close>
+
+definition s652 :: " string \<Rightarrow>(string)option " where
+ " s652 s6530 = (
+ (let s6540 = s6530 in
+ if ((string_startswith s6540 (''sraw''))) then
+ (case ((string_drop s6540 ((string_length (''sraw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6530 :: " string "
+
+
+\<comment> \<open>\<open>val _s648_ : string -> maybe string\<close>\<close>
+
+definition s648 :: " string \<Rightarrow>(string)option " where
+ " s648 s6490 = (
+ (let s6500 = s6490 in
+ if ((string_startswith s6500 (''srlw''))) then
+ (case ((string_drop s6500 ((string_length (''srlw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6490 :: " string "
+
+
+\<comment> \<open>\<open>val _s644_ : string -> maybe string\<close>\<close>
+
+definition s644 :: " string \<Rightarrow>(string)option " where
+ " s644 s6450 = (
+ (let s6460 = s6450 in
+ if ((string_startswith s6460 (''sllw''))) then
+ (case ((string_drop s6460 ((string_length (''sllw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6450 :: " string "
+
+
+\<comment> \<open>\<open>val _s640_ : string -> maybe string\<close>\<close>
+
+definition s640 :: " string \<Rightarrow>(string)option " where
+ " s640 s6410 = (
+ (let s6420 = s6410 in
+ if ((string_startswith s6420 (''subw''))) then
+ (case ((string_drop s6420 ((string_length (''subw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6410 :: " string "
+
+
+\<comment> \<open>\<open>val _s636_ : string -> maybe string\<close>\<close>
+
+definition s636 :: " string \<Rightarrow>(string)option " where
+ " s636 s6370 = (
+ (let s6380 = s6370 in
+ if ((string_startswith s6380 (''addw''))) then
+ (case ((string_drop s6380 ((string_length (''addw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6370 :: " string "
+
+
+definition rtypew_mnemonic_matches_prefix :: " string \<Rightarrow>(ropw*int)option " where
+ " rtypew_mnemonic_matches_prefix arg1 = (
+ (let s6390 = arg1 in
+ if ((case ((s636 s6390)) of Some (s1) => True | _ => False )) then
+ (case s636 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_ADDW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s640 s6390)) of Some (s1) => True | _ => False )) then
+ (case s640 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SUBW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s644 s6390)) of Some (s1) => True | _ => False )) then
+ (case s644 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SLLW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s648 s6390)) of Some (s1) => True | _ => False )) then
+ (case s648 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SRLW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s652 s6390)) of Some (s1) => True | _ => False )) then
+ (case s652 s6390 of
+ (Some (s1)) =>
+ Some (RISCV_SRAW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_forwards : sopw -> string\<close>\<close>
+
+fun shiftiwop_mnemonic_forwards :: " sopw \<Rightarrow> string " where
+ " shiftiwop_mnemonic_forwards RISCV_SLLIW = ( (''slliw''))"
+|" shiftiwop_mnemonic_forwards RISCV_SRLIW = ( (''srliw''))"
+|" shiftiwop_mnemonic_forwards RISCV_SRAIW = ( (''sraiw''))"
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_backwards : string -> M sopw\<close>\<close>
+
+definition shiftiwop_mnemonic_backwards :: " string \<Rightarrow>((register_value),(sopw),(exception))monad " where
+ " shiftiwop_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slliw'')))) then return RISCV_SLLIW
+ else if (((p00 = (''srliw'')))) then return RISCV_SRLIW
+ else if (((p00 = (''sraiw'')))) then return RISCV_SRAIW
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_forwards_matches : sopw -> bool\<close>\<close>
+
+fun shiftiwop_mnemonic_forwards_matches :: " sopw \<Rightarrow> bool " where
+ " shiftiwop_mnemonic_forwards_matches RISCV_SLLIW = ( True )"
+|" shiftiwop_mnemonic_forwards_matches RISCV_SRLIW = ( True )"
+|" shiftiwop_mnemonic_forwards_matches RISCV_SRAIW = ( True )"
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition shiftiwop_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " shiftiwop_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''slliw'')))) then True
+ else if (((p00 = (''srliw'')))) then True
+ else if (((p00 = (''sraiw'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val shiftiwop_mnemonic_matches_prefix : string -> maybe ((sopw * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s664_ : string -> maybe string\<close>\<close>
+
+definition s664 :: " string \<Rightarrow>(string)option " where
+ " s664 s6650 = (
+ (let s6660 = s6650 in
+ if ((string_startswith s6660 (''sraiw''))) then
+ (case ((string_drop s6660 ((string_length (''sraiw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6650 :: " string "
+
+
+\<comment> \<open>\<open>val _s660_ : string -> maybe string\<close>\<close>
+
+definition s660 :: " string \<Rightarrow>(string)option " where
+ " s660 s6610 = (
+ (let s6620 = s6610 in
+ if ((string_startswith s6620 (''srliw''))) then
+ (case ((string_drop s6620 ((string_length (''srliw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6610 :: " string "
+
+
+\<comment> \<open>\<open>val _s656_ : string -> maybe string\<close>\<close>
+
+definition s656 :: " string \<Rightarrow>(string)option " where
+ " s656 s6570 = (
+ (let s6580 = s6570 in
+ if ((string_startswith s6580 (''slliw''))) then
+ (case ((string_drop s6580 ((string_length (''slliw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s6570 :: " string "
+
+
+definition shiftiwop_mnemonic_matches_prefix :: " string \<Rightarrow>(sopw*int)option " where
+ " shiftiwop_mnemonic_matches_prefix arg1 = (
+ (let s6590 = arg1 in
+ if ((case ((s656 s6590)) of Some (s1) => True | _ => False )) then
+ (case s656 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SLLIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s660 s6590)) of Some (s1) => True | _ => False )) then
+ (case s660 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SRLIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s664 s6590)) of Some (s1) => True | _ => False )) then
+ (case s664 s6590 of
+ (Some (s1)) =>
+ Some (RISCV_SRAIW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_r_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_r_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''r'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_r_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_r_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''r'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_r_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_r_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_r_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_r_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''r'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s672_ : string -> maybe string\<close>\<close>
+
+definition s672 :: " string \<Rightarrow>(string)option " where
+ " s672 s6730 = (
+ (let s6740 = s6730 in
+ if ((string_startswith s6740 (''''))) then
+ (case ((string_drop s6740 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6730 :: " string "
+
+
+\<comment> \<open>\<open>val _s668_ : string -> maybe string\<close>\<close>
+
+definition s668 :: " string \<Rightarrow>(string)option " where
+ " s668 s6690 = (
+ (let s6700 = s6690 in
+ if ((string_startswith s6700 (''r''))) then
+ (case ((string_drop s6700 ((string_length (''r''))))) of s1 => Some s1 )
+ else None))"
+ for s6690 :: " string "
+
+
+definition bit_maybe_r_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_r_matches_prefix arg1 = (
+ (let s6710 = arg1 in
+ if ((case ((s668 s6710)) of Some (s1) => True | _ => False )) then
+ (case s668 s6710 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s672 s6710)) of Some (s1) => True | _ => False )) then
+ (case s672 s6710 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_w_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_w_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''w'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_w_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_w_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''w'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_w_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_w_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_w_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_w_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''w'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s680_ : string -> maybe string\<close>\<close>
+
+definition s680 :: " string \<Rightarrow>(string)option " where
+ " s680 s6810 = (
+ (let s6820 = s6810 in
+ if ((string_startswith s6820 (''''))) then
+ (case ((string_drop s6820 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6810 :: " string "
+
+
+\<comment> \<open>\<open>val _s676_ : string -> maybe string\<close>\<close>
+
+definition s676 :: " string \<Rightarrow>(string)option " where
+ " s676 s6770 = (
+ (let s6780 = s6770 in
+ if ((string_startswith s6780 (''w''))) then
+ (case ((string_drop s6780 ((string_length (''w''))))) of s1 => Some s1 )
+ else None))"
+ for s6770 :: " string "
+
+
+definition bit_maybe_w_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_w_matches_prefix arg1 = (
+ (let s6790 = arg1 in
+ if ((case ((s676 s6790)) of Some (s1) => True | _ => False )) then
+ (case s676 s6790 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s680 s6790)) of Some (s1) => True | _ => False )) then
+ (case s680 s6790 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_i_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_i_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''i'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_i_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_i_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_i_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_i_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_i_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_i_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s688_ : string -> maybe string\<close>\<close>
+
+definition s688 :: " string \<Rightarrow>(string)option " where
+ " s688 s6890 = (
+ (let s6900 = s6890 in
+ if ((string_startswith s6900 (''''))) then
+ (case ((string_drop s6900 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6890 :: " string "
+
+
+\<comment> \<open>\<open>val _s684_ : string -> maybe string\<close>\<close>
+
+definition s684 :: " string \<Rightarrow>(string)option " where
+ " s684 s6850 = (
+ (let s6860 = s6850 in
+ if ((string_startswith s6860 (''i''))) then
+ (case ((string_drop s6860 ((string_length (''i''))))) of s1 => Some s1 )
+ else None))"
+ for s6850 :: " string "
+
+
+definition bit_maybe_i_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_i_matches_prefix arg1 = (
+ (let s6870 = arg1 in
+ if ((case ((s684 s6870)) of Some (s1) => True | _ => False )) then
+ (case s684 s6870 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s688 s6870)) of Some (s1) => True | _ => False )) then
+ (case s688 s6870 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_forwards : mword ty1 -> M string\<close>\<close>
+
+definition bit_maybe_o_forwards :: "(1)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " bit_maybe_o_forwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then return (''o'')
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then return ('''')
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_backwards : string -> M (mword ty1)\<close>\<close>
+
+definition bit_maybe_o_backwards :: " string \<Rightarrow>((register_value),((1)Word.word),(exception))monad " where
+ " bit_maybe_o_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''o'')))) then return (vec_of_bits [B1] :: 1 Word.word)
+ else if (((p00 = ('''')))) then return (vec_of_bits [B0] :: 1 Word.word)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_forwards_matches : mword ty1 -> bool\<close>\<close>
+
+definition bit_maybe_o_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where
+ " bit_maybe_o_forwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B1] :: 1 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0] :: 1 Word.word)))) then True
+ else False))"
+ for arg1 :: "(1)Word.word "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_backwards_matches : string -> bool\<close>\<close>
+
+definition bit_maybe_o_backwards_matches :: " string \<Rightarrow> bool " where
+ " bit_maybe_o_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''o'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s696_ : string -> maybe string\<close>\<close>
+
+definition s696 :: " string \<Rightarrow>(string)option " where
+ " s696 s6970 = (
+ (let s6980 = s6970 in
+ if ((string_startswith s6980 (''''))) then
+ (case ((string_drop s6980 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s6970 :: " string "
+
+
+\<comment> \<open>\<open>val _s692_ : string -> maybe string\<close>\<close>
+
+definition s692 :: " string \<Rightarrow>(string)option " where
+ " s692 s6930 = (
+ (let s6940 = s6930 in
+ if ((string_startswith s6940 (''o''))) then
+ (case ((string_drop s6940 ((string_length (''o''))))) of s1 => Some s1 )
+ else None))"
+ for s6930 :: " string "
+
+
+definition bit_maybe_o_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where
+ " bit_maybe_o_matches_prefix arg1 = (
+ (let s6950 = arg1 in
+ if ((case ((s692 s6950)) of Some (s1) => True | _ => False )) then
+ (case s692 s6950 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B1] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s696 s6950)) of Some (s1) => True | _ => False )) then
+ (case s696 s6950 of
+ (Some (s1)) =>
+ Some
+ ((vec_of_bits [B0] :: 1 Word.word), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_forwards : mword ty4 -> M string\<close>\<close>
+
+definition fence_bits_forwards :: "(4)Word.word \<Rightarrow>((register_value),(string),(exception))monad " where
+ " fence_bits_forwards v__0 = (
+ (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (w :: 1 bits) = ((subrange_vec_dec v__0 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (let (r :: 1 bits) = ((subrange_vec_dec v__0 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (o1 :: 1 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ bit_maybe_i_forwards i \<bind> (\<lambda> (w__0 :: string) .
+ bit_maybe_o_forwards o1 \<bind> (\<lambda> (w__1 :: string) .
+ bit_maybe_r_forwards r \<bind> (\<lambda> (w__2 :: string) .
+ bit_maybe_w_forwards w \<bind> (\<lambda> (w__3 :: string) .
+ return ((string_append w__0
+ ((string_append w__1 ((string_append w__2 ((string_append w__3 ('''')))))))))))))))))))"
+ for v__0 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val fence_bits_backwards : string -> M (mword ty4)\<close>\<close>
+
+\<comment> \<open>\<open>val _s700_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))\<close>\<close>
+
+definition s700 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word)option " where
+ " s700 s7020 = (
+ (case ((bit_maybe_i_matches_prefix s7020 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7030)) =>
+ (case ((string_drop s7020 s7030)) of
+ s7040 =>
+ (case ((bit_maybe_o_matches_prefix s7040 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7050)) =>
+ (case ((string_drop s7040 s7050)) of
+ s7060 =>
+ (case ((bit_maybe_r_matches_prefix s7060 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7070)) =>
+ (case ((string_drop s7060 s7070)) of
+ s7080 =>
+ (case ((bit_maybe_w_matches_prefix s7080 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7090)) =>
+ (let p00 = (string_drop s7080 s7090) in
+ if (((p00 = ('''')))) then Some (i, o1, r, w) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7020 :: " string "
+
+
+definition fence_bits_backwards :: " string \<Rightarrow>((register_value),((4)Word.word),(exception))monad " where
+ " fence_bits_backwards arg1 = (
+ (let s7100 = arg1 in
+ if ((case ((s700 s7100 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word))option)) of
+ Some ((i, o1, r, w)) => True
+ | _ => False
+ )) then (case
+ (s700 s7100 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word)) option) of
+ (Some ((i, o1, r, w))) =>
+ return
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w :: 2 Word.word)) :: 3 Word.word))
+ :: 4 Word.word))
+ )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_forwards_matches : mword ty4 -> bool\<close>\<close>
+
+definition fence_bits_forwards_matches :: "(4)Word.word \<Rightarrow> bool " where
+ " fence_bits_forwards_matches v__1 = ( True )"
+ for v__1 :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val fence_bits_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s711_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1))\<close>\<close>
+
+definition s711 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word)option " where
+ " s711 s7130 = (
+ (case ((bit_maybe_i_matches_prefix s7130 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7140)) =>
+ (case ((string_drop s7130 s7140)) of
+ s7150 =>
+ (case ((bit_maybe_o_matches_prefix s7150 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7160)) =>
+ (case ((string_drop s7150 s7160)) of
+ s7170 =>
+ (case ((bit_maybe_r_matches_prefix s7170 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7180)) =>
+ (case ((string_drop s7170 s7180)) of
+ s7190 =>
+ (case ((bit_maybe_w_matches_prefix s7190 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7200)) =>
+ (let p00 = (string_drop s7190 s7200) in
+ if (((p00 = ('''')))) then Some (i, o1, r, w) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7130 :: " string "
+
+
+definition fence_bits_backwards_matches :: " string \<Rightarrow> bool " where
+ " fence_bits_backwards_matches arg1 = (
+ (let s7210 = arg1 in
+ if ((case ((s711 s7210 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word))option)) of
+ Some ((i, o1, r, w)) => True
+ | _ => False
+ )) then (case
+ (s711 s7210 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word)) option) of
+ (Some ((i, o1, r, w))) =>
+ True
+ )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s722_ : string -> maybe ((mword ty1 * mword ty1 * mword ty1 * mword ty1 * string))\<close>\<close>
+
+definition s722 :: " string \<Rightarrow>((1)Word.word*(1)Word.word*(1)Word.word*(1)Word.word*string)option " where
+ " s722 s7240 = (
+ (case ((bit_maybe_i_matches_prefix s7240 :: (( 1 Word.word * ii))option)) of
+ Some ((i, s7250)) =>
+ (case ((string_drop s7240 s7250)) of
+ s7260 =>
+ (case ((bit_maybe_o_matches_prefix s7260 :: (( 1 Word.word * ii)) option)) of
+ Some ((o1, s7270)) =>
+ (case ((string_drop s7260 s7270)) of
+ s7280 =>
+ (case ((bit_maybe_r_matches_prefix s7280 :: (( 1 Word.word * ii)) option)) of
+ Some ((r, s7290)) =>
+ (case ((string_drop s7280 s7290)) of
+ s7300 =>
+ (case ((bit_maybe_w_matches_prefix s7300 :: (( 1 Word.word * ii)) option)) of
+ Some ((w, s7310)) =>
+ (case ((string_drop s7300 s7310)) of s1 => Some (i, o1, r, w, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s7240 :: " string "
+
+
+definition fence_bits_matches_prefix :: " string \<Rightarrow>((4)Word.word*int)option " where
+ " fence_bits_matches_prefix arg1 = (
+ (let s7320 = arg1 in
+ if ((case ((s722 s7320 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word * string))option)) of
+ Some ((i, o1, r, w, s1)) => True
+ | _ => False
+ )) then (case
+ (s722 s7320 :: (( 1 Word.word * 1 Word.word * 1 Word.word * 1 Word.word * string)) option) of
+ (Some ((i, o1, r, w, s1))) =>
+ Some
+ ((concat_vec i
+ ((concat_vec o1 ((concat_vec r w :: 2 Word.word)) :: 3 Word.word)) :: 4 Word.word),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val aqrl_str : bool -> bool -> string\<close>\<close>
+
+fun aqrl_str :: " bool \<Rightarrow> bool \<Rightarrow> string " where
+ " aqrl_str (False :: bool) (False :: bool) = ( (''''))"
+|" aqrl_str (False :: bool) (True :: bool) = ( (''.rl''))"
+|" aqrl_str (True :: bool) (False :: bool) = ( (''.aq''))"
+|" aqrl_str (True :: bool) (True :: bool) = ( (''.aqrl''))"
+
+
+\<comment> \<open>\<open>val lrsc_width_str : word_width -> string\<close>\<close>
+
+fun lrsc_width_str :: " word_width \<Rightarrow> string " where
+ " lrsc_width_str BYTE = ( (''.b''))"
+|" lrsc_width_str HALF = ( (''.h''))"
+|" lrsc_width_str WORD = ( (''.w''))"
+|" lrsc_width_str DOUBLE = ( (''.d''))"
+
+
+\<comment> \<open>\<open>val process_loadres : forall 'int8_times_n. Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M Retired\<close>\<close>
+
+definition process_loadres :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " process_loadres rd addr value1 is_unsigned = (
+ (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of
+ MemValue (result) =>
+ (let (_ :: unit) = (load_reservation addr) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS)
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ ))"
+ for rd :: "(5)Word.word "
+ and addr :: "(64)Word.word "
+ and value1 :: "(('int8_times_n::len)Word.word)MemoryOpResult "
+ and is_unsigned :: " bool "
+
+
+\<comment> \<open>\<open>val encdec_amoop_forwards : amoop -> mword ty5\<close>\<close>
+
+fun encdec_amoop_forwards :: " amoop \<Rightarrow>(5)Word.word " where
+ " encdec_amoop_forwards AMOSWAP = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOADD = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOXOR = ( (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOAND = ( (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOOR = ( (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMIN = ( (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMAX = ( (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMINU = ( (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word))"
+|" encdec_amoop_forwards AMOMAXU = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_amoop_backwards : mword ty5 -> M amoop\<close>\<close>
+
+definition encdec_amoop_backwards :: "(5)Word.word \<Rightarrow>((register_value),(amoop),(exception))monad " where
+ " encdec_amoop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))
+ then
+ return AMOSWAP
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOADD
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOXOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOAND
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOOR
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOMIN
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOMAX
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ return AMOMINU
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ return AMOMAXU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_amoop_forwards_matches : amoop -> bool\<close>\<close>
+
+fun encdec_amoop_forwards_matches :: " amoop \<Rightarrow> bool " where
+ " encdec_amoop_forwards_matches AMOSWAP = ( True )"
+|" encdec_amoop_forwards_matches AMOADD = ( True )"
+|" encdec_amoop_forwards_matches AMOXOR = ( True )"
+|" encdec_amoop_forwards_matches AMOAND = ( True )"
+|" encdec_amoop_forwards_matches AMOOR = ( True )"
+|" encdec_amoop_forwards_matches AMOMIN = ( True )"
+|" encdec_amoop_forwards_matches AMOMAX = ( True )"
+|" encdec_amoop_forwards_matches AMOMINU = ( True )"
+|" encdec_amoop_forwards_matches AMOMAXU = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_amoop_backwards_matches : mword ty5 -> bool\<close>\<close>
+
+definition encdec_amoop_backwards_matches :: "(5)Word.word \<Rightarrow> bool " where
+ " encdec_amoop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))
+ then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then
+ True
+ else if (((((regidx_to_regno b__0)) = ((regidx_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then
+ True
+ else False))"
+ for arg1 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_forwards : amoop -> string\<close>\<close>
+
+fun amo_mnemonic_forwards :: " amoop \<Rightarrow> string " where
+ " amo_mnemonic_forwards AMOSWAP = ( (''amoswap''))"
+|" amo_mnemonic_forwards AMOADD = ( (''amoadd''))"
+|" amo_mnemonic_forwards AMOXOR = ( (''amoxor''))"
+|" amo_mnemonic_forwards AMOAND = ( (''amoand''))"
+|" amo_mnemonic_forwards AMOOR = ( (''amoor''))"
+|" amo_mnemonic_forwards AMOMIN = ( (''amomin''))"
+|" amo_mnemonic_forwards AMOMAX = ( (''amomax''))"
+|" amo_mnemonic_forwards AMOMINU = ( (''amominu''))"
+|" amo_mnemonic_forwards AMOMAXU = ( (''amomaxu''))"
+
+
+\<comment> \<open>\<open>val amo_mnemonic_backwards : string -> M amoop\<close>\<close>
+
+definition amo_mnemonic_backwards :: " string \<Rightarrow>((register_value),(amoop),(exception))monad " where
+ " amo_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''amoswap'')))) then return AMOSWAP
+ else if (((p00 = (''amoadd'')))) then return AMOADD
+ else if (((p00 = (''amoxor'')))) then return AMOXOR
+ else if (((p00 = (''amoand'')))) then return AMOAND
+ else if (((p00 = (''amoor'')))) then return AMOOR
+ else if (((p00 = (''amomin'')))) then return AMOMIN
+ else if (((p00 = (''amomax'')))) then return AMOMAX
+ else if (((p00 = (''amominu'')))) then return AMOMINU
+ else if (((p00 = (''amomaxu'')))) then return AMOMAXU
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_forwards_matches : amoop -> bool\<close>\<close>
+
+fun amo_mnemonic_forwards_matches :: " amoop \<Rightarrow> bool " where
+ " amo_mnemonic_forwards_matches AMOSWAP = ( True )"
+|" amo_mnemonic_forwards_matches AMOADD = ( True )"
+|" amo_mnemonic_forwards_matches AMOXOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOAND = ( True )"
+|" amo_mnemonic_forwards_matches AMOOR = ( True )"
+|" amo_mnemonic_forwards_matches AMOMIN = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAX = ( True )"
+|" amo_mnemonic_forwards_matches AMOMINU = ( True )"
+|" amo_mnemonic_forwards_matches AMOMAXU = ( True )"
+
+
+\<comment> \<open>\<open>val amo_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition amo_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " amo_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''amoswap'')))) then True
+ else if (((p00 = (''amoadd'')))) then True
+ else if (((p00 = (''amoxor'')))) then True
+ else if (((p00 = (''amoand'')))) then True
+ else if (((p00 = (''amoor'')))) then True
+ else if (((p00 = (''amomin'')))) then True
+ else if (((p00 = (''amomax'')))) then True
+ else if (((p00 = (''amominu'')))) then True
+ else if (((p00 = (''amomaxu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s765_ : string -> maybe string\<close>\<close>
+
+definition s765 :: " string \<Rightarrow>(string)option " where
+ " s765 s7660 = (
+ (let s7670 = s7660 in
+ if ((string_startswith s7670 (''amomaxu''))) then
+ (case ((string_drop s7670 ((string_length (''amomaxu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7660 :: " string "
+
+
+\<comment> \<open>\<open>val _s761_ : string -> maybe string\<close>\<close>
+
+definition s761 :: " string \<Rightarrow>(string)option " where
+ " s761 s7620 = (
+ (let s7630 = s7620 in
+ if ((string_startswith s7630 (''amominu''))) then
+ (case ((string_drop s7630 ((string_length (''amominu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7620 :: " string "
+
+
+\<comment> \<open>\<open>val _s757_ : string -> maybe string\<close>\<close>
+
+definition s757 :: " string \<Rightarrow>(string)option " where
+ " s757 s7580 = (
+ (let s7590 = s7580 in
+ if ((string_startswith s7590 (''amomax''))) then
+ (case ((string_drop s7590 ((string_length (''amomax''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7580 :: " string "
+
+
+\<comment> \<open>\<open>val _s753_ : string -> maybe string\<close>\<close>
+
+definition s753 :: " string \<Rightarrow>(string)option " where
+ " s753 s7540 = (
+ (let s7550 = s7540 in
+ if ((string_startswith s7550 (''amomin''))) then
+ (case ((string_drop s7550 ((string_length (''amomin''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7540 :: " string "
+
+
+\<comment> \<open>\<open>val _s749_ : string -> maybe string\<close>\<close>
+
+definition s749 :: " string \<Rightarrow>(string)option " where
+ " s749 s7500 = (
+ (let s7510 = s7500 in
+ if ((string_startswith s7510 (''amoor''))) then
+ (case ((string_drop s7510 ((string_length (''amoor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7500 :: " string "
+
+
+\<comment> \<open>\<open>val _s745_ : string -> maybe string\<close>\<close>
+
+definition s745 :: " string \<Rightarrow>(string)option " where
+ " s745 s7460 = (
+ (let s7470 = s7460 in
+ if ((string_startswith s7470 (''amoand''))) then
+ (case ((string_drop s7470 ((string_length (''amoand''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7460 :: " string "
+
+
+\<comment> \<open>\<open>val _s741_ : string -> maybe string\<close>\<close>
+
+definition s741 :: " string \<Rightarrow>(string)option " where
+ " s741 s7420 = (
+ (let s7430 = s7420 in
+ if ((string_startswith s7430 (''amoxor''))) then
+ (case ((string_drop s7430 ((string_length (''amoxor''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7420 :: " string "
+
+
+\<comment> \<open>\<open>val _s737_ : string -> maybe string\<close>\<close>
+
+definition s737 :: " string \<Rightarrow>(string)option " where
+ " s737 s7380 = (
+ (let s7390 = s7380 in
+ if ((string_startswith s7390 (''amoadd''))) then
+ (case ((string_drop s7390 ((string_length (''amoadd''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7380 :: " string "
+
+
+\<comment> \<open>\<open>val _s733_ : string -> maybe string\<close>\<close>
+
+definition s733 :: " string \<Rightarrow>(string)option " where
+ " s733 s7340 = (
+ (let s7350 = s7340 in
+ if ((string_startswith s7350 (''amoswap''))) then
+ (case ((string_drop s7350 ((string_length (''amoswap''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7340 :: " string "
+
+
+definition amo_mnemonic_matches_prefix :: " string \<Rightarrow>(amoop*int)option " where
+ " amo_mnemonic_matches_prefix arg1 = (
+ (let s7360 = arg1 in
+ if ((case ((s733 s7360)) of Some (s1) => True | _ => False )) then
+ (case s733 s7360 of
+ (Some (s1)) =>
+ Some (AMOSWAP, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s737 s7360)) of Some (s1) => True | _ => False )) then
+ (case s737 s7360 of
+ (Some (s1)) =>
+ Some (AMOADD, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s741 s7360)) of Some (s1) => True | _ => False )) then
+ (case s741 s7360 of
+ (Some (s1)) =>
+ Some (AMOXOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s745 s7360)) of Some (s1) => True | _ => False )) then
+ (case s745 s7360 of
+ (Some (s1)) =>
+ Some (AMOAND, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s749 s7360)) of Some (s1) => True | _ => False )) then
+ (case s749 s7360 of
+ (Some (s1)) =>
+ Some (AMOOR, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s753 s7360)) of Some (s1) => True | _ => False )) then
+ (case s753 s7360 of
+ (Some (s1)) =>
+ Some (AMOMIN, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s757 s7360)) of Some (s1) => True | _ => False )) then
+ (case s757 s7360 of
+ (Some (s1)) =>
+ Some (AMOMAX, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s761 s7360)) of Some (s1) => True | _ => False )) then
+ (case s761 s7360 of
+ (Some (s1)) =>
+ Some (AMOMINU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s765 s7360)) of Some (s1) => True | _ => False )) then
+ (case s765 s7360 of
+ (Some (s1)) =>
+ Some (AMOMAXU, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_mul_op_forwards : (bool * bool * bool) -> mword ty3\<close>\<close>
+
+fun encdec_mul_op_forwards :: " bool*bool*bool \<Rightarrow>(3)Word.word " where
+ " encdec_mul_op_forwards (False, True, True) = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, True, True) = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, True, False) = ( (vec_of_bits [B0,B1,B0] :: 3 Word.word))"
+|" encdec_mul_op_forwards (True, False, False) = ( (vec_of_bits [B0,B1,B1] :: 3 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_mul_op_backwards : mword ty3 -> M (bool * bool * bool)\<close>\<close>
+
+definition encdec_mul_op_backwards :: "(3)Word.word \<Rightarrow>((register_value),(bool*bool*bool),(exception))monad " where
+ " encdec_mul_op_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then return (False, True, True)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then return (True, True, True)
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then return (True, True, False)
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then return (True, False, False)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_mul_op_forwards_matches : (bool * bool * bool) -> bool\<close>\<close>
+
+fun encdec_mul_op_forwards_matches :: " bool*bool*bool \<Rightarrow> bool " where
+ " encdec_mul_op_forwards_matches (False, True, True) = ( True )"
+|" encdec_mul_op_forwards_matches (True, True, True) = ( True )"
+|" encdec_mul_op_forwards_matches (True, True, False) = ( True )"
+|" encdec_mul_op_forwards_matches (True, False, False) = ( True )"
+|" encdec_mul_op_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_mul_op_backwards_matches : mword ty3 -> bool\<close>\<close>
+
+definition encdec_mul_op_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where
+ " encdec_mul_op_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True
+ else False))"
+ for arg1 :: "(3)Word.word "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_forwards : (bool * bool * bool) -> string\<close>\<close>
+
+fun mul_mnemonic_forwards :: " bool*bool*bool \<Rightarrow> string " where
+ " mul_mnemonic_forwards (False, True, True) = ( (''mul''))"
+|" mul_mnemonic_forwards (True, True, True) = ( (''mulh''))"
+|" mul_mnemonic_forwards (True, True, False) = ( (''mulhsu''))"
+|" mul_mnemonic_forwards (True, False, False) = ( (''mulhu''))"
+
+
+\<comment> \<open>\<open>val mul_mnemonic_backwards : string -> M (bool * bool * bool)\<close>\<close>
+
+definition mul_mnemonic_backwards :: " string \<Rightarrow>((register_value),(bool*bool*bool),(exception))monad " where
+ " mul_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''mul'')))) then return (False, True, True)
+ else if (((p00 = (''mulh'')))) then return (True, True, True)
+ else if (((p00 = (''mulhsu'')))) then return (True, True, False)
+ else if (((p00 = (''mulhu'')))) then return (True, False, False)
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_forwards_matches : (bool * bool * bool) -> bool\<close>\<close>
+
+fun mul_mnemonic_forwards_matches :: " bool*bool*bool \<Rightarrow> bool " where
+ " mul_mnemonic_forwards_matches (False, True, True) = ( True )"
+|" mul_mnemonic_forwards_matches (True, True, True) = ( True )"
+|" mul_mnemonic_forwards_matches (True, True, False) = ( True )"
+|" mul_mnemonic_forwards_matches (True, False, False) = ( True )"
+|" mul_mnemonic_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val mul_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition mul_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " mul_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''mul'')))) then True
+ else if (((p00 = (''mulh'')))) then True
+ else if (((p00 = (''mulhsu'')))) then True
+ else if (((p00 = (''mulhu'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s781_ : string -> maybe string\<close>\<close>
+
+definition s781 :: " string \<Rightarrow>(string)option " where
+ " s781 s7820 = (
+ (let s7830 = s7820 in
+ if ((string_startswith s7830 (''mulhu''))) then
+ (case ((string_drop s7830 ((string_length (''mulhu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7820 :: " string "
+
+
+\<comment> \<open>\<open>val _s777_ : string -> maybe string\<close>\<close>
+
+definition s777 :: " string \<Rightarrow>(string)option " where
+ " s777 s7780 = (
+ (let s7790 = s7780 in
+ if ((string_startswith s7790 (''mulhsu''))) then
+ (case ((string_drop s7790 ((string_length (''mulhsu''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7780 :: " string "
+
+
+\<comment> \<open>\<open>val _s773_ : string -> maybe string\<close>\<close>
+
+definition s773 :: " string \<Rightarrow>(string)option " where
+ " s773 s7740 = (
+ (let s7750 = s7740 in
+ if ((string_startswith s7750 (''mulh''))) then
+ (case ((string_drop s7750 ((string_length (''mulh''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7740 :: " string "
+
+
+\<comment> \<open>\<open>val _s769_ : string -> maybe string\<close>\<close>
+
+definition s769 :: " string \<Rightarrow>(string)option " where
+ " s769 s7700 = (
+ (let s7710 = s7700 in
+ if ((string_startswith s7710 (''mul''))) then
+ (case ((string_drop s7710 ((string_length (''mul''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s7700 :: " string "
+
+
+definition mul_mnemonic_matches_prefix :: " string \<Rightarrow>((bool*bool*bool)*int)option " where
+ " mul_mnemonic_matches_prefix arg1 = (
+ (let s7720 = arg1 in
+ if ((case ((s769 s7720)) of Some (s1) => True | _ => False )) then
+ (case s769 s7720 of
+ (Some (s1)) =>
+ Some ((False, True, True), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s773 s7720)) of Some (s1) => True | _ => False )) then
+ (case s773 s7720 of
+ (Some (s1)) =>
+ Some ((True, True, True), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s777 s7720)) of Some (s1) => True | _ => False )) then
+ (case s777 s7720 of
+ (Some (s1)) =>
+ Some ((True, True, False), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s781 s7720)) of Some (s1) => True | _ => False )) then
+ (case s781 s7720 of
+ (Some (s1)) =>
+ Some ((True, False, False), ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_forwards : bool -> string\<close>\<close>
+
+fun maybe_not_u_forwards :: " bool \<Rightarrow> string " where
+ " maybe_not_u_forwards False = ( (''u''))"
+|" maybe_not_u_forwards True = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_not_u_backwards : string -> M bool\<close>\<close>
+
+definition maybe_not_u_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_not_u_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then return False
+ else if (((p00 = ('''')))) then return True
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_not_u_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_not_u_forwards_matches False = ( True )"
+|" maybe_not_u_forwards_matches True = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_not_u_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_not_u_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_not_u_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''u'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s789_ : string -> maybe string\<close>\<close>
+
+definition s789 :: " string \<Rightarrow>(string)option " where
+ " s789 s7900 = (
+ (let s7910 = s7900 in
+ if ((string_startswith s7910 (''''))) then
+ (case ((string_drop s7910 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s7900 :: " string "
+
+
+\<comment> \<open>\<open>val _s785_ : string -> maybe string\<close>\<close>
+
+definition s785 :: " string \<Rightarrow>(string)option " where
+ " s785 s7860 = (
+ (let s7870 = s7860 in
+ if ((string_startswith s7870 (''u''))) then
+ (case ((string_drop s7870 ((string_length (''u''))))) of s1 => Some s1 )
+ else None))"
+ for s7860 :: " string "
+
+
+definition maybe_not_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_not_u_matches_prefix arg1 = (
+ (let s7880 = arg1 in
+ if ((case ((s785 s7880)) of Some (s1) => True | _ => False )) then
+ (case s785 s7880 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s789 s7880)) of Some (s1) => True | _ => False )) then
+ (case s789 s7880 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_csrop_forwards : csrop -> mword ty2\<close>\<close>
+
+fun encdec_csrop_forwards :: " csrop \<Rightarrow>(2)Word.word " where
+ " encdec_csrop_forwards CSRRW = ( (vec_of_bits [B0,B1] :: 2 Word.word))"
+|" encdec_csrop_forwards CSRRS = ( (vec_of_bits [B1,B0] :: 2 Word.word))"
+|" encdec_csrop_forwards CSRRC = ( (vec_of_bits [B1,B1] :: 2 Word.word))"
+
+
+\<comment> \<open>\<open>val encdec_csrop_backwards : mword ty2 -> M csrop\<close>\<close>
+
+definition encdec_csrop_backwards :: "(2)Word.word \<Rightarrow>((register_value),(csrop),(exception))monad " where
+ " encdec_csrop_backwards arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return CSRRW
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return CSRRS
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then return CSRRC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_csrop_forwards_matches : csrop -> bool\<close>\<close>
+
+fun encdec_csrop_forwards_matches :: " csrop \<Rightarrow> bool " where
+ " encdec_csrop_forwards_matches CSRRW = ( True )"
+|" encdec_csrop_forwards_matches CSRRS = ( True )"
+|" encdec_csrop_forwards_matches CSRRC = ( True )"
+
+
+\<comment> \<open>\<open>val encdec_csrop_backwards_matches : mword ty2 -> bool\<close>\<close>
+
+definition encdec_csrop_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where
+ " encdec_csrop_backwards_matches arg1 = (
+ (let b__0 = arg1 in
+ if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True
+ else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True
+ else False))"
+ for arg1 :: "(2)Word.word "
+
+
+\<comment> \<open>\<open>val readCSR : mword ty12 -> M (mword ty64)\<close>\<close>
+
+definition readCSR :: "(12)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where
+ " readCSR csr = (
+ (case (csr, (( 64 :: int)::ii)) of
+ (b__0, g__15) =>
+ if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg mvendorid_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) .
+ return ((EXTZ (( 64 :: int)::ii) w__0 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg marchid_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg mimpid_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg mhartid_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ return ((get_Mstatus_bits w__4 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) . return ((get_Misa_bits w__5 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) .
+ return ((get_Medeleg_bits w__6 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__7 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__8 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_mtvec () :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__10 :: Counteren) .
+ return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__10 :: 32 Word.word)) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mscratch_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target Machine :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) .
+ return ((and_vec w__12 w__13 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg mcause_ref \<bind> (\<lambda> (w__14 :: Mcause) .
+ return ((get_Mcause_bits w__14 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg mtval_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__16 :: Minterrupts) .
+ return ((get_Minterrupts_bits w__16 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (pmpReadCfgReg (( 0 :: int)::ii) :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (pmpReadCfgReg (( 2 :: int)::ii) :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr0_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr1_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr2_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr3_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr4_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr5_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr6_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr7_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr8_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr9_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr10_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr11_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr12_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr13_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ (read_reg pmpaddr14_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ (read_reg pmpaddr15_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__35 :: 64 Word.word) .
+ return ((subrange_vec_dec w__35 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 :: 64 Word.word) .
+ return ((subrange_vec_dec w__36 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg tselect_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: 64 Word.word) .
+ return ((not_vec w__37 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__38 :: Mstatus) .
+ return ((get_Sstatus_bits ((lower_mstatus w__38)) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg sedeleg_ref \<bind> (\<lambda> (w__39 :: Sedeleg) .
+ return ((get_Sedeleg_bits w__39 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg sideleg_ref \<bind> (\<lambda> (w__40 :: Sinterrupts) .
+ return ((get_Sinterrupts_bits w__40 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__41 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__42 :: Minterrupts) .
+ return ((get_Sinterrupts_bits ((lower_mie w__41 w__42)) :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (get_stvec () :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg scounteren_ref \<bind> (\<lambda> (w__44 :: Counteren) .
+ return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__44 :: 32 Word.word)) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg sscratch_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (get_xret_target Supervisor :: ( 64 Word.word) M) \<bind> (\<lambda> (w__46 :: 64 Word.word) .
+ (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__47 :: 64 Word.word) .
+ return ((and_vec w__46 w__47 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg scause_ref \<bind> (\<lambda> (w__48 :: Mcause) .
+ return ((get_Mcause_bits w__48 :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (read_reg stval_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__50 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__51 :: Minterrupts) .
+ return ((get_Sinterrupts_bits ((lower_mip w__50 w__51)) :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg satp_ref :: ( 64 Word.word) M)
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__53 :: 64 Word.word) .
+ return ((subrange_vec_dec w__53 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__54 :: 64 Word.word) .
+ return ((subrange_vec_dec w__54 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)))
+ else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__55 :: 64 Word.word) .
+ return ((subrange_vec_dec w__55 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)))
+ else
+ (ext_read_CSR csr :: ( ( 64 Word.word)option) M) \<bind> (\<lambda> (w__56 :: ( 64 Word.word)option) .
+ return ((case w__56 of
+ Some (res) => res
+ | None =>
+ (let (_ :: unit) = (print_bits0 (''unhandled read to CSR '') csr) in
+ (EXTZ (( 64 :: int)::ii) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 64 Word.word))
+ )))
+ ) \<bind> (\<lambda> (res :: xlenbits) .
+ (let (_ :: unit) =
+ (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr)) (((@) ('' -> '') ((string_of_bits res))))))))
+ else () ) in
+ return res)))"
+ for csr :: "(12)Word.word "
+
+
+\<comment> \<open>\<open>val writeCSR : mword ty12 -> mword ty64 -> M unit\<close>\<close>
+
+definition writeCSR :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " writeCSR (csr :: csreg) (value1 :: xlenbits) = (
+ (case (csr, (( 64 :: int)::ii)) of
+ (b__0, g__14) =>
+ if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) .
+ legalize_mstatus w__0 value1 \<bind> (\<lambda> (w__1 :: Mstatus) .
+ (write_reg mstatus_ref w__1 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__2 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg misa_ref \<bind> (\<lambda> (w__3 :: Misa) .
+ legalize_misa w__3 value1 \<bind> (\<lambda> (w__4 :: Misa) .
+ (write_reg misa_ref w__4 \<then>
+ read_reg misa_ref) \<bind> (\<lambda> (w__5 :: Misa) .
+ return (Some ((get_Misa_bits w__5 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) .
+ (write_reg medeleg_ref ((legalize_medeleg w__6 value1)) \<then>
+ read_reg medeleg_ref) \<bind> (\<lambda> (w__7 :: Medeleg) .
+ return (Some ((get_Medeleg_bits w__7 :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg mideleg_ref \<bind> (\<lambda> (w__8 :: Minterrupts) .
+ (write_reg mideleg_ref ((legalize_mideleg w__8 value1)) \<then>
+ read_reg mideleg_ref) \<bind> (\<lambda> (w__9 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__9 :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__10 :: Minterrupts) .
+ legalize_mie w__10 value1 \<bind> (\<lambda> (w__11 :: Minterrupts) .
+ (write_reg mie_ref w__11 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__12 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__12 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_mtvec value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) . return (Some w__13))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg mcounteren_ref \<bind> (\<lambda> (w__14 :: Counteren) .
+ (write_reg mcounteren_ref ((legalize_mcounteren w__14 value1)) \<then>
+ read_reg mcounteren_ref) \<bind> (\<lambda> (w__15 :: Counteren) .
+ return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__15 :: 32 Word.word)) :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg mscratch_ref value1 \<then>
+ (read_reg mscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__16 :: 64 Word.word) .
+ return (Some w__16))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target Machine value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 Word.word) .
+ return (Some w__17))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits mcause_ref value1 \<then>
+ read_reg mcause_ref) \<bind> (\<lambda> (w__18 :: Mcause) .
+ return (Some ((get_Mcause_bits w__18 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg mtval_ref value1 \<then>
+ (read_reg mtval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 :: 64 Word.word) . return (Some w__19))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__20 :: Minterrupts) .
+ legalize_mip w__20 value1 \<bind> (\<lambda> (w__21 :: Minterrupts) .
+ (write_reg mip_ref w__21 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__22 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__22 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ pmpWriteCfgReg (( 0 :: int)::ii) value1 \<then> return (Some value1)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ pmpWriteCfgReg (( 2 :: int)::ii) value1 \<then> return (Some value1)
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp0cfg_ref \<bind> (\<lambda> (w__23 :: Pmpcfg_ent) .
+ (read_reg pmpaddr0_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 Word.word) .
+ (write_reg pmpaddr0_ref ((pmpWriteAddr w__23 w__24 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr0_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__25 :: 64 Word.word) .
+ return (Some w__25))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp1cfg_ref \<bind> (\<lambda> (w__26 :: Pmpcfg_ent) .
+ (read_reg pmpaddr1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 Word.word) .
+ (write_reg pmpaddr1_ref ((pmpWriteAddr w__26 w__27 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__28 :: 64 Word.word) .
+ return (Some w__28))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp2cfg_ref \<bind> (\<lambda> (w__29 :: Pmpcfg_ent) .
+ (read_reg pmpaddr2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__30 :: 64 Word.word) .
+ (write_reg pmpaddr2_ref ((pmpWriteAddr w__29 w__30 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 Word.word) .
+ return (Some w__31))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp3cfg_ref \<bind> (\<lambda> (w__32 :: Pmpcfg_ent) .
+ (read_reg pmpaddr3_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__33 :: 64 Word.word) .
+ (write_reg pmpaddr3_ref ((pmpWriteAddr w__32 w__33 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr3_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__34 :: 64 Word.word) .
+ return (Some w__34))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp4cfg_ref \<bind> (\<lambda> (w__35 :: Pmpcfg_ent) .
+ (read_reg pmpaddr4_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 :: 64 Word.word) .
+ (write_reg pmpaddr4_ref ((pmpWriteAddr w__35 w__36 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr4_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 :: 64 Word.word) .
+ return (Some w__37))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp5cfg_ref \<bind> (\<lambda> (w__38 :: Pmpcfg_ent) .
+ (read_reg pmpaddr5_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__39 :: 64 Word.word) .
+ (write_reg pmpaddr5_ref ((pmpWriteAddr w__38 w__39 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr5_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__40 :: 64 Word.word) .
+ return (Some w__40))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp6cfg_ref \<bind> (\<lambda> (w__41 :: Pmpcfg_ent) .
+ (read_reg pmpaddr6_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__42 :: 64 Word.word) .
+ (write_reg pmpaddr6_ref ((pmpWriteAddr w__41 w__42 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr6_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__43 :: 64 Word.word) .
+ return (Some w__43))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp7cfg_ref \<bind> (\<lambda> (w__44 :: Pmpcfg_ent) .
+ (read_reg pmpaddr7_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__45 :: 64 Word.word) .
+ (write_reg pmpaddr7_ref ((pmpWriteAddr w__44 w__45 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr7_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__46 :: 64 Word.word) .
+ return (Some w__46))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp8cfg_ref \<bind> (\<lambda> (w__47 :: Pmpcfg_ent) .
+ (read_reg pmpaddr8_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__48 :: 64 Word.word) .
+ (write_reg pmpaddr8_ref ((pmpWriteAddr w__47 w__48 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr8_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__49 :: 64 Word.word) .
+ return (Some w__49))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp9cfg_ref \<bind> (\<lambda> (w__50 :: Pmpcfg_ent) .
+ (read_reg pmpaddr9_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__51 :: 64 Word.word) .
+ (write_reg pmpaddr9_ref ((pmpWriteAddr w__50 w__51 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr9_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__52 :: 64 Word.word) .
+ return (Some w__52))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp10cfg_ref \<bind> (\<lambda> (w__53 :: Pmpcfg_ent) .
+ (read_reg pmpaddr10_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__54 :: 64 Word.word) .
+ (write_reg pmpaddr10_ref ((pmpWriteAddr w__53 w__54 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr10_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__55 :: 64 Word.word) .
+ return (Some w__55))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp11cfg_ref \<bind> (\<lambda> (w__56 :: Pmpcfg_ent) .
+ (read_reg pmpaddr11_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__57 :: 64 Word.word) .
+ (write_reg pmpaddr11_ref ((pmpWriteAddr w__56 w__57 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr11_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__58 :: 64 Word.word) .
+ return (Some w__58))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg pmp12cfg_ref \<bind> (\<lambda> (w__59 :: Pmpcfg_ent) .
+ (read_reg pmpaddr12_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 Word.word) .
+ (write_reg pmpaddr12_ref ((pmpWriteAddr w__59 w__60 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr12_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__61 :: 64 Word.word) .
+ return (Some w__61))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then
+ read_reg pmp13cfg_ref \<bind> (\<lambda> (w__62 :: Pmpcfg_ent) .
+ (read_reg pmpaddr13_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__63 :: 64 Word.word) .
+ (write_reg pmpaddr13_ref ((pmpWriteAddr w__62 w__63 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr13_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__64 :: 64 Word.word) .
+ return (Some w__64))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg pmp14cfg_ref \<bind> (\<lambda> (w__65 :: Pmpcfg_ent) .
+ (read_reg pmpaddr14_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__66 :: 64 Word.word) .
+ (write_reg pmpaddr14_ref ((pmpWriteAddr w__65 w__66 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr14_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__67 :: 64 Word.word) .
+ return (Some w__67))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then
+ read_reg pmp15cfg_ref \<bind> (\<lambda> (w__68 :: Pmpcfg_ent) .
+ (read_reg pmpaddr15_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__69 :: 64 Word.word) .
+ (write_reg pmpaddr15_ref ((pmpWriteAddr w__68 w__69 value1 :: 64 Word.word)) \<then>
+ (read_reg pmpaddr15_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__70 :: 64 Word.word) .
+ return (Some w__70))))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__71 :: 64 Word.word) .
+ write_reg
+ mcycle_ref
+ ((update_subrange_vec_dec w__71 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ return (Some value1))
+ else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__72 :: 64 Word.word) .
+ (write_reg
+ minstret_ref
+ ((update_subrange_vec_dec w__72 (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) value1 :: 64 Word.word)) \<then>
+ write_reg minstret_written_ref True) \<then> return (Some value1))
+ else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg tselect_ref value1 \<then>
+ (read_reg tselect_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__73 :: 64 Word.word) . return (Some w__73))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ read_reg mstatus_ref \<bind> (\<lambda> (w__74 :: Mstatus) .
+ legalize_sstatus w__74 value1 \<bind> (\<lambda> (w__75 :: Mstatus) .
+ (write_reg mstatus_ref w__75 \<then>
+ read_reg mstatus_ref) \<bind> (\<lambda> (w__76 :: Mstatus) .
+ return (Some ((get_Mstatus_bits w__76 :: 64 Word.word))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ read_reg sedeleg_ref \<bind> (\<lambda> (w__77 :: Sedeleg) .
+ (write_reg sedeleg_ref ((legalize_sedeleg w__77 value1)) \<then>
+ read_reg sedeleg_ref) \<bind> (\<lambda> (w__78 :: Sedeleg) .
+ return (Some ((get_Sedeleg_bits w__78 :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (set_Sinterrupts_bits sideleg_ref value1 \<then>
+ read_reg sideleg_ref) \<bind> (\<lambda> (w__79 :: Sinterrupts) .
+ return (Some ((get_Sinterrupts_bits w__79 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mie_ref \<bind> (\<lambda> (w__80 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__81 :: Minterrupts) .
+ legalize_sie w__80 w__81 value1 \<bind> (\<lambda> (w__82 :: Minterrupts) .
+ (write_reg mie_ref w__82 \<then>
+ read_reg mie_ref) \<bind> (\<lambda> (w__83 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__83 :: 64 Word.word)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then
+ (set_stvec value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__84 :: 64 Word.word) . return (Some w__84))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then
+ read_reg scounteren_ref \<bind> (\<lambda> (w__85 :: Counteren) .
+ (write_reg scounteren_ref ((legalize_scounteren w__85 value1)) \<then>
+ read_reg scounteren_ref) \<bind> (\<lambda> (w__86 :: Counteren) .
+ return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__86 :: 32 Word.word)) :: 64 Word.word)))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ (write_reg sscratch_ref value1 \<then>
+ (read_reg sscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__87 :: 64 Word.word) .
+ return (Some w__87))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then
+ (set_xret_target Supervisor value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__88 :: 64 Word.word) .
+ return (Some w__88))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then
+ (set_Mcause_bits scause_ref value1 \<then>
+ read_reg scause_ref) \<bind> (\<lambda> (w__89 :: Mcause) .
+ return (Some ((get_Mcause_bits w__89 :: 64 Word.word))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then
+ (write_reg stval_ref value1 \<then>
+ (read_reg stval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 Word.word) . return (Some w__90))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then
+ read_reg mip_ref \<bind> (\<lambda> (w__91 :: Minterrupts) .
+ read_reg mideleg_ref \<bind> (\<lambda> (w__92 :: Minterrupts) .
+ legalize_sip w__91 w__92 value1 \<bind> (\<lambda> (w__93 :: Minterrupts) .
+ (write_reg mip_ref w__93 \<then>
+ read_reg mip_ref) \<bind> (\<lambda> (w__94 :: Minterrupts) .
+ return (Some ((get_Minterrupts_bits w__94 :: 64 Word.word)))))))
+ else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then
+ cur_Architecture () \<bind> (\<lambda> (w__95 :: Architecture) .
+ (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__96 :: 64 Word.word) .
+ (write_reg satp_ref ((legalize_satp w__95 w__96 value1 :: 64 Word.word)) \<then>
+ (read_reg satp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__97 :: 64 Word.word) . return (Some w__97))))
+ else return None
+ ) \<bind> (\<lambda> (res :: xlenbits option) .
+ (case res of
+ Some (v) =>
+ return (if ((get_config_print_reg () )) then
+ print_dbg
+ (((@) (''CSR '')
+ (((@) ((csr_name csr))
+ (((@) ('' <- '')
+ (((@) ((string_of_bits v))
+ (((@) ('' (input: '')
+ (((@) ((string_of_bits value1)) ('')'')))))))))))))
+ else () )
+ | None =>
+ ext_write_CSR csr value1 \<bind> (\<lambda> (w__143 :: bool) .
+ return (if w__143 then ()
+ else print_bits0 (''unhandled write to CSR '') csr))
+ )))"
+ for csr :: "(12)Word.word "
+ and value1 :: "(64)Word.word "
+
+
+\<comment> \<open>\<open>val maybe_i_forwards : bool -> string\<close>\<close>
+
+fun maybe_i_forwards :: " bool \<Rightarrow> string " where
+ " maybe_i_forwards True = ( (''i''))"
+|" maybe_i_forwards False = ( (''''))"
+
+
+\<comment> \<open>\<open>val maybe_i_backwards : string -> M bool\<close>\<close>
+
+definition maybe_i_backwards :: " string \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " maybe_i_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then return True
+ else if (((p00 = ('''')))) then return False
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_i_forwards_matches : bool -> bool\<close>\<close>
+
+fun maybe_i_forwards_matches :: " bool \<Rightarrow> bool " where
+ " maybe_i_forwards_matches True = ( True )"
+|" maybe_i_forwards_matches False = ( True )"
+
+
+\<comment> \<open>\<open>val maybe_i_backwards_matches : string -> bool\<close>\<close>
+
+definition maybe_i_backwards_matches :: " string \<Rightarrow> bool " where
+ " maybe_i_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''i'')))) then True
+ else if (((p00 = ('''')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val maybe_i_matches_prefix : string -> maybe ((bool * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s797_ : string -> maybe string\<close>\<close>
+
+definition s797 :: " string \<Rightarrow>(string)option " where
+ " s797 s7980 = (
+ (let s7990 = s7980 in
+ if ((string_startswith s7990 (''''))) then
+ (case ((string_drop s7990 ((string_length (''''))))) of s1 => Some s1 )
+ else None))"
+ for s7980 :: " string "
+
+
+\<comment> \<open>\<open>val _s793_ : string -> maybe string\<close>\<close>
+
+definition s793 :: " string \<Rightarrow>(string)option " where
+ " s793 s7940 = (
+ (let s7950 = s7940 in
+ if ((string_startswith s7950 (''i''))) then
+ (case ((string_drop s7950 ((string_length (''i''))))) of s1 => Some s1 )
+ else None))"
+ for s7940 :: " string "
+
+
+definition maybe_i_matches_prefix :: " string \<Rightarrow>(bool*int)option " where
+ " maybe_i_matches_prefix arg1 = (
+ (let s7960 = arg1 in
+ if ((case ((s793 s7960)) of Some (s1) => True | _ => False )) then
+ (case s793 s7960 of
+ (Some (s1)) =>
+ Some (True, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s797 s7960)) of Some (s1) => True | _ => False )) then
+ (case s797 s7960 of
+ (Some (s1)) =>
+ Some (False, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_forwards : csrop -> string\<close>\<close>
+
+fun csr_mnemonic_forwards :: " csrop \<Rightarrow> string " where
+ " csr_mnemonic_forwards CSRRW = ( (''csrrw''))"
+|" csr_mnemonic_forwards CSRRS = ( (''csrrs''))"
+|" csr_mnemonic_forwards CSRRC = ( (''csrrc''))"
+
+
+\<comment> \<open>\<open>val csr_mnemonic_backwards : string -> M csrop\<close>\<close>
+
+definition csr_mnemonic_backwards :: " string \<Rightarrow>((register_value),(csrop),(exception))monad " where
+ " csr_mnemonic_backwards arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''csrrw'')))) then return CSRRW
+ else if (((p00 = (''csrrs'')))) then return CSRRS
+ else if (((p00 = (''csrrc'')))) then return CSRRC
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_forwards_matches : csrop -> bool\<close>\<close>
+
+fun csr_mnemonic_forwards_matches :: " csrop \<Rightarrow> bool " where
+ " csr_mnemonic_forwards_matches CSRRW = ( True )"
+|" csr_mnemonic_forwards_matches CSRRS = ( True )"
+|" csr_mnemonic_forwards_matches CSRRC = ( True )"
+
+
+\<comment> \<open>\<open>val csr_mnemonic_backwards_matches : string -> bool\<close>\<close>
+
+definition csr_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where
+ " csr_mnemonic_backwards_matches arg1 = (
+ (let p00 = arg1 in
+ if (((p00 = (''csrrw'')))) then True
+ else if (((p00 = (''csrrs'')))) then True
+ else if (((p00 = (''csrrc'')))) then True
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s809_ : string -> maybe string\<close>\<close>
+
+definition s809 :: " string \<Rightarrow>(string)option " where
+ " s809 s8100 = (
+ (let s8110 = s8100 in
+ if ((string_startswith s8110 (''csrrc''))) then
+ (case ((string_drop s8110 ((string_length (''csrrc''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8100 :: " string "
+
+
+\<comment> \<open>\<open>val _s805_ : string -> maybe string\<close>\<close>
+
+definition s805 :: " string \<Rightarrow>(string)option " where
+ " s805 s8060 = (
+ (let s8070 = s8060 in
+ if ((string_startswith s8070 (''csrrs''))) then
+ (case ((string_drop s8070 ((string_length (''csrrs''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8060 :: " string "
+
+
+\<comment> \<open>\<open>val _s801_ : string -> maybe string\<close>\<close>
+
+definition s801 :: " string \<Rightarrow>(string)option " where
+ " s801 s8020 = (
+ (let s8030 = s8020 in
+ if ((string_startswith s8030 (''csrrw''))) then
+ (case ((string_drop s8030 ((string_length (''csrrw''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s8020 :: " string "
+
+
+definition csr_mnemonic_matches_prefix :: " string \<Rightarrow>(csrop*int)option " where
+ " csr_mnemonic_matches_prefix arg1 = (
+ (let s8040 = arg1 in
+ if ((case ((s801 s8040)) of Some (s1) => True | _ => False )) then
+ (case s801 s8040 of
+ (Some (s1)) =>
+ Some (CSRRW, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s805 s8040)) of Some (s1) => True | _ => False )) then
+ (case s805 s8040 of
+ (Some (s1)) =>
+ Some (CSRRS, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s809 s8040)) of Some (s1) => True | _ => False )) then
+ (case s809 s8040 of
+ (Some (s1)) =>
+ Some (CSRRC, ((string_length arg1)) - ((string_length s1)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val encdec_forwards : ast -> M (mword ty32)\<close>\<close>
+
+fun encdec_forwards :: " ast \<Rightarrow>((register_value),((32)Word.word),(exception))monad " where
+ " encdec_forwards (UTYPE ((imm, rd, op1))) = (
+ return ((concat_vec imm
+ ((concat_vec rd ((encdec_uop_forwards op1 :: 7 Word.word)) :: 12 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RISCV_JAL ((v__2, rd))) = (
+ if (((((subrange_vec_dec v__2 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__2 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__2 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__2 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in
+ (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in
+ return ((concat_vec imm_19
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9
+ ((concat_vec imm_8
+ ((concat_vec imm_7_0
+ ((concat_vec rd (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 20 Word.word))
+ :: 21 Word.word))
+ :: 25 Word.word))
+ :: 31 Word.word))
+ :: 32 Word.word))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__2 :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RISCV_JALR ((imm, rs1, rd))) = (
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (BTYPE ((v__4, rs2, rs1, op1))) = (
+ if (((((subrange_vec_dec v__4 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__4 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__4 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__4 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in
+ (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__4 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in
+ (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__4 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec imm7_6
+ ((concat_vec imm7_5_0
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec ((encdec_bop_forwards op1 :: 3 Word.word))
+ ((concat_vec imm5_4_1
+ ((concat_vec imm5_0
+ (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 8 Word.word))
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 31 Word.word))
+ :: 32 Word.word)))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and v__4 :: "(13)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (ITYPE ((imm, rs1, rd, op1))) = (
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((encdec_iop_forwards op1 :: 3 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 26 Word.word))
+ :: 32 Word.word)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_ADD))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLT))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLTU))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_AND))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_OR))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_XOR))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SLL))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SRL))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SUB))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPE ((rs2, rs1, rd, RISCV_SRA))) = (
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (LOAD ((imm, rs1, rd, is_unsigned, size1, False, False))) = (
+ if (((((((word_width_bytes size1)) < (( 8 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))))))) then
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_unsigned :: 1 Word.word))
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+|" encdec_forwards (STORE ((v__6, rs2, rs1, size1, False, False))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__6 (( 11 :: int)::ii) (( 5 :: int)::ii) :: 7 Word.word)) in
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__6 (( 11 :: int)::ii) (( 5 :: int)::ii) :: 7 Word.word)) in
+ (let (imm5 :: 5 bits) = ((subrange_vec_dec v__6 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec imm7
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec imm5
+ (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and v__6 :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (ADDIW ((imm, rs1, rd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec imm
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SLLI))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SRLI))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTW ((shamt, rs1, rd, RISCV_SRAI))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_ADDW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SUBW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SLLW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SRLW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (RTYPEW ((rs2, rs1, rd, RISCV_SRAW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec shamt
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (FENCE ((pred, succ))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 24 Word.word))
+ :: 28 Word.word))
+ :: 32 Word.word)))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards (FENCE_TSO ((pred, succ))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)
+ ((concat_vec pred
+ ((concat_vec succ
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 24 Word.word))
+ :: 28 Word.word))
+ :: 32 Word.word)))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards (FENCEI (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (ECALL (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (MRET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (SRET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (EBREAK (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (WFI (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (SFENCE_VMA ((rs1, rs2))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (AMO ((op1, aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then
+ return ((concat_vec ((encdec_amoop_forwards op1 :: 5 Word.word))
+ ((concat_vec ((bool_bits_forwards aq :: 1 Word.word))
+ ((concat_vec ((bool_bits_forwards rl :: 1 Word.word))
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec ((size_bits_forwards size1 :: 2 Word.word))
+ ((concat_vec rd
+ (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 26 Word.word))
+ :: 27 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for size1 :: " word_width "
+ and op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards (MUL ((rs2, rs1, rd, high, signed1, signed2))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec
+ ((encdec_mul_op_forwards (high, signed1, signed2) :: 3 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (DIV ((rs2, rs1, rd, s))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (REM ((rs2, rs1, rd, s))) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (MULW ((rs2, rs1, rd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards (DIVW ((rs2, rs1, rd, s))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (REMW ((rs2, rs1, rd, s))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)
+ ((concat_vec rs2
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word))
+ ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards (CSR ((csr, rs1, rd, is_imm, op1))) = (
+ return ((concat_vec csr
+ ((concat_vec rs1
+ ((concat_vec ((bool_bits_forwards is_imm :: 1 Word.word))
+ ((concat_vec ((encdec_csrop_forwards op1 :: 2 Word.word))
+ ((concat_vec rd (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 14 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 32 Word.word)))"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" encdec_forwards (URET (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)
+ :: 12 Word.word))
+ :: 15 Word.word))
+ :: 20 Word.word))
+ :: 25 Word.word))
+ :: 32 Word.word)))"
+|" encdec_forwards (ILLEGAL (s)) = ( return s )"
+ for s :: "(32)Word.word "
+|" encdec_forwards _ = ( assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+
+
+\<comment> \<open>\<open>val encdec_backwards : mword ty32 -> M ast\<close>\<close>
+
+definition encdec_backwards :: "(32)Word.word \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " encdec_backwards arg1 = (
+ (let v__7 = arg1 in
+ (let (mappingpatterns_230 :: 7 Word.word) = ((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ and_boolM (return ((encdec_uop_backwards_matches mappingpatterns_230)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_230)) then
+ encdec_uop_backwards mappingpatterns_230 \<bind> (\<lambda> op1 . return True)
+ else return False) \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ (let (imm :: 20 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 20 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in
+ (let (mappingpatterns_230 :: 7 Word.word) = ((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ encdec_uop_backwards mappingpatterns_230 \<bind> (\<lambda> op1 . return (UTYPE (imm, rd, op1)))))))
+ else if (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__7 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in
+ (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__7 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in
+ (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 21 :: int)::ii) :: 4 Word.word)) in
+ return (RISCV_JAL ((concat_vec imm_19
+ ((concat_vec imm_7_0
+ ((concat_vec imm_8
+ ((concat_vec imm_18_13
+ ((concat_vec imm_12_9 (vec_of_bits [B0] :: 1 Word.word)
+ :: 5 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 20 Word.word))
+ :: 21 Word.word),
+ rd)))))))))
+ else if ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ return (RISCV_JALR (imm, rs1, rd))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_240 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_bop_backwards_matches mappingpatterns_240)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_240)) then
+ encdec_bop_backwards mappingpatterns_240 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in
+ (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__7 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in
+ (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in
+ (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__7 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_240 :: 3 Word.word) = ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_bop_backwards mappingpatterns_240 \<bind> (\<lambda> op1 .
+ return (BTYPE ((concat_vec imm7_6
+ ((concat_vec imm5_0
+ ((concat_vec imm7_5_0
+ ((concat_vec imm5_4_1 (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word),
+ rs2,
+ rs1,
+ op1)))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_250 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_iop_backwards_matches mappingpatterns_250)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_250)) then
+ encdec_iop_backwards mappingpatterns_250 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__7 :: bool) .
+ if w__7 then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_250 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_iop_backwards mappingpatterns_250 \<bind> (\<lambda> op1 . return (ITYPE (imm, rs1, rd, op1))))))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SLLI)))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SRLI)))))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIOP (shamt, rs1, rd, RISCV_SRAI)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_ADD)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLT)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLTU)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_AND)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_OR)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_XOR)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SLL)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SRL)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SUB)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPE (rs2, rs1, rd, RISCV_SRA)))))
+ else
+ and_boolM
+ ((let (mappingpatterns_270 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_260 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_270)))
+ (if ((size_bits_backwards_matches mappingpatterns_270)) then
+ size_bits_backwards mappingpatterns_270 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_260)))
+ (if ((bool_bits_backwards_matches mappingpatterns_260)) then
+ bool_bits_backwards mappingpatterns_260 \<bind> (\<lambda> is_unsigned .
+ return (((((((word_width_bytes size1)) < (( 8 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))))))))
+ else return False) \<bind> (\<lambda> (w__9 :: bool) .
+ return w__9))
+ else return False))))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__12 :: bool) .
+ if w__12 then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_270 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_260 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_270 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_260 \<bind> (\<lambda> is_unsigned .
+ return (LOAD (imm, rs1, rd, is_unsigned, size1, False, False))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_280 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_280)))
+ (if ((size_bits_backwards_matches mappingpatterns_280)) then
+ size_bits_backwards mappingpatterns_280 \<bind> (\<lambda> size1 .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__15 ::
+ bool) .
+ if w__15 then
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (imm7 :: 7 bits) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in
+ (let (imm5 :: 5 bits) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_280 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ size_bits_backwards mappingpatterns_280 \<bind> (\<lambda> size1 .
+ return (STORE ((concat_vec imm7 imm5 :: 12 Word.word), rs2, rs1, size1, False, False)))))))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm :: 12 Word.word) = ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ return (ADDIW (imm, rs1, rd))))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SLLI)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SRLI)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTW (shamt, rs1, rd, RISCV_SRAI)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_ADDW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SUBW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SLLW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SRLW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (RTYPEW (rs2, rs1, rd, RISCV_SRAW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SLLIW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SRLIW)))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (SHIFTIWOP (shamt, rs1, rd, RISCV_SRAIW)))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ (let (succ :: 4 Word.word) = ((subrange_vec_dec v__7 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in
+ (let (pred :: 4 Word.word) = ((subrange_vec_dec v__7 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in
+ return (FENCE (pred, succ))))
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ (let (succ :: 4 Word.word) = ((subrange_vec_dec v__7 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in
+ (let (pred :: 4 Word.word) = ((subrange_vec_dec v__7 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in
+ return (FENCE_TSO (pred, succ))))
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,
+ B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 32 Word.word)))) then
+ return (FENCEI () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (ECALL () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (MRET () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (SRET () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (EBREAK () )
+ else if (((v__7 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return (WFI () )
+ else if ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word)))))))
+ then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ return (SFENCE_VMA (rs1, rs2))))
+ else
+ and_boolM
+ ((let (mappingpatterns_310 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_300 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_290 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_310)))
+ (if ((size_bits_backwards_matches mappingpatterns_310)) then
+ size_bits_backwards mappingpatterns_310 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_300)))
+ (if ((bool_bits_backwards_matches mappingpatterns_300)) then
+ bool_bits_backwards mappingpatterns_300 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_290)))
+ (if ((bool_bits_backwards_matches mappingpatterns_290)) then
+ bool_bits_backwards mappingpatterns_290 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__17 :: bool) .
+ return w__17))
+ else return False) \<bind> (\<lambda> (w__19 :: bool) .
+ return w__19))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))))))) \<bind> (\<lambda> (w__22 ::
+ bool) .
+ if w__22 then
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_310 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_300 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_290 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_310 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_300 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_290 \<bind> (\<lambda> aq .
+ return (LOADRES (aq, rl, rs1, size1, rd))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_340 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_330 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_320 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_340)))
+ (if ((size_bits_backwards_matches mappingpatterns_340)) then
+ size_bits_backwards mappingpatterns_340 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_330)))
+ (if ((bool_bits_backwards_matches mappingpatterns_330)) then
+ bool_bits_backwards mappingpatterns_330 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_320)))
+ (if ((bool_bits_backwards_matches mappingpatterns_320)) then
+ bool_bits_backwards mappingpatterns_320 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__24 :: bool) .
+ return w__24))
+ else return False) \<bind> (\<lambda> (w__26 :: bool) .
+ return w__26))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__29 ::
+ bool) .
+ if w__29 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_340 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_330 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_320 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_340 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_330 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_320 \<bind> (\<lambda> aq .
+ return (STORECON (aq, rl, rs2, rs1, size1, rd)))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_380 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_370 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_360 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_380)))
+ (if ((size_bits_backwards_matches mappingpatterns_380)) then
+ size_bits_backwards mappingpatterns_380 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_370)))
+ (if ((bool_bits_backwards_matches mappingpatterns_370)) then
+ bool_bits_backwards mappingpatterns_370 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_360)))
+ (if ((bool_bits_backwards_matches mappingpatterns_360)) then
+ bool_bits_backwards mappingpatterns_360 \<bind> (\<lambda> aq .
+ and_boolM
+ (return ((encdec_amoop_backwards_matches mappingpatterns_350)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_350)) then
+ encdec_amoop_backwards mappingpatterns_350 \<bind> (\<lambda> op1 .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__31 :: bool) .
+ return w__31))
+ else return False) \<bind> (\<lambda> (w__33 :: bool) .
+ return w__33))
+ else return False) \<bind> (\<lambda> (w__35 :: bool) .
+ return w__35))
+ else return False)))))))
+ (return ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__38 ::
+ bool) .
+ if w__38 then
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_380 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_370 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_360 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_350 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ size_bits_backwards mappingpatterns_380 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_370 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_360 \<bind> (\<lambda> aq .
+ encdec_amoop_backwards mappingpatterns_350 \<bind> (\<lambda> op1 .
+ return (AMO (op1, aq, rl, rs2, rs1, size1, rd))))))))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_390 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_mul_op_backwards_matches mappingpatterns_390)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_390)) then
+ encdec_mul_op_backwards mappingpatterns_390 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__41 ::
+ bool) .
+ if w__41 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_390 :: 3 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_mul_op_backwards mappingpatterns_390 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return (MUL (rs2, rs1, rd, high, signed1, signed2))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_400 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_400)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_400)) then
+ bool_not_bits_backwards mappingpatterns_400 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__44 ::
+ bool) .
+ if w__44 then
+ (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_400 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_400 \<bind> (\<lambda> s .
+ return (DIV (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_410 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_410)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_410)) then
+ bool_not_bits_backwards mappingpatterns_410 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__47 ::
+ bool) .
+ if w__47 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_410 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_410 \<bind> (\<lambda> s .
+ return (REM (rs2, rs1, rd, s)))))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))))))
+ then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) = ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ return (MULW (rs2, rs1, rd)))))
+ else
+ and_boolM
+ ((let (mappingpatterns_420 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_420)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_420)) then
+ bool_not_bits_backwards mappingpatterns_420 \<bind> (\<lambda> s .
+ return ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__50 ::
+ bool) .
+ if w__50 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_420 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_420 \<bind> (\<lambda> s .
+ return (DIVW (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_430 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_430)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_430)) then
+ bool_not_bits_backwards mappingpatterns_430 \<bind> (\<lambda> s .
+ return ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__53 ::
+ bool) .
+ if w__53 then
+ (let (rs2 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_430 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_430 \<bind> (\<lambda> s .
+ return (REMW (rs2, rs1, rd, s)))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_450 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_440 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((encdec_csrop_backwards_matches mappingpatterns_450)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_450)) then
+ encdec_csrop_backwards mappingpatterns_450 \<bind> (\<lambda> op1 .
+ and_boolM
+ (return ((bool_bits_backwards_matches mappingpatterns_440)))
+ (if ((bool_bits_backwards_matches mappingpatterns_440)) then
+ bool_bits_backwards mappingpatterns_440 \<bind> (\<lambda> is_imm .
+ return True)
+ else return False) \<bind> (\<lambda> (w__55 :: bool) .
+ return w__55))
+ else return False))))
+ (return (((((subrange_vec_dec v__7 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__58 ::
+ bool) .
+ if w__58 then
+ (let (csr :: 12 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (rs1 :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: 5 Word.word) =
+ ((subrange_vec_dec v__7 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (csr :: 12 Word.word) =
+ ((subrange_vec_dec v__7 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in
+ (let (mappingpatterns_450 :: 2 Word.word) =
+ ((subrange_vec_dec v__7 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_440 :: 1 Word.word) =
+ ((subrange_vec_dec v__7 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ encdec_csrop_backwards mappingpatterns_450 \<bind> (\<lambda> op1 .
+ bool_bits_backwards mappingpatterns_440 \<bind> (\<lambda> is_imm .
+ return (CSR (csr, rs1, rd, is_imm, op1))))))))))
+ else
+ return (if (((v__7 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,
+ B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+ B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ URET ()
+ else ILLEGAL v__7))))))))))))))))))"
+ for arg1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_forwards_matches : ast -> bool\<close>\<close>
+
+fun encdec_forwards_matches :: " ast \<Rightarrow> bool " where
+ " encdec_forwards_matches (UTYPE ((imm, rd, op1))) = ( True )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RISCV_JAL ((v__220, rd))) = (
+ if (((((subrange_vec_dec v__220 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ True
+ else False )"
+ for v__220 :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RISCV_JALR ((imm, rs1, rd))) = ( True )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (BTYPE ((v__222, rs2, rs1, op1))) = (
+ if (((((subrange_vec_dec v__222 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then
+ True
+ else False )"
+ for op1 :: " bop "
+ and v__222 :: "(13)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (ITYPE ((imm, rs1, rd, op1))) = ( True )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SLLI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SRLI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIOP ((shamt, rs1, rd, RISCV_SRAI))) = ( True )"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_ADD))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLT))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLTU))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_AND))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_OR))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_XOR))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SLL))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SRL))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SUB))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPE ((rs2, rs1, rd, RISCV_SRA))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (LOAD ((imm, rs1, rd, is_unsigned, size1, False, False))) = (
+ if (((((((word_width_bytes size1)) < (( 8 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))))))) then
+ True
+ else False )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+|" encdec_forwards_matches (STORE ((v__224, rs2, rs1, size1, False, False))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and v__224 :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (ADDIW ((imm, rs1, rd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SLLI))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SRLI))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTW ((shamt, rs1, rd, RISCV_SRAI))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_ADDW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SUBW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SLLW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SRLW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (RTYPEW ((rs2, rs1, rd, RISCV_SRAW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SLLIW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRLIW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, RISCV_SRAIW))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (FENCE ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards_matches (FENCE_TSO ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" encdec_forwards_matches (FENCEI (_)) = ( True )"
+|" encdec_forwards_matches (ECALL (_)) = ( True )"
+|" encdec_forwards_matches (MRET (_)) = ( True )"
+|" encdec_forwards_matches (SRET (_)) = ( True )"
+|" encdec_forwards_matches (EBREAK (_)) = ( True )"
+|" encdec_forwards_matches (WFI (_)) = ( True )"
+|" encdec_forwards_matches (SFENCE_VMA ((rs1, rs2))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" encdec_forwards_matches (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (AMO ((op1, aq, rl, rs2, rs1, size1, rd))) = (
+ if ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))) then True else False )"
+ for size1 :: " word_width "
+ and op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" encdec_forwards_matches (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( True )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (DIV ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (REM ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (MULW ((rs2, rs1, rd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_forwards_matches (DIVW ((rs2, rs1, rd, s))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (REMW ((rs2, rs1, rd, s))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" encdec_forwards_matches (CSR ((csr, rs1, rd, is_imm, op1))) = ( True )"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" encdec_forwards_matches (URET (_)) = ( True )"
+|" encdec_forwards_matches (ILLEGAL (s)) = ( True )"
+ for s :: "(32)Word.word "
+|" encdec_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_backwards_matches : mword ty32 -> M bool\<close>\<close>
+
+definition encdec_backwards_matches :: "(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " encdec_backwards_matches arg1 = (
+ (let v__225 = arg1 in
+ (let (mappingpatterns_00 :: 7 Word.word) = ((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ and_boolM (return ((encdec_uop_backwards_matches mappingpatterns_00)))
+ (if ((encdec_uop_backwards_matches mappingpatterns_00)) then
+ encdec_uop_backwards mappingpatterns_00 \<bind> (\<lambda> op1 . return True)
+ else return False) \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ (let (mappingpatterns_00 :: 7 Word.word) = ((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in
+ encdec_uop_backwards mappingpatterns_00 \<bind> (\<lambda> op1 . return True))
+ else if (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_10 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_bop_backwards_matches mappingpatterns_10)))
+ (if ((encdec_bop_backwards_matches mappingpatterns_10)) then
+ encdec_bop_backwards mappingpatterns_10 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (let (mappingpatterns_10 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_bop_backwards mappingpatterns_10 \<bind> (\<lambda> op1 . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_20 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_iop_backwards_matches mappingpatterns_20)))
+ (if ((encdec_iop_backwards_matches mappingpatterns_20)) then
+ encdec_iop_backwards mappingpatterns_20 \<bind> (\<lambda> op1 . return True)
+ else return False)))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__7 :: bool) .
+ if w__7 then
+ (let (mappingpatterns_20 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_iop_backwards mappingpatterns_20 \<bind> (\<lambda> op1 . return True))
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((let (shamt :: 6 Word.word) = ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in
+ (((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((((bit_to_bool ((access_vec_dec shamt (( 5 :: int)::ii))))) = False)))))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_40 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_30 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_40)))
+ (if ((size_bits_backwards_matches mappingpatterns_40)) then
+ size_bits_backwards mappingpatterns_40 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_30)))
+ (if ((bool_bits_backwards_matches mappingpatterns_30)) then
+ bool_bits_backwards mappingpatterns_30 \<bind> (\<lambda> is_unsigned .
+ return (((((((word_width_bytes size1)) < (( 8 :: int)::ii))) \<or> (((((\<not> is_unsigned)) \<and> ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))))))))
+ else return False) \<bind> (\<lambda> (w__9 :: bool) .
+ return w__9))
+ else return False))))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__12 :: bool) .
+ if w__12 then
+ (let (mappingpatterns_40 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_30 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_40 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_30 \<bind> (\<lambda> is_unsigned . return True))))
+ else
+ and_boolM
+ ((let (mappingpatterns_50 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_50)))
+ (if ((size_bits_backwards_matches mappingpatterns_50)) then
+ size_bits_backwards mappingpatterns_50 \<bind> (\<lambda> size1 .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__15 ::
+ bool) .
+ if w__15 then
+ (let (mappingpatterns_50 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ size_bits_backwards mappingpatterns_50 \<bind> (\<lambda> size1 . return True))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 20 Word.word))))))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,
+ B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if (((v__225 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,
+ B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ return True
+ else if ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word)))))))
+ then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_80 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_70 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_60 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_80)))
+ (if ((size_bits_backwards_matches mappingpatterns_80)) then
+ size_bits_backwards mappingpatterns_80 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_70)))
+ (if ((bool_bits_backwards_matches mappingpatterns_70)) then
+ bool_bits_backwards mappingpatterns_70 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_60)))
+ (if ((bool_bits_backwards_matches mappingpatterns_60)) then
+ bool_bits_backwards mappingpatterns_60 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__17 :: bool) .
+ return w__17))
+ else return False) \<bind> (\<lambda> (w__19 :: bool) .
+ return w__19))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))))))) \<bind> (\<lambda> (w__22 ::
+ bool) .
+ if w__22 then
+ (let (mappingpatterns_80 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_70 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_60 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_80 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_70 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_60 \<bind> (\<lambda> aq . return True))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_90 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_110 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_100 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_110)))
+ (if ((size_bits_backwards_matches mappingpatterns_110)) then
+ size_bits_backwards mappingpatterns_110 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_100)))
+ (if ((bool_bits_backwards_matches mappingpatterns_100)) then
+ bool_bits_backwards mappingpatterns_100 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_90)))
+ (if ((bool_bits_backwards_matches mappingpatterns_90)) then
+ bool_bits_backwards mappingpatterns_90 \<bind> (\<lambda> aq .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__24 :: bool) .
+ return w__24))
+ else return False) \<bind> (\<lambda> (w__26 :: bool) .
+ return w__26))
+ else return False)))))
+ (return ((((((((regidx_to_regno
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__29 ::
+ bool) .
+ if w__29 then
+ (let (mappingpatterns_90 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_110 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_100 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ size_bits_backwards mappingpatterns_110 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_100 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_90 \<bind> (\<lambda> aq . return True))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_150 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_140 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_130 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ and_boolM (return ((size_bits_backwards_matches mappingpatterns_150)))
+ (if ((size_bits_backwards_matches mappingpatterns_150)) then
+ size_bits_backwards mappingpatterns_150 \<bind> (\<lambda> size1 .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_140)))
+ (if ((bool_bits_backwards_matches mappingpatterns_140)) then
+ bool_bits_backwards mappingpatterns_140 \<bind> (\<lambda> rl .
+ and_boolM (return ((bool_bits_backwards_matches mappingpatterns_130)))
+ (if ((bool_bits_backwards_matches mappingpatterns_130)) then
+ bool_bits_backwards mappingpatterns_130 \<bind> (\<lambda> aq .
+ and_boolM
+ (return ((encdec_amoop_backwards_matches mappingpatterns_120)))
+ (if ((encdec_amoop_backwards_matches mappingpatterns_120)) then
+ encdec_amoop_backwards mappingpatterns_120 \<bind> (\<lambda> op1 .
+ return ((((word_width_bytes size1)) \<le> (( 8 :: int)::ii))))
+ else return False) \<bind> (\<lambda> (w__31 :: bool) .
+ return w__31))
+ else return False) \<bind> (\<lambda> (w__33 :: bool) .
+ return w__33))
+ else return False) \<bind> (\<lambda> (w__35 :: bool) .
+ return w__35))
+ else return False)))))))
+ (return ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__38 ::
+ bool) .
+ if w__38 then
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ (let (mappingpatterns_150 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_140 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_130 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in
+ (let (mappingpatterns_120 :: 5 Word.word) =
+ ((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in
+ size_bits_backwards mappingpatterns_150 \<bind> (\<lambda> size1 .
+ bool_bits_backwards mappingpatterns_140 \<bind> (\<lambda> rl .
+ bool_bits_backwards mappingpatterns_130 \<bind> (\<lambda> aq .
+ encdec_amoop_backwards mappingpatterns_120 \<bind> (\<lambda> op1 . return True)))))))))
+ else
+ and_boolM
+ ((let (mappingpatterns_160 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ and_boolM (return ((encdec_mul_op_backwards_matches mappingpatterns_160)))
+ (if ((encdec_mul_op_backwards_matches mappingpatterns_160)) then
+ encdec_mul_op_backwards mappingpatterns_160 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) \<bind> (\<lambda> (w__41 ::
+ bool) .
+ if w__41 then
+ (let (mappingpatterns_160 :: 3 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in
+ encdec_mul_op_backwards mappingpatterns_160 \<bind> (\<lambda> varstup . (let (high, signed1, signed2) = varstup in
+ return True)))
+ else
+ and_boolM
+ ((let (mappingpatterns_170 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_170)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_170)) then
+ bool_not_bits_backwards mappingpatterns_170 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__44 ::
+ bool) .
+ if w__44 then
+ (let (mappingpatterns_170 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_170 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_180 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM (return ((bool_not_bits_backwards_matches mappingpatterns_180)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_180)) then
+ bool_not_bits_backwards mappingpatterns_180 \<bind> (\<lambda> s . return True)
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__47 ::
+ bool) .
+ if w__47 then
+ (let (mappingpatterns_180 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_180 \<bind> (\<lambda> s . return True))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 12 :: int)::ii)
+ :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))))))
+ then
+ return True
+ else
+ and_boolM
+ ((let (mappingpatterns_190 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_190)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_190)) then
+ bool_not_bits_backwards mappingpatterns_190 \<bind> (\<lambda> s .
+ return ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__50 ::
+ bool) .
+ if w__50 then
+ (let (mappingpatterns_190 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_190 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_200 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((bool_not_bits_backwards_matches mappingpatterns_200)))
+ (if ((bool_not_bits_backwards_matches mappingpatterns_200)) then
+ bool_not_bits_backwards mappingpatterns_200 \<bind> (\<lambda> s .
+ return ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ else return False)))
+ (return ((((((((subrange_vec_dec v__225 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 13 :: int)::ii)
+ :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii)
+ :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))))))) \<bind> (\<lambda> (w__53 ::
+ bool) .
+ if w__53 then
+ (let (mappingpatterns_200 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ bool_not_bits_backwards mappingpatterns_200 \<bind> (\<lambda> s . return True))
+ else
+ and_boolM
+ ((let (mappingpatterns_220 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_210 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ and_boolM
+ (return ((encdec_csrop_backwards_matches mappingpatterns_220)))
+ (if ((encdec_csrop_backwards_matches mappingpatterns_220)) then
+ encdec_csrop_backwards mappingpatterns_220 \<bind> (\<lambda> op1 .
+ and_boolM
+ (return ((bool_bits_backwards_matches mappingpatterns_210)))
+ (if ((bool_bits_backwards_matches mappingpatterns_210)) then
+ bool_bits_backwards mappingpatterns_210 \<bind> (\<lambda> is_imm .
+ return True)
+ else return False) \<bind> (\<lambda> (w__55 :: bool) .
+ return w__55))
+ else return False))))
+ (return (((((subrange_vec_dec v__225 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))) \<bind> (\<lambda> (w__58 ::
+ bool) .
+ if w__58 then
+ (let (mappingpatterns_220 :: 2 Word.word) =
+ ((subrange_vec_dec v__225 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in
+ (let (mappingpatterns_210 :: 1 Word.word) =
+ ((subrange_vec_dec v__225 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in
+ encdec_csrop_backwards mappingpatterns_220 \<bind> (\<lambda> op1 .
+ bool_bits_backwards mappingpatterns_210 \<bind> (\<lambda> is_imm .
+ return True))))
+ else
+ return (if (((v__225 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,
+ B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,
+ B1,B1,B0,B0,B1,B1]
+ :: 32 Word.word)))) then
+ True
+ else True))))))))))))))))))"
+ for arg1 :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_compressed_forwards : ast -> M (mword ty16)\<close>\<close>
+
+fun encdec_compressed_forwards :: " ast \<Rightarrow>((register_value),((16)Word.word),(exception))monad " where
+ " encdec_compressed_forwards (C_NOP (_)) = (
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+|" encdec_compressed_forwards (C_ADDI4SPN ((rd, v__438))) = (
+ if ((let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__438 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__438 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__438 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))))))) then
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__438 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__438 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__438 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__438 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nz54
+ ((concat_vec nz96
+ ((concat_vec nz2
+ ((concat_vec nz3
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 11 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__438 :: "(8)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_LW ((v__439, rs1, rd))) = (
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__439 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__439 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__439 (( 3 :: int)::ii) (( 1 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__439 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))"
+ for v__439 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_LD ((v__440, rs1, rd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__440 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__440 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__440 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rd (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__440 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SW ((v__441, rs1, rs2))) = (
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__441 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__441 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__441 (( 3 :: int)::ii) (( 1 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__441 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui2
+ ((concat_vec ui6
+ ((concat_vec rs2 (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))"
+ for v__441 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SD ((v__442, rs1, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__442 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__442 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__442 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec rs1
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B0,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__442 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ADDI ((v__443, rsd))) = (
+ if ((let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__443 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) then
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__443 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__443 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nzi5
+ ((concat_vec rsd
+ ((concat_vec nzi40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and v__443 :: "(6)Word.word "
+|" encdec_compressed_forwards (C_JAL (v__444)) = (
+ if ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) then
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__444 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__444 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__444 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__444 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__444 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__444 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__444 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__444 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__444 (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word))
+ :: 9 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__444 :: "(11)Word.word "
+|" encdec_compressed_forwards (C_ADDIW ((v__445, rsd))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__445 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__445 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__445 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word)
+ ((concat_vec imm5
+ ((concat_vec rsd
+ ((concat_vec imm40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__445 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LI ((v__446, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__446 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__446 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__446 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec imm5
+ ((concat_vec rd
+ ((concat_vec imm40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__446 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_ADDI16SP (v__447)) = (
+ if ((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__447 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__447 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__447 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__447 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__447 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__447 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__447 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__447 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__447 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec nzi9
+ ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)
+ ((concat_vec nzi4
+ ((concat_vec nzi6
+ ((concat_vec nzi87
+ ((concat_vec nzi5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__447 :: "(6)Word.word "
+|" encdec_compressed_forwards (C_LUI ((v__448, rd))) = (
+ if ((let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__448 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) then
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__448 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__448 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec imm17
+ ((concat_vec rd
+ ((concat_vec imm1612 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__448 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SRLI ((v__449, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__449 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__449 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__449 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__449 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SRAI ((v__450, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__450 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__450 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__450 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__450 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ANDI ((v__451, rsd))) = (
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__451 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__451 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i40 :: 5 bits) = ((subrange_vec_dec v__451 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec i5
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec i40 (vec_of_bits [B0,B1] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))"
+ for v__451 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SUB ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_XOR ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_OR ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_AND ((rsd, rs2))) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SUBW ((rsd, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_ADDW ((rsd, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word)
+ ((concat_vec rsd
+ ((concat_vec (vec_of_bits [B0,B1] :: 2 Word.word)
+ ((concat_vec rs2 (vec_of_bits [B0,B1] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards (C_J (v__452)) = (
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__452 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__452 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__452 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__452 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__452 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__452 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__452 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__452 (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__452 (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word)
+ ((concat_vec i11
+ ((concat_vec i4
+ ((concat_vec i98
+ ((concat_vec i10
+ ((concat_vec i6
+ ((concat_vec i7
+ ((concat_vec i31
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word)
+ :: 3 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word))
+ :: 9 Word.word))
+ :: 11 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))))))))"
+ for v__452 :: "(11)Word.word "
+|" encdec_compressed_forwards (C_BEQZ ((v__453, rs))) = (
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__453 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__453 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__453 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__453 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__453 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__453 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))"
+ for rs :: "(3)Word.word "
+ and v__453 :: "(8)Word.word "
+|" encdec_compressed_forwards (C_BNEZ ((v__454, rs))) = (
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__454 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__454 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__454 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__454 (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__454 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__454 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec i8
+ ((concat_vec i43
+ ((concat_vec rs
+ ((concat_vec i76
+ ((concat_vec i21
+ ((concat_vec i5 (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 7 Word.word))
+ :: 10 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))))))"
+ for v__454 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards (C_SLLI ((v__455, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__455 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word))))))))))))))))
+ then
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__455 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__455 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ ((concat_vec nzui5
+ ((concat_vec rsd
+ ((concat_vec nzui40 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__455 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LWSP ((v__456, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__456 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__456 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__456 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in
+ (let (ui42 :: 3 bits) = ((subrange_vec_dec v__456 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui42
+ ((concat_vec ui76 (vec_of_bits [B1,B0] :: 2 Word.word) :: 4 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__456 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_LDSP ((v__457, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__457 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__457 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__457 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (ui43 :: 2 bits) = ((subrange_vec_dec v__457 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in
+ return ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word)
+ ((concat_vec ui5
+ ((concat_vec rd
+ ((concat_vec ui43
+ ((concat_vec ui86 (vec_of_bits [B1,B0] :: 2 Word.word) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__457 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SWSP ((v__458, rs2))) = (
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__458 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__458 (( 5 :: int)::ii) (( 4 :: int)::ii) :: 2 Word.word)) in
+ (let (ui52 :: 4 bits) = ((subrange_vec_dec v__458 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word)
+ ((concat_vec ui52
+ ((concat_vec ui76
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 9 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))))))"
+ for v__458 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_SDSP ((v__459, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__459 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__459 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__459 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in
+ return ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word)
+ ((concat_vec ui53
+ ((concat_vec ui86
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 10 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for v__459 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_JR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec rs1
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B0] :: 1 Word.word)
+ ((concat_vec rd
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards (C_EBREAK (_)) = (
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)
+ (vec_of_bits [B1,B0] :: 2 Word.word)
+ :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word)))"
+|" encdec_compressed_forwards (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ return ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word)
+ ((concat_vec (vec_of_bits [B1] :: 1 Word.word)
+ ((concat_vec rsd
+ ((concat_vec rs2 (vec_of_bits [B1,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word))
+ :: 13 Word.word))
+ :: 16 Word.word))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards (C_ILLEGAL (s)) = ( return s )"
+ for s :: "(16)Word.word "
+|" encdec_compressed_forwards _ = ( assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+
+
+\<comment> \<open>\<open>val encdec_compressed_backwards : mword ty16 -> ast\<close>\<close>
+
+definition encdec_compressed_backwards :: "(16)Word.word \<Rightarrow> ast " where
+ " encdec_compressed_backwards arg1 = (
+ (let v__460 = arg1 in
+ if (((v__460 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))
+ then
+ C_NOP ()
+ else if (((((let (nz96 :: 4 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ C_ADDI4SPN (rd,
+ (concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_LW ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word), rs1, rd))))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_LD ((concat_vec ui76 ui53 :: 5 Word.word), rs1, rd)))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ (let (ui6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (ui2 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ C_SW ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word), rs1, rs2))))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: 3 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (rs1 :: 3 bits) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ C_SD ((concat_vec ui76 ui53 :: 5 Word.word), rs1, rs2)))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADDI ((concat_vec nzi5 nzi40 :: 6 Word.word), rsd))))
+ else if (((((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__460 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in
+ C_JAL ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 9 Word.word))
+ :: 10 Word.word))
+ :: 11 Word.word))))))))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADDIW ((concat_vec imm5 imm40 :: 6 Word.word), rsd))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_LI ((concat_vec imm5 imm40 :: 6 Word.word), rd))))
+ else if (((((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regidx_to_regno ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ C_ADDI16SP ((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)))))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_LUI ((concat_vec imm17 imm1612 :: 6 Word.word), rd))))
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SRLI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SRAI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ANDI ((concat_vec i5 i40 :: 6 Word.word), rsd))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_SUB (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_XOR (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_OR (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_AND (rsd, rs2)))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_SUBW (rsd, rs2)))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ (let (rsd :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: cregidx) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ C_ADDW (rsd, rs2)))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (i98 :: 2 bits) = ((subrange_vec_dec v__460 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in
+ (let (i7 :: 1 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (let (i6 :: 1 bits) = ((subrange_vec_dec v__460 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i4 :: 1 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in
+ (let (i31 :: 3 bits) = ((subrange_vec_dec v__460 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in
+ (let (i11 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i10 :: 1 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in
+ C_J ((concat_vec i11
+ ((concat_vec i10
+ ((concat_vec i98
+ ((concat_vec i7
+ ((concat_vec i6
+ ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word))
+ :: 6 Word.word))
+ :: 7 Word.word))
+ :: 9 Word.word))
+ :: 10 Word.word))
+ :: 11 Word.word))))))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (rs :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ C_BEQZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word),
+ rs)))))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ (let (rs :: cregidx) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (i8 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (i76 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (i5 :: 1 bits) = ((subrange_vec_dec v__460 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (i43 :: 2 bits) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in
+ (let (i21 :: 2 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ C_BNEZ ((concat_vec i8
+ ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word))
+ :: 7 Word.word))
+ :: 8 Word.word),
+ rs)))))))
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word)))))))))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SLLI ((concat_vec nzui5 nzui40 :: 6 Word.word), rsd))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (ui42 :: 3 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_LWSP ((concat_vec ui76 ((concat_vec ui5 ui42 :: 4 Word.word)) :: 6 Word.word), rd)))))
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__460 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in
+ (let (ui5 :: 1 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (ui43 :: 2 bits) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_LDSP ((concat_vec ui86 ((concat_vec ui5 ui43 :: 3 Word.word)) :: 6 Word.word), rd)))))
+ else if ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ (let (ui76 :: 2 bits) = ((subrange_vec_dec v__460 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in
+ (let (ui52 :: 4 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SWSP ((concat_vec ui76 ui52 :: 6 Word.word), rs2))))
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (ui86 :: 3 bits) = ((subrange_vec_dec v__460 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in
+ (let (ui53 :: 3 bits) = ((subrange_vec_dec v__460 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_SDSP ((concat_vec ui86 ui53 :: 6 Word.word), rs2))))
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ (let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_JR rs1)
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ (let (rs1 :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_JALR rs1)
+ else if (((((let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ C_MV (rd, rs2)))
+ else if (((v__460 = (vec_of_bits [B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 16 Word.word)))) then
+ C_EBREAK ()
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__460 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__460 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ (let (rsd :: regidx) = ((subrange_vec_dec v__460 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__460 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ C_ADD (rsd, rs2)))
+ else C_ILLEGAL v__460))"
+ for arg1 :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val encdec_compressed_forwards_matches : ast -> bool\<close>\<close>
+
+fun encdec_compressed_forwards_matches :: " ast \<Rightarrow> bool " where
+ " encdec_compressed_forwards_matches (C_NOP (_)) = ( True )"
+|" encdec_compressed_forwards_matches (C_ADDI4SPN ((rd, v__596))) = (
+ if ((let (nz96 :: 4 bits) = ((subrange_vec_dec v__596 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz96 :: 4 bits) = ((subrange_vec_dec v__596 (( 7 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__596 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__596 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__596 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))))))) then
+ True
+ else False )"
+ for v__596 :: "(8)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_LW ((v__597, rs1, rd))) = ( True )"
+ for v__597 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_LD ((v__598, rs1, rd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__598 :: "(5)Word.word "
+ and rs1 :: "(3)Word.word "
+ and rd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SW ((v__599, rs1, rs2))) = ( True )"
+ for v__599 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SD ((v__600, rs1, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__600 :: "(5)Word.word "
+ and rs2 :: "(3)Word.word "
+ and rs1 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDI ((v__601, rsd))) = (
+ if ((let (nzi5 :: 1 bits) = ((subrange_vec_dec v__601 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__601 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__601 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) then
+ True
+ else False )"
+ for v__601 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JAL (v__602)) = ( if ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) then True else False )"
+ for v__602 :: "(11)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDIW ((v__603, rsd))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for v__603 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LI ((v__604, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for v__604 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDI16SP (v__605)) = (
+ if ((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__605 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__605 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__605 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__605 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__605 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__605 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then
+ True
+ else False )"
+ for v__605 :: "(6)Word.word "
+|" encdec_compressed_forwards_matches (C_LUI ((v__606, rd))) = (
+ if ((let (imm17 :: 1 bits) = ((subrange_vec_dec v__606 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__606 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__606 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) then
+ True
+ else False )"
+ for v__606 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SRLI ((v__607, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__607 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__607 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__607 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ True
+ else False )"
+ for v__607 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SRAI ((v__608, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__608 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__608 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__608 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))) then
+ True
+ else False )"
+ for v__608 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ANDI ((v__609, rsd))) = ( True )"
+ for v__609 :: "(6)Word.word "
+ and rsd :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SUB ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_XOR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_OR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_AND ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SUBW ((rsd, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_ADDW ((rsd, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_J (v__610)) = ( True )"
+ for v__610 :: "(11)Word.word "
+|" encdec_compressed_forwards_matches (C_BEQZ ((v__611, rs))) = ( True )"
+ for v__611 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_BNEZ ((v__612, rs))) = ( True )"
+ for v__612 :: "(8)Word.word "
+ and rs :: "(3)Word.word "
+|" encdec_compressed_forwards_matches (C_SLLI ((v__613, rsd))) = (
+ if ((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__613 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__613 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__613 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word))))))))))))))))
+ then
+ True
+ else False )"
+ for v__613 :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LWSP ((v__614, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for v__614 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_LDSP ((v__615, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for v__615 :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SWSP ((v__616, rs2))) = ( True )"
+ for v__616 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_SDSP ((v__617, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for v__617 :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JR (rs1)) = ( if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_EBREAK (_)) = ( True )"
+|" encdec_compressed_forwards_matches (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" encdec_compressed_forwards_matches (C_ILLEGAL (s)) = ( True )"
+ for s :: "(16)Word.word "
+|" encdec_compressed_forwards_matches _ = ( False )"
+
+
+\<comment> \<open>\<open>val encdec_compressed_backwards_matches : mword ty16 -> bool\<close>\<close>
+
+definition encdec_compressed_backwards_matches :: "(16)Word.word \<Rightarrow> bool " where
+ " encdec_compressed_backwards_matches arg1 = (
+ (let v__618 = arg1 in
+ if (((v__618 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))
+ then
+ True
+ else if (((((let (nz96 :: 4 bits) = ((subrange_vec_dec v__618 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in
+ (let (nz54 :: 2 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in
+ (let (nz3 :: 1 bits) = ((subrange_vec_dec v__618 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nz2 :: 1 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nz96
+ ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word))
+ :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzi5 nzi40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (nzi9 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__618 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in
+ (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__618 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__618 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in
+ (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in
+ (((concat_vec nzi9
+ ((concat_vec nzi87
+ ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word))
+ :: 5 Word.word))
+ :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regidx_to_regno ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regidx_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (imm17 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((((concat_vec imm17 imm1612 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__618 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in
+ (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((concat_vec nzui5 nzui40 :: 6 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<or> (((nzui5 = ((bool_to_bits False :: 1 Word.word)))))))))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ True
+ else if (((((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ True
+ else if (((((let (rs1 :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word)))))))))) then
+ True
+ else if (((((let (rs2 :: regidx) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ (let (rd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else if (((v__618 = (vec_of_bits [B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 16 Word.word)))) then
+ True
+ else if (((((let (rsd :: regidx) = ((subrange_vec_dec v__618 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in
+ (let (rs2 :: regidx) = ((subrange_vec_dec v__618 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))))) \<and> ((((((((subrange_vec_dec v__618 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__618 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))))))) then
+ True
+ else True))"
+ for arg1 :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val execute_WFI : unit -> M Retired\<close>\<close>
+
+definition execute_WFI :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_WFI _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ Machine => platform_wfi () \<then> return RETIRE_SUCCESS
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) .
+ if (((((get_Mstatus_TW w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then
+ handle_illegal () \<then> return RETIRE_FAIL
+ else platform_wfi () \<then> return RETIRE_SUCCESS)
+ | User => handle_illegal () \<then> return RETIRE_FAIL
+ )))"
+
+
+\<comment> \<open>\<open>val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M Retired\<close>\<close>
+
+definition execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_UTYPE imm rd op1 = (
+ (let (off :: xlenbits) =
+ ((EXTS (( 64 :: int)::ii)
+ ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)
+ :: 32 Word.word))
+ :: 64 Word.word)) in
+ (case op1 of
+ RISCV_LUI => return off
+ | RISCV_AUIPC =>
+ (get_arch_pc () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return ((add_vec w__0 off :: 64 Word.word)))
+ ) \<bind> (\<lambda> (ret :: xlenbits) .
+ wX ((regidx_to_regno rd)) ret \<then> return RETIRE_SUCCESS)))"
+ for imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " uop "
+
+
+\<comment> \<open>\<open>val execute_URET : unit -> M Retired\<close>\<close>
+
+definition execute_URET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_URET _ = (
+ haveUsrMode () \<bind> (\<lambda> (w__0 :: bool) .
+ (if ((\<not> w__0)) then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (exception_handler w__1 (CTL_URET () ) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ set_next_pc w__3)))) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_STORECON :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_STORECON aq rl rs2 rs1 width rd = (
+ speculate_conditional_success () \<bind> (\<lambda> (w__0 :: bool) .
+ if (((w__0 = False))) then
+ wX ((regidx_to_regno rd)) ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) \<then>
+ return RETIRE_SUCCESS
+ else
+ haveAtomics () \<bind> (\<lambda> (w__1 :: bool) .
+ if w__1 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 64 :: int)::ii) :: 64 Word.word)) Write width \<bind> (\<lambda> (w__2 :: unit
+ Ext_DataAddr_Check) .
+ (case w__2 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (let (aligned :: bool) =
+ ((case width of
+ BYTE => True
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))
+ )) in
+ if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return RETIRE_FAIL
+ else if (((((match_reservation vaddr)) = False))) then
+ wX ((regidx_to_regno rd)) ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ else
+ (translateAddr vaddr Write :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__3 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__3 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__10) => mem_write_ea addr (( 4 :: int)::ii) aq rl True
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then mem_write_ea addr (( 8 :: int)::ii) aq rl True
+ else internal_error (''STORECON expected word or double'')
+ | _ => internal_error (''STORECON expected word or double'')
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__9) =>
+ mem_write_value addr (( 4 :: int)::ii)
+ ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq rl True
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True
+ else internal_error (''STORECON expected word or double'')
+ | _ => internal_error (''STORECON expected word or double'')
+ ) \<bind> (\<lambda> (res :: bool MemoryOpResult) .
+ (case res of
+ MemValue (True) =>
+ wX ((regidx_to_regno rd))
+ ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ | MemValue (False) =>
+ wX ((regidx_to_regno rd))
+ ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) \<then>
+ ((let (_ :: unit) = (cancel_reservation () ) in
+ return RETIRE_SUCCESS))
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ )))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL)))"
+ for aq :: " bool "
+ and rl :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_STORE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_STORE imm rs2 rs1 width aq rl = (
+ (let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ ext_data_get_addr rs1 offset Write width \<bind> (\<lambda> (w__0 :: unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then
+ handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Write :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__1 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case width of
+ BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False
+ | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False
+ | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False
+ | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (case (width, (( 64 :: int):: ii)) of
+ (BYTE, g__3) =>
+ mem_write_value addr (( 1 :: int):: ii)
+ ((subrange_vec_dec rs2_val (( 7 :: int):: ii) (( 0 :: int):: ii) :: 8 Word.word))
+ aq rl False
+ | (HALF, g__4) =>
+ mem_write_value addr (( 2 :: int):: ii)
+ ((subrange_vec_dec rs2_val (( 15 :: int):: ii) (( 0 :: int):: ii) :: 16 Word.word))
+ aq rl False
+ | (WORD, g__5) =>
+ mem_write_value addr (( 4 :: int):: ii)
+ ((subrange_vec_dec rs2_val (( 31 :: int):: ii) (( 0 :: int):: ii) :: 32 Word.word))
+ aq rl False
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int):: ii)))) then
+ mem_write_value addr (( 8 :: int):: ii) rs2_val aq rl False else
+ assert_exp False
+ (''Pattern match failure at model/riscv_insts_base.sail 394:47 - 399:15'')
+ \<then> exit0 ()
+ ) \<bind> (\<lambda> (res :: bool MemoryOpResult) .
+ (case res of
+ MemValue (True) => return RETIRE_SUCCESS
+ | MemValue (False) => internal_error (''store got false from mem_write_value'')
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ ))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and aq :: " bool "
+ and rl :: " bool "
+
+
+\<comment> \<open>\<open>val execute_SRET : unit -> M Retired\<close>\<close>
+
+definition execute_SRET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SRET _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (case w__0 of
+ User => handle_illegal ()
+ | Supervisor =>
+ or_boolM (haveSupMode () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1))))
+ (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) .
+ return (((((get_Mstatus_TSR w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) \<bind> (\<lambda> (w__3 ::
+ bool) .
+ if w__3 then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__4 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) .
+ (exception_handler w__4 (CTL_SRET () ) w__5 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) .
+ set_next_pc w__6))))
+ | Machine =>
+ haveSupMode () \<bind> (\<lambda> (w__7 :: bool) .
+ if ((\<not> w__7)) then handle_illegal ()
+ else
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__8 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) .
+ (exception_handler w__8 (CTL_SRET () ) w__9 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) .
+ set_next_pc w__10))))
+ ) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M Retired\<close>\<close>
+
+definition execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTW shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt :: 32 Word.word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 32 Word.word)
+ | RISCV_SRAI => (shift_right_arith32 rs1_val shamt :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word)) \<then> return RETIRE_SUCCESS))))"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sop "
+
+
+\<comment> \<open>\<open>val execute_SHIFTIWOP : mword ty5 -> mword ty5 -> mword ty5 -> sopw -> M Retired\<close>\<close>
+
+definition execute_SHIFTIWOP :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sopw \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTIWOP shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_SLLIW =>
+ (shift_bits_left ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ | RISCV_SRLIW =>
+ (shift_bits_right ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ | RISCV_SRAIW =>
+ (shift_right_arith32 ((subrange_vec_dec rs1_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) shamt
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word)) \<then> return RETIRE_SUCCESS)))"
+ for shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sopw "
+
+
+\<comment> \<open>\<open>val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M Retired\<close>\<close>
+
+definition execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SHIFTIOP shamt rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_SLLI => (shift_bits_left rs1_val shamt :: 64 Word.word)
+ | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 64 Word.word)
+ | RISCV_SRAI => (shift_right_arith64 rs1_val shamt :: 64 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS)))"
+ for shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " sop "
+
+
+\<comment> \<open>\<open>val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_SFENCE_VMA rs1 rs2 = (
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then return None
+ else
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ return (Some w__0))) \<bind> (\<lambda> (addr :: xlenbits option) .
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then return None
+ else
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ return (Some w__1))) \<bind> (\<lambda> (asid :: xlenbits option) .
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) .
+ (case w__2 of
+ User => handle_illegal () \<then> return RETIRE_FAIL
+ | Supervisor =>
+ read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) .
+ read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) .
+ (let p__7 =
+ (architecture ((get_mstatus_SXL w__3 :: 2 Word.word)), (get_Mstatus_TVM w__4 :: 1 Word.word)) in
+ (case p__7 of
+ (Some (g__6), v_0) =>
+ if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then
+ handle_illegal () \<then> return RETIRE_FAIL
+ else if (((v_0 = ((bool_to_bits False :: 1 Word.word))))) then
+ flush_TLB asid addr \<then> return RETIRE_SUCCESS
+ else
+ (case (Some g__6, v_0) of
+ (_, _) => internal_error (''unimplemented sfence architecture'')
+ )
+ | (_, _) => internal_error (''unimplemented sfence architecture'')
+ ))))
+ | Machine => flush_TLB asid addr \<then> return RETIRE_SUCCESS
+ )))))"
+ for rs1 :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M Retired\<close>\<close>
+
+definition execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RTYPEW rs2 rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (result :: 32 bits) =
+ ((case op1 of
+ RISCV_ADDW => (add_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SUBW => (sub_vec rs1_val rs2_val :: 32 Word.word)
+ | RISCV_SLLW =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRLW =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ | RISCV_SRAW =>
+ (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word))
+ :: 32 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word)) \<then> return RETIRE_SUCCESS))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " ropw "
+
+
+\<comment> \<open>\<open>val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M Retired\<close>\<close>
+
+definition execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RTYPE rs2 rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_ADD => (add_vec rs1_val rs2_val :: 64 Word.word)
+ | RISCV_SLT =>
+ (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word)
+ | RISCV_SLTU =>
+ (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word)
+ | RISCV_AND => (and_vec rs1_val rs2_val :: 64 Word.word)
+ | RISCV_OR => (or_vec rs1_val rs2_val :: 64 Word.word)
+ | RISCV_XOR => (xor_vec rs1_val rs2_val :: 64 Word.word)
+ | RISCV_SLL =>
+ (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word))
+ :: 64 Word.word)
+ | RISCV_SRL =>
+ (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word))
+ :: 64 Word.word)
+ | RISCV_SUB => (sub_vec rs1_val rs2_val :: 64 Word.word)
+ | RISCV_SRA =>
+ (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word))
+ :: 64 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " rop "
+
+
+\<comment> \<open>\<open>val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RISCV_JALR imm rs1 rd = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in
+ (case ((ext_control_check_addr t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (addr) =>
+ (let target = ((update_vec_dec addr (( 0 :: int)::ii) B0 :: 64 Word.word)) in
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (get_next_pc () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ (wX ((regidx_to_regno rd)) w__3 \<then> set_next_pc target) \<then> return RETIRE_SUCCESS)))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_RISCV_JAL :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_RISCV_JAL imm rd = (
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (target) =>
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (get_next_pc () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ (wX ((regidx_to_regno rd)) w__3 \<then> set_next_pc target) \<then> return RETIRE_SUCCESS))
+ ))))"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_REMW rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 64 Word.word)) \<then>
+ return RETIRE_SUCCESS)))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_REM :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_REM rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+ wX ((regidx_to_regno rd)) ((to_bits (( 64 :: int)::ii) r :: 64 Word.word)) \<then> return RETIRE_SUCCESS)))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MULW rs2 rs1 rd = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (Word.sint rs1_val) in
+ (let (rs2_int :: ii) = (Word.sint rs2_val) in
+ (let result32 =
+ ((subrange_vec_dec ((to_bits (( 64 :: int)::ii) ((rs1_int * rs2_int)) :: 64 Word.word)) (( 31 :: int)::ii)
+ (( 0 :: int)::ii)
+ :: 32 Word.word)) in
+ (let (result :: xlenbits) = ((EXTS (( 64 :: int)::ii) result32 :: 64 Word.word)) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MUL rs2 rs1 rd high signed1 signed2 = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if signed1 then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if signed2 then Word.sint rs2_val else Word.uint rs2_val) in
+ (let result_wide =
+ ((to_bits (((( 2 :: int)::ii) * (( 64 :: int)::ii))) ((rs1_int * rs2_int)) :: 128 Word.word)) in
+ (let result =
+ (if high then
+ (subrange_vec_dec result_wide (((((( 2 :: int)::ii) * (( 64 :: int)::ii))) - (( 1 :: int)::ii)))
+ (( 64 :: int)::ii)
+ :: 64 Word.word)
+ else (subrange_vec_dec result_wide (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: 64 Word.word)) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and high :: " bool "
+ and signed1 :: " bool "
+ and signed2 :: " bool "
+
+
+\<comment> \<open>\<open>val execute_MRET : unit -> M Retired\<close>\<close>
+
+definition execute_MRET :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_MRET _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))
+ then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (exception_handler w__1 (CTL_MRET () ) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ set_next_pc w__3)))
+ else handle_illegal () ) \<then>
+ return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_LOADRES :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_LOADRES aq rl rs1 width rd = (
+ haveAtomics () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 64 :: int)::ii) :: 64 Word.word)) Read width \<bind> (\<lambda> (w__1 :: unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (let (aligned :: bool) =
+ ((case width of
+ BYTE => True
+ | HALF =>
+ (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word))
+ | WORD =>
+ (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))
+ | DOUBLE =>
+ (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))
+ )) in
+ if ((\<not> aligned)) then handle_mem_exception vaddr E_Load_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Read :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__2 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__8) =>
+ (mem_read Read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 32 Word.word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__3 False)
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then
+ (mem_read Read addr (( 8 :: int)::ii) aq rl True :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 64 Word.word)
+ MemoryOpResult) .
+ process_loadres rd vaddr w__5 False)
+ else internal_error (''LOADRES expected WORD or DOUBLE'')
+ | _ => internal_error (''LOADRES expected WORD or DOUBLE'')
+ )
+ )))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for aq :: " bool "
+ and rl :: " bool "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M Retired\<close>\<close>
+
+definition execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_LOAD imm rs1 rd is_unsigned width aq rl = (
+ (let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ ext_data_get_addr rs1 offset Read width \<bind> (\<lambda> (w__0 :: unit Ext_DataAddr_Check) .
+ (case w__0 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ if ((check_misaligned vaddr width)) then
+ handle_mem_exception vaddr E_Load_Addr_Align \<then> return RETIRE_FAIL
+ else
+ (translateAddr vaddr Read :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__1 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__1 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 64 :: int):: ii)) of
+ (BYTE, g__0) =>
+ (mem_read Read addr (( 1 :: int):: ii) aq rl False :: ( ( 8 Word.word) MemoryOpResult) M)
+ \<bind>
+ (\<lambda> (w__2 :: ( 8 Word.word) MemoryOpResult) .
+ process_load rd vaddr w__2 is_unsigned)
+ | (HALF, g__1) =>
+ (mem_read Read addr (( 2 :: int):: ii) aq rl False :: ( ( 16 Word.word) MemoryOpResult) M)
+ \<bind>
+ (\<lambda> (w__4 :: ( 16 Word.word) MemoryOpResult) .
+ process_load rd vaddr w__4 is_unsigned)
+ | (WORD, g__2) =>
+ (mem_read Read addr (( 4 :: int):: ii) aq rl False :: ( ( 32 Word.word) MemoryOpResult) M)
+ \<bind>
+ (\<lambda> (w__6 :: ( 32 Word.word) MemoryOpResult) .
+ process_load rd vaddr w__6 is_unsigned)
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int):: ii)))) then
+ (mem_read Read addr (( 8 :: int):: ii) aq rl False :: ( ( 64 Word.word) MemoryOpResult) M)
+ \<bind>
+ (\<lambda> (w__8 :: ( 64 Word.word) MemoryOpResult) .
+ process_load rd vaddr w__8 is_unsigned) else
+ assert_exp False
+ (''Pattern match failure at model/riscv_insts_base.sail 329:10 - 338:11'')
+ \<then> exit0 ()
+ )
+ ))
+ ))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and width :: " word_width "
+ and aq :: " bool "
+ and rl :: " bool "
+
+
+\<comment> \<open>\<open>val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M Retired\<close>\<close>
+
+definition execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ITYPE imm rs1 rd op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (let (immext :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ (let (result :: xlenbits) =
+ ((case op1 of
+ RISCV_ADDI => (add_vec rs1_val immext :: 64 Word.word)
+ | RISCV_SLTI =>
+ (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) :: 1 Word.word)) :: 64 Word.word)
+ | RISCV_SLTIU =>
+ (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) :: 1 Word.word)) :: 64 Word.word)
+ | RISCV_ANDI => (and_vec rs1_val immext :: 64 Word.word)
+ | RISCV_ORI => (or_vec rs1_val immext :: 64 Word.word)
+ | RISCV_XORI => (xor_vec rs1_val immext :: 64 Word.word)
+ )) in
+ wX ((regidx_to_regno rd)) result \<then> return RETIRE_SUCCESS))))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and op1 :: " iop "
+
+
+\<comment> \<open>\<open>val execute_ILLEGAL : mword ty32 -> M Retired\<close>\<close>
+
+definition execute_ILLEGAL :: "(32)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ILLEGAL s = ( handle_illegal () \<then> return RETIRE_FAIL )"
+ for s :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val execute_FENCE_TSO : mword ty4 -> mword ty4 -> M Retired\<close>\<close>
+
+definition execute_FENCE_TSO :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_FENCE_TSO pred succ = (
+ (case (pred, succ) of
+ (v__794, v__795) =>
+ if ((((((((subrange_vec_dec v__794 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__795 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_tso
+ else
+ return (if ((((((((subrange_vec_dec v__794 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__795 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ ()
+ else
+ (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in
+ () ))
+ ) \<then>
+ return RETIRE_SUCCESS )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val execute_FENCEI : unit -> Retired\<close>\<close>
+
+definition execute_FENCEI :: " unit \<Rightarrow> Retired " where
+ " execute_FENCEI _ = ( RETIRE_SUCCESS )"
+
+
+\<comment> \<open>\<open>val execute_FENCE : mword ty4 -> mword ty4 -> M Retired\<close>\<close>
+
+definition execute_FENCE :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_FENCE pred succ = (
+ (case (pred, succ) of
+ (v__754, v__755) =>
+ if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_rw
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_rw_r
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_r_w
+ else if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ barrier Barrier_RISCV_w_r
+ else
+ return (if ((((((((subrange_vec_dec v__754 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__755 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ ()
+ else
+ (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in
+ () ))
+ ) \<then>
+ return RETIRE_SUCCESS )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+
+
+\<comment> \<open>\<open>val execute_ECALL : unit -> M Retired\<close>\<close>
+
+definition execute_ECALL :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ECALL _ = (
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) .
+ (let (t :: sync_exception) =
+ ((| sync_exception_trap =
+ ((case w__0 of
+ User => E_U_EnvCall
+ | Supervisor => E_S_EnvCall
+ | Machine => E_M_EnvCall
+ )),
+ sync_exception_excinfo = None,
+ sync_exception_ext_exception = None |)) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (exception_handler w__1 (CTL_TRAP t) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) .
+ set_next_pc w__3 \<then> return RETIRE_FAIL))))))"
+
+
+\<comment> \<open>\<open>val execute_EBREAK : unit -> M Retired\<close>\<close>
+
+definition execute_EBREAK :: " unit \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_EBREAK _ = (
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ handle_mem_exception w__0 E_Breakpoint \<then> return RETIRE_FAIL))"
+
+
+\<comment> \<open>\<open>val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_DIVW rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let rs1_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let rs2_val = ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in
+ (let (q' :: ii) =
+ (if (((s \<and> ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then
+ (( 0 :: int)::ii) - ((pow (( 2 :: int)::ii) (( 31 :: int)::ii)))
+ else q) in
+ wX ((regidx_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 64 Word.word)) \<then>
+ return RETIRE_SUCCESS))))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M Retired\<close>\<close>
+
+definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_DIV rs2 rs1 rd s = (
+ haveMulDiv () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in
+ (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in
+ (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in
+ (let (q' :: ii) = (if (((s \<and> ((q > xlen_max_signed))))) then xlen_min_signed else q) in
+ wX ((regidx_to_regno rd)) ((to_bits (( 64 :: int)::ii) q' :: 64 Word.word)) \<then> return RETIRE_SUCCESS))))))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+
+
+\<comment> \<open>\<open>val execute_C_NOP : unit -> Retired\<close>\<close>
+
+definition execute_C_NOP :: " unit \<Rightarrow> Retired " where
+ " execute_C_NOP _ = ( RETIRE_SUCCESS )"
+
+
+\<comment> \<open>\<open>val execute_C_ILLEGAL : mword ty16 -> M Retired\<close>\<close>
+
+definition execute_C_ILLEGAL :: "(16)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_C_ILLEGAL s = ( handle_illegal () \<then> return RETIRE_FAIL )"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M Retired\<close>\<close>
+
+definition execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_CSR csr rs1 rd is_imm op1 = (
+ (if is_imm then return ((EXTZ (( 64 :: int)::ii) rs1 :: 64 Word.word))
+ else (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (rs1_val :: xlenbits) .
+ (let (isWrite :: bool) =
+ ((case op1 of
+ CSRRW => True
+ | _ => if is_imm then (((Word.uint rs1_val)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii))
+ )) in
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) .
+ check_CSR csr w__1 isWrite \<bind> (\<lambda> (w__2 :: bool) .
+ if ((\<not> w__2)) then handle_illegal () \<then> return RETIRE_FAIL
+ else
+ (readCSR csr :: ( 64 Word.word) M) \<bind> (\<lambda> csr_val .
+ ((if isWrite then
+ (let (new_val :: xlenbits) =
+ ((case op1 of
+ CSRRW => rs1_val
+ | CSRRS => (or_vec csr_val rs1_val :: 64 Word.word)
+ | CSRRC => (and_vec csr_val ((not_vec rs1_val :: 64 Word.word)) :: 64 Word.word)
+ )) in
+ writeCSR csr new_val)
+ else return () ) \<then>
+ wX ((regidx_to_regno rd)) csr_val) \<then> return RETIRE_SUCCESS))))))"
+ for csr :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and is_imm :: " bool "
+ and op1 :: " csrop "
+
+
+\<comment> \<open>\<open>val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M Retired\<close>\<close>
+
+definition execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_BTYPE imm rs2 rs1 op1 = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val .
+ (let (taken :: bool) =
+ ((case op1 of
+ RISCV_BEQ => (rs1_val = rs2_val)
+ | RISCV_BNE => (rs1_val \<noteq> rs2_val)
+ | RISCV_BLT => zopz0zI_s rs1_val rs2_val
+ | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val
+ | RISCV_BLTU => zopz0zI_u rs1_val rs2_val
+ | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val
+ )) in
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let (t :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in
+ if taken then
+ (case ((ext_control_check_pc t)) of
+ Ext_ControlAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_control_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_ControlAddr_OK (target) =>
+ and_boolM (return ((bit_to_bool ((access_vec_dec target (( 1 :: int)::ii))))))
+ (haveRVC () \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: bool) .
+ if w__2 then handle_mem_exception target E_Fetch_Addr_Align \<then> return RETIRE_FAIL
+ else set_next_pc target \<then> return RETIRE_SUCCESS)
+ )
+ else return RETIRE_SUCCESS))))))"
+ for imm :: "(13)Word.word "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and op1 :: " bop "
+
+
+\<comment> \<open>\<open>val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_AMO op1 aq rl rs2 rs1 width rd = (
+ haveAtomics () \<bind> (\<lambda> (w__0 :: bool) .
+ if w__0 then
+ ext_data_get_addr rs1 ((zeros_implicit (( 64 :: int)::ii) :: 64 Word.word)) ReadWrite width \<bind> (\<lambda> (w__1 :: unit
+ Ext_DataAddr_Check) .
+ (case w__1 of
+ Ext_DataAddr_Error (e) =>
+ (let (_ :: unit) = (ext_handle_data_check_error e) in
+ return RETIRE_FAIL)
+ | Ext_DataAddr_OK (vaddr) =>
+ (translateAddr vaddr ReadWrite :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__2 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__2 of
+ TR_Failure (e) => handle_mem_exception vaddr e \<then> return RETIRE_FAIL
+ | TR_Address (addr) =>
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__13) => mem_write_ea addr (( 4 :: int)::ii) (((aq \<and> rl))) rl True
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then mem_write_ea addr (( 8 :: int)::ii) (((aq \<and> rl))) rl True
+ else internal_error (''AMO expected WORD or DOUBLE'')
+ | _ => internal_error (''AMO expected WORD or DOUBLE'')
+ ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) .
+ (rX ((regidx_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (rs2_val :: xlenbits) .
+ (case eares of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (_) =>
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__12) =>
+ (mem_read ReadWrite addr (( 4 :: int)::ii) aq (((aq \<and> rl))) True
+ :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__8 :: ( 32 Word.word) MemoryOpResult) .
+ return ((extend_value False w__8 :: ( 64 Word.word) MemoryOpResult)))
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then
+ (mem_read ReadWrite addr (( 8 :: int)::ii) aq (((aq \<and> rl))) True
+ :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__9 :: ( 64 Word.word) MemoryOpResult) .
+ return ((extend_value False w__9 :: ( 64 Word.word) MemoryOpResult)))
+ else
+ (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 64 Word.word)MemoryOpResult) M)
+ | _ =>
+ (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 64 Word.word)MemoryOpResult) M)
+ ) \<bind> (\<lambda> (rval :: xlenbits MemoryOpResult) .
+ (case rval of
+ MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ | MemValue (loaded) =>
+ (let (result :: xlenbits) =
+ ((case op1 of
+ AMOSWAP => rs2_val
+ | AMOADD => (add_vec rs2_val loaded :: 64 Word.word)
+ | AMOXOR => (xor_vec rs2_val loaded :: 64 Word.word)
+ | AMOAND => (and_vec rs2_val loaded :: 64 Word.word)
+ | AMOOR => (or_vec rs2_val loaded :: 64 Word.word)
+ | AMOMIN =>
+ (to_bits (( 64 :: int)::ii) ((min ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word)
+ | AMOMAX =>
+ (to_bits (( 64 :: int)::ii) ((max ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word)
+ | AMOMINU =>
+ (to_bits (( 64 :: int)::ii) ((min ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word)
+ | AMOMAXU =>
+ (to_bits (( 64 :: int)::ii) ((max ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word)
+ )) in
+ (case (width, (( 64 :: int)::ii)) of
+ (WORD, g__11) =>
+ mem_write_value addr (( 4 :: int)::ii)
+ ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) (((aq \<and> rl))) rl
+ True
+ | (DOUBLE, p00) =>
+ if (((p00 = (( 64 :: int)::ii)))) then
+ mem_write_value addr (( 8 :: int)::ii) result (((aq \<and> rl))) rl True
+ else internal_error (''AMO expected WORD or DOUBLE'')
+ | _ => internal_error (''AMO expected WORD or DOUBLE'')
+ ) \<bind> (\<lambda> (wval :: bool MemoryOpResult) .
+ (case wval of
+ MemValue (True) => wX ((regidx_to_regno rd)) loaded \<then> return RETIRE_SUCCESS
+ | MemValue (False) => internal_error (''AMO got false from mem_write_value'')
+ | MemException (e) => handle_mem_exception addr e \<then> return RETIRE_FAIL
+ )))
+ ))
+ )))
+ ))
+ ))
+ else handle_illegal () \<then> return RETIRE_FAIL))"
+ for op1 :: " amoop "
+ and aq :: " bool "
+ and rl :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and width :: " word_width "
+ and rd :: "(5)Word.word "
+
+
+\<comment> \<open>\<open>val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M Retired\<close>\<close>
+
+definition execute_ADDIW :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute_ADDIW imm rs1 rd = (
+ (rX ((regidx_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let (result :: xlenbits) = ((add_vec ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) w__0 :: 64 Word.word)) in
+ wX ((regidx_to_regno rd))
+ ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then>
+ return RETIRE_SUCCESS)))"
+ for imm :: "(12)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+
+
+function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value),(Retired),(exception))monad " where
+ " execute (C_ADDI4SPN ((rdc, nzimm))) = (
+ (let (imm :: 12 bits) =
+ ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word)
+ ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 10 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ execute (ITYPE (imm, sp, rd, RISCV_ADDI)))))"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_LW ((uimm, rsc, rdc))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ (let rs = ((creg2reg_idx rsc :: 5 Word.word)) in
+ execute (LOAD (imm, rs, rd, False, WORD, False, False))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_LD ((uimm, rsc, rdc))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ (let rd = ((creg2reg_idx rdc :: 5 Word.word)) in
+ (let rs = ((creg2reg_idx rsc :: 5 Word.word)) in
+ execute (LOAD (imm, rs, rd, False, DOUBLE, False, False))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" execute (C_SW ((uimm, rsc1, rsc2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word))
+ :: 12 Word.word)) in
+ (let rs1 = ((creg2reg_idx rsc1 :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rsc2 :: 5 Word.word)) in
+ execute (STORE (imm, rs2, rs1, WORD, False, False))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" execute (C_SD ((uimm, rsc1, rsc2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ (let rs1 = ((creg2reg_idx rsc1 :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rsc2 :: 5 Word.word)) in
+ execute (STORE (imm, rs2, rs1, DOUBLE, False, False))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" execute (C_ADDI ((nzi, rsd))) = (
+ (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) nzi :: 12 Word.word)) in
+ execute (ITYPE (imm, rsd, rsd, RISCV_ADDI))))"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" execute (C_JAL (imm)) = (
+ execute
+ (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word))
+ :: 21 Word.word),
+ ra)))"
+ for imm :: "(11)Word.word "
+|" execute (C_ADDIW ((imm, rsd))) = ( execute (ADDIW ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word), rsd, rsd)))"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" execute (C_LI ((imm, rd))) = (
+ (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word)) in
+ execute (ITYPE (imm, zreg, rd, RISCV_ADDI))))"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_ADDI16SP (imm)) = (
+ (let (imm :: 12 bits) =
+ ((EXTS (( 12 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 10 Word.word))
+ :: 12 Word.word)) in
+ execute (ITYPE (imm, sp, sp, RISCV_ADDI))))"
+ for imm :: "(6)Word.word "
+|" execute (C_LUI ((imm, rd))) = (
+ (let (res :: 20 bits) = ((EXTS (( 20 :: int)::ii) imm :: 20 Word.word)) in
+ execute (UTYPE (res, rd, RISCV_LUI))))"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_SRLI ((shamt, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRLI))))"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_SRAI ((shamt, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SRAI))))"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_ANDI ((imm, rsd))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ execute (ITYPE ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word), rsd, rsd, RISCV_ANDI))))"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" execute (C_SUB ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_SUB)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_XOR ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_XOR)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_OR ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_OR)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_AND ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPE (rs2, rsd, rsd, RISCV_AND)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_SUBW ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_SUBW)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_ADDW ((rsd, rs2))) = (
+ (let rsd = ((creg2reg_idx rsd :: 5 Word.word)) in
+ (let rs2 = ((creg2reg_idx rs2 :: 5 Word.word)) in
+ execute (RTYPEW (rs2, rsd, rsd, RISCV_ADDW)))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" execute (C_J (imm)) = (
+ execute
+ (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word))
+ :: 21 Word.word),
+ zreg)))"
+ for imm :: "(11)Word.word "
+|" execute (C_BEQZ ((imm, rs))) = (
+ execute
+ (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word))
+ :: 13 Word.word),
+ zreg,
+ (creg2reg_idx rs :: 5 Word.word),
+ RISCV_BEQ)))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" execute (C_BNEZ ((imm, rs))) = (
+ execute
+ (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word))
+ :: 13 Word.word),
+ zreg,
+ (creg2reg_idx rs :: 5 Word.word),
+ RISCV_BNE)))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" execute (C_SLLI ((shamt, rsd))) = ( execute (SHIFTIOP (shamt, rsd, rsd, RISCV_SLLI)))"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" execute (C_LWSP ((uimm, rd))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ execute (LOAD (imm, sp, rd, False, WORD, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_LDSP ((uimm, rd))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word))
+ :: 12 Word.word)) in
+ execute (LOAD (imm, sp, rd, False, DOUBLE, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_SWSP ((uimm, rs2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word))
+ :: 12 Word.word)) in
+ execute (STORE (imm, rs2, sp, WORD, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (C_SDSP ((uimm, rs2))) = (
+ (let (imm :: 12 bits) =
+ ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word))
+ :: 12 Word.word)) in
+ execute (STORE (imm, rs2, sp, DOUBLE, False, False))))"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (C_JR (rs1)) = (
+ execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word), rs1, zreg)))"
+ for rs1 :: "(5)Word.word "
+|" execute (C_JALR (rs1)) = (
+ execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word), rs1, ra)))"
+ for rs1 :: "(5)Word.word "
+|" execute (C_MV ((rd, rs2))) = ( execute (RTYPE (rs2, zreg, rd, RISCV_ADD)))"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (C_EBREAK (_)) = ( execute (EBREAK () ))"
+|" execute (C_ADD ((rsd, rs2))) = ( execute (RTYPE (rs2, rsd, rsd, RISCV_ADD)))"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" execute (UTYPE ((imm, rd, op1))) = ( execute_UTYPE imm rd op1 )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RISCV_JAL ((imm, rd))) = ( execute_RISCV_JAL imm rd )"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (BTYPE ((imm, rs2, rs1, op1))) = ( execute_BTYPE imm rs2 rs1 op1 )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" execute (ITYPE ((imm, rs1, rd, op1))) = ( execute_ITYPE imm rs1 rd op1 )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTIOP ((shamt, rs1, rd, op1))) = ( execute_SHIFTIOP shamt rs1 rd op1 )"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RTYPE ((rs2, rs1, rd, op1))) = ( execute_RTYPE rs2 rs1 rd op1 )"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (LOAD ((imm, rs1, rd, is_unsigned, width, aq, rl))) = (
+ execute_LOAD imm rs1 rd is_unsigned width aq rl )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (STORE ((imm, rs2, rs1, width, aq, rl))) = ( execute_STORE imm rs2 rs1 width aq rl )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (ADDIW ((imm, rs1, rd))) = ( execute_ADDIW imm rs1 rd )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTW ((shamt, rs1, rd, op1))) = ( execute_SHIFTW shamt rs1 rd op1 )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (RTYPEW ((rs2, rs1, rd, op1))) = ( execute_RTYPEW rs2 rs1 rd op1 )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (SHIFTIWOP ((shamt, rs1, rd, op1))) = ( execute_SHIFTIWOP shamt rs1 rd op1 )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (FENCE ((pred, succ))) = ( execute_FENCE pred succ )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" execute (FENCE_TSO ((pred, succ))) = ( execute_FENCE_TSO pred succ )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" execute (FENCEI (arg0)) = ( return ((execute_FENCEI arg0)))"
+ for arg0 :: " unit "
+|" execute (ECALL (arg0)) = ( execute_ECALL arg0 )"
+ for arg0 :: " unit "
+|" execute (MRET (arg0)) = ( execute_MRET arg0 )"
+ for arg0 :: " unit "
+|" execute (SRET (arg0)) = ( execute_SRET arg0 )"
+ for arg0 :: " unit "
+|" execute (EBREAK (arg0)) = ( execute_EBREAK arg0 )"
+ for arg0 :: " unit "
+|" execute (WFI (arg0)) = ( execute_WFI arg0 )"
+ for arg0 :: " unit "
+|" execute (SFENCE_VMA ((rs1, rs2))) = ( execute_SFENCE_VMA rs1 rs2 )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" execute (LOADRES ((aq, rl, rs1, width, rd))) = ( execute_LOADRES aq rl rs1 width rd )"
+ for rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (STORECON ((aq, rl, rs2, rs1, width, rd))) = ( execute_STORECON aq rl rs2 rs1 width rd )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = ( execute_AMO op1 aq rl rs2 rs1 width rd )"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" execute (C_NOP (arg0)) = ( return ((execute_C_NOP arg0)))"
+ for arg0 :: " unit "
+|" execute (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( execute_MUL rs2 rs1 rd high signed1 signed2 )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (DIV ((rs2, rs1, rd, s))) = ( execute_DIV rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (REM ((rs2, rs1, rd, s))) = ( execute_REM rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (MULW ((rs2, rs1, rd))) = ( execute_MULW rs2 rs1 rd )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (DIVW ((rs2, rs1, rd, s))) = ( execute_DIVW rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (REMW ((rs2, rs1, rd, s))) = ( execute_REMW rs2 rs1 rd s )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" execute (CSR ((csr, rs1, rd, is_imm, op1))) = ( execute_CSR csr rs1 rd is_imm op1 )"
+ for op1 :: " csrop "
+ and is_imm :: " bool "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" execute (URET (arg0)) = ( execute_URET arg0 )"
+ for arg0 :: " unit "
+|" execute (RISCV_JALR ((imm, rs1, rd))) = ( execute_RISCV_JALR imm rs1 rd )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" execute (ILLEGAL (s)) = ( execute_ILLEGAL s )"
+ for s :: "(32)Word.word "
+|" execute (C_ILLEGAL (s)) = ( execute_C_ILLEGAL s )"
+ for s :: "(16)Word.word "
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val assembly_forwards : ast -> M string\<close>\<close>
+
+fun assembly_forwards :: " ast \<Rightarrow>((register_value),(string),(exception))monad " where
+ " assembly_forwards (UTYPE ((imm, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__0 :: string) .
+ return ((string_append ((utype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__0
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RISCV_JAL ((imm, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__1 :: string) .
+ return ((string_append (''jal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__1
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RISCV_JALR ((imm, rs1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__2 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__3 :: string) .
+ return ((string_append (''jalr'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__2
+ ((string_append ((sep_forwards () ))
+ ((string_append w__3
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (BTYPE ((imm, rs2, rs1, op1))) = (
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__4 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__5 :: string) .
+ return ((string_append ((btype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__4
+ ((string_append ((sep_forwards () ))
+ ((string_append w__5
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" assembly_forwards (ITYPE ((imm, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__6 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__7 :: string) .
+ return ((string_append ((itype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__6
+ ((string_append ((sep_forwards () ))
+ ((string_append w__7
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))))))))"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTIOP ((shamt, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__8 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__9 :: string) .
+ return ((string_append ((shiftiop_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__8
+ ((string_append ((sep_forwards () ))
+ ((string_append w__9
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))))))))"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RTYPE ((rs2, rs1, rd, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__10 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__11 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__12 :: string) .
+ return ((string_append ((rtype_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__10
+ ((string_append ((sep_forwards () ))
+ ((string_append w__11
+ ((string_append ((sep_forwards () )) ((string_append w__12 ('''')))))))))))))))))))"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__13 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__14 :: string) .
+ return ((string_append (''l'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_u_forwards is_unsigned))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__13
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm))
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append (''('')
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append w__14
+ ((string_append
+ ((opt_spc_forwards () ))
+ ((string_append ('')'') (''''))))))))))))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (STORE ((imm, rs2, rs1, size1, aq, rl))) = (
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__15 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__16 :: string) .
+ return ((string_append (''s'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__15
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm))
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append (''('')
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append w__16
+ ((string_append ((opt_spc_forwards () ))
+ ((string_append ('')'') (''''))))))))))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (ADDIW ((imm, rs1, rd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__17 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__18 :: string) .
+ return ((string_append (''addiw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__17
+ ((string_append ((sep_forwards () ))
+ ((string_append w__18
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTW ((shamt, rs1, rd, op1))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__21 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__22 :: string) .
+ return ((string_append ((shiftw_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__21
+ ((string_append ((sep_forwards () ))
+ ((string_append w__22
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (RTYPEW ((rs2, rs1, rd, op1))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__25 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__26 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__27 :: string) .
+ return ((string_append ((rtypew_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__25
+ ((string_append ((sep_forwards () ))
+ ((string_append w__26
+ ((string_append ((sep_forwards () )) ((string_append w__27 (''''))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (SHIFTIWOP ((shamt, rs1, rd, op1))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__30 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__31 :: string) .
+ return ((string_append ((shiftiwop_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__30
+ ((string_append ((sep_forwards () ))
+ ((string_append w__31
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (FENCE ((pred, succ))) = (
+ fence_bits_forwards pred \<bind> (\<lambda> (w__34 :: string) .
+ fence_bits_forwards succ \<bind> (\<lambda> (w__35 :: string) .
+ return ((string_append (''fence'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__34
+ ((string_append ((sep_forwards () )) ((string_append w__35 (''''))))))))))))))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards (FENCE_TSO ((pred, succ))) = (
+ fence_bits_forwards pred \<bind> (\<lambda> (w__36 :: string) .
+ fence_bits_forwards succ \<bind> (\<lambda> (w__37 :: string) .
+ return ((string_append (''fence.tso'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__36
+ ((string_append ((sep_forwards () )) ((string_append w__37 (''''))))))))))))))"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards (FENCEI (_)) = ( return (''fence.i''))"
+|" assembly_forwards (ECALL (_)) = ( return (''ecall''))"
+|" assembly_forwards (MRET (_)) = ( return (''mret''))"
+|" assembly_forwards (SRET (_)) = ( return (''sret''))"
+|" assembly_forwards (EBREAK (_)) = ( return (''ebreak''))"
+|" assembly_forwards (WFI (_)) = ( return (''wfi''))"
+|" assembly_forwards (SFENCE_VMA ((rs1, rs2))) = (
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__38 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__39 :: string) .
+ return ((string_append (''sfence.vma'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__38
+ ((string_append ((sep_forwards () )) ((string_append w__39 (''''))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" assembly_forwards (LOADRES ((aq, rl, rs1, size1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__40 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__41 :: string) .
+ return ((string_append (''lr.'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__40
+ ((string_append ((sep_forwards () )) ((string_append w__41 (''''))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (STORECON ((aq, rl, rs2, rs1, size1, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__42 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__43 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__44 :: string) .
+ return ((string_append (''sc.'')
+ ((string_append ((size_mnemonic_forwards size1))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__42
+ ((string_append ((sep_forwards () ))
+ ((string_append w__43
+ ((string_append ((sep_forwards () ))
+ ((string_append w__44 ('''')))))))))))))))))))))))))"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__45 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__46 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__47 :: string) .
+ return ((string_append ((amo_mnemonic_forwards op1))
+ ((string_append (''.'')
+ ((string_append ((size_mnemonic_forwards width))
+ ((string_append ((maybe_aq_forwards aq))
+ ((string_append ((maybe_rl_forwards rl))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__45
+ ((string_append ((sep_forwards () ))
+ ((string_append w__46
+ ((string_append ((sep_forwards () ))
+ ((string_append w__47 ('''')))))))))))))))))))))))))))"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" assembly_forwards (C_NOP (_)) = ( return (''c.nop''))"
+|" assembly_forwards (C_ADDI4SPN ((rdc, nzimm))) = (
+ if (((nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then
+ creg_name_forwards rdc \<bind> (\<lambda> (w__48 :: string) .
+ return ((string_append (''c.addi4spn'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__48
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 10 Word.word)))) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_LW ((uimm, rsc, rdc))) = (
+ creg_name_forwards rdc \<bind> (\<lambda> (w__51 :: string) .
+ creg_name_forwards rsc \<bind> (\<lambda> (w__52 :: string) .
+ return ((string_append (''c.lw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__51
+ ((string_append ((sep_forwards () ))
+ ((string_append w__52
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 7 Word.word)))) (''''))))))))))))))))))"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_LD ((uimm, rsc, rdc))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rdc \<bind> (\<lambda> (w__53 :: string) .
+ creg_name_forwards rsc \<bind> (\<lambda> (w__54 :: string) .
+ return ((string_append (''c.ld'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__53
+ ((string_append ((sep_forwards () ))
+ ((string_append w__54
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm
+ (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ :: 8 Word.word)))) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards (C_SW ((uimm, rsc1, rsc2))) = (
+ creg_name_forwards rsc1 \<bind> (\<lambda> (w__57 :: string) .
+ creg_name_forwards rsc2 \<bind> (\<lambda> (w__58 :: string) .
+ return ((string_append (''c.sw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__57
+ ((string_append ((sep_forwards () ))
+ ((string_append w__58
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word)
+ :: 7 Word.word)))) (''''))))))))))))))))))"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards (C_SD ((uimm, rsc1, rsc2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsc1 \<bind> (\<lambda> (w__59 :: string) .
+ creg_name_forwards rsc2 \<bind> (\<lambda> (w__60 :: string) .
+ return ((string_append (''c.sd'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__59
+ ((string_append ((sep_forwards () ))
+ ((string_append w__60
+ ((string_append ((sep_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec uimm
+ (vec_of_bits [B0,B0,B0] :: 3 Word.word)
+ :: 8 Word.word)))) ('''')))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards (C_ADDI ((nzi, rsd))) = (
+ if ((((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__63 :: string) .
+ return ((string_append (''c.addi'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__63
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits nzi)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" assembly_forwards (C_JAL (imm)) = (
+ if ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) then
+ return ((string_append (''c.jal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append
+ ((decimal_string_of_bits
+ ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)))) ('''')))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards (C_ADDIW ((imm, rsd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__68 :: string) .
+ return ((string_append (''c.addiw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__68
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards (C_LI ((imm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__71 :: string) .
+ return ((string_append (''c.li'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__71
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_ADDI16SP (imm)) = (
+ if (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ return ((string_append (''c.addi16sp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+|" assembly_forwards (C_LUI ((imm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__76 :: string) .
+ return ((string_append (''c.lui'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__76
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SRLI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__79 :: string) .
+ return ((string_append (''c.srli'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__79
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_SRAI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__82 :: string) .
+ return ((string_append (''c.srai'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__82
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_ANDI ((imm, rsd))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__85 :: string) .
+ return ((string_append (''c.andi'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__85
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards (C_SUB ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__86 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__87 :: string) .
+ return ((string_append (''c.sub'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__86
+ ((string_append ((sep_forwards () )) ((string_append w__87 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_XOR ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__88 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__89 :: string) .
+ return ((string_append (''c.xor'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__88
+ ((string_append ((sep_forwards () )) ((string_append w__89 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_OR ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__90 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__91 :: string) .
+ return ((string_append (''c.or'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__90
+ ((string_append ((sep_forwards () )) ((string_append w__91 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_AND ((rsd, rs2))) = (
+ creg_name_forwards rsd \<bind> (\<lambda> (w__92 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__93 :: string) .
+ return ((string_append (''c.and'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__92
+ ((string_append ((sep_forwards () )) ((string_append w__93 (''''))))))))))))))"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_SUBW ((rsd, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__94 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__95 :: string) .
+ return ((string_append (''c.subw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__94
+ ((string_append ((sep_forwards () )) ((string_append w__95 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_ADDW ((rsd, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ creg_name_forwards rsd \<bind> (\<lambda> (w__98 :: string) .
+ creg_name_forwards rs2 \<bind> (\<lambda> (w__99 :: string) .
+ return ((string_append (''c.addw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__98
+ ((string_append ((sep_forwards () )) ((string_append w__99 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards (C_J (imm)) = (
+ return ((string_append (''c.j'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) (''''))))))))"
+ for imm :: "(11)Word.word "
+|" assembly_forwards (C_BEQZ ((imm, rs))) = (
+ creg_name_forwards rs \<bind> (\<lambda> (w__102 :: string) .
+ return ((string_append (''c.beqz'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__102
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards (C_BNEZ ((imm, rs))) = (
+ creg_name_forwards rs \<bind> (\<lambda> (w__103 :: string) .
+ return ((string_append (''c.bnez'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__103
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits imm)) ('''')))))))))))))"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards (C_SLLI ((shamt, rsd))) = (
+ if ((((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__104 :: string) .
+ return ((string_append (''c.slli'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__104
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits shamt)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards (C_LWSP ((uimm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__107 :: string) .
+ return ((string_append (''c.lwsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__107
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_LDSP ((uimm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ reg_name_forwards rd \<bind> (\<lambda> (w__110 :: string) .
+ return ((string_append (''c.ldsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__110
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SWSP ((uimm, rd))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__113 :: string) .
+ return ((string_append (''c.swsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__113
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) ('''')))))))))))))"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_SDSP ((uimm, rs2))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__114 :: string) .
+ return ((string_append (''c.sdsp'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__114
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits uimm)) (''''))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards (C_JR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__117 :: string) .
+ return ((string_append (''c.jr'')
+ ((string_append ((spc_forwards () )) ((string_append w__117 (''''))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__120 :: string) .
+ return ((string_append (''c.jalr'')
+ ((string_append ((spc_forwards () )) ((string_append w__120 (''''))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__123 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__124 :: string) .
+ return ((string_append (''c.mv'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__123
+ ((string_append ((sep_forwards () )) ((string_append w__124 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (C_EBREAK (_)) = ( return (''c.ebreak''))"
+|" assembly_forwards (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ reg_name_forwards rsd \<bind> (\<lambda> (w__127 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__128 :: string) .
+ return ((string_append (''c.add'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__127
+ ((string_append ((sep_forwards () )) ((string_append w__128 ('''')))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards (MUL ((rs2, rs1, rd, high, signed1, signed2))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__131 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__132 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__133 :: string) .
+ return ((string_append ((mul_mnemonic_forwards (high, signed1, signed2)))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__131
+ ((string_append ((sep_forwards () ))
+ ((string_append w__132
+ ((string_append ((sep_forwards () )) ((string_append w__133 ('''')))))))))))))))))))"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (DIV ((rs2, rs1, rd, s))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__134 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__135 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__136 :: string) .
+ return ((string_append (''div'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__134
+ ((string_append ((sep_forwards () ))
+ ((string_append w__135
+ ((string_append ((sep_forwards () )) ((string_append w__136 ('''')))))))))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (REM ((rs2, rs1, rd, s))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__137 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__138 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__139 :: string) .
+ return ((string_append (''rem'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__137
+ ((string_append ((sep_forwards () ))
+ ((string_append w__138
+ ((string_append ((sep_forwards () )) ((string_append w__139 ('''')))))))))))))))))))))"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (MULW ((rs2, rs1, rd))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__140 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__141 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__142 :: string) .
+ return ((string_append (''mulw'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__140
+ ((string_append ((sep_forwards () ))
+ ((string_append w__141
+ ((string_append ((sep_forwards () )) ((string_append w__142 (''''))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards (DIVW ((rs2, rs1, rd, s))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__145 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__146 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__147 :: string) .
+ return ((string_append (''div'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append (''w'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__145
+ ((string_append ((sep_forwards () ))
+ ((string_append w__146
+ ((string_append ((sep_forwards () ))
+ ((string_append w__147 (''''))))))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (REMW ((rs2, rs1, rd, s))) = (
+ if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then
+ reg_name_forwards rd \<bind> (\<lambda> (w__150 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__151 :: string) .
+ reg_name_forwards rs2 \<bind> (\<lambda> (w__152 :: string) .
+ return ((string_append (''rem'')
+ ((string_append ((maybe_not_u_forwards s))
+ ((string_append (''w'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__150
+ ((string_append ((sep_forwards () ))
+ ((string_append w__151
+ ((string_append ((sep_forwards () ))
+ ((string_append w__152 (''''))))))))))))))))))))))
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards (CSR ((csr, rs1, rd, True, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__155 :: string) .
+ csr_name_map_forwards csr \<bind> (\<lambda> (w__156 :: string) .
+ return ((string_append ((csr_mnemonic_forwards op1))
+ ((string_append (''i'')
+ ((string_append ((spc_forwards () ))
+ ((string_append w__155
+ ((string_append ((sep_forwards () ))
+ ((string_append ((decimal_string_of_bits rs1))
+ ((string_append ((sep_forwards () )) ((string_append w__156 (''''))))))))))))))))))))"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards (CSR ((csr, rs1, rd, False, op1))) = (
+ reg_name_forwards rd \<bind> (\<lambda> (w__157 :: string) .
+ reg_name_forwards rs1 \<bind> (\<lambda> (w__158 :: string) .
+ csr_name_map_forwards csr \<bind> (\<lambda> (w__159 :: string) .
+ return ((string_append ((csr_mnemonic_forwards op1))
+ ((string_append ((spc_forwards () ))
+ ((string_append w__157
+ ((string_append ((sep_forwards () ))
+ ((string_append w__158
+ ((string_append ((sep_forwards () )) ((string_append w__159 ('''')))))))))))))))))))"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards (URET (_)) = ( return (''uret''))"
+|" assembly_forwards (ILLEGAL (s)) = (
+ return ((string_append (''illegal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) (''''))))))))"
+ for s :: "(32)Word.word "
+|" assembly_forwards (C_ILLEGAL (s)) = (
+ return ((string_append (''c.illegal'')
+ ((string_append ((spc_forwards () ))
+ ((string_append ((decimal_string_of_bits s)) (''''))))))))"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val assembly_backwards : string -> M ast\<close>\<close>
+
+\<comment> \<open>\<open>val _s1677_ : string -> maybe (mword ty16)\<close>\<close>
+
+definition s1677 :: " string \<Rightarrow>((16)Word.word)option " where
+ " s1677 s16780 = (
+ (let s16790 = s16780 in
+ if ((string_startswith s16790 (''c.illegal''))) then
+ (case ((string_drop s16790 ((string_length (''c.illegal''))))) of
+ s16800 =>
+ (case ((spc_matches_prefix0 s16800)) of
+ Some ((_, s16810)) =>
+ (case ((string_drop s16800 s16810)) of
+ s16820 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16820 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s16830)) =>
+ (let p00 = (string_drop s16820 s16830) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16780 :: " string "
+
+
+\<comment> \<open>\<open>val _s1669_ : string -> maybe (mword ty32)\<close>\<close>
+
+definition s1669 :: " string \<Rightarrow>((32)Word.word)option " where
+ " s1669 s16700 = (
+ (let s16710 = s16700 in
+ if ((string_startswith s16710 (''illegal''))) then
+ (case ((string_drop s16710 ((string_length (''illegal''))))) of
+ s16720 =>
+ (case ((spc_matches_prefix0 s16720)) of
+ Some ((_, s16730)) =>
+ (case ((string_drop s16720 s16730)) of
+ s16740 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16740 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s16750)) =>
+ (let p00 = (string_drop s16740 s16750) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16700 :: " string "
+
+
+\<comment> \<open>\<open>val _s1652_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1652 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1652 s16540 = (
+ (case ((csr_mnemonic_matches_prefix s16540)) of
+ Some ((op1, s16550)) =>
+ (case ((string_drop s16540 s16550)) of
+ s16560 =>
+ (case ((spc_matches_prefix0 s16560)) of
+ Some ((_, s16570)) =>
+ (case ((string_drop s16560 s16570)) of
+ s16580 =>
+ (case ((reg_name_matches_prefix s16580 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16590)) =>
+ (case ((string_drop s16580 s16590)) of
+ s16600 =>
+ (case ((sep_matches_prefix s16600)) of
+ Some ((_, s16610)) =>
+ (case ((string_drop s16600 s16610)) of
+ s16620 =>
+ (case ((reg_name_matches_prefix s16620 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16630)) =>
+ (case ((string_drop s16620 s16630)) of
+ s16640 =>
+ (case ((sep_matches_prefix s16640)) of
+ Some ((_, s16650)) =>
+ (case ((string_drop s16640 s16650)) of
+ s16660 =>
+ (case ((csr_name_map_matches_prefix s16660
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s16670)) =>
+ (let p00 = (string_drop s16660 s16670) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s16540 :: " string "
+
+
+\<comment> \<open>\<open>val _s1634_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1634 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1634 s16360 = (
+ (case ((csr_mnemonic_matches_prefix s16360)) of
+ Some ((op1, s16370)) =>
+ (let s16380 = (string_drop s16360 s16370) in
+ if ((string_startswith s16380 (''i''))) then
+ (case ((string_drop s16380 ((string_length (''i''))))) of
+ s16390 =>
+ (case ((spc_matches_prefix0 s16390)) of
+ Some ((_, s16400)) =>
+ (case ((string_drop s16390 s16400)) of
+ s16410 =>
+ (case ((reg_name_matches_prefix s16410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16420)) =>
+ (case ((string_drop s16410 s16420)) of
+ s16430 =>
+ (case ((sep_matches_prefix s16430)) of
+ Some ((_, s16440)) =>
+ (case ((string_drop s16430 s16440)) of
+ s16450 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16460)) =>
+ (case ((string_drop s16450 s16460)) of
+ s16470 =>
+ (case ((sep_matches_prefix s16470)) of
+ Some ((_, s16480)) =>
+ (case ((string_drop s16470 s16480)) of
+ s16490 =>
+ (case ((csr_name_map_matches_prefix s16490
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s16500)) =>
+ (let p00 = (string_drop s16490 s16500) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s16360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1615_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1615 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1615 s16160 = (
+ (let s16170 = s16160 in
+ if ((string_startswith s16170 (''rem''))) then
+ (case ((string_drop s16170 ((string_length (''rem''))))) of
+ s16180 =>
+ (case ((maybe_not_u_matches_prefix s16180)) of
+ Some ((s, s16190)) =>
+ (let s16200 = (string_drop s16180 s16190) in
+ if ((string_startswith s16200 (''w''))) then
+ (case ((string_drop s16200 ((string_length (''w''))))) of
+ s16210 =>
+ (case ((spc_matches_prefix0 s16210)) of
+ Some ((_, s16220)) =>
+ (case ((string_drop s16210 s16220)) of
+ s16230 =>
+ (case ((reg_name_matches_prefix s16230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16240)) =>
+ (case ((string_drop s16230 s16240)) of
+ s16250 =>
+ (case ((sep_matches_prefix s16250)) of
+ Some ((_, s16260)) =>
+ (case ((string_drop s16250 s16260)) of
+ s16270 =>
+ (case ((reg_name_matches_prefix s16270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16280)) =>
+ (case ((string_drop s16270 s16280)) of
+ s16290 =>
+ (case ((sep_matches_prefix s16290)) of
+ Some ((_, s16300)) =>
+ (case ((string_drop s16290 s16300)) of
+ s16310 =>
+ (case ((reg_name_matches_prefix s16310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s16320)) =>
+ (let p00 = (string_drop s16310 s16320) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s16160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1596_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1596 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1596 s15970 = (
+ (let s15980 = s15970 in
+ if ((string_startswith s15980 (''div''))) then
+ (case ((string_drop s15980 ((string_length (''div''))))) of
+ s15990 =>
+ (case ((maybe_not_u_matches_prefix s15990)) of
+ Some ((s, s16000)) =>
+ (let s16010 = (string_drop s15990 s16000) in
+ if ((string_startswith s16010 (''w''))) then
+ (case ((string_drop s16010 ((string_length (''w''))))) of
+ s16020 =>
+ (case ((spc_matches_prefix0 s16020)) of
+ Some ((_, s16030)) =>
+ (case ((string_drop s16020 s16030)) of
+ s16040 =>
+ (case ((reg_name_matches_prefix s16040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16050)) =>
+ (case ((string_drop s16040 s16050)) of
+ s16060 =>
+ (case ((sep_matches_prefix s16060)) of
+ Some ((_, s16070)) =>
+ (case ((string_drop s16060 s16070)) of
+ s16080 =>
+ (case ((reg_name_matches_prefix s16080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s16090)) =>
+ (case ((string_drop s16080 s16090)) of
+ s16100 =>
+ (case ((sep_matches_prefix s16100)) of
+ Some ((_, s16110)) =>
+ (case ((string_drop s16100 s16110)) of
+ s16120 =>
+ (case ((reg_name_matches_prefix s16120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s16130)) =>
+ (let p00 = (string_drop s16120 s16130) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s15970 :: " string "
+
+
+\<comment> \<open>\<open>val _s1580_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1580 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1580 s15810 = (
+ (let s15820 = s15810 in
+ if ((string_startswith s15820 (''mulw''))) then
+ (case ((string_drop s15820 ((string_length (''mulw''))))) of
+ s15830 =>
+ (case ((spc_matches_prefix0 s15830)) of
+ Some ((_, s15840)) =>
+ (case ((string_drop s15830 s15840)) of
+ s15850 =>
+ (case ((reg_name_matches_prefix s15850 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15860)) =>
+ (case ((string_drop s15850 s15860)) of
+ s15870 =>
+ (case ((sep_matches_prefix s15870)) of
+ Some ((_, s15880)) =>
+ (case ((string_drop s15870 s15880)) of
+ s15890 =>
+ (case ((reg_name_matches_prefix s15890 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15900)) =>
+ (case ((string_drop s15890 s15900)) of
+ s15910 =>
+ (case ((sep_matches_prefix s15910)) of
+ Some ((_, s15920)) =>
+ (case ((string_drop s15910 s15920)) of
+ s15930 =>
+ (case ((reg_name_matches_prefix s15930 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15940)) =>
+ (let p00 = (string_drop s15930 s15940) in
+ if (((p00 = ('''')))) then Some (rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15810 :: " string "
+
+
+\<comment> \<open>\<open>val _s1562_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1562 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1562 s15630 = (
+ (let s15640 = s15630 in
+ if ((string_startswith s15640 (''rem''))) then
+ (case ((string_drop s15640 ((string_length (''rem''))))) of
+ s15650 =>
+ (case ((maybe_not_u_matches_prefix s15650)) of
+ Some ((s, s15660)) =>
+ (case ((string_drop s15650 s15660)) of
+ s15670 =>
+ (case ((spc_matches_prefix0 s15670)) of
+ Some ((_, s15680)) =>
+ (case ((string_drop s15670 s15680)) of
+ s15690 =>
+ (case ((reg_name_matches_prefix s15690 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15700)) =>
+ (case ((string_drop s15690 s15700)) of
+ s15710 =>
+ (case ((sep_matches_prefix s15710)) of
+ Some ((_, s15720)) =>
+ (case ((string_drop s15710 s15720)) of
+ s15730 =>
+ (case ((reg_name_matches_prefix s15730 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15740)) =>
+ (case ((string_drop s15730 s15740)) of
+ s15750 =>
+ (case ((sep_matches_prefix s15750)) of
+ Some ((_, s15760)) =>
+ (case ((string_drop s15750 s15760)) of
+ s15770 =>
+ (case ((reg_name_matches_prefix s15770 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15780)) =>
+ (let p00 = (string_drop s15770 s15780) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15630 :: " string "
+
+
+\<comment> \<open>\<open>val _s1544_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1544 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1544 s15450 = (
+ (let s15460 = s15450 in
+ if ((string_startswith s15460 (''div''))) then
+ (case ((string_drop s15460 ((string_length (''div''))))) of
+ s15470 =>
+ (case ((maybe_not_u_matches_prefix s15470)) of
+ Some ((s, s15480)) =>
+ (case ((string_drop s15470 s15480)) of
+ s15490 =>
+ (case ((spc_matches_prefix0 s15490)) of
+ Some ((_, s15500)) =>
+ (case ((string_drop s15490 s15500)) of
+ s15510 =>
+ (case ((reg_name_matches_prefix s15510 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15520)) =>
+ (case ((string_drop s15510 s15520)) of
+ s15530 =>
+ (case ((sep_matches_prefix s15530)) of
+ Some ((_, s15540)) =>
+ (case ((string_drop s15530 s15540)) of
+ s15550 =>
+ (case ((reg_name_matches_prefix s15550 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15560)) =>
+ (case ((string_drop s15550 s15560)) of
+ s15570 =>
+ (case ((sep_matches_prefix s15570)) of
+ Some ((_, s15580)) =>
+ (case ((string_drop s15570 s15580)) of
+ s15590 =>
+ (case ((reg_name_matches_prefix s15590 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15600)) =>
+ (let p00 = (string_drop s15590 s15600) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15450 :: " string "
+
+
+\<comment> \<open>\<open>val _s1527_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1527 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1527 s15290 = (
+ (case ((mul_mnemonic_matches_prefix s15290)) of
+ Some (((high, signed1, signed2), s15300)) =>
+ (case ((string_drop s15290 s15300)) of
+ s15310 =>
+ (case ((spc_matches_prefix0 s15310)) of
+ Some ((_, s15320)) =>
+ (case ((string_drop s15310 s15320)) of
+ s15330 =>
+ (case ((reg_name_matches_prefix s15330 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15340)) =>
+ (case ((string_drop s15330 s15340)) of
+ s15350 =>
+ (case ((sep_matches_prefix s15350)) of
+ Some ((_, s15360)) =>
+ (case ((string_drop s15350 s15360)) of
+ s15370 =>
+ (case ((reg_name_matches_prefix s15370 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15380)) =>
+ (case ((string_drop s15370 s15380)) of
+ s15390 =>
+ (case ((sep_matches_prefix s15390)) of
+ Some ((_, s15400)) =>
+ (case ((string_drop s15390 s15400)) of
+ s15410 =>
+ (case ((reg_name_matches_prefix s15410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15420)) =>
+ (let p00 = (string_drop s15410 s15420) in
+ if (((p00 = ('''')))) then Some (high, signed1, signed2, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s15290 :: " string "
+
+
+\<comment> \<open>\<open>val _s1515_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1515 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1515 s15160 = (
+ (let s15170 = s15160 in
+ if ((string_startswith s15170 (''c.add''))) then
+ (case ((string_drop s15170 ((string_length (''c.add''))))) of
+ s15180 =>
+ (case ((spc_matches_prefix0 s15180)) of
+ Some ((_, s15190)) =>
+ (case ((string_drop s15180 s15190)) of
+ s15200 =>
+ (case ((reg_name_matches_prefix s15200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s15210)) =>
+ (case ((string_drop s15200 s15210)) of
+ s15220 =>
+ (case ((sep_matches_prefix s15220)) of
+ Some ((_, s15230)) =>
+ (case ((string_drop s15220 s15230)) of
+ s15240 =>
+ (case ((reg_name_matches_prefix s15240 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15250)) =>
+ (let p00 = (string_drop s15240 s15250) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1503_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1503 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1503 s15040 = (
+ (let s15050 = s15040 in
+ if ((string_startswith s15050 (''c.mv''))) then
+ (case ((string_drop s15050 ((string_length (''c.mv''))))) of
+ s15060 =>
+ (case ((spc_matches_prefix0 s15060)) of
+ Some ((_, s15070)) =>
+ (case ((string_drop s15060 s15070)) of
+ s15080 =>
+ (case ((reg_name_matches_prefix s15080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s15090)) =>
+ (case ((string_drop s15080 s15090)) of
+ s15100 =>
+ (case ((sep_matches_prefix s15100)) of
+ Some ((_, s15110)) =>
+ (case ((string_drop s15100 s15110)) of
+ s15120 =>
+ (case ((reg_name_matches_prefix s15120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s15130)) =>
+ (let p00 = (string_drop s15120 s15130) in
+ if (((p00 = ('''')))) then Some (rd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s15040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1495_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s1495 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s1495 s14960 = (
+ (let s14970 = s14960 in
+ if ((string_startswith s14970 (''c.jalr''))) then
+ (case ((string_drop s14970 ((string_length (''c.jalr''))))) of
+ s14980 =>
+ (case ((spc_matches_prefix0 s14980)) of
+ Some ((_, s14990)) =>
+ (case ((string_drop s14980 s14990)) of
+ s15000 =>
+ (case ((reg_name_matches_prefix s15000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s15010)) =>
+ (let p00 = (string_drop s15000 s15010) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14960 :: " string "
+
+
+\<comment> \<open>\<open>val _s1487_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s1487 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s1487 s14880 = (
+ (let s14890 = s14880 in
+ if ((string_startswith s14890 (''c.jr''))) then
+ (case ((string_drop s14890 ((string_length (''c.jr''))))) of
+ s14900 =>
+ (case ((spc_matches_prefix0 s14900)) of
+ Some ((_, s14910)) =>
+ (case ((string_drop s14900 s14910)) of
+ s14920 =>
+ (case ((reg_name_matches_prefix s14920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s14930)) =>
+ (let p00 = (string_drop s14920 s14930) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14880 :: " string "
+
+
+\<comment> \<open>\<open>val _s1475_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1475 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1475 s14760 = (
+ (let s14770 = s14760 in
+ if ((string_startswith s14770 (''c.sdsp''))) then
+ (case ((string_drop s14770 ((string_length (''c.sdsp''))))) of
+ s14780 =>
+ (case ((spc_matches_prefix0 s14780)) of
+ Some ((_, s14790)) =>
+ (case ((string_drop s14780 s14790)) of
+ s14800 =>
+ (case ((reg_name_matches_prefix s14800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s14810)) =>
+ (case ((string_drop s14800 s14810)) of
+ s14820 =>
+ (case ((sep_matches_prefix s14820)) of
+ Some ((_, s14830)) =>
+ (case ((string_drop s14820 s14830)) of
+ s14840 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14840 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14850)) =>
+ (let p00 = (string_drop s14840 s14850) in
+ if (((p00 = ('''')))) then Some (rs2, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1463_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1463 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1463 s14640 = (
+ (let s14650 = s14640 in
+ if ((string_startswith s14650 (''c.swsp''))) then
+ (case ((string_drop s14650 ((string_length (''c.swsp''))))) of
+ s14660 =>
+ (case ((spc_matches_prefix0 s14660)) of
+ Some ((_, s14670)) =>
+ (case ((string_drop s14660 s14670)) of
+ s14680 =>
+ (case ((reg_name_matches_prefix s14680 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14690)) =>
+ (case ((string_drop s14680 s14690)) of
+ s14700 =>
+ (case ((sep_matches_prefix s14700)) of
+ Some ((_, s14710)) =>
+ (case ((string_drop s14700 s14710)) of
+ s14720 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14720 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14730)) =>
+ (let p00 = (string_drop s14720 s14730) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14640 :: " string "
+
+
+\<comment> \<open>\<open>val _s1451_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1451 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1451 s14520 = (
+ (let s14530 = s14520 in
+ if ((string_startswith s14530 (''c.ldsp''))) then
+ (case ((string_drop s14530 ((string_length (''c.ldsp''))))) of
+ s14540 =>
+ (case ((spc_matches_prefix0 s14540)) of
+ Some ((_, s14550)) =>
+ (case ((string_drop s14540 s14550)) of
+ s14560 =>
+ (case ((reg_name_matches_prefix s14560 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14570)) =>
+ (case ((string_drop s14560 s14570)) of
+ s14580 =>
+ (case ((sep_matches_prefix s14580)) of
+ Some ((_, s14590)) =>
+ (case ((string_drop s14580 s14590)) of
+ s14600 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14600 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14610)) =>
+ (let p00 = (string_drop s14600 s14610) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14520 :: " string "
+
+
+\<comment> \<open>\<open>val _s1439_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1439 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1439 s14400 = (
+ (let s14410 = s14400 in
+ if ((string_startswith s14410 (''c.lwsp''))) then
+ (case ((string_drop s14410 ((string_length (''c.lwsp''))))) of
+ s14420 =>
+ (case ((spc_matches_prefix0 s14420)) of
+ Some ((_, s14430)) =>
+ (case ((string_drop s14420 s14430)) of
+ s14440 =>
+ (case ((reg_name_matches_prefix s14440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s14450)) =>
+ (case ((string_drop s14440 s14450)) of
+ s14460 =>
+ (case ((sep_matches_prefix s14460)) of
+ Some ((_, s14470)) =>
+ (case ((string_drop s14460 s14470)) of
+ s14480 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14480 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s14490)) =>
+ (let p00 = (string_drop s14480 s14490) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14400 :: " string "
+
+
+\<comment> \<open>\<open>val _s1427_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1427 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1427 s14280 = (
+ (let s14290 = s14280 in
+ if ((string_startswith s14290 (''c.slli''))) then
+ (case ((string_drop s14290 ((string_length (''c.slli''))))) of
+ s14300 =>
+ (case ((spc_matches_prefix0 s14300)) of
+ Some ((_, s14310)) =>
+ (case ((string_drop s14300 s14310)) of
+ s14320 =>
+ (case ((reg_name_matches_prefix s14320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s14330)) =>
+ (case ((string_drop s14320 s14330)) of
+ s14340 =>
+ (case ((sep_matches_prefix s14340)) of
+ Some ((_, s14350)) =>
+ (case ((string_drop s14340 s14350)) of
+ s14360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14360 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s14370)) =>
+ (let p00 = (string_drop s14360 s14370) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14280 :: " string "
+
+
+\<comment> \<open>\<open>val _s1415_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1415 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1415 s14160 = (
+ (let s14170 = s14160 in
+ if ((string_startswith s14170 (''c.bnez''))) then
+ (case ((string_drop s14170 ((string_length (''c.bnez''))))) of
+ s14180 =>
+ (case ((spc_matches_prefix0 s14180)) of
+ Some ((_, s14190)) =>
+ (case ((string_drop s14180 s14190)) of
+ s14200 =>
+ (case ((creg_name_matches_prefix s14200 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s14210)) =>
+ (case ((string_drop s14200 s14210)) of
+ s14220 =>
+ (case ((sep_matches_prefix s14220)) of
+ Some ((_, s14230)) =>
+ (case ((string_drop s14220 s14230)) of
+ s14240 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14240 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s14250)) =>
+ (let p00 = (string_drop s14240 s14250) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14160 :: " string "
+
+
+\<comment> \<open>\<open>val _s1403_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1403 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1403 s14040 = (
+ (let s14050 = s14040 in
+ if ((string_startswith s14050 (''c.beqz''))) then
+ (case ((string_drop s14050 ((string_length (''c.beqz''))))) of
+ s14060 =>
+ (case ((spc_matches_prefix0 s14060)) of
+ Some ((_, s14070)) =>
+ (case ((string_drop s14060 s14070)) of
+ s14080 =>
+ (case ((creg_name_matches_prefix s14080 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s14090)) =>
+ (case ((string_drop s14080 s14090)) of
+ s14100 =>
+ (case ((sep_matches_prefix s14100)) of
+ Some ((_, s14110)) =>
+ (case ((string_drop s14100 s14110)) of
+ s14120 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14120 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s14130)) =>
+ (let p00 = (string_drop s14120 s14130) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s14040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1395_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s1395 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s1395 s13960 = (
+ (let s13970 = s13960 in
+ if ((string_startswith s13970 (''c.j''))) then
+ (case ((string_drop s13970 ((string_length (''c.j''))))) of
+ s13980 =>
+ (case ((spc_matches_prefix0 s13980)) of
+ Some ((_, s13990)) =>
+ (case ((string_drop s13980 s13990)) of
+ s14000 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s14000 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s14010)) =>
+ (let p00 = (string_drop s14000 s14010) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13960 :: " string "
+
+
+\<comment> \<open>\<open>val _s1383_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1383 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1383 s13840 = (
+ (let s13850 = s13840 in
+ if ((string_startswith s13850 (''c.addw''))) then
+ (case ((string_drop s13850 ((string_length (''c.addw''))))) of
+ s13860 =>
+ (case ((spc_matches_prefix0 s13860)) of
+ Some ((_, s13870)) =>
+ (case ((string_drop s13860 s13870)) of
+ s13880 =>
+ (case ((creg_name_matches_prefix s13880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13890)) =>
+ (case ((string_drop s13880 s13890)) of
+ s13900 =>
+ (case ((sep_matches_prefix s13900)) of
+ Some ((_, s13910)) =>
+ (case ((string_drop s13900 s13910)) of
+ s13920 =>
+ (case ((creg_name_matches_prefix s13920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13930)) =>
+ (let p00 = (string_drop s13920 s13930) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13840 :: " string "
+
+
+\<comment> \<open>\<open>val _s1371_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1371 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1371 s13720 = (
+ (let s13730 = s13720 in
+ if ((string_startswith s13730 (''c.subw''))) then
+ (case ((string_drop s13730 ((string_length (''c.subw''))))) of
+ s13740 =>
+ (case ((spc_matches_prefix0 s13740)) of
+ Some ((_, s13750)) =>
+ (case ((string_drop s13740 s13750)) of
+ s13760 =>
+ (case ((creg_name_matches_prefix s13760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13770)) =>
+ (case ((string_drop s13760 s13770)) of
+ s13780 =>
+ (case ((sep_matches_prefix s13780)) of
+ Some ((_, s13790)) =>
+ (case ((string_drop s13780 s13790)) of
+ s13800 =>
+ (case ((creg_name_matches_prefix s13800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13810)) =>
+ (let p00 = (string_drop s13800 s13810) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13720 :: " string "
+
+
+\<comment> \<open>\<open>val _s1359_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1359 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1359 s13600 = (
+ (let s13610 = s13600 in
+ if ((string_startswith s13610 (''c.and''))) then
+ (case ((string_drop s13610 ((string_length (''c.and''))))) of
+ s13620 =>
+ (case ((spc_matches_prefix0 s13620)) of
+ Some ((_, s13630)) =>
+ (case ((string_drop s13620 s13630)) of
+ s13640 =>
+ (case ((creg_name_matches_prefix s13640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13650)) =>
+ (case ((string_drop s13640 s13650)) of
+ s13660 =>
+ (case ((sep_matches_prefix s13660)) of
+ Some ((_, s13670)) =>
+ (case ((string_drop s13660 s13670)) of
+ s13680 =>
+ (case ((creg_name_matches_prefix s13680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13690)) =>
+ (let p00 = (string_drop s13680 s13690) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1347_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1347 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1347 s13480 = (
+ (let s13490 = s13480 in
+ if ((string_startswith s13490 (''c.or''))) then
+ (case ((string_drop s13490 ((string_length (''c.or''))))) of
+ s13500 =>
+ (case ((spc_matches_prefix0 s13500)) of
+ Some ((_, s13510)) =>
+ (case ((string_drop s13500 s13510)) of
+ s13520 =>
+ (case ((creg_name_matches_prefix s13520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13530)) =>
+ (case ((string_drop s13520 s13530)) of
+ s13540 =>
+ (case ((sep_matches_prefix s13540)) of
+ Some ((_, s13550)) =>
+ (case ((string_drop s13540 s13550)) of
+ s13560 =>
+ (case ((creg_name_matches_prefix s13560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13570)) =>
+ (let p00 = (string_drop s13560 s13570) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1335_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1335 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1335 s13360 = (
+ (let s13370 = s13360 in
+ if ((string_startswith s13370 (''c.xor''))) then
+ (case ((string_drop s13370 ((string_length (''c.xor''))))) of
+ s13380 =>
+ (case ((spc_matches_prefix0 s13380)) of
+ Some ((_, s13390)) =>
+ (case ((string_drop s13380 s13390)) of
+ s13400 =>
+ (case ((creg_name_matches_prefix s13400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13410)) =>
+ (case ((string_drop s13400 s13410)) of
+ s13420 =>
+ (case ((sep_matches_prefix s13420)) of
+ Some ((_, s13430)) =>
+ (case ((string_drop s13420 s13430)) of
+ s13440 =>
+ (case ((creg_name_matches_prefix s13440 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13450)) =>
+ (let p00 = (string_drop s13440 s13450) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1323_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s1323 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s1323 s13240 = (
+ (let s13250 = s13240 in
+ if ((string_startswith s13250 (''c.sub''))) then
+ (case ((string_drop s13250 ((string_length (''c.sub''))))) of
+ s13260 =>
+ (case ((spc_matches_prefix0 s13260)) of
+ Some ((_, s13270)) =>
+ (case ((string_drop s13260 s13270)) of
+ s13280 =>
+ (case ((creg_name_matches_prefix s13280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13290)) =>
+ (case ((string_drop s13280 s13290)) of
+ s13300 =>
+ (case ((sep_matches_prefix s13300)) of
+ Some ((_, s13310)) =>
+ (case ((string_drop s13300 s13310)) of
+ s13320 =>
+ (case ((creg_name_matches_prefix s13320 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s13330)) =>
+ (let p00 = (string_drop s13320 s13330) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13240 :: " string "
+
+
+\<comment> \<open>\<open>val _s1311_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1311 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1311 s13120 = (
+ (let s13130 = s13120 in
+ if ((string_startswith s13130 (''c.andi''))) then
+ (case ((string_drop s13130 ((string_length (''c.andi''))))) of
+ s13140 =>
+ (case ((spc_matches_prefix0 s13140)) of
+ Some ((_, s13150)) =>
+ (case ((string_drop s13140 s13150)) of
+ s13160 =>
+ (case ((creg_name_matches_prefix s13160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13170)) =>
+ (case ((string_drop s13160 s13170)) of
+ s13180 =>
+ (case ((sep_matches_prefix s13180)) of
+ Some ((_, s13190)) =>
+ (case ((string_drop s13180 s13190)) of
+ s13200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s13200 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s13210)) =>
+ (let p00 = (string_drop s13200 s13210) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13120 :: " string "
+
+
+\<comment> \<open>\<open>val _s1299_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1299 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1299 s13000 = (
+ (let s13010 = s13000 in
+ if ((string_startswith s13010 (''c.srai''))) then
+ (case ((string_drop s13010 ((string_length (''c.srai''))))) of
+ s13020 =>
+ (case ((spc_matches_prefix0 s13020)) of
+ Some ((_, s13030)) =>
+ (case ((string_drop s13020 s13030)) of
+ s13040 =>
+ (case ((creg_name_matches_prefix s13040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s13050)) =>
+ (case ((string_drop s13040 s13050)) of
+ s13060 =>
+ (case ((sep_matches_prefix s13060)) of
+ Some ((_, s13070)) =>
+ (case ((string_drop s13060 s13070)) of
+ s13080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s13080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s13090)) =>
+ (let p00 = (string_drop s13080 s13090) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s13000 :: " string "
+
+
+\<comment> \<open>\<open>val _s1287_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s1287 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s1287 s12880 = (
+ (let s12890 = s12880 in
+ if ((string_startswith s12890 (''c.srli''))) then
+ (case ((string_drop s12890 ((string_length (''c.srli''))))) of
+ s12900 =>
+ (case ((spc_matches_prefix0 s12900)) of
+ Some ((_, s12910)) =>
+ (case ((string_drop s12900 s12910)) of
+ s12920 =>
+ (case ((creg_name_matches_prefix s12920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s12930)) =>
+ (case ((string_drop s12920 s12930)) of
+ s12940 =>
+ (case ((sep_matches_prefix s12940)) of
+ Some ((_, s12950)) =>
+ (case ((string_drop s12940 s12950)) of
+ s12960 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12960 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s12970)) =>
+ (let p00 = (string_drop s12960 s12970) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12880 :: " string "
+
+
+\<comment> \<open>\<open>val _s1275_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1275 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1275 s12760 = (
+ (let s12770 = s12760 in
+ if ((string_startswith s12770 (''c.lui''))) then
+ (case ((string_drop s12770 ((string_length (''c.lui''))))) of
+ s12780 =>
+ (case ((spc_matches_prefix0 s12780)) of
+ Some ((_, s12790)) =>
+ (case ((string_drop s12780 s12790)) of
+ s12800 =>
+ (case ((reg_name_matches_prefix s12800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s12810)) =>
+ (case ((string_drop s12800 s12810)) of
+ s12820 =>
+ (case ((sep_matches_prefix s12820)) of
+ Some ((_, s12830)) =>
+ (case ((string_drop s12820 s12830)) of
+ s12840 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12840 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12850)) =>
+ (let p00 = (string_drop s12840 s12850) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1267_ : string -> maybe (mword ty6)\<close>\<close>
+
+definition s1267 :: " string \<Rightarrow>((6)Word.word)option " where
+ " s1267 s12680 = (
+ (let s12690 = s12680 in
+ if ((string_startswith s12690 (''c.addi16sp''))) then
+ (case ((string_drop s12690 ((string_length (''c.addi16sp''))))) of
+ s12700 =>
+ (case ((spc_matches_prefix0 s12700)) of
+ Some ((_, s12710)) =>
+ (case ((string_drop s12700 s12710)) of
+ s12720 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12720 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12730)) =>
+ (let p00 = (string_drop s12720 s12730) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12680 :: " string "
+
+
+\<comment> \<open>\<open>val _s1255_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1255 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1255 s12560 = (
+ (let s12570 = s12560 in
+ if ((string_startswith s12570 (''c.li''))) then
+ (case ((string_drop s12570 ((string_length (''c.li''))))) of
+ s12580 =>
+ (case ((spc_matches_prefix0 s12580)) of
+ Some ((_, s12590)) =>
+ (case ((string_drop s12580 s12590)) of
+ s12600 =>
+ (case ((reg_name_matches_prefix s12600 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s12610)) =>
+ (case ((string_drop s12600 s12610)) of
+ s12620 =>
+ (case ((sep_matches_prefix s12620)) of
+ Some ((_, s12630)) =>
+ (case ((string_drop s12620 s12630)) of
+ s12640 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12640 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12650)) =>
+ (let p00 = (string_drop s12640 s12650) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12560 :: " string "
+
+
+\<comment> \<open>\<open>val _s1243_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1243 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1243 s12440 = (
+ (let s12450 = s12440 in
+ if ((string_startswith s12450 (''c.addiw''))) then
+ (case ((string_drop s12450 ((string_length (''c.addiw''))))) of
+ s12460 =>
+ (case ((spc_matches_prefix0 s12460)) of
+ Some ((_, s12470)) =>
+ (case ((string_drop s12460 s12470)) of
+ s12480 =>
+ (case ((reg_name_matches_prefix s12480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s12490)) =>
+ (case ((string_drop s12480 s12490)) of
+ s12500 =>
+ (case ((sep_matches_prefix s12500)) of
+ Some ((_, s12510)) =>
+ (case ((string_drop s12500 s12510)) of
+ s12520 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12520 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s12530)) =>
+ (let p00 = (string_drop s12520 s12530) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12440 :: " string "
+
+
+\<comment> \<open>\<open>val _s1235_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s1235 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s1235 s12360 = (
+ (let s12370 = s12360 in
+ if ((string_startswith s12370 (''c.jal''))) then
+ (case ((string_drop s12370 ((string_length (''c.jal''))))) of
+ s12380 =>
+ (case ((spc_matches_prefix0 s12380)) of
+ Some ((_, s12390)) =>
+ (case ((string_drop s12380 s12390)) of
+ s12400 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12400 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__802, s12410)) =>
+ if (((((subrange_vec_dec v__802 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__802
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__802
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let p00 = (string_drop s12400 s12410) in
+ if (((p00 = ('''')))) then Some imm else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12360 :: " string "
+
+
+\<comment> \<open>\<open>val _s1223_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s1223 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s1223 s12240 = (
+ (let s12250 = s12240 in
+ if ((string_startswith s12250 (''c.addi''))) then
+ (case ((string_drop s12250 ((string_length (''c.addi''))))) of
+ s12260 =>
+ (case ((spc_matches_prefix0 s12260)) of
+ Some ((_, s12270)) =>
+ (case ((string_drop s12260 s12270)) of
+ s12280 =>
+ (case ((reg_name_matches_prefix s12280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s12290)) =>
+ (case ((string_drop s12280 s12290)) of
+ s12300 =>
+ (case ((sep_matches_prefix s12300)) of
+ Some ((_, s12310)) =>
+ (case ((string_drop s12300 s12310)) of
+ s12320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12320 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s12330)) =>
+ (let p00 = (string_drop s12320 s12330) in
+ if (((p00 = ('''')))) then Some (rsd, nzi) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12240 :: " string "
+
+
+\<comment> \<open>\<open>val _s1207_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1207 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1207 s12080 = (
+ (let s12090 = s12080 in
+ if ((string_startswith s12090 (''c.sd''))) then
+ (case ((string_drop s12090 ((string_length (''c.sd''))))) of
+ s12100 =>
+ (case ((spc_matches_prefix0 s12100)) of
+ Some ((_, s12110)) =>
+ (case ((string_drop s12100 s12110)) of
+ s12120 =>
+ (case ((creg_name_matches_prefix s12120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s12130)) =>
+ (case ((string_drop s12120 s12130)) of
+ s12140 =>
+ (case ((sep_matches_prefix s12140)) of
+ Some ((_, s12150)) =>
+ (case ((string_drop s12140 s12150)) of
+ s12160 =>
+ (case ((creg_name_matches_prefix s12160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s12170)) =>
+ (case ((string_drop s12160 s12170)) of
+ s12180 =>
+ (case ((sep_matches_prefix s12180)) of
+ Some ((_, s12190)) =>
+ (case ((string_drop s12180 s12190)) of
+ s12200 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12200 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__804, s12210)) =>
+ if (((((subrange_vec_dec v__804 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__804 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__804 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s12200 s12210) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s12080 :: " string "
+
+
+\<comment> \<open>\<open>val _s1191_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1191 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1191 s11920 = (
+ (let s11930 = s11920 in
+ if ((string_startswith s11930 (''c.sw''))) then
+ (case ((string_drop s11930 ((string_length (''c.sw''))))) of
+ s11940 =>
+ (case ((spc_matches_prefix0 s11940)) of
+ Some ((_, s11950)) =>
+ (case ((string_drop s11940 s11950)) of
+ s11960 =>
+ (case ((creg_name_matches_prefix s11960 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s11970)) =>
+ (case ((string_drop s11960 s11970)) of
+ s11980 =>
+ (case ((sep_matches_prefix s11980)) of
+ Some ((_, s11990)) =>
+ (case ((string_drop s11980 s11990)) of
+ s12000 =>
+ (case ((creg_name_matches_prefix s12000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s12010)) =>
+ (case ((string_drop s12000 s12010)) of
+ s12020 =>
+ (case ((sep_matches_prefix s12020)) of
+ Some ((_, s12030)) =>
+ (case ((string_drop s12020 s12030)) of
+ s12040 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s12040 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__806, s12050)) =>
+ if (((((subrange_vec_dec v__806 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__806 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__806 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s12040 s12050) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11920 :: " string "
+
+
+\<comment> \<open>\<open>val _s1175_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1175 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1175 s11760 = (
+ (let s11770 = s11760 in
+ if ((string_startswith s11770 (''c.ld''))) then
+ (case ((string_drop s11770 ((string_length (''c.ld''))))) of
+ s11780 =>
+ (case ((spc_matches_prefix0 s11780)) of
+ Some ((_, s11790)) =>
+ (case ((string_drop s11780 s11790)) of
+ s11800 =>
+ (case ((creg_name_matches_prefix s11800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11810)) =>
+ (case ((string_drop s11800 s11810)) of
+ s11820 =>
+ (case ((sep_matches_prefix s11820)) of
+ Some ((_, s11830)) =>
+ (case ((string_drop s11820 s11830)) of
+ s11840 =>
+ (case ((creg_name_matches_prefix s11840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s11850)) =>
+ (case ((string_drop s11840 s11850)) of
+ s11860 =>
+ (case ((sep_matches_prefix s11860)) of
+ Some ((_, s11870)) =>
+ (case ((string_drop s11860 s11870)) of
+ s11880 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11880 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__808, s11890)) =>
+ if (((((subrange_vec_dec v__808 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__808 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__808 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s11880 s11890) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11760 :: " string "
+
+
+\<comment> \<open>\<open>val _s1159_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s1159 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s1159 s11600 = (
+ (let s11610 = s11600 in
+ if ((string_startswith s11610 (''c.lw''))) then
+ (case ((string_drop s11610 ((string_length (''c.lw''))))) of
+ s11620 =>
+ (case ((spc_matches_prefix0 s11620)) of
+ Some ((_, s11630)) =>
+ (case ((string_drop s11620 s11630)) of
+ s11640 =>
+ (case ((creg_name_matches_prefix s11640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11650)) =>
+ (case ((string_drop s11640 s11650)) of
+ s11660 =>
+ (case ((sep_matches_prefix s11660)) of
+ Some ((_, s11670)) =>
+ (case ((string_drop s11660 s11670)) of
+ s11680 =>
+ (case ((creg_name_matches_prefix s11680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s11690)) =>
+ (case ((string_drop s11680 s11690)) of
+ s11700 =>
+ (case ((sep_matches_prefix s11700)) of
+ Some ((_, s11710)) =>
+ (case ((string_drop s11700 s11710)) of
+ s11720 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11720 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__810, s11730)) =>
+ if (((((subrange_vec_dec v__810 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__810 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__810 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s11720 s11730) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1147_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s1147 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s1147 s11480 = (
+ (let s11490 = s11480 in
+ if ((string_startswith s11490 (''c.addi4spn''))) then
+ (case ((string_drop s11490 ((string_length (''c.addi4spn''))))) of
+ s11500 =>
+ (case ((spc_matches_prefix0 s11500)) of
+ Some ((_, s11510)) =>
+ (case ((string_drop s11500 s11510)) of
+ s11520 =>
+ (case ((creg_name_matches_prefix s11520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s11530)) =>
+ (case ((string_drop s11520 s11530)) of
+ s11540 =>
+ (case ((sep_matches_prefix s11540)) of
+ Some ((_, s11550)) =>
+ (case ((string_drop s11540 s11550)) of
+ s11560 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s11560 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__812, s11570)) =>
+ if (((((subrange_vec_dec v__812 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__812 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__812 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let p00 = (string_drop s11560 s11570) in
+ if (((p00 = ('''')))) then Some (rdc, nzimm) else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1123_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1123 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1123 s11250 = (
+ (case ((amo_mnemonic_matches_prefix s11250)) of
+ Some ((op1, s11260)) =>
+ (let s11270 = (string_drop s11250 s11260) in
+ if ((string_startswith s11270 (''.''))) then
+ (case ((string_drop s11270 ((string_length (''.''))))) of
+ s11280 =>
+ (case ((size_mnemonic_matches_prefix s11280)) of
+ Some ((width, s11290)) =>
+ (case ((string_drop s11280 s11290)) of
+ s11300 =>
+ (case ((maybe_aq_matches_prefix s11300)) of
+ Some ((aq, s11310)) =>
+ (case ((string_drop s11300 s11310)) of
+ s11320 =>
+ (case ((maybe_rl_matches_prefix s11320)) of
+ Some ((rl, s11330)) =>
+ (case ((string_drop s11320 s11330)) of
+ s11340 =>
+ (case ((spc_matches_prefix0 s11340)) of
+ Some ((_, s11350)) =>
+ (case ((string_drop s11340 s11350)) of
+ s11360 =>
+ (case ((reg_name_matches_prefix s11360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s11370)) =>
+ (case ((string_drop s11360 s11370)) of
+ s11380 =>
+ (case ((sep_matches_prefix s11380)) of
+ Some ((_, s11390)) =>
+ (case ((string_drop s11380 s11390)) of
+ s11400 =>
+ (case ((reg_name_matches_prefix s11400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s11410)) =>
+ (case ((string_drop s11400 s11410)) of
+ s11420 =>
+ (case ((sep_matches_prefix s11420)) of
+ Some ((_, s11430)) =>
+ (case ((string_drop s11420 s11430)) of
+ s11440 =>
+ (case ((reg_name_matches_prefix s11440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s11450)) =>
+ (let p00 = (string_drop s11440 s11450) in
+ if (((p00 = ('''')))) then Some (op1, width, aq, rl, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s11250 :: " string "
+
+
+\<comment> \<open>\<open>val _s1101_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1101 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1101 s11020 = (
+ (let s11030 = s11020 in
+ if ((string_startswith s11030 (''sc.''))) then
+ (case ((string_drop s11030 ((string_length (''sc.''))))) of
+ s11040 =>
+ (case ((size_mnemonic_matches_prefix s11040)) of
+ Some ((size1, s11050)) =>
+ (case ((string_drop s11040 s11050)) of
+ s11060 =>
+ (case ((maybe_aq_matches_prefix s11060)) of
+ Some ((aq, s11070)) =>
+ (case ((string_drop s11060 s11070)) of
+ s11080 =>
+ (case ((maybe_rl_matches_prefix s11080)) of
+ Some ((rl, s11090)) =>
+ (case ((string_drop s11080 s11090)) of
+ s11100 =>
+ (case ((spc_matches_prefix0 s11100)) of
+ Some ((_, s11110)) =>
+ (case ((string_drop s11100 s11110)) of
+ s11120 =>
+ (case ((reg_name_matches_prefix s11120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s11130)) =>
+ (case ((string_drop s11120 s11130)) of
+ s11140 =>
+ (case ((sep_matches_prefix s11140)) of
+ Some ((_, s11150)) =>
+ (case ((string_drop s11140 s11150)) of
+ s11160 =>
+ (case ((reg_name_matches_prefix s11160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s11170)) =>
+ (case ((string_drop s11160 s11170)) of
+ s11180 =>
+ (case ((sep_matches_prefix s11180)) of
+ Some ((_, s11190)) =>
+ (case ((string_drop s11180 s11190)) of
+ s11200 =>
+ (case ((reg_name_matches_prefix s11200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s11210)) =>
+ (let p00 = (string_drop s11200 s11210) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s11020 :: " string "
+
+
+\<comment> \<open>\<open>val _s1083_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1083 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word)option " where
+ " s1083 s10840 = (
+ (let s10850 = s10840 in
+ if ((string_startswith s10850 (''lr.''))) then
+ (case ((string_drop s10850 ((string_length (''lr.''))))) of
+ s10860 =>
+ (case ((size_mnemonic_matches_prefix s10860)) of
+ Some ((size1, s10870)) =>
+ (case ((string_drop s10860 s10870)) of
+ s10880 =>
+ (case ((maybe_aq_matches_prefix s10880)) of
+ Some ((aq, s10890)) =>
+ (case ((string_drop s10880 s10890)) of
+ s10900 =>
+ (case ((maybe_rl_matches_prefix s10900)) of
+ Some ((rl, s10910)) =>
+ (case ((string_drop s10900 s10910)) of
+ s10920 =>
+ (case ((spc_matches_prefix0 s10920)) of
+ Some ((_, s10930)) =>
+ (case ((string_drop s10920 s10930)) of
+ s10940 =>
+ (case ((reg_name_matches_prefix s10940 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10950)) =>
+ (case ((string_drop s10940 s10950)) of
+ s10960 =>
+ (case ((sep_matches_prefix s10960)) of
+ Some ((_, s10970)) =>
+ (case ((string_drop s10960 s10970)) of
+ s10980 =>
+ (case ((reg_name_matches_prefix s10980 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10990)) =>
+ (let p00 = (string_drop s10980 s10990) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10840 :: " string "
+
+
+\<comment> \<open>\<open>val _s1071_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1071 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1071 s10720 = (
+ (let s10730 = s10720 in
+ if ((string_startswith s10730 (''sfence.vma''))) then
+ (case ((string_drop s10730 ((string_length (''sfence.vma''))))) of
+ s10740 =>
+ (case ((spc_matches_prefix0 s10740)) of
+ Some ((_, s10750)) =>
+ (case ((string_drop s10740 s10750)) of
+ s10760 =>
+ (case ((reg_name_matches_prefix s10760 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10770)) =>
+ (case ((string_drop s10760 s10770)) of
+ s10780 =>
+ (case ((sep_matches_prefix s10780)) of
+ Some ((_, s10790)) =>
+ (case ((string_drop s10780 s10790)) of
+ s10800 =>
+ (case ((reg_name_matches_prefix s10800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s10810)) =>
+ (let p00 = (string_drop s10800 s10810) in
+ if (((p00 = ('''')))) then Some (rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10720 :: " string "
+
+
+\<comment> \<open>\<open>val _s1059_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1059 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1059 s10600 = (
+ (let s10610 = s10600 in
+ if ((string_startswith s10610 (''fence.tso''))) then
+ (case ((string_drop s10610 ((string_length (''fence.tso''))))) of
+ s10620 =>
+ (case ((spc_matches_prefix0 s10620)) of
+ Some ((_, s10630)) =>
+ (case ((string_drop s10620 s10630)) of
+ s10640 =>
+ (case ((fence_bits_matches_prefix s10640 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s10650)) =>
+ (case ((string_drop s10640 s10650)) of
+ s10660 =>
+ (case ((sep_matches_prefix s10660)) of
+ Some ((_, s10670)) =>
+ (case ((string_drop s10660 s10670)) of
+ s10680 =>
+ (case ((fence_bits_matches_prefix s10680 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s10690)) =>
+ (let p00 = (string_drop s10680 s10690) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10600 :: " string "
+
+
+\<comment> \<open>\<open>val _s1047_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1047 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1047 s10480 = (
+ (let s10490 = s10480 in
+ if ((string_startswith s10490 (''fence''))) then
+ (case ((string_drop s10490 ((string_length (''fence''))))) of
+ s10500 =>
+ (case ((spc_matches_prefix0 s10500)) of
+ Some ((_, s10510)) =>
+ (case ((string_drop s10500 s10510)) of
+ s10520 =>
+ (case ((fence_bits_matches_prefix s10520 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s10530)) =>
+ (case ((string_drop s10520 s10530)) of
+ s10540 =>
+ (case ((sep_matches_prefix s10540)) of
+ Some ((_, s10550)) =>
+ (case ((string_drop s10540 s10550)) of
+ s10560 =>
+ (case ((fence_bits_matches_prefix s10560 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s10570)) =>
+ (let p00 = (string_drop s10560 s10570) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s10480 :: " string "
+
+
+\<comment> \<open>\<open>val _s1030_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1030 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1030 s10320 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s10320)) of
+ Some ((op1, s10330)) =>
+ (case ((string_drop s10320 s10330)) of
+ s10340 =>
+ (case ((spc_matches_prefix0 s10340)) of
+ Some ((_, s10350)) =>
+ (case ((string_drop s10340 s10350)) of
+ s10360 =>
+ (case ((reg_name_matches_prefix s10360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10370)) =>
+ (case ((string_drop s10360 s10370)) of
+ s10380 =>
+ (case ((sep_matches_prefix s10380)) of
+ Some ((_, s10390)) =>
+ (case ((string_drop s10380 s10390)) of
+ s10400 =>
+ (case ((reg_name_matches_prefix s10400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10410)) =>
+ (case ((string_drop s10400 s10410)) of
+ s10420 =>
+ (case ((sep_matches_prefix s10420)) of
+ Some ((_, s10430)) =>
+ (case ((string_drop s10420 s10430)) of
+ s10440 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s10440 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s10450)) =>
+ (let p00 = (string_drop s10440 s10450) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s10320 :: " string "
+
+
+\<comment> \<open>\<open>val _s1013_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1013 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1013 s10150 = (
+ (case ((rtypew_mnemonic_matches_prefix s10150)) of
+ Some ((op1, s10160)) =>
+ (case ((string_drop s10150 s10160)) of
+ s10170 =>
+ (case ((spc_matches_prefix0 s10170)) of
+ Some ((_, s10180)) =>
+ (case ((string_drop s10170 s10180)) of
+ s10190 =>
+ (case ((reg_name_matches_prefix s10190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10200)) =>
+ (case ((string_drop s10190 s10200)) of
+ s10210 =>
+ (case ((sep_matches_prefix s10210)) of
+ Some ((_, s10220)) =>
+ (case ((string_drop s10210 s10220)) of
+ s10230 =>
+ (case ((reg_name_matches_prefix s10230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10240)) =>
+ (case ((string_drop s10230 s10240)) of
+ s10250 =>
+ (case ((sep_matches_prefix s10250)) of
+ Some ((_, s10260)) =>
+ (case ((string_drop s10250 s10260)) of
+ s10270 =>
+ (case ((reg_name_matches_prefix s10270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s10280)) =>
+ (let p00 = (string_drop s10270 s10280) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s10150 :: " string "
+
+
+\<comment> \<open>\<open>val _s996_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s996 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s996 s9980 = (
+ (case ((shiftw_mnemonic_matches_prefix s9980)) of
+ Some ((op1, s9990)) =>
+ (case ((string_drop s9980 s9990)) of
+ s10000 =>
+ (case ((spc_matches_prefix0 s10000)) of
+ Some ((_, s10010)) =>
+ (case ((string_drop s10000 s10010)) of
+ s10020 =>
+ (case ((reg_name_matches_prefix s10020 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s10030)) =>
+ (case ((string_drop s10020 s10030)) of
+ s10040 =>
+ (case ((sep_matches_prefix s10040)) of
+ Some ((_, s10050)) =>
+ (case ((string_drop s10040 s10050)) of
+ s10060 =>
+ (case ((reg_name_matches_prefix s10060 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s10070)) =>
+ (case ((string_drop s10060 s10070)) of
+ s10080 =>
+ (case ((sep_matches_prefix s10080)) of
+ Some ((_, s10090)) =>
+ (case ((string_drop s10080 s10090)) of
+ s10100 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s10100 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s10110)) =>
+ (let p00 = (string_drop s10100 s10110) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s9980 :: " string "
+
+
+\<comment> \<open>\<open>val _s980_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s980 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s980 s9810 = (
+ (let s9820 = s9810 in
+ if ((string_startswith s9820 (''addiw''))) then
+ (case ((string_drop s9820 ((string_length (''addiw''))))) of
+ s9830 =>
+ (case ((spc_matches_prefix0 s9830)) of
+ Some ((_, s9840)) =>
+ (case ((string_drop s9830 s9840)) of
+ s9850 =>
+ (case ((reg_name_matches_prefix s9850 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9860)) =>
+ (case ((string_drop s9850 s9860)) of
+ s9870 =>
+ (case ((sep_matches_prefix s9870)) of
+ Some ((_, s9880)) =>
+ (case ((string_drop s9870 s9880)) of
+ s9890 =>
+ (case ((reg_name_matches_prefix s9890 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9900)) =>
+ (case ((string_drop s9890 s9900)) of
+ s9910 =>
+ (case ((sep_matches_prefix s9910)) of
+ Some ((_, s9920)) =>
+ (case ((string_drop s9910 s9920)) of
+ s9930 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9930 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9940)) =>
+ (let p00 = (string_drop s9930 s9940) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9810 :: " string "
+
+
+\<comment> \<open>\<open>val _s952_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s952 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s952 s9530 = (
+ (let s9540 = s9530 in
+ if ((string_startswith s9540 (''s''))) then
+ (case ((string_drop s9540 ((string_length (''s''))))) of
+ s9550 =>
+ (case ((size_mnemonic_matches_prefix s9550)) of
+ Some ((size1, s9560)) =>
+ (case ((string_drop s9550 s9560)) of
+ s9570 =>
+ (case ((maybe_aq_matches_prefix s9570)) of
+ Some ((aq, s9580)) =>
+ (case ((string_drop s9570 s9580)) of
+ s9590 =>
+ (case ((maybe_rl_matches_prefix s9590)) of
+ Some ((rl, s9600)) =>
+ (case ((string_drop s9590 s9600)) of
+ s9610 =>
+ (case ((spc_matches_prefix0 s9610)) of
+ Some ((_, s9620)) =>
+ (case ((string_drop s9610 s9620)) of
+ s9630 =>
+ (case ((reg_name_matches_prefix s9630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s9640)) =>
+ (case ((string_drop s9630 s9640)) of
+ s9650 =>
+ (case ((sep_matches_prefix s9650)) of
+ Some ((_, s9660)) =>
+ (case ((string_drop s9650 s9660)) of
+ s9670 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9670 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9680)) =>
+ (case ((string_drop s9670 s9680)) of
+ s9690 =>
+ (case ((opt_spc_matches_prefix0 s9690)) of
+ Some ((_, s9700)) =>
+ (let s9710 = (string_drop s9690 s9700) in
+ if ((string_startswith s9710 (''(''))) then
+ (case ((string_drop s9710 ((string_length (''(''))))) of
+ s9720 =>
+ (case ((opt_spc_matches_prefix0 s9720)) of
+ Some ((_, s9730)) =>
+ (case ((string_drop s9720 s9730)) of
+ s9740 =>
+ (case ((reg_name_matches_prefix s9740 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9750)) =>
+ (case ((string_drop s9740 s9750)) of
+ s9760 =>
+ (case ((opt_spc_matches_prefix0 s9760)) of
+ Some ((_, s9770)) =>
+ (let s9780 = (string_drop s9760 s9770) in
+ if ((string_startswith s9780 ('')''))) then
+ (let p00 = (string_drop s9780 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rs2, imm, rs1) else
+ None) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9530 :: " string "
+
+
+\<comment> \<open>\<open>val _s922_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s922 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s922 s9230 = (
+ (let s9240 = s9230 in
+ if ((string_startswith s9240 (''l''))) then
+ (case ((string_drop s9240 ((string_length (''l''))))) of
+ s9250 =>
+ (case ((size_mnemonic_matches_prefix s9250)) of
+ Some ((size1, s9260)) =>
+ (case ((string_drop s9250 s9260)) of
+ s9270 =>
+ (case ((maybe_u_matches_prefix s9270)) of
+ Some ((is_unsigned, s9280)) =>
+ (case ((string_drop s9270 s9280)) of
+ s9290 =>
+ (case ((maybe_aq_matches_prefix s9290)) of
+ Some ((aq, s9300)) =>
+ (case ((string_drop s9290 s9300)) of
+ s9310 =>
+ (case ((maybe_rl_matches_prefix s9310)) of
+ Some ((rl, s9320)) =>
+ (case ((string_drop s9310 s9320)) of
+ s9330 =>
+ (case ((spc_matches_prefix0 s9330)) of
+ Some ((_, s9340)) =>
+ (case ((string_drop s9330 s9340)) of
+ s9350 =>
+ (case ((reg_name_matches_prefix s9350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9360)) =>
+ (case ((string_drop s9350 s9360)) of
+ s9370 =>
+ (case ((sep_matches_prefix s9370)) of
+ Some ((_, s9380)) =>
+ (case ((string_drop s9370 s9380)) of
+ s9390 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9390 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s9400)) =>
+ (case ((string_drop s9390 s9400)) of
+ s9410 =>
+ (case ((opt_spc_matches_prefix0 s9410)) of
+ Some ((_, s9420)) =>
+ (let s9430 = (string_drop s9410 s9420) in
+ if ((string_startswith s9430 (''(''))) then
+ (case ((string_drop s9430 ((string_length (''(''))))) of
+ s9440 =>
+ (case ((opt_spc_matches_prefix0 s9440)) of
+ Some ((_, s9450)) =>
+ (case ((string_drop s9440 s9450)) of
+ s9460 =>
+ (case ((reg_name_matches_prefix s9460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9470)) =>
+ (case ((string_drop s9460 s9470)) of
+ s9480 =>
+ (case ((opt_spc_matches_prefix0 s9480)) of
+ Some ((_, s9490)) =>
+ (let s9500 = (string_drop s9480 s9490) in
+ if ((string_startswith s9500 ('')''))) then
+ (let p00 = (string_drop s9500 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1) else None) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s9230 :: " string "
+
+
+\<comment> \<open>\<open>val _s905_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s905 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s905 s9070 = (
+ (case ((rtype_mnemonic_matches_prefix s9070)) of
+ Some ((op1, s9080)) =>
+ (case ((string_drop s9070 s9080)) of
+ s9090 =>
+ (case ((spc_matches_prefix0 s9090)) of
+ Some ((_, s9100)) =>
+ (case ((string_drop s9090 s9100)) of
+ s9110 =>
+ (case ((reg_name_matches_prefix s9110 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s9120)) =>
+ (case ((string_drop s9110 s9120)) of
+ s9130 =>
+ (case ((sep_matches_prefix s9130)) of
+ Some ((_, s9140)) =>
+ (case ((string_drop s9130 s9140)) of
+ s9150 =>
+ (case ((reg_name_matches_prefix s9150 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s9160)) =>
+ (case ((string_drop s9150 s9160)) of
+ s9170 =>
+ (case ((sep_matches_prefix s9170)) of
+ Some ((_, s9180)) =>
+ (case ((string_drop s9170 s9180)) of
+ s9190 =>
+ (case ((reg_name_matches_prefix s9190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s9200)) =>
+ (let p00 = (string_drop s9190 s9200) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s9070 :: " string "
+
+
+\<comment> \<open>\<open>val _s888_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))\<close>\<close>
+
+definition s888 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word)option " where
+ " s888 s8900 = (
+ (case ((shiftiop_mnemonic_matches_prefix s8900)) of
+ Some ((op1, s8910)) =>
+ (case ((string_drop s8900 s8910)) of
+ s8920 =>
+ (case ((spc_matches_prefix0 s8920)) of
+ Some ((_, s8930)) =>
+ (case ((string_drop s8920 s8930)) of
+ s8940 =>
+ (case ((reg_name_matches_prefix s8940 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8950)) =>
+ (case ((string_drop s8940 s8950)) of
+ s8960 =>
+ (case ((sep_matches_prefix s8960)) of
+ Some ((_, s8970)) =>
+ (case ((string_drop s8960 s8970)) of
+ s8980 =>
+ (case ((reg_name_matches_prefix s8980 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8990)) =>
+ (case ((string_drop s8980 s8990)) of
+ s9000 =>
+ (case ((sep_matches_prefix s9000)) of
+ Some ((_, s9010)) =>
+ (case ((string_drop s9000 s9010)) of
+ s9020 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s9020 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s9030)) =>
+ (let p00 = (string_drop s9020 s9030) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8900 :: " string "
+
+
+\<comment> \<open>\<open>val _s871_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s871 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s871 s8730 = (
+ (case ((itype_mnemonic_matches_prefix s8730)) of
+ Some ((op1, s8740)) =>
+ (case ((string_drop s8730 s8740)) of
+ s8750 =>
+ (case ((spc_matches_prefix0 s8750)) of
+ Some ((_, s8760)) =>
+ (case ((string_drop s8750 s8760)) of
+ s8770 =>
+ (case ((reg_name_matches_prefix s8770 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8780)) =>
+ (case ((string_drop s8770 s8780)) of
+ s8790 =>
+ (case ((sep_matches_prefix s8790)) of
+ Some ((_, s8800)) =>
+ (case ((string_drop s8790 s8800)) of
+ s8810 =>
+ (case ((reg_name_matches_prefix s8810 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8820)) =>
+ (case ((string_drop s8810 s8820)) of
+ s8830 =>
+ (case ((sep_matches_prefix s8830)) of
+ Some ((_, s8840)) =>
+ (case ((string_drop s8830 s8840)) of
+ s8850 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8850 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s8860)) =>
+ (let p00 = (string_drop s8850 s8860) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8730 :: " string "
+
+
+\<comment> \<open>\<open>val _s854_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))\<close>\<close>
+
+definition s854 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word)option " where
+ " s854 s8560 = (
+ (case ((btype_mnemonic_matches_prefix s8560)) of
+ Some ((op1, s8570)) =>
+ (case ((string_drop s8560 s8570)) of
+ s8580 =>
+ (case ((spc_matches_prefix0 s8580)) of
+ Some ((_, s8590)) =>
+ (case ((string_drop s8580 s8590)) of
+ s8600 =>
+ (case ((reg_name_matches_prefix s8600 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8610)) =>
+ (case ((string_drop s8600 s8610)) of
+ s8620 =>
+ (case ((sep_matches_prefix s8620)) of
+ Some ((_, s8630)) =>
+ (case ((string_drop s8620 s8630)) of
+ s8640 =>
+ (case ((reg_name_matches_prefix s8640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s8650)) =>
+ (case ((string_drop s8640 s8650)) of
+ s8660 =>
+ (case ((sep_matches_prefix s8660)) of
+ Some ((_, s8670)) =>
+ (case ((string_drop s8660 s8670)) of
+ s8680 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8680 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s8690)) =>
+ (let p00 = (string_drop s8680 s8690) in
+ if (((p00 = ('''')))) then Some (op1, rs1, rs2, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8560 :: " string "
+
+
+\<comment> \<open>\<open>val _s838_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s838 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s838 s8390 = (
+ (let s8400 = s8390 in
+ if ((string_startswith s8400 (''jalr''))) then
+ (case ((string_drop s8400 ((string_length (''jalr''))))) of
+ s8410 =>
+ (case ((spc_matches_prefix0 s8410)) of
+ Some ((_, s8420)) =>
+ (case ((string_drop s8410 s8420)) of
+ s8430 =>
+ (case ((reg_name_matches_prefix s8430 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8440)) =>
+ (case ((string_drop s8430 s8440)) of
+ s8450 =>
+ (case ((sep_matches_prefix s8450)) of
+ Some ((_, s8460)) =>
+ (case ((string_drop s8450 s8460)) of
+ s8470 =>
+ (case ((reg_name_matches_prefix s8470 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s8480)) =>
+ (case ((string_drop s8470 s8480)) of
+ s8490 =>
+ (case ((sep_matches_prefix s8490)) of
+ Some ((_, s8500)) =>
+ (case ((string_drop s8490 s8500)) of
+ s8510 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8510 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s8520)) =>
+ (let p00 = (string_drop s8510 s8520) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s8390 :: " string "
+
+
+\<comment> \<open>\<open>val _s826_ : string -> maybe ((mword ty5 * mword ty21))\<close>\<close>
+
+definition s826 :: " string \<Rightarrow>((5)Word.word*(21)Word.word)option " where
+ " s826 s8270 = (
+ (let s8280 = s8270 in
+ if ((string_startswith s8280 (''jal''))) then
+ (case ((string_drop s8280 ((string_length (''jal''))))) of
+ s8290 =>
+ (case ((spc_matches_prefix0 s8290)) of
+ Some ((_, s8300)) =>
+ (case ((string_drop s8290 s8300)) of
+ s8310 =>
+ (case ((reg_name_matches_prefix s8310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8320)) =>
+ (case ((string_drop s8310 s8320)) of
+ s8330 =>
+ (case ((sep_matches_prefix s8330)) of
+ Some ((_, s8340)) =>
+ (case ((string_drop s8330 s8340)) of
+ s8350 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8350 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s8360)) =>
+ (let p00 = (string_drop s8350 s8360) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s8270 :: " string "
+
+
+\<comment> \<open>\<open>val _s813_ : string -> maybe ((uop * mword ty5 * mword ty20))\<close>\<close>
+
+definition s813 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word)option " where
+ " s813 s8150 = (
+ (case ((utype_mnemonic_matches_prefix s8150)) of
+ Some ((op1, s8160)) =>
+ (case ((string_drop s8150 s8160)) of
+ s8170 =>
+ (case ((spc_matches_prefix0 s8170)) of
+ Some ((_, s8180)) =>
+ (case ((string_drop s8170 s8180)) of
+ s8190 =>
+ (case ((reg_name_matches_prefix s8190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s8200)) =>
+ (case ((string_drop s8190 s8200)) of
+ s8210 =>
+ (case ((sep_matches_prefix s8210)) of
+ Some ((_, s8220)) =>
+ (case ((string_drop s8210 s8220)) of
+ s8230 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s8230 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s8240)) =>
+ (let p00 = (string_drop s8230 s8240) in
+ if (((p00 = ('''')))) then Some (op1, rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s8150 :: " string "
+
+
+definition assembly_backwards :: " string \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " assembly_backwards arg1 = (
+ (let s8250 = arg1 in
+ if ((case ((s813 s8250 :: ((uop * 5 Word.word * 20 Word.word))option)) of
+ Some ((op1, rd, imm)) => True
+ | _ => False
+ )) then (case (s813 s8250 :: (( uop * 5 Word.word * 20 Word.word)) option) of
+ (Some ((op1, rd, imm))) =>
+ return (UTYPE (imm, rd, op1))
+ )
+ else if ((case ((s826 s8250 :: (( 5 Word.word * 21 Word.word))option)) of
+ Some ((rd, imm)) => True
+ | _ => False
+ )) then (case (s826 s8250 :: (( 5 Word.word * 21 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (RISCV_JAL (imm, rd))
+ )
+ else if ((case ((s838 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => True
+ | _ => False
+ )) then (case (s838 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ return (RISCV_JALR (imm, rs1, rd))
+ )
+ else if ((case ((s854 s8250 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word))option)) of
+ Some ((op1, rs1, rs2, imm)) => True
+ | _ => False
+ )) then (case
+ (s854 s8250 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word)) option) of
+ (Some ((op1, rs1, rs2, imm))) =>
+ return (BTYPE (imm, rs2, rs1, op1))
+ )
+ else if ((case ((s871 s8250 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, imm)) => True
+ | _ => False
+ )) then (case
+ (s871 s8250 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, imm))) =>
+ return (ITYPE (imm, rs1, rd, op1))
+ )
+ else if ((case ((s888 s8250 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => True
+ | _ => False
+ )) then (case
+ (s888 s8250 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTIOP (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s905 s8250 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s905 s8250 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ return (RTYPE (rs2, rs1, rd, op1))
+ )
+ else if ((case ((s922 s8250
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s922 s8250
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ return (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl))
+ )
+ else if ((case ((s952 s8250
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s952 s8250 :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1))) =>
+ return (STORE (imm, rs2, rs1, size1, aq, rl))
+ )
+ else if ((case ((s980 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s980 s8250 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ return (ADDIW (imm, rs1, rd))
+ )
+ else if ((case ((s996 s8250 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s996 s8250 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTW (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s1013 s8250 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1013 s8250 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ return (RTYPEW (rs2, rs1, rd, op1))
+ )
+ else if ((case ((s1030 s8250 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1030 s8250 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ return (SHIFTIWOP (shamt, rs1, rd, op1))
+ )
+ else if ((case ((s1047 s8250 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1047 s8250 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ return (FENCE (pred, succ))
+ )
+ else if ((case ((s1059 s8250 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1059 s8250 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ return (FENCE_TSO (pred, succ))
+ )
+ else if (((s8250 = (''fence.i'')))) then return (FENCEI () )
+ else if (((s8250 = (''ecall'')))) then return (ECALL () )
+ else if (((s8250 = (''mret'')))) then return (MRET () )
+ else if (((s8250 = (''sret'')))) then return (SRET () )
+ else if (((s8250 = (''ebreak'')))) then return (EBREAK () )
+ else if (((s8250 = (''wfi'')))) then return (WFI () )
+ else if ((case ((s1071 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rs1, rs2)) => True
+ | _ => False
+ )) then (case (s1071 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rs1, rs2))) =>
+ return (SFENCE_VMA (rs1, rs2))
+ )
+ else if ((case ((s1083 s8250 :: ((word_width * bool * bool * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1083 s8250 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1))) =>
+ return (LOADRES (aq, rl, rs1, size1, rd))
+ )
+ else if ((case ((s1101 s8250
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1101 s8250 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2))) =>
+ return (STORECON (aq, rl, rs2, rs1, size1, rd))
+ )
+ else if ((case ((s1123 s8250
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1123 s8250
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2))) =>
+ return (AMO (op1, aq, rl, rs2, rs1, width, rd))
+ )
+ else if (((s8250 = (''c.nop'')))) then return (C_NOP () )
+ else if ((case ((s1147 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rdc, nzimm)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s1147 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rdc, nzimm))) =>
+ return (C_ADDI4SPN (rdc, nzimm))
+ )
+ else if ((case ((s1159 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => True
+ | _ => False
+ )) then (case (s1159 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ return (C_LW (uimm, rsc, rdc))
+ )
+ else if ((case ((s1175 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1175 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ return (C_LD (uimm, rsc, rdc))
+ )
+ else if ((case ((s1191 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => True
+ | _ => False
+ )) then (case
+ (s1191 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ return (C_SW (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1207 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1207 s8250 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ return (C_SD (uimm, rsc1, rsc2))
+ )
+ else if ((case ((s1223 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, nzi)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1223 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, nzi))) =>
+ return (C_ADDI (nzi, rsd))
+ )
+ else if ((case ((s1235 s8250 :: ( 11 Word.word)option)) of
+ Some (imm) => ((( 64 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s1235 s8250 :: ( 11 Word.word) option) of
+ (Some (imm)) =>
+ return (C_JAL imm)
+ )
+ else if ((case ((s1243 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1243 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ return (C_ADDIW (imm, rsd))
+ )
+ else if ((case ((s1255 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1255 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (C_LI (imm, rd))
+ )
+ else if ((case ((s1267 s8250 :: ( 6 Word.word)option)) of
+ Some (imm) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1267 s8250 :: ( 6 Word.word) option) of
+ (Some (imm)) =>
+ return (C_ADDI16SP imm)
+ )
+ else if ((case ((s1275 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s1275 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ return (C_LUI (imm, rd))
+ )
+ else if ((case ((s1287 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1287 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SRLI (shamt, rsd))
+ )
+ else if ((case ((s1299 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s1299 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SRAI (shamt, rsd))
+ )
+ else if ((case ((s1311 s8250 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => True
+ | _ => False
+ )) then (case (s1311 s8250 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ return (C_ANDI (imm, rsd))
+ )
+ else if ((case ((s1323 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1323 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_SUB (rsd, rs2))
+ )
+ else if ((case ((s1335 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1335 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_XOR (rsd, rs2))
+ )
+ else if ((case ((s1347 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1347 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_OR (rsd, rs2))
+ )
+ else if ((case ((s1359 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s1359 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_AND (rsd, rs2))
+ )
+ else if ((case ((s1371 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1371 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_SUBW (rsd, rs2))
+ )
+ else if ((case ((s1383 s8250 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1383 s8250 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_ADDW (rsd, rs2))
+ )
+ else if ((case ((s1395 s8250 :: ( 11 Word.word)option)) of
+ Some (imm) => True
+ | _ => False
+ )) then (case (s1395 s8250 :: ( 11 Word.word) option) of
+ (Some (imm)) =>
+ return (C_J imm)
+ )
+ else if ((case ((s1403 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s1403 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ return (C_BEQZ (imm, rs))
+ )
+ else if ((case ((s1415 s8250 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s1415 s8250 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ return (C_BNEZ (imm, rs))
+ )
+ else if ((case ((s1427 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1427 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ return (C_SLLI (shamt, rsd))
+ )
+ else if ((case ((s1439 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1439 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_LWSP (uimm, rd))
+ )
+ else if ((case ((s1451 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s1451 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_LDSP (uimm, rd))
+ )
+ else if ((case ((s1463 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => True
+ | _ => False
+ )) then (case (s1463 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ return (C_SWSP (uimm, rd))
+ )
+ else if ((case ((s1475 s8250 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rs2, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1475 s8250 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rs2, uimm))) =>
+ return (C_SDSP (uimm, rs2))
+ )
+ else if ((case ((s1487 s8250 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1487 s8250 :: ( 5 Word.word) option) of
+ (Some (rs1)) =>
+ return (C_JR rs1)
+ )
+ else if ((case ((s1495 s8250 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s1495 s8250 :: ( 5 Word.word) option) of
+ (Some (rs1)) =>
+ return (C_JALR rs1)
+ )
+ else if ((case ((s1503 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1503 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs2))) =>
+ return (C_MV (rd, rs2))
+ )
+ else if (((s8250 = (''c.ebreak'')))) then return (C_EBREAK () )
+ else if ((case ((s1515 s8250 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s1515 s8250 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ return (C_ADD (rsd, rs2))
+ )
+ else if ((case ((s1527 s8250
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1527 s8250 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2))) =>
+ return (MUL (rs2, rs1, rd, high, signed1, signed2))
+ )
+ else if ((case ((s1544 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1544 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (DIV (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1562 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1562 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (REM (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1580 s8250 :: (( 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1580 s8250 :: (( 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs1, rs2))) =>
+ return (MULW (rs2, rs1, rd))
+ )
+ else if ((case ((s1596 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1596 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (DIVW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1615 s8250 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1615 s8250 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ return (REMW (rs2, rs1, rd, s))
+ )
+ else if ((case ((s1634 s8250 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s1634 s8250 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ return (CSR (csr, rs1, rd, True, op1))
+ )
+ else if ((case ((s1652 s8250 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s1652 s8250 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ return (CSR (csr, rs1, rd, False, op1))
+ )
+ else if (((s8250 = (''uret'')))) then return (URET () )
+ else if ((case ((s1669 s8250 :: ( 32 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s1669 s8250 :: ( 32 Word.word) option) of
+ (Some (s)) =>
+ return (ILLEGAL s)
+ )
+ else if ((case ((s1677 s8250 :: ( 16 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s1677 s8250 :: ( 16 Word.word) option) of
+ (Some (s)) =>
+ return (C_ILLEGAL s)
+ )
+ else assert_exp False (''Pattern match failure at unknown location'') \<then> exit0 () ))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val assembly_forwards_matches : ast -> bool\<close>\<close>
+
+fun assembly_forwards_matches :: " ast \<Rightarrow> bool " where
+ " assembly_forwards_matches (UTYPE ((imm, rd, op1))) = ( True )"
+ for op1 :: " uop "
+ and imm :: "(20)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RISCV_JAL ((imm, rd))) = ( True )"
+ for imm :: "(21)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RISCV_JALR ((imm, rs1, rd))) = ( True )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (BTYPE ((imm, rs2, rs1, op1))) = ( True )"
+ for op1 :: " bop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(13)Word.word "
+|" assembly_forwards_matches (ITYPE ((imm, rs1, rd, op1))) = ( True )"
+ for op1 :: " iop "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTIOP ((shamt, rs1, rd, op1))) = ( True )"
+ for op1 :: " sop "
+ and shamt :: "(6)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RTYPE ((rs2, rs1, rd, op1))) = ( True )"
+ for op1 :: " rop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (LOAD ((imm, rs1, rd, is_unsigned, size1, aq, rl))) = ( True )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+ and is_unsigned :: " bool "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (STORE ((imm, rs2, rs1, size1, aq, rl))) = ( True )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (ADDIW ((imm, rs1, rd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs1 :: "(5)Word.word "
+ and imm :: "(12)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTW ((shamt, rs1, rd, op1))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " sop "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (RTYPEW ((rs2, rs1, rd, op1))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " ropw "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (SHIFTIWOP ((shamt, rs1, rd, op1))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for op1 :: " sopw "
+ and shamt :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (FENCE ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards_matches (FENCE_TSO ((pred, succ))) = ( True )"
+ for pred :: "(4)Word.word "
+ and succ :: "(4)Word.word "
+|" assembly_forwards_matches (FENCEI (_)) = ( True )"
+|" assembly_forwards_matches (ECALL (_)) = ( True )"
+|" assembly_forwards_matches (MRET (_)) = ( True )"
+|" assembly_forwards_matches (SRET (_)) = ( True )"
+|" assembly_forwards_matches (EBREAK (_)) = ( True )"
+|" assembly_forwards_matches (WFI (_)) = ( True )"
+|" assembly_forwards_matches (SFENCE_VMA ((rs1, rs2))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (LOADRES ((aq, rl, rs1, size1, rd))) = ( True )"
+ for size1 :: " word_width "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (STORECON ((aq, rl, rs2, rs1, size1, rd))) = ( True )"
+ for size1 :: " word_width "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and rl :: " bool "
+|" assembly_forwards_matches (AMO ((op1, aq, rl, rs2, rs1, width, rd))) = ( True )"
+ for op1 :: " amoop "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and aq :: " bool "
+ and width :: " word_width "
+ and rl :: " bool "
+|" assembly_forwards_matches (C_NOP (_)) = ( True )"
+|" assembly_forwards_matches (C_ADDI4SPN ((rdc, nzimm))) = (
+ if (((nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then True else False )"
+ for nzimm :: "(8)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_LW ((uimm, rsc, rdc))) = ( True )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_LD ((uimm, rsc, rdc))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsc :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+ and rdc :: "(3)Word.word "
+|" assembly_forwards_matches (C_SW ((uimm, rsc1, rsc2))) = ( True )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards_matches (C_SD ((uimm, rsc1, rsc2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsc2 :: "(3)Word.word "
+ and rsc1 :: "(3)Word.word "
+ and uimm :: "(5)Word.word "
+|" assembly_forwards_matches (C_ADDI ((nzi, rsd))) = (
+ if ((((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for nzi :: "(6)Word.word "
+ and rsd :: "(5)Word.word "
+|" assembly_forwards_matches (C_JAL (imm)) = ( if ((((( 64 :: int)::ii) = (( 32 :: int)::ii)))) then True else False )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards_matches (C_ADDIW ((imm, rsd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(5)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_LI ((imm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_ADDI16SP (imm)) = (
+ if (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_LUI ((imm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then
+ True
+ else False )"
+ for imm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SRLI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_SRAI ((shamt, rsd))) = (
+ if (((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_ANDI ((imm, rsd))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and imm :: "(6)Word.word "
+|" assembly_forwards_matches (C_SUB ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_XOR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_OR ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_AND ((rsd, rs2))) = ( True )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_SUBW ((rsd, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_ADDW ((rsd, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rsd :: "(3)Word.word "
+ and rs2 :: "(3)Word.word "
+|" assembly_forwards_matches (C_J (imm)) = ( True )"
+ for imm :: "(11)Word.word "
+|" assembly_forwards_matches (C_BEQZ ((imm, rs))) = ( True )"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards_matches (C_BNEZ ((imm, rs))) = ( True )"
+ for rs :: "(3)Word.word "
+ and imm :: "(8)Word.word "
+|" assembly_forwards_matches (C_SLLI ((shamt, rsd))) = (
+ if ((((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and shamt :: "(6)Word.word "
+|" assembly_forwards_matches (C_LWSP ((uimm, rd))) = (
+ if (((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_LDSP ((uimm, rd))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))))
+ then
+ True
+ else False )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SWSP ((uimm, rd))) = ( True )"
+ for uimm :: "(6)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_SDSP ((uimm, rs2))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for uimm :: "(6)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards_matches (C_JR (rs1)) = ( if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (C_JALR (rs1)) = (
+ if (((((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg))))) then True else False )"
+ for rs1 :: "(5)Word.word "
+|" assembly_forwards_matches (C_MV ((rd, rs2))) = (
+ if ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rs2 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (C_EBREAK (_)) = ( True )"
+|" assembly_forwards_matches (C_ADD ((rsd, rs2))) = (
+ if ((((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg)))))))) then
+ True
+ else False )"
+ for rsd :: "(5)Word.word "
+ and rs2 :: "(5)Word.word "
+|" assembly_forwards_matches (MUL ((rs2, rs1, rd, high, signed1, signed2))) = ( True )"
+ for signed2 :: " bool "
+ and signed1 :: " bool "
+ and high :: " bool "
+ and rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (DIV ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (REM ((rs2, rs1, rd, s))) = ( True )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (MULW ((rs2, rs1, rd))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+|" assembly_forwards_matches (DIVW ((rs2, rs1, rd, s))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (REMW ((rs2, rs1, rd, s))) = ( if ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))) then True else False )"
+ for rs2 :: "(5)Word.word "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and s :: " bool "
+|" assembly_forwards_matches (CSR ((csr, rs1, rd, True, op1))) = ( True )"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards_matches (CSR ((csr, rs1, rd, False, op1))) = ( True )"
+ for op1 :: " csrop "
+ and rs1 :: "(5)Word.word "
+ and rd :: "(5)Word.word "
+ and csr :: "(12)Word.word "
+|" assembly_forwards_matches (URET (_)) = ( True )"
+|" assembly_forwards_matches (ILLEGAL (s)) = ( True )"
+ for s :: "(32)Word.word "
+|" assembly_forwards_matches (C_ILLEGAL (s)) = ( True )"
+ for s :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val assembly_backwards_matches : string -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val _s2549_ : string -> maybe (mword ty16)\<close>\<close>
+
+definition s2549 :: " string \<Rightarrow>((16)Word.word)option " where
+ " s2549 s25500 = (
+ (let s25510 = s25500 in
+ if ((string_startswith s25510 (''c.illegal''))) then
+ (case ((string_drop s25510 ((string_length (''c.illegal''))))) of
+ s25520 =>
+ (case ((spc_matches_prefix0 s25520)) of
+ Some ((_, s25530)) =>
+ (case ((string_drop s25520 s25530)) of
+ s25540 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25540 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s25550)) =>
+ (let p00 = (string_drop s25540 s25550) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25500 :: " string "
+
+
+\<comment> \<open>\<open>val _s2541_ : string -> maybe (mword ty32)\<close>\<close>
+
+definition s2541 :: " string \<Rightarrow>((32)Word.word)option " where
+ " s2541 s25420 = (
+ (let s25430 = s25420 in
+ if ((string_startswith s25430 (''illegal''))) then
+ (case ((string_drop s25430 ((string_length (''illegal''))))) of
+ s25440 =>
+ (case ((spc_matches_prefix0 s25440)) of
+ Some ((_, s25450)) =>
+ (case ((string_drop s25440 s25450)) of
+ s25460 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25460 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s25470)) =>
+ (let p00 = (string_drop s25460 s25470) in
+ if (((p00 = ('''')))) then Some s else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25420 :: " string "
+
+
+\<comment> \<open>\<open>val _s2524_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s2524 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s2524 s25260 = (
+ (case ((csr_mnemonic_matches_prefix s25260)) of
+ Some ((op1, s25270)) =>
+ (case ((string_drop s25260 s25270)) of
+ s25280 =>
+ (case ((spc_matches_prefix0 s25280)) of
+ Some ((_, s25290)) =>
+ (case ((string_drop s25280 s25290)) of
+ s25300 =>
+ (case ((reg_name_matches_prefix s25300 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25310)) =>
+ (case ((string_drop s25300 s25310)) of
+ s25320 =>
+ (case ((sep_matches_prefix s25320)) of
+ Some ((_, s25330)) =>
+ (case ((string_drop s25320 s25330)) of
+ s25340 =>
+ (case ((reg_name_matches_prefix s25340 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25350)) =>
+ (case ((string_drop s25340 s25350)) of
+ s25360 =>
+ (case ((sep_matches_prefix s25360)) of
+ Some ((_, s25370)) =>
+ (case ((string_drop s25360 s25370)) of
+ s25380 =>
+ (case ((csr_name_map_matches_prefix s25380
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s25390)) =>
+ (let p00 = (string_drop s25380 s25390) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s25260 :: " string "
+
+
+\<comment> \<open>\<open>val _s2506_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s2506 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s2506 s25080 = (
+ (case ((csr_mnemonic_matches_prefix s25080)) of
+ Some ((op1, s25090)) =>
+ (let s25100 = (string_drop s25080 s25090) in
+ if ((string_startswith s25100 (''i''))) then
+ (case ((string_drop s25100 ((string_length (''i''))))) of
+ s25110 =>
+ (case ((spc_matches_prefix0 s25110)) of
+ Some ((_, s25120)) =>
+ (case ((string_drop s25110 s25120)) of
+ s25130 =>
+ (case ((reg_name_matches_prefix s25130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25140)) =>
+ (case ((string_drop s25130 s25140)) of
+ s25150 =>
+ (case ((sep_matches_prefix s25150)) of
+ Some ((_, s25160)) =>
+ (case ((string_drop s25150 s25160)) of
+ s25170 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25180)) =>
+ (case ((string_drop s25170 s25180)) of
+ s25190 =>
+ (case ((sep_matches_prefix s25190)) of
+ Some ((_, s25200)) =>
+ (case ((string_drop s25190 s25200)) of
+ s25210 =>
+ (case ((csr_name_map_matches_prefix s25210
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s25220)) =>
+ (let p00 = (string_drop s25210 s25220) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, csr) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s25080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2487_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2487 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2487 s24880 = (
+ (let s24890 = s24880 in
+ if ((string_startswith s24890 (''rem''))) then
+ (case ((string_drop s24890 ((string_length (''rem''))))) of
+ s24900 =>
+ (case ((maybe_not_u_matches_prefix s24900)) of
+ Some ((s, s24910)) =>
+ (let s24920 = (string_drop s24900 s24910) in
+ if ((string_startswith s24920 (''w''))) then
+ (case ((string_drop s24920 ((string_length (''w''))))) of
+ s24930 =>
+ (case ((spc_matches_prefix0 s24930)) of
+ Some ((_, s24940)) =>
+ (case ((string_drop s24930 s24940)) of
+ s24950 =>
+ (case ((reg_name_matches_prefix s24950 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24960)) =>
+ (case ((string_drop s24950 s24960)) of
+ s24970 =>
+ (case ((sep_matches_prefix s24970)) of
+ Some ((_, s24980)) =>
+ (case ((string_drop s24970 s24980)) of
+ s24990 =>
+ (case ((reg_name_matches_prefix s24990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25000)) =>
+ (case ((string_drop s24990 s25000)) of
+ s25010 =>
+ (case ((sep_matches_prefix s25010)) of
+ Some ((_, s25020)) =>
+ (case ((string_drop s25010 s25020)) of
+ s25030 =>
+ (case ((reg_name_matches_prefix s25030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s25040)) =>
+ (let p00 = (string_drop s25030 s25040) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s24880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2468_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2468 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2468 s24690 = (
+ (let s24700 = s24690 in
+ if ((string_startswith s24700 (''div''))) then
+ (case ((string_drop s24700 ((string_length (''div''))))) of
+ s24710 =>
+ (case ((maybe_not_u_matches_prefix s24710)) of
+ Some ((s, s24720)) =>
+ (let s24730 = (string_drop s24710 s24720) in
+ if ((string_startswith s24730 (''w''))) then
+ (case ((string_drop s24730 ((string_length (''w''))))) of
+ s24740 =>
+ (case ((spc_matches_prefix0 s24740)) of
+ Some ((_, s24750)) =>
+ (case ((string_drop s24740 s24750)) of
+ s24760 =>
+ (case ((reg_name_matches_prefix s24760 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24770)) =>
+ (case ((string_drop s24760 s24770)) of
+ s24780 =>
+ (case ((sep_matches_prefix s24780)) of
+ Some ((_, s24790)) =>
+ (case ((string_drop s24780 s24790)) of
+ s24800 =>
+ (case ((reg_name_matches_prefix s24800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24810)) =>
+ (case ((string_drop s24800 s24810)) of
+ s24820 =>
+ (case ((sep_matches_prefix s24820)) of
+ Some ((_, s24830)) =>
+ (case ((string_drop s24820 s24830)) of
+ s24840 =>
+ (case ((reg_name_matches_prefix s24840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24850)) =>
+ (let p00 = (string_drop s24840 s24850) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s24690 :: " string "
+
+
+\<comment> \<open>\<open>val _s2452_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2452 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2452 s24530 = (
+ (let s24540 = s24530 in
+ if ((string_startswith s24540 (''mulw''))) then
+ (case ((string_drop s24540 ((string_length (''mulw''))))) of
+ s24550 =>
+ (case ((spc_matches_prefix0 s24550)) of
+ Some ((_, s24560)) =>
+ (case ((string_drop s24550 s24560)) of
+ s24570 =>
+ (case ((reg_name_matches_prefix s24570 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24580)) =>
+ (case ((string_drop s24570 s24580)) of
+ s24590 =>
+ (case ((sep_matches_prefix s24590)) of
+ Some ((_, s24600)) =>
+ (case ((string_drop s24590 s24600)) of
+ s24610 =>
+ (case ((reg_name_matches_prefix s24610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24620)) =>
+ (case ((string_drop s24610 s24620)) of
+ s24630 =>
+ (case ((sep_matches_prefix s24630)) of
+ Some ((_, s24640)) =>
+ (case ((string_drop s24630 s24640)) of
+ s24650 =>
+ (case ((reg_name_matches_prefix s24650 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24660)) =>
+ (let p00 = (string_drop s24650 s24660) in
+ if (((p00 = ('''')))) then Some (rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24530 :: " string "
+
+
+\<comment> \<open>\<open>val _s2434_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2434 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2434 s24350 = (
+ (let s24360 = s24350 in
+ if ((string_startswith s24360 (''rem''))) then
+ (case ((string_drop s24360 ((string_length (''rem''))))) of
+ s24370 =>
+ (case ((maybe_not_u_matches_prefix s24370)) of
+ Some ((s, s24380)) =>
+ (case ((string_drop s24370 s24380)) of
+ s24390 =>
+ (case ((spc_matches_prefix0 s24390)) of
+ Some ((_, s24400)) =>
+ (case ((string_drop s24390 s24400)) of
+ s24410 =>
+ (case ((reg_name_matches_prefix s24410 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24420)) =>
+ (case ((string_drop s24410 s24420)) of
+ s24430 =>
+ (case ((sep_matches_prefix s24430)) of
+ Some ((_, s24440)) =>
+ (case ((string_drop s24430 s24440)) of
+ s24450 =>
+ (case ((reg_name_matches_prefix s24450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24460)) =>
+ (case ((string_drop s24450 s24460)) of
+ s24470 =>
+ (case ((sep_matches_prefix s24470)) of
+ Some ((_, s24480)) =>
+ (case ((string_drop s24470 s24480)) of
+ s24490 =>
+ (case ((reg_name_matches_prefix s24490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24500)) =>
+ (let p00 = (string_drop s24490 s24500) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24350 :: " string "
+
+
+\<comment> \<open>\<open>val _s2416_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2416 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2416 s24170 = (
+ (let s24180 = s24170 in
+ if ((string_startswith s24180 (''div''))) then
+ (case ((string_drop s24180 ((string_length (''div''))))) of
+ s24190 =>
+ (case ((maybe_not_u_matches_prefix s24190)) of
+ Some ((s, s24200)) =>
+ (case ((string_drop s24190 s24200)) of
+ s24210 =>
+ (case ((spc_matches_prefix0 s24210)) of
+ Some ((_, s24220)) =>
+ (case ((string_drop s24210 s24220)) of
+ s24230 =>
+ (case ((reg_name_matches_prefix s24230 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24240)) =>
+ (case ((string_drop s24230 s24240)) of
+ s24250 =>
+ (case ((sep_matches_prefix s24250)) of
+ Some ((_, s24260)) =>
+ (case ((string_drop s24250 s24260)) of
+ s24270 =>
+ (case ((reg_name_matches_prefix s24270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24280)) =>
+ (case ((string_drop s24270 s24280)) of
+ s24290 =>
+ (case ((sep_matches_prefix s24290)) of
+ Some ((_, s24300)) =>
+ (case ((string_drop s24290 s24300)) of
+ s24310 =>
+ (case ((reg_name_matches_prefix s24310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24320)) =>
+ (let p00 = (string_drop s24310 s24320) in
+ if (((p00 = ('''')))) then Some (s, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s24170 :: " string "
+
+
+\<comment> \<open>\<open>val _s2399_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s2399 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s2399 s24010 = (
+ (case ((mul_mnemonic_matches_prefix s24010)) of
+ Some (((high, signed1, signed2), s24020)) =>
+ (case ((string_drop s24010 s24020)) of
+ s24030 =>
+ (case ((spc_matches_prefix0 s24030)) of
+ Some ((_, s24040)) =>
+ (case ((string_drop s24030 s24040)) of
+ s24050 =>
+ (case ((reg_name_matches_prefix s24050 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s24060)) =>
+ (case ((string_drop s24050 s24060)) of
+ s24070 =>
+ (case ((sep_matches_prefix s24070)) of
+ Some ((_, s24080)) =>
+ (case ((string_drop s24070 s24080)) of
+ s24090 =>
+ (case ((reg_name_matches_prefix s24090 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s24100)) =>
+ (case ((string_drop s24090 s24100)) of
+ s24110 =>
+ (case ((sep_matches_prefix s24110)) of
+ Some ((_, s24120)) =>
+ (case ((string_drop s24110 s24120)) of
+ s24130 =>
+ (case ((reg_name_matches_prefix s24130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s24140)) =>
+ (let p00 = (string_drop s24130 s24140) in
+ if (((p00 = ('''')))) then Some (high, signed1, signed2, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s24010 :: " string "
+
+
+\<comment> \<open>\<open>val _s2387_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s2387 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s2387 s23880 = (
+ (let s23890 = s23880 in
+ if ((string_startswith s23890 (''c.add''))) then
+ (case ((string_drop s23890 ((string_length (''c.add''))))) of
+ s23900 =>
+ (case ((spc_matches_prefix0 s23900)) of
+ Some ((_, s23910)) =>
+ (case ((string_drop s23900 s23910)) of
+ s23920 =>
+ (case ((reg_name_matches_prefix s23920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s23930)) =>
+ (case ((string_drop s23920 s23930)) of
+ s23940 =>
+ (case ((sep_matches_prefix s23940)) of
+ Some ((_, s23950)) =>
+ (case ((string_drop s23940 s23950)) of
+ s23960 =>
+ (case ((reg_name_matches_prefix s23960 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23970)) =>
+ (let p00 = (string_drop s23960 s23970) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2375_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s2375 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s2375 s23760 = (
+ (let s23770 = s23760 in
+ if ((string_startswith s23770 (''c.mv''))) then
+ (case ((string_drop s23770 ((string_length (''c.mv''))))) of
+ s23780 =>
+ (case ((spc_matches_prefix0 s23780)) of
+ Some ((_, s23790)) =>
+ (case ((string_drop s23780 s23790)) of
+ s23800 =>
+ (case ((reg_name_matches_prefix s23800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23810)) =>
+ (case ((string_drop s23800 s23810)) of
+ s23820 =>
+ (case ((sep_matches_prefix s23820)) of
+ Some ((_, s23830)) =>
+ (case ((string_drop s23820 s23830)) of
+ s23840 =>
+ (case ((reg_name_matches_prefix s23840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23850)) =>
+ (let p00 = (string_drop s23840 s23850) in
+ if (((p00 = ('''')))) then Some (rd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2367_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s2367 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s2367 s23680 = (
+ (let s23690 = s23680 in
+ if ((string_startswith s23690 (''c.jalr''))) then
+ (case ((string_drop s23690 ((string_length (''c.jalr''))))) of
+ s23700 =>
+ (case ((spc_matches_prefix0 s23700)) of
+ Some ((_, s23710)) =>
+ (case ((string_drop s23700 s23710)) of
+ s23720 =>
+ (case ((reg_name_matches_prefix s23720 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s23730)) =>
+ (let p00 = (string_drop s23720 s23730) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23680 :: " string "
+
+
+\<comment> \<open>\<open>val _s2359_ : string -> maybe (mword ty5)\<close>\<close>
+
+definition s2359 :: " string \<Rightarrow>((5)Word.word)option " where
+ " s2359 s23600 = (
+ (let s23610 = s23600 in
+ if ((string_startswith s23610 (''c.jr''))) then
+ (case ((string_drop s23610 ((string_length (''c.jr''))))) of
+ s23620 =>
+ (case ((spc_matches_prefix0 s23620)) of
+ Some ((_, s23630)) =>
+ (case ((string_drop s23620 s23630)) of
+ s23640 =>
+ (case ((reg_name_matches_prefix s23640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s23650)) =>
+ (let p00 = (string_drop s23640 s23650) in
+ if (((p00 = ('''')))) then Some rs1 else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23600 :: " string "
+
+
+\<comment> \<open>\<open>val _s2347_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2347 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2347 s23480 = (
+ (let s23490 = s23480 in
+ if ((string_startswith s23490 (''c.sdsp''))) then
+ (case ((string_drop s23490 ((string_length (''c.sdsp''))))) of
+ s23500 =>
+ (case ((spc_matches_prefix0 s23500)) of
+ Some ((_, s23510)) =>
+ (case ((string_drop s23500 s23510)) of
+ s23520 =>
+ (case ((reg_name_matches_prefix s23520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s23530)) =>
+ (case ((string_drop s23520 s23530)) of
+ s23540 =>
+ (case ((sep_matches_prefix s23540)) of
+ Some ((_, s23550)) =>
+ (case ((string_drop s23540 s23550)) of
+ s23560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23560 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23570)) =>
+ (let p00 = (string_drop s23560 s23570) in
+ if (((p00 = ('''')))) then Some (rs2, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2335_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2335 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2335 s23360 = (
+ (let s23370 = s23360 in
+ if ((string_startswith s23370 (''c.swsp''))) then
+ (case ((string_drop s23370 ((string_length (''c.swsp''))))) of
+ s23380 =>
+ (case ((spc_matches_prefix0 s23380)) of
+ Some ((_, s23390)) =>
+ (case ((string_drop s23380 s23390)) of
+ s23400 =>
+ (case ((reg_name_matches_prefix s23400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23410)) =>
+ (case ((string_drop s23400 s23410)) of
+ s23420 =>
+ (case ((sep_matches_prefix s23420)) of
+ Some ((_, s23430)) =>
+ (case ((string_drop s23420 s23430)) of
+ s23440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23440 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23450)) =>
+ (let p00 = (string_drop s23440 s23450) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23360 :: " string "
+
+
+\<comment> \<open>\<open>val _s2323_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2323 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2323 s23240 = (
+ (let s23250 = s23240 in
+ if ((string_startswith s23250 (''c.ldsp''))) then
+ (case ((string_drop s23250 ((string_length (''c.ldsp''))))) of
+ s23260 =>
+ (case ((spc_matches_prefix0 s23260)) of
+ Some ((_, s23270)) =>
+ (case ((string_drop s23260 s23270)) of
+ s23280 =>
+ (case ((reg_name_matches_prefix s23280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23290)) =>
+ (case ((string_drop s23280 s23290)) of
+ s23300 =>
+ (case ((sep_matches_prefix s23300)) of
+ Some ((_, s23310)) =>
+ (case ((string_drop s23300 s23310)) of
+ s23320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23320 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23330)) =>
+ (let p00 = (string_drop s23320 s23330) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23240 :: " string "
+
+
+\<comment> \<open>\<open>val _s2311_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2311 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2311 s23120 = (
+ (let s23130 = s23120 in
+ if ((string_startswith s23130 (''c.lwsp''))) then
+ (case ((string_drop s23130 ((string_length (''c.lwsp''))))) of
+ s23140 =>
+ (case ((spc_matches_prefix0 s23140)) of
+ Some ((_, s23150)) =>
+ (case ((string_drop s23140 s23150)) of
+ s23160 =>
+ (case ((reg_name_matches_prefix s23160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s23170)) =>
+ (case ((string_drop s23160 s23170)) of
+ s23180 =>
+ (case ((sep_matches_prefix s23180)) of
+ Some ((_, s23190)) =>
+ (case ((string_drop s23180 s23190)) of
+ s23200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23200 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s23210)) =>
+ (let p00 = (string_drop s23200 s23210) in
+ if (((p00 = ('''')))) then Some (rd, uimm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23120 :: " string "
+
+
+\<comment> \<open>\<open>val _s2299_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2299 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2299 s23000 = (
+ (let s23010 = s23000 in
+ if ((string_startswith s23010 (''c.slli''))) then
+ (case ((string_drop s23010 ((string_length (''c.slli''))))) of
+ s23020 =>
+ (case ((spc_matches_prefix0 s23020)) of
+ Some ((_, s23030)) =>
+ (case ((string_drop s23020 s23030)) of
+ s23040 =>
+ (case ((reg_name_matches_prefix s23040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s23050)) =>
+ (case ((string_drop s23040 s23050)) of
+ s23060 =>
+ (case ((sep_matches_prefix s23060)) of
+ Some ((_, s23070)) =>
+ (case ((string_drop s23060 s23070)) of
+ s23080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s23080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s23090)) =>
+ (let p00 = (string_drop s23080 s23090) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s23000 :: " string "
+
+
+\<comment> \<open>\<open>val _s2287_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2287 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2287 s22880 = (
+ (let s22890 = s22880 in
+ if ((string_startswith s22890 (''c.bnez''))) then
+ (case ((string_drop s22890 ((string_length (''c.bnez''))))) of
+ s22900 =>
+ (case ((spc_matches_prefix0 s22900)) of
+ Some ((_, s22910)) =>
+ (case ((string_drop s22900 s22910)) of
+ s22920 =>
+ (case ((creg_name_matches_prefix s22920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s22930)) =>
+ (case ((string_drop s22920 s22930)) of
+ s22940 =>
+ (case ((sep_matches_prefix s22940)) of
+ Some ((_, s22950)) =>
+ (case ((string_drop s22940 s22950)) of
+ s22960 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22960 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s22970)) =>
+ (let p00 = (string_drop s22960 s22970) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22880 :: " string "
+
+
+\<comment> \<open>\<open>val _s2275_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2275 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2275 s22760 = (
+ (let s22770 = s22760 in
+ if ((string_startswith s22770 (''c.beqz''))) then
+ (case ((string_drop s22770 ((string_length (''c.beqz''))))) of
+ s22780 =>
+ (case ((spc_matches_prefix0 s22780)) of
+ Some ((_, s22790)) =>
+ (case ((string_drop s22780 s22790)) of
+ s22800 =>
+ (case ((creg_name_matches_prefix s22800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s22810)) =>
+ (case ((string_drop s22800 s22810)) of
+ s22820 =>
+ (case ((sep_matches_prefix s22820)) of
+ Some ((_, s22830)) =>
+ (case ((string_drop s22820 s22830)) of
+ s22840 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22840 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s22850)) =>
+ (let p00 = (string_drop s22840 s22850) in
+ if (((p00 = ('''')))) then Some (rs, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2267_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s2267 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s2267 s22680 = (
+ (let s22690 = s22680 in
+ if ((string_startswith s22690 (''c.j''))) then
+ (case ((string_drop s22690 ((string_length (''c.j''))))) of
+ s22700 =>
+ (case ((spc_matches_prefix0 s22700)) of
+ Some ((_, s22710)) =>
+ (case ((string_drop s22700 s22710)) of
+ s22720 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s22720 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s22730)) =>
+ (let p00 = (string_drop s22720 s22730) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22680 :: " string "
+
+
+\<comment> \<open>\<open>val _s2255_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2255 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2255 s22560 = (
+ (let s22570 = s22560 in
+ if ((string_startswith s22570 (''c.addw''))) then
+ (case ((string_drop s22570 ((string_length (''c.addw''))))) of
+ s22580 =>
+ (case ((spc_matches_prefix0 s22580)) of
+ Some ((_, s22590)) =>
+ (case ((string_drop s22580 s22590)) of
+ s22600 =>
+ (case ((creg_name_matches_prefix s22600 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22610)) =>
+ (case ((string_drop s22600 s22610)) of
+ s22620 =>
+ (case ((sep_matches_prefix s22620)) of
+ Some ((_, s22630)) =>
+ (case ((string_drop s22620 s22630)) of
+ s22640 =>
+ (case ((creg_name_matches_prefix s22640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22650)) =>
+ (let p00 = (string_drop s22640 s22650) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22560 :: " string "
+
+
+\<comment> \<open>\<open>val _s2243_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2243 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2243 s22440 = (
+ (let s22450 = s22440 in
+ if ((string_startswith s22450 (''c.subw''))) then
+ (case ((string_drop s22450 ((string_length (''c.subw''))))) of
+ s22460 =>
+ (case ((spc_matches_prefix0 s22460)) of
+ Some ((_, s22470)) =>
+ (case ((string_drop s22460 s22470)) of
+ s22480 =>
+ (case ((creg_name_matches_prefix s22480 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22490)) =>
+ (case ((string_drop s22480 s22490)) of
+ s22500 =>
+ (case ((sep_matches_prefix s22500)) of
+ Some ((_, s22510)) =>
+ (case ((string_drop s22500 s22510)) of
+ s22520 =>
+ (case ((creg_name_matches_prefix s22520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22530)) =>
+ (let p00 = (string_drop s22520 s22530) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22440 :: " string "
+
+
+\<comment> \<open>\<open>val _s2231_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2231 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2231 s22320 = (
+ (let s22330 = s22320 in
+ if ((string_startswith s22330 (''c.and''))) then
+ (case ((string_drop s22330 ((string_length (''c.and''))))) of
+ s22340 =>
+ (case ((spc_matches_prefix0 s22340)) of
+ Some ((_, s22350)) =>
+ (case ((string_drop s22340 s22350)) of
+ s22360 =>
+ (case ((creg_name_matches_prefix s22360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22370)) =>
+ (case ((string_drop s22360 s22370)) of
+ s22380 =>
+ (case ((sep_matches_prefix s22380)) of
+ Some ((_, s22390)) =>
+ (case ((string_drop s22380 s22390)) of
+ s22400 =>
+ (case ((creg_name_matches_prefix s22400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22410)) =>
+ (let p00 = (string_drop s22400 s22410) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2219_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2219 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2219 s22200 = (
+ (let s22210 = s22200 in
+ if ((string_startswith s22210 (''c.or''))) then
+ (case ((string_drop s22210 ((string_length (''c.or''))))) of
+ s22220 =>
+ (case ((spc_matches_prefix0 s22220)) of
+ Some ((_, s22230)) =>
+ (case ((string_drop s22220 s22230)) of
+ s22240 =>
+ (case ((creg_name_matches_prefix s22240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22250)) =>
+ (case ((string_drop s22240 s22250)) of
+ s22260 =>
+ (case ((sep_matches_prefix s22260)) of
+ Some ((_, s22270)) =>
+ (case ((string_drop s22260 s22270)) of
+ s22280 =>
+ (case ((creg_name_matches_prefix s22280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22290)) =>
+ (let p00 = (string_drop s22280 s22290) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2207_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2207 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2207 s22080 = (
+ (let s22090 = s22080 in
+ if ((string_startswith s22090 (''c.xor''))) then
+ (case ((string_drop s22090 ((string_length (''c.xor''))))) of
+ s22100 =>
+ (case ((spc_matches_prefix0 s22100)) of
+ Some ((_, s22110)) =>
+ (case ((string_drop s22100 s22110)) of
+ s22120 =>
+ (case ((creg_name_matches_prefix s22120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22130)) =>
+ (case ((string_drop s22120 s22130)) of
+ s22140 =>
+ (case ((sep_matches_prefix s22140)) of
+ Some ((_, s22150)) =>
+ (case ((string_drop s22140 s22150)) of
+ s22160 =>
+ (case ((creg_name_matches_prefix s22160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22170)) =>
+ (let p00 = (string_drop s22160 s22170) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s22080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2195_ : string -> maybe ((mword ty3 * mword ty3))\<close>\<close>
+
+definition s2195 :: " string \<Rightarrow>((3)Word.word*(3)Word.word)option " where
+ " s2195 s21960 = (
+ (let s21970 = s21960 in
+ if ((string_startswith s21970 (''c.sub''))) then
+ (case ((string_drop s21970 ((string_length (''c.sub''))))) of
+ s21980 =>
+ (case ((spc_matches_prefix0 s21980)) of
+ Some ((_, s21990)) =>
+ (case ((string_drop s21980 s21990)) of
+ s22000 =>
+ (case ((creg_name_matches_prefix s22000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s22010)) =>
+ (case ((string_drop s22000 s22010)) of
+ s22020 =>
+ (case ((sep_matches_prefix s22020)) of
+ Some ((_, s22030)) =>
+ (case ((string_drop s22020 s22030)) of
+ s22040 =>
+ (case ((creg_name_matches_prefix s22040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s22050)) =>
+ (let p00 = (string_drop s22040 s22050) in
+ if (((p00 = ('''')))) then Some (rsd, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2183_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2183 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2183 s21840 = (
+ (let s21850 = s21840 in
+ if ((string_startswith s21850 (''c.andi''))) then
+ (case ((string_drop s21850 ((string_length (''c.andi''))))) of
+ s21860 =>
+ (case ((spc_matches_prefix0 s21860)) of
+ Some ((_, s21870)) =>
+ (case ((string_drop s21860 s21870)) of
+ s21880 =>
+ (case ((creg_name_matches_prefix s21880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21890)) =>
+ (case ((string_drop s21880 s21890)) of
+ s21900 =>
+ (case ((sep_matches_prefix s21900)) of
+ Some ((_, s21910)) =>
+ (case ((string_drop s21900 s21910)) of
+ s21920 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21920 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21930)) =>
+ (let p00 = (string_drop s21920 s21930) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21840 :: " string "
+
+
+\<comment> \<open>\<open>val _s2171_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2171 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2171 s21720 = (
+ (let s21730 = s21720 in
+ if ((string_startswith s21730 (''c.srai''))) then
+ (case ((string_drop s21730 ((string_length (''c.srai''))))) of
+ s21740 =>
+ (case ((spc_matches_prefix0 s21740)) of
+ Some ((_, s21750)) =>
+ (case ((string_drop s21740 s21750)) of
+ s21760 =>
+ (case ((creg_name_matches_prefix s21760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21770)) =>
+ (case ((string_drop s21760 s21770)) of
+ s21780 =>
+ (case ((sep_matches_prefix s21780)) of
+ Some ((_, s21790)) =>
+ (case ((string_drop s21780 s21790)) of
+ s21800 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21800 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s21810)) =>
+ (let p00 = (string_drop s21800 s21810) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21720 :: " string "
+
+
+\<comment> \<open>\<open>val _s2159_ : string -> maybe ((mword ty3 * mword ty6))\<close>\<close>
+
+definition s2159 :: " string \<Rightarrow>((3)Word.word*(6)Word.word)option " where
+ " s2159 s21600 = (
+ (let s21610 = s21600 in
+ if ((string_startswith s21610 (''c.srli''))) then
+ (case ((string_drop s21610 ((string_length (''c.srli''))))) of
+ s21620 =>
+ (case ((spc_matches_prefix0 s21620)) of
+ Some ((_, s21630)) =>
+ (case ((string_drop s21620 s21630)) of
+ s21640 =>
+ (case ((creg_name_matches_prefix s21640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s21650)) =>
+ (case ((string_drop s21640 s21650)) of
+ s21660 =>
+ (case ((sep_matches_prefix s21660)) of
+ Some ((_, s21670)) =>
+ (case ((string_drop s21660 s21670)) of
+ s21680 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21680 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s21690)) =>
+ (let p00 = (string_drop s21680 s21690) in
+ if (((p00 = ('''')))) then Some (rsd, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21600 :: " string "
+
+
+\<comment> \<open>\<open>val _s2147_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2147 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2147 s21480 = (
+ (let s21490 = s21480 in
+ if ((string_startswith s21490 (''c.lui''))) then
+ (case ((string_drop s21490 ((string_length (''c.lui''))))) of
+ s21500 =>
+ (case ((spc_matches_prefix0 s21500)) of
+ Some ((_, s21510)) =>
+ (case ((string_drop s21500 s21510)) of
+ s21520 =>
+ (case ((reg_name_matches_prefix s21520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s21530)) =>
+ (case ((string_drop s21520 s21530)) of
+ s21540 =>
+ (case ((sep_matches_prefix s21540)) of
+ Some ((_, s21550)) =>
+ (case ((string_drop s21540 s21550)) of
+ s21560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21560 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21570)) =>
+ (let p00 = (string_drop s21560 s21570) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2139_ : string -> maybe (mword ty6)\<close>\<close>
+
+definition s2139 :: " string \<Rightarrow>((6)Word.word)option " where
+ " s2139 s21400 = (
+ (let s21410 = s21400 in
+ if ((string_startswith s21410 (''c.addi16sp''))) then
+ (case ((string_drop s21410 ((string_length (''c.addi16sp''))))) of
+ s21420 =>
+ (case ((spc_matches_prefix0 s21420)) of
+ Some ((_, s21430)) =>
+ (case ((string_drop s21420 s21430)) of
+ s21440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21440 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21450)) =>
+ (let p00 = (string_drop s21440 s21450) in
+ if (((p00 = ('''')))) then Some imm else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21400 :: " string "
+
+
+\<comment> \<open>\<open>val _s2127_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2127 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2127 s21280 = (
+ (let s21290 = s21280 in
+ if ((string_startswith s21290 (''c.li''))) then
+ (case ((string_drop s21290 ((string_length (''c.li''))))) of
+ s21300 =>
+ (case ((spc_matches_prefix0 s21300)) of
+ Some ((_, s21310)) =>
+ (case ((string_drop s21300 s21310)) of
+ s21320 =>
+ (case ((reg_name_matches_prefix s21320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s21330)) =>
+ (case ((string_drop s21320 s21330)) of
+ s21340 =>
+ (case ((sep_matches_prefix s21340)) of
+ Some ((_, s21350)) =>
+ (case ((string_drop s21340 s21350)) of
+ s21360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21360 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21370)) =>
+ (let p00 = (string_drop s21360 s21370) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21280 :: " string "
+
+
+\<comment> \<open>\<open>val _s2115_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2115 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2115 s21160 = (
+ (let s21170 = s21160 in
+ if ((string_startswith s21170 (''c.addiw''))) then
+ (case ((string_drop s21170 ((string_length (''c.addiw''))))) of
+ s21180 =>
+ (case ((spc_matches_prefix0 s21180)) of
+ Some ((_, s21190)) =>
+ (case ((string_drop s21180 s21190)) of
+ s21200 =>
+ (case ((reg_name_matches_prefix s21200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s21210)) =>
+ (case ((string_drop s21200 s21210)) of
+ s21220 =>
+ (case ((sep_matches_prefix s21220)) of
+ Some ((_, s21230)) =>
+ (case ((string_drop s21220 s21230)) of
+ s21240 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21240 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s21250)) =>
+ (let p00 = (string_drop s21240 s21250) in
+ if (((p00 = ('''')))) then Some (rsd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2107_ : string -> maybe (mword ty11)\<close>\<close>
+
+definition s2107 :: " string \<Rightarrow>((11)Word.word)option " where
+ " s2107 s21080 = (
+ (let s21090 = s21080 in
+ if ((string_startswith s21090 (''c.jal''))) then
+ (case ((string_drop s21090 ((string_length (''c.jal''))))) of
+ s21100 =>
+ (case ((spc_matches_prefix0 s21100)) of
+ Some ((_, s21110)) =>
+ (case ((string_drop s21100 s21110)) of
+ s21120 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21120 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__814, s21130)) =>
+ if (((((subrange_vec_dec v__814 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__814
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__814
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let p00 = (string_drop s21120 s21130) in
+ if (((p00 = ('''')))) then Some imm else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s21080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2095_ : string -> maybe ((mword ty5 * mword ty6))\<close>\<close>
+
+definition s2095 :: " string \<Rightarrow>((5)Word.word*(6)Word.word)option " where
+ " s2095 s20960 = (
+ (let s20970 = s20960 in
+ if ((string_startswith s20970 (''c.addi''))) then
+ (case ((string_drop s20970 ((string_length (''c.addi''))))) of
+ s20980 =>
+ (case ((spc_matches_prefix0 s20980)) of
+ Some ((_, s20990)) =>
+ (case ((string_drop s20980 s20990)) of
+ s21000 =>
+ (case ((reg_name_matches_prefix s21000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s21010)) =>
+ (case ((string_drop s21000 s21010)) of
+ s21020 =>
+ (case ((sep_matches_prefix s21020)) of
+ Some ((_, s21030)) =>
+ (case ((string_drop s21020 s21030)) of
+ s21040 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s21040 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s21050)) =>
+ (let p00 = (string_drop s21040 s21050) in
+ if (((p00 = ('''')))) then Some (rsd, nzi) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2079_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2079 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2079 s20800 = (
+ (let s20810 = s20800 in
+ if ((string_startswith s20810 (''c.sd''))) then
+ (case ((string_drop s20810 ((string_length (''c.sd''))))) of
+ s20820 =>
+ (case ((spc_matches_prefix0 s20820)) of
+ Some ((_, s20830)) =>
+ (case ((string_drop s20820 s20830)) of
+ s20840 =>
+ (case ((creg_name_matches_prefix s20840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s20850)) =>
+ (case ((string_drop s20840 s20850)) of
+ s20860 =>
+ (case ((sep_matches_prefix s20860)) of
+ Some ((_, s20870)) =>
+ (case ((string_drop s20860 s20870)) of
+ s20880 =>
+ (case ((creg_name_matches_prefix s20880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s20890)) =>
+ (case ((string_drop s20880 s20890)) of
+ s20900 =>
+ (case ((sep_matches_prefix s20900)) of
+ Some ((_, s20910)) =>
+ (case ((string_drop s20900 s20910)) of
+ s20920 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20920 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__816, s20930)) =>
+ if (((((subrange_vec_dec v__816 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__816 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__816 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20920 s20930) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20800 :: " string "
+
+
+\<comment> \<open>\<open>val _s2063_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2063 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2063 s20640 = (
+ (let s20650 = s20640 in
+ if ((string_startswith s20650 (''c.sw''))) then
+ (case ((string_drop s20650 ((string_length (''c.sw''))))) of
+ s20660 =>
+ (case ((spc_matches_prefix0 s20660)) of
+ Some ((_, s20670)) =>
+ (case ((string_drop s20660 s20670)) of
+ s20680 =>
+ (case ((creg_name_matches_prefix s20680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s20690)) =>
+ (case ((string_drop s20680 s20690)) of
+ s20700 =>
+ (case ((sep_matches_prefix s20700)) of
+ Some ((_, s20710)) =>
+ (case ((string_drop s20700 s20710)) of
+ s20720 =>
+ (case ((creg_name_matches_prefix s20720 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s20730)) =>
+ (case ((string_drop s20720 s20730)) of
+ s20740 =>
+ (case ((sep_matches_prefix s20740)) of
+ Some ((_, s20750)) =>
+ (case ((string_drop s20740 s20750)) of
+ s20760 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20760 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__818, s20770)) =>
+ if (((((subrange_vec_dec v__818 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__818 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__818 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20760 s20770) in
+ if (((p00 = ('''')))) then Some (rsc1, rsc2, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20640 :: " string "
+
+
+\<comment> \<open>\<open>val _s2047_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2047 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2047 s20480 = (
+ (let s20490 = s20480 in
+ if ((string_startswith s20490 (''c.ld''))) then
+ (case ((string_drop s20490 ((string_length (''c.ld''))))) of
+ s20500 =>
+ (case ((spc_matches_prefix0 s20500)) of
+ Some ((_, s20510)) =>
+ (case ((string_drop s20500 s20510)) of
+ s20520 =>
+ (case ((creg_name_matches_prefix s20520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20530)) =>
+ (case ((string_drop s20520 s20530)) of
+ s20540 =>
+ (case ((sep_matches_prefix s20540)) of
+ Some ((_, s20550)) =>
+ (case ((string_drop s20540 s20550)) of
+ s20560 =>
+ (case ((creg_name_matches_prefix s20560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s20570)) =>
+ (case ((string_drop s20560 s20570)) of
+ s20580 =>
+ (case ((sep_matches_prefix s20580)) of
+ Some ((_, s20590)) =>
+ (case ((string_drop s20580 s20590)) of
+ s20600 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20600 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__820, s20610)) =>
+ if (((((subrange_vec_dec v__820 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__820 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__820 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20600 s20610) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2031_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5))\<close>\<close>
+
+definition s2031 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word)option " where
+ " s2031 s20320 = (
+ (let s20330 = s20320 in
+ if ((string_startswith s20330 (''c.lw''))) then
+ (case ((string_drop s20330 ((string_length (''c.lw''))))) of
+ s20340 =>
+ (case ((spc_matches_prefix0 s20340)) of
+ Some ((_, s20350)) =>
+ (case ((string_drop s20340 s20350)) of
+ s20360 =>
+ (case ((creg_name_matches_prefix s20360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20370)) =>
+ (case ((string_drop s20360 s20370)) of
+ s20380 =>
+ (case ((sep_matches_prefix s20380)) of
+ Some ((_, s20390)) =>
+ (case ((string_drop s20380 s20390)) of
+ s20400 =>
+ (case ((creg_name_matches_prefix s20400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s20410)) =>
+ (case ((string_drop s20400 s20410)) of
+ s20420 =>
+ (case ((sep_matches_prefix s20420)) of
+ Some ((_, s20430)) =>
+ (case ((string_drop s20420 s20430)) of
+ s20440 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20440 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__822, s20450)) =>
+ if (((((subrange_vec_dec v__822 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__822 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__822 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let p00 = (string_drop s20440 s20450) in
+ if (((p00 = ('''')))) then Some (rdc, rsc, uimm) else None))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2019_ : string -> maybe ((mword ty3 * mword ty8))\<close>\<close>
+
+definition s2019 :: " string \<Rightarrow>((3)Word.word*(8)Word.word)option " where
+ " s2019 s20200 = (
+ (let s20210 = s20200 in
+ if ((string_startswith s20210 (''c.addi4spn''))) then
+ (case ((string_drop s20210 ((string_length (''c.addi4spn''))))) of
+ s20220 =>
+ (case ((spc_matches_prefix0 s20220)) of
+ Some ((_, s20230)) =>
+ (case ((string_drop s20220 s20230)) of
+ s20240 =>
+ (case ((creg_name_matches_prefix s20240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s20250)) =>
+ (case ((string_drop s20240 s20250)) of
+ s20260 =>
+ (case ((sep_matches_prefix s20260)) of
+ Some ((_, s20270)) =>
+ (case ((string_drop s20260 s20270)) of
+ s20280 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s20280 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__824, s20290)) =>
+ if (((((subrange_vec_dec v__824 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__824 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__824 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let p00 = (string_drop s20280 s20290) in
+ if (((p00 = ('''')))) then Some (rdc, nzimm) else None))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s20200 :: " string "
+
+
+\<comment> \<open>\<open>val _s1995_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1995 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1995 s19970 = (
+ (case ((amo_mnemonic_matches_prefix s19970)) of
+ Some ((op1, s19980)) =>
+ (let s19990 = (string_drop s19970 s19980) in
+ if ((string_startswith s19990 (''.''))) then
+ (case ((string_drop s19990 ((string_length (''.''))))) of
+ s20000 =>
+ (case ((size_mnemonic_matches_prefix s20000)) of
+ Some ((width, s20010)) =>
+ (case ((string_drop s20000 s20010)) of
+ s20020 =>
+ (case ((maybe_aq_matches_prefix s20020)) of
+ Some ((aq, s20030)) =>
+ (case ((string_drop s20020 s20030)) of
+ s20040 =>
+ (case ((maybe_rl_matches_prefix s20040)) of
+ Some ((rl, s20050)) =>
+ (case ((string_drop s20040 s20050)) of
+ s20060 =>
+ (case ((spc_matches_prefix0 s20060)) of
+ Some ((_, s20070)) =>
+ (case ((string_drop s20060 s20070)) of
+ s20080 =>
+ (case ((reg_name_matches_prefix s20080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s20090)) =>
+ (case ((string_drop s20080 s20090)) of
+ s20100 =>
+ (case ((sep_matches_prefix s20100)) of
+ Some ((_, s20110)) =>
+ (case ((string_drop s20100 s20110)) of
+ s20120 =>
+ (case ((reg_name_matches_prefix s20120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s20130)) =>
+ (case ((string_drop s20120 s20130)) of
+ s20140 =>
+ (case ((sep_matches_prefix s20140)) of
+ Some ((_, s20150)) =>
+ (case ((string_drop s20140 s20150)) of
+ s20160 =>
+ (case ((reg_name_matches_prefix s20160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s20170)) =>
+ (let p00 = (string_drop s20160 s20170) in
+ if (((p00 = ('''')))) then Some (op1, width, aq, rl, rd, rs1, rs2) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s19970 :: " string "
+
+
+\<comment> \<open>\<open>val _s1973_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1973 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1973 s19740 = (
+ (let s19750 = s19740 in
+ if ((string_startswith s19750 (''sc.''))) then
+ (case ((string_drop s19750 ((string_length (''sc.''))))) of
+ s19760 =>
+ (case ((size_mnemonic_matches_prefix s19760)) of
+ Some ((size1, s19770)) =>
+ (case ((string_drop s19760 s19770)) of
+ s19780 =>
+ (case ((maybe_aq_matches_prefix s19780)) of
+ Some ((aq, s19790)) =>
+ (case ((string_drop s19780 s19790)) of
+ s19800 =>
+ (case ((maybe_rl_matches_prefix s19800)) of
+ Some ((rl, s19810)) =>
+ (case ((string_drop s19800 s19810)) of
+ s19820 =>
+ (case ((spc_matches_prefix0 s19820)) of
+ Some ((_, s19830)) =>
+ (case ((string_drop s19820 s19830)) of
+ s19840 =>
+ (case ((reg_name_matches_prefix s19840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19850)) =>
+ (case ((string_drop s19840 s19850)) of
+ s19860 =>
+ (case ((sep_matches_prefix s19860)) of
+ Some ((_, s19870)) =>
+ (case ((string_drop s19860 s19870)) of
+ s19880 =>
+ (case ((reg_name_matches_prefix s19880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19890)) =>
+ (case ((string_drop s19880 s19890)) of
+ s19900 =>
+ (case ((sep_matches_prefix s19900)) of
+ Some ((_, s19910)) =>
+ (case ((string_drop s19900 s19910)) of
+ s19920 =>
+ (case ((reg_name_matches_prefix s19920 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19930)) =>
+ (let p00 = (string_drop s19920 s19930) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19740 :: " string "
+
+
+\<comment> \<open>\<open>val _s1955_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1955 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word)option " where
+ " s1955 s19560 = (
+ (let s19570 = s19560 in
+ if ((string_startswith s19570 (''lr.''))) then
+ (case ((string_drop s19570 ((string_length (''lr.''))))) of
+ s19580 =>
+ (case ((size_mnemonic_matches_prefix s19580)) of
+ Some ((size1, s19590)) =>
+ (case ((string_drop s19580 s19590)) of
+ s19600 =>
+ (case ((maybe_aq_matches_prefix s19600)) of
+ Some ((aq, s19610)) =>
+ (case ((string_drop s19600 s19610)) of
+ s19620 =>
+ (case ((maybe_rl_matches_prefix s19620)) of
+ Some ((rl, s19630)) =>
+ (case ((string_drop s19620 s19630)) of
+ s19640 =>
+ (case ((spc_matches_prefix0 s19640)) of
+ Some ((_, s19650)) =>
+ (case ((string_drop s19640 s19650)) of
+ s19660 =>
+ (case ((reg_name_matches_prefix s19660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19670)) =>
+ (case ((string_drop s19660 s19670)) of
+ s19680 =>
+ (case ((sep_matches_prefix s19680)) of
+ Some ((_, s19690)) =>
+ (case ((string_drop s19680 s19690)) of
+ s19700 =>
+ (case ((reg_name_matches_prefix s19700 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19710)) =>
+ (let p00 = (string_drop s19700 s19710) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rd, rs1) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19560 :: " string "
+
+
+\<comment> \<open>\<open>val _s1943_ : string -> maybe ((mword ty5 * mword ty5))\<close>\<close>
+
+definition s1943 :: " string \<Rightarrow>((5)Word.word*(5)Word.word)option " where
+ " s1943 s19440 = (
+ (let s19450 = s19440 in
+ if ((string_startswith s19450 (''sfence.vma''))) then
+ (case ((string_drop s19450 ((string_length (''sfence.vma''))))) of
+ s19460 =>
+ (case ((spc_matches_prefix0 s19460)) of
+ Some ((_, s19470)) =>
+ (case ((string_drop s19460 s19470)) of
+ s19480 =>
+ (case ((reg_name_matches_prefix s19480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19490)) =>
+ (case ((string_drop s19480 s19490)) of
+ s19500 =>
+ (case ((sep_matches_prefix s19500)) of
+ Some ((_, s19510)) =>
+ (case ((string_drop s19500 s19510)) of
+ s19520 =>
+ (case ((reg_name_matches_prefix s19520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19530)) =>
+ (let p00 = (string_drop s19520 s19530) in
+ if (((p00 = ('''')))) then Some (rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19440 :: " string "
+
+
+\<comment> \<open>\<open>val _s1931_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1931 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1931 s19320 = (
+ (let s19330 = s19320 in
+ if ((string_startswith s19330 (''fence.tso''))) then
+ (case ((string_drop s19330 ((string_length (''fence.tso''))))) of
+ s19340 =>
+ (case ((spc_matches_prefix0 s19340)) of
+ Some ((_, s19350)) =>
+ (case ((string_drop s19340 s19350)) of
+ s19360 =>
+ (case ((fence_bits_matches_prefix s19360 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s19370)) =>
+ (case ((string_drop s19360 s19370)) of
+ s19380 =>
+ (case ((sep_matches_prefix s19380)) of
+ Some ((_, s19390)) =>
+ (case ((string_drop s19380 s19390)) of
+ s19400 =>
+ (case ((fence_bits_matches_prefix s19400 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s19410)) =>
+ (let p00 = (string_drop s19400 s19410) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19320 :: " string "
+
+
+\<comment> \<open>\<open>val _s1919_ : string -> maybe ((mword ty4 * mword ty4))\<close>\<close>
+
+definition s1919 :: " string \<Rightarrow>((4)Word.word*(4)Word.word)option " where
+ " s1919 s19200 = (
+ (let s19210 = s19200 in
+ if ((string_startswith s19210 (''fence''))) then
+ (case ((string_drop s19210 ((string_length (''fence''))))) of
+ s19220 =>
+ (case ((spc_matches_prefix0 s19220)) of
+ Some ((_, s19230)) =>
+ (case ((string_drop s19220 s19230)) of
+ s19240 =>
+ (case ((fence_bits_matches_prefix s19240 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s19250)) =>
+ (case ((string_drop s19240 s19250)) of
+ s19260 =>
+ (case ((sep_matches_prefix s19260)) of
+ Some ((_, s19270)) =>
+ (case ((string_drop s19260 s19270)) of
+ s19280 =>
+ (case ((fence_bits_matches_prefix s19280 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s19290)) =>
+ (let p00 = (string_drop s19280 s19290) in
+ if (((p00 = ('''')))) then Some (pred, succ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s19200 :: " string "
+
+
+\<comment> \<open>\<open>val _s1902_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1902 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1902 s19040 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s19040)) of
+ Some ((op1, s19050)) =>
+ (case ((string_drop s19040 s19050)) of
+ s19060 =>
+ (case ((spc_matches_prefix0 s19060)) of
+ Some ((_, s19070)) =>
+ (case ((string_drop s19060 s19070)) of
+ s19080 =>
+ (case ((reg_name_matches_prefix s19080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s19090)) =>
+ (case ((string_drop s19080 s19090)) of
+ s19100 =>
+ (case ((sep_matches_prefix s19100)) of
+ Some ((_, s19110)) =>
+ (case ((string_drop s19100 s19110)) of
+ s19120 =>
+ (case ((reg_name_matches_prefix s19120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s19130)) =>
+ (case ((string_drop s19120 s19130)) of
+ s19140 =>
+ (case ((sep_matches_prefix s19140)) of
+ Some ((_, s19150)) =>
+ (case ((string_drop s19140 s19150)) of
+ s19160 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s19160 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s19170)) =>
+ (let p00 = (string_drop s19160 s19170) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s19040 :: " string "
+
+
+\<comment> \<open>\<open>val _s1885_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1885 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1885 s18870 = (
+ (case ((rtypew_mnemonic_matches_prefix s18870)) of
+ Some ((op1, s18880)) =>
+ (case ((string_drop s18870 s18880)) of
+ s18890 =>
+ (case ((spc_matches_prefix0 s18890)) of
+ Some ((_, s18900)) =>
+ (case ((string_drop s18890 s18900)) of
+ s18910 =>
+ (case ((reg_name_matches_prefix s18910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18920)) =>
+ (case ((string_drop s18910 s18920)) of
+ s18930 =>
+ (case ((sep_matches_prefix s18930)) of
+ Some ((_, s18940)) =>
+ (case ((string_drop s18930 s18940)) of
+ s18950 =>
+ (case ((reg_name_matches_prefix s18950 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18960)) =>
+ (case ((string_drop s18950 s18960)) of
+ s18970 =>
+ (case ((sep_matches_prefix s18970)) of
+ Some ((_, s18980)) =>
+ (case ((string_drop s18970 s18980)) of
+ s18990 =>
+ (case ((reg_name_matches_prefix s18990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s19000)) =>
+ (let p00 = (string_drop s18990 s19000) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s18870 :: " string "
+
+
+\<comment> \<open>\<open>val _s1868_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1868 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1868 s18700 = (
+ (case ((shiftw_mnemonic_matches_prefix s18700)) of
+ Some ((op1, s18710)) =>
+ (case ((string_drop s18700 s18710)) of
+ s18720 =>
+ (case ((spc_matches_prefix0 s18720)) of
+ Some ((_, s18730)) =>
+ (case ((string_drop s18720 s18730)) of
+ s18740 =>
+ (case ((reg_name_matches_prefix s18740 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18750)) =>
+ (case ((string_drop s18740 s18750)) of
+ s18760 =>
+ (case ((sep_matches_prefix s18760)) of
+ Some ((_, s18770)) =>
+ (case ((string_drop s18760 s18770)) of
+ s18780 =>
+ (case ((reg_name_matches_prefix s18780 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18790)) =>
+ (case ((string_drop s18780 s18790)) of
+ s18800 =>
+ (case ((sep_matches_prefix s18800)) of
+ Some ((_, s18810)) =>
+ (case ((string_drop s18800 s18810)) of
+ s18820 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18820 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s18830)) =>
+ (let p00 = (string_drop s18820 s18830) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s18700 :: " string "
+
+
+\<comment> \<open>\<open>val _s1852_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1852 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1852 s18530 = (
+ (let s18540 = s18530 in
+ if ((string_startswith s18540 (''addiw''))) then
+ (case ((string_drop s18540 ((string_length (''addiw''))))) of
+ s18550 =>
+ (case ((spc_matches_prefix0 s18550)) of
+ Some ((_, s18560)) =>
+ (case ((string_drop s18550 s18560)) of
+ s18570 =>
+ (case ((reg_name_matches_prefix s18570 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18580)) =>
+ (case ((string_drop s18570 s18580)) of
+ s18590 =>
+ (case ((sep_matches_prefix s18590)) of
+ Some ((_, s18600)) =>
+ (case ((string_drop s18590 s18600)) of
+ s18610 =>
+ (case ((reg_name_matches_prefix s18610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18620)) =>
+ (case ((string_drop s18610 s18620)) of
+ s18630 =>
+ (case ((sep_matches_prefix s18630)) of
+ Some ((_, s18640)) =>
+ (case ((string_drop s18630 s18640)) of
+ s18650 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18650 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18660)) =>
+ (let p00 = (string_drop s18650 s18660) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s18530 :: " string "
+
+
+\<comment> \<open>\<open>val _s1824_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s1824 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s1824 s18250 = (
+ (let s18260 = s18250 in
+ if ((string_startswith s18260 (''s''))) then
+ (case ((string_drop s18260 ((string_length (''s''))))) of
+ s18270 =>
+ (case ((size_mnemonic_matches_prefix s18270)) of
+ Some ((size1, s18280)) =>
+ (case ((string_drop s18270 s18280)) of
+ s18290 =>
+ (case ((maybe_aq_matches_prefix s18290)) of
+ Some ((aq, s18300)) =>
+ (case ((string_drop s18290 s18300)) of
+ s18310 =>
+ (case ((maybe_rl_matches_prefix s18310)) of
+ Some ((rl, s18320)) =>
+ (case ((string_drop s18310 s18320)) of
+ s18330 =>
+ (case ((spc_matches_prefix0 s18330)) of
+ Some ((_, s18340)) =>
+ (case ((string_drop s18330 s18340)) of
+ s18350 =>
+ (case ((reg_name_matches_prefix s18350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s18360)) =>
+ (case ((string_drop s18350 s18360)) of
+ s18370 =>
+ (case ((sep_matches_prefix s18370)) of
+ Some ((_, s18380)) =>
+ (case ((string_drop s18370 s18380)) of
+ s18390 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18390 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18400)) =>
+ (case ((string_drop s18390 s18400)) of
+ s18410 =>
+ (case ((opt_spc_matches_prefix0 s18410)) of
+ Some ((_, s18420)) =>
+ (let s18430 = (string_drop s18410 s18420) in
+ if ((string_startswith s18430 (''(''))) then
+ (case ((string_drop s18430 ((string_length (''(''))))) of
+ s18440 =>
+ (case ((opt_spc_matches_prefix0 s18440)) of
+ Some ((_, s18450)) =>
+ (case ((string_drop s18440 s18450)) of
+ s18460 =>
+ (case ((reg_name_matches_prefix s18460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18470)) =>
+ (case ((string_drop s18460 s18470)) of
+ s18480 =>
+ (case ((opt_spc_matches_prefix0 s18480)) of
+ Some ((_, s18490)) =>
+ (let s18500 = (string_drop s18480 s18490) in
+ if ((string_startswith s18500 ('')''))) then
+ (let p00 = (string_drop s18500 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then Some (size1, aq, rl, rs2, imm, rs1) else
+ None) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s18250 :: " string "
+
+
+\<comment> \<open>\<open>val _s1794_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5))\<close>\<close>
+
+definition s1794 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word)option " where
+ " s1794 s17950 = (
+ (let s17960 = s17950 in
+ if ((string_startswith s17960 (''l''))) then
+ (case ((string_drop s17960 ((string_length (''l''))))) of
+ s17970 =>
+ (case ((size_mnemonic_matches_prefix s17970)) of
+ Some ((size1, s17980)) =>
+ (case ((string_drop s17970 s17980)) of
+ s17990 =>
+ (case ((maybe_u_matches_prefix s17990)) of
+ Some ((is_unsigned, s18000)) =>
+ (case ((string_drop s17990 s18000)) of
+ s18010 =>
+ (case ((maybe_aq_matches_prefix s18010)) of
+ Some ((aq, s18020)) =>
+ (case ((string_drop s18010 s18020)) of
+ s18030 =>
+ (case ((maybe_rl_matches_prefix s18030)) of
+ Some ((rl, s18040)) =>
+ (case ((string_drop s18030 s18040)) of
+ s18050 =>
+ (case ((spc_matches_prefix0 s18050)) of
+ Some ((_, s18060)) =>
+ (case ((string_drop s18050 s18060)) of
+ s18070 =>
+ (case ((reg_name_matches_prefix s18070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s18080)) =>
+ (case ((string_drop s18070 s18080)) of
+ s18090 =>
+ (case ((sep_matches_prefix s18090)) of
+ Some ((_, s18100)) =>
+ (case ((string_drop s18090 s18100)) of
+ s18110 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s18110 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s18120)) =>
+ (case ((string_drop s18110 s18120)) of
+ s18130 =>
+ (case ((opt_spc_matches_prefix0 s18130)) of
+ Some ((_, s18140)) =>
+ (let s18150 = (string_drop s18130 s18140) in
+ if ((string_startswith s18150 (''(''))) then
+ (case ((string_drop s18150 ((string_length (''(''))))) of
+ s18160 =>
+ (case ((opt_spc_matches_prefix0 s18160)) of
+ Some ((_, s18170)) =>
+ (case ((string_drop s18160 s18170)) of
+ s18180 =>
+ (case ((reg_name_matches_prefix s18180 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s18190)) =>
+ (case ((string_drop s18180 s18190)) of
+ s18200 =>
+ (case ((opt_spc_matches_prefix0 s18200)) of
+ Some ((_, s18210)) =>
+ (let s18220 = (string_drop s18200 s18210) in
+ if ((string_startswith s18220 ('')''))) then
+ (let p00 = (string_drop s18220 ((string_length ('')'')))) in
+ if (((p00 = ('''')))) then
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1) else None) else
+ None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s17950 :: " string "
+
+
+\<comment> \<open>\<open>val _s1777_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5))\<close>\<close>
+
+definition s1777 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word)option " where
+ " s1777 s17790 = (
+ (case ((rtype_mnemonic_matches_prefix s17790)) of
+ Some ((op1, s17800)) =>
+ (case ((string_drop s17790 s17800)) of
+ s17810 =>
+ (case ((spc_matches_prefix0 s17810)) of
+ Some ((_, s17820)) =>
+ (case ((string_drop s17810 s17820)) of
+ s17830 =>
+ (case ((reg_name_matches_prefix s17830 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17840)) =>
+ (case ((string_drop s17830 s17840)) of
+ s17850 =>
+ (case ((sep_matches_prefix s17850)) of
+ Some ((_, s17860)) =>
+ (case ((string_drop s17850 s17860)) of
+ s17870 =>
+ (case ((reg_name_matches_prefix s17870 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17880)) =>
+ (case ((string_drop s17870 s17880)) of
+ s17890 =>
+ (case ((sep_matches_prefix s17890)) of
+ Some ((_, s17900)) =>
+ (case ((string_drop s17890 s17900)) of
+ s17910 =>
+ (case ((reg_name_matches_prefix s17910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s17920)) =>
+ (let p00 = (string_drop s17910 s17920) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, rs2) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17790 :: " string "
+
+
+\<comment> \<open>\<open>val _s1760_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6))\<close>\<close>
+
+definition s1760 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word)option " where
+ " s1760 s17620 = (
+ (case ((shiftiop_mnemonic_matches_prefix s17620)) of
+ Some ((op1, s17630)) =>
+ (case ((string_drop s17620 s17630)) of
+ s17640 =>
+ (case ((spc_matches_prefix0 s17640)) of
+ Some ((_, s17650)) =>
+ (case ((string_drop s17640 s17650)) of
+ s17660 =>
+ (case ((reg_name_matches_prefix s17660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17670)) =>
+ (case ((string_drop s17660 s17670)) of
+ s17680 =>
+ (case ((sep_matches_prefix s17680)) of
+ Some ((_, s17690)) =>
+ (case ((string_drop s17680 s17690)) of
+ s17700 =>
+ (case ((reg_name_matches_prefix s17700 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17710)) =>
+ (case ((string_drop s17700 s17710)) of
+ s17720 =>
+ (case ((sep_matches_prefix s17720)) of
+ Some ((_, s17730)) =>
+ (case ((string_drop s17720 s17730)) of
+ s17740 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17740 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s17750)) =>
+ (let p00 = (string_drop s17740 s17750) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, shamt) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17620 :: " string "
+
+
+\<comment> \<open>\<open>val _s1743_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1743 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1743 s17450 = (
+ (case ((itype_mnemonic_matches_prefix s17450)) of
+ Some ((op1, s17460)) =>
+ (case ((string_drop s17450 s17460)) of
+ s17470 =>
+ (case ((spc_matches_prefix0 s17470)) of
+ Some ((_, s17480)) =>
+ (case ((string_drop s17470 s17480)) of
+ s17490 =>
+ (case ((reg_name_matches_prefix s17490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17500)) =>
+ (case ((string_drop s17490 s17500)) of
+ s17510 =>
+ (case ((sep_matches_prefix s17510)) of
+ Some ((_, s17520)) =>
+ (case ((string_drop s17510 s17520)) of
+ s17530 =>
+ (case ((reg_name_matches_prefix s17530 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17540)) =>
+ (case ((string_drop s17530 s17540)) of
+ s17550 =>
+ (case ((sep_matches_prefix s17550)) of
+ Some ((_, s17560)) =>
+ (case ((string_drop s17550 s17560)) of
+ s17570 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17570 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s17580)) =>
+ (let p00 = (string_drop s17570 s17580) in
+ if (((p00 = ('''')))) then Some (op1, rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17450 :: " string "
+
+
+\<comment> \<open>\<open>val _s1726_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13))\<close>\<close>
+
+definition s1726 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word)option " where
+ " s1726 s17280 = (
+ (case ((btype_mnemonic_matches_prefix s17280)) of
+ Some ((op1, s17290)) =>
+ (case ((string_drop s17280 s17290)) of
+ s17300 =>
+ (case ((spc_matches_prefix0 s17300)) of
+ Some ((_, s17310)) =>
+ (case ((string_drop s17300 s17310)) of
+ s17320 =>
+ (case ((reg_name_matches_prefix s17320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17330)) =>
+ (case ((string_drop s17320 s17330)) of
+ s17340 =>
+ (case ((sep_matches_prefix s17340)) of
+ Some ((_, s17350)) =>
+ (case ((string_drop s17340 s17350)) of
+ s17360 =>
+ (case ((reg_name_matches_prefix s17360 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s17370)) =>
+ (case ((string_drop s17360 s17370)) of
+ s17380 =>
+ (case ((sep_matches_prefix s17380)) of
+ Some ((_, s17390)) =>
+ (case ((string_drop s17380 s17390)) of
+ s17400 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17400 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s17410)) =>
+ (let p00 = (string_drop s17400 s17410) in
+ if (((p00 = ('''')))) then Some (op1, rs1, rs2, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s17280 :: " string "
+
+
+\<comment> \<open>\<open>val _s1710_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12))\<close>\<close>
+
+definition s1710 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word)option " where
+ " s1710 s17110 = (
+ (let s17120 = s17110 in
+ if ((string_startswith s17120 (''jalr''))) then
+ (case ((string_drop s17120 ((string_length (''jalr''))))) of
+ s17130 =>
+ (case ((spc_matches_prefix0 s17130)) of
+ Some ((_, s17140)) =>
+ (case ((string_drop s17130 s17140)) of
+ s17150 =>
+ (case ((reg_name_matches_prefix s17150 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17160)) =>
+ (case ((string_drop s17150 s17160)) of
+ s17170 =>
+ (case ((sep_matches_prefix s17170)) of
+ Some ((_, s17180)) =>
+ (case ((string_drop s17170 s17180)) of
+ s17190 =>
+ (case ((reg_name_matches_prefix s17190 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s17200)) =>
+ (case ((string_drop s17190 s17200)) of
+ s17210 =>
+ (case ((sep_matches_prefix s17210)) of
+ Some ((_, s17220)) =>
+ (case ((string_drop s17210 s17220)) of
+ s17230 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17230 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s17240)) =>
+ (let p00 = (string_drop s17230 s17240) in
+ if (((p00 = ('''')))) then Some (rd, rs1, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s17110 :: " string "
+
+
+\<comment> \<open>\<open>val _s1698_ : string -> maybe ((mword ty5 * mword ty21))\<close>\<close>
+
+definition s1698 :: " string \<Rightarrow>((5)Word.word*(21)Word.word)option " where
+ " s1698 s16990 = (
+ (let s17000 = s16990 in
+ if ((string_startswith s17000 (''jal''))) then
+ (case ((string_drop s17000 ((string_length (''jal''))))) of
+ s17010 =>
+ (case ((spc_matches_prefix0 s17010)) of
+ Some ((_, s17020)) =>
+ (case ((string_drop s17010 s17020)) of
+ s17030 =>
+ (case ((reg_name_matches_prefix s17030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s17040)) =>
+ (case ((string_drop s17030 s17040)) of
+ s17050 =>
+ (case ((sep_matches_prefix s17050)) of
+ Some ((_, s17060)) =>
+ (case ((string_drop s17050 s17060)) of
+ s17070 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s17070 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s17080)) =>
+ (let p00 = (string_drop s17070 s17080) in
+ if (((p00 = ('''')))) then Some (rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s16990 :: " string "
+
+
+\<comment> \<open>\<open>val _s1685_ : string -> maybe ((uop * mword ty5 * mword ty20))\<close>\<close>
+
+definition s1685 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word)option " where
+ " s1685 s16870 = (
+ (case ((utype_mnemonic_matches_prefix s16870)) of
+ Some ((op1, s16880)) =>
+ (case ((string_drop s16870 s16880)) of
+ s16890 =>
+ (case ((spc_matches_prefix0 s16890)) of
+ Some ((_, s16900)) =>
+ (case ((string_drop s16890 s16900)) of
+ s16910 =>
+ (case ((reg_name_matches_prefix s16910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s16920)) =>
+ (case ((string_drop s16910 s16920)) of
+ s16930 =>
+ (case ((sep_matches_prefix s16930)) of
+ Some ((_, s16940)) =>
+ (case ((string_drop s16930 s16940)) of
+ s16950 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s16950 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s16960)) =>
+ (let p00 = (string_drop s16950 s16960) in
+ if (((p00 = ('''')))) then Some (op1, rd, imm) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s16870 :: " string "
+
+
+definition assembly_backwards_matches :: " string \<Rightarrow> bool " where
+ " assembly_backwards_matches arg1 = (
+ (let s16970 = arg1 in
+ if ((case ((s1685 s16970 :: ((uop * 5 Word.word * 20 Word.word))option)) of
+ Some ((op1, rd, imm)) => True
+ | _ => False
+ )) then (case (s1685 s16970 :: (( uop * 5 Word.word * 20 Word.word)) option) of
+ (Some ((op1, rd, imm))) =>
+ True
+ )
+ else if ((case ((s1698 s16970 :: (( 5 Word.word * 21 Word.word))option)) of
+ Some ((rd, imm)) => True
+ | _ => False
+ )) then (case (s1698 s16970 :: (( 5 Word.word * 21 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s1710 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => True
+ | _ => False
+ )) then (case (s1710 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1726 s16970 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word))option)) of
+ Some ((op1, rs1, rs2, imm)) => True
+ | _ => False
+ )) then (case
+ (s1726 s16970 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word)) option) of
+ (Some ((op1, rs1, rs2, imm))) =>
+ True
+ )
+ else if ((case ((s1743 s16970 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, imm)) => True
+ | _ => False
+ )) then (case
+ (s1743 s16970 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1760 s16970 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => True
+ | _ => False
+ )) then (case
+ (s1760 s16970 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1777 s16970 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1777 s16970 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1794 s16970
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1794 s16970
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1))) =>
+ True
+ )
+ else if ((case ((s1824 s16970
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1824 s16970 :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1))) =>
+ True
+ )
+ else if ((case ((s1852 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((rd, rs1, imm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s1852 s16970 :: (( 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((rd, rs1, imm))) =>
+ True
+ )
+ else if ((case ((s1868 s16970 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1868 s16970 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1885 s16970 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1885 s16970 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1902 s16970 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, rd, rs1, shamt)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s1902 s16970 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, rd, rs1, shamt))) =>
+ True
+ )
+ else if ((case ((s1919 s16970 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1919 s16970 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ True
+ )
+ else if ((case ((s1931 s16970 :: (( 4 Word.word * 4 Word.word))option)) of
+ Some ((pred, succ)) => True
+ | _ => False
+ )) then (case (s1931 s16970 :: (( 4 Word.word * 4 Word.word)) option) of
+ (Some ((pred, succ))) =>
+ True
+ )
+ else if (((s16970 = (''fence.i'')))) then True
+ else if (((s16970 = (''ecall'')))) then True
+ else if (((s16970 = (''mret'')))) then True
+ else if (((s16970 = (''sret'')))) then True
+ else if (((s16970 = (''ebreak'')))) then True
+ else if (((s16970 = (''wfi'')))) then True
+ else if ((case ((s1943 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rs1, rs2)) => True
+ | _ => False
+ )) then (case (s1943 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1955 s16970 :: ((word_width * bool * bool * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1)) => True
+ | _ => False
+ )) then (case
+ (s1955 s16970 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1))) =>
+ True
+ )
+ else if ((case ((s1973 s16970
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1973 s16970 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s1995 s16970
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s1995 s16970
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2))) =>
+ True
+ )
+ else if (((s16970 = (''c.nop'')))) then True
+ else if ((case ((s2019 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rdc, nzimm)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s2019 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rdc, nzimm))) =>
+ True
+ )
+ else if ((case ((s2031 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => True
+ | _ => False
+ )) then (case
+ (s2031 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ True
+ )
+ else if ((case ((s2047 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rdc, rsc, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2047 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rdc, rsc, uimm))) =>
+ True
+ )
+ else if ((case ((s2063 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => True
+ | _ => False
+ )) then (case
+ (s2063 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ True
+ )
+ else if ((case ((s2079 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word))option)) of
+ Some ((rsc1, rsc2, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2079 s16970 :: (( 3 Word.word * 3 Word.word * 5 Word.word)) option) of
+ (Some ((rsc1, rsc2, uimm))) =>
+ True
+ )
+ else if ((case ((s2095 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, nzi)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2095 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, nzi))) =>
+ True
+ )
+ else if ((case ((s2107 s16970 :: ( 11 Word.word)option)) of
+ Some (imm) => ((( 64 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s2107 s16970 :: ( 11 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2115 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2115 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ True
+ )
+ else if ((case ((s2127 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2127 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s2139 s16970 :: ( 6 Word.word)option)) of
+ Some (imm) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2139 s16970 :: ( 6 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2147 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, imm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s2147 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, imm))) =>
+ True
+ )
+ else if ((case ((s2159 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2159 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2171 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s2171 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2183 s16970 :: (( 3 Word.word * 6 Word.word))option)) of
+ Some ((rsd, imm)) => True
+ | _ => False
+ )) then (case (s2183 s16970 :: (( 3 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, imm))) =>
+ True
+ )
+ else if ((case ((s2195 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2195 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2207 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2207 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2219 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2219 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2231 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => True
+ | _ => False
+ )) then (case (s2231 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2243 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2243 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2255 s16970 :: (( 3 Word.word * 3 Word.word))option)) of
+ Some ((rsd, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2255 s16970 :: (( 3 Word.word * 3 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2267 s16970 :: ( 11 Word.word)option)) of
+ Some (imm) => True
+ | _ => False
+ )) then (case (s2267 s16970 :: ( 11 Word.word) option) of (Some (imm)) => True )
+ else if ((case ((s2275 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s2275 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ True
+ )
+ else if ((case ((s2287 s16970 :: (( 3 Word.word * 8 Word.word))option)) of
+ Some ((rs, imm)) => True
+ | _ => False
+ )) then (case (s2287 s16970 :: (( 3 Word.word * 8 Word.word)) option) of
+ (Some ((rs, imm))) =>
+ True
+ )
+ else if ((case ((s2299 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rsd, shamt)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2299 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rsd, shamt))) =>
+ True
+ )
+ else if ((case ((s2311 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2311 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2323 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s2323 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2335 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rd, uimm)) => True
+ | _ => False
+ )) then (case (s2335 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rd, uimm))) =>
+ True
+ )
+ else if ((case ((s2347 s16970 :: (( 5 Word.word * 6 Word.word))option)) of
+ Some ((rs2, uimm)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2347 s16970 :: (( 5 Word.word * 6 Word.word)) option) of
+ (Some ((rs2, uimm))) =>
+ True
+ )
+ else if ((case ((s2359 s16970 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2359 s16970 :: ( 5 Word.word) option) of (Some (rs1)) => True )
+ else if ((case ((s2367 s16970 :: ( 5 Word.word)option)) of
+ Some (rs1) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s2367 s16970 :: ( 5 Word.word) option) of (Some (rs1)) => True )
+ else if ((case ((s2375 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs2)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2375 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs2))) =>
+ True
+ )
+ else if (((s16970 = (''c.ebreak'')))) then True
+ else if ((case ((s2387 s16970 :: (( 5 Word.word * 5 Word.word))option)) of
+ Some ((rsd, rs2)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2387 s16970 :: (( 5 Word.word * 5 Word.word)) option) of
+ (Some ((rsd, rs2))) =>
+ True
+ )
+ else if ((case ((s2399 s16970
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2399 s16970 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2416 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2416 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2434 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => True
+ | _ => False
+ )) then (case
+ (s2434 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2452 s16970 :: (( 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s2452 s16970 :: (( 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2468 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2468 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2487 s16970 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word))option)) of
+ Some ((s, rd, rs1, rs2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2487 s16970 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word)) option) of
+ (Some ((s, rd, rs1, rs2))) =>
+ True
+ )
+ else if ((case ((s2506 s16970 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s2506 s16970 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ True
+ )
+ else if ((case ((s2524 s16970 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word))option)) of
+ Some ((op1, rd, rs1, csr)) => True
+ | _ => False
+ )) then (case
+ (s2524 s16970 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word)) option) of
+ (Some ((op1, rd, rs1, csr))) =>
+ True
+ )
+ else if (((s16970 = (''uret'')))) then True
+ else if ((case ((s2541 s16970 :: ( 32 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s2541 s16970 :: ( 32 Word.word) option) of (Some (s)) => True )
+ else if ((case ((s2549 s16970 :: ( 16 Word.word)option)) of Some (s) => True | _ => False ))
+ then (case (s2549 s16970 :: ( 16 Word.word) option) of (Some (s)) => True )
+ else False))"
+ for arg1 :: " string "
+
+
+\<comment> \<open>\<open>val assembly_matches_prefix : string -> maybe ((ast * ii))\<close>\<close>
+
+\<comment> \<open>\<open>val _s3457_ : string -> maybe ((mword ty16 * string))\<close>\<close>
+
+definition s3457 :: " string \<Rightarrow>((16)Word.word*string)option " where
+ " s3457 s34580 = (
+ (let s34590 = s34580 in
+ if ((string_startswith s34590 (''c.illegal''))) then
+ (case ((string_drop s34590 ((string_length (''c.illegal''))))) of
+ s34600 =>
+ (case ((spc_matches_prefix0 s34600)) of
+ Some ((_, s34610)) =>
+ (case ((string_drop s34600 s34610)) of
+ s34620 =>
+ (case ((hex_bits_16_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34620 :: (( 16 Word.word * ii)) option)) of
+ Some ((s, s34630)) =>
+ (case ((string_drop s34620 s34630)) of s2 => Some (s, s2) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s34580 :: " string "
+
+
+\<comment> \<open>\<open>val _s3449_ : string -> maybe ((mword ty32 * string))\<close>\<close>
+
+definition s3449 :: " string \<Rightarrow>((32)Word.word*string)option " where
+ " s3449 s34500 = (
+ (let s34510 = s34500 in
+ if ((string_startswith s34510 (''illegal''))) then
+ (case ((string_drop s34510 ((string_length (''illegal''))))) of
+ s34520 =>
+ (case ((spc_matches_prefix0 s34520)) of
+ Some ((_, s34530)) =>
+ (case ((string_drop s34520 s34530)) of
+ s34540 =>
+ (case ((hex_bits_32_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34540 :: (( 32 Word.word * ii)) option)) of
+ Some ((s, s34550)) =>
+ (case ((string_drop s34540 s34550)) of s2 => Some (s, s2) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s34500 :: " string "
+
+
+\<comment> \<open>\<open>val _s3445_ : string -> maybe string\<close>\<close>
+
+definition s3445 :: " string \<Rightarrow>(string)option " where
+ " s3445 s34460 = (
+ (let s34470 = s34460 in
+ if ((string_startswith s34470 (''uret''))) then
+ (case ((string_drop s34470 ((string_length (''uret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s34460 :: " string "
+
+
+\<comment> \<open>\<open>val _s3428_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s3428 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s3428 s34300 = (
+ (case ((csr_mnemonic_matches_prefix s34300)) of
+ Some ((op1, s34310)) =>
+ (case ((string_drop s34300 s34310)) of
+ s34320 =>
+ (case ((spc_matches_prefix0 s34320)) of
+ Some ((_, s34330)) =>
+ (case ((string_drop s34320 s34330)) of
+ s34340 =>
+ (case ((reg_name_matches_prefix s34340 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34350)) =>
+ (case ((string_drop s34340 s34350)) of
+ s34360 =>
+ (case ((sep_matches_prefix s34360)) of
+ Some ((_, s34370)) =>
+ (case ((string_drop s34360 s34370)) of
+ s34380 =>
+ (case ((reg_name_matches_prefix s34380 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34390)) =>
+ (case ((string_drop s34380 s34390)) of
+ s34400 =>
+ (case ((sep_matches_prefix s34400)) of
+ Some ((_, s34410)) =>
+ (case ((string_drop s34400 s34410)) of
+ s34420 =>
+ (case ((csr_name_map_matches_prefix s34420
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s34430)) =>
+ (case ((string_drop s34420 s34430)) of
+ s1 => Some (op1, rd, rs1, csr, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s34300 :: " string "
+
+
+\<comment> \<open>\<open>val _s3410_ : string -> maybe ((csrop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s3410 :: " string \<Rightarrow>(csrop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s3410 s34120 = (
+ (case ((csr_mnemonic_matches_prefix s34120)) of
+ Some ((op1, s34130)) =>
+ (let s34140 = (string_drop s34120 s34130) in
+ if ((string_startswith s34140 (''i''))) then
+ (case ((string_drop s34140 ((string_length (''i''))))) of
+ s34150 =>
+ (case ((spc_matches_prefix0 s34150)) of
+ Some ((_, s34160)) =>
+ (case ((string_drop s34150 s34160)) of
+ s34170 =>
+ (case ((reg_name_matches_prefix s34170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34180)) =>
+ (case ((string_drop s34170 s34180)) of
+ s34190 =>
+ (case ((sep_matches_prefix s34190)) of
+ Some ((_, s34200)) =>
+ (case ((string_drop s34190 s34200)) of
+ s34210 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s34210 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34220)) =>
+ (case ((string_drop s34210 s34220)) of
+ s34230 =>
+ (case ((sep_matches_prefix s34230)) of
+ Some ((_, s34240)) =>
+ (case ((string_drop s34230 s34240)) of
+ s34250 =>
+ (case ((csr_name_map_matches_prefix s34250
+ :: (( 12 Word.word * ii)) option)) of
+ Some ((csr, s34260)) =>
+ (case ((string_drop s34250 s34260)) of
+ s1 => Some (op1, rd, rs1, csr, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s34120 :: " string "
+
+
+\<comment> \<open>\<open>val _s3391_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3391 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3391 s33920 = (
+ (let s33930 = s33920 in
+ if ((string_startswith s33930 (''rem''))) then
+ (case ((string_drop s33930 ((string_length (''rem''))))) of
+ s33940 =>
+ (case ((maybe_not_u_matches_prefix s33940)) of
+ Some ((s, s33950)) =>
+ (let s33960 = (string_drop s33940 s33950) in
+ if ((string_startswith s33960 (''w''))) then
+ (case ((string_drop s33960 ((string_length (''w''))))) of
+ s33970 =>
+ (case ((spc_matches_prefix0 s33970)) of
+ Some ((_, s33980)) =>
+ (case ((string_drop s33970 s33980)) of
+ s33990 =>
+ (case ((reg_name_matches_prefix s33990 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s34000)) =>
+ (case ((string_drop s33990 s34000)) of
+ s34010 =>
+ (case ((sep_matches_prefix s34010)) of
+ Some ((_, s34020)) =>
+ (case ((string_drop s34010 s34020)) of
+ s34030 =>
+ (case ((reg_name_matches_prefix s34030 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s34040)) =>
+ (case ((string_drop s34030 s34040)) of
+ s34050 =>
+ (case ((sep_matches_prefix s34050)) of
+ Some ((_, s34060)) =>
+ (case ((string_drop s34050 s34060)) of
+ s34070 =>
+ (case ((reg_name_matches_prefix s34070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s34080)) =>
+ (case ((string_drop s34070 s34080)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s33920 :: " string "
+
+
+\<comment> \<open>\<open>val _s3372_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3372 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3372 s33730 = (
+ (let s33740 = s33730 in
+ if ((string_startswith s33740 (''div''))) then
+ (case ((string_drop s33740 ((string_length (''div''))))) of
+ s33750 =>
+ (case ((maybe_not_u_matches_prefix s33750)) of
+ Some ((s, s33760)) =>
+ (let s33770 = (string_drop s33750 s33760) in
+ if ((string_startswith s33770 (''w''))) then
+ (case ((string_drop s33770 ((string_length (''w''))))) of
+ s33780 =>
+ (case ((spc_matches_prefix0 s33780)) of
+ Some ((_, s33790)) =>
+ (case ((string_drop s33780 s33790)) of
+ s33800 =>
+ (case ((reg_name_matches_prefix s33800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33810)) =>
+ (case ((string_drop s33800 s33810)) of
+ s33820 =>
+ (case ((sep_matches_prefix s33820)) of
+ Some ((_, s33830)) =>
+ (case ((string_drop s33820 s33830)) of
+ s33840 =>
+ (case ((reg_name_matches_prefix s33840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33850)) =>
+ (case ((string_drop s33840 s33850)) of
+ s33860 =>
+ (case ((sep_matches_prefix s33860)) of
+ Some ((_, s33870)) =>
+ (case ((string_drop s33860 s33870)) of
+ s33880 =>
+ (case ((reg_name_matches_prefix s33880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33890)) =>
+ (case ((string_drop s33880 s33890)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ else None))"
+ for s33730 :: " string "
+
+
+\<comment> \<open>\<open>val _s3356_ : string -> maybe ((mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3356 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3356 s33570 = (
+ (let s33580 = s33570 in
+ if ((string_startswith s33580 (''mulw''))) then
+ (case ((string_drop s33580 ((string_length (''mulw''))))) of
+ s33590 =>
+ (case ((spc_matches_prefix0 s33590)) of
+ Some ((_, s33600)) =>
+ (case ((string_drop s33590 s33600)) of
+ s33610 =>
+ (case ((reg_name_matches_prefix s33610 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33620)) =>
+ (case ((string_drop s33610 s33620)) of
+ s33630 =>
+ (case ((sep_matches_prefix s33630)) of
+ Some ((_, s33640)) =>
+ (case ((string_drop s33630 s33640)) of
+ s33650 =>
+ (case ((reg_name_matches_prefix s33650 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33660)) =>
+ (case ((string_drop s33650 s33660)) of
+ s33670 =>
+ (case ((sep_matches_prefix s33670)) of
+ Some ((_, s33680)) =>
+ (case ((string_drop s33670 s33680)) of
+ s33690 =>
+ (case ((reg_name_matches_prefix s33690 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33700)) =>
+ (case ((string_drop s33690 s33700)) of s1 => Some (rd, rs1, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33570 :: " string "
+
+
+\<comment> \<open>\<open>val _s3338_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3338 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3338 s33390 = (
+ (let s33400 = s33390 in
+ if ((string_startswith s33400 (''rem''))) then
+ (case ((string_drop s33400 ((string_length (''rem''))))) of
+ s33410 =>
+ (case ((maybe_not_u_matches_prefix s33410)) of
+ Some ((s, s33420)) =>
+ (case ((string_drop s33410 s33420)) of
+ s33430 =>
+ (case ((spc_matches_prefix0 s33430)) of
+ Some ((_, s33440)) =>
+ (case ((string_drop s33430 s33440)) of
+ s33450 =>
+ (case ((reg_name_matches_prefix s33450 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33460)) =>
+ (case ((string_drop s33450 s33460)) of
+ s33470 =>
+ (case ((sep_matches_prefix s33470)) of
+ Some ((_, s33480)) =>
+ (case ((string_drop s33470 s33480)) of
+ s33490 =>
+ (case ((reg_name_matches_prefix s33490 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33500)) =>
+ (case ((string_drop s33490 s33500)) of
+ s33510 =>
+ (case ((sep_matches_prefix s33510)) of
+ Some ((_, s33520)) =>
+ (case ((string_drop s33510 s33520)) of
+ s33530 =>
+ (case ((reg_name_matches_prefix s33530 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33540)) =>
+ (case ((string_drop s33530 s33540)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33390 :: " string "
+
+
+\<comment> \<open>\<open>val _s3320_ : string -> maybe ((bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3320 :: " string \<Rightarrow>(bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3320 s33210 = (
+ (let s33220 = s33210 in
+ if ((string_startswith s33220 (''div''))) then
+ (case ((string_drop s33220 ((string_length (''div''))))) of
+ s33230 =>
+ (case ((maybe_not_u_matches_prefix s33230)) of
+ Some ((s, s33240)) =>
+ (case ((string_drop s33230 s33240)) of
+ s33250 =>
+ (case ((spc_matches_prefix0 s33250)) of
+ Some ((_, s33260)) =>
+ (case ((string_drop s33250 s33260)) of
+ s33270 =>
+ (case ((reg_name_matches_prefix s33270 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33280)) =>
+ (case ((string_drop s33270 s33280)) of
+ s33290 =>
+ (case ((sep_matches_prefix s33290)) of
+ Some ((_, s33300)) =>
+ (case ((string_drop s33290 s33300)) of
+ s33310 =>
+ (case ((reg_name_matches_prefix s33310 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33320)) =>
+ (case ((string_drop s33310 s33320)) of
+ s33330 =>
+ (case ((sep_matches_prefix s33330)) of
+ Some ((_, s33340)) =>
+ (case ((string_drop s33330 s33340)) of
+ s33350 =>
+ (case ((reg_name_matches_prefix s33350 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33360)) =>
+ (case ((string_drop s33350 s33360)) of
+ s2 => Some (s, rd, rs1, rs2, s2)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s33210 :: " string "
+
+
+\<comment> \<open>\<open>val _s3303_ : string -> maybe ((bool * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3303 :: " string \<Rightarrow>(bool*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s3303 s33050 = (
+ (case ((mul_mnemonic_matches_prefix s33050)) of
+ Some (((high, signed1, signed2), s33060)) =>
+ (case ((string_drop s33050 s33060)) of
+ s33070 =>
+ (case ((spc_matches_prefix0 s33070)) of
+ Some ((_, s33080)) =>
+ (case ((string_drop s33070 s33080)) of
+ s33090 =>
+ (case ((reg_name_matches_prefix s33090 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s33100)) =>
+ (case ((string_drop s33090 s33100)) of
+ s33110 =>
+ (case ((sep_matches_prefix s33110)) of
+ Some ((_, s33120)) =>
+ (case ((string_drop s33110 s33120)) of
+ s33130 =>
+ (case ((reg_name_matches_prefix s33130 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s33140)) =>
+ (case ((string_drop s33130 s33140)) of
+ s33150 =>
+ (case ((sep_matches_prefix s33150)) of
+ Some ((_, s33160)) =>
+ (case ((string_drop s33150 s33160)) of
+ s33170 =>
+ (case ((reg_name_matches_prefix s33170 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33180)) =>
+ (case ((string_drop s33170 s33180)) of
+ s1 => Some (high, signed1, signed2, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s33050 :: " string "
+
+
+\<comment> \<open>\<open>val _s3291_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3291 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s3291 s32920 = (
+ (let s32930 = s32920 in
+ if ((string_startswith s32930 (''c.add''))) then
+ (case ((string_drop s32930 ((string_length (''c.add''))))) of
+ s32940 =>
+ (case ((spc_matches_prefix0 s32940)) of
+ Some ((_, s32950)) =>
+ (case ((string_drop s32940 s32950)) of
+ s32960 =>
+ (case ((reg_name_matches_prefix s32960 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s32970)) =>
+ (case ((string_drop s32960 s32970)) of
+ s32980 =>
+ (case ((sep_matches_prefix s32980)) of
+ Some ((_, s32990)) =>
+ (case ((string_drop s32980 s32990)) of
+ s33000 =>
+ (case ((reg_name_matches_prefix s33000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s33010)) =>
+ (case ((string_drop s33000 s33010)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32920 :: " string "
+
+
+\<comment> \<open>\<open>val _s3287_ : string -> maybe string\<close>\<close>
+
+definition s3287 :: " string \<Rightarrow>(string)option " where
+ " s3287 s32880 = (
+ (let s32890 = s32880 in
+ if ((string_startswith s32890 (''c.ebreak''))) then
+ (case ((string_drop s32890 ((string_length (''c.ebreak''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s32880 :: " string "
+
+
+\<comment> \<open>\<open>val _s3275_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s3275 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s3275 s32760 = (
+ (let s32770 = s32760 in
+ if ((string_startswith s32770 (''c.mv''))) then
+ (case ((string_drop s32770 ((string_length (''c.mv''))))) of
+ s32780 =>
+ (case ((spc_matches_prefix0 s32780)) of
+ Some ((_, s32790)) =>
+ (case ((string_drop s32780 s32790)) of
+ s32800 =>
+ (case ((reg_name_matches_prefix s32800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32810)) =>
+ (case ((string_drop s32800 s32810)) of
+ s32820 =>
+ (case ((sep_matches_prefix s32820)) of
+ Some ((_, s32830)) =>
+ (case ((string_drop s32820 s32830)) of
+ s32840 =>
+ (case ((reg_name_matches_prefix s32840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s32850)) =>
+ (case ((string_drop s32840 s32850)) of s1 => Some (rd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32760 :: " string "
+
+
+\<comment> \<open>\<open>val _s3267_ : string -> maybe ((mword ty5 * string))\<close>\<close>
+
+definition s3267 :: " string \<Rightarrow>((5)Word.word*string)option " where
+ " s3267 s32680 = (
+ (let s32690 = s32680 in
+ if ((string_startswith s32690 (''c.jalr''))) then
+ (case ((string_drop s32690 ((string_length (''c.jalr''))))) of
+ s32700 =>
+ (case ((spc_matches_prefix0 s32700)) of
+ Some ((_, s32710)) =>
+ (case ((string_drop s32700 s32710)) of
+ s32720 =>
+ (case ((reg_name_matches_prefix s32720 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s32730)) =>
+ (case ((string_drop s32720 s32730)) of s1 => Some (rs1, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32680 :: " string "
+
+
+\<comment> \<open>\<open>val _s3259_ : string -> maybe ((mword ty5 * string))\<close>\<close>
+
+definition s3259 :: " string \<Rightarrow>((5)Word.word*string)option " where
+ " s3259 s32600 = (
+ (let s32610 = s32600 in
+ if ((string_startswith s32610 (''c.jr''))) then
+ (case ((string_drop s32610 ((string_length (''c.jr''))))) of
+ s32620 =>
+ (case ((spc_matches_prefix0 s32620)) of
+ Some ((_, s32630)) =>
+ (case ((string_drop s32620 s32630)) of
+ s32640 =>
+ (case ((reg_name_matches_prefix s32640 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s32650)) =>
+ (case ((string_drop s32640 s32650)) of s1 => Some (rs1, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32600 :: " string "
+
+
+\<comment> \<open>\<open>val _s3247_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3247 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3247 s32480 = (
+ (let s32490 = s32480 in
+ if ((string_startswith s32490 (''c.sdsp''))) then
+ (case ((string_drop s32490 ((string_length (''c.sdsp''))))) of
+ s32500 =>
+ (case ((spc_matches_prefix0 s32500)) of
+ Some ((_, s32510)) =>
+ (case ((string_drop s32500 s32510)) of
+ s32520 =>
+ (case ((reg_name_matches_prefix s32520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s32530)) =>
+ (case ((string_drop s32520 s32530)) of
+ s32540 =>
+ (case ((sep_matches_prefix s32540)) of
+ Some ((_, s32550)) =>
+ (case ((string_drop s32540 s32550)) of
+ s32560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32560 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32570)) =>
+ (case ((string_drop s32560 s32570)) of s1 => Some (rs2, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32480 :: " string "
+
+
+\<comment> \<open>\<open>val _s3235_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3235 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3235 s32360 = (
+ (let s32370 = s32360 in
+ if ((string_startswith s32370 (''c.swsp''))) then
+ (case ((string_drop s32370 ((string_length (''c.swsp''))))) of
+ s32380 =>
+ (case ((spc_matches_prefix0 s32380)) of
+ Some ((_, s32390)) =>
+ (case ((string_drop s32380 s32390)) of
+ s32400 =>
+ (case ((reg_name_matches_prefix s32400 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32410)) =>
+ (case ((string_drop s32400 s32410)) of
+ s32420 =>
+ (case ((sep_matches_prefix s32420)) of
+ Some ((_, s32430)) =>
+ (case ((string_drop s32420 s32430)) of
+ s32440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32440 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32450)) =>
+ (case ((string_drop s32440 s32450)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32360 :: " string "
+
+
+\<comment> \<open>\<open>val _s3223_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3223 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3223 s32240 = (
+ (let s32250 = s32240 in
+ if ((string_startswith s32250 (''c.ldsp''))) then
+ (case ((string_drop s32250 ((string_length (''c.ldsp''))))) of
+ s32260 =>
+ (case ((spc_matches_prefix0 s32260)) of
+ Some ((_, s32270)) =>
+ (case ((string_drop s32260 s32270)) of
+ s32280 =>
+ (case ((reg_name_matches_prefix s32280 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32290)) =>
+ (case ((string_drop s32280 s32290)) of
+ s32300 =>
+ (case ((sep_matches_prefix s32300)) of
+ Some ((_, s32310)) =>
+ (case ((string_drop s32300 s32310)) of
+ s32320 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32320 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32330)) =>
+ (case ((string_drop s32320 s32330)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32240 :: " string "
+
+
+\<comment> \<open>\<open>val _s3211_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3211 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3211 s32120 = (
+ (let s32130 = s32120 in
+ if ((string_startswith s32130 (''c.lwsp''))) then
+ (case ((string_drop s32130 ((string_length (''c.lwsp''))))) of
+ s32140 =>
+ (case ((spc_matches_prefix0 s32140)) of
+ Some ((_, s32150)) =>
+ (case ((string_drop s32140 s32150)) of
+ s32160 =>
+ (case ((reg_name_matches_prefix s32160 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s32170)) =>
+ (case ((string_drop s32160 s32170)) of
+ s32180 =>
+ (case ((sep_matches_prefix s32180)) of
+ Some ((_, s32190)) =>
+ (case ((string_drop s32180 s32190)) of
+ s32200 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32200 :: (( 6 Word.word * ii)) option)) of
+ Some ((uimm, s32210)) =>
+ (case ((string_drop s32200 s32210)) of s1 => Some (rd, uimm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32120 :: " string "
+
+
+\<comment> \<open>\<open>val _s3199_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3199 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3199 s32000 = (
+ (let s32010 = s32000 in
+ if ((string_startswith s32010 (''c.slli''))) then
+ (case ((string_drop s32010 ((string_length (''c.slli''))))) of
+ s32020 =>
+ (case ((spc_matches_prefix0 s32020)) of
+ Some ((_, s32030)) =>
+ (case ((string_drop s32020 s32030)) of
+ s32040 =>
+ (case ((reg_name_matches_prefix s32040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s32050)) =>
+ (case ((string_drop s32040 s32050)) of
+ s32060 =>
+ (case ((sep_matches_prefix s32060)) of
+ Some ((_, s32070)) =>
+ (case ((string_drop s32060 s32070)) of
+ s32080 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s32080 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s32090)) =>
+ (case ((string_drop s32080 s32090)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s32000 :: " string "
+
+
+\<comment> \<open>\<open>val _s3187_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s3187 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s3187 s31880 = (
+ (let s31890 = s31880 in
+ if ((string_startswith s31890 (''c.bnez''))) then
+ (case ((string_drop s31890 ((string_length (''c.bnez''))))) of
+ s31900 =>
+ (case ((spc_matches_prefix0 s31900)) of
+ Some ((_, s31910)) =>
+ (case ((string_drop s31900 s31910)) of
+ s31920 =>
+ (case ((creg_name_matches_prefix s31920 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s31930)) =>
+ (case ((string_drop s31920 s31930)) of
+ s31940 =>
+ (case ((sep_matches_prefix s31940)) of
+ Some ((_, s31950)) =>
+ (case ((string_drop s31940 s31950)) of
+ s31960 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31960 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s31970)) =>
+ (case ((string_drop s31960 s31970)) of s1 => Some (rs, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31880 :: " string "
+
+
+\<comment> \<open>\<open>val _s3175_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s3175 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s3175 s31760 = (
+ (let s31770 = s31760 in
+ if ((string_startswith s31770 (''c.beqz''))) then
+ (case ((string_drop s31770 ((string_length (''c.beqz''))))) of
+ s31780 =>
+ (case ((spc_matches_prefix0 s31780)) of
+ Some ((_, s31790)) =>
+ (case ((string_drop s31780 s31790)) of
+ s31800 =>
+ (case ((creg_name_matches_prefix s31800 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs, s31810)) =>
+ (case ((string_drop s31800 s31810)) of
+ s31820 =>
+ (case ((sep_matches_prefix s31820)) of
+ Some ((_, s31830)) =>
+ (case ((string_drop s31820 s31830)) of
+ s31840 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31840 :: (( 8 Word.word * ii)) option)) of
+ Some ((imm, s31850)) =>
+ (case ((string_drop s31840 s31850)) of s1 => Some (rs, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31760 :: " string "
+
+
+\<comment> \<open>\<open>val _s3167_ : string -> maybe ((mword ty11 * string))\<close>\<close>
+
+definition s3167 :: " string \<Rightarrow>((11)Word.word*string)option " where
+ " s3167 s31680 = (
+ (let s31690 = s31680 in
+ if ((string_startswith s31690 (''c.j''))) then
+ (case ((string_drop s31690 ((string_length (''c.j''))))) of
+ s31700 =>
+ (case ((spc_matches_prefix0 s31700)) of
+ Some ((_, s31710)) =>
+ (case ((string_drop s31700 s31710)) of
+ s31720 =>
+ (case ((hex_bits_11_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s31720 :: (( 11 Word.word * ii)) option)) of
+ Some ((imm, s31730)) =>
+ (case ((string_drop s31720 s31730)) of s1 => Some (imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31680 :: " string "
+
+
+\<comment> \<open>\<open>val _s3155_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3155 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3155 s31560 = (
+ (let s31570 = s31560 in
+ if ((string_startswith s31570 (''c.addw''))) then
+ (case ((string_drop s31570 ((string_length (''c.addw''))))) of
+ s31580 =>
+ (case ((spc_matches_prefix0 s31580)) of
+ Some ((_, s31590)) =>
+ (case ((string_drop s31580 s31590)) of
+ s31600 =>
+ (case ((creg_name_matches_prefix s31600 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31610)) =>
+ (case ((string_drop s31600 s31610)) of
+ s31620 =>
+ (case ((sep_matches_prefix s31620)) of
+ Some ((_, s31630)) =>
+ (case ((string_drop s31620 s31630)) of
+ s31640 =>
+ (case ((creg_name_matches_prefix s31640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31650)) =>
+ (case ((string_drop s31640 s31650)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31560 :: " string "
+
+
+\<comment> \<open>\<open>val _s3143_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3143 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3143 s31440 = (
+ (let s31450 = s31440 in
+ if ((string_startswith s31450 (''c.subw''))) then
+ (case ((string_drop s31450 ((string_length (''c.subw''))))) of
+ s31460 =>
+ (case ((spc_matches_prefix0 s31460)) of
+ Some ((_, s31470)) =>
+ (case ((string_drop s31460 s31470)) of
+ s31480 =>
+ (case ((creg_name_matches_prefix s31480 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31490)) =>
+ (case ((string_drop s31480 s31490)) of
+ s31500 =>
+ (case ((sep_matches_prefix s31500)) of
+ Some ((_, s31510)) =>
+ (case ((string_drop s31500 s31510)) of
+ s31520 =>
+ (case ((creg_name_matches_prefix s31520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31530)) =>
+ (case ((string_drop s31520 s31530)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31440 :: " string "
+
+
+\<comment> \<open>\<open>val _s3131_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3131 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3131 s31320 = (
+ (let s31330 = s31320 in
+ if ((string_startswith s31330 (''c.and''))) then
+ (case ((string_drop s31330 ((string_length (''c.and''))))) of
+ s31340 =>
+ (case ((spc_matches_prefix0 s31340)) of
+ Some ((_, s31350)) =>
+ (case ((string_drop s31340 s31350)) of
+ s31360 =>
+ (case ((creg_name_matches_prefix s31360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31370)) =>
+ (case ((string_drop s31360 s31370)) of
+ s31380 =>
+ (case ((sep_matches_prefix s31380)) of
+ Some ((_, s31390)) =>
+ (case ((string_drop s31380 s31390)) of
+ s31400 =>
+ (case ((creg_name_matches_prefix s31400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31410)) =>
+ (case ((string_drop s31400 s31410)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31320 :: " string "
+
+
+\<comment> \<open>\<open>val _s3119_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3119 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3119 s31200 = (
+ (let s31210 = s31200 in
+ if ((string_startswith s31210 (''c.or''))) then
+ (case ((string_drop s31210 ((string_length (''c.or''))))) of
+ s31220 =>
+ (case ((spc_matches_prefix0 s31220)) of
+ Some ((_, s31230)) =>
+ (case ((string_drop s31220 s31230)) of
+ s31240 =>
+ (case ((creg_name_matches_prefix s31240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31250)) =>
+ (case ((string_drop s31240 s31250)) of
+ s31260 =>
+ (case ((sep_matches_prefix s31260)) of
+ Some ((_, s31270)) =>
+ (case ((string_drop s31260 s31270)) of
+ s31280 =>
+ (case ((creg_name_matches_prefix s31280 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31290)) =>
+ (case ((string_drop s31280 s31290)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31200 :: " string "
+
+
+\<comment> \<open>\<open>val _s3107_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3107 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3107 s31080 = (
+ (let s31090 = s31080 in
+ if ((string_startswith s31090 (''c.xor''))) then
+ (case ((string_drop s31090 ((string_length (''c.xor''))))) of
+ s31100 =>
+ (case ((spc_matches_prefix0 s31100)) of
+ Some ((_, s31110)) =>
+ (case ((string_drop s31100 s31110)) of
+ s31120 =>
+ (case ((creg_name_matches_prefix s31120 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31130)) =>
+ (case ((string_drop s31120 s31130)) of
+ s31140 =>
+ (case ((sep_matches_prefix s31140)) of
+ Some ((_, s31150)) =>
+ (case ((string_drop s31140 s31150)) of
+ s31160 =>
+ (case ((creg_name_matches_prefix s31160 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31170)) =>
+ (case ((string_drop s31160 s31170)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s31080 :: " string "
+
+
+\<comment> \<open>\<open>val _s3095_ : string -> maybe ((mword ty3 * mword ty3 * string))\<close>\<close>
+
+definition s3095 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*string)option " where
+ " s3095 s30960 = (
+ (let s30970 = s30960 in
+ if ((string_startswith s30970 (''c.sub''))) then
+ (case ((string_drop s30970 ((string_length (''c.sub''))))) of
+ s30980 =>
+ (case ((spc_matches_prefix0 s30980)) of
+ Some ((_, s30990)) =>
+ (case ((string_drop s30980 s30990)) of
+ s31000 =>
+ (case ((creg_name_matches_prefix s31000 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s31010)) =>
+ (case ((string_drop s31000 s31010)) of
+ s31020 =>
+ (case ((sep_matches_prefix s31020)) of
+ Some ((_, s31030)) =>
+ (case ((string_drop s31020 s31030)) of
+ s31040 =>
+ (case ((creg_name_matches_prefix s31040 :: (( 3 Word.word * ii)) option)) of
+ Some ((rs2, s31050)) =>
+ (case ((string_drop s31040 s31050)) of s1 => Some (rsd, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30960 :: " string "
+
+
+\<comment> \<open>\<open>val _s3083_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3083 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3083 s30840 = (
+ (let s30850 = s30840 in
+ if ((string_startswith s30850 (''c.andi''))) then
+ (case ((string_drop s30850 ((string_length (''c.andi''))))) of
+ s30860 =>
+ (case ((spc_matches_prefix0 s30860)) of
+ Some ((_, s30870)) =>
+ (case ((string_drop s30860 s30870)) of
+ s30880 =>
+ (case ((creg_name_matches_prefix s30880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30890)) =>
+ (case ((string_drop s30880 s30890)) of
+ s30900 =>
+ (case ((sep_matches_prefix s30900)) of
+ Some ((_, s30910)) =>
+ (case ((string_drop s30900 s30910)) of
+ s30920 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30920 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30930)) =>
+ (case ((string_drop s30920 s30930)) of s1 => Some (rsd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30840 :: " string "
+
+
+\<comment> \<open>\<open>val _s3071_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3071 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3071 s30720 = (
+ (let s30730 = s30720 in
+ if ((string_startswith s30730 (''c.srai''))) then
+ (case ((string_drop s30730 ((string_length (''c.srai''))))) of
+ s30740 =>
+ (case ((spc_matches_prefix0 s30740)) of
+ Some ((_, s30750)) =>
+ (case ((string_drop s30740 s30750)) of
+ s30760 =>
+ (case ((creg_name_matches_prefix s30760 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30770)) =>
+ (case ((string_drop s30760 s30770)) of
+ s30780 =>
+ (case ((sep_matches_prefix s30780)) of
+ Some ((_, s30790)) =>
+ (case ((string_drop s30780 s30790)) of
+ s30800 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30800 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s30810)) =>
+ (case ((string_drop s30800 s30810)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30720 :: " string "
+
+
+\<comment> \<open>\<open>val _s3059_ : string -> maybe ((mword ty3 * mword ty6 * string))\<close>\<close>
+
+definition s3059 :: " string \<Rightarrow>((3)Word.word*(6)Word.word*string)option " where
+ " s3059 s30600 = (
+ (let s30610 = s30600 in
+ if ((string_startswith s30610 (''c.srli''))) then
+ (case ((string_drop s30610 ((string_length (''c.srli''))))) of
+ s30620 =>
+ (case ((spc_matches_prefix0 s30620)) of
+ Some ((_, s30630)) =>
+ (case ((string_drop s30620 s30630)) of
+ s30640 =>
+ (case ((creg_name_matches_prefix s30640 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsd, s30650)) =>
+ (case ((string_drop s30640 s30650)) of
+ s30660 =>
+ (case ((sep_matches_prefix s30660)) of
+ Some ((_, s30670)) =>
+ (case ((string_drop s30660 s30670)) of
+ s30680 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30680 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s30690)) =>
+ (case ((string_drop s30680 s30690)) of s1 => Some (rsd, shamt, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30600 :: " string "
+
+
+\<comment> \<open>\<open>val _s3047_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3047 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3047 s30480 = (
+ (let s30490 = s30480 in
+ if ((string_startswith s30490 (''c.lui''))) then
+ (case ((string_drop s30490 ((string_length (''c.lui''))))) of
+ s30500 =>
+ (case ((spc_matches_prefix0 s30500)) of
+ Some ((_, s30510)) =>
+ (case ((string_drop s30500 s30510)) of
+ s30520 =>
+ (case ((reg_name_matches_prefix s30520 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s30530)) =>
+ (case ((string_drop s30520 s30530)) of
+ s30540 =>
+ (case ((sep_matches_prefix s30540)) of
+ Some ((_, s30550)) =>
+ (case ((string_drop s30540 s30550)) of
+ s30560 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30560 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30570)) =>
+ (case ((string_drop s30560 s30570)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30480 :: " string "
+
+
+\<comment> \<open>\<open>val _s3039_ : string -> maybe ((mword ty6 * string))\<close>\<close>
+
+definition s3039 :: " string \<Rightarrow>((6)Word.word*string)option " where
+ " s3039 s30400 = (
+ (let s30410 = s30400 in
+ if ((string_startswith s30410 (''c.addi16sp''))) then
+ (case ((string_drop s30410 ((string_length (''c.addi16sp''))))) of
+ s30420 =>
+ (case ((spc_matches_prefix0 s30420)) of
+ Some ((_, s30430)) =>
+ (case ((string_drop s30420 s30430)) of
+ s30440 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30440 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30450)) =>
+ (case ((string_drop s30440 s30450)) of s1 => Some (imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30400 :: " string "
+
+
+\<comment> \<open>\<open>val _s3027_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3027 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3027 s30280 = (
+ (let s30290 = s30280 in
+ if ((string_startswith s30290 (''c.li''))) then
+ (case ((string_drop s30290 ((string_length (''c.li''))))) of
+ s30300 =>
+ (case ((spc_matches_prefix0 s30300)) of
+ Some ((_, s30310)) =>
+ (case ((string_drop s30300 s30310)) of
+ s30320 =>
+ (case ((reg_name_matches_prefix s30320 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s30330)) =>
+ (case ((string_drop s30320 s30330)) of
+ s30340 =>
+ (case ((sep_matches_prefix s30340)) of
+ Some ((_, s30350)) =>
+ (case ((string_drop s30340 s30350)) of
+ s30360 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30360 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30370)) =>
+ (case ((string_drop s30360 s30370)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30280 :: " string "
+
+
+\<comment> \<open>\<open>val _s3015_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s3015 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s3015 s30160 = (
+ (let s30170 = s30160 in
+ if ((string_startswith s30170 (''c.addiw''))) then
+ (case ((string_drop s30170 ((string_length (''c.addiw''))))) of
+ s30180 =>
+ (case ((spc_matches_prefix0 s30180)) of
+ Some ((_, s30190)) =>
+ (case ((string_drop s30180 s30190)) of
+ s30200 =>
+ (case ((reg_name_matches_prefix s30200 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s30210)) =>
+ (case ((string_drop s30200 s30210)) of
+ s30220 =>
+ (case ((sep_matches_prefix s30220)) of
+ Some ((_, s30230)) =>
+ (case ((string_drop s30220 s30230)) of
+ s30240 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30240 :: (( 6 Word.word * ii)) option)) of
+ Some ((imm, s30250)) =>
+ (case ((string_drop s30240 s30250)) of s1 => Some (rsd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30160 :: " string "
+
+
+\<comment> \<open>\<open>val _s3007_ : string -> maybe ((mword ty11 * string))\<close>\<close>
+
+definition s3007 :: " string \<Rightarrow>((11)Word.word*string)option " where
+ " s3007 s30080 = (
+ (let s30090 = s30080 in
+ if ((string_startswith s30090 (''c.jal''))) then
+ (case ((string_drop s30090 ((string_length (''c.jal''))))) of
+ s30100 =>
+ (case ((spc_matches_prefix0 s30100)) of
+ Some ((_, s30110)) =>
+ (case ((string_drop s30100 s30110)) of
+ s30120 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30120 :: (( 12 Word.word * ii)) option)) of
+ Some ((v__826, s30130)) =>
+ if (((((subrange_vec_dec v__826 (( 0 :: int):: ii) (( 0 :: int):: ii) :: 1 Word.word))
+ = (vec_of_bits [B0] :: 1 Word.word)))) then
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__826
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (let (imm :: 11 Word.word) = ((subrange_vec_dec v__826
+ (( 11 :: int):: ii) (( 1 :: int):: ii) :: 11 Word.word)) in
+ (case ((string_drop s30120 s30130)) of s1 => Some (imm, s1) ))) else
+ None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s30080 :: " string "
+
+
+\<comment> \<open>\<open>val _s2995_ : string -> maybe ((mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s2995 :: " string \<Rightarrow>((5)Word.word*(6)Word.word*string)option " where
+ " s2995 s29960 = (
+ (let s29970 = s29960 in
+ if ((string_startswith s29970 (''c.addi''))) then
+ (case ((string_drop s29970 ((string_length (''c.addi''))))) of
+ s29980 =>
+ (case ((spc_matches_prefix0 s29980)) of
+ Some ((_, s29990)) =>
+ (case ((string_drop s29980 s29990)) of
+ s30000 =>
+ (case ((reg_name_matches_prefix s30000 :: (( 5 Word.word * ii)) option)) of
+ Some ((rsd, s30010)) =>
+ (case ((string_drop s30000 s30010)) of
+ s30020 =>
+ (case ((sep_matches_prefix s30020)) of
+ Some ((_, s30030)) =>
+ (case ((string_drop s30020 s30030)) of
+ s30040 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s30040 :: (( 6 Word.word * ii)) option)) of
+ Some ((nzi, s30050)) =>
+ (case ((string_drop s30040 s30050)) of s1 => Some (rsd, nzi, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29960 :: " string "
+
+
+\<comment> \<open>\<open>val _s2979_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2979 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2979 s29800 = (
+ (let s29810 = s29800 in
+ if ((string_startswith s29810 (''c.sd''))) then
+ (case ((string_drop s29810 ((string_length (''c.sd''))))) of
+ s29820 =>
+ (case ((spc_matches_prefix0 s29820)) of
+ Some ((_, s29830)) =>
+ (case ((string_drop s29820 s29830)) of
+ s29840 =>
+ (case ((creg_name_matches_prefix s29840 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s29850)) =>
+ (case ((string_drop s29840 s29850)) of
+ s29860 =>
+ (case ((sep_matches_prefix s29860)) of
+ Some ((_, s29870)) =>
+ (case ((string_drop s29860 s29870)) of
+ s29880 =>
+ (case ((creg_name_matches_prefix s29880 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s29890)) =>
+ (case ((string_drop s29880 s29890)) of
+ s29900 =>
+ (case ((sep_matches_prefix s29900)) of
+ Some ((_, s29910)) =>
+ (case ((string_drop s29900 s29910)) of
+ s29920 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29920 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__828, s29930)) =>
+ if (((((subrange_vec_dec v__828 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__828 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__828 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29920 s29930)) of
+ s1 => Some (rsc1, rsc2, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29800 :: " string "
+
+
+\<comment> \<open>\<open>val _s2963_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2963 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2963 s29640 = (
+ (let s29650 = s29640 in
+ if ((string_startswith s29650 (''c.sw''))) then
+ (case ((string_drop s29650 ((string_length (''c.sw''))))) of
+ s29660 =>
+ (case ((spc_matches_prefix0 s29660)) of
+ Some ((_, s29670)) =>
+ (case ((string_drop s29660 s29670)) of
+ s29680 =>
+ (case ((creg_name_matches_prefix s29680 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc1, s29690)) =>
+ (case ((string_drop s29680 s29690)) of
+ s29700 =>
+ (case ((sep_matches_prefix s29700)) of
+ Some ((_, s29710)) =>
+ (case ((string_drop s29700 s29710)) of
+ s29720 =>
+ (case ((creg_name_matches_prefix s29720 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc2, s29730)) =>
+ (case ((string_drop s29720 s29730)) of
+ s29740 =>
+ (case ((sep_matches_prefix s29740)) of
+ Some ((_, s29750)) =>
+ (case ((string_drop s29740 s29750)) of
+ s29760 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29760 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__830, s29770)) =>
+ if (((((subrange_vec_dec v__830 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__830 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__830 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29760 s29770)) of
+ s1 => Some (rsc1, rsc2, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29640 :: " string "
+
+
+\<comment> \<open>\<open>val _s2947_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2947 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2947 s29480 = (
+ (let s29490 = s29480 in
+ if ((string_startswith s29490 (''c.ld''))) then
+ (case ((string_drop s29490 ((string_length (''c.ld''))))) of
+ s29500 =>
+ (case ((spc_matches_prefix0 s29500)) of
+ Some ((_, s29510)) =>
+ (case ((string_drop s29500 s29510)) of
+ s29520 =>
+ (case ((creg_name_matches_prefix s29520 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29530)) =>
+ (case ((string_drop s29520 s29530)) of
+ s29540 =>
+ (case ((sep_matches_prefix s29540)) of
+ Some ((_, s29550)) =>
+ (case ((string_drop s29540 s29550)) of
+ s29560 =>
+ (case ((creg_name_matches_prefix s29560 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s29570)) =>
+ (case ((string_drop s29560 s29570)) of
+ s29580 =>
+ (case ((sep_matches_prefix s29580)) of
+ Some ((_, s29590)) =>
+ (case ((string_drop s29580 s29590)) of
+ s29600 =>
+ (case ((hex_bits_8_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29600 :: (( 8 Word.word * ii)) option)) of
+ Some ((v__832, s29610)) =>
+ if (((((subrange_vec_dec v__832 (( 2 :: int):: ii) (( 0 :: int):: ii) :: 3 Word.word))
+ = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__832 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__832 (( 7 :: int):: ii) (( 3 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29600 s29610)) of
+ s1 => Some (rdc, rsc, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29480 :: " string "
+
+
+\<comment> \<open>\<open>val _s2931_ : string -> maybe ((mword ty3 * mword ty3 * mword ty5 * string))\<close>\<close>
+
+definition s2931 :: " string \<Rightarrow>((3)Word.word*(3)Word.word*(5)Word.word*string)option " where
+ " s2931 s29320 = (
+ (let s29330 = s29320 in
+ if ((string_startswith s29330 (''c.lw''))) then
+ (case ((string_drop s29330 ((string_length (''c.lw''))))) of
+ s29340 =>
+ (case ((spc_matches_prefix0 s29340)) of
+ Some ((_, s29350)) =>
+ (case ((string_drop s29340 s29350)) of
+ s29360 =>
+ (case ((creg_name_matches_prefix s29360 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29370)) =>
+ (case ((string_drop s29360 s29370)) of
+ s29380 =>
+ (case ((sep_matches_prefix s29380)) of
+ Some ((_, s29390)) =>
+ (case ((string_drop s29380 s29390)) of
+ s29400 =>
+ (case ((creg_name_matches_prefix s29400 :: (( 3 Word.word * ii)) option)) of
+ Some ((rsc, s29410)) =>
+ (case ((string_drop s29400 s29410)) of
+ s29420 =>
+ (case ((sep_matches_prefix s29420)) of
+ Some ((_, s29430)) =>
+ (case ((string_drop s29420 s29430)) of
+ s29440 =>
+ (case ((hex_bits_7_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29440 :: (( 7 Word.word * ii)) option)) of
+ Some ((v__834, s29450)) =>
+ if (((((subrange_vec_dec v__834 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__834 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (let (uimm :: 5 Word.word) =
+ ((subrange_vec_dec v__834 (( 6 :: int):: ii) (( 2 :: int):: ii) :: 5 Word.word)) in
+ (case ((string_drop s29440 s29450)) of
+ s1 => Some (rdc, rsc, uimm, s1)
+ ))) else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2919_ : string -> maybe ((mword ty3 * mword ty8 * string))\<close>\<close>
+
+definition s2919 :: " string \<Rightarrow>((3)Word.word*(8)Word.word*string)option " where
+ " s2919 s29200 = (
+ (let s29210 = s29200 in
+ if ((string_startswith s29210 (''c.addi4spn''))) then
+ (case ((string_drop s29210 ((string_length (''c.addi4spn''))))) of
+ s29220 =>
+ (case ((spc_matches_prefix0 s29220)) of
+ Some ((_, s29230)) =>
+ (case ((string_drop s29220 s29230)) of
+ s29240 =>
+ (case ((creg_name_matches_prefix s29240 :: (( 3 Word.word * ii)) option)) of
+ Some ((rdc, s29250)) =>
+ (case ((string_drop s29240 s29250)) of
+ s29260 =>
+ (case ((sep_matches_prefix s29260)) of
+ Some ((_, s29270)) =>
+ (case ((string_drop s29260 s29270)) of
+ s29280 =>
+ (case ((hex_bits_10_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s29280 :: (( 10 Word.word * ii)) option)) of
+ Some ((v__836, s29290)) =>
+ if (((((subrange_vec_dec v__836 (( 1 :: int):: ii) (( 0 :: int):: ii) :: 2 Word.word))
+ = (vec_of_bits [B0,B0] :: 2 Word.word)))) then
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__836 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (let (nzimm :: 8 Word.word) =
+ ((subrange_vec_dec v__836 (( 9 :: int):: ii) (( 2 :: int):: ii) :: 8 Word.word)) in
+ (case ((string_drop s29280 s29290)) of s1 => Some (rdc, nzimm, s1) )))
+ else None
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s29200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2915_ : string -> maybe string\<close>\<close>
+
+definition s2915 :: " string \<Rightarrow>(string)option " where
+ " s2915 s29160 = (
+ (let s29170 = s29160 in
+ if ((string_startswith s29170 (''c.nop''))) then
+ (case ((string_drop s29170 ((string_length (''c.nop''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s29160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2891_ : string -> maybe ((amoop * word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2891 :: " string \<Rightarrow>(amoop*word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2891 s28930 = (
+ (case ((amo_mnemonic_matches_prefix s28930)) of
+ Some ((op1, s28940)) =>
+ (let s28950 = (string_drop s28930 s28940) in
+ if ((string_startswith s28950 (''.''))) then
+ (case ((string_drop s28950 ((string_length (''.''))))) of
+ s28960 =>
+ (case ((size_mnemonic_matches_prefix s28960)) of
+ Some ((width, s28970)) =>
+ (case ((string_drop s28960 s28970)) of
+ s28980 =>
+ (case ((maybe_aq_matches_prefix s28980)) of
+ Some ((aq, s28990)) =>
+ (case ((string_drop s28980 s28990)) of
+ s29000 =>
+ (case ((maybe_rl_matches_prefix s29000)) of
+ Some ((rl, s29010)) =>
+ (case ((string_drop s29000 s29010)) of
+ s29020 =>
+ (case ((spc_matches_prefix0 s29020)) of
+ Some ((_, s29030)) =>
+ (case ((string_drop s29020 s29030)) of
+ s29040 =>
+ (case ((reg_name_matches_prefix s29040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s29050)) =>
+ (case ((string_drop s29040 s29050)) of
+ s29060 =>
+ (case ((sep_matches_prefix s29060)) of
+ Some ((_, s29070)) =>
+ (case ((string_drop s29060 s29070)) of
+ s29080 =>
+ (case ((reg_name_matches_prefix s29080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s29090)) =>
+ (case ((string_drop s29080 s29090)) of
+ s29100 =>
+ (case ((sep_matches_prefix s29100)) of
+ Some ((_, s29110)) =>
+ (case ((string_drop s29100 s29110)) of
+ s29120 =>
+ (case ((reg_name_matches_prefix s29120 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s29130)) =>
+ (case ((string_drop s29120 s29130)) of
+ s1 =>
+ Some (op1, width, aq, rl, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None)
+ | _ => None
+ ))"
+ for s28930 :: " string "
+
+
+\<comment> \<open>\<open>val _s2869_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2869 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2869 s28700 = (
+ (let s28710 = s28700 in
+ if ((string_startswith s28710 (''sc.''))) then
+ (case ((string_drop s28710 ((string_length (''sc.''))))) of
+ s28720 =>
+ (case ((size_mnemonic_matches_prefix s28720)) of
+ Some ((size1, s28730)) =>
+ (case ((string_drop s28720 s28730)) of
+ s28740 =>
+ (case ((maybe_aq_matches_prefix s28740)) of
+ Some ((aq, s28750)) =>
+ (case ((string_drop s28740 s28750)) of
+ s28760 =>
+ (case ((maybe_rl_matches_prefix s28760)) of
+ Some ((rl, s28770)) =>
+ (case ((string_drop s28760 s28770)) of
+ s28780 =>
+ (case ((spc_matches_prefix0 s28780)) of
+ Some ((_, s28790)) =>
+ (case ((string_drop s28780 s28790)) of
+ s28800 =>
+ (case ((reg_name_matches_prefix s28800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s28810)) =>
+ (case ((string_drop s28800 s28810)) of
+ s28820 =>
+ (case ((sep_matches_prefix s28820)) of
+ Some ((_, s28830)) =>
+ (case ((string_drop s28820 s28830)) of
+ s28840 =>
+ (case ((reg_name_matches_prefix s28840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28850)) =>
+ (case ((string_drop s28840 s28850)) of
+ s28860 =>
+ (case ((sep_matches_prefix s28860)) of
+ Some ((_, s28870)) =>
+ (case ((string_drop s28860 s28870)) of
+ s28880 =>
+ (case ((reg_name_matches_prefix s28880 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s28890)) =>
+ (case ((string_drop s28880 s28890)) of
+ s1 =>
+ Some (size1, aq, rl, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28700 :: " string "
+
+
+\<comment> \<open>\<open>val _s2851_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2851 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(5)Word.word*string)option " where
+ " s2851 s28520 = (
+ (let s28530 = s28520 in
+ if ((string_startswith s28530 (''lr.''))) then
+ (case ((string_drop s28530 ((string_length (''lr.''))))) of
+ s28540 =>
+ (case ((size_mnemonic_matches_prefix s28540)) of
+ Some ((size1, s28550)) =>
+ (case ((string_drop s28540 s28550)) of
+ s28560 =>
+ (case ((maybe_aq_matches_prefix s28560)) of
+ Some ((aq, s28570)) =>
+ (case ((string_drop s28560 s28570)) of
+ s28580 =>
+ (case ((maybe_rl_matches_prefix s28580)) of
+ Some ((rl, s28590)) =>
+ (case ((string_drop s28580 s28590)) of
+ s28600 =>
+ (case ((spc_matches_prefix0 s28600)) of
+ Some ((_, s28610)) =>
+ (case ((string_drop s28600 s28610)) of
+ s28620 =>
+ (case ((reg_name_matches_prefix s28620 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s28630)) =>
+ (case ((string_drop s28620 s28630)) of
+ s28640 =>
+ (case ((sep_matches_prefix s28640)) of
+ Some ((_, s28650)) =>
+ (case ((string_drop s28640 s28650)) of
+ s28660 =>
+ (case ((reg_name_matches_prefix s28660 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28670)) =>
+ (case ((string_drop s28660 s28670)) of
+ s1 => Some (size1, aq, rl, rd, rs1, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28520 :: " string "
+
+
+\<comment> \<open>\<open>val _s2839_ : string -> maybe ((mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2839 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*string)option " where
+ " s2839 s28400 = (
+ (let s28410 = s28400 in
+ if ((string_startswith s28410 (''sfence.vma''))) then
+ (case ((string_drop s28410 ((string_length (''sfence.vma''))))) of
+ s28420 =>
+ (case ((spc_matches_prefix0 s28420)) of
+ Some ((_, s28430)) =>
+ (case ((string_drop s28420 s28430)) of
+ s28440 =>
+ (case ((reg_name_matches_prefix s28440 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s28450)) =>
+ (case ((string_drop s28440 s28450)) of
+ s28460 =>
+ (case ((sep_matches_prefix s28460)) of
+ Some ((_, s28470)) =>
+ (case ((string_drop s28460 s28470)) of
+ s28480 =>
+ (case ((reg_name_matches_prefix s28480 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s28490)) =>
+ (case ((string_drop s28480 s28490)) of s1 => Some (rs1, rs2, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28400 :: " string "
+
+
+\<comment> \<open>\<open>val _s2835_ : string -> maybe string\<close>\<close>
+
+definition s2835 :: " string \<Rightarrow>(string)option " where
+ " s2835 s28360 = (
+ (let s28370 = s28360 in
+ if ((string_startswith s28370 (''wfi''))) then
+ (case ((string_drop s28370 ((string_length (''wfi''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28360 :: " string "
+
+
+\<comment> \<open>\<open>val _s2831_ : string -> maybe string\<close>\<close>
+
+definition s2831 :: " string \<Rightarrow>(string)option " where
+ " s2831 s28320 = (
+ (let s28330 = s28320 in
+ if ((string_startswith s28330 (''ebreak''))) then
+ (case ((string_drop s28330 ((string_length (''ebreak''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28320 :: " string "
+
+
+\<comment> \<open>\<open>val _s2827_ : string -> maybe string\<close>\<close>
+
+definition s2827 :: " string \<Rightarrow>(string)option " where
+ " s2827 s28280 = (
+ (let s28290 = s28280 in
+ if ((string_startswith s28290 (''sret''))) then
+ (case ((string_drop s28290 ((string_length (''sret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28280 :: " string "
+
+
+\<comment> \<open>\<open>val _s2823_ : string -> maybe string\<close>\<close>
+
+definition s2823 :: " string \<Rightarrow>(string)option " where
+ " s2823 s28240 = (
+ (let s28250 = s28240 in
+ if ((string_startswith s28250 (''mret''))) then
+ (case ((string_drop s28250 ((string_length (''mret''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28240 :: " string "
+
+
+\<comment> \<open>\<open>val _s2819_ : string -> maybe string\<close>\<close>
+
+definition s2819 :: " string \<Rightarrow>(string)option " where
+ " s2819 s28200 = (
+ (let s28210 = s28200 in
+ if ((string_startswith s28210 (''ecall''))) then
+ (case ((string_drop s28210 ((string_length (''ecall''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28200 :: " string "
+
+
+\<comment> \<open>\<open>val _s2815_ : string -> maybe string\<close>\<close>
+
+definition s2815 :: " string \<Rightarrow>(string)option " where
+ " s2815 s28160 = (
+ (let s28170 = s28160 in
+ if ((string_startswith s28170 (''fence.i''))) then
+ (case ((string_drop s28170 ((string_length (''fence.i''))))) of
+ s1 => Some s1
+ )
+ else None))"
+ for s28160 :: " string "
+
+
+\<comment> \<open>\<open>val _s2803_ : string -> maybe ((mword ty4 * mword ty4 * string))\<close>\<close>
+
+definition s2803 :: " string \<Rightarrow>((4)Word.word*(4)Word.word*string)option " where
+ " s2803 s28040 = (
+ (let s28050 = s28040 in
+ if ((string_startswith s28050 (''fence.tso''))) then
+ (case ((string_drop s28050 ((string_length (''fence.tso''))))) of
+ s28060 =>
+ (case ((spc_matches_prefix0 s28060)) of
+ Some ((_, s28070)) =>
+ (case ((string_drop s28060 s28070)) of
+ s28080 =>
+ (case ((fence_bits_matches_prefix s28080 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s28090)) =>
+ (case ((string_drop s28080 s28090)) of
+ s28100 =>
+ (case ((sep_matches_prefix s28100)) of
+ Some ((_, s28110)) =>
+ (case ((string_drop s28100 s28110)) of
+ s28120 =>
+ (case ((fence_bits_matches_prefix s28120 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s28130)) =>
+ (case ((string_drop s28120 s28130)) of s1 => Some (pred, succ, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s28040 :: " string "
+
+
+\<comment> \<open>\<open>val _s2791_ : string -> maybe ((mword ty4 * mword ty4 * string))\<close>\<close>
+
+definition s2791 :: " string \<Rightarrow>((4)Word.word*(4)Word.word*string)option " where
+ " s2791 s27920 = (
+ (let s27930 = s27920 in
+ if ((string_startswith s27930 (''fence''))) then
+ (case ((string_drop s27930 ((string_length (''fence''))))) of
+ s27940 =>
+ (case ((spc_matches_prefix0 s27940)) of
+ Some ((_, s27950)) =>
+ (case ((string_drop s27940 s27950)) of
+ s27960 =>
+ (case ((fence_bits_matches_prefix s27960 :: (( 4 Word.word * ii)) option)) of
+ Some ((pred, s27970)) =>
+ (case ((string_drop s27960 s27970)) of
+ s27980 =>
+ (case ((sep_matches_prefix s27980)) of
+ Some ((_, s27990)) =>
+ (case ((string_drop s27980 s27990)) of
+ s28000 =>
+ (case ((fence_bits_matches_prefix s28000 :: (( 4 Word.word * ii)) option)) of
+ Some ((succ, s28010)) =>
+ (case ((string_drop s28000 s28010)) of s1 => Some (pred, succ, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s27920 :: " string "
+
+
+\<comment> \<open>\<open>val _s2774_ : string -> maybe ((sopw * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2774 :: " string \<Rightarrow>(sopw*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2774 s27760 = (
+ (case ((shiftiwop_mnemonic_matches_prefix s27760)) of
+ Some ((op1, s27770)) =>
+ (case ((string_drop s27760 s27770)) of
+ s27780 =>
+ (case ((spc_matches_prefix0 s27780)) of
+ Some ((_, s27790)) =>
+ (case ((string_drop s27780 s27790)) of
+ s27800 =>
+ (case ((reg_name_matches_prefix s27800 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27810)) =>
+ (case ((string_drop s27800 s27810)) of
+ s27820 =>
+ (case ((sep_matches_prefix s27820)) of
+ Some ((_, s27830)) =>
+ (case ((string_drop s27820 s27830)) of
+ s27840 =>
+ (case ((reg_name_matches_prefix s27840 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27850)) =>
+ (case ((string_drop s27840 s27850)) of
+ s27860 =>
+ (case ((sep_matches_prefix s27860)) of
+ Some ((_, s27870)) =>
+ (case ((string_drop s27860 s27870)) of
+ s27880 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27880 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s27890)) =>
+ (case ((string_drop s27880 s27890)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27760 :: " string "
+
+
+\<comment> \<open>\<open>val _s2757_ : string -> maybe ((ropw * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2757 :: " string \<Rightarrow>(ropw*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2757 s27590 = (
+ (case ((rtypew_mnemonic_matches_prefix s27590)) of
+ Some ((op1, s27600)) =>
+ (case ((string_drop s27590 s27600)) of
+ s27610 =>
+ (case ((spc_matches_prefix0 s27610)) of
+ Some ((_, s27620)) =>
+ (case ((string_drop s27610 s27620)) of
+ s27630 =>
+ (case ((reg_name_matches_prefix s27630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27640)) =>
+ (case ((string_drop s27630 s27640)) of
+ s27650 =>
+ (case ((sep_matches_prefix s27650)) of
+ Some ((_, s27660)) =>
+ (case ((string_drop s27650 s27660)) of
+ s27670 =>
+ (case ((reg_name_matches_prefix s27670 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27680)) =>
+ (case ((string_drop s27670 s27680)) of
+ s27690 =>
+ (case ((sep_matches_prefix s27690)) of
+ Some ((_, s27700)) =>
+ (case ((string_drop s27690 s27700)) of
+ s27710 =>
+ (case ((reg_name_matches_prefix s27710 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s27720)) =>
+ (case ((string_drop s27710 s27720)) of
+ s1 => Some (op1, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27590 :: " string "
+
+
+\<comment> \<open>\<open>val _s2740_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2740 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2740 s27420 = (
+ (case ((shiftw_mnemonic_matches_prefix s27420)) of
+ Some ((op1, s27430)) =>
+ (case ((string_drop s27420 s27430)) of
+ s27440 =>
+ (case ((spc_matches_prefix0 s27440)) of
+ Some ((_, s27450)) =>
+ (case ((string_drop s27440 s27450)) of
+ s27460 =>
+ (case ((reg_name_matches_prefix s27460 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27470)) =>
+ (case ((string_drop s27460 s27470)) of
+ s27480 =>
+ (case ((sep_matches_prefix s27480)) of
+ Some ((_, s27490)) =>
+ (case ((string_drop s27480 s27490)) of
+ s27500 =>
+ (case ((reg_name_matches_prefix s27500 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27510)) =>
+ (case ((string_drop s27500 s27510)) of
+ s27520 =>
+ (case ((sep_matches_prefix s27520)) of
+ Some ((_, s27530)) =>
+ (case ((string_drop s27520 s27530)) of
+ s27540 =>
+ (case ((hex_bits_5_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27540 :: (( 5 Word.word * ii)) option)) of
+ Some ((shamt, s27550)) =>
+ (case ((string_drop s27540 s27550)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s27420 :: " string "
+
+
+\<comment> \<open>\<open>val _s2724_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2724 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2724 s27250 = (
+ (let s27260 = s27250 in
+ if ((string_startswith s27260 (''addiw''))) then
+ (case ((string_drop s27260 ((string_length (''addiw''))))) of
+ s27270 =>
+ (case ((spc_matches_prefix0 s27270)) of
+ Some ((_, s27280)) =>
+ (case ((string_drop s27270 s27280)) of
+ s27290 =>
+ (case ((reg_name_matches_prefix s27290 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s27300)) =>
+ (case ((string_drop s27290 s27300)) of
+ s27310 =>
+ (case ((sep_matches_prefix s27310)) of
+ Some ((_, s27320)) =>
+ (case ((string_drop s27310 s27320)) of
+ s27330 =>
+ (case ((reg_name_matches_prefix s27330 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27340)) =>
+ (case ((string_drop s27330 s27340)) of
+ s27350 =>
+ (case ((sep_matches_prefix s27350)) of
+ Some ((_, s27360)) =>
+ (case ((string_drop s27350 s27360)) of
+ s27370 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27370 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s27380)) =>
+ (case ((string_drop s27370 s27380)) of s1 => Some (rd, rs1, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s27250 :: " string "
+
+
+\<comment> \<open>\<open>val _s2696_ : string -> maybe ((word_width * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))\<close>\<close>
+
+definition s2696 :: " string \<Rightarrow>(word_width*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word*string)option " where
+ " s2696 s26970 = (
+ (let s26980 = s26970 in
+ if ((string_startswith s26980 (''s''))) then
+ (case ((string_drop s26980 ((string_length (''s''))))) of
+ s26990 =>
+ (case ((size_mnemonic_matches_prefix s26990)) of
+ Some ((size1, s27000)) =>
+ (case ((string_drop s26990 s27000)) of
+ s27010 =>
+ (case ((maybe_aq_matches_prefix s27010)) of
+ Some ((aq, s27020)) =>
+ (case ((string_drop s27010 s27020)) of
+ s27030 =>
+ (case ((maybe_rl_matches_prefix s27030)) of
+ Some ((rl, s27040)) =>
+ (case ((string_drop s27030 s27040)) of
+ s27050 =>
+ (case ((spc_matches_prefix0 s27050)) of
+ Some ((_, s27060)) =>
+ (case ((string_drop s27050 s27060)) of
+ s27070 =>
+ (case ((reg_name_matches_prefix s27070 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s27080)) =>
+ (case ((string_drop s27070 s27080)) of
+ s27090 =>
+ (case ((sep_matches_prefix s27090)) of
+ Some ((_, s27100)) =>
+ (case ((string_drop s27090 s27100)) of
+ s27110 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s27110 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s27120)) =>
+ (case ((string_drop s27110 s27120)) of
+ s27130 =>
+ (case ((opt_spc_matches_prefix0 s27130)) of
+ Some ((_, s27140)) =>
+ (let s27150 = (string_drop s27130 s27140) in
+ if ((string_startswith s27150 (''(''))) then
+ (case ((string_drop s27150 ((string_length (''(''))))) of
+ s27160 =>
+ (case ((opt_spc_matches_prefix0 s27160)) of
+ Some ((_, s27170)) =>
+ (case ((string_drop s27160 s27170)) of
+ s27180 =>
+ (case ((reg_name_matches_prefix s27180 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s27190)) =>
+ (case ((string_drop s27180 s27190)) of
+ s27200 =>
+ (case ((opt_spc_matches_prefix0 s27200)) of
+ Some ((_, s27210)) =>
+ (let s27220 = (string_drop s27200 s27210) in
+ if ((string_startswith s27220 ('')''))) then
+ (case ((string_drop s27220 ((string_length ('')''))))) of
+ s1 =>
+ Some (size1, aq, rl, rs2, imm, rs1, s1)
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s26970 :: " string "
+
+
+\<comment> \<open>\<open>val _s2666_ : string -> maybe ((word_width * bool * bool * bool * mword ty5 * mword ty12 * mword ty5 * string))\<close>\<close>
+
+definition s2666 :: " string \<Rightarrow>(word_width*bool*bool*bool*(5)Word.word*(12)Word.word*(5)Word.word*string)option " where
+ " s2666 s26670 = (
+ (let s26680 = s26670 in
+ if ((string_startswith s26680 (''l''))) then
+ (case ((string_drop s26680 ((string_length (''l''))))) of
+ s26690 =>
+ (case ((size_mnemonic_matches_prefix s26690)) of
+ Some ((size1, s26700)) =>
+ (case ((string_drop s26690 s26700)) of
+ s26710 =>
+ (case ((maybe_u_matches_prefix s26710)) of
+ Some ((is_unsigned, s26720)) =>
+ (case ((string_drop s26710 s26720)) of
+ s26730 =>
+ (case ((maybe_aq_matches_prefix s26730)) of
+ Some ((aq, s26740)) =>
+ (case ((string_drop s26730 s26740)) of
+ s26750 =>
+ (case ((maybe_rl_matches_prefix s26750)) of
+ Some ((rl, s26760)) =>
+ (case ((string_drop s26750 s26760)) of
+ s26770 =>
+ (case ((spc_matches_prefix0 s26770)) of
+ Some ((_, s26780)) =>
+ (case ((string_drop s26770 s26780)) of
+ s26790 =>
+ (case ((reg_name_matches_prefix s26790 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26800)) =>
+ (case ((string_drop s26790 s26800)) of
+ s26810 =>
+ (case ((sep_matches_prefix s26810)) of
+ Some ((_, s26820)) =>
+ (case ((string_drop s26810 s26820)) of
+ s26830 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26830 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s26840)) =>
+ (case ((string_drop s26830 s26840)) of
+ s26850 =>
+ (case ((opt_spc_matches_prefix0 s26850)) of
+ Some ((_, s26860)) =>
+ (let s26870 = (string_drop s26850 s26860) in
+ if ((string_startswith s26870 (''(''))) then
+ (case ((string_drop s26870 ((string_length (''(''))))) of
+ s26880 =>
+ (case ((opt_spc_matches_prefix0 s26880)) of
+ Some ((_, s26890)) =>
+ (case ((string_drop s26880 s26890)) of
+ s26900 =>
+ (case ((reg_name_matches_prefix s26900 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26910)) =>
+ (case ((string_drop s26900 s26910)) of
+ s26920 =>
+ (case ((opt_spc_matches_prefix0 s26920)) of
+ Some ((_, s26930)) =>
+ (let s26940 = (string_drop s26920 s26930) in
+ if ((string_startswith s26940 ('')''))) then
+ (case ((string_drop s26940 ((string_length ('')''))))) of
+ s1 =>
+ Some (size1, is_unsigned, aq, rl, rd, imm, rs1, s1)
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ ) else None)
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s26670 :: " string "
+
+
+\<comment> \<open>\<open>val _s2649_ : string -> maybe ((rop * mword ty5 * mword ty5 * mword ty5 * string))\<close>\<close>
+
+definition s2649 :: " string \<Rightarrow>(rop*(5)Word.word*(5)Word.word*(5)Word.word*string)option " where
+ " s2649 s26510 = (
+ (case ((rtype_mnemonic_matches_prefix s26510)) of
+ Some ((op1, s26520)) =>
+ (case ((string_drop s26510 s26520)) of
+ s26530 =>
+ (case ((spc_matches_prefix0 s26530)) of
+ Some ((_, s26540)) =>
+ (case ((string_drop s26530 s26540)) of
+ s26550 =>
+ (case ((reg_name_matches_prefix s26550 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26560)) =>
+ (case ((string_drop s26550 s26560)) of
+ s26570 =>
+ (case ((sep_matches_prefix s26570)) of
+ Some ((_, s26580)) =>
+ (case ((string_drop s26570 s26580)) of
+ s26590 =>
+ (case ((reg_name_matches_prefix s26590 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26600)) =>
+ (case ((string_drop s26590 s26600)) of
+ s26610 =>
+ (case ((sep_matches_prefix s26610)) of
+ Some ((_, s26620)) =>
+ (case ((string_drop s26610 s26620)) of
+ s26630 =>
+ (case ((reg_name_matches_prefix s26630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s26640)) =>
+ (case ((string_drop s26630 s26640)) of
+ s1 => Some (op1, rd, rs1, rs2, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26510 :: " string "
+
+
+\<comment> \<open>\<open>val _s2632_ : string -> maybe ((sop * mword ty5 * mword ty5 * mword ty6 * string))\<close>\<close>
+
+definition s2632 :: " string \<Rightarrow>(sop*(5)Word.word*(5)Word.word*(6)Word.word*string)option " where
+ " s2632 s26340 = (
+ (case ((shiftiop_mnemonic_matches_prefix s26340)) of
+ Some ((op1, s26350)) =>
+ (case ((string_drop s26340 s26350)) of
+ s26360 =>
+ (case ((spc_matches_prefix0 s26360)) of
+ Some ((_, s26370)) =>
+ (case ((string_drop s26360 s26370)) of
+ s26380 =>
+ (case ((reg_name_matches_prefix s26380 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26390)) =>
+ (case ((string_drop s26380 s26390)) of
+ s26400 =>
+ (case ((sep_matches_prefix s26400)) of
+ Some ((_, s26410)) =>
+ (case ((string_drop s26400 s26410)) of
+ s26420 =>
+ (case ((reg_name_matches_prefix s26420 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26430)) =>
+ (case ((string_drop s26420 s26430)) of
+ s26440 =>
+ (case ((sep_matches_prefix s26440)) of
+ Some ((_, s26450)) =>
+ (case ((string_drop s26440 s26450)) of
+ s26460 =>
+ (case ((hex_bits_6_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26460 :: (( 6 Word.word * ii)) option)) of
+ Some ((shamt, s26470)) =>
+ (case ((string_drop s26460 s26470)) of
+ s1 => Some (op1, rd, rs1, shamt, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26340 :: " string "
+
+
+\<comment> \<open>\<open>val _s2615_ : string -> maybe ((iop * mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2615 :: " string \<Rightarrow>(iop*(5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2615 s26170 = (
+ (case ((itype_mnemonic_matches_prefix s26170)) of
+ Some ((op1, s26180)) =>
+ (case ((string_drop s26170 s26180)) of
+ s26190 =>
+ (case ((spc_matches_prefix0 s26190)) of
+ Some ((_, s26200)) =>
+ (case ((string_drop s26190 s26200)) of
+ s26210 =>
+ (case ((reg_name_matches_prefix s26210 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s26220)) =>
+ (case ((string_drop s26210 s26220)) of
+ s26230 =>
+ (case ((sep_matches_prefix s26230)) of
+ Some ((_, s26240)) =>
+ (case ((string_drop s26230 s26240)) of
+ s26250 =>
+ (case ((reg_name_matches_prefix s26250 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26260)) =>
+ (case ((string_drop s26250 s26260)) of
+ s26270 =>
+ (case ((sep_matches_prefix s26270)) of
+ Some ((_, s26280)) =>
+ (case ((string_drop s26270 s26280)) of
+ s26290 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26290 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s26300)) =>
+ (case ((string_drop s26290 s26300)) of
+ s1 => Some (op1, rd, rs1, imm, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26170 :: " string "
+
+
+\<comment> \<open>\<open>val _s2598_ : string -> maybe ((bop * mword ty5 * mword ty5 * mword ty13 * string))\<close>\<close>
+
+definition s2598 :: " string \<Rightarrow>(bop*(5)Word.word*(5)Word.word*(13)Word.word*string)option " where
+ " s2598 s26000 = (
+ (case ((btype_mnemonic_matches_prefix s26000)) of
+ Some ((op1, s26010)) =>
+ (case ((string_drop s26000 s26010)) of
+ s26020 =>
+ (case ((spc_matches_prefix0 s26020)) of
+ Some ((_, s26030)) =>
+ (case ((string_drop s26020 s26030)) of
+ s26040 =>
+ (case ((reg_name_matches_prefix s26040 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s26050)) =>
+ (case ((string_drop s26040 s26050)) of
+ s26060 =>
+ (case ((sep_matches_prefix s26060)) of
+ Some ((_, s26070)) =>
+ (case ((string_drop s26060 s26070)) of
+ s26080 =>
+ (case ((reg_name_matches_prefix s26080 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs2, s26090)) =>
+ (case ((string_drop s26080 s26090)) of
+ s26100 =>
+ (case ((sep_matches_prefix s26100)) of
+ Some ((_, s26110)) =>
+ (case ((string_drop s26100 s26110)) of
+ s26120 =>
+ (case ((hex_bits_13_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s26120 :: (( 13 Word.word * ii)) option)) of
+ Some ((imm, s26130)) =>
+ (case ((string_drop s26120 s26130)) of
+ s1 => Some (op1, rs1, rs2, imm, s1)
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s26000 :: " string "
+
+
+\<comment> \<open>\<open>val _s2582_ : string -> maybe ((mword ty5 * mword ty5 * mword ty12 * string))\<close>\<close>
+
+definition s2582 :: " string \<Rightarrow>((5)Word.word*(5)Word.word*(12)Word.word*string)option " where
+ " s2582 s25830 = (
+ (let s25840 = s25830 in
+ if ((string_startswith s25840 (''jalr''))) then
+ (case ((string_drop s25840 ((string_length (''jalr''))))) of
+ s25850 =>
+ (case ((spc_matches_prefix0 s25850)) of
+ Some ((_, s25860)) =>
+ (case ((string_drop s25850 s25860)) of
+ s25870 =>
+ (case ((reg_name_matches_prefix s25870 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25880)) =>
+ (case ((string_drop s25870 s25880)) of
+ s25890 =>
+ (case ((sep_matches_prefix s25890)) of
+ Some ((_, s25900)) =>
+ (case ((string_drop s25890 s25900)) of
+ s25910 =>
+ (case ((reg_name_matches_prefix s25910 :: (( 5 Word.word * ii)) option)) of
+ Some ((rs1, s25920)) =>
+ (case ((string_drop s25910 s25920)) of
+ s25930 =>
+ (case ((sep_matches_prefix s25930)) of
+ Some ((_, s25940)) =>
+ (case ((string_drop s25930 s25940)) of
+ s25950 =>
+ (case ((hex_bits_12_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25950 :: (( 12 Word.word * ii)) option)) of
+ Some ((imm, s25960)) =>
+ (case ((string_drop s25950 s25960)) of s1 => Some (rd, rs1, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25830 :: " string "
+
+
+\<comment> \<open>\<open>val _s2570_ : string -> maybe ((mword ty5 * mword ty21 * string))\<close>\<close>
+
+definition s2570 :: " string \<Rightarrow>((5)Word.word*(21)Word.word*string)option " where
+ " s2570 s25710 = (
+ (let s25720 = s25710 in
+ if ((string_startswith s25720 (''jal''))) then
+ (case ((string_drop s25720 ((string_length (''jal''))))) of
+ s25730 =>
+ (case ((spc_matches_prefix0 s25730)) of
+ Some ((_, s25740)) =>
+ (case ((string_drop s25730 s25740)) of
+ s25750 =>
+ (case ((reg_name_matches_prefix s25750 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25760)) =>
+ (case ((string_drop s25750 s25760)) of
+ s25770 =>
+ (case ((sep_matches_prefix s25770)) of
+ Some ((_, s25780)) =>
+ (case ((string_drop s25770 s25780)) of
+ s25790 =>
+ (case ((hex_bits_21_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25790 :: (( 21 Word.word * ii)) option)) of
+ Some ((imm, s25800)) =>
+ (case ((string_drop s25790 s25800)) of s1 => Some (rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ else None))"
+ for s25710 :: " string "
+
+
+\<comment> \<open>\<open>val _s2557_ : string -> maybe ((uop * mword ty5 * mword ty20 * string))\<close>\<close>
+
+definition s2557 :: " string \<Rightarrow>(uop*(5)Word.word*(20)Word.word*string)option " where
+ " s2557 s25590 = (
+ (case ((utype_mnemonic_matches_prefix s25590)) of
+ Some ((op1, s25600)) =>
+ (case ((string_drop s25590 s25600)) of
+ s25610 =>
+ (case ((spc_matches_prefix0 s25610)) of
+ Some ((_, s25620)) =>
+ (case ((string_drop s25610 s25620)) of
+ s25630 =>
+ (case ((reg_name_matches_prefix s25630 :: (( 5 Word.word * ii)) option)) of
+ Some ((rd, s25640)) =>
+ (case ((string_drop s25630 s25640)) of
+ s25650 =>
+ (case ((sep_matches_prefix s25650)) of
+ Some ((_, s25660)) =>
+ (case ((string_drop s25650 s25660)) of
+ s25670 =>
+ (case ((hex_bits_20_matches_prefix
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict
+ s25670 :: (( 20 Word.word * ii)) option)) of
+ Some ((imm, s25680)) =>
+ (case ((string_drop s25670 s25680)) of s1 => Some (op1, rd, imm, s1) )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ )
+ )
+ | _ => None
+ ))"
+ for s25590 :: " string "
+
+
+definition assembly_matches_prefix :: " string \<Rightarrow>(ast*int)option " where
+ " assembly_matches_prefix arg1 = (
+ (let s25690 = arg1 in
+ if ((case ((s2557 s25690 :: ((uop * 5 Word.word * 20 Word.word * string))option)) of
+ Some ((op1, rd, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2557 s25690 :: (( uop * 5 Word.word * 20 Word.word * string)) option) of
+ (Some ((op1, rd, imm, s1))) =>
+ Some (UTYPE (imm, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2570 s25690 :: (( 5 Word.word * 21 Word.word * string))option)) of
+ Some ((rd, imm, s1)) => True
+ | _ => False
+ )) then (case (s2570 s25690 :: (( 5 Word.word * 21 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (RISCV_JAL (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2582 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((rd, rs1, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2582 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((rd, rs1, imm, s1))) =>
+ Some
+ (RISCV_JALR (imm, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2598 s25690 :: ((bop * 5 Word.word * 5 Word.word * 13 Word.word * string))option)) of
+ Some ((op1, rs1, rs2, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2598 s25690 :: (( bop * 5 Word.word * 5 Word.word * 13 Word.word * string)) option) of
+ (Some ((op1, rs1, rs2, imm, s1))) =>
+ Some
+ (BTYPE (imm, rs2, rs1, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2615 s25690 :: ((iop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, imm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2615 s25690 :: (( iop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, imm, s1))) =>
+ Some
+ (ITYPE (imm, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2632 s25690 :: ((sop * 5 Word.word * 5 Word.word * 6 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => True
+ | _ => False
+ )) then (case
+ (s2632 s25690 :: (( sop * 5 Word.word * 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTIOP (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2649 s25690 :: ((rop * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2649 s25690 :: (( rop * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, rs2, s1))) =>
+ Some
+ (RTYPE (rs2, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2666 s25690
+ :: ((word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, is_unsigned, aq, rl, rd, imm, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2666 s25690
+ :: (( word_width * bool * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, is_unsigned, aq, rl, rd, imm, rs1, s1))) =>
+ Some
+ (LOAD (imm, rs1, rd, is_unsigned, size1, aq, rl),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2696 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rs2, imm, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2696 s25690
+ :: (( word_width * bool * bool * 5 Word.word * 12 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rs2, imm, rs1, s1))) =>
+ Some
+ (STORE (imm, rs2, rs1, size1, aq, rl),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2724 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((rd, rs1, imm, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2724 s25690 :: (( 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((rd, rs1, imm, s1))) =>
+ Some (ADDIW (imm, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2740 s25690 :: ((sop * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2740 s25690 :: (( sop * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTW (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2757 s25690 :: ((ropw * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, rs2, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2757 s25690 :: (( ropw * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, rs2, s1))) =>
+ Some
+ (RTYPEW (rs2, rs1, rd, op1), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2774 s25690 :: ((sopw * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, rd, rs1, shamt, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2774 s25690 :: (( sopw * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, shamt, s1))) =>
+ Some
+ (SHIFTIWOP (shamt, rs1, rd, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2791 s25690 :: (( 4 Word.word * 4 Word.word * string))option)) of
+ Some ((pred, succ, s1)) => True
+ | _ => False
+ )) then (case (s2791 s25690 :: (( 4 Word.word * 4 Word.word * string)) option) of
+ (Some ((pred, succ, s1))) =>
+ Some (FENCE (pred, succ), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2803 s25690 :: (( 4 Word.word * 4 Word.word * string))option)) of
+ Some ((pred, succ, s1)) => True
+ | _ => False
+ )) then (case (s2803 s25690 :: (( 4 Word.word * 4 Word.word * string)) option) of
+ (Some ((pred, succ, s1))) =>
+ Some (FENCE_TSO (pred, succ), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2815 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2815 s25690 of
+ (Some (s1)) =>
+ Some (FENCEI () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2819 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2819 s25690 of
+ (Some (s1)) =>
+ Some (ECALL () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2823 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2823 s25690 of
+ (Some (s1)) =>
+ Some (MRET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2827 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2827 s25690 of
+ (Some (s1)) =>
+ Some (SRET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2831 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2831 s25690 of
+ (Some (s1)) =>
+ Some (EBREAK () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2835 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2835 s25690 of
+ (Some (s1)) =>
+ Some (WFI () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2839 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case (s2839 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rs1, rs2, s1))) =>
+ Some (SFENCE_VMA (rs1, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2851 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rd, rs1, s1)) => True
+ | _ => False
+ )) then (case
+ (s2851 s25690 :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rd, rs1, s1))) =>
+ Some
+ (LOADRES (aq, rl, rs1, size1, rd), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s2869 s25690
+ :: ((word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((size1, aq, rl, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2869 s25690
+ :: (( word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((size1, aq, rl, rd, rs1, rs2, s1))) =>
+ Some
+ (STORECON (aq, rl, rs2, rs1, size1, rd),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2891 s25690
+ :: ((amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((op1, width, aq, rl, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s2891 s25690
+ :: (( amoop * word_width * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((op1, width, aq, rl, rd, rs1, rs2, s1))) =>
+ Some
+ (AMO (op1, aq, rl, rs2, rs1, width, rd),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2915 s25690)) of Some (s1) => True | _ => False )) then
+ (case s2915 s25690 of
+ (Some (s1)) =>
+ Some (C_NOP () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2919 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rdc, nzimm, s1)) => (nzimm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))
+ | _ => False
+ )) then (case (s2919 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rdc, nzimm, s1))) =>
+ Some
+ (C_ADDI4SPN (rdc, nzimm), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2931 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rdc, rsc, uimm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2931 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rdc, rsc, uimm, s1))) =>
+ Some (C_LW (uimm, rsc, rdc), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2947 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rdc, rsc, uimm, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2947 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rdc, rsc, uimm, s1))) =>
+ Some (C_LD (uimm, rsc, rdc), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2963 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rsc1, rsc2, uimm, s1)) => True
+ | _ => False
+ )) then (case
+ (s2963 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsc1, rsc2, uimm, s1))) =>
+ Some
+ (C_SW (uimm, rsc1, rsc2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2979 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string))option)) of
+ Some ((rsc1, rsc2, uimm, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s2979 s25690 :: (( 3 Word.word * 3 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsc1, rsc2, uimm, s1))) =>
+ Some
+ (C_SD (uimm, rsc1, rsc2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s2995 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, nzi, s1)) =>
+ ((((nzi \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s2995 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, nzi, s1))) =>
+ Some (C_ADDI (nzi, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3007 s25690 :: (( 11 Word.word * string))option)) of
+ Some ((imm, s1)) => ((( 64 :: int)::ii) = (( 32 :: int)::ii))
+ | _ => False
+ )) then (case (s3007 s25690 :: (( 11 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_JAL imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3015 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, imm, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3015 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, imm, s1))) =>
+ Some (C_ADDIW (imm, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3027 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, imm, s1)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3027 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (C_LI (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3039 s25690 :: (( 6 Word.word * string))option)) of
+ Some ((imm, s1)) => (imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3039 s25690 :: (( 6 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_ADDI16SP imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3047 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, imm, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno sp))))) \<and> (((imm \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))
+ | _ => False
+ )) then (case (s3047 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, imm, s1))) =>
+ Some (C_LUI (imm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3059 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3059 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SRLI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3071 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) => (shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))
+ | _ => False
+ )) then (case (s3071 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SRAI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3083 s25690 :: (( 3 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, imm, s1)) => True
+ | _ => False
+ )) then (case (s3083 s25690 :: (( 3 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, imm, s1))) =>
+ Some (C_ANDI (imm, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3095 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3095 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_SUB (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3107 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3107 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_XOR (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3119 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3119 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_OR (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3131 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => True
+ | _ => False
+ )) then (case (s3131 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_AND (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3143 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3143 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_SUBW (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3155 s25690 :: (( 3 Word.word * 3 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3155 s25690 :: (( 3 Word.word * 3 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_ADDW (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3167 s25690 :: (( 11 Word.word * string))option)) of
+ Some ((imm, s1)) => True
+ | _ => False
+ )) then (case (s3167 s25690 :: (( 11 Word.word * string)) option) of
+ (Some ((imm, s1))) =>
+ Some (C_J imm, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3175 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rs, imm, s1)) => True
+ | _ => False
+ )) then (case (s3175 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rs, imm, s1))) =>
+ Some (C_BEQZ (imm, rs), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3187 s25690 :: (( 3 Word.word * 8 Word.word * string))option)) of
+ Some ((rs, imm, s1)) => True
+ | _ => False
+ )) then (case (s3187 s25690 :: (( 3 Word.word * 8 Word.word * string)) option) of
+ (Some ((rs, imm, s1))) =>
+ Some (C_BNEZ (imm, rs), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3199 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rsd, shamt, s1)) =>
+ ((((shamt \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3199 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rsd, shamt, s1))) =>
+ Some (C_SLLI (shamt, rsd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3211 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) => (((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3211 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_LWSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3223 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> ((((( 64 :: int)::ii) = (( 64 :: int)::ii)))))
+ | _ => False
+ )) then (case (s3223 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_LDSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3235 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rd, uimm, s1)) => True
+ | _ => False
+ )) then (case (s3235 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rd, uimm, s1))) =>
+ Some (C_SWSP (uimm, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3247 s25690 :: (( 5 Word.word * 6 Word.word * string))option)) of
+ Some ((rs2, uimm, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case (s3247 s25690 :: (( 5 Word.word * 6 Word.word * string)) option) of
+ (Some ((rs2, uimm, s1))) =>
+ Some (C_SDSP (uimm, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3259 s25690 :: (( 5 Word.word * string))option)) of
+ Some ((rs1, s1)) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3259 s25690 :: (( 5 Word.word * string)) option) of
+ (Some ((rs1, s1))) =>
+ Some (C_JR rs1, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3267 s25690 :: (( 5 Word.word * string))option)) of
+ Some ((rs1, s1)) => (((regidx_to_regno rs1)) \<noteq> ((regidx_to_regno zreg)))
+ | _ => False
+ )) then (case (s3267 s25690 :: (( 5 Word.word * string)) option) of
+ (Some ((rs1, s1))) =>
+ Some (C_JALR rs1, ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3275 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rd, rs2, s1)) =>
+ ((((((regidx_to_regno rd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3275 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rd, rs2, s1))) =>
+ Some (C_MV (rd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3287 s25690)) of Some (s1) => True | _ => False )) then
+ (case s3287 s25690 of
+ (Some (s1)) =>
+ Some (C_EBREAK () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3291 s25690 :: (( 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rsd, rs2, s1)) =>
+ ((((((regidx_to_regno rsd)) \<noteq> ((regidx_to_regno zreg))))) \<and> (((((regidx_to_regno rs2)) \<noteq> ((regidx_to_regno zreg))))))
+ | _ => False
+ )) then (case (s3291 s25690 :: (( 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rsd, rs2, s1))) =>
+ Some (C_ADD (rsd, rs2), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3303 s25690
+ :: ((bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((high, signed1, signed2, rd, rs1, rs2, s1)) => True
+ | _ => False
+ )) then (case
+ (s3303 s25690 :: (( bool * bool * bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((high, signed1, signed2, rd, rs1, rs2, s1))) =>
+ Some
+ (MUL (rs2, rs1, rd, high, signed1, signed2),
+ ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3320 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => True
+ | _ => False
+ )) then (case
+ (s3320 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (DIV (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3338 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => True
+ | _ => False
+ )) then (case
+ (s3338 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (REM (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3356 s25690 :: (( 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((rd, rs1, rs2, s1)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3356 s25690 :: (( 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((rd, rs1, rs2, s1))) =>
+ Some (MULW (rs2, rs1, rd), ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3372 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3372 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (DIVW (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3391 s25690 :: ((bool * 5 Word.word * 5 Word.word * 5 Word.word * string))option)) of
+ Some ((s, rd, rs1, rs2, s2)) => ((( 64 :: int)::ii) = (( 64 :: int)::ii))
+ | _ => False
+ )) then (case
+ (s3391 s25690 :: (( bool * 5 Word.word * 5 Word.word * 5 Word.word * string)) option) of
+ (Some ((s, rd, rs1, rs2, s2))) =>
+ Some (REMW (rs2, rs1, rd, s), ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3410 s25690 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, csr, s1)) => True
+ | _ => False
+ )) then (case
+ (s3410 s25690 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, csr, s1))) =>
+ Some
+ (CSR (csr, rs1, rd, True, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s3428 s25690 :: ((csrop * 5 Word.word * 5 Word.word * 12 Word.word * string))option)) of
+ Some ((op1, rd, rs1, csr, s1)) => True
+ | _ => False
+ )) then (case
+ (s3428 s25690 :: (( csrop * 5 Word.word * 5 Word.word * 12 Word.word * string)) option) of
+ (Some ((op1, rd, rs1, csr, s1))) =>
+ Some
+ (CSR (csr, rs1, rd, False, op1), ((string_length arg1)) -
+ ((string_length s1)))
+ )
+ else if ((case ((s3445 s25690)) of Some (s1) => True | _ => False )) then
+ (case s3445 s25690 of
+ (Some (s1)) =>
+ Some (URET () , ((string_length arg1)) - ((string_length s1)))
+ )
+ else if ((case ((s3449 s25690 :: (( 32 Word.word * string))option)) of
+ Some ((s, s2)) => True
+ | _ => False
+ )) then (case (s3449 s25690 :: (( 32 Word.word * string)) option) of
+ (Some ((s, s2))) =>
+ Some (ILLEGAL s, ((string_length arg1)) - ((string_length s2)))
+ )
+ else if ((case ((s3457 s25690 :: (( 16 Word.word * string))option)) of
+ Some ((s, s2)) => True
+ | _ => False
+ )) then (case (s3457 s25690 :: (( 16 Word.word * string)) option) of
+ (Some ((s, s2))) =>
+ Some (C_ILLEGAL s, ((string_length arg1)) - ((string_length s2)))
+ )
+ else None))"
+ for arg1 :: " string "
+
+
+definition print_insn :: " ast \<Rightarrow>((register_value),(string),(exception))monad " where
+ " print_insn insn = ( assembly_forwards insn )"
+ for insn :: " ast "
+
+
+\<comment> \<open>\<open>val decode : mword ty32 -> M ast\<close>\<close>
+
+definition decode :: "(32)Word.word \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " decode bv = ( encdec_backwards bv )"
+ for bv :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val decodeCompressed : mword ty16 -> ast\<close>\<close>
+
+definition decodeCompressed :: "(16)Word.word \<Rightarrow> ast " where
+ " decodeCompressed bv = ( encdec_compressed_backwards bv )"
+ for bv :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val ext_init : unit -> unit\<close>\<close>
+
+definition ext_init :: " unit \<Rightarrow> unit " where
+ " ext_init _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_fetch_hook : FetchResult -> FetchResult\<close>\<close>
+
+definition ext_fetch_hook :: " FetchResult \<Rightarrow> FetchResult " where
+ " ext_fetch_hook f = ( f )"
+ for f :: " FetchResult "
+
+
+\<comment> \<open>\<open>val ext_pre_step_hook : unit -> unit\<close>\<close>
+
+definition ext_pre_step_hook :: " unit \<Rightarrow> unit " where
+ " ext_pre_step_hook _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_post_step_hook : unit -> unit\<close>\<close>
+
+definition ext_post_step_hook :: " unit \<Rightarrow> unit " where
+ " ext_post_step_hook _ = ( () )"
+
+
+\<comment> \<open>\<open>val ext_post_decode_hook : ast -> M ast\<close>\<close>
+
+definition ext_post_decode_hook :: " ast \<Rightarrow>((register_value),(ast),(exception))monad " where
+ " ext_post_decode_hook x = ( return x )"
+ for x :: " ast "
+
+
+\<comment> \<open>\<open>val isRVC : mword ty16 -> bool\<close>\<close>
+
+definition isRVC :: "(16)Word.word \<Rightarrow> bool " where
+ " isRVC h = (
+ \<not> (((((subrange_vec_dec h (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))"
+ for h :: "(16)Word.word "
+
+
+\<comment> \<open>\<open>val fetch : unit -> M FetchResult\<close>\<close>
+
+definition fetch :: " unit \<Rightarrow>((register_value),(FetchResult),(exception))monad " where
+ " fetch _ = (
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (case ((ext_fetch_check_pc w__0 w__1)) of
+ Ext_FetchAddr_Error (e) => return (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc) =>
+ or_boolM
+ (return (((((cast_unit_vec0 ((access_vec_dec use_pc (( 0 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))
+ (and_boolM
+ (return (((((cast_unit_vec0 ((access_vec_dec use_pc (( 1 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))
+ (haveRVC () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))) \<bind> (\<lambda> (w__4 :: bool) .
+ if w__4 then
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) .
+ return (F_Error (E_Fetch_Addr_Align, w__5)))
+ else
+ (translateAddr use_pc Execute :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__6 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__6 of
+ TR_Failure (e) =>
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ return (F_Error (e, w__7)))
+ | TR_Address (ppclo) =>
+ (mem_read Execute ppclo (( 2 :: int)::ii) False False False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__8 :: ( 16 Word.word)
+ MemoryOpResult) .
+ (case w__8 of
+ MemException (e) =>
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) .
+ return (F_Error (E_Fetch_Access_Fault, w__9)))
+ | MemValue (ilo) =>
+ if ((isRVC ilo)) then return (F_RVC ilo)
+ else
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) .
+ (let (PC_hi :: xlenbits) = ((add_vec_int w__10 (( 2 :: int)::ii) :: 64 Word.word)) in
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 Word.word) .
+ (case ((ext_fetch_check_pc w__11 PC_hi)) of
+ Ext_FetchAddr_Error (e) => return (F_Ext_Error e)
+ | Ext_FetchAddr_OK (use_pc_hi) =>
+ (translateAddr use_pc_hi Execute :: ( (( 64 Word.word), ExceptionType)TR_Result) M) \<bind> (\<lambda> (w__12 :: (( 64 Word.word), ExceptionType)
+ TR_Result) .
+ (case w__12 of
+ TR_Failure (e) => return (F_Error (e, PC_hi))
+ | TR_Address (ppchi) =>
+ (mem_read Execute ppchi (( 2 :: int)::ii) False False False
+ :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__13 :: ( 16 Word.word)
+ MemoryOpResult) .
+ return ((case w__13 of
+ MemException (e) => F_Error (E_Fetch_Access_Fault, PC_hi)
+ | MemValue (ihi) => F_Base ((concat_vec ihi ilo :: 32 Word.word))
+ )))
+ ))
+ ))))
+ ))
+ )))
+ ))))"
+
+
+\<comment> \<open>\<open>val step : ii -> M bool\<close>\<close>
+
+definition step :: " int \<Rightarrow>((register_value),(bool),(exception))monad " where
+ " step step_no = (
+ (let (_ :: unit) = (ext_pre_step_hook () ) in
+ (write_reg minstret_written_ref False \<then>
+ read_reg cur_privilege_ref) \<bind> (\<lambda> (w__0 :: Privilege) .
+ dispatchInterrupt w__0 \<bind> (\<lambda> (w__1 :: ((InterruptType * Privilege))option) .
+ (case w__1 of
+ Some ((intr, priv)) =>
+ (let (_ :: unit) =
+ (if ((get_config_print_instr () )) then
+ print_bits0 (''Handling interrupt: '') ((interruptType_to_bits intr :: 8 Word.word))
+ else () ) in
+ handle_interrupt intr priv \<then> return (RETIRE_FAIL, False))
+ | None =>
+ fetch () \<bind> (\<lambda> (w__2 :: FetchResult) .
+ (let (f :: FetchResult) = (ext_fetch_hook w__2) in
+ (case f of
+ F_Ext_Error (e) =>
+ (let (_ :: unit) = (ext_handle_fetch_check_error e) in
+ return (RETIRE_FAIL, False))
+ | F_Error ((e, addr)) => handle_mem_exception addr e \<then> return (RETIRE_FAIL, False)
+ | F_RVC (h) =>
+ (let ast = (decodeCompressed h) in
+ ((if ((get_config_print_instr () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__3 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) .
+ print_insn ast \<bind> (\<lambda> (w__5 :: string) .
+ return ((print_dbg
+ (((@) (''['')
+ (((@) ((stringFromInteger step_no))
+ (((@) (''] ['')
+ (((@) ((privLevel_to_str w__3))
+ (((@) ('']: '')
+ (((@) ((string_of_bits w__4))
+ (((@) ('' ('')
+ (((@) ((string_of_bits h))
+ (((@) ('') '') w__5)))))))))))))))))))))))
+ else return () ) \<then>
+ haveRVC () ) \<bind> (\<lambda> (w__6 :: bool) .
+ if w__6 then
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) .
+ (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii) :: 64 Word.word)) \<then>
+ ext_post_decode_hook ast) \<bind> (\<lambda> (w__8 :: ast) .
+ execute w__8 \<bind> (\<lambda> (w__9 :: Retired) . return (w__9, True))))
+ else handle_illegal () \<then> return (RETIRE_FAIL, True)))
+ | F_Base (w) =>
+ decode w \<bind> (\<lambda> ast .
+ ((if ((get_config_print_instr () )) then
+ read_reg cur_privilege_ref \<bind> (\<lambda> (w__11 :: Privilege) .
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) .
+ print_insn ast \<bind> (\<lambda> (w__13 :: string) .
+ return ((print_dbg
+ (((@) (''['')
+ (((@) ((stringFromInteger step_no))
+ (((@) (''] ['')
+ (((@) ((privLevel_to_str w__11))
+ (((@) ('']: '')
+ (((@) ((string_of_bits w__12))
+ (((@) ('' ('')
+ (((@) ((string_of_bits w))
+ (((@) ('') '') w__13)))))))))))))))))))))))
+ else return () ) \<then>
+ (read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) .
+ (write_reg nextPC_ref ((add_vec_int w__14 (( 4 :: int)::ii) :: 64 Word.word)) \<then>
+ ext_post_decode_hook ast) \<bind> (\<lambda> (w__15 :: ast) .
+ execute w__15 \<bind> (\<lambda> (w__16 :: Retired) . return (w__16, True)))))
+ )))
+ ) \<bind> (\<lambda> varstup . (let ((retired :: Retired), (stepped :: bool)) = varstup in
+ (tick_pc () \<then>
+ (case retired of RETIRE_SUCCESS => retire_instruction () | RETIRE_FAIL => return () )) \<then>
+ ((let (_ :: unit) = (ext_post_step_hook () ) in
+ return stepped))))))))"
+ for step_no :: " int "
+
+
+\<comment> \<open>\<open>val loop : unit -> M unit\<close>\<close>
+
+definition loop :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " loop _ = (
+ (let insns_per_tick = (plat_insns_per_tick () ) in
+ (let (i :: ii) = ((( 0 :: int)::ii)) in
+ (let (step_no :: ii) = ((( 0 :: int)::ii)) in
+ (whileM (i, step_no)
+ (\<lambda> varstup . (let (i, step_no) = varstup in
+ read_reg htif_done_ref \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0)))))
+ (\<lambda> varstup . (let (i, step_no) = varstup in
+ step step_no \<bind> (\<lambda> stepped .
+ (let (step_no :: ii) = (if stepped then step_no + (( 1 :: int)::ii) else step_no) in
+ read_reg htif_done_ref \<bind> (\<lambda> (w__1 :: bool) .
+ (if w__1 then
+ (read_reg htif_exit_code_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) .
+ (let exit_val = (Word.uint w__2) in
+ return ((let _ =
+ (if (((exit_val = (( 0 :: int)::ii)))) then print_endline (''SUCCESS'')
+ else print_int (''FAILURE: '') exit_val) in
+ i))))
+ else
+ (let i = (i + (( 1 :: int)::ii)) in
+ if (((i = insns_per_tick))) then (tick_clock () \<then> tick_platform () ) \<then> return (( 0 :: int)::ii)
+ else return i)) \<bind> (\<lambda> (i :: ii) .
+ return (i, step_no)))))))) \<bind> (\<lambda> varstup . (let ((i :: ii), (step_no :: ii)) = varstup in
+ return () ))))))"
+
+
+\<comment> \<open>\<open>val init_model : unit -> M unit\<close>\<close>
+
+definition init_model :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where
+ " init_model _ = (
+ ((init_platform () \<then>
+ init_sys () ) \<then>
+ init_vmem () ) \<then>
+ ((let (_ :: unit) = (ext_init () ) in
+ ext_init_regs () )))"
+
+
+definition GPRstr :: "(string)list " where
+ " GPRstr = (
+ [(''x31''),(''x30''),(''x29''),(''x28''),(''x27''),(''x26''),(''x25''),(''x24''),(''x23''),(''x22''),(''x21''),(''x20''),(''x19''),(''x18''),(''x17''),(''x16''),
+ (''x15''),(''x14''),(''x13''),(''x12''),(''x11''),(''x10''),(''x9''),(''x8''),(''x7''),(''x6''),(''x5''),(''x4''),(''x3''),(''x2''),(''x1''),(''x0'')])"
+
+
+definition CIA_fp :: " regfp " where
+ " CIA_fp = ( RFull (''CIA''))"
+
+
+definition NIA_fp :: " regfp " where
+ " NIA_fp = ( RFull (''NIA''))"
+
+
+\<comment> \<open>\<open>val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)\<close>\<close>
+
+definition initial_analysis :: " ast \<Rightarrow>((register_value),((regfp)list*(regfp)list*(regfp)list*(niafp)list*diafp*instruction_kind),(exception))monad " where
+ " initial_analysis instr = (
+ (let iR = ([]) in
+ (let oR = ([]) in
+ (let aR = ([]) in
+ (let ik = (IK_simple () ) in
+ (let Nias = ([NIAFP_successor () ]) in
+ (let Dia = (DIAFP_none () ) in
+ (case instr of
+ EBREAK (_) => return (Nias, aR, iR, ik, oR)
+ | UTYPE ((imm, rd, op1)) =>
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR))
+ | RISCV_JAL ((imm, rd)) =>
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) .
+ (let (Nias :: niafp list) = ([NIAFP_concrete_address ((add_vec w__0 offset :: 64 Word.word))]) in
+ (let (ik :: instruction_kind) = (IK_branch () ) in
+ return (Nias, aR, iR, ik, oR))))))
+ | RISCV_JALR ((imm, rs, rd)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ (let (Nias :: niafp list) = ([NIAFP_indirect_address () ]) in
+ (let (ik :: instruction_kind) = (IK_branch () ) in
+ return (Nias, aR, iR, ik, oR))))))
+ | BTYPE ((imm, rs2, rs1, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let ik = (IK_branch () ) in
+ (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in
+ (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) .
+ (let (Nias :: niafp list) =
+ ([NIAFP_concrete_address ((add_vec w__1 offset :: 64 Word.word)),NIAFP_successor () ]) in
+ return (Nias, aR, iR, ik, oR)))))))
+ | ITYPE ((imm, rs, rd, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR)))
+ | SHIFTIOP ((imm, rs, rd, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR)))
+ | RTYPE ((rs2, rs1, rd, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR))))
+ | CSR ((csr, rs1, rd, is_imm, op1)) =>
+ (let (isWrite :: bool) =
+ ((case op1 of
+ CSRRW => True
+ | _ => if is_imm then (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii))
+ )) in
+ (let (iR :: regfp list) = ((RFull ((csr_name csr))) # iR) in
+ (let (iR :: regfp list) =
+ (if ((\<not> is_imm)) then (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR
+ else iR) in
+ (let (oR :: regfp list) = (if isWrite then (RFull ((csr_name csr))) # oR else oR) in
+ (let (oR :: regfp list) = ((RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR))))))
+ | LOAD ((imm, rs, rd, unsign, width, aq, rl)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (let aR = iR in
+ (case (aq, rl) of
+ (False, False) => return (IK_mem_read Read_plain)
+ | (True, False) => return (IK_mem_read Read_RISCV_acquire)
+ | (True, True) => return (IK_mem_read Read_RISCV_strong_acquire)
+ | _ => internal_error (''LOAD type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__3 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__3 in
+ return (Nias, aR, iR, ik, oR))))))
+ | STORE ((imm, rs2, rs1, width, aq, rl)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (aR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # aR) in
+ (case (aq, rl) of
+ (False, False) => return (IK_mem_write Write_plain)
+ | (False, True) => return (IK_mem_write Write_RISCV_release)
+ | (True, True) => return (IK_mem_write Write_RISCV_strong_release)
+ | _ => internal_error (''STORE type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__5 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__5 in
+ return (Nias, aR, iR, ik, oR))))))
+ | ADDIW ((imm, rs, rd)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR)))
+ | SHIFTW ((imm, rs, rd, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR)))
+ | RTYPEW ((rs2, rs1, rd, op1)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ return (Nias, aR, iR, ik, oR))))
+ | FENCE ((pred, succ)) =>
+ (case (pred, succ) of
+ (v__838, v__839) =>
+ if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_rw_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_r_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_r_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_rw_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_w_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_w_rw)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_rw_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_r_w)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_w_r)
+ else if ((((((((subrange_vec_dec v__838 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__839 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then
+ return (IK_simple () )
+ else internal_error (''barrier type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__17 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__17 in
+ return (Nias, aR, iR, ik, oR)))
+ | FENCE_TSO ((pred, succ)) =>
+ (case (pred, succ) of
+ (v__878, v__879) =>
+ if ((((((((subrange_vec_dec v__878 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__879 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then
+ return (IK_barrier Barrier_RISCV_tso)
+ else internal_error (''barrier type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__20 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__20 in
+ return (Nias, aR, iR, ik, oR)))
+ | FENCEI (_) =>
+ (let (ik :: instruction_kind) = (IK_simple () ) in
+ return (Nias, aR, iR, ik, oR))
+ | LOADRES ((aq, rl, rs1, width, rd)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (let aR = iR in
+ (case (aq, rl) of
+ (False, False) => return (IK_mem_read Read_RISCV_reserved)
+ | (True, False) => return (IK_mem_read Read_RISCV_reserved_acquire)
+ | (True, True) => return (IK_mem_read Read_RISCV_reserved_strong_acquire)
+ | (False, True) => internal_error (''LOADRES type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__22 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__22 in
+ return (Nias, aR, iR, ik, oR))))))
+ | STORECON ((aq, rl, rs2, rs1, width, rd)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (aR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # aR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (case (aq, rl) of
+ (False, False) => return (IK_mem_write Write_RISCV_conditional)
+ | (False, True) => return (IK_mem_write Write_RISCV_conditional_release)
+ | (True, True) => return (IK_mem_write Write_RISCV_conditional_strong_release)
+ | (True, False) => internal_error (''STORECON type not implemented in initial_analysis'')
+ ) \<bind> (\<lambda> (w__24 :: instruction_kind) .
+ (let (ik :: instruction_kind) = w__24 in
+ return (Nias, aR, iR, ik, oR)))))))
+ | AMO ((op1, aq, rl, rs2, rs1, width, rd)) =>
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs2)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs2))))) # iR) in
+ (let (iR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then iR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # iR) in
+ (let (aR :: regfp list) =
+ (if (((((regidx_to_regno rs1)) = (( 0 :: int)::ii)))) then aR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rs1))))) # aR) in
+ (let (oR :: regfp list) =
+ (if (((((regidx_to_regno rd)) = (( 0 :: int)::ii)))) then oR
+ else (RFull ((access_list_dec GPRstr ((regidx_to_regno rd))))) # oR) in
+ (let (ik :: instruction_kind) =
+ ((case (aq, rl) of
+ (False, False) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional)
+ | (False, True) => IK_mem_rmw (Read_RISCV_reserved, Write_RISCV_conditional_release)
+ | (True, False) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional)
+ | (True, True) => IK_mem_rmw (Read_RISCV_reserved_acquire, Write_RISCV_conditional_release)
+ )) in
+ return (Nias, aR, iR, ik, oR))))))
+ | _ => return (Nias, aR, iR, ik, oR)
+ ) \<bind> (\<lambda> varstup . (let ((Nias :: niafp list), (aR :: regfp list), (iR :: regfp list), (ik ::
+ instruction_kind), (oR :: regfp list)) = varstup in
+ return (iR, oR, aR, Nias, Dia, ik))))))))))"
+ for instr :: " ast "
+
+
+
+end
diff --git a/prover_snapshots/isabelle/RV64/RiscvAuxiliary.thy b/prover_snapshots/isabelle/RV64/RiscvAuxiliary.thy
new file mode 100644
index 0000000..1d09558
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/RiscvAuxiliary.thy
@@ -0,0 +1,37 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV64/riscv.lem\<close>.\<close>
+
+theory "RiscvAuxiliary"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+ "Riscv_types"
+ "Riscv_extras"
+ "Riscv"
+
+begin
+
+
+\<comment> \<open>\<open>**************************************************\<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> Termination Proofs \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open>**************************************************\<close>\<close>
+
+termination n_leading_spaces0 by lexicographic_order
+
+termination walk39 by lexicographic_order
+
+termination walk48 by lexicographic_order
+
+termination execute by lexicographic_order
+
+
+
+end
diff --git a/prover_snapshots/isabelle/RV64/Riscv_extras.thy b/prover_snapshots/isabelle/RV64/Riscv_extras.thy
new file mode 100644
index 0000000..3b3515c
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/Riscv_extras.thy
@@ -0,0 +1,362 @@
+chapter \<open>Generated by Lem from \<open>handwritten_support/riscv_extras.lem\<close>.\<close>
+
+theory "Riscv_extras"
+
+imports
+ Main
+ "LEM.Lem_pervasives"
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+
+type_synonym 'a bitvector =" ( 'a::len)Word.word "
+
+definition MEM_fence_rw_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_rw _ = ( barrier Barrier_RISCV_rw_rw )"
+
+definition MEM_fence_r_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_rw _ = ( barrier Barrier_RISCV_r_rw )"
+
+definition MEM_fence_r_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_r _ = ( barrier Barrier_RISCV_r_r )"
+
+definition MEM_fence_rw_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_w _ = ( barrier Barrier_RISCV_rw_w )"
+
+definition MEM_fence_w_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_w _ = ( barrier Barrier_RISCV_w_w )"
+
+definition MEM_fence_w_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_rw _ = ( barrier Barrier_RISCV_w_rw )"
+
+definition MEM_fence_rw_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_rw_r _ = ( barrier Barrier_RISCV_rw_r )"
+
+definition MEM_fence_r_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_r_w _ = ( barrier Barrier_RISCV_r_w )"
+
+definition MEM_fence_w_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_w_r _ = ( barrier Barrier_RISCV_w_r )"
+
+definition MEM_fence_tso :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_tso _ = ( barrier Barrier_RISCV_tso )"
+
+definition MEM_fence_i :: " unit \<Rightarrow>('b,(unit),'a)monad " where
+ " MEM_fence_i _ = ( barrier Barrier_RISCV_i )"
+
+
+\<comment> \<open>\<open>val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+
+definition MEMea :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_strong_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_conditional addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " MEMea_conditional_release addr size1 = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+definition MEMea_conditional_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad "
+ where
+ " MEMea_conditional_strong_release addr size1
+ = ( write_mem_ea
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release () addr size1 )"
+ for addr :: "('a::len)Word.word "
+ and size1 :: " int "
+
+
+\<comment> \<open>\<open>val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e\<close>\<close>
+
+definition MEMr :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_strong_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMr_reserved_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where
+ " MEMr_reserved_strong_acquire addrsize size1 hexRAM addr = ( read_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val MEMw : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+\<comment> \<open>\<open>val MEMw_conditional_strong_release : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv bool 'e\<close>\<close>
+
+definition MEMw :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_strong_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_strong_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+definition MEMw_conditional_strong_release :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(bool),'e)monad " where
+ " MEMw_conditional_strong_release addrsize size1 hexRAM addr = ( write_mem
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addrsize addr size1 )"
+ for addrsize :: " int "
+ and size1 :: " int "
+ and hexRAM :: "('a::len)Word.word "
+ and addr :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit\<close>\<close>
+definition load_reservation :: "('a::len)Word.word \<Rightarrow> unit " where
+ " load_reservation addr = ( () )"
+ for addr :: "('a::len)Word.word "
+
+
+definition speculate_conditional_success :: " unit \<Rightarrow>('b,(bool),'a)monad " where
+ " speculate_conditional_success _ = ( excl_result () )"
+
+
+definition match_reservation :: " 'a \<Rightarrow> bool " where
+ " match_reservation _ = ( True )"
+
+definition cancel_reservation :: " unit \<Rightarrow> unit " where
+ " cancel_reservation _ = ( () )"
+
+
+\<comment> \<open>\<open>val sys_enable_writable_misa : unit -> bool\<close>\<close>
+definition sys_enable_writable_misa :: " unit \<Rightarrow> bool " where
+ " sys_enable_writable_misa _ = ( True )"
+
+
+\<comment> \<open>\<open>val sys_enable_rvc : unit -> bool\<close>\<close>
+definition sys_enable_rvc :: " unit \<Rightarrow> bool " where
+ " sys_enable_rvc _ = ( True )"
+
+
+\<comment> \<open>\<open>val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_ram_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_ram_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_ram_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_ram_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_rom_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_rom_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_rom_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_rom_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_clint_base :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_clint_base _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_clint_size :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_clint_size _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_enable_dirty_update : unit -> bool\<close>\<close>
+definition plat_enable_dirty_update :: " unit \<Rightarrow> bool " where
+ " plat_enable_dirty_update _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_enable_misaligned_access : unit -> bool\<close>\<close>
+definition plat_enable_misaligned_access :: " unit \<Rightarrow> bool " where
+ " plat_enable_misaligned_access _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_enable_pmp : unit -> bool\<close>\<close>
+definition plat_enable_pmp :: " unit \<Rightarrow> bool " where
+ " plat_enable_pmp _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_mtval_has_illegal_inst_bits : unit -> bool\<close>\<close>
+definition plat_mtval_has_illegal_inst_bits :: " unit \<Rightarrow> bool " where
+ " plat_mtval_has_illegal_inst_bits _ = ( False )"
+
+
+\<comment> \<open>\<open>val plat_insns_per_tick : unit -> integer\<close>\<close>
+definition plat_insns_per_tick :: " unit \<Rightarrow> int " where
+ " plat_insns_per_tick _ = (( 1 :: int))"
+
+
+\<comment> \<open>\<open>val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_htif_tohost :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_htif_tohost _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit\<close>\<close>
+definition plat_term_write :: "('a::len)Word.word \<Rightarrow> unit " where
+ " plat_term_write _ = ( () )"
+
+
+\<comment> \<open>\<open>val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a\<close>\<close>
+definition plat_term_read :: " unit \<Rightarrow>('a::len)Word.word " where
+ " plat_term_read _ = ( Word.word_of_int(( 0 :: int)))"
+
+
+\<comment> \<open>\<open>val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a\<close>\<close>
+definition shift_bits_right :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " shift_bits_right v m = ( shiftr v (Word.uint m))"
+ for v :: "('a::len)Word.word "
+ and m :: "('b::len)Word.word "
+
+\<comment> \<open>\<open>val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a\<close>\<close>
+definition shift_bits_left :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " shift_bits_left v m = ( shiftl v (Word.uint m))"
+ for v :: "('a::len)Word.word "
+ and m :: "('b::len)Word.word "
+
+
+\<comment> \<open>\<open>val print_string : string -> string -> unit\<close>\<close>
+definition print_string :: " string \<Rightarrow> string \<Rightarrow> unit " where
+ " print_string msg s = ( () )"
+ for msg :: " string "
+ and s :: " string "
+ \<comment> \<open>\<open> print_endline (msg ^ s) \<close>\<close>
+
+\<comment> \<open>\<open>val prerr_string : string -> string -> unit\<close>\<close>
+definition prerr_string :: " string \<Rightarrow> string \<Rightarrow> unit " where
+ " prerr_string msg s = ( prerr_endline (msg @ s))"
+ for msg :: " string "
+ and s :: " string "
+
+
+\<comment> \<open>\<open>val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit\<close>\<close>
+definition prerr_bits :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where
+ " prerr_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))"
+ for msg :: " string "
+ and bs :: "('a::len)Word.word "
+
+
+\<comment> \<open>\<open>val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit\<close>\<close>
+definition print_bits0 :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where
+ " print_bits0 msg bs = ( () )"
+ for msg :: " string "
+ and bs :: "('a::len)Word.word "
+ \<comment> \<open>\<open> print_endline (msg ^ (show_bitlist (bits_of bs))) \<close>\<close>
+
+\<comment> \<open>\<open>val print_dbg : string -> unit\<close>\<close>
+definition print_dbg :: " string \<Rightarrow> unit " where
+ " print_dbg msg = ( () )"
+ for msg :: " string "
+
+end
diff --git a/prover_snapshots/isabelle/RV64/Riscv_lemmas.thy b/prover_snapshots/isabelle/RV64/Riscv_lemmas.thy
new file mode 100644
index 0000000..f7b88bd
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/Riscv_lemmas.thy
@@ -0,0 +1,995 @@
+theory Riscv_lemmas
+ imports
+ Sail.Sail2_values_lemmas
+ Sail.Sail2_state_lemmas
+ Riscv
+begin
+
+abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)"
+
+lemmas register_defs = get_regval_def set_regval_def satp_ref_def tlb48_ref_def tlb39_ref_def
+ htif_exit_code_ref_def htif_done_ref_def htif_tohost_ref_def mtimecmp_ref_def utval_ref_def
+ ucause_ref_def uepc_ref_def uscratch_ref_def utvec_ref_def pmpaddr15_ref_def pmpaddr14_ref_def
+ pmpaddr13_ref_def pmpaddr12_ref_def pmpaddr11_ref_def pmpaddr10_ref_def pmpaddr9_ref_def
+ pmpaddr8_ref_def pmpaddr7_ref_def pmpaddr6_ref_def pmpaddr5_ref_def pmpaddr4_ref_def
+ pmpaddr3_ref_def pmpaddr2_ref_def pmpaddr1_ref_def pmpaddr0_ref_def pmp15cfg_ref_def
+ pmp14cfg_ref_def pmp13cfg_ref_def pmp12cfg_ref_def pmp11cfg_ref_def pmp10cfg_ref_def
+ pmp9cfg_ref_def pmp8cfg_ref_def pmp7cfg_ref_def pmp6cfg_ref_def pmp5cfg_ref_def pmp4cfg_ref_def
+ pmp3cfg_ref_def pmp2cfg_ref_def pmp1cfg_ref_def pmp0cfg_ref_def tselect_ref_def stval_ref_def
+ scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def sideleg_ref_def sedeleg_ref_def
+ mhartid_ref_def marchid_ref_def mimpid_ref_def mvendorid_ref_def minstret_written_ref_def
+ minstret_ref_def mtime_ref_def mcycle_ref_def scounteren_ref_def mcounteren_ref_def
+ mscratch_ref_def mtval_ref_def mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def
+ mideleg_ref_def mie_ref_def mip_ref_def mstatus_ref_def misa_ref_def cur_inst_ref_def
+ cur_privilege_ref_def x31_ref_def x30_ref_def x29_ref_def x28_ref_def x27_ref_def x26_ref_def
+ x25_ref_def x24_ref_def x23_ref_def x22_ref_def x21_ref_def x20_ref_def x19_ref_def x18_ref_def
+ x17_ref_def x16_ref_def x15_ref_def x14_ref_def x13_ref_def x12_ref_def x11_ref_def x10_ref_def
+ x9_ref_def x8_ref_def x7_ref_def x6_ref_def x5_ref_def x4_ref_def x3_ref_def x2_ref_def x1_ref_def
+ Xs_ref_def instbits_ref_def nextPC_ref_def PC_ref_def
+
+lemma regval_Counteren[simp]:
+ "Counteren_of_regval (regval_of_Counteren v) = Some v"
+ by (auto simp: regval_of_Counteren_def)
+
+lemma regval_Mcause[simp]:
+ "Mcause_of_regval (regval_of_Mcause v) = Some v"
+ by (auto simp: regval_of_Mcause_def)
+
+lemma regval_Medeleg[simp]:
+ "Medeleg_of_regval (regval_of_Medeleg v) = Some v"
+ by (auto simp: regval_of_Medeleg_def)
+
+lemma regval_Minterrupts[simp]:
+ "Minterrupts_of_regval (regval_of_Minterrupts v) = Some v"
+ by (auto simp: regval_of_Minterrupts_def)
+
+lemma regval_Misa[simp]:
+ "Misa_of_regval (regval_of_Misa v) = Some v"
+ by (auto simp: regval_of_Misa_def)
+
+lemma regval_Mstatus[simp]:
+ "Mstatus_of_regval (regval_of_Mstatus v) = Some v"
+ by (auto simp: regval_of_Mstatus_def)
+
+lemma regval_Mtvec[simp]:
+ "Mtvec_of_regval (regval_of_Mtvec v) = Some v"
+ by (auto simp: regval_of_Mtvec_def)
+
+lemma regval_Pmpcfg_ent[simp]:
+ "Pmpcfg_ent_of_regval (regval_of_Pmpcfg_ent v) = Some v"
+ by (auto simp: regval_of_Pmpcfg_ent_def)
+
+lemma regval_Privilege[simp]:
+ "Privilege_of_regval (regval_of_Privilege v) = Some v"
+ by (auto simp: regval_of_Privilege_def)
+
+lemma regval_Sedeleg[simp]:
+ "Sedeleg_of_regval (regval_of_Sedeleg v) = Some v"
+ by (auto simp: regval_of_Sedeleg_def)
+
+lemma regval_Sinterrupts[simp]:
+ "Sinterrupts_of_regval (regval_of_Sinterrupts v) = Some v"
+ by (auto simp: regval_of_Sinterrupts_def)
+
+lemma regval_TLB_Entry_16_39_56_64[simp]:
+ "TLB_Entry_16_39_56_64_of_regval (regval_of_TLB_Entry_16_39_56_64 v) = Some v"
+ by (auto simp: regval_of_TLB_Entry_16_39_56_64_def)
+
+lemma regval_TLB_Entry_16_48_56_64[simp]:
+ "TLB_Entry_16_48_56_64_of_regval (regval_of_TLB_Entry_16_48_56_64 v) = Some v"
+ by (auto simp: regval_of_TLB_Entry_16_48_56_64_def)
+
+lemma regval_bool[simp]:
+ "bool_of_regval (regval_of_bool v) = Some v"
+ by (auto simp: regval_of_bool_def)
+
+lemma regval_vector_32_dec_bit[simp]:
+ "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v"
+ by (auto simp: regval_of_vector_32_dec_bit_def)
+
+lemma regval_vector_64_dec_bit[simp]:
+ "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v"
+ by (auto simp: regval_of_vector_64_dec_bit_def)
+
+lemma vector_of_rv_rv_of_vector[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v"
+proof -
+ from assms have "of_rv \<circ> rv_of = Some" by auto
+ then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def)
+qed
+
+lemma option_of_rv_rv_of_option[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v"
+ using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def)
+
+lemma list_of_rv_rv_of_list[simp]:
+ assumes "\<And>v. of_rv (rv_of v) = Some v"
+ shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v"
+proof -
+ from assms have "of_rv \<circ> rv_of = Some" by auto
+ with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def)
+qed
+
+lemma liftS_read_reg_satp[liftState_simp]:
+ "\<lbrakk>read_reg satp_ref\<rbrakk>\<^sub>S = readS (satp \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_satp[liftState_simp]:
+ "\<lbrakk>write_reg satp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (satp_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tlb48[liftState_simp]:
+ "\<lbrakk>read_reg tlb48_ref\<rbrakk>\<^sub>S = readS (tlb48 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tlb48[liftState_simp]:
+ "\<lbrakk>write_reg tlb48_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tlb48_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tlb39[liftState_simp]:
+ "\<lbrakk>read_reg tlb39_ref\<rbrakk>\<^sub>S = readS (tlb39 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tlb39[liftState_simp]:
+ "\<lbrakk>write_reg tlb39_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tlb39_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_exit_code[liftState_simp]:
+ "\<lbrakk>read_reg htif_exit_code_ref\<rbrakk>\<^sub>S = readS (htif_exit_code \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_exit_code[liftState_simp]:
+ "\<lbrakk>write_reg htif_exit_code_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_exit_code_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_done[liftState_simp]:
+ "\<lbrakk>read_reg htif_done_ref\<rbrakk>\<^sub>S = readS (htif_done \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_done[liftState_simp]:
+ "\<lbrakk>write_reg htif_done_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_done_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_htif_tohost[liftState_simp]:
+ "\<lbrakk>read_reg htif_tohost_ref\<rbrakk>\<^sub>S = readS (htif_tohost \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_htif_tohost[liftState_simp]:
+ "\<lbrakk>write_reg htif_tohost_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_tohost_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtimecmp[liftState_simp]:
+ "\<lbrakk>read_reg mtimecmp_ref\<rbrakk>\<^sub>S = readS (mtimecmp \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtimecmp[liftState_simp]:
+ "\<lbrakk>write_reg mtimecmp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtimecmp_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_utval[liftState_simp]:
+ "\<lbrakk>read_reg utval_ref\<rbrakk>\<^sub>S = readS (utval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_utval[liftState_simp]:
+ "\<lbrakk>write_reg utval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (utval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_ucause[liftState_simp]:
+ "\<lbrakk>read_reg ucause_ref\<rbrakk>\<^sub>S = readS (ucause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_ucause[liftState_simp]:
+ "\<lbrakk>write_reg ucause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ucause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_uepc[liftState_simp]:
+ "\<lbrakk>read_reg uepc_ref\<rbrakk>\<^sub>S = readS (uepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_uepc[liftState_simp]:
+ "\<lbrakk>write_reg uepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (uepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_uscratch[liftState_simp]:
+ "\<lbrakk>read_reg uscratch_ref\<rbrakk>\<^sub>S = readS (uscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_uscratch[liftState_simp]:
+ "\<lbrakk>write_reg uscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (uscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_utvec[liftState_simp]:
+ "\<lbrakk>read_reg utvec_ref\<rbrakk>\<^sub>S = readS (utvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_utvec[liftState_simp]:
+ "\<lbrakk>write_reg utvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (utvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr15[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr15_ref\<rbrakk>\<^sub>S = readS (pmpaddr15 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr15[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr15_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr14[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr14_ref\<rbrakk>\<^sub>S = readS (pmpaddr14 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr14[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr14_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr13[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr13_ref\<rbrakk>\<^sub>S = readS (pmpaddr13 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr13[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr13_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr12[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr12_ref\<rbrakk>\<^sub>S = readS (pmpaddr12 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr12[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr12_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr11[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr11_ref\<rbrakk>\<^sub>S = readS (pmpaddr11 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr11[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr11_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr10[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr10_ref\<rbrakk>\<^sub>S = readS (pmpaddr10 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr10[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr10_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr9[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr9_ref\<rbrakk>\<^sub>S = readS (pmpaddr9 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr9[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr9_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr8[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr8_ref\<rbrakk>\<^sub>S = readS (pmpaddr8 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr8[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr8_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr7[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr7_ref\<rbrakk>\<^sub>S = readS (pmpaddr7 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr7[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr7_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr6[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr6_ref\<rbrakk>\<^sub>S = readS (pmpaddr6 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr6[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr6_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr5[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr5_ref\<rbrakk>\<^sub>S = readS (pmpaddr5 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr5[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr5_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr4[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr4_ref\<rbrakk>\<^sub>S = readS (pmpaddr4 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr4[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr4_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr3[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr3_ref\<rbrakk>\<^sub>S = readS (pmpaddr3 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr3[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr3_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr2[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr2_ref\<rbrakk>\<^sub>S = readS (pmpaddr2 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr2[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr2_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr1[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr1_ref\<rbrakk>\<^sub>S = readS (pmpaddr1 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr1[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr1_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmpaddr0[liftState_simp]:
+ "\<lbrakk>read_reg pmpaddr0_ref\<rbrakk>\<^sub>S = readS (pmpaddr0 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmpaddr0[liftState_simp]:
+ "\<lbrakk>write_reg pmpaddr0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp15cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp15cfg_ref\<rbrakk>\<^sub>S = readS (pmp15cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp15cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp15cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp15cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp14cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp14cfg_ref\<rbrakk>\<^sub>S = readS (pmp14cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp14cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp14cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp14cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp13cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp13cfg_ref\<rbrakk>\<^sub>S = readS (pmp13cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp13cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp13cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp13cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp12cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp12cfg_ref\<rbrakk>\<^sub>S = readS (pmp12cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp12cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp12cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp12cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp11cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp11cfg_ref\<rbrakk>\<^sub>S = readS (pmp11cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp11cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp11cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp11cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp10cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp10cfg_ref\<rbrakk>\<^sub>S = readS (pmp10cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp10cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp10cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp10cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp9cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp9cfg_ref\<rbrakk>\<^sub>S = readS (pmp9cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp9cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp9cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp9cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp8cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp8cfg_ref\<rbrakk>\<^sub>S = readS (pmp8cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp8cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp8cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp8cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp7cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp7cfg_ref\<rbrakk>\<^sub>S = readS (pmp7cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp7cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp7cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp7cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp6cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp6cfg_ref\<rbrakk>\<^sub>S = readS (pmp6cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp6cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp6cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp6cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp5cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp5cfg_ref\<rbrakk>\<^sub>S = readS (pmp5cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp5cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp5cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp5cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp4cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp4cfg_ref\<rbrakk>\<^sub>S = readS (pmp4cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp4cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp4cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp4cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp3cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp3cfg_ref\<rbrakk>\<^sub>S = readS (pmp3cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp3cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp3cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp3cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp2cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp2cfg_ref\<rbrakk>\<^sub>S = readS (pmp2cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp2cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp2cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp2cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp1cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp1cfg_ref\<rbrakk>\<^sub>S = readS (pmp1cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp1cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp1cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp1cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_pmp0cfg[liftState_simp]:
+ "\<lbrakk>read_reg pmp0cfg_ref\<rbrakk>\<^sub>S = readS (pmp0cfg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_pmp0cfg[liftState_simp]:
+ "\<lbrakk>write_reg pmp0cfg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmp0cfg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_tselect[liftState_simp]:
+ "\<lbrakk>read_reg tselect_ref\<rbrakk>\<^sub>S = readS (tselect \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_tselect[liftState_simp]:
+ "\<lbrakk>write_reg tselect_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tselect_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stval[liftState_simp]:
+ "\<lbrakk>read_reg stval_ref\<rbrakk>\<^sub>S = readS (stval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stval[liftState_simp]:
+ "\<lbrakk>write_reg stval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scause[liftState_simp]:
+ "\<lbrakk>read_reg scause_ref\<rbrakk>\<^sub>S = readS (scause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scause[liftState_simp]:
+ "\<lbrakk>write_reg scause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sepc[liftState_simp]:
+ "\<lbrakk>read_reg sepc_ref\<rbrakk>\<^sub>S = readS (sepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sepc[liftState_simp]:
+ "\<lbrakk>write_reg sepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sscratch[liftState_simp]:
+ "\<lbrakk>read_reg sscratch_ref\<rbrakk>\<^sub>S = readS (sscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sscratch[liftState_simp]:
+ "\<lbrakk>write_reg sscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_stvec[liftState_simp]:
+ "\<lbrakk>read_reg stvec_ref\<rbrakk>\<^sub>S = readS (stvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_stvec[liftState_simp]:
+ "\<lbrakk>write_reg stvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sideleg[liftState_simp]:
+ "\<lbrakk>read_reg sideleg_ref\<rbrakk>\<^sub>S = readS (sideleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sideleg[liftState_simp]:
+ "\<lbrakk>write_reg sideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sideleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_sedeleg[liftState_simp]:
+ "\<lbrakk>read_reg sedeleg_ref\<rbrakk>\<^sub>S = readS (sedeleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_sedeleg[liftState_simp]:
+ "\<lbrakk>write_reg sedeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mhartid[liftState_simp]:
+ "\<lbrakk>read_reg mhartid_ref\<rbrakk>\<^sub>S = readS (mhartid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mhartid[liftState_simp]:
+ "\<lbrakk>write_reg mhartid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mhartid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_marchid[liftState_simp]:
+ "\<lbrakk>read_reg marchid_ref\<rbrakk>\<^sub>S = readS (marchid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_marchid[liftState_simp]:
+ "\<lbrakk>write_reg marchid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (marchid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mimpid[liftState_simp]:
+ "\<lbrakk>read_reg mimpid_ref\<rbrakk>\<^sub>S = readS (mimpid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mimpid[liftState_simp]:
+ "\<lbrakk>write_reg mimpid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mimpid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mvendorid[liftState_simp]:
+ "\<lbrakk>read_reg mvendorid_ref\<rbrakk>\<^sub>S = readS (mvendorid \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mvendorid[liftState_simp]:
+ "\<lbrakk>write_reg mvendorid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret_written[liftState_simp]:
+ "\<lbrakk>read_reg minstret_written_ref\<rbrakk>\<^sub>S = readS (minstret_written \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret_written[liftState_simp]:
+ "\<lbrakk>write_reg minstret_written_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_written_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_minstret[liftState_simp]:
+ "\<lbrakk>read_reg minstret_ref\<rbrakk>\<^sub>S = readS (minstret \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_minstret[liftState_simp]:
+ "\<lbrakk>write_reg minstret_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtime[liftState_simp]:
+ "\<lbrakk>read_reg mtime_ref\<rbrakk>\<^sub>S = readS (mtime \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtime[liftState_simp]:
+ "\<lbrakk>write_reg mtime_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtime_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcycle[liftState_simp]:
+ "\<lbrakk>read_reg mcycle_ref\<rbrakk>\<^sub>S = readS (mcycle \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcycle[liftState_simp]:
+ "\<lbrakk>write_reg mcycle_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcycle_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_scounteren[liftState_simp]:
+ "\<lbrakk>read_reg scounteren_ref\<rbrakk>\<^sub>S = readS (scounteren \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_scounteren[liftState_simp]:
+ "\<lbrakk>write_reg scounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scounteren_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcounteren[liftState_simp]:
+ "\<lbrakk>read_reg mcounteren_ref\<rbrakk>\<^sub>S = readS (mcounteren \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcounteren[liftState_simp]:
+ "\<lbrakk>write_reg mcounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcounteren_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mscratch[liftState_simp]:
+ "\<lbrakk>read_reg mscratch_ref\<rbrakk>\<^sub>S = readS (mscratch \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mscratch[liftState_simp]:
+ "\<lbrakk>write_reg mscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mscratch_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtval[liftState_simp]:
+ "\<lbrakk>read_reg mtval_ref\<rbrakk>\<^sub>S = readS (mtval \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtval[liftState_simp]:
+ "\<lbrakk>write_reg mtval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtval_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mepc[liftState_simp]:
+ "\<lbrakk>read_reg mepc_ref\<rbrakk>\<^sub>S = readS (mepc \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mepc[liftState_simp]:
+ "\<lbrakk>write_reg mepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mepc_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mcause[liftState_simp]:
+ "\<lbrakk>read_reg mcause_ref\<rbrakk>\<^sub>S = readS (mcause \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mcause[liftState_simp]:
+ "\<lbrakk>write_reg mcause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcause_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mtvec[liftState_simp]:
+ "\<lbrakk>read_reg mtvec_ref\<rbrakk>\<^sub>S = readS (mtvec \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mtvec[liftState_simp]:
+ "\<lbrakk>write_reg mtvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtvec_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_medeleg[liftState_simp]:
+ "\<lbrakk>read_reg medeleg_ref\<rbrakk>\<^sub>S = readS (medeleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_medeleg[liftState_simp]:
+ "\<lbrakk>write_reg medeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (medeleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mideleg[liftState_simp]:
+ "\<lbrakk>read_reg mideleg_ref\<rbrakk>\<^sub>S = readS (mideleg \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mideleg[liftState_simp]:
+ "\<lbrakk>write_reg mideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mideleg_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mie[liftState_simp]:
+ "\<lbrakk>read_reg mie_ref\<rbrakk>\<^sub>S = readS (mie \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mie[liftState_simp]:
+ "\<lbrakk>write_reg mie_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mie_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mip[liftState_simp]:
+ "\<lbrakk>read_reg mip_ref\<rbrakk>\<^sub>S = readS (mip \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mip[liftState_simp]:
+ "\<lbrakk>write_reg mip_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mip_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_mstatus[liftState_simp]:
+ "\<lbrakk>read_reg mstatus_ref\<rbrakk>\<^sub>S = readS (mstatus \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_mstatus[liftState_simp]:
+ "\<lbrakk>write_reg mstatus_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mstatus_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_misa[liftState_simp]:
+ "\<lbrakk>read_reg misa_ref\<rbrakk>\<^sub>S = readS (misa \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_misa[liftState_simp]:
+ "\<lbrakk>write_reg misa_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (misa_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_inst[liftState_simp]:
+ "\<lbrakk>read_reg cur_inst_ref\<rbrakk>\<^sub>S = readS (cur_inst \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_cur_inst[liftState_simp]:
+ "\<lbrakk>write_reg cur_inst_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_cur_privilege[liftState_simp]:
+ "\<lbrakk>read_reg cur_privilege_ref\<rbrakk>\<^sub>S = readS (cur_privilege \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_cur_privilege[liftState_simp]:
+ "\<lbrakk>write_reg cur_privilege_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x31[liftState_simp]:
+ "\<lbrakk>read_reg x31_ref\<rbrakk>\<^sub>S = readS (x31 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x31[liftState_simp]:
+ "\<lbrakk>write_reg x31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x31_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x30[liftState_simp]:
+ "\<lbrakk>read_reg x30_ref\<rbrakk>\<^sub>S = readS (x30 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x30[liftState_simp]:
+ "\<lbrakk>write_reg x30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x30_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x29[liftState_simp]:
+ "\<lbrakk>read_reg x29_ref\<rbrakk>\<^sub>S = readS (x29 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x29[liftState_simp]:
+ "\<lbrakk>write_reg x29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x29_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x28[liftState_simp]:
+ "\<lbrakk>read_reg x28_ref\<rbrakk>\<^sub>S = readS (x28 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x28[liftState_simp]:
+ "\<lbrakk>write_reg x28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x28_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x27[liftState_simp]:
+ "\<lbrakk>read_reg x27_ref\<rbrakk>\<^sub>S = readS (x27 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x27[liftState_simp]:
+ "\<lbrakk>write_reg x27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x27_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x26[liftState_simp]:
+ "\<lbrakk>read_reg x26_ref\<rbrakk>\<^sub>S = readS (x26 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x26[liftState_simp]:
+ "\<lbrakk>write_reg x26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x26_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x25[liftState_simp]:
+ "\<lbrakk>read_reg x25_ref\<rbrakk>\<^sub>S = readS (x25 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x25[liftState_simp]:
+ "\<lbrakk>write_reg x25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x25_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x24[liftState_simp]:
+ "\<lbrakk>read_reg x24_ref\<rbrakk>\<^sub>S = readS (x24 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x24[liftState_simp]:
+ "\<lbrakk>write_reg x24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x24_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x23[liftState_simp]:
+ "\<lbrakk>read_reg x23_ref\<rbrakk>\<^sub>S = readS (x23 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x23[liftState_simp]:
+ "\<lbrakk>write_reg x23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x23_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x22[liftState_simp]:
+ "\<lbrakk>read_reg x22_ref\<rbrakk>\<^sub>S = readS (x22 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x22[liftState_simp]:
+ "\<lbrakk>write_reg x22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x22_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x21[liftState_simp]:
+ "\<lbrakk>read_reg x21_ref\<rbrakk>\<^sub>S = readS (x21 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x21[liftState_simp]:
+ "\<lbrakk>write_reg x21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x21_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x20[liftState_simp]:
+ "\<lbrakk>read_reg x20_ref\<rbrakk>\<^sub>S = readS (x20 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x20[liftState_simp]:
+ "\<lbrakk>write_reg x20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x20_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x19[liftState_simp]:
+ "\<lbrakk>read_reg x19_ref\<rbrakk>\<^sub>S = readS (x19 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x19[liftState_simp]:
+ "\<lbrakk>write_reg x19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x19_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x18[liftState_simp]:
+ "\<lbrakk>read_reg x18_ref\<rbrakk>\<^sub>S = readS (x18 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x18[liftState_simp]:
+ "\<lbrakk>write_reg x18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x18_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x17[liftState_simp]:
+ "\<lbrakk>read_reg x17_ref\<rbrakk>\<^sub>S = readS (x17 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x17[liftState_simp]:
+ "\<lbrakk>write_reg x17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x17_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x16[liftState_simp]:
+ "\<lbrakk>read_reg x16_ref\<rbrakk>\<^sub>S = readS (x16 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x16[liftState_simp]:
+ "\<lbrakk>write_reg x16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x16_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x15[liftState_simp]:
+ "\<lbrakk>read_reg x15_ref\<rbrakk>\<^sub>S = readS (x15 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x15[liftState_simp]:
+ "\<lbrakk>write_reg x15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x15_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x14[liftState_simp]:
+ "\<lbrakk>read_reg x14_ref\<rbrakk>\<^sub>S = readS (x14 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x14[liftState_simp]:
+ "\<lbrakk>write_reg x14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x14_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x13[liftState_simp]:
+ "\<lbrakk>read_reg x13_ref\<rbrakk>\<^sub>S = readS (x13 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x13[liftState_simp]:
+ "\<lbrakk>write_reg x13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x13_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x12[liftState_simp]:
+ "\<lbrakk>read_reg x12_ref\<rbrakk>\<^sub>S = readS (x12 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x12[liftState_simp]:
+ "\<lbrakk>write_reg x12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x12_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x11[liftState_simp]:
+ "\<lbrakk>read_reg x11_ref\<rbrakk>\<^sub>S = readS (x11 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x11[liftState_simp]:
+ "\<lbrakk>write_reg x11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x11_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x10[liftState_simp]:
+ "\<lbrakk>read_reg x10_ref\<rbrakk>\<^sub>S = readS (x10 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x10[liftState_simp]:
+ "\<lbrakk>write_reg x10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x10_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x9[liftState_simp]:
+ "\<lbrakk>read_reg x9_ref\<rbrakk>\<^sub>S = readS (x9 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x9[liftState_simp]:
+ "\<lbrakk>write_reg x9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x9_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x8[liftState_simp]:
+ "\<lbrakk>read_reg x8_ref\<rbrakk>\<^sub>S = readS (x8 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x8[liftState_simp]:
+ "\<lbrakk>write_reg x8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x8_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x7[liftState_simp]:
+ "\<lbrakk>read_reg x7_ref\<rbrakk>\<^sub>S = readS (x7 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x7[liftState_simp]:
+ "\<lbrakk>write_reg x7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x7_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x6[liftState_simp]:
+ "\<lbrakk>read_reg x6_ref\<rbrakk>\<^sub>S = readS (x6 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x6[liftState_simp]:
+ "\<lbrakk>write_reg x6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x6_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x5[liftState_simp]:
+ "\<lbrakk>read_reg x5_ref\<rbrakk>\<^sub>S = readS (x5 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x5[liftState_simp]:
+ "\<lbrakk>write_reg x5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x5_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x4[liftState_simp]:
+ "\<lbrakk>read_reg x4_ref\<rbrakk>\<^sub>S = readS (x4 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x4[liftState_simp]:
+ "\<lbrakk>write_reg x4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x4_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x3[liftState_simp]:
+ "\<lbrakk>read_reg x3_ref\<rbrakk>\<^sub>S = readS (x3 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x3[liftState_simp]:
+ "\<lbrakk>write_reg x3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x3_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x2[liftState_simp]:
+ "\<lbrakk>read_reg x2_ref\<rbrakk>\<^sub>S = readS (x2 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x2[liftState_simp]:
+ "\<lbrakk>write_reg x2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x2_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_x1[liftState_simp]:
+ "\<lbrakk>read_reg x1_ref\<rbrakk>\<^sub>S = readS (x1 \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_x1[liftState_simp]:
+ "\<lbrakk>write_reg x1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x1_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_Xs[liftState_simp]:
+ "\<lbrakk>read_reg Xs_ref\<rbrakk>\<^sub>S = readS (Xs \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_Xs[liftState_simp]:
+ "\<lbrakk>write_reg Xs_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Xs_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_instbits[liftState_simp]:
+ "\<lbrakk>read_reg instbits_ref\<rbrakk>\<^sub>S = readS (instbits \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_instbits[liftState_simp]:
+ "\<lbrakk>write_reg instbits_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (instbits_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_nextPC[liftState_simp]:
+ "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_nextPC[liftState_simp]:
+ "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+lemma liftS_read_reg_PC[liftState_simp]:
+ "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)"
+ by (auto simp: liftState_read_reg_readS register_defs)
+
+lemma liftS_write_reg_PC[liftState_simp]:
+ "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))"
+ by (auto simp: liftState_write_reg_updateS register_defs)
+
+end
diff --git a/prover_snapshots/isabelle/RV64/Riscv_types.thy b/prover_snapshots/isabelle/RV64/Riscv_types.thy
new file mode 100644
index 0000000..748e594
--- /dev/null
+++ b/prover_snapshots/isabelle/RV64/Riscv_types.thy
@@ -0,0 +1,2335 @@
+chapter \<open>Generated by Lem from \<open>generated_definitions/lem/RV64/riscv_types.lem\<close>.\<close>
+
+theory "Riscv_types"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail.Sail2_instr_kinds"
+ "Sail.Sail2_values"
+ "Sail.Sail2_operators_mwords"
+ "Sail.Sail2_prompt_monad"
+ "Sail.Sail2_prompt"
+ "Sail.Sail2_string"
+
+begin
+
+\<comment> \<open>\<open>Generated by Sail from riscv.\<close>\<close>
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_string\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators_mwords\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+
+
+type_synonym 'n bits =" ( 'n::len)Word.word "
+
+datatype regfp =
+ RFull " (string)"
+ | RSlice " ((string * ii * ii))"
+ | RSliceBit " ((string * ii))"
+ | RField " ((string * string))"
+
+
+
+type_synonym regfps =" regfp list "
+
+datatype niafp =
+ NIAFP_successor " (unit)"
+ | NIAFP_concrete_address " ( 64 bits)"
+ | NIAFP_indirect_address " (unit)"
+
+
+
+type_synonym niafps =" niafp list "
+
+datatype diafp = DIAFP_none " (unit)" | DIAFP_concrete " ( 64 bits)" | DIAFP_reg " (regfp)"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+type_synonym xlenbits =" 64 bits "
+
+type_synonym mem_meta =" unit "
+
+
+
+type_synonym half =" 16 bits "
+
+type_synonym word0 =" 32 bits "
+
+type_synonym regidx =" 5 bits "
+
+type_synonym cregidx =" 3 bits "
+
+type_synonym csreg =" 12 bits "
+
+type_synonym 'n regno =" int "
+
+type_synonym opcode =" 7 bits "
+
+type_synonym imm12 =" 12 bits "
+
+type_synonym imm20 =" 20 bits "
+
+type_synonym amo =" 1 bits "
+
+datatype Architecture = RV32 | RV64 | RV128
+
+
+
+type_synonym arch_xlen =" 2 bits "
+
+type_synonym priv_level =" 2 bits "
+
+datatype Privilege = User | Supervisor | Machine
+
+
+
+datatype amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU
+
+
+
+datatype bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU
+
+
+
+datatype csrop = CSRRW | CSRRS | CSRRC
+
+
+
+datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI
+
+
+
+datatype rop =
+ RISCV_ADD
+ | RISCV_SUB
+ | RISCV_SLL
+ | RISCV_SLT
+ | RISCV_SLTU
+ | RISCV_XOR
+ | RISCV_SRL
+ | RISCV_SRA
+ | RISCV_OR
+ | RISCV_AND
+
+
+
+datatype ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW
+
+
+
+datatype sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI
+
+
+
+datatype sopw = RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW
+
+
+
+datatype uop = RISCV_LUI | RISCV_AUIPC
+
+
+
+datatype word_width = BYTE | HALF | WORD | DOUBLE
+
+
+
+datatype (plugins only: size) ast =
+ UTYPE " (( 20 bits * regidx * uop))"
+ | RISCV_JAL " (( 21 bits * regidx))"
+ | RISCV_JALR " (( 12 bits * regidx * regidx))"
+ | BTYPE " (( 13 bits * regidx * regidx * bop))"
+ | ITYPE " (( 12 bits * regidx * regidx * iop))"
+ | SHIFTIOP " (( 6 bits * regidx * regidx * sop))"
+ | RTYPE " ((regidx * regidx * regidx * rop))"
+ | LOAD " (( 12 bits * regidx * regidx * bool * word_width * bool * bool))"
+ | STORE " (( 12 bits * regidx * regidx * word_width * bool * bool))"
+ | ADDIW " (( 12 bits * regidx * regidx))"
+ | SHIFTW " (( 5 bits * regidx * regidx * sop))"
+ | RTYPEW " ((regidx * regidx * regidx * ropw))"
+ | SHIFTIWOP " (( 5 bits * regidx * regidx * sopw))"
+ | FENCE " (( 4 bits * 4 bits))"
+ | FENCE_TSO " (( 4 bits * 4 bits))"
+ | FENCEI " (unit)"
+ | ECALL " (unit)"
+ | MRET " (unit)"
+ | SRET " (unit)"
+ | EBREAK " (unit)"
+ | WFI " (unit)"
+ | SFENCE_VMA " ((regidx * regidx))"
+ | LOADRES " ((bool * bool * regidx * word_width * regidx))"
+ | STORECON " ((bool * bool * regidx * regidx * word_width * regidx))"
+ | AMO " ((amoop * bool * bool * regidx * regidx * word_width * regidx))"
+ | C_NOP " (unit)"
+ | C_ADDI4SPN " ((cregidx * 8 bits))"
+ | C_LW " (( 5 bits * cregidx * cregidx))"
+ | C_LD " (( 5 bits * cregidx * cregidx))"
+ | C_SW " (( 5 bits * cregidx * cregidx))"
+ | C_SD " (( 5 bits * cregidx * cregidx))"
+ | C_ADDI " (( 6 bits * regidx))"
+ | C_JAL " ( 11 bits)"
+ | C_ADDIW " (( 6 bits * regidx))"
+ | C_LI " (( 6 bits * regidx))"
+ | C_ADDI16SP " ( 6 bits)"
+ | C_LUI " (( 6 bits * regidx))"
+ | C_SRLI " (( 6 bits * cregidx))"
+ | C_SRAI " (( 6 bits * cregidx))"
+ | C_ANDI " (( 6 bits * cregidx))"
+ | C_SUB " ((cregidx * cregidx))"
+ | C_XOR " ((cregidx * cregidx))"
+ | C_OR " ((cregidx * cregidx))"
+ | C_AND " ((cregidx * cregidx))"
+ | C_SUBW " ((cregidx * cregidx))"
+ | C_ADDW " ((cregidx * cregidx))"
+ | C_J " ( 11 bits)"
+ | C_BEQZ " (( 8 bits * cregidx))"
+ | C_BNEZ " (( 8 bits * cregidx))"
+ | C_SLLI " (( 6 bits * regidx))"
+ | C_LWSP " (( 6 bits * regidx))"
+ | C_LDSP " (( 6 bits * regidx))"
+ | C_SWSP " (( 6 bits * regidx))"
+ | C_SDSP " (( 6 bits * regidx))"
+ | C_JR " (regidx)"
+ | C_JALR " (regidx)"
+ | C_MV " ((regidx * regidx))"
+ | C_EBREAK " (unit)"
+ | C_ADD " ((regidx * regidx))"
+ | MUL " ((regidx * regidx * regidx * bool * bool * bool))"
+ | DIV " ((regidx * regidx * regidx * bool))"
+ | REM " ((regidx * regidx * regidx * bool))"
+ | MULW " ((regidx * regidx * regidx))"
+ | DIVW " ((regidx * regidx * regidx * bool))"
+ | REMW " ((regidx * regidx * regidx * bool))"
+ | CSR " (( 12 bits * regidx * regidx * bool * csrop))"
+ | URET " (unit)"
+ | ILLEGAL " (word0)"
+ | C_ILLEGAL " (half)"
+
+
+
+datatype Retired = RETIRE_SUCCESS | RETIRE_FAIL
+
+
+
+datatype AccessType = Read | Write | ReadWrite | Execute
+
+
+
+type_synonym exc_code =" 8 bits "
+
+datatype InterruptType =
+ I_U_Software
+ | I_S_Software
+ | I_M_Software
+ | I_U_Timer
+ | I_S_Timer
+ | I_M_Timer
+ | I_U_External
+ | I_S_External
+ | I_M_External
+
+
+
+datatype ExceptionType =
+ E_Fetch_Addr_Align
+ | E_Fetch_Access_Fault
+ | E_Illegal_Instr
+ | E_Breakpoint
+ | E_Load_Addr_Align
+ | E_Load_Access_Fault
+ | E_SAMO_Addr_Align
+ | E_SAMO_Access_Fault
+ | E_U_EnvCall
+ | E_S_EnvCall
+ | E_Reserved_10
+ | E_M_EnvCall
+ | E_Fetch_Page_Fault
+ | E_Load_Page_Fault
+ | E_Reserved_14
+ | E_SAMO_Page_Fault
+ | E_CHERI
+
+
+
+datatype exception = Error_not_implemented " (string)" | Error_internal_error " (unit)"
+
+
+
+type_synonym tv_mode =" 2 bits "
+
+datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved
+
+
+
+type_synonym ext_status =" 2 bits "
+
+datatype ExtStatus = Off | Initial | Clean | Dirty
+
+
+
+type_synonym satp_mode =" 4 bits "
+
+datatype SATPMode = Sbare | Sv32 | Sv39 | Sv48
+
+
+
+type_synonym csrRW =" 2 bits "
+
+type_synonym regtype =" xlenbits "
+
+record Misa =
+ Misa_Misa_chunk_0 ::" 64 Word.word "
+
+
+
+record SV48_PTE =
+ SV48_PTE_SV48_PTE_chunk_0 ::" 64 Word.word "
+
+
+
+record PTE_Bits =
+ PTE_Bits_PTE_Bits_chunk_0 ::" 8 Word.word "
+
+
+
+record Pmpcfg_ent =
+ Pmpcfg_ent_Pmpcfg_ent_chunk_0 ::" 8 Word.word "
+
+
+
+record Mstatus =
+ Mstatus_Mstatus_chunk_0 ::" 64 Word.word "
+
+
+
+record Sstatus =
+ Sstatus_Sstatus_chunk_0 ::" 64 Word.word "
+
+
+
+record Ustatus =
+ Ustatus_Ustatus_chunk_0 ::" 64 Word.word "
+
+
+
+record Minterrupts =
+ Minterrupts_Minterrupts_chunk_0 ::" 64 Word.word "
+
+
+
+record Sinterrupts =
+ Sinterrupts_Sinterrupts_chunk_0 ::" 64 Word.word "
+
+
+
+record Uinterrupts =
+ Uinterrupts_Uinterrupts_chunk_0 ::" 64 Word.word "
+
+
+
+record Medeleg =
+ Medeleg_Medeleg_chunk_0 ::" 64 Word.word "
+
+
+
+record Sedeleg =
+ Sedeleg_Sedeleg_chunk_0 ::" 64 Word.word "
+
+
+
+record Mtvec =
+ Mtvec_Mtvec_chunk_0 ::" 64 Word.word "
+
+
+
+record Satp32 =
+ Satp32_Satp32_chunk_0 ::" 32 Word.word "
+
+
+
+record Mcause =
+ Mcause_Mcause_chunk_0 ::" 64 Word.word "
+
+
+
+record Counteren =
+ Counteren_Counteren_chunk_0 ::" 32 Word.word "
+
+
+
+record Satp64 =
+ Satp64_Satp64_chunk_0 ::" 64 Word.word "
+
+
+
+datatype PmpAddrMatchType = OFF | TOR | NA4 | NAPOT
+
+
+
+type_synonym pmp_addr_range =" ((xlenbits * xlenbits))option "
+
+datatype pmpAddrMatch = PMP_NoMatch | PMP_PartialMatch | PMP_Match
+
+
+
+datatype pmpMatch = PMP_Success | PMP_Continue | PMP_Fail
+
+
+
+datatype 'a Ext_FetchAddr_Check = Ext_FetchAddr_OK " (xlenbits)" | Ext_FetchAddr_Error " ('a)"
+
+
+
+datatype 'a Ext_ControlAddr_Check = Ext_ControlAddr_OK " (xlenbits)" | Ext_ControlAddr_Error " ('a)"
+
+
+
+datatype 'a Ext_DataAddr_Check = Ext_DataAddr_OK " (xlenbits)" | Ext_DataAddr_Error " ('a)"
+
+
+
+type_synonym ext_fetch_addr_error =" unit "
+
+type_synonym ext_control_addr_error =" unit "
+
+type_synonym ext_data_addr_error =" unit "
+
+type_synonym ext_exception =" unit "
+
+record sync_exception =
+
+ sync_exception_trap ::" ExceptionType "
+
+ sync_exception_excinfo ::" xlenbits option "
+
+ sync_exception_ext_exception ::" ext_exception option "
+
+
+
+datatype interrupt_set =
+ Ints_Pending " (xlenbits)" | Ints_Delegated " (xlenbits)" | Ints_Empty " (unit)"
+
+
+
+datatype ctl_result =
+ CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL_MRET " (unit)" | CTL_URET " (unit)"
+
+
+
+datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)"
+
+
+
+record htif_cmd =
+ htif_cmd_htif_cmd_chunk_0 ::" 64 Word.word "
+
+
+
+type_synonym pteAttribs =" 8 bits "
+
+datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update
+
+
+
+type_synonym vaddr32 =" 32 bits "
+
+type_synonym paddr32 =" 34 bits "
+
+type_synonym pte32 =" 32 bits "
+
+type_synonym asid32 =" 9 bits "
+
+record SV32_Vaddr =
+ SV32_Vaddr_SV32_Vaddr_chunk_0 ::" 32 Word.word "
+
+
+
+record SV48_Vaddr =
+ SV48_Vaddr_SV48_Vaddr_chunk_0 ::" 48 Word.word "
+
+
+
+record SV48_Paddr =
+ SV48_Paddr_SV48_Paddr_chunk_0 ::" 56 Word.word "
+
+
+
+record SV32_Paddr =
+ SV32_Paddr_SV32_Paddr_chunk_0 ::" 34 Word.word "
+
+
+
+record SV32_PTE =
+ SV32_PTE_SV32_PTE_chunk_0 ::" 32 Word.word "
+
+
+
+type_synonym paddr64 =" 56 bits "
+
+type_synonym pte64 =" 64 bits "
+
+type_synonym asid64 =" 16 bits "
+
+type_synonym vaddr39 =" 39 bits "
+
+record SV39_Vaddr =
+ SV39_Vaddr_SV39_Vaddr_chunk_0 ::" 39 Word.word "
+
+
+
+record SV39_Paddr =
+ SV39_Paddr_SV39_Paddr_chunk_0 ::" 56 Word.word "
+
+
+
+record SV39_PTE =
+ SV39_PTE_SV39_PTE_chunk_0 ::" 64 Word.word "
+
+
+
+type_synonym vaddr48 =" 48 bits "
+
+type_synonym pte48 =" 64 bits "
+
+datatype( 'paddr, 'pte) PTW_Result =
+ PTW_Success " (('paddr * 'pte * 'paddr * ii * bool))" | PTW_Failure " (PTW_Error)"
+
+
+
+datatype( 'paddr, 'failure) TR_Result = TR_Address " ('paddr)" | TR_Failure " ('failure)"
+
+
+
+record (overloaded) ( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry =
+
+ TLB_Entry_asid ::" 'asidlen bits "
+
+ TLB_Entry_global ::" bool "
+
+ TLB_Entry_vAddr ::" 'valen bits "
+
+ TLB_Entry_pAddr ::" 'palen bits "
+
+ TLB_Entry_vMatchMask ::" 'valen bits "
+
+ TLB_Entry_vAddrMask ::" 'valen bits "
+
+ TLB_Entry_pte ::" 'ptelen bits "
+
+ TLB_Entry_pteAddr ::" 'palen bits "
+
+ TLB_Entry_age ::" 64 bits "
+
+
+
+type_synonym TLB39_Entry =" (16, 39, 56, 64) TLB_Entry "
+
+type_synonym TLB48_Entry =" (16, 48, 56, 64) TLB_Entry "
+
+datatype FetchResult =
+ F_Ext_Error " (ext_fetch_addr_error)"
+ | F_Base " (word0)"
+ | F_RVC " (half)"
+ | F_Error " ((ExceptionType * xlenbits))"
+
+
+
+datatype register_value =
+ Regval_vector " ((ii * bool * register_value list))"
+ | Regval_list " ( register_value list)"
+ | Regval_option " ( register_value option)"
+ | Regval_Counteren " (Counteren)"
+ | Regval_Mcause " (Mcause)"
+ | Regval_Medeleg " (Medeleg)"
+ | Regval_Minterrupts " (Minterrupts)"
+ | Regval_Misa " (Misa)"
+ | Regval_Mstatus " (Mstatus)"
+ | Regval_Mtvec " (Mtvec)"
+ | Regval_Pmpcfg_ent " (Pmpcfg_ent)"
+ | Regval_Privilege " (Privilege)"
+ | Regval_Sedeleg " (Sedeleg)"
+ | Regval_Sinterrupts " (Sinterrupts)"
+ | Regval_TLB_Entry_16_39_56_64 " ( (16, 39, 56, 64)TLB_Entry)"
+ | Regval_TLB_Entry_16_48_56_64 " ( (16, 48, 56, 64)TLB_Entry)"
+ | Regval_bool " (bool)"
+ | Regval_vector_32_dec_bit " ( 32 Word.word)"
+ | Regval_vector_64_dec_bit " ( 64 Word.word)"
+
+
+
+record regstate =
+
+ satp ::" 64 Word.word "
+
+ tlb48 ::" ( (16, 48, 56, 64)TLB_Entry)option "
+
+ tlb39 ::" ( (16, 39, 56, 64)TLB_Entry)option "
+
+ htif_exit_code ::" 64 Word.word "
+
+ htif_done ::" bool "
+
+ htif_tohost ::" 64 Word.word "
+
+ mtimecmp ::" 64 Word.word "
+
+ utval ::" 64 Word.word "
+
+ ucause ::" Mcause "
+
+ uepc ::" 64 Word.word "
+
+ uscratch ::" 64 Word.word "
+
+ utvec ::" Mtvec "
+
+ pmpaddr15 ::" 64 Word.word "
+
+ pmpaddr14 ::" 64 Word.word "
+
+ pmpaddr13 ::" 64 Word.word "
+
+ pmpaddr12 ::" 64 Word.word "
+
+ pmpaddr11 ::" 64 Word.word "
+
+ pmpaddr10 ::" 64 Word.word "
+
+ pmpaddr9 ::" 64 Word.word "
+
+ pmpaddr8 ::" 64 Word.word "
+
+ pmpaddr7 ::" 64 Word.word "
+
+ pmpaddr6 ::" 64 Word.word "
+
+ pmpaddr5 ::" 64 Word.word "
+
+ pmpaddr4 ::" 64 Word.word "
+
+ pmpaddr3 ::" 64 Word.word "
+
+ pmpaddr2 ::" 64 Word.word "
+
+ pmpaddr1 ::" 64 Word.word "
+
+ pmpaddr0 ::" 64 Word.word "
+
+ pmp15cfg ::" Pmpcfg_ent "
+
+ pmp14cfg ::" Pmpcfg_ent "
+
+ pmp13cfg ::" Pmpcfg_ent "
+
+ pmp12cfg ::" Pmpcfg_ent "
+
+ pmp11cfg ::" Pmpcfg_ent "
+
+ pmp10cfg ::" Pmpcfg_ent "
+
+ pmp9cfg ::" Pmpcfg_ent "
+
+ pmp8cfg ::" Pmpcfg_ent "
+
+ pmp7cfg ::" Pmpcfg_ent "
+
+ pmp6cfg ::" Pmpcfg_ent "
+
+ pmp5cfg ::" Pmpcfg_ent "
+
+ pmp4cfg ::" Pmpcfg_ent "
+
+ pmp3cfg ::" Pmpcfg_ent "
+
+ pmp2cfg ::" Pmpcfg_ent "
+
+ pmp1cfg ::" Pmpcfg_ent "
+
+ pmp0cfg ::" Pmpcfg_ent "
+
+ tselect ::" 64 Word.word "
+
+ stval ::" 64 Word.word "
+
+ scause ::" Mcause "
+
+ sepc ::" 64 Word.word "
+
+ sscratch ::" 64 Word.word "
+
+ stvec ::" Mtvec "
+
+ sideleg ::" Sinterrupts "
+
+ sedeleg ::" Sedeleg "
+
+ mhartid ::" 64 Word.word "
+
+ marchid ::" 64 Word.word "
+
+ mimpid ::" 64 Word.word "
+
+ mvendorid ::" 32 Word.word "
+
+ minstret_written ::" bool "
+
+ minstret ::" 64 Word.word "
+
+ mtime ::" 64 Word.word "
+
+ mcycle ::" 64 Word.word "
+
+ scounteren ::" Counteren "
+
+ mcounteren ::" Counteren "
+
+ mscratch ::" 64 Word.word "
+
+ mtval ::" 64 Word.word "
+
+ mepc ::" 64 Word.word "
+
+ mcause ::" Mcause "
+
+ mtvec ::" Mtvec "
+
+ medeleg ::" Medeleg "
+
+ mideleg ::" Minterrupts "
+
+ mie ::" Minterrupts "
+
+ mip ::" Minterrupts "
+
+ mstatus ::" Mstatus "
+
+ misa ::" Misa "
+
+ cur_inst ::" 64 Word.word "
+
+ cur_privilege ::" Privilege "
+
+ x31 ::" 64 Word.word "
+
+ x30 ::" 64 Word.word "
+
+ x29 ::" 64 Word.word "
+
+ x28 ::" 64 Word.word "
+
+ x27 ::" 64 Word.word "
+
+ x26 ::" 64 Word.word "
+
+ x25 ::" 64 Word.word "
+
+ x24 ::" 64 Word.word "
+
+ x23 ::" 64 Word.word "
+
+ x22 ::" 64 Word.word "
+
+ x21 ::" 64 Word.word "
+
+ x20 ::" 64 Word.word "
+
+ x19 ::" 64 Word.word "
+
+ x18 ::" 64 Word.word "
+
+ x17 ::" 64 Word.word "
+
+ x16 ::" 64 Word.word "
+
+ x15 ::" 64 Word.word "
+
+ x14 ::" 64 Word.word "
+
+ x13 ::" 64 Word.word "
+
+ x12 ::" 64 Word.word "
+
+ x11 ::" 64 Word.word "
+
+ x10 ::" 64 Word.word "
+
+ x9 ::" 64 Word.word "
+
+ x8 ::" 64 Word.word "
+
+ x7 ::" 64 Word.word "
+
+ x6 ::" 64 Word.word "
+
+ x5 ::" 64 Word.word "
+
+ x4 ::" 64 Word.word "
+
+ x3 ::" 64 Word.word "
+
+ x2 ::" 64 Word.word "
+
+ x1 ::" 64 Word.word "
+
+ Xs ::" ( 64 Word.word) list "
+
+ instbits ::" 64 Word.word "
+
+ nextPC ::" 64 Word.word "
+
+ PC ::" 64 Word.word "
+
+
+
+
+
+\<comment> \<open>\<open>val Counteren_of_regval : register_value -> maybe Counteren\<close>\<close>
+
+fun Counteren_of_regval :: " register_value \<Rightarrow>(Counteren)option " where
+ " Counteren_of_regval (Regval_Counteren (v)) = ( Some v )"
+ for v :: " Counteren "
+|" Counteren_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Counteren : Counteren -> register_value\<close>\<close>
+
+definition regval_of_Counteren :: " Counteren \<Rightarrow> register_value " where
+ " regval_of_Counteren v = ( Regval_Counteren v )"
+ for v :: " Counteren "
+
+
+\<comment> \<open>\<open>val Mcause_of_regval : register_value -> maybe Mcause\<close>\<close>
+
+fun Mcause_of_regval :: " register_value \<Rightarrow>(Mcause)option " where
+ " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )"
+ for v :: " Mcause "
+|" Mcause_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mcause : Mcause -> register_value\<close>\<close>
+
+definition regval_of_Mcause :: " Mcause \<Rightarrow> register_value " where
+ " regval_of_Mcause v = ( Regval_Mcause v )"
+ for v :: " Mcause "
+
+
+\<comment> \<open>\<open>val Medeleg_of_regval : register_value -> maybe Medeleg\<close>\<close>
+
+fun Medeleg_of_regval :: " register_value \<Rightarrow>(Medeleg)option " where
+ " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )"
+ for v :: " Medeleg "
+|" Medeleg_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Medeleg : Medeleg -> register_value\<close>\<close>
+
+definition regval_of_Medeleg :: " Medeleg \<Rightarrow> register_value " where
+ " regval_of_Medeleg v = ( Regval_Medeleg v )"
+ for v :: " Medeleg "
+
+
+\<comment> \<open>\<open>val Minterrupts_of_regval : register_value -> maybe Minterrupts\<close>\<close>
+
+fun Minterrupts_of_regval :: " register_value \<Rightarrow>(Minterrupts)option " where
+ " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )"
+ for v :: " Minterrupts "
+|" Minterrupts_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Minterrupts : Minterrupts -> register_value\<close>\<close>
+
+definition regval_of_Minterrupts :: " Minterrupts \<Rightarrow> register_value " where
+ " regval_of_Minterrupts v = ( Regval_Minterrupts v )"
+ for v :: " Minterrupts "
+
+
+\<comment> \<open>\<open>val Misa_of_regval : register_value -> maybe Misa\<close>\<close>
+
+fun Misa_of_regval :: " register_value \<Rightarrow>(Misa)option " where
+ " Misa_of_regval (Regval_Misa (v)) = ( Some v )"
+ for v :: " Misa "
+|" Misa_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Misa : Misa -> register_value\<close>\<close>
+
+definition regval_of_Misa :: " Misa \<Rightarrow> register_value " where
+ " regval_of_Misa v = ( Regval_Misa v )"
+ for v :: " Misa "
+
+
+\<comment> \<open>\<open>val Mstatus_of_regval : register_value -> maybe Mstatus\<close>\<close>
+
+fun Mstatus_of_regval :: " register_value \<Rightarrow>(Mstatus)option " where
+ " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )"
+ for v :: " Mstatus "
+|" Mstatus_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mstatus : Mstatus -> register_value\<close>\<close>
+
+definition regval_of_Mstatus :: " Mstatus \<Rightarrow> register_value " where
+ " regval_of_Mstatus v = ( Regval_Mstatus v )"
+ for v :: " Mstatus "
+
+
+\<comment> \<open>\<open>val Mtvec_of_regval : register_value -> maybe Mtvec\<close>\<close>
+
+fun Mtvec_of_regval :: " register_value \<Rightarrow>(Mtvec)option " where
+ " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )"
+ for v :: " Mtvec "
+|" Mtvec_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Mtvec : Mtvec -> register_value\<close>\<close>
+
+definition regval_of_Mtvec :: " Mtvec \<Rightarrow> register_value " where
+ " regval_of_Mtvec v = ( Regval_Mtvec v )"
+ for v :: " Mtvec "
+
+
+\<comment> \<open>\<open>val Pmpcfg_ent_of_regval : register_value -> maybe Pmpcfg_ent\<close>\<close>
+
+fun Pmpcfg_ent_of_regval :: " register_value \<Rightarrow>(Pmpcfg_ent)option " where
+ " Pmpcfg_ent_of_regval (Regval_Pmpcfg_ent (v)) = ( Some v )"
+ for v :: " Pmpcfg_ent "
+|" Pmpcfg_ent_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Pmpcfg_ent : Pmpcfg_ent -> register_value\<close>\<close>
+
+definition regval_of_Pmpcfg_ent :: " Pmpcfg_ent \<Rightarrow> register_value " where
+ " regval_of_Pmpcfg_ent v = ( Regval_Pmpcfg_ent v )"
+ for v :: " Pmpcfg_ent "
+
+
+\<comment> \<open>\<open>val Privilege_of_regval : register_value -> maybe Privilege\<close>\<close>
+
+fun Privilege_of_regval :: " register_value \<Rightarrow>(Privilege)option " where
+ " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )"
+ for v :: " Privilege "
+|" Privilege_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Privilege : Privilege -> register_value\<close>\<close>
+
+definition regval_of_Privilege :: " Privilege \<Rightarrow> register_value " where
+ " regval_of_Privilege v = ( Regval_Privilege v )"
+ for v :: " Privilege "
+
+
+\<comment> \<open>\<open>val Sedeleg_of_regval : register_value -> maybe Sedeleg\<close>\<close>
+
+fun Sedeleg_of_regval :: " register_value \<Rightarrow>(Sedeleg)option " where
+ " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )"
+ for v :: " Sedeleg "
+|" Sedeleg_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Sedeleg : Sedeleg -> register_value\<close>\<close>
+
+definition regval_of_Sedeleg :: " Sedeleg \<Rightarrow> register_value " where
+ " regval_of_Sedeleg v = ( Regval_Sedeleg v )"
+ for v :: " Sedeleg "
+
+
+\<comment> \<open>\<open>val Sinterrupts_of_regval : register_value -> maybe Sinterrupts\<close>\<close>
+
+fun Sinterrupts_of_regval :: " register_value \<Rightarrow>(Sinterrupts)option " where
+ " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )"
+ for v :: " Sinterrupts "
+|" Sinterrupts_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_Sinterrupts : Sinterrupts -> register_value\<close>\<close>
+
+definition regval_of_Sinterrupts :: " Sinterrupts \<Rightarrow> register_value " where
+ " regval_of_Sinterrupts v = ( Regval_Sinterrupts v )"
+ for v :: " Sinterrupts "
+
+
+\<comment> \<open>\<open>val TLB_Entry_16_39_56_64_of_regval : register_value -> maybe (TLB_Entry ty16 ty39 ty56 ty64)\<close>\<close>
+
+fun TLB_Entry_16_39_56_64_of_regval :: " register_value \<Rightarrow>(((16),(39),(56),(64))TLB_Entry)option " where
+ " TLB_Entry_16_39_56_64_of_regval (Regval_TLB_Entry_16_39_56_64 (v)) = ( Some v )"
+ for v :: "((16),(39),(56),(64))TLB_Entry "
+|" TLB_Entry_16_39_56_64_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_TLB_Entry_16_39_56_64 : TLB_Entry ty16 ty39 ty56 ty64 -> register_value\<close>\<close>
+
+definition regval_of_TLB_Entry_16_39_56_64 :: "((16),(39),(56),(64))TLB_Entry \<Rightarrow> register_value " where
+ " regval_of_TLB_Entry_16_39_56_64 v = ( Regval_TLB_Entry_16_39_56_64 v )"
+ for v :: "((16),(39),(56),(64))TLB_Entry "
+
+
+\<comment> \<open>\<open>val TLB_Entry_16_48_56_64_of_regval : register_value -> maybe (TLB_Entry ty16 ty48 ty56 ty64)\<close>\<close>
+
+fun TLB_Entry_16_48_56_64_of_regval :: " register_value \<Rightarrow>(((16),(48),(56),(64))TLB_Entry)option " where
+ " TLB_Entry_16_48_56_64_of_regval (Regval_TLB_Entry_16_48_56_64 (v)) = ( Some v )"
+ for v :: "((16),(48),(56),(64))TLB_Entry "
+|" TLB_Entry_16_48_56_64_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_TLB_Entry_16_48_56_64 : TLB_Entry ty16 ty48 ty56 ty64 -> register_value\<close>\<close>
+
+definition regval_of_TLB_Entry_16_48_56_64 :: "((16),(48),(56),(64))TLB_Entry \<Rightarrow> register_value " where
+ " regval_of_TLB_Entry_16_48_56_64 v = ( Regval_TLB_Entry_16_48_56_64 v )"
+ for v :: "((16),(48),(56),(64))TLB_Entry "
+
+
+\<comment> \<open>\<open>val bool_of_regval : register_value -> maybe bool\<close>\<close>
+
+fun bool_of_regval :: " register_value \<Rightarrow>(bool)option " where
+ " bool_of_regval (Regval_bool (v)) = ( Some v )"
+ for v :: " bool "
+|" bool_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_bool : bool -> register_value\<close>\<close>
+
+definition regval_of_bool :: " bool \<Rightarrow> register_value " where
+ " regval_of_bool v = ( Regval_bool v )"
+ for v :: " bool "
+
+
+\<comment> \<open>\<open>val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)\<close>\<close>
+
+fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where
+ " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )"
+ for v :: "(32)Word.word "
+|" vector_32_dec_bit_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_vector_32_dec_bit : mword ty32 -> register_value\<close>\<close>
+
+definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register_value " where
+ " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )"
+ for v :: "(32)Word.word "
+
+
+\<comment> \<open>\<open>val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)\<close>\<close>
+
+fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where
+ " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )"
+ for v :: "(64)Word.word "
+|" vector_64_dec_bit_of_regval _ = ( None )"
+
+
+\<comment> \<open>\<open>val regval_of_vector_64_dec_bit : mword ty64 -> register_value\<close>\<close>
+
+definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where
+ " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )"
+ for v :: "(64)Word.word "
+
+
+
+
+\<comment> \<open>\<open>val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)\<close>\<close>
+definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where
+ " vector_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_vector (_, _, v) => just_list (List.map of_regval1 v)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value\<close>\<close>
+definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where
+ " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and size1 :: " int "
+ and is_inc :: " bool "
+ and xs :: " 'a list "
+
+
+\<comment> \<open>\<open>val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)\<close>\<close>
+definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where
+ " list_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_list v => just_list (List.map of_regval1 v)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value\<close>\<close>
+definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where
+ " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and xs :: " 'a list "
+
+
+\<comment> \<open>\<open>val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)\<close>\<close>
+definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where
+ " option_of_regval of_regval1 = ( \<lambda>x .
+ (case x of
+ Regval_option v => Some (Option.bind v of_regval1)
+ | _ => None
+ ) )"
+ for of_regval1 :: " register_value \<Rightarrow> 'a option "
+
+
+\<comment> \<open>\<open>val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value\<close>\<close>
+definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where
+ " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))"
+ for regval_of1 :: " 'a \<Rightarrow> register_value "
+ and v :: " 'a option "
+
+
+
+definition satp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " satp_ref = ( (|
+ name = (''satp''),
+ read_from = (\<lambda> s . (satp s)),
+ write_to = (\<lambda> v s . (( s (| satp := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition tlb48_ref :: "((regstate),(register_value),((((16),(48),(56),(64))TLB_Entry)option))register_ref " where
+ " tlb48_ref = ( (|
+ name = (''tlb48''),
+ read_from = (\<lambda> s . (tlb48 s)),
+ write_to = (\<lambda> v s . (( s (| tlb48 := v |)))),
+ of_regval = (\<lambda> v . option_of_regval (\<lambda> v . TLB_Entry_16_48_56_64_of_regval v) v),
+ regval_of = (\<lambda> v . regval_of_option (\<lambda> v . regval_of_TLB_Entry_16_48_56_64 v) v) |) )"
+
+
+definition tlb39_ref :: "((regstate),(register_value),((((16),(39),(56),(64))TLB_Entry)option))register_ref " where
+ " tlb39_ref = ( (|
+ name = (''tlb39''),
+ read_from = (\<lambda> s . (tlb39 s)),
+ write_to = (\<lambda> v s . (( s (| tlb39 := v |)))),
+ of_regval = (\<lambda> v . option_of_regval (\<lambda> v . TLB_Entry_16_39_56_64_of_regval v) v),
+ regval_of = (\<lambda> v . regval_of_option (\<lambda> v . regval_of_TLB_Entry_16_39_56_64 v) v) |) )"
+
+
+definition htif_exit_code_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " htif_exit_code_ref = ( (|
+ name = (''htif_exit_code''),
+ read_from = (\<lambda> s . (htif_exit_code s)),
+ write_to = (\<lambda> v s . (( s (| htif_exit_code := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition htif_done_ref :: "((regstate),(register_value),(bool))register_ref " where
+ " htif_done_ref = ( (|
+ name = (''htif_done''),
+ read_from = (\<lambda> s . (htif_done s)),
+ write_to = (\<lambda> v s . (( s (| htif_done := v |)))),
+ of_regval = (\<lambda> v . bool_of_regval v),
+ regval_of = (\<lambda> v . regval_of_bool v) |) )"
+
+
+definition htif_tohost_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " htif_tohost_ref = ( (|
+ name = (''htif_tohost''),
+ read_from = (\<lambda> s . (htif_tohost s)),
+ write_to = (\<lambda> v s . (( s (| htif_tohost := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtimecmp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mtimecmp_ref = ( (|
+ name = (''mtimecmp''),
+ read_from = (\<lambda> s . (mtimecmp s)),
+ write_to = (\<lambda> v s . (( s (| mtimecmp := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition utval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " utval_ref = ( (|
+ name = (''utval''),
+ read_from = (\<lambda> s . (utval s)),
+ write_to = (\<lambda> v s . (( s (| utval := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition ucause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " ucause_ref = ( (|
+ name = (''ucause''),
+ read_from = (\<lambda> s . (ucause s)),
+ write_to = (\<lambda> v s . (( s (| ucause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition uepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " uepc_ref = ( (|
+ name = (''uepc''),
+ read_from = (\<lambda> s . (uepc s)),
+ write_to = (\<lambda> v s . (( s (| uepc := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition uscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " uscratch_ref = ( (|
+ name = (''uscratch''),
+ read_from = (\<lambda> s . (uscratch s)),
+ write_to = (\<lambda> v s . (( s (| uscratch := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition utvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " utvec_ref = ( (|
+ name = (''utvec''),
+ read_from = (\<lambda> s . (utvec s)),
+ write_to = (\<lambda> v s . (( s (| utvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition pmpaddr15_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr15_ref = ( (|
+ name = (''pmpaddr15''),
+ read_from = (\<lambda> s . (pmpaddr15 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr15 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr14_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr14_ref = ( (|
+ name = (''pmpaddr14''),
+ read_from = (\<lambda> s . (pmpaddr14 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr14 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr13_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr13_ref = ( (|
+ name = (''pmpaddr13''),
+ read_from = (\<lambda> s . (pmpaddr13 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr13 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr12_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr12_ref = ( (|
+ name = (''pmpaddr12''),
+ read_from = (\<lambda> s . (pmpaddr12 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr12 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr11_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr11_ref = ( (|
+ name = (''pmpaddr11''),
+ read_from = (\<lambda> s . (pmpaddr11 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr11 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr10_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr10_ref = ( (|
+ name = (''pmpaddr10''),
+ read_from = (\<lambda> s . (pmpaddr10 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr10 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr9_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr9_ref = ( (|
+ name = (''pmpaddr9''),
+ read_from = (\<lambda> s . (pmpaddr9 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr9 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr8_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr8_ref = ( (|
+ name = (''pmpaddr8''),
+ read_from = (\<lambda> s . (pmpaddr8 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr8 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr7_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr7_ref = ( (|
+ name = (''pmpaddr7''),
+ read_from = (\<lambda> s . (pmpaddr7 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr7 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr6_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr6_ref = ( (|
+ name = (''pmpaddr6''),
+ read_from = (\<lambda> s . (pmpaddr6 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr6 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr5_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr5_ref = ( (|
+ name = (''pmpaddr5''),
+ read_from = (\<lambda> s . (pmpaddr5 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr5 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr4_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr4_ref = ( (|
+ name = (''pmpaddr4''),
+ read_from = (\<lambda> s . (pmpaddr4 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr4 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr3_ref = ( (|
+ name = (''pmpaddr3''),
+ read_from = (\<lambda> s . (pmpaddr3 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr3 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr2_ref = ( (|
+ name = (''pmpaddr2''),
+ read_from = (\<lambda> s . (pmpaddr2 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr2 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr1_ref = ( (|
+ name = (''pmpaddr1''),
+ read_from = (\<lambda> s . (pmpaddr1 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr1 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmpaddr0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " pmpaddr0_ref = ( (|
+ name = (''pmpaddr0''),
+ read_from = (\<lambda> s . (pmpaddr0 s)),
+ write_to = (\<lambda> v s . (( s (| pmpaddr0 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition pmp15cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp15cfg_ref = ( (|
+ name = (''pmp15cfg''),
+ read_from = (\<lambda> s . (pmp15cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp15cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp14cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp14cfg_ref = ( (|
+ name = (''pmp14cfg''),
+ read_from = (\<lambda> s . (pmp14cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp14cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp13cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp13cfg_ref = ( (|
+ name = (''pmp13cfg''),
+ read_from = (\<lambda> s . (pmp13cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp13cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp12cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp12cfg_ref = ( (|
+ name = (''pmp12cfg''),
+ read_from = (\<lambda> s . (pmp12cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp12cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp11cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp11cfg_ref = ( (|
+ name = (''pmp11cfg''),
+ read_from = (\<lambda> s . (pmp11cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp11cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp10cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp10cfg_ref = ( (|
+ name = (''pmp10cfg''),
+ read_from = (\<lambda> s . (pmp10cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp10cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp9cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp9cfg_ref = ( (|
+ name = (''pmp9cfg''),
+ read_from = (\<lambda> s . (pmp9cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp9cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp8cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp8cfg_ref = ( (|
+ name = (''pmp8cfg''),
+ read_from = (\<lambda> s . (pmp8cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp8cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp7cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp7cfg_ref = ( (|
+ name = (''pmp7cfg''),
+ read_from = (\<lambda> s . (pmp7cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp7cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp6cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp6cfg_ref = ( (|
+ name = (''pmp6cfg''),
+ read_from = (\<lambda> s . (pmp6cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp6cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp5cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp5cfg_ref = ( (|
+ name = (''pmp5cfg''),
+ read_from = (\<lambda> s . (pmp5cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp5cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp4cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp4cfg_ref = ( (|
+ name = (''pmp4cfg''),
+ read_from = (\<lambda> s . (pmp4cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp4cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp3cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp3cfg_ref = ( (|
+ name = (''pmp3cfg''),
+ read_from = (\<lambda> s . (pmp3cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp3cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp2cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp2cfg_ref = ( (|
+ name = (''pmp2cfg''),
+ read_from = (\<lambda> s . (pmp2cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp2cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp1cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp1cfg_ref = ( (|
+ name = (''pmp1cfg''),
+ read_from = (\<lambda> s . (pmp1cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp1cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition pmp0cfg_ref :: "((regstate),(register_value),(Pmpcfg_ent))register_ref " where
+ " pmp0cfg_ref = ( (|
+ name = (''pmp0cfg''),
+ read_from = (\<lambda> s . (pmp0cfg s)),
+ write_to = (\<lambda> v s . (( s (| pmp0cfg := v |)))),
+ of_regval = (\<lambda> v . Pmpcfg_ent_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Pmpcfg_ent v) |) )"
+
+
+definition tselect_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " tselect_ref = ( (|
+ name = (''tselect''),
+ read_from = (\<lambda> s . (tselect s)),
+ write_to = (\<lambda> v s . (( s (| tselect := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition stval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " stval_ref = ( (|
+ name = (''stval''),
+ read_from = (\<lambda> s . (stval s)),
+ write_to = (\<lambda> v s . (( s (| stval := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition scause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " scause_ref = ( (|
+ name = (''scause''),
+ read_from = (\<lambda> s . (scause s)),
+ write_to = (\<lambda> v s . (( s (| scause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition sepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " sepc_ref = ( (|
+ name = (''sepc''),
+ read_from = (\<lambda> s . (sepc s)),
+ write_to = (\<lambda> v s . (( s (| sepc := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition sscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " sscratch_ref = ( (|
+ name = (''sscratch''),
+ read_from = (\<lambda> s . (sscratch s)),
+ write_to = (\<lambda> v s . (( s (| sscratch := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition stvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " stvec_ref = ( (|
+ name = (''stvec''),
+ read_from = (\<lambda> s . (stvec s)),
+ write_to = (\<lambda> v s . (( s (| stvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition sideleg_ref :: "((regstate),(register_value),(Sinterrupts))register_ref " where
+ " sideleg_ref = ( (|
+ name = (''sideleg''),
+ read_from = (\<lambda> s . (sideleg s)),
+ write_to = (\<lambda> v s . (( s (| sideleg := v |)))),
+ of_regval = (\<lambda> v . Sinterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Sinterrupts v) |) )"
+
+
+definition sedeleg_ref :: "((regstate),(register_value),(Sedeleg))register_ref " where
+ " sedeleg_ref = ( (|
+ name = (''sedeleg''),
+ read_from = (\<lambda> s . (sedeleg s)),
+ write_to = (\<lambda> v s . (( s (| sedeleg := v |)))),
+ of_regval = (\<lambda> v . Sedeleg_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Sedeleg v) |) )"
+
+
+definition mhartid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mhartid_ref = ( (|
+ name = (''mhartid''),
+ read_from = (\<lambda> s . (mhartid s)),
+ write_to = (\<lambda> v s . (( s (| mhartid := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition marchid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " marchid_ref = ( (|
+ name = (''marchid''),
+ read_from = (\<lambda> s . (marchid s)),
+ write_to = (\<lambda> v s . (( s (| marchid := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mimpid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mimpid_ref = ( (|
+ name = (''mimpid''),
+ read_from = (\<lambda> s . (mimpid s)),
+ write_to = (\<lambda> v s . (( s (| mimpid := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mvendorid_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where
+ " mvendorid_ref = ( (|
+ name = (''mvendorid''),
+ read_from = (\<lambda> s . (mvendorid s)),
+ write_to = (\<lambda> v s . (( s (| mvendorid := v |)))),
+ of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )"
+
+
+definition minstret_written_ref :: "((regstate),(register_value),(bool))register_ref " where
+ " minstret_written_ref = ( (|
+ name = (''minstret_written''),
+ read_from = (\<lambda> s . (minstret_written s)),
+ write_to = (\<lambda> v s . (( s (| minstret_written := v |)))),
+ of_regval = (\<lambda> v . bool_of_regval v),
+ regval_of = (\<lambda> v . regval_of_bool v) |) )"
+
+
+definition minstret_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " minstret_ref = ( (|
+ name = (''minstret''),
+ read_from = (\<lambda> s . (minstret s)),
+ write_to = (\<lambda> v s . (( s (| minstret := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtime_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mtime_ref = ( (|
+ name = (''mtime''),
+ read_from = (\<lambda> s . (mtime s)),
+ write_to = (\<lambda> v s . (( s (| mtime := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mcycle_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mcycle_ref = ( (|
+ name = (''mcycle''),
+ read_from = (\<lambda> s . (mcycle s)),
+ write_to = (\<lambda> v s . (( s (| mcycle := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition scounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where
+ " scounteren_ref = ( (|
+ name = (''scounteren''),
+ read_from = (\<lambda> s . (scounteren s)),
+ write_to = (\<lambda> v s . (( s (| scounteren := v |)))),
+ of_regval = (\<lambda> v . Counteren_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Counteren v) |) )"
+
+
+definition mcounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where
+ " mcounteren_ref = ( (|
+ name = (''mcounteren''),
+ read_from = (\<lambda> s . (mcounteren s)),
+ write_to = (\<lambda> v s . (( s (| mcounteren := v |)))),
+ of_regval = (\<lambda> v . Counteren_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Counteren v) |) )"
+
+
+definition mscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mscratch_ref = ( (|
+ name = (''mscratch''),
+ read_from = (\<lambda> s . (mscratch s)),
+ write_to = (\<lambda> v s . (( s (| mscratch := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mtval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mtval_ref = ( (|
+ name = (''mtval''),
+ read_from = (\<lambda> s . (mtval s)),
+ write_to = (\<lambda> v s . (( s (| mtval := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " mepc_ref = ( (|
+ name = (''mepc''),
+ read_from = (\<lambda> s . (mepc s)),
+ write_to = (\<lambda> v s . (( s (| mepc := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition mcause_ref :: "((regstate),(register_value),(Mcause))register_ref " where
+ " mcause_ref = ( (|
+ name = (''mcause''),
+ read_from = (\<lambda> s . (mcause s)),
+ write_to = (\<lambda> v s . (( s (| mcause := v |)))),
+ of_regval = (\<lambda> v . Mcause_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mcause v) |) )"
+
+
+definition mtvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where
+ " mtvec_ref = ( (|
+ name = (''mtvec''),
+ read_from = (\<lambda> s . (mtvec s)),
+ write_to = (\<lambda> v s . (( s (| mtvec := v |)))),
+ of_regval = (\<lambda> v . Mtvec_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mtvec v) |) )"
+
+
+definition medeleg_ref :: "((regstate),(register_value),(Medeleg))register_ref " where
+ " medeleg_ref = ( (|
+ name = (''medeleg''),
+ read_from = (\<lambda> s . (medeleg s)),
+ write_to = (\<lambda> v s . (( s (| medeleg := v |)))),
+ of_regval = (\<lambda> v . Medeleg_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Medeleg v) |) )"
+
+
+definition mideleg_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mideleg_ref = ( (|
+ name = (''mideleg''),
+ read_from = (\<lambda> s . (mideleg s)),
+ write_to = (\<lambda> v s . (( s (| mideleg := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mie_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mie_ref = ( (|
+ name = (''mie''),
+ read_from = (\<lambda> s . (mie s)),
+ write_to = (\<lambda> v s . (( s (| mie := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mip_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where
+ " mip_ref = ( (|
+ name = (''mip''),
+ read_from = (\<lambda> s . (mip s)),
+ write_to = (\<lambda> v s . (( s (| mip := v |)))),
+ of_regval = (\<lambda> v . Minterrupts_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )"
+
+
+definition mstatus_ref :: "((regstate),(register_value),(Mstatus))register_ref " where
+ " mstatus_ref = ( (|
+ name = (''mstatus''),
+ read_from = (\<lambda> s . (mstatus s)),
+ write_to = (\<lambda> v s . (( s (| mstatus := v |)))),
+ of_regval = (\<lambda> v . Mstatus_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Mstatus v) |) )"
+
+
+definition misa_ref :: "((regstate),(register_value),(Misa))register_ref " where
+ " misa_ref = ( (|
+ name = (''misa''),
+ read_from = (\<lambda> s . (misa s)),
+ write_to = (\<lambda> v s . (( s (| misa := v |)))),
+ of_regval = (\<lambda> v . Misa_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Misa v) |) )"
+
+
+definition cur_inst_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " cur_inst_ref = ( (|
+ name = (''cur_inst''),
+ read_from = (\<lambda> s . (cur_inst s)),
+ write_to = (\<lambda> v s . (( s (| cur_inst := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition cur_privilege_ref :: "((regstate),(register_value),(Privilege))register_ref " where
+ " cur_privilege_ref = ( (|
+ name = (''cur_privilege''),
+ read_from = (\<lambda> s . (cur_privilege s)),
+ write_to = (\<lambda> v s . (( s (| cur_privilege := v |)))),
+ of_regval = (\<lambda> v . Privilege_of_regval v),
+ regval_of = (\<lambda> v . regval_of_Privilege v) |) )"
+
+
+definition x31_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x31_ref = ( (|
+ name = (''x31''),
+ read_from = (\<lambda> s . (x31 s)),
+ write_to = (\<lambda> v s . (( s (| x31 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x30_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x30_ref = ( (|
+ name = (''x30''),
+ read_from = (\<lambda> s . (x30 s)),
+ write_to = (\<lambda> v s . (( s (| x30 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x29_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x29_ref = ( (|
+ name = (''x29''),
+ read_from = (\<lambda> s . (x29 s)),
+ write_to = (\<lambda> v s . (( s (| x29 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x28_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x28_ref = ( (|
+ name = (''x28''),
+ read_from = (\<lambda> s . (x28 s)),
+ write_to = (\<lambda> v s . (( s (| x28 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x27_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x27_ref = ( (|
+ name = (''x27''),
+ read_from = (\<lambda> s . (x27 s)),
+ write_to = (\<lambda> v s . (( s (| x27 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x26_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x26_ref = ( (|
+ name = (''x26''),
+ read_from = (\<lambda> s . (x26 s)),
+ write_to = (\<lambda> v s . (( s (| x26 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x25_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x25_ref = ( (|
+ name = (''x25''),
+ read_from = (\<lambda> s . (x25 s)),
+ write_to = (\<lambda> v s . (( s (| x25 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x24_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x24_ref = ( (|
+ name = (''x24''),
+ read_from = (\<lambda> s . (x24 s)),
+ write_to = (\<lambda> v s . (( s (| x24 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x23_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x23_ref = ( (|
+ name = (''x23''),
+ read_from = (\<lambda> s . (x23 s)),
+ write_to = (\<lambda> v s . (( s (| x23 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x22_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x22_ref = ( (|
+ name = (''x22''),
+ read_from = (\<lambda> s . (x22 s)),
+ write_to = (\<lambda> v s . (( s (| x22 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x21_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x21_ref = ( (|
+ name = (''x21''),
+ read_from = (\<lambda> s . (x21 s)),
+ write_to = (\<lambda> v s . (( s (| x21 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x20_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x20_ref = ( (|
+ name = (''x20''),
+ read_from = (\<lambda> s . (x20 s)),
+ write_to = (\<lambda> v s . (( s (| x20 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x19_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x19_ref = ( (|
+ name = (''x19''),
+ read_from = (\<lambda> s . (x19 s)),
+ write_to = (\<lambda> v s . (( s (| x19 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x18_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x18_ref = ( (|
+ name = (''x18''),
+ read_from = (\<lambda> s . (x18 s)),
+ write_to = (\<lambda> v s . (( s (| x18 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x17_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x17_ref = ( (|
+ name = (''x17''),
+ read_from = (\<lambda> s . (x17 s)),
+ write_to = (\<lambda> v s . (( s (| x17 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x16_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x16_ref = ( (|
+ name = (''x16''),
+ read_from = (\<lambda> s . (x16 s)),
+ write_to = (\<lambda> v s . (( s (| x16 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x15_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x15_ref = ( (|
+ name = (''x15''),
+ read_from = (\<lambda> s . (x15 s)),
+ write_to = (\<lambda> v s . (( s (| x15 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x14_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x14_ref = ( (|
+ name = (''x14''),
+ read_from = (\<lambda> s . (x14 s)),
+ write_to = (\<lambda> v s . (( s (| x14 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x13_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x13_ref = ( (|
+ name = (''x13''),
+ read_from = (\<lambda> s . (x13 s)),
+ write_to = (\<lambda> v s . (( s (| x13 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x12_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x12_ref = ( (|
+ name = (''x12''),
+ read_from = (\<lambda> s . (x12 s)),
+ write_to = (\<lambda> v s . (( s (| x12 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x11_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x11_ref = ( (|
+ name = (''x11''),
+ read_from = (\<lambda> s . (x11 s)),
+ write_to = (\<lambda> v s . (( s (| x11 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x10_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x10_ref = ( (|
+ name = (''x10''),
+ read_from = (\<lambda> s . (x10 s)),
+ write_to = (\<lambda> v s . (( s (| x10 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x9_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x9_ref = ( (|
+ name = (''x9''),
+ read_from = (\<lambda> s . (x9 s)),
+ write_to = (\<lambda> v s . (( s (| x9 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x8_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x8_ref = ( (|
+ name = (''x8''),
+ read_from = (\<lambda> s . (x8 s)),
+ write_to = (\<lambda> v s . (( s (| x8 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x7_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x7_ref = ( (|
+ name = (''x7''),
+ read_from = (\<lambda> s . (x7 s)),
+ write_to = (\<lambda> v s . (( s (| x7 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x6_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x6_ref = ( (|
+ name = (''x6''),
+ read_from = (\<lambda> s . (x6 s)),
+ write_to = (\<lambda> v s . (( s (| x6 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x5_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x5_ref = ( (|
+ name = (''x5''),
+ read_from = (\<lambda> s . (x5 s)),
+ write_to = (\<lambda> v s . (( s (| x5 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x4_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x4_ref = ( (|
+ name = (''x4''),
+ read_from = (\<lambda> s . (x4 s)),
+ write_to = (\<lambda> v s . (( s (| x4 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x3_ref = ( (|
+ name = (''x3''),
+ read_from = (\<lambda> s . (x3 s)),
+ write_to = (\<lambda> v s . (( s (| x3 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x2_ref = ( (|
+ name = (''x2''),
+ read_from = (\<lambda> s . (x2 s)),
+ write_to = (\<lambda> v s . (( s (| x2 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition x1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " x1_ref = ( (|
+ name = (''x1''),
+ read_from = (\<lambda> s . (x1 s)),
+ write_to = (\<lambda> v s . (( s (| x1 := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where
+ " Xs_ref = ( (|
+ name = (''Xs''),
+ read_from = (\<lambda> s . (Xs s)),
+ write_to = (\<lambda> v s . (( s (| Xs := v |)))),
+ of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v),
+ regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )"
+
+
+definition instbits_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " instbits_ref = ( (|
+ name = (''instbits''),
+ read_from = (\<lambda> s . (instbits s)),
+ write_to = (\<lambda> v s . (( s (| instbits := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " nextPC_ref = ( (|
+ name = (''nextPC''),
+ read_from = (\<lambda> s . (nextPC s)),
+ write_to = (\<lambda> v s . (( s (| nextPC := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where
+ " PC_ref = ( (|
+ name = (''PC''),
+ read_from = (\<lambda> s . (PC s)),
+ write_to = (\<lambda> v s . (( s (| PC := v |)))),
+ of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v),
+ regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )"
+
+
+\<comment> \<open>\<open>val get_regval : string -> regstate -> maybe register_value\<close>\<close>
+definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where
+ " get_regval reg_name s = (
+ if reg_name = (''satp'') then Some ((regval_of satp_ref) ((read_from satp_ref) s)) else
+ if reg_name = (''tlb48'') then Some ((regval_of tlb48_ref) ((read_from tlb48_ref) s)) else
+ if reg_name = (''tlb39'') then Some ((regval_of tlb39_ref) ((read_from tlb39_ref) s)) else
+ if reg_name = (''htif_exit_code'') then Some ((regval_of htif_exit_code_ref) ((read_from htif_exit_code_ref) s)) else
+ if reg_name = (''htif_done'') then Some ((regval_of htif_done_ref) ((read_from htif_done_ref) s)) else
+ if reg_name = (''htif_tohost'') then Some ((regval_of htif_tohost_ref) ((read_from htif_tohost_ref) s)) else
+ if reg_name = (''mtimecmp'') then Some ((regval_of mtimecmp_ref) ((read_from mtimecmp_ref) s)) else
+ if reg_name = (''utval'') then Some ((regval_of utval_ref) ((read_from utval_ref) s)) else
+ if reg_name = (''ucause'') then Some ((regval_of ucause_ref) ((read_from ucause_ref) s)) else
+ if reg_name = (''uepc'') then Some ((regval_of uepc_ref) ((read_from uepc_ref) s)) else
+ if reg_name = (''uscratch'') then Some ((regval_of uscratch_ref) ((read_from uscratch_ref) s)) else
+ if reg_name = (''utvec'') then Some ((regval_of utvec_ref) ((read_from utvec_ref) s)) else
+ if reg_name = (''pmpaddr15'') then Some ((regval_of pmpaddr15_ref) ((read_from pmpaddr15_ref) s)) else
+ if reg_name = (''pmpaddr14'') then Some ((regval_of pmpaddr14_ref) ((read_from pmpaddr14_ref) s)) else
+ if reg_name = (''pmpaddr13'') then Some ((regval_of pmpaddr13_ref) ((read_from pmpaddr13_ref) s)) else
+ if reg_name = (''pmpaddr12'') then Some ((regval_of pmpaddr12_ref) ((read_from pmpaddr12_ref) s)) else
+ if reg_name = (''pmpaddr11'') then Some ((regval_of pmpaddr11_ref) ((read_from pmpaddr11_ref) s)) else
+ if reg_name = (''pmpaddr10'') then Some ((regval_of pmpaddr10_ref) ((read_from pmpaddr10_ref) s)) else
+ if reg_name = (''pmpaddr9'') then Some ((regval_of pmpaddr9_ref) ((read_from pmpaddr9_ref) s)) else
+ if reg_name = (''pmpaddr8'') then Some ((regval_of pmpaddr8_ref) ((read_from pmpaddr8_ref) s)) else
+ if reg_name = (''pmpaddr7'') then Some ((regval_of pmpaddr7_ref) ((read_from pmpaddr7_ref) s)) else
+ if reg_name = (''pmpaddr6'') then Some ((regval_of pmpaddr6_ref) ((read_from pmpaddr6_ref) s)) else
+ if reg_name = (''pmpaddr5'') then Some ((regval_of pmpaddr5_ref) ((read_from pmpaddr5_ref) s)) else
+ if reg_name = (''pmpaddr4'') then Some ((regval_of pmpaddr4_ref) ((read_from pmpaddr4_ref) s)) else
+ if reg_name = (''pmpaddr3'') then Some ((regval_of pmpaddr3_ref) ((read_from pmpaddr3_ref) s)) else
+ if reg_name = (''pmpaddr2'') then Some ((regval_of pmpaddr2_ref) ((read_from pmpaddr2_ref) s)) else
+ if reg_name = (''pmpaddr1'') then Some ((regval_of pmpaddr1_ref) ((read_from pmpaddr1_ref) s)) else
+ if reg_name = (''pmpaddr0'') then Some ((regval_of pmpaddr0_ref) ((read_from pmpaddr0_ref) s)) else
+ if reg_name = (''pmp15cfg'') then Some ((regval_of pmp15cfg_ref) ((read_from pmp15cfg_ref) s)) else
+ if reg_name = (''pmp14cfg'') then Some ((regval_of pmp14cfg_ref) ((read_from pmp14cfg_ref) s)) else
+ if reg_name = (''pmp13cfg'') then Some ((regval_of pmp13cfg_ref) ((read_from pmp13cfg_ref) s)) else
+ if reg_name = (''pmp12cfg'') then Some ((regval_of pmp12cfg_ref) ((read_from pmp12cfg_ref) s)) else
+ if reg_name = (''pmp11cfg'') then Some ((regval_of pmp11cfg_ref) ((read_from pmp11cfg_ref) s)) else
+ if reg_name = (''pmp10cfg'') then Some ((regval_of pmp10cfg_ref) ((read_from pmp10cfg_ref) s)) else
+ if reg_name = (''pmp9cfg'') then Some ((regval_of pmp9cfg_ref) ((read_from pmp9cfg_ref) s)) else
+ if reg_name = (''pmp8cfg'') then Some ((regval_of pmp8cfg_ref) ((read_from pmp8cfg_ref) s)) else
+ if reg_name = (''pmp7cfg'') then Some ((regval_of pmp7cfg_ref) ((read_from pmp7cfg_ref) s)) else
+ if reg_name = (''pmp6cfg'') then Some ((regval_of pmp6cfg_ref) ((read_from pmp6cfg_ref) s)) else
+ if reg_name = (''pmp5cfg'') then Some ((regval_of pmp5cfg_ref) ((read_from pmp5cfg_ref) s)) else
+ if reg_name = (''pmp4cfg'') then Some ((regval_of pmp4cfg_ref) ((read_from pmp4cfg_ref) s)) else
+ if reg_name = (''pmp3cfg'') then Some ((regval_of pmp3cfg_ref) ((read_from pmp3cfg_ref) s)) else
+ if reg_name = (''pmp2cfg'') then Some ((regval_of pmp2cfg_ref) ((read_from pmp2cfg_ref) s)) else
+ if reg_name = (''pmp1cfg'') then Some ((regval_of pmp1cfg_ref) ((read_from pmp1cfg_ref) s)) else
+ if reg_name = (''pmp0cfg'') then Some ((regval_of pmp0cfg_ref) ((read_from pmp0cfg_ref) s)) else
+ if reg_name = (''tselect'') then Some ((regval_of tselect_ref) ((read_from tselect_ref) s)) else
+ if reg_name = (''stval'') then Some ((regval_of stval_ref) ((read_from stval_ref) s)) else
+ if reg_name = (''scause'') then Some ((regval_of scause_ref) ((read_from scause_ref) s)) else
+ if reg_name = (''sepc'') then Some ((regval_of sepc_ref) ((read_from sepc_ref) s)) else
+ if reg_name = (''sscratch'') then Some ((regval_of sscratch_ref) ((read_from sscratch_ref) s)) else
+ if reg_name = (''stvec'') then Some ((regval_of stvec_ref) ((read_from stvec_ref) s)) else
+ if reg_name = (''sideleg'') then Some ((regval_of sideleg_ref) ((read_from sideleg_ref) s)) else
+ if reg_name = (''sedeleg'') then Some ((regval_of sedeleg_ref) ((read_from sedeleg_ref) s)) else
+ if reg_name = (''mhartid'') then Some ((regval_of mhartid_ref) ((read_from mhartid_ref) s)) else
+ if reg_name = (''marchid'') then Some ((regval_of marchid_ref) ((read_from marchid_ref) s)) else
+ if reg_name = (''mimpid'') then Some ((regval_of mimpid_ref) ((read_from mimpid_ref) s)) else
+ if reg_name = (''mvendorid'') then Some ((regval_of mvendorid_ref) ((read_from mvendorid_ref) s)) else
+ if reg_name = (''minstret_written'') then Some ((regval_of minstret_written_ref) ((read_from minstret_written_ref) s)) else
+ if reg_name = (''minstret'') then Some ((regval_of minstret_ref) ((read_from minstret_ref) s)) else
+ if reg_name = (''mtime'') then Some ((regval_of mtime_ref) ((read_from mtime_ref) s)) else
+ if reg_name = (''mcycle'') then Some ((regval_of mcycle_ref) ((read_from mcycle_ref) s)) else
+ if reg_name = (''scounteren'') then Some ((regval_of scounteren_ref) ((read_from scounteren_ref) s)) else
+ if reg_name = (''mcounteren'') then Some ((regval_of mcounteren_ref) ((read_from mcounteren_ref) s)) else
+ if reg_name = (''mscratch'') then Some ((regval_of mscratch_ref) ((read_from mscratch_ref) s)) else
+ if reg_name = (''mtval'') then Some ((regval_of mtval_ref) ((read_from mtval_ref) s)) else
+ if reg_name = (''mepc'') then Some ((regval_of mepc_ref) ((read_from mepc_ref) s)) else
+ if reg_name = (''mcause'') then Some ((regval_of mcause_ref) ((read_from mcause_ref) s)) else
+ if reg_name = (''mtvec'') then Some ((regval_of mtvec_ref) ((read_from mtvec_ref) s)) else
+ if reg_name = (''medeleg'') then Some ((regval_of medeleg_ref) ((read_from medeleg_ref) s)) else
+ if reg_name = (''mideleg'') then Some ((regval_of mideleg_ref) ((read_from mideleg_ref) s)) else
+ if reg_name = (''mie'') then Some ((regval_of mie_ref) ((read_from mie_ref) s)) else
+ if reg_name = (''mip'') then Some ((regval_of mip_ref) ((read_from mip_ref) s)) else
+ if reg_name = (''mstatus'') then Some ((regval_of mstatus_ref) ((read_from mstatus_ref) s)) else
+ if reg_name = (''misa'') then Some ((regval_of misa_ref) ((read_from misa_ref) s)) else
+ if reg_name = (''cur_inst'') then Some ((regval_of cur_inst_ref) ((read_from cur_inst_ref) s)) else
+ if reg_name = (''cur_privilege'') then Some ((regval_of cur_privilege_ref) ((read_from cur_privilege_ref) s)) else
+ if reg_name = (''x31'') then Some ((regval_of x31_ref) ((read_from x31_ref) s)) else
+ if reg_name = (''x30'') then Some ((regval_of x30_ref) ((read_from x30_ref) s)) else
+ if reg_name = (''x29'') then Some ((regval_of x29_ref) ((read_from x29_ref) s)) else
+ if reg_name = (''x28'') then Some ((regval_of x28_ref) ((read_from x28_ref) s)) else
+ if reg_name = (''x27'') then Some ((regval_of x27_ref) ((read_from x27_ref) s)) else
+ if reg_name = (''x26'') then Some ((regval_of x26_ref) ((read_from x26_ref) s)) else
+ if reg_name = (''x25'') then Some ((regval_of x25_ref) ((read_from x25_ref) s)) else
+ if reg_name = (''x24'') then Some ((regval_of x24_ref) ((read_from x24_ref) s)) else
+ if reg_name = (''x23'') then Some ((regval_of x23_ref) ((read_from x23_ref) s)) else
+ if reg_name = (''x22'') then Some ((regval_of x22_ref) ((read_from x22_ref) s)) else
+ if reg_name = (''x21'') then Some ((regval_of x21_ref) ((read_from x21_ref) s)) else
+ if reg_name = (''x20'') then Some ((regval_of x20_ref) ((read_from x20_ref) s)) else
+ if reg_name = (''x19'') then Some ((regval_of x19_ref) ((read_from x19_ref) s)) else
+ if reg_name = (''x18'') then Some ((regval_of x18_ref) ((read_from x18_ref) s)) else
+ if reg_name = (''x17'') then Some ((regval_of x17_ref) ((read_from x17_ref) s)) else
+ if reg_name = (''x16'') then Some ((regval_of x16_ref) ((read_from x16_ref) s)) else
+ if reg_name = (''x15'') then Some ((regval_of x15_ref) ((read_from x15_ref) s)) else
+ if reg_name = (''x14'') then Some ((regval_of x14_ref) ((read_from x14_ref) s)) else
+ if reg_name = (''x13'') then Some ((regval_of x13_ref) ((read_from x13_ref) s)) else
+ if reg_name = (''x12'') then Some ((regval_of x12_ref) ((read_from x12_ref) s)) else
+ if reg_name = (''x11'') then Some ((regval_of x11_ref) ((read_from x11_ref) s)) else
+ if reg_name = (''x10'') then Some ((regval_of x10_ref) ((read_from x10_ref) s)) else
+ if reg_name = (''x9'') then Some ((regval_of x9_ref) ((read_from x9_ref) s)) else
+ if reg_name = (''x8'') then Some ((regval_of x8_ref) ((read_from x8_ref) s)) else
+ if reg_name = (''x7'') then Some ((regval_of x7_ref) ((read_from x7_ref) s)) else
+ if reg_name = (''x6'') then Some ((regval_of x6_ref) ((read_from x6_ref) s)) else
+ if reg_name = (''x5'') then Some ((regval_of x5_ref) ((read_from x5_ref) s)) else
+ if reg_name = (''x4'') then Some ((regval_of x4_ref) ((read_from x4_ref) s)) else
+ if reg_name = (''x3'') then Some ((regval_of x3_ref) ((read_from x3_ref) s)) else
+ if reg_name = (''x2'') then Some ((regval_of x2_ref) ((read_from x2_ref) s)) else
+ if reg_name = (''x1'') then Some ((regval_of x1_ref) ((read_from x1_ref) s)) else
+ if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else
+ if reg_name = (''instbits'') then Some ((regval_of instbits_ref) ((read_from instbits_ref) s)) else
+ if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else
+ if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else
+ None )"
+ for reg_name :: " string "
+ and s :: " regstate "
+
+
+\<comment> \<open>\<open>val set_regval : string -> register_value -> regstate -> maybe regstate\<close>\<close>
+definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where
+ " set_regval reg_name v s = (
+ if reg_name = (''satp'') then map_option (\<lambda> v . (write_to satp_ref) v s) ((of_regval satp_ref) v) else
+ if reg_name = (''tlb48'') then map_option (\<lambda> v . (write_to tlb48_ref) v s) ((of_regval tlb48_ref) v) else
+ if reg_name = (''tlb39'') then map_option (\<lambda> v . (write_to tlb39_ref) v s) ((of_regval tlb39_ref) v) else
+ if reg_name = (''htif_exit_code'') then map_option (\<lambda> v . (write_to htif_exit_code_ref) v s) ((of_regval htif_exit_code_ref) v) else
+ if reg_name = (''htif_done'') then map_option (\<lambda> v . (write_to htif_done_ref) v s) ((of_regval htif_done_ref) v) else
+ if reg_name = (''htif_tohost'') then map_option (\<lambda> v . (write_to htif_tohost_ref) v s) ((of_regval htif_tohost_ref) v) else
+ if reg_name = (''mtimecmp'') then map_option (\<lambda> v . (write_to mtimecmp_ref) v s) ((of_regval mtimecmp_ref) v) else
+ if reg_name = (''utval'') then map_option (\<lambda> v . (write_to utval_ref) v s) ((of_regval utval_ref) v) else
+ if reg_name = (''ucause'') then map_option (\<lambda> v . (write_to ucause_ref) v s) ((of_regval ucause_ref) v) else
+ if reg_name = (''uepc'') then map_option (\<lambda> v . (write_to uepc_ref) v s) ((of_regval uepc_ref) v) else
+ if reg_name = (''uscratch'') then map_option (\<lambda> v . (write_to uscratch_ref) v s) ((of_regval uscratch_ref) v) else
+ if reg_name = (''utvec'') then map_option (\<lambda> v . (write_to utvec_ref) v s) ((of_regval utvec_ref) v) else
+ if reg_name = (''pmpaddr15'') then map_option (\<lambda> v . (write_to pmpaddr15_ref) v s) ((of_regval pmpaddr15_ref) v) else
+ if reg_name = (''pmpaddr14'') then map_option (\<lambda> v . (write_to pmpaddr14_ref) v s) ((of_regval pmpaddr14_ref) v) else
+ if reg_name = (''pmpaddr13'') then map_option (\<lambda> v . (write_to pmpaddr13_ref) v s) ((of_regval pmpaddr13_ref) v) else
+ if reg_name = (''pmpaddr12'') then map_option (\<lambda> v . (write_to pmpaddr12_ref) v s) ((of_regval pmpaddr12_ref) v) else
+ if reg_name = (''pmpaddr11'') then map_option (\<lambda> v . (write_to pmpaddr11_ref) v s) ((of_regval pmpaddr11_ref) v) else
+ if reg_name = (''pmpaddr10'') then map_option (\<lambda> v . (write_to pmpaddr10_ref) v s) ((of_regval pmpaddr10_ref) v) else
+ if reg_name = (''pmpaddr9'') then map_option (\<lambda> v . (write_to pmpaddr9_ref) v s) ((of_regval pmpaddr9_ref) v) else
+ if reg_name = (''pmpaddr8'') then map_option (\<lambda> v . (write_to pmpaddr8_ref) v s) ((of_regval pmpaddr8_ref) v) else
+ if reg_name = (''pmpaddr7'') then map_option (\<lambda> v . (write_to pmpaddr7_ref) v s) ((of_regval pmpaddr7_ref) v) else
+ if reg_name = (''pmpaddr6'') then map_option (\<lambda> v . (write_to pmpaddr6_ref) v s) ((of_regval pmpaddr6_ref) v) else
+ if reg_name = (''pmpaddr5'') then map_option (\<lambda> v . (write_to pmpaddr5_ref) v s) ((of_regval pmpaddr5_ref) v) else
+ if reg_name = (''pmpaddr4'') then map_option (\<lambda> v . (write_to pmpaddr4_ref) v s) ((of_regval pmpaddr4_ref) v) else
+ if reg_name = (''pmpaddr3'') then map_option (\<lambda> v . (write_to pmpaddr3_ref) v s) ((of_regval pmpaddr3_ref) v) else
+ if reg_name = (''pmpaddr2'') then map_option (\<lambda> v . (write_to pmpaddr2_ref) v s) ((of_regval pmpaddr2_ref) v) else
+ if reg_name = (''pmpaddr1'') then map_option (\<lambda> v . (write_to pmpaddr1_ref) v s) ((of_regval pmpaddr1_ref) v) else
+ if reg_name = (''pmpaddr0'') then map_option (\<lambda> v . (write_to pmpaddr0_ref) v s) ((of_regval pmpaddr0_ref) v) else
+ if reg_name = (''pmp15cfg'') then map_option (\<lambda> v . (write_to pmp15cfg_ref) v s) ((of_regval pmp15cfg_ref) v) else
+ if reg_name = (''pmp14cfg'') then map_option (\<lambda> v . (write_to pmp14cfg_ref) v s) ((of_regval pmp14cfg_ref) v) else
+ if reg_name = (''pmp13cfg'') then map_option (\<lambda> v . (write_to pmp13cfg_ref) v s) ((of_regval pmp13cfg_ref) v) else
+ if reg_name = (''pmp12cfg'') then map_option (\<lambda> v . (write_to pmp12cfg_ref) v s) ((of_regval pmp12cfg_ref) v) else
+ if reg_name = (''pmp11cfg'') then map_option (\<lambda> v . (write_to pmp11cfg_ref) v s) ((of_regval pmp11cfg_ref) v) else
+ if reg_name = (''pmp10cfg'') then map_option (\<lambda> v . (write_to pmp10cfg_ref) v s) ((of_regval pmp10cfg_ref) v) else
+ if reg_name = (''pmp9cfg'') then map_option (\<lambda> v . (write_to pmp9cfg_ref) v s) ((of_regval pmp9cfg_ref) v) else
+ if reg_name = (''pmp8cfg'') then map_option (\<lambda> v . (write_to pmp8cfg_ref) v s) ((of_regval pmp8cfg_ref) v) else
+ if reg_name = (''pmp7cfg'') then map_option (\<lambda> v . (write_to pmp7cfg_ref) v s) ((of_regval pmp7cfg_ref) v) else
+ if reg_name = (''pmp6cfg'') then map_option (\<lambda> v . (write_to pmp6cfg_ref) v s) ((of_regval pmp6cfg_ref) v) else
+ if reg_name = (''pmp5cfg'') then map_option (\<lambda> v . (write_to pmp5cfg_ref) v s) ((of_regval pmp5cfg_ref) v) else
+ if reg_name = (''pmp4cfg'') then map_option (\<lambda> v . (write_to pmp4cfg_ref) v s) ((of_regval pmp4cfg_ref) v) else
+ if reg_name = (''pmp3cfg'') then map_option (\<lambda> v . (write_to pmp3cfg_ref) v s) ((of_regval pmp3cfg_ref) v) else
+ if reg_name = (''pmp2cfg'') then map_option (\<lambda> v . (write_to pmp2cfg_ref) v s) ((of_regval pmp2cfg_ref) v) else
+ if reg_name = (''pmp1cfg'') then map_option (\<lambda> v . (write_to pmp1cfg_ref) v s) ((of_regval pmp1cfg_ref) v) else
+ if reg_name = (''pmp0cfg'') then map_option (\<lambda> v . (write_to pmp0cfg_ref) v s) ((of_regval pmp0cfg_ref) v) else
+ if reg_name = (''tselect'') then map_option (\<lambda> v . (write_to tselect_ref) v s) ((of_regval tselect_ref) v) else
+ if reg_name = (''stval'') then map_option (\<lambda> v . (write_to stval_ref) v s) ((of_regval stval_ref) v) else
+ if reg_name = (''scause'') then map_option (\<lambda> v . (write_to scause_ref) v s) ((of_regval scause_ref) v) else
+ if reg_name = (''sepc'') then map_option (\<lambda> v . (write_to sepc_ref) v s) ((of_regval sepc_ref) v) else
+ if reg_name = (''sscratch'') then map_option (\<lambda> v . (write_to sscratch_ref) v s) ((of_regval sscratch_ref) v) else
+ if reg_name = (''stvec'') then map_option (\<lambda> v . (write_to stvec_ref) v s) ((of_regval stvec_ref) v) else
+ if reg_name = (''sideleg'') then map_option (\<lambda> v . (write_to sideleg_ref) v s) ((of_regval sideleg_ref) v) else
+ if reg_name = (''sedeleg'') then map_option (\<lambda> v . (write_to sedeleg_ref) v s) ((of_regval sedeleg_ref) v) else
+ if reg_name = (''mhartid'') then map_option (\<lambda> v . (write_to mhartid_ref) v s) ((of_regval mhartid_ref) v) else
+ if reg_name = (''marchid'') then map_option (\<lambda> v . (write_to marchid_ref) v s) ((of_regval marchid_ref) v) else
+ if reg_name = (''mimpid'') then map_option (\<lambda> v . (write_to mimpid_ref) v s) ((of_regval mimpid_ref) v) else
+ if reg_name = (''mvendorid'') then map_option (\<lambda> v . (write_to mvendorid_ref) v s) ((of_regval mvendorid_ref) v) else
+ if reg_name = (''minstret_written'') then map_option (\<lambda> v . (write_to minstret_written_ref) v s) ((of_regval minstret_written_ref) v) else
+ if reg_name = (''minstret'') then map_option (\<lambda> v . (write_to minstret_ref) v s) ((of_regval minstret_ref) v) else
+ if reg_name = (''mtime'') then map_option (\<lambda> v . (write_to mtime_ref) v s) ((of_regval mtime_ref) v) else
+ if reg_name = (''mcycle'') then map_option (\<lambda> v . (write_to mcycle_ref) v s) ((of_regval mcycle_ref) v) else
+ if reg_name = (''scounteren'') then map_option (\<lambda> v . (write_to scounteren_ref) v s) ((of_regval scounteren_ref) v) else
+ if reg_name = (''mcounteren'') then map_option (\<lambda> v . (write_to mcounteren_ref) v s) ((of_regval mcounteren_ref) v) else
+ if reg_name = (''mscratch'') then map_option (\<lambda> v . (write_to mscratch_ref) v s) ((of_regval mscratch_ref) v) else
+ if reg_name = (''mtval'') then map_option (\<lambda> v . (write_to mtval_ref) v s) ((of_regval mtval_ref) v) else
+ if reg_name = (''mepc'') then map_option (\<lambda> v . (write_to mepc_ref) v s) ((of_regval mepc_ref) v) else
+ if reg_name = (''mcause'') then map_option (\<lambda> v . (write_to mcause_ref) v s) ((of_regval mcause_ref) v) else
+ if reg_name = (''mtvec'') then map_option (\<lambda> v . (write_to mtvec_ref) v s) ((of_regval mtvec_ref) v) else
+ if reg_name = (''medeleg'') then map_option (\<lambda> v . (write_to medeleg_ref) v s) ((of_regval medeleg_ref) v) else
+ if reg_name = (''mideleg'') then map_option (\<lambda> v . (write_to mideleg_ref) v s) ((of_regval mideleg_ref) v) else
+ if reg_name = (''mie'') then map_option (\<lambda> v . (write_to mie_ref) v s) ((of_regval mie_ref) v) else
+ if reg_name = (''mip'') then map_option (\<lambda> v . (write_to mip_ref) v s) ((of_regval mip_ref) v) else
+ if reg_name = (''mstatus'') then map_option (\<lambda> v . (write_to mstatus_ref) v s) ((of_regval mstatus_ref) v) else
+ if reg_name = (''misa'') then map_option (\<lambda> v . (write_to misa_ref) v s) ((of_regval misa_ref) v) else
+ if reg_name = (''cur_inst'') then map_option (\<lambda> v . (write_to cur_inst_ref) v s) ((of_regval cur_inst_ref) v) else
+ if reg_name = (''cur_privilege'') then map_option (\<lambda> v . (write_to cur_privilege_ref) v s) ((of_regval cur_privilege_ref) v) else
+ if reg_name = (''x31'') then map_option (\<lambda> v . (write_to x31_ref) v s) ((of_regval x31_ref) v) else
+ if reg_name = (''x30'') then map_option (\<lambda> v . (write_to x30_ref) v s) ((of_regval x30_ref) v) else
+ if reg_name = (''x29'') then map_option (\<lambda> v . (write_to x29_ref) v s) ((of_regval x29_ref) v) else
+ if reg_name = (''x28'') then map_option (\<lambda> v . (write_to x28_ref) v s) ((of_regval x28_ref) v) else
+ if reg_name = (''x27'') then map_option (\<lambda> v . (write_to x27_ref) v s) ((of_regval x27_ref) v) else
+ if reg_name = (''x26'') then map_option (\<lambda> v . (write_to x26_ref) v s) ((of_regval x26_ref) v) else
+ if reg_name = (''x25'') then map_option (\<lambda> v . (write_to x25_ref) v s) ((of_regval x25_ref) v) else
+ if reg_name = (''x24'') then map_option (\<lambda> v . (write_to x24_ref) v s) ((of_regval x24_ref) v) else
+ if reg_name = (''x23'') then map_option (\<lambda> v . (write_to x23_ref) v s) ((of_regval x23_ref) v) else
+ if reg_name = (''x22'') then map_option (\<lambda> v . (write_to x22_ref) v s) ((of_regval x22_ref) v) else
+ if reg_name = (''x21'') then map_option (\<lambda> v . (write_to x21_ref) v s) ((of_regval x21_ref) v) else
+ if reg_name = (''x20'') then map_option (\<lambda> v . (write_to x20_ref) v s) ((of_regval x20_ref) v) else
+ if reg_name = (''x19'') then map_option (\<lambda> v . (write_to x19_ref) v s) ((of_regval x19_ref) v) else
+ if reg_name = (''x18'') then map_option (\<lambda> v . (write_to x18_ref) v s) ((of_regval x18_ref) v) else
+ if reg_name = (''x17'') then map_option (\<lambda> v . (write_to x17_ref) v s) ((of_regval x17_ref) v) else
+ if reg_name = (''x16'') then map_option (\<lambda> v . (write_to x16_ref) v s) ((of_regval x16_ref) v) else
+ if reg_name = (''x15'') then map_option (\<lambda> v . (write_to x15_ref) v s) ((of_regval x15_ref) v) else
+ if reg_name = (''x14'') then map_option (\<lambda> v . (write_to x14_ref) v s) ((of_regval x14_ref) v) else
+ if reg_name = (''x13'') then map_option (\<lambda> v . (write_to x13_ref) v s) ((of_regval x13_ref) v) else
+ if reg_name = (''x12'') then map_option (\<lambda> v . (write_to x12_ref) v s) ((of_regval x12_ref) v) else
+ if reg_name = (''x11'') then map_option (\<lambda> v . (write_to x11_ref) v s) ((of_regval x11_ref) v) else
+ if reg_name = (''x10'') then map_option (\<lambda> v . (write_to x10_ref) v s) ((of_regval x10_ref) v) else
+ if reg_name = (''x9'') then map_option (\<lambda> v . (write_to x9_ref) v s) ((of_regval x9_ref) v) else
+ if reg_name = (''x8'') then map_option (\<lambda> v . (write_to x8_ref) v s) ((of_regval x8_ref) v) else
+ if reg_name = (''x7'') then map_option (\<lambda> v . (write_to x7_ref) v s) ((of_regval x7_ref) v) else
+ if reg_name = (''x6'') then map_option (\<lambda> v . (write_to x6_ref) v s) ((of_regval x6_ref) v) else
+ if reg_name = (''x5'') then map_option (\<lambda> v . (write_to x5_ref) v s) ((of_regval x5_ref) v) else
+ if reg_name = (''x4'') then map_option (\<lambda> v . (write_to x4_ref) v s) ((of_regval x4_ref) v) else
+ if reg_name = (''x3'') then map_option (\<lambda> v . (write_to x3_ref) v s) ((of_regval x3_ref) v) else
+ if reg_name = (''x2'') then map_option (\<lambda> v . (write_to x2_ref) v s) ((of_regval x2_ref) v) else
+ if reg_name = (''x1'') then map_option (\<lambda> v . (write_to x1_ref) v s) ((of_regval x1_ref) v) else
+ if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else
+ if reg_name = (''instbits'') then map_option (\<lambda> v . (write_to instbits_ref) v s) ((of_regval instbits_ref) v) else
+ if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else
+ if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else
+ None )"
+ for reg_name :: " string "
+ and v :: " register_value "
+ and s :: " regstate "
+
+
+definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where
+ " register_accessors = ( (get_regval, set_regval))"
+
+
+
+type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR "
+type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad "
+end
diff --git a/prover_snapshots/isabelle/lib/ROOTS b/prover_snapshots/isabelle/lib/ROOTS
new file mode 100644
index 0000000..ca9e18c
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/ROOTS
@@ -0,0 +1,2 @@
+lem
+sail
diff --git a/prover_snapshots/isabelle/lib/lem/Lem.thy b/prover_snapshots/isabelle/lib/lem/Lem.thy
new file mode 100644
index 0000000..ae2c2f2
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem.thy
@@ -0,0 +1,108 @@
+(*========================================================================*)
+(* Lem *)
+(* *)
+(* Dominic Mulligan, University of Cambridge *)
+(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *)
+(* Gabriel Kerneis, University of Cambridge *)
+(* Kathy Gray, University of Cambridge *)
+(* Peter Boehm, University of Cambridge (while working on Lem) *)
+(* Peter Sewell, University of Cambridge *)
+(* Scott Owens, University of Kent *)
+(* Thomas Tuerk, University of Cambridge *)
+(* Brian Campbell, University of Edinburgh *)
+(* Shaked Flur, University of Cambridge *)
+(* Thomas Bauereiss, University of Cambridge *)
+(* Stephen Kell, University of Cambridge *)
+(* Thomas Williams *)
+(* Lars Hupel *)
+(* Basile Clement *)
+(* *)
+(* The Lem sources are copyright 2010-2018 *)
+(* by the authors above and Institut National de Recherche en *)
+(* Informatique et en Automatique (INRIA). *)
+(* *)
+(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *)
+(* are distributed under the license below. The former are distributed *)
+(* under the LGPLv2, as in the LICENSE file. *)
+(* *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in the *)
+(* documentation and/or other materials provided with the distribution. *)
+(* 3. The names of the authors may not be used to endorse or promote *)
+(* products derived from this software without specific prior written *)
+(* permission. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *)
+(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *)
+(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *)
+(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *)
+(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *)
+(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *)
+(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *)
+(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *)
+(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *)
+(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *)
+(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *)
+(*========================================================================*)
+
+chapter\<open>Mappings of Syntax needed by Lem\<close>
+
+theory "Lem"
+
+imports
+ LemExtraDefs
+ "HOL-Word.Word"
+begin
+
+type_synonym numeral = nat
+
+subsection \<open>Finite Maps\<close>
+
+abbreviation (input) "map_find k m \<equiv> the (m k)"
+abbreviation (input) "map_update k v m \<equiv> m (k \<mapsto> v)"
+abbreviation (input) "map_remove k m \<equiv> m |` (- {k})"
+abbreviation (input) "map_any P m \<equiv> \<exists> (k, v) \<in> map_to_set m. P k v"
+abbreviation (input) "map_all P m \<equiv> \<forall> (k, v) \<in> map_to_set m. P k v"
+
+subsection \<open>Lists\<close>
+
+abbreviation (input) "list_mem e l \<equiv> (e \<in> set l)"
+abbreviation (input) "list_forall P l \<equiv> (\<forall>e\<in>set l. P e)"
+abbreviation (input) "list_exists P l \<equiv> (\<exists>e\<in>set l. P e)"
+abbreviation (input) "list_unzip l \<equiv> (map fst l, map snd l)"
+
+subsection \<open>Sets\<close>
+
+abbreviation (input) "set_filter P (s::'a set) \<equiv> {x \<in> s. P x}"
+abbreviation (input) "set_bigunion S \<equiv> \<Union> S"
+abbreviation (input) "set_biginter S \<equiv> \<Inter> S"
+
+subsection \<open>Natural numbers\<close>
+
+subsection \<open>Integers\<close>
+
+
+subsection \<open>Dummy\<close>
+
+consts
+ bitwise_xor :: "nat \<Rightarrow> nat \<Rightarrow> nat"
+ num_asr :: "nat \<Rightarrow> nat \<Rightarrow> nat"
+ num_lsl :: "nat \<Rightarrow> nat \<Rightarrow> nat"
+ bitwise_or :: "nat \<Rightarrow> nat \<Rightarrow> nat"
+ bitwise_not :: "nat \<Rightarrow> nat"
+ bitwise_and :: "nat \<Rightarrow> nat \<Rightarrow> nat"
+
+subsection \<open>Machine words\<close>
+
+definition word_update :: "'a::len word \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow> 'b::len word \<Rightarrow> 'a word" where
+ "word_update v lo hi w =
+ (let sz = size v in
+ of_bl (take (sz-hi-1) (to_bl v) @ to_bl w @ drop (sz-lo) (to_bl v)))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/LemExtraDefs.thy b/prover_snapshots/isabelle/lib/lem/LemExtraDefs.thy
new file mode 100644
index 0000000..e43ff66
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/LemExtraDefs.thy
@@ -0,0 +1,1255 @@
+(*========================================================================*)
+(* Lem *)
+(* *)
+(* Dominic Mulligan, University of Cambridge *)
+(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *)
+(* Gabriel Kerneis, University of Cambridge *)
+(* Kathy Gray, University of Cambridge *)
+(* Peter Boehm, University of Cambridge (while working on Lem) *)
+(* Peter Sewell, University of Cambridge *)
+(* Scott Owens, University of Kent *)
+(* Thomas Tuerk, University of Cambridge *)
+(* Brian Campbell, University of Edinburgh *)
+(* Shaked Flur, University of Cambridge *)
+(* Thomas Bauereiss, University of Cambridge *)
+(* Stephen Kell, University of Cambridge *)
+(* Thomas Williams *)
+(* Lars Hupel *)
+(* Basile Clement *)
+(* *)
+(* The Lem sources are copyright 2010-2018 *)
+(* by the authors above and Institut National de Recherche en *)
+(* Informatique et en Automatique (INRIA). *)
+(* *)
+(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *)
+(* are distributed under the license below. The former are distributed *)
+(* under the LGPLv2, as in the LICENSE file. *)
+(* *)
+(* *)
+(* Redistribution and use in source and binary forms, with or without *)
+(* modification, are permitted provided that the following conditions *)
+(* are met: *)
+(* 1. Redistributions of source code must retain the above copyright *)
+(* notice, this list of conditions and the following disclaimer. *)
+(* 2. Redistributions in binary form must reproduce the above copyright *)
+(* notice, this list of conditions and the following disclaimer in the *)
+(* documentation and/or other materials provided with the distribution. *)
+(* 3. The names of the authors may not be used to endorse or promote *)
+(* products derived from this software without specific prior written *)
+(* permission. *)
+(* *)
+(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *)
+(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *)
+(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *)
+(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *)
+(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *)
+(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *)
+(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *)
+(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *)
+(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *)
+(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *)
+(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *)
+(*========================================================================*)
+
+chapter \<open>Auxiliary Definitions needed by Lem\<close>
+
+theory "LemExtraDefs"
+
+imports
+ Main
+ "HOL-Library.Permutation"
+ "HOL-Library.While_Combinator"
+begin
+
+subsection \<open>General\<close>
+
+consts failwith :: " 'a \<Rightarrow> 'b"
+
+subsection \<open>Lists\<close>
+
+fun index :: " 'a list \<Rightarrow> nat \<Rightarrow> 'a option " where
+ "index [] n = None"
+ | "index (x # xs) 0 = Some x"
+ | "index (x # xs) (Suc n) = index xs n"
+
+lemma index_eq_some [simp]:
+ "index l n = Some x \<longleftrightarrow> (n < length l \<and> (x = l ! n))"
+proof (induct l arbitrary: n x)
+ case Nil thus ?case by simp
+next
+ case (Cons e es n x)
+ note ind_hyp = this
+
+ show ?case
+ proof (cases n)
+ case 0 thus ?thesis by auto
+ next
+ case (Suc n')
+ with ind_hyp show ?thesis by simp
+ qed
+qed
+
+lemma index_eq_none [simp]:
+ "index l n = None \<longleftrightarrow> length l \<le> n"
+by (rule iffD1[OF Not_eq_iff]) auto
+
+
+lemma index_simps [simp]:
+ "length l \<le> n \<Longrightarrow> index l n = None"
+ "n < length l \<Longrightarrow> index l n = Some (l ! n)"
+by (simp_all)
+
+fun find_indices :: "('a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> nat list" where
+ "find_indices P [] = []"
+ | "find_indices P (x # xs) = (if P x then 0 # (map Suc (find_indices P xs)) else (map Suc (find_indices P xs)))"
+
+lemma length_find_indices :
+ "length (find_indices P l) \<le> length l"
+by (induct l) auto
+
+lemma sorted_map_suc :
+ "sorted l \<Longrightarrow> sorted (map Suc l)"
+by (induct l) (simp_all)
+
+lemma sorted_find_indices :
+ "sorted (find_indices P xs)"
+proof (induct xs)
+ case Nil thus ?case by simp
+next
+ case (Cons x xs)
+ from sorted_map_suc[OF this]
+ show ?case
+ by (simp)
+qed
+
+lemma find_indices_set [simp] :
+ "set (find_indices P l) = {i. i < length l \<and> P (l ! i)}"
+proof (intro set_eqI)
+ fix i
+ show "i \<in> set (find_indices P l) \<longleftrightarrow> (i \<in> {i. i < length l \<and> P (l ! i)})"
+ proof (induct l arbitrary: i)
+ case Nil thus ?case by simp
+ next
+ case (Cons x l' i)
+ note ind_hyp = this
+ show ?case
+ proof (cases i)
+ case 0 thus ?thesis by auto
+ next
+ case (Suc i') with ind_hyp[of i'] show ?thesis by auto
+ qed
+ qed
+qed
+
+definition find_index where
+ "find_index P xs = (case find_indices P xs of
+ [] \<Rightarrow> None
+ | i # _ \<Rightarrow> Some i)"
+
+lemma find_index_eq_some [simp] :
+ "(find_index P xs = Some ii) \<longleftrightarrow> (ii < length xs \<and> P (xs ! ii) \<and> (\<forall>i' < ii. \<not>(P (xs ! i'))))"
+ (is "?lhs = ?rhs")
+proof (cases "find_indices P xs")
+ case Nil
+ with find_indices_set[of P xs]
+ show ?thesis
+ unfolding find_index_def by auto
+next
+ case (Cons i il) note find_indices_eq = this
+
+ from sorted_find_indices[of P xs] find_indices_eq
+ have "sorted (i # il)" by simp
+ hence i_leq: "\<And>i'. i' \<in> set (i # il) \<Longrightarrow> i \<le> i'" by auto
+
+ from find_indices_set[of P xs, unfolded find_indices_eq]
+ have set_i_il_eq:"\<And>i'. i' \<in> set (i # il) = (i' < length xs \<and> P (xs ! i'))"
+ by simp
+
+ have lhs_eq: "find_index P xs = Some i"
+ unfolding find_index_def find_indices_eq by simp
+
+ show ?thesis
+ proof (intro iffI)
+ assume ?lhs
+ with lhs_eq have ii_eq[simp]: "ii = i" by simp
+
+ from set_i_il_eq[of i] i_leq[unfolded set_i_il_eq]
+ show ?rhs by auto (metis leD less_trans)
+ next
+ assume ?rhs
+ with set_i_il_eq[of ii]
+ have "ii \<in> set (i # il) \<and> (ii \<le> i)"
+ by (metis leI length_pos_if_in_set nth_Cons_0 nth_mem set_i_il_eq)
+
+ with i_leq [of ii] have "i = ii" by simp
+ thus ?lhs unfolding lhs_eq by simp
+ qed
+qed
+
+lemma find_index_eq_none [simp] :
+ "(find_index P xs = None) \<longleftrightarrow> (\<forall>x \<in> set xs. \<not>(P x))" (is "?lhs = ?rhs")
+proof (rule iffD1[OF Not_eq_iff], intro iffI)
+ assume "\<not> ?lhs"
+ then obtain i where "find_index P xs = Some i" by auto
+ hence "i < length xs \<and> P (xs ! i)" by simp
+ thus "\<not> ?rhs" by auto
+next
+ let ?p = "(\<lambda>i. i < length xs \<and> P(xs ! i))"
+
+ assume "\<not> ?rhs"
+ then obtain i where "?p i"
+ by (metis in_set_conv_nth)
+
+ from LeastI [of ?p, OF \<open>?p i\<close>]
+ have "?p (Least ?p)" .
+
+ hence "find_index P xs = Some (Least ?p)"
+ by (subst find_index_eq_some) (metis (mono_tags) less_trans not_less_Least)
+
+ thus "\<not> ?lhs" by blast
+qed
+
+definition genlist where
+ "genlist f n = map f (upt 0 n)"
+
+lemma genlist_length [simp] :
+ "length (genlist f n) = n"
+unfolding genlist_def by simp
+
+lemma genlist_simps [simp]:
+ "genlist f 0 = []"
+ "genlist f (Suc n) = genlist f n @ [f n]"
+unfolding genlist_def by auto
+
+definition split_at where
+ "split_at n l = (take n l, drop n l)"
+
+fun delete_first :: "('a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> ('a list) option " where
+ "delete_first P [] = None"
+ | "delete_first P (x # xs) =
+ (if (P x) then Some xs else
+ map_option (\<lambda>xs'. x # xs') (delete_first P xs))"
+declare delete_first.simps [simp del]
+
+lemma delete_first_simps [simp] :
+ "delete_first P [] = None"
+ "P x \<Longrightarrow> delete_first P (x # xs) = Some xs"
+ "\<not>(P x) \<Longrightarrow> delete_first P (x # xs) = map_option (\<lambda>xs'. x # xs') (delete_first P xs)"
+unfolding delete_first.simps by auto
+
+lemmas delete_first_unroll = delete_first.simps(2)
+
+
+lemma delete_first_eq_none [simp] :
+ "delete_first P l = None \<longleftrightarrow> (\<forall>x \<in> set l. \<not> (P x))"
+by (induct l) (auto simp add: delete_first_unroll)
+
+lemma delete_first_eq_some :
+ "delete_first P l = (Some l') \<longleftrightarrow> (\<exists>l1 x l2. P x \<and> (\<forall>x \<in> set l1. \<not>(P x)) \<and> (l = l1 @ (x # l2)) \<and> (l' = l1 @ l2))"
+ (is "?lhs l l' = (\<exists>l1 x l2. ?rhs_body l1 x l2 l l')")
+proof (induct l arbitrary: l')
+ case Nil thus ?case by simp
+next
+ case (Cons e l l')
+ note ind_hyp = this
+
+ show ?case
+ proof (cases "P e")
+ case True
+ show ?thesis
+ proof (rule iffI)
+ assume "?lhs (e # l) l'"
+ with \<open>P e\<close> have "l = l'" by simp
+ with \<open>P e\<close> have "?rhs_body [] e l' (e # l) l'" by simp
+ thus "\<exists>l1 x l2. ?rhs_body l1 x l2 (e # l) l'" by blast
+ next
+ assume "\<exists>l1 x l2. ?rhs_body l1 x l2 (e # l) l'"
+ then obtain l1 x l2 where body_ok: "?rhs_body l1 x l2 (e # l) l'" by blast
+
+ from body_ok \<open>P e\<close> have l1_eq[simp]: "l = l'"
+ by (cases l1) (simp_all)
+ with \<open>P e\<close> show "?lhs (e # l) l'" by simp
+ qed
+ next
+ case False
+ define rhs_pred where "rhs_pred \<equiv> \<lambda>l1 x l2 l l'. ?rhs_body l1 x l2 l l'"
+ have rhs_fold: "\<And>l1 x l2 l l'. ?rhs_body l1 x l2 l l' = rhs_pred l1 x l2 l l'"
+ unfolding rhs_pred_def by simp
+
+ have "(\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l') = (\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l')"
+ proof (intro iffI)
+ assume "\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l'"
+ then obtain z l1 x l2 where "rhs_pred l1 x l2 l z" and l'_eq: "l' = e # z" by auto
+ with \<open>\<not>(P e)\<close> have "rhs_pred (e # l1) x l2 (e # l) l'"
+ unfolding rhs_pred_def by simp
+ thus "\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l'" by blast
+ next
+ assume "\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l'"
+ then obtain l1 x l2 where "rhs_pred l1 x l2 (e # l) l'" by blast
+ with \<open>\<not> (P e)\<close> obtain l1' where l1_eq[simp]: "l1 = e # l1'"
+ unfolding rhs_pred_def by (cases l1) (auto)
+
+ with \<open>rhs_pred l1 x l2 (e # l) l'\<close>
+ have "rhs_pred l1' x l2 l (l1' @ l2) \<and> e # (l1' @ l2) = l'"
+ unfolding rhs_pred_def by (simp)
+ thus "\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l'" by blast
+ qed
+ with \<open>\<not> P e\<close> show ?thesis
+ unfolding rhs_fold
+ by (simp add: ind_hyp[unfolded rhs_fold])
+ qed
+qed
+
+
+lemma perm_eval [code] :
+ "perm [] l \<longleftrightarrow> l = []" (is ?g1)
+ "perm (x # xs) l \<longleftrightarrow> (case delete_first (\<lambda>e. e = x) l of
+ None => False
+ | Some l' => perm xs l')" (is ?g2)
+proof -
+ show ?g1 by auto
+next
+ show ?g2
+ proof (cases "delete_first (\<lambda>e. e = x) l")
+ case None note del_eq = this
+ hence "x \<notin> set l" by auto
+ with perm_set_eq [of "x # xs" l]
+ have "\<not> perm (x # xs) l" by auto
+ thus ?thesis unfolding del_eq by simp
+ next
+ case (Some l') note del_eq = this
+
+ from del_eq[unfolded delete_first_eq_some]
+ obtain l1 l2 where l_eq: "l = l1 @ [x] @ l2" and l'_eq: "l' = l1 @ l2" by auto
+
+ have "(x # xs <~~> l1 @ x # l2) = (xs <~~> l1 @ l2)"
+ proof -
+ from perm_append_swap [of l1 "[x]"]
+ perm_append2 [of "l1 @ [x]" "x # l1" l2]
+ have "l1 @ x # l2 <~~> x # (l1 @ l2)" by simp
+ hence "x # xs <~~> l1 @ x # l2 \<longleftrightarrow> x # xs <~~> x # (l1 @ l2)"
+ by (metis perm.trans perm_sym)
+ thus ?thesis by simp
+ qed
+ with del_eq l_eq l'_eq show ?thesis by simp
+ qed
+qed
+
+
+fun sorted_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> bool " where
+ "sorted_by cmp [] = True"
+ | "sorted_by cmp [_] = True"
+ | "sorted_by cmp (x1 # x2 # xs) = ((cmp x1 x2) \<and> sorted_by cmp (x2 # xs))"
+
+lemma sorted_by_lesseq [simp] :
+ "sorted_by ((\<le>) :: ('a::{linorder}) => 'a => bool) = sorted"
+proof (rule ext)
+ fix l :: "'a list"
+ show "sorted_by (\<le>) l = sorted l"
+ proof (induct l)
+ case Nil thus ?case by simp
+ next
+ case (Cons x xs)
+ thus ?case by (cases xs) (simp_all del: sorted.simps(2) add: sorted2_simps)
+ qed
+qed
+
+lemma sorted_by_cons_imp :
+ "sorted_by cmp (x # xs) \<Longrightarrow> sorted_by cmp xs"
+by (cases xs) simp_all
+
+lemma sorted_by_cons_trans :
+ assumes trans_cmp: "transp cmp"
+ shows "sorted_by cmp (x # xs) = ((\<forall>x' \<in> set xs . cmp x x') \<and> sorted_by cmp xs)"
+proof (induct xs arbitrary: x)
+ case Nil thus ?case by simp
+next
+ case (Cons x2 xs x1)
+ note ind_hyp = this
+
+ from trans_cmp
+ show ?case
+ by (auto simp add: ind_hyp transp_def)
+qed
+
+
+fun insert_sort_insert_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ "insert_sort_insert_by cmp e ([]) = ( [e])"
+| "insert_sort_insert_by cmp e (x # xs) = ( if cmp e x then (e # (x # xs)) else x # (insert_sort_insert_by cmp e xs))"
+
+
+lemma insert_sort_insert_by_length [simp] :
+ "length (insert_sort_insert_by cmp e l) = Suc (length l)"
+by (induct l) auto
+
+lemma insert_sort_insert_by_set [simp] :
+ "set (insert_sort_insert_by cmp e l) = insert e (set l)"
+by (induct l) auto
+
+lemma insert_sort_insert_by_perm :
+ "(insert_sort_insert_by cmp e l) <~~> (e # l)"
+proof (induct l)
+ case Nil thus ?case by simp
+next
+ case (Cons e2 l')
+ note ind_hyp = this
+
+ have "e2 # e # l' <~~> e # e2 # l'" by (rule perm.swap)
+ hence "e2 # insert_sort_insert_by cmp e l' <~~> e # e2 # l'"
+ using ind_hyp by (metis cons_perm_eq perm.trans)
+ thus ?case by simp
+qed
+
+
+lemma insert_sort_insert_by_sorted_by :
+assumes cmp_cases: "\<And>y. y \<in> set l \<Longrightarrow> \<not> (cmp e y) \<Longrightarrow> cmp y e"
+assumes cmp_trans: "transp cmp"
+shows "sorted_by cmp l \<Longrightarrow> sorted_by cmp (insert_sort_insert_by cmp e l)"
+using cmp_cases
+proof (induct l)
+ case Nil thus ?case by simp
+next
+ case (Cons x1 l')
+ note ind_hyp = Cons(1)
+ note sorted_x1_l' = Cons(2)
+ note cmp_cases = Cons(3)
+
+ show ?case
+ proof (cases l')
+ case Nil with cmp_cases show ?thesis by simp
+ next
+ case (Cons x2 l'') note l'_eq = this
+
+ from l'_eq sorted_x1_l' have "cmp x1 x2" "sorted_by cmp l'" by simp_all
+
+ show ?thesis
+ proof (cases "cmp e x1")
+ case True
+ with \<open>cmp x1 x2\<close> \<open>sorted_by cmp l'\<close>
+ have "sorted_by cmp (x1 # l')"
+ unfolding l'_eq by (simp)
+ with \<open>cmp e x1\<close>
+ show ?thesis by simp
+ next
+ case False
+
+ with cmp_cases have "cmp x1 e" by simp
+ have "\<And>x'. x' \<in> set l' \<Longrightarrow> cmp x1 x'"
+ proof -
+ fix x'
+ assume "x' \<in> set l'"
+ hence "x' = x2 \<or> cmp x2 x'"
+ using \<open>sorted_by cmp l'\<close> l'_eq sorted_by_cons_trans [OF cmp_trans, of x2 l'']
+ by auto
+ with transpD[OF cmp_trans, of x1 x2 x'] \<open>cmp x1 x2\<close>
+ show "cmp x1 x'" by blast
+ qed
+ hence "sorted_by cmp (x1 # insert_sort_insert_by cmp e l')"
+ using ind_hyp [OF \<open>sorted_by cmp l'\<close>] \<open>cmp x1 e\<close> cmp_cases
+ unfolding sorted_by_cons_trans[OF cmp_trans]
+ by simp
+ with \<open>\<not>(cmp e x1)\<close>
+ show ?thesis by simp
+ qed
+ qed
+qed
+
+
+
+fun insert_sort_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ "insert_sort_by cmp [] = []"
+ | "insert_sort_by cmp (x # xs) = insert_sort_insert_by cmp x (insert_sort_by cmp xs)"
+
+
+lemma insert_sort_by_perm :
+ "(insert_sort_by cmp l) <~~> l"
+proof (induct l)
+ case Nil thus ?case by simp
+next
+ case (Cons x l)
+ thus ?case
+ by simp (metis cons_perm_eq insert_sort_insert_by_perm perm.trans)
+qed
+
+lemma insert_sort_by_length [simp]:
+ "length (insert_sort_by cmp l) = length l"
+by (induct l) auto
+
+lemma insert_sort_by_set [simp]:
+ "set (insert_sort_by cmp l) = set l"
+by (induct l) auto
+
+definition sort_by where
+ "sort_by = insert_sort_by"
+
+lemma sort_by_simps [simp]:
+ "length (sort_by cmp l) = length l"
+ "set (sort_by cmp l) = set l"
+unfolding sort_by_def by simp_all
+
+lemma sort_by_perm :
+ "sort_by cmp l <~~> l"
+unfolding sort_by_def
+by (simp add: insert_sort_by_perm)
+
+subsection \<open>Maps\<close>
+
+definition map_image :: "('v \<Rightarrow> 'w) \<Rightarrow> ('k, 'v) map \<Rightarrow> ('k, 'w) map" where
+ "map_image f m = (\<lambda>k. map_option f (m k))"
+
+definition map_domain_image :: "('k \<Rightarrow> 'v \<Rightarrow> 'w) \<Rightarrow> ('k, 'v) map \<Rightarrow> ('k, 'w) map" where
+ "map_domain_image f m = (\<lambda>k. map_option (f k) (m k))"
+
+
+lemma map_image_simps [simp]:
+ "(map_image f m) k = None \<longleftrightarrow> m k = None"
+ "(map_image f m) k = Some x \<longleftrightarrow> (\<exists>x'. (m k = Some x') \<and> (x = f x'))"
+ "(map_image f Map.empty) = Map.empty"
+ "(map_image f (m (k \<mapsto> v)) = (map_image f m) (k \<mapsto> f v))"
+unfolding map_image_def by auto
+
+lemma map_image_dom_ran [simp]:
+ "dom (map_image f m) = dom m"
+ "ran (map_image f m) = f ` (ran m)"
+unfolding dom_def ran_def by auto
+
+definition map_to_set :: "('k, 'v) map \<Rightarrow> ('k * 'v) set" where
+ "map_to_set m = { (k, v) . m k = Some v }"
+
+lemma map_to_set_simps [simp] :
+ "map_to_set Map.empty = {}" (is ?g1)
+ "map_to_set (m ((k::'k) \<mapsto> (v::'v))) = (insert (k, v) (map_to_set (m |` (- {k}))))" (is ?g2)
+proof -
+ show ?g1 unfolding map_to_set_def by simp
+next
+ show ?g2
+ proof (rule set_eqI)
+ fix kv :: "('k * 'v)"
+ obtain k' v' where kv_eq[simp]: "kv = (k', v')" by (rule prod.exhaust)
+
+ show "(kv \<in> map_to_set (m(k \<mapsto> v))) = (kv \<in> insert (k, v) (map_to_set (m |` (- {k}))))"
+ by (auto simp add: map_to_set_def)
+ qed
+qed
+
+
+subsection \<open>Sets\<close>
+
+definition "set_choose s \<equiv> (SOME x. (x \<in> s))"
+
+definition without_trans_edges :: "('a \<times> 'a) set \<Rightarrow> ('a \<times> 'a) set" where
+ "without_trans_edges S \<equiv>
+ let ts = trancl S in
+ { (x, y) \<in> S. \<forall>z \<in> snd ` S. x \<noteq> z \<and> y \<noteq> z \<longrightarrow> \<not> ((x, z) \<in> ts \<and> (z, y) \<in> ts)}"
+
+definition unbounded_lfp :: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where
+ "unbounded_lfp S f \<equiv>
+ while (\<lambda>x. x \<subset> S) f S"
+
+definition unbounded_gfp :: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where
+ "unbounded_gfp S f \<equiv>
+ while (\<lambda>x. S \<subset> x) f S"
+
+lemma set_choose_thm[simp]:
+ "s \<noteq> {} \<Longrightarrow> (set_choose s) \<in> s"
+unfolding set_choose_def
+by (rule someI_ex) auto
+
+lemma set_choose_sing [simp]:
+ "set_choose {x} = x"
+ unfolding set_choose_def
+ by auto
+
+lemma set_choose_code [code]:
+ "set_choose (set [x]) = x"
+by auto
+
+lemma set_choose_in [intro] :
+ assumes "s \<noteq> {}"
+ shows "set_choose s \<in> s"
+proof -
+ from \<open>s \<noteq> {}\<close>
+ obtain x where "x \<in> s" by auto
+ thus ?thesis
+ unfolding set_choose_def
+ by (rule someI)
+qed
+
+
+definition set_case where
+ "set_case s c_empty c_sing c_else =
+ (if (s = {}) then c_empty else
+ (if (card s = 1) then c_sing (set_choose s) else
+ c_else))"
+
+lemma set_case_simps [simp] :
+ "set_case {} c_empty c_sing c_else = c_empty"
+ "set_case {x} c_empty c_sing c_else = c_sing x"
+ "card s > 1 \<Longrightarrow> set_case s c_empty c_sing c_else = c_else"
+ "\<not>(finite s) \<Longrightarrow> set_case s c_empty c_sing c_else = c_else"
+unfolding set_case_def by auto
+
+lemma set_case_simp_insert2 [simp] :
+assumes x12_neq: "x1 \<noteq> x2"
+shows "set_case (insert x1 (insert x2 xs)) c_empty c_sing c_else = c_else"
+proof (cases "finite xs")
+ case False thus ?thesis by (simp)
+next
+ case True note fin_xs = this
+
+ have "card {x1,x2} \<le> card (insert x1 (insert x2 xs))"
+ by (rule card_mono) (auto simp add: fin_xs)
+ with x12_neq have "1 < card (insert x1 (insert x2 xs))" by simp
+ thus ?thesis by auto
+qed
+
+lemma set_case_code [code] :
+ "set_case (set []) c_empty c_sing c_else = c_empty"
+ "set_case (set [x]) c_empty c_sing c_else = c_sing x"
+ "set_case (set (x1 # x2 # xs)) c_empty c_sing c_else =
+ (if (x1 = x2) then
+ set_case (set (x2 # xs)) c_empty c_sing c_else
+ else
+ c_else)"
+by auto
+
+definition set_lfp:: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where
+ "set_lfp s f = lfp (\<lambda>s'. f s' \<union> s)"
+
+lemma set_lfp_tail_rec_def :
+assumes mono_f: "mono f"
+shows "set_lfp s f = (if (f s) \<subseteq> s then s else (set_lfp (s \<union> f s) f))" (is "?ls = ?rs")
+proof (cases "f s \<subseteq> s")
+ case True note fs_sub_s = this
+
+ from fs_sub_s have "\<Inter>{u. f u \<union> s \<subseteq> u} = s" by auto
+ hence "?ls = s" unfolding set_lfp_def lfp_def .
+ with fs_sub_s show "?ls = ?rs" by simp
+next
+ case False note not_fs_sub_s = this
+
+ from mono_f have mono_f': "mono (\<lambda>s'. f s' \<union> s)"
+ unfolding mono_def by auto
+
+ have "\<Inter>{u. f u \<union> s \<subseteq> u} = \<Inter>{u. f u \<union> (s \<union> f s) \<subseteq> u}" (is "\<Inter>?S1 = \<Inter>?S2")
+ proof
+ have "?S2 \<subseteq> ?S1" by auto
+ thus "\<Inter>?S1 \<subseteq> \<Inter>?S2" by (rule Inf_superset_mono)
+ next
+ { fix e
+ assume "e \<in> \<Inter>?S2"
+ hence S2_prop: "\<And>s'. f s' \<subseteq> s' \<Longrightarrow> s \<subseteq> s' \<Longrightarrow> f s \<subseteq> s' \<Longrightarrow> e \<in> s'" by simp
+
+ { fix s'
+ assume "f s' \<subseteq> s'" "s \<subseteq> s'"
+
+ from mono_f \<open>s \<subseteq> s'\<close>
+ have "f s \<subseteq> f s'" unfolding mono_def by simp
+ with \<open>f s' \<subseteq> s'\<close> have "f s \<subseteq> s'" by simp
+ with \<open>f s' \<subseteq> s'\<close> \<open>s \<subseteq> s'\<close> S2_prop
+ have "e \<in> s'" by simp
+ }
+ hence "e \<in> \<Inter>?S1" by simp
+ }
+ thus "\<Inter>?S2 \<subseteq> \<Inter>?S1" by auto
+ qed
+ hence "?ls = (set_lfp (s \<union> f s) f)"
+ unfolding set_lfp_def lfp_def .
+ with not_fs_sub_s show "?ls = ?rs" by simp
+qed
+
+lemma set_lfp_simps [simp] :
+"mono f \<Longrightarrow> f s \<subseteq> s \<Longrightarrow> set_lfp s f = s"
+"mono f \<Longrightarrow> \<not>(f s \<subseteq> s) \<Longrightarrow> set_lfp s f = (set_lfp (s \<union> f s) f)"
+by (metis set_lfp_tail_rec_def)+
+
+
+fun insert_in_list_at_arbitrary_pos where
+ "insert_in_list_at_arbitrary_pos x [] = {[x]}"
+ | "insert_in_list_at_arbitrary_pos x (y # ys) =
+ insert (x # y # ys) ((\<lambda>l. y # l) ` (insert_in_list_at_arbitrary_pos x ys))"
+
+lemma insert_in_list_at_arbitrary_pos_thm :
+ "xl \<in> insert_in_list_at_arbitrary_pos x l \<longleftrightarrow>
+ (\<exists>l1 l2. l = l1 @ l2 \<and> xl = l1 @ [x] @ l2)"
+proof (induct l arbitrary: xl)
+ case Nil thus ?case by simp
+next
+ case (Cons y l xyl)
+ note ind_hyp = this
+
+ show ?case
+ proof (rule iffI)
+ assume xyl_in: "xyl \<in> insert_in_list_at_arbitrary_pos x (y # l)"
+ show "\<exists>l1 l2. y # l = l1 @ l2 \<and> xyl = l1 @ [x] @ l2"
+ proof (cases "xyl = x # y # l")
+ case True
+ hence "y # l = [] @ (y # l) \<and> xyl = [] @ [x] @ (y # l)" by simp
+ thus ?thesis by blast
+ next
+ case False
+ with xyl_in have "xyl \<in> (#) y ` insert_in_list_at_arbitrary_pos x l" by simp
+ with ind_hyp obtain l1 l2 where "l = l1 @ l2 \<and> xyl = y # l1 @ x # l2"
+ by (auto simp add: image_def Bex_def)
+ hence "y # l = (y # l1) @ l2 \<and> xyl = (y # l1) @ [x] @ l2" by simp
+ thus ?thesis by blast
+ qed
+ next
+ assume "\<exists>l1 l2. y # l = l1 @ l2 \<and> xyl = l1 @ [x] @ l2"
+ then obtain l1 l2 where yl_eq: "y # l = l1 @ l2" and xyl_eq: "xyl = l1 @ [x] @ l2" by blast
+ show "xyl \<in> insert_in_list_at_arbitrary_pos x (y # l)"
+ proof (cases l1)
+ case Nil
+ with yl_eq xyl_eq
+ have "xyl = x # y # l" by simp
+ thus ?thesis by simp
+ next
+ case (Cons y' l1')
+ with yl_eq have l1_eq: "l1 = y # l1'" and l_eq: "l = l1' @ l2" by simp_all
+
+ have "\<exists>l1'' l2''. l = l1'' @ l2'' \<and> l1' @ [x] @ l2 = l1'' @ [x] @ l2''"
+ apply (rule_tac exI[where x = l1'])
+ apply (rule_tac exI [where x = l2])
+ apply (simp add: l_eq)
+ done
+ hence "(l1' @ [x] @ l2) \<in> insert_in_list_at_arbitrary_pos x l"
+ unfolding ind_hyp by blast
+ hence "\<exists>l'. l' \<in> insert_in_list_at_arbitrary_pos x l \<and> l1 @ x # l2 = y # l'"
+ by (rule_tac exI [where x = "l1' @ [x] @ l2"]) (simp add: l1_eq)
+ thus ?thesis
+ by (simp add: image_def Bex_def xyl_eq)
+ qed
+ qed
+qed
+
+definition list_of_set_set :: "'a set \<Rightarrow> ('a list) set" where
+"list_of_set_set s = { l . (set l = s) \<and> distinct l }"
+
+lemma list_of_set_set_empty [simp]:
+ "list_of_set_set {} = {[]}"
+unfolding list_of_set_set_def by auto
+
+lemma list_of_set_set_insert [simp] :
+ "list_of_set_set (insert x s) =
+ \<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x})))"
+ (is "?lhs = ?rhs")
+proof (intro set_eqI)
+ fix l
+
+ have "(set l = insert x s \<and> distinct l) \<longleftrightarrow> (\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2)"
+ proof (intro iffI)
+ assume "set l = insert x s \<and> distinct l"
+ hence set_l_eq: "set l = insert x s" and "distinct l" by simp_all
+
+ from \<open>set l = insert x s\<close>
+ have "x \<in> set l" by simp
+ then obtain l1 l2 where l_eq: "l = l1 @ x # l2"
+ unfolding in_set_conv_decomp by blast
+
+ from \<open>distinct l\<close> l_eq
+ have "distinct (l1 @ l2)" and x_nin: "x \<notin> set (l1 @ l2)"
+ by auto
+
+ from x_nin set_l_eq[unfolded l_eq]
+ have set_l12_eq: "set (l1 @ l2) = s - {x}"
+ by auto
+
+ from \<open>distinct (l1 @ l2)\<close> l_eq set_l12_eq
+ show "\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2"
+ by blast
+ next
+ assume "\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2"
+ then obtain l1 l2 where "set (l1 @ l2) = s - {x}" "distinct (l1 @ l2)" "l = l1 @ x # l2"
+ by blast
+ thus "set l = insert x s \<and> distinct l"
+ by auto
+ qed
+
+ thus "l \<in> list_of_set_set (insert x s) \<longleftrightarrow> l \<in> (\<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x}))))"
+ unfolding list_of_set_set_def
+ by (simp add: insert_in_list_at_arbitrary_pos_thm ex_simps[symmetric] del: ex_simps)
+qed
+
+lemma list_of_set_set_code [code]:
+ "list_of_set_set (set []) = {[]}"
+ "list_of_set_set (set (x # xs)) =
+ \<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set ((set xs) - {x})))"
+by simp_all
+
+lemma list_of_set_set_is_empty :
+ "list_of_set_set s = {} \<longleftrightarrow> \<not> (finite s)"
+proof -
+ have "finite s \<longleftrightarrow> (\<exists>l. set l = s \<and> distinct l)"
+ proof (rule iffI)
+ assume "\<exists>l. set l = s \<and> distinct l" then
+ obtain l where "s = set l" by blast
+ thus "finite s" by simp
+ next
+ assume "finite s"
+ thus "\<exists>l. set l = s \<and> distinct l"
+ proof (induct s)
+ case empty
+ show ?case by auto
+ next
+ case (insert e s)
+ note e_nin_s = insert(2)
+ from insert(3) obtain l where set_l: "set l = s" and dist_l: "distinct l" by blast
+
+ from set_l have set_el: "set (e # l) = insert e s" by auto
+ from dist_l set_l e_nin_s have dist_el: "distinct (e # l)" by simp
+
+ from set_el dist_el show ?case by blast
+ qed
+ qed
+ thus ?thesis
+ unfolding list_of_set_set_def by simp
+qed
+
+definition list_of_set :: "'a set \<Rightarrow> 'a list" where
+ "list_of_set s = set_choose (list_of_set_set s)"
+
+lemma list_of_set [simp] :
+ assumes fin_s: "finite s"
+ shows "set (list_of_set s) = s"
+ "distinct (list_of_set s)"
+proof -
+ from fin_s list_of_set_set_is_empty[of s]
+ have "\<not> (list_of_set_set s = {})" by simp
+ hence "list_of_set s \<in> list_of_set_set s"
+ unfolding list_of_set_def
+ by (rule set_choose_thm)
+ thus "set (list_of_set s) = s"
+ "distinct (list_of_set s)" unfolding list_of_set_set_def
+ by simp_all
+qed
+
+lemma list_of_set_in:
+ "finite s \<Longrightarrow> list_of_set s \<in> list_of_set_set s"
+unfolding list_of_set_def
+by (metis list_of_set_set_is_empty set_choose_thm)
+
+definition ordered_list_of_set where
+ "ordered_list_of_set cmp s = set_choose (sort_by cmp ` list_of_set_set s)"
+
+subsection \<open>sum\<close>
+
+find_consts "'a list => ('a list * _)"
+
+fun sum_partition :: "('a + 'b) list \<Rightarrow> 'a list * 'b list" where
+ "sum_partition [] = ([], [])"
+| "sum_partition ((Inl l) # lrs) =
+ (let (ll, rl) = sum_partition lrs in
+ (l # ll, rl))"
+| "sum_partition ((Inr r) # lrs) =
+ (let (ll, rl) = sum_partition lrs in
+ (ll, r # rl))"
+
+lemma sum_partition_length :
+ "List.length lrs = List.length (fst (sum_partition lrs)) + List.length (snd (sum_partition lrs))"
+proof (induct lrs)
+ case Nil thus ?case by simp
+next
+ case (Cons lr lrs) thus ?case
+ by (cases lr) (auto split: prod.split)
+qed
+
+subsection \<open>sorting\<close>
+
+subsection \<open>Strings\<close>
+
+declare String.literal.explode_inverse [simp]
+
+subsection \<open>num to string conversions\<close>
+
+definition nat_list_to_string :: "nat list \<Rightarrow> string" where
+ "nat_list_to_string nl = map char_of nl"
+
+definition is_digit where
+ "is_digit (n::nat) = (n < 10)"
+
+lemma is_digit_simps[simp] :
+ "n < 10 \<Longrightarrow> is_digit n"
+ "\<not>(n < 10) \<Longrightarrow> \<not>(is_digit n)"
+unfolding is_digit_def by simp_all
+
+lemma is_digit_expand :
+ "is_digit n \<longleftrightarrow>
+ (n = 0) \<or> (n = 1) \<or> (n = 2) \<or> (n = 3) \<or> (n = 4) \<or>
+ (n = 5) \<or> (n = 6) \<or> (n = 7) \<or> (n = 8) \<or> (n = 9)"
+unfolding is_digit_def by auto
+
+lemmas is_digitE = is_digit_expand[THEN iffD1,elim_format]
+lemmas is_digitI = is_digit_expand[THEN iffD2,rule_format]
+
+definition is_digit_char where
+ "is_digit_char c \<longleftrightarrow>
+ (c = CHR ''0'') \<or> (c = CHR ''5'') \<or>
+ (c = CHR ''1'') \<or> (c = CHR ''6'') \<or>
+ (c = CHR ''2'') \<or> (c = CHR ''7'') \<or>
+ (c = CHR ''3'') \<or> (c = CHR ''8'') \<or>
+ (c = CHR ''4'') \<or> (c = CHR ''9'')"
+
+lemma is_digit_char_simps[simp] :
+ "is_digit_char (CHR ''0'')"
+ "is_digit_char (CHR ''1'')"
+ "is_digit_char (CHR ''2'')"
+ "is_digit_char (CHR ''3'')"
+ "is_digit_char (CHR ''4'')"
+ "is_digit_char (CHR ''5'')"
+ "is_digit_char (CHR ''6'')"
+ "is_digit_char (CHR ''7'')"
+ "is_digit_char (CHR ''8'')"
+ "is_digit_char (CHR ''9'')"
+unfolding is_digit_char_def by simp_all
+
+lemmas is_digit_charE = is_digit_char_def[THEN iffD1,elim_format]
+lemmas is_digit_charI = is_digit_char_def[THEN iffD2,rule_format]
+
+definition digit_to_char :: "nat \<Rightarrow> char" where
+ "digit_to_char n = (
+ if n = 0 then CHR ''0''
+ else if n = 1 then CHR ''1''
+ else if n = 2 then CHR ''2''
+ else if n = 3 then CHR ''3''
+ else if n = 4 then CHR ''4''
+ else if n = 5 then CHR ''5''
+ else if n = 6 then CHR ''6''
+ else if n = 7 then CHR ''7''
+ else if n = 8 then CHR ''8''
+ else if n = 9 then CHR ''9''
+ else CHR ''X'')"
+
+lemma digit_to_char_simps [simp]:
+ "digit_to_char 0 = CHR ''0''"
+ "digit_to_char (Suc 0) = CHR ''1''"
+ "digit_to_char 2 = CHR ''2''"
+ "digit_to_char 3 = CHR ''3''"
+ "digit_to_char 4 = CHR ''4''"
+ "digit_to_char 5 = CHR ''5''"
+ "digit_to_char 6 = CHR ''6''"
+ "digit_to_char 7 = CHR ''7''"
+ "digit_to_char 8 = CHR ''8''"
+ "digit_to_char 9 = CHR ''9''"
+ "n > 9 \<Longrightarrow> digit_to_char n = CHR ''X''"
+unfolding digit_to_char_def
+by simp_all
+
+definition char_to_digit :: "char \<Rightarrow> nat" where
+ "char_to_digit c = (
+ if c = CHR ''0'' then 0
+ else if c = CHR ''1'' then 1
+ else if c = CHR ''2'' then 2
+ else if c = CHR ''3'' then 3
+ else if c = CHR ''4'' then 4
+ else if c = CHR ''5'' then 5
+ else if c = CHR ''6'' then 6
+ else if c = CHR ''7'' then 7
+ else if c = CHR ''8'' then 8
+ else if c = CHR ''9'' then 9
+ else 10)"
+
+lemma char_to_digit_simps [simp]:
+ "char_to_digit (CHR ''0'') = 0"
+ "char_to_digit (CHR ''1'') = 1"
+ "char_to_digit (CHR ''2'') = 2"
+ "char_to_digit (CHR ''3'') = 3"
+ "char_to_digit (CHR ''4'') = 4"
+ "char_to_digit (CHR ''5'') = 5"
+ "char_to_digit (CHR ''6'') = 6"
+ "char_to_digit (CHR ''7'') = 7"
+ "char_to_digit (CHR ''8'') = 8"
+ "char_to_digit (CHR ''9'') = 9"
+unfolding char_to_digit_def by simp_all
+
+
+lemma diget_to_char_inv[simp]:
+assumes is_digit: "is_digit n"
+shows "char_to_digit (digit_to_char n) = n"
+using is_digit unfolding is_digit_expand by auto
+
+lemma char_to_diget_inv[simp]:
+assumes is_digit: "is_digit_char c"
+shows "digit_to_char (char_to_digit c) = c"
+using is_digit
+unfolding char_to_digit_def is_digit_char_def
+by auto
+
+lemma char_to_digit_div_mod [simp]:
+assumes is_digit: "is_digit_char c"
+shows "char_to_digit c < 10"
+using is_digit
+unfolding char_to_digit_def is_digit_char_def
+by auto
+
+
+lemma is_digit_char_intro[simp]:
+ "is_digit (char_to_digit c) = is_digit_char c"
+unfolding char_to_digit_def is_digit_char_def is_digit_expand
+by auto
+
+lemma is_digit_intro[simp]:
+ "is_digit_char (digit_to_char n) = is_digit n"
+unfolding digit_to_char_def is_digit_char_def is_digit_expand
+by auto
+
+lemma digit_to_char_11:
+"digit_to_char n1 = digit_to_char n2 \<Longrightarrow>
+ (is_digit n1 = is_digit n2) \<and> (is_digit n1 \<longrightarrow> (n1 = n2))"
+by (metis diget_to_char_inv is_digit_intro)
+
+lemma char_to_digit_11:
+"char_to_digit c1 = char_to_digit c2 \<Longrightarrow>
+ (is_digit_char c1 = is_digit_char c2) \<and> (is_digit_char c1 \<longrightarrow> (c1 = c2))"
+by (metis char_to_diget_inv is_digit_char_intro)
+
+function nat_to_string :: "nat \<Rightarrow> string" where
+ "nat_to_string n =
+ (if (is_digit n) then [digit_to_char n] else
+ nat_to_string (n div 10) @ [digit_to_char (n mod 10)])"
+by auto
+termination
+ by (relation "measure id") (auto simp add: is_digit_def)
+
+definition int_to_string :: "int \<Rightarrow> string" where
+ "int_to_string i \<equiv>
+ if i < 0 then
+ ''-'' @ nat_to_string (nat (abs i))
+ else
+ nat_to_string (nat i)"
+
+lemma nat_to_string_simps[simp]:
+ "is_digit n \<Longrightarrow> nat_to_string n = [digit_to_char n]"
+ "\<not>(is_digit n) \<Longrightarrow> nat_to_string n = nat_to_string (n div 10) @ [digit_to_char (n mod 10)]"
+by simp_all
+declare nat_to_string.simps[simp del]
+
+lemma nat_to_string_neq_nil[simp]:
+ "nat_to_string n \<noteq> []"
+ by (cases "is_digit n") simp_all
+
+lemmas nat_to_string_neq_nil2[simp] = nat_to_string_neq_nil[symmetric]
+
+lemma nat_to_string_char_to_digit [simp]:
+ "is_digit_char c \<Longrightarrow> nat_to_string (char_to_digit c) = [c]"
+by auto
+
+lemma nat_to_string_11[simp] :
+ "(nat_to_string n1 = nat_to_string n2) \<longleftrightarrow> n1 = n2"
+proof (rule iffI)
+ assume "n1 = n2"
+ thus "nat_to_string n1 = nat_to_string n2" by simp
+next
+ assume "nat_to_string n1 = nat_to_string n2"
+ thus "n1 = n2"
+ proof (induct n2 arbitrary: n1 rule: less_induct)
+ case (less n2')
+ note ind_hyp = this(1)
+ note n2s_eq = less(2)
+
+ have is_dig_eq: "is_digit n2' = is_digit n1" using n2s_eq
+ apply (cases "is_digit n2'")
+ apply (case_tac [!] "is_digit n1")
+ apply (simp_all)
+ done
+
+ show ?case
+ proof (cases "is_digit n2'")
+ case True with n2s_eq is_dig_eq show ?thesis by simp (metis digit_to_char_11)
+ next
+ case False
+ with is_dig_eq have not_digs : "\<not> (is_digit n1)" "\<not> (is_digit n2')" by simp_all
+
+ from not_digs(2) have "n2' div 10 < n2'" unfolding is_digit_def by auto
+ note ind_hyp' = ind_hyp [OF this, of "n1 div 10"]
+
+ from not_digs n2s_eq ind_hyp' digit_to_char_11[of "n1 mod 10" "n2' mod 10"]
+ have "(n1 mod 10) = (n2' mod 10)" "n1 div 10 = n2' div 10" by simp_all
+ thus "n1 = n2'" by (metis div_mult_mod_eq)
+ qed
+ qed
+qed
+
+definition "is_nat_string s \<equiv> (\<forall>c\<in>set s. is_digit_char c)"
+definition "is_strong_nat_string s \<equiv> is_nat_string s \<and> (s \<noteq> []) \<and> (hd s = CHR ''0'' \<longrightarrow> length s = 1)"
+
+lemma is_nat_string_simps[simp]:
+ "is_nat_string []"
+ "is_nat_string (c # s) \<longleftrightarrow> is_digit_char c \<and> is_nat_string s"
+unfolding is_nat_string_def by simp_all
+
+lemma is_strong_nat_string_simps[simp]:
+ "\<not>(is_strong_nat_string [])"
+ "is_strong_nat_string (c # s) \<longleftrightarrow> is_digit_char c \<and> is_nat_string s \<and>
+ (c = CHR ''0'' \<longrightarrow> s = [])"
+unfolding is_strong_nat_string_def by simp_all
+
+fun string_to_nat_aux :: "nat \<Rightarrow> string \<Rightarrow> nat" where
+ "string_to_nat_aux n [] = n"
+ | "string_to_nat_aux n (d#ds) =
+ string_to_nat_aux (n*10 + char_to_digit d) ds"
+
+definition string_to_nat :: "string \<Rightarrow> nat option" where
+ "string_to_nat s \<equiv>
+ (if is_nat_string s then Some (string_to_nat_aux 0 s) else None)"
+
+definition string_to_nat' :: "string \<Rightarrow> nat" where
+ "string_to_nat' s \<equiv> the (string_to_nat s)"
+
+lemma string_to_nat_aux_inv :
+assumes "is_nat_string s"
+assumes "n > 0 \<or> is_strong_nat_string s"
+shows "nat_to_string (string_to_nat_aux n s) =
+(if n = 0 then '''' else nat_to_string n) @ s"
+using assms
+proof (induct s arbitrary: n)
+ case Nil
+ thus ?case
+ by (simp add: is_strong_nat_string_def)
+next
+ case (Cons c s n)
+ from Cons(2) have "is_digit_char c" "is_nat_string s" by simp_all
+ note cs_ok = Cons(3)
+ let ?m = "n*10 + char_to_digit c"
+ note ind_hyp = Cons(1)[OF \<open>is_nat_string s\<close>, of ?m]
+
+ from \<open>is_digit_char c\<close> have m_div: "?m div 10 = n" and
+ m_mod: "?m mod 10 = char_to_digit c"
+ unfolding is_digit_char_def
+ by auto
+
+ show ?case
+ proof (cases "?m = 0")
+ case True
+ with \<open>is_digit_char c\<close>
+ have "n = 0" "c = CHR ''0''" unfolding is_digit_char_def by auto
+ moreover with cs_ok have "s = []" by simp
+ ultimately show ?thesis by simp
+ next
+ case False note m_neq_0 = this
+ with ind_hyp have ind_hyp':
+ "nat_to_string (string_to_nat_aux ?m s) = (nat_to_string ?m) @ s" by auto
+
+ hence "nat_to_string (string_to_nat_aux n (c # s)) = (nat_to_string ?m) @ s"
+ by simp
+
+ with \<open>is_digit_char c\<close> m_div show ?thesis by simp
+ qed
+qed
+
+lemma string_to_nat_inv :
+assumes strong_nat_s: "is_strong_nat_string s"
+assumes s2n_s: "string_to_nat s = Some n"
+shows "nat_to_string n = s"
+proof -
+ from strong_nat_s have nat_s: "is_nat_string s" unfolding is_strong_nat_string_def by simp
+ with s2n_s have n_eq: "n = string_to_nat_aux 0 s" unfolding string_to_nat_def by simp
+
+ from string_to_nat_aux_inv[of s 0, folded n_eq] nat_s strong_nat_s
+ show ?thesis by simp
+qed
+
+lemma nat_to_string_induct [case_names "digit" "non_digit"]:
+assumes digit: "\<And>d. is_digit d \<Longrightarrow> P d"
+assumes not_digit: "\<And>n. \<not>(is_digit n) \<Longrightarrow> P (n div 10) \<Longrightarrow> P (n mod 10) \<Longrightarrow> P n"
+shows "P n"
+proof (induct n rule: less_induct)
+ case (less n)
+ note ind_hyp = this
+
+ show ?case
+ proof (cases "is_digit n")
+ case True with digit show ?thesis by simp
+ next
+ case False note not_dig = this
+ hence "n div 10 < n" "n mod 10 < n" unfolding is_digit_def by auto
+ with not_dig ind_hyp not_digit show ?thesis by simp
+ qed
+qed
+
+lemma nat_to_string___is_nat_string [simp]:
+ "is_nat_string (nat_to_string n)"
+unfolding is_nat_string_def
+proof (induct n rule: nat_to_string_induct)
+ case (digit d)
+ thus ?case by simp
+next
+ case (non_digit n)
+ thus ?case by simp
+qed
+
+lemma nat_to_string___eq_0 [simp]:
+ "(nat_to_string n = (CHR ''0'')#s) \<longleftrightarrow> (n = 0 \<and> s = [])"
+unfolding is_nat_string_def
+proof (induct n arbitrary: s rule: nat_to_string_induct)
+ case (digit d) thus ?case unfolding is_digit_expand by auto
+next
+ case (non_digit n)
+
+ obtain c s' where ns_eq: "nat_to_string (n div 10) = c # s'"
+ by (cases "nat_to_string (n div 10)") auto
+
+ from non_digit(1) have "n div 10 \<noteq> 0" unfolding is_digit_def by auto
+ with non_digit(2) ns_eq have c_neq: "c \<noteq> CHR ''0''" by auto
+
+ from \<open>\<not> (is_digit n)\<close> c_neq ns_eq
+ show ?case by auto
+qed
+
+lemma nat_to_string___is_strong_nat_string:
+ "is_strong_nat_string (nat_to_string n)"
+proof (cases "is_digit n")
+ case True thus ?thesis by simp
+next
+ case False note not_digit = this
+
+ obtain c s' where ns_eq: "nat_to_string n = c # s'"
+ by (cases "nat_to_string n") auto
+
+ from not_digit have "0 < n" unfolding is_digit_def by simp
+ with ns_eq have c_neq: "c \<noteq> CHR ''0''" by auto
+ hence "hd (nat_to_string n) \<noteq> CHR ''0''" unfolding ns_eq by simp
+
+ thus ?thesis unfolding is_strong_nat_string_def
+ by simp
+qed
+
+lemma nat_to_string_inv :
+ "string_to_nat (nat_to_string n) = Some n"
+by (metis nat_to_string_11
+ nat_to_string___is_nat_string
+ nat_to_string___is_strong_nat_string
+ string_to_nat_def
+ string_to_nat_inv)
+
+definition The_opt where
+ "The_opt p = (if (\<exists>!x. p x) then Some (The p) else None)"
+
+lemma The_opt_eq_some [simp] :
+"((The_opt p) = (Some x)) \<longleftrightarrow> ((p x) \<and> ((\<forall> y. p y \<longrightarrow> (x = y))))"
+ (is "?lhs = ?rhs")
+proof (cases "\<exists>!x. p x")
+ case True
+ note exists_unique = this
+ then obtain x where p_x: "p x" by auto
+
+ from the1_equality[of p x] exists_unique p_x
+ have the_opt_eq: "The_opt p = Some x"
+ unfolding The_opt_def by simp
+
+ from exists_unique the_opt_eq p_x show ?thesis
+ by auto
+next
+ case False
+ note not_unique = this
+
+ hence "The_opt p = None"
+ unfolding The_opt_def by simp
+ with not_unique show ?thesis by auto
+qed
+
+lemma The_opt_eq_none [simp] :
+"((The_opt p) = None) \<longleftrightarrow> \<not>(\<exists>!x. p x)"
+unfolding The_opt_def by auto
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_assert_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_assert_extra.thy
new file mode 100644
index 0000000..dc744ac
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_assert_extra.thy
@@ -0,0 +1,45 @@
+chapter \<open>Generated by Lem from \<open>assert_extra.lem\<close>.\<close>
+
+theory "Lem_assert_extra"
+
+imports
+ Main
+ "Lem"
+
+begin
+
+
+\<comment> \<open>\<open>open import {ocaml} `Xstring`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `stringTheory` `lemTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `$LIB_DIR/Lem`\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+\<comment> \<open>\<open> failing with a proper error message \<close>\<close>
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val failwith: forall 'a. string -> 'a\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+\<comment> \<open>\<open> failing without an error message \<close>\<close>
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val fail : forall 'a. 'a\<close>\<close>
+definition fail :: " 'a " where
+ " fail = ( failwith (''fail''))"
+
+
+\<comment> \<open>\<open> ------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> assertions \<close>\<close>
+\<comment> \<open>\<open> ------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val ensure : bool -> string -> unit\<close>\<close>
+definition ensure :: " bool \<Rightarrow> string \<Rightarrow> unit " where
+ " ensure test msg = (
+ if test then
+ ()
+ else
+ failwith msg )"
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_basic_classes.thy b/prover_snapshots/isabelle/lib/lem/Lem_basic_classes.thy
new file mode 100644
index 0000000..488006f
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_basic_classes.thy
@@ -0,0 +1,501 @@
+chapter \<open>Generated by Lem from \<open>basic_classes.lem\<close>.\<close>
+
+theory "Lem_basic_classes"
+
+imports
+ Main
+ "Lem_bool"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> Basic Type Classes \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>open import Bool\<close>\<close>
+
+\<comment> \<open>\<open>open import {coq} `Coq.Strings.Ascii`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `ternaryComparisonsTheory`\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Equality \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> Lem`s default equality (=) is defined by the following type-class Eq.
+ This typeclass should define equality on an abstract datatype 'a. It should
+ always coincide with the default equality of Coq, HOL and Isabelle.
+ For OCaml, it might be different, since abstract datatypes like sets
+ might have fancy equalities. \<close>\<close>
+
+\<comment> \<open>\<open>class ( Eq 'a )
+ val = [isEqual] : 'a -> 'a -> bool
+ val <> [isInequal] : 'a -> 'a -> bool
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> (=) should for all instances be an equivalence relation
+ The isEquivalence predicate of relations could be used here.
+ However, this would lead to a cyclic dependency. \<close>\<close>
+
+\<comment> \<open>\<open> TODO: add later, once lemmata can be assigned to classes
+lemma eq_equiv: ((forall x. (x = x)) &&
+ (forall x y. (x = y) <-> (y = x)) &&
+ (forall x y z. ((x = y) && (y = z)) --> (x = z)))
+\<close>\<close>
+
+\<comment> \<open>\<open> Structural equality \<close>\<close>
+
+\<comment> \<open>\<open> Sometimes, it is also handy to be able to use structural equality.
+ This equality is mapped to the build-in equality of backends. This equality
+ differs significantly for each backend. For example, OCaml can`t check equality
+ of function types, whereas HOL can. When using structural equality, one should
+ know what one is doing. The only guarentee is that is behaves like
+ the native backend equality.
+
+ A lengthy name for structural equality is used to discourage its direct use.
+ It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions
+ for equality \<close>\<close>
+\<comment> \<open>\<open>val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let unsafe_structural_inequality x y= not (unsafe_structural_equality x y)\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Orderings \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> The type-class Ord represents total orders (also called linear orders) \<close>\<close>
+datatype ordering = LT | EQ | GT
+
+fun orderingIsLess :: " ordering \<Rightarrow> bool " where
+ " orderingIsLess LT = ( True )"
+|" orderingIsLess _ = ( False )"
+
+fun orderingIsGreater :: " ordering \<Rightarrow> bool " where
+ " orderingIsGreater GT = ( True )"
+|" orderingIsGreater _ = ( False )"
+
+fun orderingIsEqual :: " ordering \<Rightarrow> bool " where
+ " orderingIsEqual EQ = ( True )"
+|" orderingIsEqual _ = ( False )"
+
+
+definition ordering_cases :: " ordering \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where
+ " ordering_cases r lt eq gt = (
+ if orderingIsLess r then lt else
+ if orderingIsEqual r then eq else gt )"
+
+
+
+\<comment> \<open>\<open>val orderingEqual : ordering -> ordering -> bool\<close>\<close>
+
+record 'a Ord_class=
+
+ compare_method ::" 'a \<Rightarrow> 'a \<Rightarrow> ordering "
+
+ isLess_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool "
+
+ isLessEqual_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool "
+
+ isGreater_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool "
+
+ isGreaterEqual_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool "
+
+
+
+
+\<comment> \<open>\<open> Ocaml provides default, polymorphic compare functions. Let's use them
+ as the default. However, because used perhaps in a typeclass they must be
+ defined for all targets. So, explicitly declare them as undefined for
+ all other targets. If explictly declare undefined, the type-checker won't complain and
+ an error will only be raised when trying to actually output the function for a certain
+ target. \<close>\<close>
+\<comment> \<open>\<open>val defaultCompare : forall 'a. 'a -> 'a -> ordering\<close>\<close>
+\<comment> \<open>\<open>val defaultLess : forall 'a. 'a -> 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val defaultLessEq : forall 'a. 'a -> 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val defaultGreater : forall 'a. 'a -> 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val defaultGreaterEq : forall 'a. 'a -> 'a -> bool\<close>\<close>
+
+
+definition genericCompare :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where
+ " genericCompare (less1:: 'a \<Rightarrow> 'a \<Rightarrow> bool) (equal:: 'a \<Rightarrow> 'a \<Rightarrow> bool) (x :: 'a) (y :: 'a) = (
+ if less1 x y then
+ LT
+ else if equal x y then
+ EQ
+ else
+ GT )"
+
+
+
+\<comment> \<open>\<open>
+\<open> compare should really be a total order \<close>
+lemma ord_OK_1: (
+ (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) &&
+ (forall x y. (compare x y = LT) <-> (compare y x = GT)))
+
+lemma ord_OK_2: (
+ (forall x y z. (x <= y) && (y <= z) --> (x <= z)) &&
+ (forall x y. (x <= y) || (y <= x))
+)
+\<close>\<close>
+
+\<comment> \<open>\<open> let's derive a compare function from the Ord type-class \<close>\<close>
+\<comment> \<open>\<open>val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering\<close>\<close>
+definition ordCompare :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where
+ " ordCompare dict_Basic_classes_Ord_a x y = (
+ if ((isLess_method dict_Basic_classes_Ord_a) x y) then LT else
+ if (x = y) then EQ else GT )"
+
+
+record 'a OrdMaxMin_class=
+
+ max_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+ min_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+\<comment> \<open>\<open>val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a\<close>\<close>
+
+\<comment> \<open>\<open>val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a\<close>\<close>
+
+\<comment> \<open>\<open>val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a\<close>\<close>
+
+\<comment> \<open>\<open>val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_var_dict :: " 'a Ord_class \<Rightarrow> 'a OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_var_dict dict_Basic_classes_Ord_a = ((|
+
+ max_method = ((\<lambda> x y. if (
+ (isLessEqual_method dict_Basic_classes_Ord_a) y x) then x else y)),
+
+ min_method = ((\<lambda> x y. if (
+ (isLessEqual_method dict_Basic_classes_Ord_a) x y) then x else y))|) )"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> SetTypes \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> Set implementations use often an order on the elements. This allows the OCaml implementation
+ to use trees for implementing them. At least, one needs to be able to check equality on sets.
+ One could use the Ord type-class for sets. However, defining a special typeclass is cleaner
+ and allows more flexibility. One can make e.g. sure, that this type-class is ignored for
+ backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate
+ the functions "<", "<=" ... \<close>\<close>
+
+\<comment> \<open>\<open>class ( SetType 'a )
+ val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering
+end\<close>\<close>
+
+fun boolCompare :: " bool \<Rightarrow> bool \<Rightarrow> ordering " where
+ " boolCompare True True = ( EQ )"
+|" boolCompare True False = ( GT )"
+|" boolCompare False True = ( LT )"
+|" boolCompare False False = ( EQ )"
+
+
+\<comment> \<open>\<open> strings \<close>\<close>
+
+\<comment> \<open>\<open>val charEqual : char -> char -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val stringEquality : string -> string -> bool\<close>\<close>
+
+\<comment> \<open>\<open> pairs \<close>\<close>
+
+\<comment> \<open>\<open>val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool\<close>\<close>
+\<comment> \<open>\<open>let pairEqual (a1, b1) (a2, b2)= (a1 = a2) && (b1 = b2)\<close>\<close>
+
+\<comment> \<open>\<open>val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering\<close>\<close>
+fun pairCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> ordering " where
+ " pairCompare cmpa cmpb (a1, b1) (a2, b2) = (
+ (case cmpa a1 a2 of
+ LT => LT
+ | GT => GT
+ | EQ => cmpb b1 b2
+ ))"
+
+
+fun pairLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'b*'a \<Rightarrow> 'b*'a \<Rightarrow> bool " where
+ " pairLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( (
+ (isLess_method dict_Basic_classes_Ord_b) x1 y1) \<or> (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \<and> ((isLess_method dict_Basic_classes_Ord_a) x2 y2)))"
+
+fun pairLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'b*'a \<Rightarrow> 'b*'a \<Rightarrow> bool " where
+ " pairLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( (
+ (isLess_method dict_Basic_classes_Ord_b) x1 y1) \<or> (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \<and> ((isLessEqual_method dict_Basic_classes_Ord_a) x2 y2)))"
+
+
+definition pairGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> bool " where
+ " pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLess
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )"
+
+definition pairGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> bool " where
+ " pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLessEq
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )"
+
+
+definition instance_Basic_classes_Ord_tup2_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow>('a*'b)Ord_class " where
+ " instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b = ((|
+
+ compare_method = (pairCompare
+ (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b)),
+
+ isLess_method =
+ (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a),
+
+ isLessEqual_method =
+ (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a),
+
+ isGreater_method =
+ (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b),
+
+ isGreaterEqual_method =
+ (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b) |) )"
+
+
+
+\<comment> \<open>\<open> triples \<close>\<close>
+
+\<comment> \<open>\<open>val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool\<close>\<close>
+\<comment> \<open>\<open>let tripleEqual (x1, x2, x3) (y1, y2, y3)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))\<close>\<close>
+
+\<comment> \<open>\<open>val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering\<close>\<close>
+fun tripleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> ordering " where
+ " tripleCompare cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2) = (
+ pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2)))"
+
+
+fun tripleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> bool " where
+ " tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))"
+
+fun tripleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> bool " where
+ " tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))"
+
+
+definition tripleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'c*'b*'a \<Rightarrow> 'c*'b*'a \<Rightarrow> bool " where
+ " tripleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLess
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )"
+
+definition tripleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'c*'b*'a \<Rightarrow> 'c*'b*'a \<Rightarrow> bool " where
+ " tripleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLessEq
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )"
+
+
+definition instance_Basic_classes_Ord_tup3_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow>('a*'b*'c)Ord_class " where
+ " instance_Basic_classes_Ord_tup3_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c = ((|
+
+ compare_method = (tripleCompare
+ (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c)),
+
+ isLess_method =
+ (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c),
+
+ isLessEqual_method =
+ (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c),
+
+ isGreater_method =
+ (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a),
+
+ isGreaterEqual_method =
+ (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a) |) )"
+
+
+\<comment> \<open>\<open> quadruples \<close>\<close>
+
+\<comment> \<open>\<open>val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool\<close>\<close>
+\<comment> \<open>\<open>let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))\<close>\<close>
+
+\<comment> \<open>\<open>val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering\<close>\<close>
+fun quadrupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> ordering " where
+ " quadrupleCompare cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2) = (
+ pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2))))"
+
+
+fun quadrupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> bool " where
+ " quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))"
+
+fun quadrupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> bool " where
+ " quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))"
+
+
+definition quadrupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> bool " where
+ " quadrupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLess
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )"
+
+definition quadrupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> bool " where
+ " quadrupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLessEq
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )"
+
+
+definition instance_Basic_classes_Ord_tup4_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow>('a*'b*'c*'d)Ord_class " where
+ " instance_Basic_classes_Ord_tup4_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d = ((|
+
+ compare_method = (quadrupleCompare
+ (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d)),
+
+ isLess_method =
+ (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d),
+
+ isLessEqual_method =
+ (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d),
+
+ isGreater_method =
+ (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a),
+
+ isGreaterEqual_method =
+ (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )"
+
+
+\<comment> \<open>\<open> quintuples \<close>\<close>
+
+\<comment> \<open>\<open>val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool\<close>\<close>
+\<comment> \<open>\<open>let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))\<close>\<close>
+
+\<comment> \<open>\<open>val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering\<close>\<close>
+fun quintupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow>('e \<Rightarrow> 'e \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> ordering " where
+ " quintupleCompare cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2) = (
+ pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2)))))"
+
+
+fun quintupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> bool " where
+ " quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))"
+
+fun quintupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> bool " where
+ " quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))"
+
+
+definition quintupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> bool " where
+ " quintupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLess
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )"
+
+definition quintupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> bool " where
+ " quintupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLessEq
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )"
+
+
+definition instance_Basic_classes_Ord_tup5_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow>('a*'b*'c*'d*'e)Ord_class " where
+ " instance_Basic_classes_Ord_tup5_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e = ((|
+
+ compare_method = (quintupleCompare
+ (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e)),
+
+ isLess_method =
+ (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e),
+
+ isLessEqual_method =
+ (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e),
+
+ isGreater_method =
+ (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a),
+
+ isGreaterEqual_method =
+ (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_a) |) )"
+
+
+\<comment> \<open>\<open> sextuples \<close>\<close>
+
+\<comment> \<open>\<open>val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool\<close>\<close>
+\<comment> \<open>\<open>let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))\<close>\<close>
+
+\<comment> \<open>\<open>val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+ ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) ->
+ ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering\<close>\<close>
+fun sextupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow>('e \<Rightarrow> 'e \<Rightarrow> ordering)\<Rightarrow>('f \<Rightarrow> 'f \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> ordering " where
+ " sextupleCompare cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2) = (
+ pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2))))))"
+
+
+fun sextupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> bool " where
+ " sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLess
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))"
+
+fun sextupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> bool " where
+ " sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLessEq
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+ (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))"
+
+
+definition sextupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> bool " where
+ " sextupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLess
+ dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )"
+
+definition sextupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> bool " where
+ " sextupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLessEq
+ dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )"
+
+
+definition instance_Basic_classes_Ord_tup6_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow>('a*'b*'c*'d*'e*'f)Ord_class " where
+ " instance_Basic_classes_Ord_tup6_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f = ((|
+
+ compare_method = (sextupleCompare
+ (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e) (compare_method dict_Basic_classes_Ord_f)),
+
+ isLess_method =
+ (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f),
+
+ isLessEqual_method =
+ (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+ dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+ dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f),
+
+ isGreater_method =
+ (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a),
+
+ isGreaterEqual_method =
+ (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+ dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+ dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_bool.thy b/prover_snapshots/isabelle/lib/lem/Lem_bool.thy
new file mode 100644
index 0000000..942342c
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_bool.thy
@@ -0,0 +1,75 @@
+chapter \<open>Generated by Lem from \<open>bool.lem\<close>.\<close>
+
+theory "Lem_bool"
+
+imports
+ Main
+
+begin
+
+
+
+\<comment> \<open>\<open> The type bool is hard-coded, so are true and false \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> not \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val not : bool -> bool\<close>\<close>
+\<comment> \<open>\<open>let not b= match b with
+ | true -> false
+ | false -> true
+end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> and \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val && [and] : bool -> bool -> bool\<close>\<close>
+\<comment> \<open>\<open>let && b1 b2= match (b1, b2) with
+ | (true, true) -> true
+ | _ -> false
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> or \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val || [or] : bool -> bool -> bool\<close>\<close>
+\<comment> \<open>\<open>let || b1 b2= match (b1, b2) with
+ | (false, false) -> false
+ | _ -> true
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> implication \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val --> [imp] : bool -> bool -> bool\<close>\<close>
+\<comment> \<open>\<open>let --> b1 b2= match (b1, b2) with
+ | (true, false) -> false
+ | _ -> true
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> equivalence \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val <-> [equiv] : bool -> bool -> bool\<close>\<close>
+\<comment> \<open>\<open>let <-> b1 b2= match (b1, b2) with
+ | (true, true) -> true
+ | (false, false) -> true
+ | _ -> false
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> xor \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val xor : bool -> bool -> bool\<close>\<close>
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_either.thy b/prover_snapshots/isabelle/lib/lem/Lem_either.thy
new file mode 100644
index 0000000..17bfe1a
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_either.thy
@@ -0,0 +1,85 @@
+chapter \<open>Generated by Lem from \<open>either.lem\<close>.\<close>
+
+theory "Lem_either"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_list"
+ "Lem_tuple"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes List Tuple\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `sumTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {ocaml} `Either`\<close>\<close>
+
+\<comment> \<open>\<open>type either 'a 'b
+ = Left of 'a
+ | Right of 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Equality. \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool\<close>\<close>
+\<comment> \<open>\<open>val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool\<close>\<close>
+
+definition eitherEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> bool)\<Rightarrow>('a,'b)sum \<Rightarrow>('a,'b)sum \<Rightarrow> bool " where
+ " eitherEqualBy eql eqr (left:: ('a, 'b) sum) (right:: ('a, 'b) sum) = (
+ (case (left, right) of
+ (Inl l, Inl l') => eql l l'
+ | (Inr r, Inr r') => eqr r r'
+ | _ => False
+ ))"
+
+\<comment> \<open>\<open>let eitherEqual= eitherEqualBy (=) (=)\<close>\<close>
+
+fun either_setElemCompare :: "('d \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('d,'c)sum \<Rightarrow>('b,'a)sum \<Rightarrow> ordering " where
+ " either_setElemCompare cmpa cmpb (Inl x') (Inl y') = ( cmpa x' y' )"
+|" either_setElemCompare cmpa cmpb (Inr x') (Inr y') = ( cmpb x' y' )"
+|" either_setElemCompare cmpa cmpb (Inl _) (Inr _) = ( LT )"
+|" either_setElemCompare cmpa cmpb (Inr _) (Inl _) = ( GT )"
+
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Utility functions. \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isLeft : forall 'a 'b. either 'a 'b -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val isRight : forall 'a 'b. either 'a 'b -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open>val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c\<close>\<close>
+\<comment> \<open>\<open>let either fa fb x= match x with
+ | Left a -> fa a
+ | Right b -> fb b
+end\<close>\<close>
+
+
+\<comment> \<open>\<open>val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)\<close>\<close>
+\<comment> \<open>\<open>let rec partitionEither l= match l with
+ | [] -> ([], [])
+ | x :: xs -> begin
+ let (ll, rl) = partitionEither xs in
+ match x with
+ | Left l -> (l::ll, rl)
+ | Right r -> (ll, r::rl)
+ end
+ end
+end\<close>\<close>
+
+
+\<comment> \<open>\<open>val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a\<close>\<close>
+
+
+\<comment> \<open>\<open>val rights : forall 'a 'b. list (either 'a 'b) -> list 'b\<close>\<close>
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_function.thy b/prover_snapshots/isabelle/lib/lem/Lem_function.thy
new file mode 100644
index 0000000..f9b93dd
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_function.thy
@@ -0,0 +1,72 @@
+chapter \<open>Generated by Lem from \<open>function.lem\<close>.\<close>
+
+theory "Lem_function"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> A library for common operations on functions \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>open import Bool Basic_classes\<close>\<close>
+
+\<comment> \<open>\<open>open import {coq} `Program.Basics`\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> identity function \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val id : forall 'a. 'a -> 'a\<close>\<close>
+\<comment> \<open>\<open>let id x= x\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> constant function \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val const : forall 'a 'b. 'a -> 'b -> 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> function composition \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)\<close>\<close>
+\<comment> \<open>\<open>let comb f g= (fun x -> f (g x))\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> function application \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)\<close>\<close>
+\<comment> \<open>\<open>let $ f= (fun x -> f x)\<close>\<close>
+
+\<comment> \<open>\<open>val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b\<close>\<close>
+\<comment> \<open>\<open>let $> x f= f x\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> flipping argument order \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)\<close>\<close>
+\<comment> \<open>\<open>let flip f= (fun x y -> f y x)\<close>\<close>
+
+
+\<comment> \<open>\<open> currying / uncurrying \<close>\<close>
+
+\<comment> \<open>\<open>val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c\<close>\<close>
+definition curry :: "('a*'b \<Rightarrow> 'c)\<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow> 'c " where
+ " curry f = ( (\<lambda> a b . f (a, b)))"
+
+
+\<comment> \<open>\<open>val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)\<close>\<close>
+fun uncurry :: "('a \<Rightarrow> 'b \<Rightarrow> 'c)\<Rightarrow> 'a*'b \<Rightarrow> 'c " where
+ " uncurry f (a,b) = ( f a b )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_function_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_function_extra.thy
new file mode 100644
index 0000000..f4bb5ff
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_function_extra.thy
@@ -0,0 +1,29 @@
+chapter \<open>Generated by Lem from \<open>function_extra.lem\<close>.\<close>
+
+theory "Lem_function_extra"
+
+imports
+ Main
+ "Lem_maybe"
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_num"
+ "Lem_function"
+ "Lem"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Maybe Bool Basic_classes Num Function\<close>\<close>
+
+\<comment> \<open>\<open>open import {hol} `lemTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `$LIB_DIR/Lem`\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> getting a unique value \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val THE : forall 'a. ('a -> bool) -> maybe 'a\<close>\<close>
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_list.thy b/prover_snapshots/isabelle/lib/lem/Lem_list.thy
new file mode 100644
index 0000000..99f11e0
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_list.thy
@@ -0,0 +1,776 @@
+chapter \<open>Generated by Lem from \<open>list.lem\<close>.\<close>
+
+theory "Lem_list"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_maybe"
+ "Lem_basic_classes"
+ "Lem_function"
+ "Lem_tuple"
+ "Lem_num"
+ "Lem"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Maybe Basic_classes Function Tuple Num\<close>\<close>
+
+\<comment> \<open>\<open>open import {coq} `Coq.Lists.List`\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `$LIB_DIR/Lem`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Basic list functions \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> The type of lists as well as list literals like [], [1;2], ... are hardcoded.
+ Thus, we can directly dive into derived definitions. \<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> cons \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val :: : forall 'a. 'a -> list 'a -> list 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Emptyness check \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val null : forall 'a. list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let null l= match l with [] -> true | _ -> false end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Length \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val length : forall 'a. list 'a -> nat\<close>\<close>
+\<comment> \<open>\<open>let rec length l=
+ match l with
+ | [] -> 0
+ | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1
+ end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Equality \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool\<close>\<close>
+
+fun listEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " listEqualBy eq ([]) ([]) = ( True )"
+|" listEqualBy eq ([]) (_ # _) = ( False )"
+|" listEqualBy eq (_ # _) ([]) = ( False )"
+|" listEqualBy eq (x # xs) (y # ys) = ( (eq x y \<and> listEqualBy eq xs ys))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> compare \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> ordering\<close>\<close>
+\<comment> \<open>\<open>val lexicographicCompareBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a -> ordering\<close>\<close>
+
+fun lexicographicCompareBy :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> ordering " where
+ " lexicographicCompareBy cmp ([]) ([]) = ( EQ )"
+|" lexicographicCompareBy cmp ([]) (_ # _) = ( LT )"
+|" lexicographicCompareBy cmp (_ # _) ([]) = ( GT )"
+|" lexicographicCompareBy cmp (x # xs) (y # ys) = ( (
+ (case cmp x y of
+ LT => LT
+ | GT => GT
+ | EQ => lexicographicCompareBy cmp xs ys
+ )
+ ))"
+
+
+\<comment> \<open>\<open>val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool\<close>\<close>
+fun lexicographicLessBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " lexicographicLessBy less1 less_eq1 ([]) ([]) = ( False )"
+|" lexicographicLessBy less1 less_eq1 ([]) (_ # _) = ( True )"
+|" lexicographicLessBy less1 less_eq1 (_ # _) ([]) = ( False )"
+|" lexicographicLessBy less1 less_eq1 (x # xs) (y # ys) = ( ((less1 x y) \<or> ((less_eq1 x y) \<and> (lexicographicLessBy less1 less_eq1 xs ys))))"
+
+
+\<comment> \<open>\<open>val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool\<close>\<close>
+fun lexicographicLessEqBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " lexicographicLessEqBy less1 less_eq1 ([]) ([]) = ( True )"
+|" lexicographicLessEqBy less1 less_eq1 ([]) (_ # _) = ( True )"
+|" lexicographicLessEqBy less1 less_eq1 (_ # _) ([]) = ( False )"
+|" lexicographicLessEqBy less1 less_eq1 (x # xs) (y # ys) = ( (less1 x y \<or> (less_eq1 x y \<and> lexicographicLessEqBy less1 less_eq1 xs ys)))"
+
+
+
+definition instance_Basic_classes_Ord_list_dict :: " 'a Ord_class \<Rightarrow>('a list)Ord_class " where
+ " instance_Basic_classes_Ord_list_dict dict_Basic_classes_Ord_a = ((|
+
+ compare_method = (lexicographicCompareBy
+ (compare_method dict_Basic_classes_Ord_a)),
+
+ isLess_method = (lexicographicLessBy
+ (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)),
+
+ isLessEqual_method = (lexicographicLessEqBy
+ (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)),
+
+ isGreater_method = (\<lambda> x y. (lexicographicLessBy
+ (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x)),
+
+ isGreaterEqual_method = (\<lambda> x y. (lexicographicLessEqBy
+ (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x))|) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Append \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val ++ : forall 'a. list 'a -> list 'a -> list 'a\<close>\<close> \<comment> \<open>\<open> originally append \<close>\<close>
+\<comment> \<open>\<open>let rec ++ xs ys= match xs with
+ | [] -> ys
+ | x :: xs' -> x :: (xs' ++ ys)
+ end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> snoc \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val snoc : forall 'a. 'a -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let snoc e l= l ++ [e]\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Reverse \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> First lets define the function [reverse_append], which is
+ closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1].
+ This can be implemented more efficienctly than appending and is
+ used to implement reverse. \<close>\<close>
+
+\<comment> \<open>\<open>val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a\<close>\<close> \<comment> \<open>\<open> originally named rev_append \<close>\<close>
+\<comment> \<open>\<open>let rec reverseAppend l1 l2= match l1 with
+ | [] -> l2
+ | x :: xs -> reverseAppend xs (x :: l2)
+ end\<close>\<close>
+
+\<comment> \<open>\<open> Reversing a list \<close>\<close>
+\<comment> \<open>\<open>val reverse : forall 'a. list 'a -> list 'a\<close>\<close> \<comment> \<open>\<open> originally named rev \<close>\<close>
+\<comment> \<open>\<open>let reverse l= reverseAppend l []\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Map \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b\<close>\<close>
+function (sequential,domintros) map_tr :: " 'b list \<Rightarrow>('a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> 'b list " where
+ " map_tr rev_acc f ([]) = ( List.rev rev_acc )"
+|" map_tr rev_acc f (x # xs) = ( map_tr ((f x) # rev_acc) f xs )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open> taken from: https://blogs.janestreet.com/optimizing-list-map/ \<close>\<close>
+\<comment> \<open>\<open>val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b\<close>\<close>
+function (sequential,domintros) count_map :: "('a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> nat \<Rightarrow> 'b list " where
+ " count_map f ([]) ctr = ( [])"
+|" count_map f (hd1 # tl1) ctr = ( f hd1 #
+ (if ctr <( 5000 :: nat) then count_map f tl1 (ctr +( 1 :: nat))
+ else map_tr [] f tl1))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b\<close>\<close>
+\<comment> \<open>\<open>let map f l= count_map f l 0\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Reverse Map \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Folding \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> fold left \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a\<close>\<close> \<comment> \<open>\<open> originally foldl \<close>\<close>
+
+\<comment> \<open>\<open>let rec foldl f b l= match l with
+ | [] -> b
+ | x :: xs -> foldl f (f b x) xs
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> fold right \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b\<close>\<close> \<comment> \<open>\<open> originally foldr with different argument order \<close>\<close>
+\<comment> \<open>\<open>let rec foldr f b l= match l with
+ | [] -> b
+ | x :: xs -> f x (foldr f b xs)
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> concatenating lists \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val concat : forall 'a. list (list 'a) -> list 'a\<close>\<close> \<comment> \<open>\<open> before also called "flatten" \<close>\<close>
+\<comment> \<open>\<open>let concat= foldr (++) []\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------- \<close>\<close>
+\<comment> \<open>\<open> concatenating with mapping \<close>\<close>
+\<comment> \<open>\<open> -------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> universal qualification \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val all : forall 'a. ('a -> bool) -> list 'a -> bool\<close>\<close> \<comment> \<open>\<open> originally for_all \<close>\<close>
+\<comment> \<open>\<open>let all P l= foldl (fun r e -> P e && r) true l\<close>\<close>
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> existential qualification \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val any : forall 'a. ('a -> bool) -> list 'a -> bool\<close>\<close> \<comment> \<open>\<open> originally exist \<close>\<close>
+\<comment> \<open>\<open>let any P l= foldl (fun r e -> P e || r) false l\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> dest_init \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> get the initial part and the last element of the list in a safe way \<close>\<close>
+
+\<comment> \<open>\<open>val dest_init : forall 'a. list 'a -> maybe (list 'a * 'a)\<close>\<close>
+
+fun dest_init_aux :: " 'a list \<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list*'a " where
+ " dest_init_aux rev_init last_elem_seen ([]) = ( (List.rev rev_init, last_elem_seen))"
+|" dest_init_aux rev_init last_elem_seen (x # xs) = ( dest_init_aux (last_elem_seen # rev_init) x xs )"
+
+
+fun dest_init :: " 'a list \<Rightarrow>('a list*'a)option " where
+ " dest_init ([]) = ( None )"
+|" dest_init (x # xs) = ( Some (dest_init_aux [] x xs))"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Indexing lists \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> index / nth with maybe \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val index : forall 'a. list 'a -> nat -> maybe 'a\<close>\<close>
+
+\<comment> \<open>\<open>let rec index l n= match l with
+ | [] -> Nothing
+ | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then Just x else index xs ((Instance_Num_NumMinus_nat.-)n 1)
+end\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> findIndices \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P].
+ Counting starts with 0, the result list is sorted ascendingly \<close>\<close>
+\<comment> \<open>\<open>val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat\<close>\<close>
+
+fun findIndices_aux :: " nat \<Rightarrow>('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow>(nat)list " where
+ " findIndices_aux (i::nat) P ([]) = ( [])"
+|" findIndices_aux (i::nat) P (x # xs) = ( if P x then i # findIndices_aux (i +( 1 :: nat)) P xs else findIndices_aux (i +( 1 :: nat)) P xs )"
+
+\<comment> \<open>\<open>let findIndices P l= findIndices_aux 0 P l\<close>\<close>
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> findIndex \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> findIndex returns the first index of a list that satisfies a given predicate. \<close>\<close>
+\<comment> \<open>\<open>val findIndex : forall 'a. ('a -> bool) -> list 'a -> maybe nat\<close>\<close>
+\<comment> \<open>\<open>let findIndex P l= match findIndices P l with
+ | [] -> Nothing
+ | x :: _ -> Just x
+end\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> elemIndices \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> elemIndex \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> maybe nat\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Creating lists \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> genlist \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] \<close>\<close>
+\<comment> \<open>\<open>val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a\<close>\<close>
+
+
+\<comment> \<open>\<open>let rec genlist f n=
+ match n with
+ | 0 -> []
+ | n' + 1 -> snoc (f n') (genlist f n')
+ end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> replicate \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val replicate : forall 'a. nat -> 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let rec replicate n x=
+ match n with
+ | 0 -> []
+ | n' + 1 -> x :: replicate n' x
+ end\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Sublists \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> splitAt \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> [splitAt n xs] returns a tuple (xs1, xs2), with "append xs1 xs2 = xs" and
+ "length xs1 = n". If there are not enough elements
+ in [xs], the original list and the empty one are returned. \<close>\<close>
+\<comment> \<open>\<open>val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)\<close>\<close>
+function (sequential,domintros) splitAtAcc :: " 'a list \<Rightarrow> nat \<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where
+ " splitAtAcc revAcc n l = (
+ (case l of
+ [] => (List.rev revAcc, [])
+ | x # xs => if n \<le>( 0 :: nat) then (List.rev revAcc, l) else splitAtAcc (x # revAcc) (n-( 1 :: nat)) xs
+ ))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)\<close>\<close>
+\<comment> \<open>\<open>let rec splitAt n l=
+ splitAtAcc [] n l\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> take \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> take n xs returns the prefix of xs of length n, or xs itself if n > length xs \<close>\<close>
+\<comment> \<open>\<open>val take : forall 'a. nat -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let take n l= fst (splitAt n l)\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> drop \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. \<close>\<close>
+\<comment> \<open>\<open>val drop : forall 'a. nat -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let drop n l= snd (splitAt n l)\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+\<comment> \<open>\<open> splitWhile, takeWhile, and dropWhile \<close>\<close>
+\<comment> \<open>\<open> ------------------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)\<close>\<close>
+fun splitWhile_tr :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where
+ " splitWhile_tr p ([]) acc1 = (
+ (List.rev acc1, []))"
+|" splitWhile_tr p (x # xs) acc1 = (
+ if p x then
+ splitWhile_tr p xs (x # acc1)
+ else
+ (List.rev acc1, (x # xs)))"
+
+
+\<comment> \<open>\<open>val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)\<close>\<close>
+definition splitWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where
+ " splitWhile p xs = ( splitWhile_tr p xs [])"
+
+
+\<comment> \<open>\<open> [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. \<close>\<close>
+\<comment> \<open>\<open>val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a\<close>\<close>
+definition takeWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " takeWhile p l = ( fst (splitWhile p l))"
+
+
+\<comment> \<open>\<open> [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. \<close>\<close>
+\<comment> \<open>\<open>val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a\<close>\<close>
+definition dropWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " dropWhile p l = ( snd (splitWhile p l))"
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> isPrefixOf \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool\<close>\<close>
+fun isPrefixOf :: " 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " isPrefixOf ([]) _ = ( True )"
+|" isPrefixOf (_ # _) ([]) = ( False )"
+|" isPrefixOf (x # xs) (y # ys) = ( (x = y) \<and> isPrefixOf xs ys )"
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> update \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val update : forall 'a. list 'a -> nat -> 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let rec update l n e=
+ match l with
+ | [] -> []
+ | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e)
+end\<close>\<close>
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Searching lists \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> Membership test \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> The membership test, one of the basic list functions, is actually tricky for
+ Lem, because it is tricky, which equality to use. From Lem`s point of
+ perspective, we want to use the equality provided by the equality type - class.
+ This allows for example to check whether a set is in a list of sets.
+
+ However, in order to use the equality type class, elem essentially becomes
+ existential quantification over lists. For types, which implement semantic
+ equality (=) with syntactic equality, this is overly complicated. In
+ our theorem prover backend, we would end up with overly complicated, harder
+ to read definitions and some of the automation would be harder to apply.
+ Moreover, nearly all the old Lem generated code would change and require
+ (hopefully minor) adaptions of proofs.
+
+ For now, we ignore this problem and just demand, that all instances of
+ the equality type class do the right thing for the theorem prover backends.
+\<close>\<close>
+
+\<comment> \<open>\<open>val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool\<close>\<close>
+
+definition elemBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " elemBy eq e l = ( ((\<exists> x \<in> (set l). (eq e) x)))"
+
+\<comment> \<open>\<open>let elem= elemBy (=)\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> Find \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val find : forall 'a. ('a -> bool) -> list 'a -> maybe 'a\<close>\<close> \<comment> \<open>\<open> previously not of maybe type \<close>\<close>
+\<comment> \<open>\<open>let rec find P l= match l with
+ | [] -> Nothing
+ | x :: xs -> if P x then Just x else find P xs
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------- \<close>\<close>
+\<comment> \<open>\<open> Lookup in an associative list \<close>\<close>
+\<comment> \<open>\<open> ----------------------------- \<close>\<close>
+\<comment> \<open>\<open>val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> maybe 'b\<close>\<close>
+\<comment> \<open>\<open>val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> maybe 'b\<close>\<close>
+
+\<comment> \<open>\<open> DPM: eta-expansion for Coq backend type-inference. \<close>\<close>
+definition lookupBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow>('a*'b)list \<Rightarrow> 'b option " where
+ " lookupBy eq k m = ( map_option (\<lambda> x . snd x) (List.find ( \<lambda>x .
+ (case x of (k', _) => eq k k' )) m))"
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> filter \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let rec filter P l= match l with
+ | [] -> []
+ | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs
+ end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> partition \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a\<close>\<close>
+\<comment> \<open>\<open>let partition P l= (filter P l, filter (fun x -> not (P x)) l)\<close>\<close>
+
+\<comment> \<open>\<open>val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a\<close>\<close>
+definition reversePartition :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where
+ " reversePartition P l = ( List.partition P (List.rev l))"
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> delete first element \<close>\<close>
+\<comment> \<open>\<open> with certain property \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> maybe (list 'a)\<close>\<close>
+\<comment> \<open>\<open>let rec deleteFirst P l= match l with
+ | [] -> Nothing
+ | x :: xs -> if (P x) then Just xs else Maybe.map (fun xs' -> x :: xs') (deleteFirst P xs)
+ end\<close>\<close>
+
+
+\<comment> \<open>\<open>val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a\<close>\<close>
+
+definition deleteBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " deleteBy eq x l = ( case_option l id (delete_first (eq x) l))"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Zipping and unzipping lists \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> zip \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. \<close>\<close>
+\<comment> \<open>\<open>val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)\<close>\<close> \<comment> \<open>\<open> before combine \<close>\<close>
+\<comment> \<open>\<open>let rec zip l1 l2= match (l1, l2) with
+ | (x :: xs, y :: ys) -> (x, y) :: zip xs ys
+ | _ -> []
+end\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> unzip \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)\<close>\<close>
+\<comment> \<open>\<open>let rec unzip l= match l with
+ | [] -> ([], [])
+ | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys)
+end\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> distinct elements \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val allDistinct : forall 'a. Eq 'a => list 'a -> bool\<close>\<close>
+fun allDistinct :: " 'a list \<Rightarrow> bool " where
+ " allDistinct ([]) = ( True )"
+|" allDistinct (x # l') = ( \<not> (Set.member x (set l')) \<and> allDistinct l' )"
+
+
+\<comment> \<open>\<open> some more useful functions \<close>\<close>
+\<comment> \<open>\<open>val mapMaybe : forall 'a 'b. ('a -> maybe 'b) -> list 'a -> list 'b\<close>\<close>
+function (sequential,domintros) mapMaybe :: "('a \<Rightarrow> 'b option)\<Rightarrow> 'a list \<Rightarrow> 'b list " where
+ " mapMaybe f ([]) = ( [])"
+|" mapMaybe f (x # xs) = (
+ (case f x of
+ None => mapMaybe f xs
+ | Some y => y # (mapMaybe f xs)
+ ))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b\<close>\<close>
+function (sequential,domintros) mapiAux :: "(nat \<Rightarrow> 'b \<Rightarrow> 'a)\<Rightarrow> nat \<Rightarrow> 'b list \<Rightarrow> 'a list " where
+ " mapiAux f (n :: nat) ([]) = ( [])"
+|" mapiAux f (n :: nat) (x # xs) = ( (f n x) # mapiAux f (n +( 1 :: nat)) xs )"
+by pat_completeness auto
+
+definition mapi :: "(nat \<Rightarrow> 'a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> 'b list " where
+ " mapi f l = ( mapiAux f(( 0 :: nat)) l )"
+
+
+\<comment> \<open>\<open>val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a\<close>\<close>
+definition deletes :: " 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " deletes xs ys = (
+ List.foldl ((\<lambda> x y. remove1 y x)) xs ys )"
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Comments (not clean yet, please ignore the rest of the file) \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> skipped from Haskell Lib\<close>\<close>
+\<comment> \<open>\<open> -----------------------
+
+intersperse :: a -> [a] -> [a]
+intercalate :: [a] -> [[a]] -> [a]
+transpose :: [[a]] -> [[a]]
+subsequences :: [a] -> [[a]]
+permutations :: [a] -> [[a]]
+foldl` :: (a -> b -> a) -> a -> [b] -> aSource
+foldl1` :: (a -> a -> a) -> [a] -> aSource
+
+and
+or
+sum
+product
+maximum
+minimum
+scanl
+scanr
+scanl1
+scanr1
+Accumulating maps
+
+mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+
+iterate :: (a -> a) -> a -> [a]
+repeat :: a -> [a]
+cycle :: [a] -> [a]
+unfoldr
+
+
+takeWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source
+span :: (a -> Bool) -> [a] -> ([a], [a])Source
+break :: (a -> Bool) -> [a] -> ([a], [a])Source
+break p is equivalent to span (not . p).
+stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source
+group :: Eq a => [a] -> [[a]]Source
+inits :: [a] -> [[a]]Source
+tails :: [a] -> [[a]]Source
+
+
+isPrefixOf :: Eq a => [a] -> [a] -> BoolSource
+isSuffixOf :: Eq a => [a] -> [a] -> BoolSource
+isInfixOf :: Eq a => [a] -> [a] -> BoolSource
+
+
+
+notElem :: Eq a => a -> [a] -> BoolSource
+
+zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source
+zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source
+zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source
+zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source
+zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source
+
+zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source
+zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source
+zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source
+zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source
+zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source
+zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source
+
+
+unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source
+unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source
+unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source
+unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source
+unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source
+
+
+lines :: String -> [String]Source
+words :: String -> [String]Source
+unlines :: [String] -> StringSource
+unwords :: [String] -> StringSource
+nub :: Eq a => [a] -> [a]Source
+delete :: Eq a => a -> [a] -> [a]Source
+
+(\\) :: Eq a => [a] -> [a] -> [a]Source
+union :: Eq a => [a] -> [a] -> [a]Source
+intersect :: Eq a => [a] -> [a] -> [a]Source
+sort :: Ord a => [a] -> [a]Source
+insert :: Ord a => a -> [a] -> [a]Source
+
+
+nubBy :: (a -> a -> Bool) -> [a] -> [a]Source
+deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source
+deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source
+sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source
+insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source
+maximumBy :: (a -> a -> Ordering) -> [a] -> aSource
+minimumBy :: (a -> a -> Ordering) -> [a] -> aSource
+genericLength :: Num i => [b] -> iSource
+genericTake :: Integral i => i -> [a] -> [a]Source
+genericDrop :: Integral i => i -> [a] -> [a]Source
+genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source
+genericIndex :: Integral a => [b] -> a -> bSource
+genericReplicate :: Integral i => i -> a -> [a]Source
+
+
+\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> skipped from Lem Lib \<close>\<close>
+\<comment> \<open>\<open> -----------------------
+
+
+val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c
+val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c
+val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a
+val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c
+
+
+\<open> now maybe result and called lookup \<close>
+val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b
+let inline {ocaml} assoc = Ocaml.List.assoc
+
+
+val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool
+val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b)
+
+
+
+val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+
+val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a
+val intersect : forall 'a. list 'a -> list 'a -> list 'a
+
+
+\<close>\<close>
+
+\<comment> \<open>\<open>val catMaybes : forall 'a. list (maybe 'a) -> list 'a\<close>\<close>
+function (sequential,domintros) catMaybes :: "('a option)list \<Rightarrow> 'a list " where
+ " catMaybes ([]) = (
+ [])"
+|" catMaybes (None # xs') = (
+ catMaybes xs' )"
+|" catMaybes (Some x # xs') = (
+ x # catMaybes xs' )"
+by pat_completeness auto
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_list_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_list_extra.thy
new file mode 100644
index 0000000..edca436
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_list_extra.thy
@@ -0,0 +1,117 @@
+chapter \<open>Generated by Lem from \<open>list_extra.lem\<close>.\<close>
+
+theory "Lem_list_extra"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_maybe"
+ "Lem_basic_classes"
+ "Lem_tuple"
+ "Lem_num"
+ "Lem_list"
+ "Lem_assert_extra"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Maybe Basic_classes Tuple Num List Assert_extra\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> head of non-empty list \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val head : forall 'a. list 'a -> 'a\<close>\<close>
+\<comment> \<open>\<open>let head l= match l with | x::xs -> x | [] -> failwith "List_extra.head of empty list" end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> tail of non-empty list \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val tail : forall 'a. list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let tail l= match l with | x::xs -> xs | [] -> failwith "List_extra.tail of empty list" end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> last \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val last : forall 'a. list 'a -> 'a\<close>\<close>
+\<comment> \<open>\<open>let rec last l= match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith "List_extra.last of empty list" end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> init \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> All elements of a non-empty list except the last one. \<close>\<close>
+\<comment> \<open>\<open>val init : forall 'a. list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>let rec init l= match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith "List_extra.init of empty list" end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> foldl1 / foldr1 \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> folding functions for non-empty lists,
+ which don`t take the base case \<close>\<close>
+\<comment> \<open>\<open>val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a\<close>\<close>
+fun foldl1 :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a " where
+ " foldl1 f (x # xs) = ( List.foldl f x xs )"
+|" foldl1 f ([]) = ( failwith (''List_extra.foldl1 of empty list''))"
+
+
+\<comment> \<open>\<open>val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a\<close>\<close>
+fun foldr1 :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a " where
+ " foldr1 f (x # xs) = ( List.foldr f xs x )"
+|" foldr1 f ([]) = ( failwith (''List_extra.foldr1 of empty list''))"
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> nth element \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> get the nth element of a list \<close>\<close>
+\<comment> \<open>\<open>val nth : forall 'a. list 'a -> nat -> 'a\<close>\<close>
+\<comment> \<open>\<open>let nth l n= match index l n with Just e -> e | Nothing -> failwith "List_extra.nth" end\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> Find_non_pure \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open>val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a\<close>\<close>
+definition findNonPure :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a " where
+ " findNonPure P l = ( (case (List.find P l) of
+ Some e => e
+ | None => failwith (''List_extra.findNonPure'')
+))"
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> zip same length \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)\<close>\<close>
+fun zipSameLength :: " 'a list \<Rightarrow> 'b list \<Rightarrow>('a*'b)list " where
+ " zipSameLength l1 l2 = ( (case (l1, l2) of
+ (x # xs, y # ys) => (x, y) # zipSameLength xs ys
+ | ([], []) => []
+ | _ => failwith (''List_extra.zipSameLength of different length lists'')
+
+))"
+
+
+\<comment> \<open>\<open>val unfoldr: forall 'a 'b. ('a -> maybe ('b * 'a)) -> 'a -> list 'b\<close>\<close>
+function (sequential,domintros) unfoldr :: "('a \<Rightarrow>('b*'a)option)\<Rightarrow> 'a \<Rightarrow> 'b list " where
+ " unfoldr f x = (
+ (case f x of
+ Some (y, x') =>
+ y # unfoldr f x'
+ | None =>
+ []
+ ))"
+by pat_completeness auto
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_machine_word.thy b/prover_snapshots/isabelle/lib/lem/Lem_machine_word.thy
new file mode 100644
index 0000000..358a739
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_machine_word.thy
@@ -0,0 +1,453 @@
+chapter \<open>Generated by Lem from \<open>machine_word.lem\<close>.\<close>
+
+theory "Lem_machine_word"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_num"
+ "Lem_basic_classes"
+ "Lem_show"
+ "Lem_function"
+ "HOL-Word.Word"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Num Basic_classes Show Function\<close>\<close>
+
+\<comment> \<open>\<open>open import {isabelle} `HOL-Word.Word`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`\<close>\<close>
+
+\<comment> \<open>\<open>type mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>class (Size 'a)
+ val size : nat
+end\<close>\<close>
+
+\<comment> \<open>\<open>val native_size : forall 'a. nat\<close>\<close>
+
+\<comment> \<open>\<open>val ocaml_inject : forall 'a. nat * natural -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open> A singleton type family that can be used to carry a size as the type parameter \<close>\<close>
+
+\<comment> \<open>\<open>type itself 'a\<close>\<close>
+
+\<comment> \<open>\<open>val the_value : forall 'a. itself 'a\<close>\<close>
+
+\<comment> \<open>\<open>val size_itself : forall 'a. Size 'a => itself 'a -> nat\<close>\<close>
+definition size_itself :: "('a::len)itself \<Rightarrow> nat " where
+ " size_itself x = ( (len_of (TYPE(_) :: 'a itself)))"
+
+
+\<comment> \<open>\<open>*****************************************************************\<close>\<close>
+\<comment> \<open>\<open> Fixed bitwidths extracted from Anthony's models. \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> If you need a size N that is not included here, put the lines \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> type tyN \<close>\<close>
+\<comment> \<open>\<open> instance (Size tyN) let size = N end \<close>\<close>
+\<comment> \<open>\<open> declare isabelle target_rep type tyN = `N` \<close>\<close>
+\<comment> \<open>\<open> declare hol target_rep type tyN = `N` \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> in your project, replacing N in each line. \<close>\<close>
+\<comment> \<open>\<open>*****************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>type ty1\<close>\<close>
+\<comment> \<open>\<open>type ty2\<close>\<close>
+\<comment> \<open>\<open>type ty3\<close>\<close>
+\<comment> \<open>\<open>type ty4\<close>\<close>
+\<comment> \<open>\<open>type ty5\<close>\<close>
+\<comment> \<open>\<open>type ty6\<close>\<close>
+\<comment> \<open>\<open>type ty7\<close>\<close>
+\<comment> \<open>\<open>type ty8\<close>\<close>
+\<comment> \<open>\<open>type ty9\<close>\<close>
+\<comment> \<open>\<open>type ty10\<close>\<close>
+\<comment> \<open>\<open>type ty11\<close>\<close>
+\<comment> \<open>\<open>type ty12\<close>\<close>
+\<comment> \<open>\<open>type ty13\<close>\<close>
+\<comment> \<open>\<open>type ty14\<close>\<close>
+\<comment> \<open>\<open>type ty15\<close>\<close>
+\<comment> \<open>\<open>type ty16\<close>\<close>
+\<comment> \<open>\<open>type ty17\<close>\<close>
+\<comment> \<open>\<open>type ty18\<close>\<close>
+\<comment> \<open>\<open>type ty19\<close>\<close>
+\<comment> \<open>\<open>type ty20\<close>\<close>
+\<comment> \<open>\<open>type ty21\<close>\<close>
+\<comment> \<open>\<open>type ty22\<close>\<close>
+\<comment> \<open>\<open>type ty23\<close>\<close>
+\<comment> \<open>\<open>type ty24\<close>\<close>
+\<comment> \<open>\<open>type ty25\<close>\<close>
+\<comment> \<open>\<open>type ty26\<close>\<close>
+\<comment> \<open>\<open>type ty27\<close>\<close>
+\<comment> \<open>\<open>type ty28\<close>\<close>
+\<comment> \<open>\<open>type ty29\<close>\<close>
+\<comment> \<open>\<open>type ty30\<close>\<close>
+\<comment> \<open>\<open>type ty31\<close>\<close>
+\<comment> \<open>\<open>type ty32\<close>\<close>
+\<comment> \<open>\<open>type ty33\<close>\<close>
+\<comment> \<open>\<open>type ty34\<close>\<close>
+\<comment> \<open>\<open>type ty35\<close>\<close>
+\<comment> \<open>\<open>type ty36\<close>\<close>
+\<comment> \<open>\<open>type ty37\<close>\<close>
+\<comment> \<open>\<open>type ty38\<close>\<close>
+\<comment> \<open>\<open>type ty39\<close>\<close>
+\<comment> \<open>\<open>type ty40\<close>\<close>
+\<comment> \<open>\<open>type ty41\<close>\<close>
+\<comment> \<open>\<open>type ty42\<close>\<close>
+\<comment> \<open>\<open>type ty43\<close>\<close>
+\<comment> \<open>\<open>type ty44\<close>\<close>
+\<comment> \<open>\<open>type ty45\<close>\<close>
+\<comment> \<open>\<open>type ty46\<close>\<close>
+\<comment> \<open>\<open>type ty47\<close>\<close>
+\<comment> \<open>\<open>type ty48\<close>\<close>
+\<comment> \<open>\<open>type ty49\<close>\<close>
+\<comment> \<open>\<open>type ty50\<close>\<close>
+\<comment> \<open>\<open>type ty51\<close>\<close>
+\<comment> \<open>\<open>type ty52\<close>\<close>
+\<comment> \<open>\<open>type ty53\<close>\<close>
+\<comment> \<open>\<open>type ty54\<close>\<close>
+\<comment> \<open>\<open>type ty55\<close>\<close>
+\<comment> \<open>\<open>type ty56\<close>\<close>
+\<comment> \<open>\<open>type ty57\<close>\<close>
+\<comment> \<open>\<open>type ty58\<close>\<close>
+\<comment> \<open>\<open>type ty59\<close>\<close>
+\<comment> \<open>\<open>type ty60\<close>\<close>
+\<comment> \<open>\<open>type ty61\<close>\<close>
+\<comment> \<open>\<open>type ty62\<close>\<close>
+\<comment> \<open>\<open>type ty63\<close>\<close>
+\<comment> \<open>\<open>type ty64\<close>\<close>
+\<comment> \<open>\<open>type ty65\<close>\<close>
+\<comment> \<open>\<open>type ty66\<close>\<close>
+\<comment> \<open>\<open>type ty67\<close>\<close>
+\<comment> \<open>\<open>type ty68\<close>\<close>
+\<comment> \<open>\<open>type ty69\<close>\<close>
+\<comment> \<open>\<open>type ty70\<close>\<close>
+\<comment> \<open>\<open>type ty71\<close>\<close>
+\<comment> \<open>\<open>type ty72\<close>\<close>
+\<comment> \<open>\<open>type ty73\<close>\<close>
+\<comment> \<open>\<open>type ty74\<close>\<close>
+\<comment> \<open>\<open>type ty75\<close>\<close>
+\<comment> \<open>\<open>type ty76\<close>\<close>
+\<comment> \<open>\<open>type ty77\<close>\<close>
+\<comment> \<open>\<open>type ty78\<close>\<close>
+\<comment> \<open>\<open>type ty79\<close>\<close>
+\<comment> \<open>\<open>type ty80\<close>\<close>
+\<comment> \<open>\<open>type ty81\<close>\<close>
+\<comment> \<open>\<open>type ty82\<close>\<close>
+\<comment> \<open>\<open>type ty83\<close>\<close>
+\<comment> \<open>\<open>type ty84\<close>\<close>
+\<comment> \<open>\<open>type ty85\<close>\<close>
+\<comment> \<open>\<open>type ty86\<close>\<close>
+\<comment> \<open>\<open>type ty87\<close>\<close>
+\<comment> \<open>\<open>type ty88\<close>\<close>
+\<comment> \<open>\<open>type ty89\<close>\<close>
+\<comment> \<open>\<open>type ty90\<close>\<close>
+\<comment> \<open>\<open>type ty91\<close>\<close>
+\<comment> \<open>\<open>type ty92\<close>\<close>
+\<comment> \<open>\<open>type ty93\<close>\<close>
+\<comment> \<open>\<open>type ty94\<close>\<close>
+\<comment> \<open>\<open>type ty95\<close>\<close>
+\<comment> \<open>\<open>type ty96\<close>\<close>
+\<comment> \<open>\<open>type ty97\<close>\<close>
+\<comment> \<open>\<open>type ty98\<close>\<close>
+\<comment> \<open>\<open>type ty99\<close>\<close>
+\<comment> \<open>\<open>type ty100\<close>\<close>
+\<comment> \<open>\<open>type ty101\<close>\<close>
+\<comment> \<open>\<open>type ty102\<close>\<close>
+\<comment> \<open>\<open>type ty103\<close>\<close>
+\<comment> \<open>\<open>type ty104\<close>\<close>
+\<comment> \<open>\<open>type ty105\<close>\<close>
+\<comment> \<open>\<open>type ty106\<close>\<close>
+\<comment> \<open>\<open>type ty107\<close>\<close>
+\<comment> \<open>\<open>type ty108\<close>\<close>
+\<comment> \<open>\<open>type ty109\<close>\<close>
+\<comment> \<open>\<open>type ty110\<close>\<close>
+\<comment> \<open>\<open>type ty111\<close>\<close>
+\<comment> \<open>\<open>type ty112\<close>\<close>
+\<comment> \<open>\<open>type ty113\<close>\<close>
+\<comment> \<open>\<open>type ty114\<close>\<close>
+\<comment> \<open>\<open>type ty115\<close>\<close>
+\<comment> \<open>\<open>type ty116\<close>\<close>
+\<comment> \<open>\<open>type ty117\<close>\<close>
+\<comment> \<open>\<open>type ty118\<close>\<close>
+\<comment> \<open>\<open>type ty119\<close>\<close>
+\<comment> \<open>\<open>type ty120\<close>\<close>
+\<comment> \<open>\<open>type ty121\<close>\<close>
+\<comment> \<open>\<open>type ty122\<close>\<close>
+\<comment> \<open>\<open>type ty123\<close>\<close>
+\<comment> \<open>\<open>type ty124\<close>\<close>
+\<comment> \<open>\<open>type ty125\<close>\<close>
+\<comment> \<open>\<open>type ty126\<close>\<close>
+\<comment> \<open>\<open>type ty127\<close>\<close>
+\<comment> \<open>\<open>type ty128\<close>\<close>
+\<comment> \<open>\<open>type ty129\<close>\<close>
+\<comment> \<open>\<open>type ty130\<close>\<close>
+\<comment> \<open>\<open>type ty131\<close>\<close>
+\<comment> \<open>\<open>type ty132\<close>\<close>
+\<comment> \<open>\<open>type ty133\<close>\<close>
+\<comment> \<open>\<open>type ty134\<close>\<close>
+\<comment> \<open>\<open>type ty135\<close>\<close>
+\<comment> \<open>\<open>type ty136\<close>\<close>
+\<comment> \<open>\<open>type ty137\<close>\<close>
+\<comment> \<open>\<open>type ty138\<close>\<close>
+\<comment> \<open>\<open>type ty139\<close>\<close>
+\<comment> \<open>\<open>type ty140\<close>\<close>
+\<comment> \<open>\<open>type ty141\<close>\<close>
+\<comment> \<open>\<open>type ty142\<close>\<close>
+\<comment> \<open>\<open>type ty143\<close>\<close>
+\<comment> \<open>\<open>type ty144\<close>\<close>
+\<comment> \<open>\<open>type ty145\<close>\<close>
+\<comment> \<open>\<open>type ty146\<close>\<close>
+\<comment> \<open>\<open>type ty147\<close>\<close>
+\<comment> \<open>\<open>type ty148\<close>\<close>
+\<comment> \<open>\<open>type ty149\<close>\<close>
+\<comment> \<open>\<open>type ty150\<close>\<close>
+\<comment> \<open>\<open>type ty151\<close>\<close>
+\<comment> \<open>\<open>type ty152\<close>\<close>
+\<comment> \<open>\<open>type ty153\<close>\<close>
+\<comment> \<open>\<open>type ty154\<close>\<close>
+\<comment> \<open>\<open>type ty155\<close>\<close>
+\<comment> \<open>\<open>type ty156\<close>\<close>
+\<comment> \<open>\<open>type ty157\<close>\<close>
+\<comment> \<open>\<open>type ty158\<close>\<close>
+\<comment> \<open>\<open>type ty159\<close>\<close>
+\<comment> \<open>\<open>type ty160\<close>\<close>
+\<comment> \<open>\<open>type ty161\<close>\<close>
+\<comment> \<open>\<open>type ty162\<close>\<close>
+\<comment> \<open>\<open>type ty163\<close>\<close>
+\<comment> \<open>\<open>type ty164\<close>\<close>
+\<comment> \<open>\<open>type ty165\<close>\<close>
+\<comment> \<open>\<open>type ty166\<close>\<close>
+\<comment> \<open>\<open>type ty167\<close>\<close>
+\<comment> \<open>\<open>type ty168\<close>\<close>
+\<comment> \<open>\<open>type ty169\<close>\<close>
+\<comment> \<open>\<open>type ty170\<close>\<close>
+\<comment> \<open>\<open>type ty171\<close>\<close>
+\<comment> \<open>\<open>type ty172\<close>\<close>
+\<comment> \<open>\<open>type ty173\<close>\<close>
+\<comment> \<open>\<open>type ty174\<close>\<close>
+\<comment> \<open>\<open>type ty175\<close>\<close>
+\<comment> \<open>\<open>type ty176\<close>\<close>
+\<comment> \<open>\<open>type ty177\<close>\<close>
+\<comment> \<open>\<open>type ty178\<close>\<close>
+\<comment> \<open>\<open>type ty179\<close>\<close>
+\<comment> \<open>\<open>type ty180\<close>\<close>
+\<comment> \<open>\<open>type ty181\<close>\<close>
+\<comment> \<open>\<open>type ty182\<close>\<close>
+\<comment> \<open>\<open>type ty183\<close>\<close>
+\<comment> \<open>\<open>type ty184\<close>\<close>
+\<comment> \<open>\<open>type ty185\<close>\<close>
+\<comment> \<open>\<open>type ty186\<close>\<close>
+\<comment> \<open>\<open>type ty187\<close>\<close>
+\<comment> \<open>\<open>type ty188\<close>\<close>
+\<comment> \<open>\<open>type ty189\<close>\<close>
+\<comment> \<open>\<open>type ty190\<close>\<close>
+\<comment> \<open>\<open>type ty191\<close>\<close>
+\<comment> \<open>\<open>type ty192\<close>\<close>
+\<comment> \<open>\<open>type ty193\<close>\<close>
+\<comment> \<open>\<open>type ty194\<close>\<close>
+\<comment> \<open>\<open>type ty195\<close>\<close>
+\<comment> \<open>\<open>type ty196\<close>\<close>
+\<comment> \<open>\<open>type ty197\<close>\<close>
+\<comment> \<open>\<open>type ty198\<close>\<close>
+\<comment> \<open>\<open>type ty199\<close>\<close>
+\<comment> \<open>\<open>type ty200\<close>\<close>
+\<comment> \<open>\<open>type ty201\<close>\<close>
+\<comment> \<open>\<open>type ty202\<close>\<close>
+\<comment> \<open>\<open>type ty203\<close>\<close>
+\<comment> \<open>\<open>type ty204\<close>\<close>
+\<comment> \<open>\<open>type ty205\<close>\<close>
+\<comment> \<open>\<open>type ty206\<close>\<close>
+\<comment> \<open>\<open>type ty207\<close>\<close>
+\<comment> \<open>\<open>type ty208\<close>\<close>
+\<comment> \<open>\<open>type ty209\<close>\<close>
+\<comment> \<open>\<open>type ty210\<close>\<close>
+\<comment> \<open>\<open>type ty211\<close>\<close>
+\<comment> \<open>\<open>type ty212\<close>\<close>
+\<comment> \<open>\<open>type ty213\<close>\<close>
+\<comment> \<open>\<open>type ty214\<close>\<close>
+\<comment> \<open>\<open>type ty215\<close>\<close>
+\<comment> \<open>\<open>type ty216\<close>\<close>
+\<comment> \<open>\<open>type ty217\<close>\<close>
+\<comment> \<open>\<open>type ty218\<close>\<close>
+\<comment> \<open>\<open>type ty219\<close>\<close>
+\<comment> \<open>\<open>type ty220\<close>\<close>
+\<comment> \<open>\<open>type ty221\<close>\<close>
+\<comment> \<open>\<open>type ty222\<close>\<close>
+\<comment> \<open>\<open>type ty223\<close>\<close>
+\<comment> \<open>\<open>type ty224\<close>\<close>
+\<comment> \<open>\<open>type ty225\<close>\<close>
+\<comment> \<open>\<open>type ty226\<close>\<close>
+\<comment> \<open>\<open>type ty227\<close>\<close>
+\<comment> \<open>\<open>type ty228\<close>\<close>
+\<comment> \<open>\<open>type ty229\<close>\<close>
+\<comment> \<open>\<open>type ty230\<close>\<close>
+\<comment> \<open>\<open>type ty231\<close>\<close>
+\<comment> \<open>\<open>type ty232\<close>\<close>
+\<comment> \<open>\<open>type ty233\<close>\<close>
+\<comment> \<open>\<open>type ty234\<close>\<close>
+\<comment> \<open>\<open>type ty235\<close>\<close>
+\<comment> \<open>\<open>type ty236\<close>\<close>
+\<comment> \<open>\<open>type ty237\<close>\<close>
+\<comment> \<open>\<open>type ty238\<close>\<close>
+\<comment> \<open>\<open>type ty239\<close>\<close>
+\<comment> \<open>\<open>type ty240\<close>\<close>
+\<comment> \<open>\<open>type ty241\<close>\<close>
+\<comment> \<open>\<open>type ty242\<close>\<close>
+\<comment> \<open>\<open>type ty243\<close>\<close>
+\<comment> \<open>\<open>type ty244\<close>\<close>
+\<comment> \<open>\<open>type ty245\<close>\<close>
+\<comment> \<open>\<open>type ty246\<close>\<close>
+\<comment> \<open>\<open>type ty247\<close>\<close>
+\<comment> \<open>\<open>type ty248\<close>\<close>
+\<comment> \<open>\<open>type ty249\<close>\<close>
+\<comment> \<open>\<open>type ty250\<close>\<close>
+\<comment> \<open>\<open>type ty251\<close>\<close>
+\<comment> \<open>\<open>type ty252\<close>\<close>
+\<comment> \<open>\<open>type ty253\<close>\<close>
+\<comment> \<open>\<open>type ty254\<close>\<close>
+\<comment> \<open>\<open>type ty255\<close>\<close>
+\<comment> \<open>\<open>type ty256\<close>\<close>
+\<comment> \<open>\<open>type ty257\<close>\<close>
+
+\<comment> \<open>\<open>val word_length : forall 'a. mword 'a -> nat\<close>\<close>
+
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+\<comment> \<open>\<open> Conversions \<close>\<close>
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val signedIntegerFromWord : forall 'a. mword 'a -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val unsignedIntegerFromWord : forall 'a. mword 'a -> integer\<close>\<close>
+
+\<comment> \<open>\<open> Version without typeclass constraint so that we can derive operations
+ in Lem for one of the theorem provers without requiring it. \<close>\<close>
+\<comment> \<open>\<open>val proverWordFromInteger : forall 'a. integer -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val wordFromInteger : forall 'a. Size 'a => integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open> The OCaml version is defined after the arithmetic operations, below. \<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromWord : forall 'a. mword 'a -> natural\<close>\<close>
+
+\<comment> \<open>\<open>val wordFromNatural : forall 'a. Size 'a => natural -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val wordToHex : forall 'a. mword 'a -> string\<close>\<close>
+\<comment> \<open>\<open> Building libraries fails if we don't provide implementations for the
+ type class. \<close>\<close>
+definition wordToHex :: "('a::len)Word.word \<Rightarrow> string " where
+ " wordToHex w = ( (''wordToHex not yet implemented''))"
+
+
+definition instance_Show_Show_Machine_word_mword_dict :: "(('a::len)Word.word)Show_class " where
+ " instance_Show_Show_Machine_word_mword_dict = ((|
+
+ show_method = wordToHex |) )"
+
+
+\<comment> \<open>\<open>val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val bitlistFromWord : forall 'a. mword 'a -> list bool\<close>\<close>
+
+
+\<comment> \<open>\<open>val size_test_fn : forall 'a. Size 'a => mword 'a -> nat\<close>\<close>
+definition size_test_fn :: "('a::len)Word.word \<Rightarrow> nat " where
+ " size_test_fn _ = ( (len_of (TYPE(_) :: 'a itself)))"
+
+
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+\<comment> \<open>\<open> Comparisons \<close>\<close>
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val mwordEq : forall 'a. mword 'a -> mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val signedLess : forall 'a. mword 'a -> mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open> Comparison tests are below, after the definition of wordFromInteger \<close>\<close>
+
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+\<comment> \<open>\<open> Appending, splitting and probing words \<close>\<close>
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c\<close>\<close>
+
+\<comment> \<open>\<open> Note that we assume the result type has the correct size, especially
+ for Isabelle. \<close>\<close>
+\<comment> \<open>\<open>val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b\<close>\<close>
+
+\<comment> \<open>\<open> Needs to be in the prover because we'd end up with unknown sizes in the
+ types in Lem.
+\<close>\<close>
+\<comment> \<open>\<open>val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val getBit : forall 'a. mword 'a -> nat -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val msb : forall 'a. mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val lsb : forall 'a. mword 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+\<comment> \<open>\<open> Bitwise operations, shifts, etc. \<close>\<close>
+\<comment> \<open>\<open>****************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val shiftLeft : forall 'a. mword 'a -> nat -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val shiftRight : forall 'a. mword 'a -> nat -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val lAnd : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val lOr : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val lXor : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val lNot : forall 'a. mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val rotateRight : forall 'a. nat -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b\<close>\<close>
+
+\<comment> \<open>\<open>val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b\<close>\<close>
+
+\<comment> \<open>\<open> Sign extension tests are below, after the definition of wordFromInteger \<close>\<close>
+
+\<comment> \<open>\<open>***************************************************************\<close>\<close>
+\<comment> \<open>\<open> Arithmetic \<close>\<close>
+\<comment> \<open>\<open>***************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val plus : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val minus : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val uminus : forall 'a. mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val times : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+definition signedDivide :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " signedDivide x y = (
+ if Bits.msb x then
+ if Bits.msb y then (- x) div (- y)
+ else - ((- x) div y)
+ else if Bits.msb y then - (x div (- y))
+ else x div y )"
+
+
+\<comment> \<open>\<open>val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a\<close>\<close>
+
+\<comment> \<open>\<open>val wordFromNumeral : forall 'a. Size 'a => numeral -> mword 'a\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_map.thy b/prover_snapshots/isabelle/lib/lem/Lem_map.thy
new file mode 100644
index 0000000..89aed53
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_map.thy
@@ -0,0 +1,159 @@
+chapter \<open>Generated by Lem from \<open>map.lem\<close>.\<close>
+
+theory "Lem_map"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_function"
+ "Lem_maybe"
+ "Lem_list"
+ "Lem_tuple"
+ "Lem_set"
+ "Lem_num"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes Function Maybe List Tuple Set Num\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `finite_mapTheory` `finite_mapLib`\<close>\<close>
+
+\<comment> \<open>\<open>type map 'k 'v\<close>\<close>
+
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Map equality. \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool\<close>\<close>
+\<comment> \<open>\<open>val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Map type class \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>class ( MapKeyType 'a )
+ val {ocaml;coq} mapKeyCompare : 'a -> 'a -> ordering
+end\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Empty maps \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v\<close>\<close>
+\<comment> \<open>\<open>val emptyBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Insertion \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val insert : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Singleton \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v\<close>\<close>
+
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Emptyness check \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val null : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> lookup \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val lookupBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> maybe 'v\<close>\<close>
+
+\<comment> \<open>\<open>val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> maybe 'v\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> findWithDefault \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> from lists \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val fromList : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v\<close>\<close>
+\<comment> \<open>\<open>let fromList l= foldl (fun m (k,v) -> insert k v m) empty l\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> to sets / domain / range \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)\<close>\<close>
+\<comment> \<open>\<open>val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> ordering) -> map 'k 'v -> set ('k * 'v)\<close>\<close>
+
+
+\<comment> \<open>\<open>val domainBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v -> set 'k\<close>\<close>
+\<comment> \<open>\<open>val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k\<close>\<close>
+
+
+\<comment> \<open>\<open>val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v\<close>\<close>
+\<comment> \<open>\<open>val rangeBy : forall 'k 'v. ('v -> 'v -> ordering) -> map 'k 'v -> set 'v\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> member \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val member : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val notMember : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Quantification \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool\<close>\<close>
+\<comment> \<open>\<open>val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool\<close>\<close>
+
+\<comment> \<open>\<open>let all P m= (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Set-like operations. \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open>val deleteBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> map 'k 'v\<close>\<close>
+\<comment> \<open>\<open>val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v\<close>\<close>
+\<comment> \<open>\<open>val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v\<close>\<close>
+
+\<comment> \<open>\<open>val union : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v\<close>\<close>
+
+\<comment> \<open>\<open>val unions : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v\<close>\<close>
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Maps (in the functor sense). \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val map : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w\<close>\<close>
+
+\<comment> \<open>\<open>val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> Cardinality \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open>val size : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat\<close>\<close>
+
+\<comment> \<open>\<open> instance of SetType \<close>\<close>
+definition map_setElemCompare :: "(('d*'c)set \<Rightarrow>('b*'a)set \<Rightarrow> 'e)\<Rightarrow>('d,'c)Map.map \<Rightarrow>('b,'a)Map.map \<Rightarrow> 'e " where
+ " map_setElemCompare cmp x y = (
+ cmp (map_to_set x) (map_to_set y))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_map_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_map_extra.thy
new file mode 100644
index 0000000..0072d23
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_map_extra.thy
@@ -0,0 +1,82 @@
+chapter \<open>Generated by Lem from \<open>map_extra.lem\<close>.\<close>
+
+theory "Lem_map_extra"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_function"
+ "Lem_assert_extra"
+ "Lem_maybe"
+ "Lem_list"
+ "Lem_num"
+ "Lem_set"
+ "Lem_map"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> find \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val find : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> 'v\<close>\<close>
+\<comment> \<open>\<open>let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith "Map_extra.find" end\<close>\<close>
+
+
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> from sets / domain / range \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+
+\<comment> \<open>\<open>val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> map 'k 'v\<close>\<close>
+definition fromSet :: "('k \<Rightarrow> 'v)\<Rightarrow> 'k set \<Rightarrow>('k,'v)Map.map " where
+ " fromSet f s = ( Finite_Set.fold (\<lambda> k m . map_update k (f k) m) Map.empty s )"
+
+
+\<comment> \<open>\<open>
+assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty)
+assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)]
+\<close>\<close>
+
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> fold \<close>\<close>
+\<comment> \<open>\<open> -------------------------------------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> map 'k 'v -> 'r -> 'r\<close>\<close>
+definition fold :: "('k \<Rightarrow> 'v \<Rightarrow> 'r \<Rightarrow> 'r)\<Rightarrow>('k,'v)Map.map \<Rightarrow> 'r \<Rightarrow> 'r " where
+ " fold f m v = ( Finite_Set.fold ( \<lambda>x .
+ (case x of (k, v) => \<lambda> r . f k v r )) v (map_to_set m))"
+
+
+\<comment> \<open>\<open>
+assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9)
+assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12)
+\<close>\<close>
+
+\<comment> \<open>\<open>val toList: forall 'k 'v. MapKeyType 'k => map 'k 'v -> list ('k * 'v)\<close>\<close>
+\<comment> \<open>\<open> declare compile_message toList = "Map_extra.toList is only defined for the ocaml, isabelle and coq backend" \<close>\<close>
+
+\<comment> \<open>\<open> more 'map' functions \<close>\<close>
+
+\<comment> \<open>\<open> TODO: this function is in map_extra rather than map just for implementation reasons \<close>\<close>
+\<comment> \<open>\<open>val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> maybe 'c) -> map 'a 'b -> map 'a 'c\<close>\<close>
+\<comment> \<open>\<open> OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle \<close>\<close>
+definition option_map :: "('a \<Rightarrow> 'b \<Rightarrow> 'c option)\<Rightarrow>('a,'b)Map.map \<Rightarrow>('a,'c)Map.map " where
+ " option_map f m = (
+ List.foldl
+ (\<lambda> m' . \<lambda>x .
+ (case x of
+ (k, v) =>
+ (case f k v of None => m' | Some v' => map_update k v' m' )
+ ))
+ Map.empty
+ (list_of_set (LemExtraDefs.map_to_set m)))"
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_maybe.thy b/prover_snapshots/isabelle/lib/lem/Lem_maybe.thy
new file mode 100644
index 0000000..2cbdc73
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_maybe.thy
@@ -0,0 +1,113 @@
+chapter \<open>Generated by Lem from \<open>maybe.lem\<close>.\<close>
+
+theory "Lem_maybe"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_function"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes Function\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Basic stuff \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>type maybe 'a =
+ | Nothing
+ | Just of 'a\<close>\<close>
+
+
+\<comment> \<open>\<open>val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool\<close>\<close>
+
+fun maybeEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a option \<Rightarrow> 'a option \<Rightarrow> bool " where
+ " maybeEqualBy eq None None = ( True )"
+|" maybeEqualBy eq None (Some _) = ( False )"
+|" maybeEqualBy eq (Some _) None = ( False )"
+|" maybeEqualBy eq (Some x') (Some y') = ( (eq x' y'))"
+
+
+
+fun maybeCompare :: "('b \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'b option \<Rightarrow> 'a option \<Rightarrow> ordering " where
+ " maybeCompare cmp None None = ( EQ )"
+|" maybeCompare cmp None (Some _) = ( LT )"
+|" maybeCompare cmp (Some _) None = ( GT )"
+|" maybeCompare cmp (Some x') (Some y') = ( cmp x' y' )"
+
+
+definition instance_Basic_classes_Ord_Maybe_maybe_dict :: " 'a Ord_class \<Rightarrow>('a option)Ord_class " where
+ " instance_Basic_classes_Ord_Maybe_maybe_dict dict_Basic_classes_Ord_a = ((|
+
+ compare_method = (maybeCompare
+ (compare_method dict_Basic_classes_Ord_a)),
+
+ isLess_method = (\<lambda> m1 . (\<lambda> m2 . maybeCompare
+ (compare_method dict_Basic_classes_Ord_a) m1 m2 = LT)),
+
+ isLessEqual_method = (\<lambda> m1 . (\<lambda> m2 . ((let r = (maybeCompare
+ (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = LT) \<or> (r = EQ))))),
+
+ isGreater_method = (\<lambda> m1 . (\<lambda> m2 . maybeCompare
+ (compare_method dict_Basic_classes_Ord_a) m1 m2 = GT)),
+
+ isGreaterEqual_method = (\<lambda> m1 . (\<lambda> m2 . ((let r = (maybeCompare
+ (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = GT) \<or> (r = EQ)))))|) )"
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> maybe \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b\<close>\<close>
+\<comment> \<open>\<open>let maybe d f mb= match mb with
+ | Just a -> f a
+ | Nothing -> d
+end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> isJust / isNothing \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isJust : forall 'a. maybe 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isJust mb= match mb with
+ | Just _ -> true
+ | Nothing -> false
+end\<close>\<close>
+
+\<comment> \<open>\<open>val isNothing : forall 'a. maybe 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isNothing mb= match mb with
+ | Just _ -> false
+ | Nothing -> true
+end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> fromMaybe \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a\<close>\<close>
+\<comment> \<open>\<open>let fromMaybe d mb= match mb with
+ | Just v -> v
+ | Nothing -> d
+end\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> map \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b\<close>\<close>
+\<comment> \<open>\<open>let map f= maybe Nothing (fun v -> Just (f v))\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> bind \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b\<close>\<close>
+\<comment> \<open>\<open>let bind mb f= maybe Nothing f mb\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_maybe_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_maybe_extra.thy
new file mode 100644
index 0000000..cfe1836
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_maybe_extra.thy
@@ -0,0 +1,24 @@
+chapter \<open>Generated by Lem from \<open>maybe_extra.lem\<close>.\<close>
+
+theory "Lem_maybe_extra"
+
+imports
+ Main
+ "Lem_basic_classes"
+ "Lem_maybe"
+ "Lem_assert_extra"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Basic_classes Maybe Assert_extra\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> fromJust \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val fromJust : forall 'a. maybe 'a -> 'a\<close>\<close>
+\<comment> \<open>\<open>let fromJust op= match op with | Just v -> v | Nothing -> failwith "fromJust of Nothing" end\<close>\<close>
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_num.thy b/prover_snapshots/isabelle/lib/lem/Lem_num.thy
new file mode 100644
index 0000000..c31f690
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_num.thy
@@ -0,0 +1,1313 @@
+chapter \<open>Generated by Lem from \<open>num.lem\<close>.\<close>
+
+theory "Lem_num"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "HOL-Word.Word"
+ "Complex_Main"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `HOL-Word.Word` `Complex_Main`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`\<close>\<close>
+
+\<comment> \<open>\<open>class inline ( Numeral 'a )
+ val fromNumeral : numeral -> 'a
+end\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Syntactic type-classes for common operations \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> Typeclasses can be used as a mean to overload constants like "+", "-", etc \<close>\<close>
+
+record 'a NumNegate_class=
+
+ numNegate_method ::" 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumAbs_class=
+
+ abs_method ::" 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumAdd_class=
+
+ numAdd_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumMinus_class=
+
+ numMinus_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumMult_class=
+
+ numMult_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumPow_class=
+
+ numPow_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a "
+
+
+
+record 'a NumDivision_class=
+
+ numDivision_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumIntegerDivision_class=
+
+ div_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+
+record 'a NumRemainder_class=
+
+ mod_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumSucc_class=
+
+ succ_method ::" 'a \<Rightarrow> 'a "
+
+
+
+record 'a NumPred_class=
+
+ pred_method ::" 'a \<Rightarrow> 'a "
+
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> natural \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> unbounded size natural numbers \<close>\<close>
+\<comment> \<open>\<open>type natural\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> bounded size integers with uncertain length \<close>\<close>
+
+\<comment> \<open>\<open>type int\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> integer \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> unbounded size integers \<close>\<close>
+
+\<comment> \<open>\<open>type integer\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> bint \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> TODO the bounded ints are only partially implemented, use with care. \<close>\<close>
+
+\<comment> \<open>\<open> 32 bit integers \<close>\<close>
+\<comment> \<open>\<open>type int32\<close>\<close>
+
+\<comment> \<open>\<open> 64 bit integers \<close>\<close>
+\<comment> \<open>\<open>type int64\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> rational \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> unbounded size and precision rational numbers \<close>\<close>
+
+\<comment> \<open>\<open>type rational\<close>\<close> \<comment> \<open>\<open> ???: better type for this in HOL? \<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> real \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> real numbers \<close>\<close>
+\<comment> \<open>\<open> Note that for OCaml, this is mapped to floats with 64 bits. \<close>\<close>
+
+\<comment> \<open>\<open>type real\<close>\<close> \<comment> \<open>\<open> ???: better type for this in HOL? \<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> double \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> double precision floating point (64 bits) \<close>\<close>
+
+\<comment> \<open>\<open>type float64\<close>\<close> \<comment> \<open>\<open> ???: better type for this in HOL? \<close>\<close>
+
+\<comment> \<open>\<open>type float32\<close>\<close> \<comment> \<open>\<open> ???: better type for this in HOL? \<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Binding the standard operations for the number types \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> nat \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val natFromNumeral : numeral -> nat\<close>\<close>
+
+\<comment> \<open>\<open>val natEq : nat -> nat -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val natLess : nat -> nat -> bool\<close>\<close>
+\<comment> \<open>\<open>val natLessEqual : nat -> nat -> bool\<close>\<close>
+\<comment> \<open>\<open>val natGreater : nat -> nat -> bool\<close>\<close>
+\<comment> \<open>\<open>val natGreaterEqual : nat -> nat -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val natCompare : nat -> nat -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_nat_dict :: "(nat)Ord_class " where
+ " instance_Basic_classes_Ord_nat_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val natAdd : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumAdd_nat_dict :: "(nat)NumAdd_class " where
+ " instance_Num_NumAdd_nat_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val natMinus : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumMinus_nat_dict :: "(nat)NumMinus_class " where
+ " instance_Num_NumMinus_nat_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val natSucc : nat -> nat\<close>\<close>
+\<comment> \<open>\<open>let natSucc n= (Instance_Num_NumAdd_nat.+) n 1\<close>\<close>
+definition instance_Num_NumSucc_nat_dict :: "(nat)NumSucc_class " where
+ " instance_Num_NumSucc_nat_dict = ((|
+
+ succ_method = Suc |) )"
+
+
+\<comment> \<open>\<open>val natPred : nat -> nat\<close>\<close>
+definition instance_Num_NumPred_nat_dict :: "(nat)NumPred_class " where
+ " instance_Num_NumPred_nat_dict = ((|
+
+ pred_method = (\<lambda> n. n -( 1 :: nat))|) )"
+
+
+\<comment> \<open>\<open>val natMult : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumMult_nat_dict :: "(nat)NumMult_class " where
+ " instance_Num_NumMult_nat_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+\<comment> \<open>\<open>val natDiv : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_nat_dict :: "(nat)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_nat_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_nat_dict :: "(nat)NumDivision_class " where
+ " instance_Num_NumDivision_nat_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val natMod : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumRemainder_nat_dict :: "(nat)NumRemainder_class " where
+ " instance_Num_NumRemainder_nat_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+
+\<comment> \<open>\<open>val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a\<close>\<close>
+fun gen_pow_aux :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where
+ " gen_pow_aux (mul :: 'a \<Rightarrow> 'a \<Rightarrow> 'a) (a :: 'a) (b :: 'a) (e :: nat) = (
+ (case e of
+ 0 => a \<comment> \<open>\<open> cannot happen, call discipline guarentees e >= 1 \<close>\<close>
+ | (Suc 0) => mul a b
+ | ( (Suc(Suc e'))) => (let e'' = (e div( 2 :: nat)) in
+ (let a' = (if (e mod( 2 :: nat)) =( 0 :: nat) then a else mul a b) in
+ gen_pow_aux mul a' (mul b b) e''))
+ ))"
+
+
+definition gen_pow :: " 'a \<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where
+ " gen_pow (one :: 'a) (mul :: 'a \<Rightarrow> 'a \<Rightarrow> 'a) (b :: 'a) (e :: nat) = (
+ if e <( 0 :: nat) then one else
+ if (e =( 0 :: nat)) then one else gen_pow_aux mul one b e )"
+
+
+\<comment> \<open>\<open>val natPow : nat -> nat -> nat\<close>\<close>
+
+definition instance_Num_NumPow_nat_dict :: "(nat)NumPow_class " where
+ " instance_Num_NumPow_nat_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val natMin : nat -> nat -> nat\<close>\<close>
+
+\<comment> \<open>\<open>val natMax : nat -> nat -> nat\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_nat_dict :: "(nat)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_nat_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> natural \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromNumeral : numeral -> natural\<close>\<close>
+
+\<comment> \<open>\<open>val naturalEq : natural -> natural -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val naturalLess : natural -> natural -> bool\<close>\<close>
+\<comment> \<open>\<open>val naturalLessEqual : natural -> natural -> bool\<close>\<close>
+\<comment> \<open>\<open>val naturalGreater : natural -> natural -> bool\<close>\<close>
+\<comment> \<open>\<open>val naturalGreaterEqual : natural -> natural -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val naturalCompare : natural -> natural -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_natural_dict :: "(nat)Ord_class " where
+ " instance_Basic_classes_Ord_Num_natural_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val naturalAdd : natural -> natural -> natural\<close>\<close>
+
+definition instance_Num_NumAdd_Num_natural_dict :: "(nat)NumAdd_class " where
+ " instance_Num_NumAdd_Num_natural_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val naturalMinus : natural -> natural -> natural\<close>\<close>
+
+definition instance_Num_NumMinus_Num_natural_dict :: "(nat)NumMinus_class " where
+ " instance_Num_NumMinus_Num_natural_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val naturalSucc : natural -> natural\<close>\<close>
+\<comment> \<open>\<open>let naturalSucc n= (Instance_Num_NumAdd_Num_natural.+) n 1\<close>\<close>
+definition instance_Num_NumSucc_Num_natural_dict :: "(nat)NumSucc_class " where
+ " instance_Num_NumSucc_Num_natural_dict = ((|
+
+ succ_method = Suc |) )"
+
+
+\<comment> \<open>\<open>val naturalPred : natural -> natural\<close>\<close>
+definition instance_Num_NumPred_Num_natural_dict :: "(nat)NumPred_class " where
+ " instance_Num_NumPred_Num_natural_dict = ((|
+
+ pred_method = (\<lambda> n. n -( 1 :: nat))|) )"
+
+
+\<comment> \<open>\<open>val naturalMult : natural -> natural -> natural\<close>\<close>
+
+definition instance_Num_NumMult_Num_natural_dict :: "(nat)NumMult_class " where
+ " instance_Num_NumMult_Num_natural_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+
+\<comment> \<open>\<open>val naturalPow : natural -> nat -> natural\<close>\<close>
+
+definition instance_Num_NumPow_Num_natural_dict :: "(nat)NumPow_class " where
+ " instance_Num_NumPow_Num_natural_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val naturalDiv : natural -> natural -> natural\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_Num_natural_dict :: "(nat)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Num_natural_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_Num_natural_dict :: "(nat)NumDivision_class " where
+ " instance_Num_NumDivision_Num_natural_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val naturalMod : natural -> natural -> natural\<close>\<close>
+
+definition instance_Num_NumRemainder_Num_natural_dict :: "(nat)NumRemainder_class " where
+ " instance_Num_NumRemainder_Num_natural_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+\<comment> \<open>\<open>val naturalMin : natural -> natural -> natural\<close>\<close>
+
+\<comment> \<open>\<open>val naturalMax : natural -> natural -> natural\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_natural_dict :: "(nat)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_natural_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val intFromNumeral : numeral -> int\<close>\<close>
+
+\<comment> \<open>\<open>val intEq : int -> int -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val intLess : int -> int -> bool\<close>\<close>
+\<comment> \<open>\<open>val intLessEqual : int -> int -> bool\<close>\<close>
+\<comment> \<open>\<open>val intGreater : int -> int -> bool\<close>\<close>
+\<comment> \<open>\<open>val intGreaterEqual : int -> int -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val intCompare : int -> int -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_int_dict :: "(int)Ord_class " where
+ " instance_Basic_classes_Ord_Num_int_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val intNegate : int -> int\<close>\<close>
+
+definition instance_Num_NumNegate_Num_int_dict :: "(int)NumNegate_class " where
+ " instance_Num_NumNegate_Num_int_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val intAbs : int -> int\<close>\<close> \<comment> \<open>\<open> TODO: check \<close>\<close>
+
+definition instance_Num_NumAbs_Num_int_dict :: "(int)NumAbs_class " where
+ " instance_Num_NumAbs_Num_int_dict = ((|
+
+ abs_method = abs |) )"
+
+
+\<comment> \<open>\<open>val intAdd : int -> int -> int\<close>\<close>
+
+definition instance_Num_NumAdd_Num_int_dict :: "(int)NumAdd_class " where
+ " instance_Num_NumAdd_Num_int_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val intMinus : int -> int -> int\<close>\<close>
+
+definition instance_Num_NumMinus_Num_int_dict :: "(int)NumMinus_class " where
+ " instance_Num_NumMinus_Num_int_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val intSucc : int -> int\<close>\<close>
+definition instance_Num_NumSucc_Num_int_dict :: "(int)NumSucc_class " where
+ " instance_Num_NumSucc_Num_int_dict = ((|
+
+ succ_method = (\<lambda> n. n +( 1 :: int))|) )"
+
+
+\<comment> \<open>\<open>val intPred : int -> int\<close>\<close>
+definition instance_Num_NumPred_Num_int_dict :: "(int)NumPred_class " where
+ " instance_Num_NumPred_Num_int_dict = ((|
+
+ pred_method = (\<lambda> n. n -( 1 :: int))|) )"
+
+
+\<comment> \<open>\<open>val intMult : int -> int -> int\<close>\<close>
+
+definition instance_Num_NumMult_Num_int_dict :: "(int)NumMult_class " where
+ " instance_Num_NumMult_Num_int_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+
+\<comment> \<open>\<open>val intPow : int -> nat -> int\<close>\<close>
+
+definition instance_Num_NumPow_Num_int_dict :: "(int)NumPow_class " where
+ " instance_Num_NumPow_Num_int_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val intDiv : int -> int -> int\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_Num_int_dict :: "(int)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Num_int_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_Num_int_dict :: "(int)NumDivision_class " where
+ " instance_Num_NumDivision_Num_int_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val intMod : int -> int -> int\<close>\<close>
+
+definition instance_Num_NumRemainder_Num_int_dict :: "(int)NumRemainder_class " where
+ " instance_Num_NumRemainder_Num_int_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+\<comment> \<open>\<open>val intMin : int -> int -> int\<close>\<close>
+
+\<comment> \<open>\<open>val intMax : int -> int -> int\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_int_dict :: "(int)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_int_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int32 \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open>val int32FromNumeral : numeral -> int32\<close>\<close>
+
+\<comment> \<open>\<open>val int32Eq : int32 -> int32 -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val int32Less : int32 -> int32 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int32LessEqual : int32 -> int32 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int32Greater : int32 -> int32 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int32GreaterEqual : int32 -> int32 -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val int32Compare : int32 -> int32 -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_int32_dict :: "( 32 word)Ord_class " where
+ " instance_Basic_classes_Ord_Num_int32_dict = ((|
+
+ compare_method = (genericCompare word_sless (=)),
+
+ isLess_method = word_sless,
+
+ isLessEqual_method = word_sle,
+
+ isGreater_method = (\<lambda> x y. word_sless y x),
+
+ isGreaterEqual_method = (\<lambda> x y. word_sle y x)|) )"
+
+
+\<comment> \<open>\<open>val int32Negate : int32 -> int32\<close>\<close>
+
+definition instance_Num_NumNegate_Num_int32_dict :: "( 32 word)NumNegate_class " where
+ " instance_Num_NumNegate_Num_int32_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val int32Abs : int32 -> int32\<close>\<close>
+definition int32Abs :: " 32 word \<Rightarrow> 32 word " where
+ " int32Abs i = ( (if word_sle(((word_of_int 0) :: 32 word)) i then i else - i))"
+
+
+definition instance_Num_NumAbs_Num_int32_dict :: "( 32 word)NumAbs_class " where
+ " instance_Num_NumAbs_Num_int32_dict = ((|
+
+ abs_method = int32Abs |) )"
+
+
+
+\<comment> \<open>\<open>val int32Add : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Num_NumAdd_Num_int32_dict :: "( 32 word)NumAdd_class " where
+ " instance_Num_NumAdd_Num_int32_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val int32Minus : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Num_NumMinus_Num_int32_dict :: "( 32 word)NumMinus_class " where
+ " instance_Num_NumMinus_Num_int32_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val int32Succ : int32 -> int32\<close>\<close>
+
+definition instance_Num_NumSucc_Num_int32_dict :: "( 32 word)NumSucc_class " where
+ " instance_Num_NumSucc_Num_int32_dict = ((|
+
+ succ_method = (\<lambda> n. n +((word_of_int 1) :: 32 word))|) )"
+
+
+\<comment> \<open>\<open>val int32Pred : int32 -> int32\<close>\<close>
+definition instance_Num_NumPred_Num_int32_dict :: "( 32 word)NumPred_class " where
+ " instance_Num_NumPred_Num_int32_dict = ((|
+
+ pred_method = (\<lambda> n. n -((word_of_int 1) :: 32 word))|) )"
+
+
+\<comment> \<open>\<open>val int32Mult : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Num_NumMult_Num_int32_dict :: "( 32 word)NumMult_class " where
+ " instance_Num_NumMult_Num_int32_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+
+\<comment> \<open>\<open>val int32Pow : int32 -> nat -> int32\<close>\<close>
+
+definition instance_Num_NumPow_Num_int32_dict :: "( 32 word)NumPow_class " where
+ " instance_Num_NumPow_Num_int32_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val int32Div : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_Num_int32_dict :: "( 32 word)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Num_int32_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_Num_int32_dict :: "( 32 word)NumDivision_class " where
+ " instance_Num_NumDivision_Num_int32_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val int32Mod : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Num_NumRemainder_Num_int32_dict :: "( 32 word)NumRemainder_class " where
+ " instance_Num_NumRemainder_Num_int32_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+\<comment> \<open>\<open>val int32Min : int32 -> int32 -> int32\<close>\<close>
+
+\<comment> \<open>\<open>val int32Max : int32 -> int32 -> int32\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_int32_dict :: "( 32 word)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_int32_dict = ((|
+
+ max_method = ((\<lambda> x y. if (word_sle y x) then x else y)),
+
+ min_method = ((\<lambda> x y. if (word_sle x y) then x else y))|) )"
+
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int64 \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open>val int64FromNumeral : numeral -> int64\<close>\<close>
+
+\<comment> \<open>\<open>val int64Eq : int64 -> int64 -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val int64Less : int64 -> int64 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int64LessEqual : int64 -> int64 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int64Greater : int64 -> int64 -> bool\<close>\<close>
+\<comment> \<open>\<open>val int64GreaterEqual : int64 -> int64 -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val int64Compare : int64 -> int64 -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_int64_dict :: "( 64 word)Ord_class " where
+ " instance_Basic_classes_Ord_Num_int64_dict = ((|
+
+ compare_method = (genericCompare word_sless (=)),
+
+ isLess_method = word_sless,
+
+ isLessEqual_method = word_sle,
+
+ isGreater_method = (\<lambda> x y. word_sless y x),
+
+ isGreaterEqual_method = (\<lambda> x y. word_sle y x)|) )"
+
+
+\<comment> \<open>\<open>val int64Negate : int64 -> int64\<close>\<close>
+
+definition instance_Num_NumNegate_Num_int64_dict :: "( 64 word)NumNegate_class " where
+ " instance_Num_NumNegate_Num_int64_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val int64Abs : int64 -> int64\<close>\<close>
+definition int64Abs :: " 64 word \<Rightarrow> 64 word " where
+ " int64Abs i = ( (if word_sle(((word_of_int 0) :: 64 word)) i then i else - i))"
+
+
+definition instance_Num_NumAbs_Num_int64_dict :: "( 64 word)NumAbs_class " where
+ " instance_Num_NumAbs_Num_int64_dict = ((|
+
+ abs_method = int64Abs |) )"
+
+
+
+\<comment> \<open>\<open>val int64Add : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Num_NumAdd_Num_int64_dict :: "( 64 word)NumAdd_class " where
+ " instance_Num_NumAdd_Num_int64_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val int64Minus : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Num_NumMinus_Num_int64_dict :: "( 64 word)NumMinus_class " where
+ " instance_Num_NumMinus_Num_int64_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val int64Succ : int64 -> int64\<close>\<close>
+
+definition instance_Num_NumSucc_Num_int64_dict :: "( 64 word)NumSucc_class " where
+ " instance_Num_NumSucc_Num_int64_dict = ((|
+
+ succ_method = (\<lambda> n. n +((word_of_int 1) :: 64 word))|) )"
+
+
+\<comment> \<open>\<open>val int64Pred : int64 -> int64\<close>\<close>
+definition instance_Num_NumPred_Num_int64_dict :: "( 64 word)NumPred_class " where
+ " instance_Num_NumPred_Num_int64_dict = ((|
+
+ pred_method = (\<lambda> n. n -((word_of_int 1) :: 64 word))|) )"
+
+
+\<comment> \<open>\<open>val int64Mult : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Num_NumMult_Num_int64_dict :: "( 64 word)NumMult_class " where
+ " instance_Num_NumMult_Num_int64_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+
+\<comment> \<open>\<open>val int64Pow : int64 -> nat -> int64\<close>\<close>
+
+definition instance_Num_NumPow_Num_int64_dict :: "( 64 word)NumPow_class " where
+ " instance_Num_NumPow_Num_int64_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val int64Div : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_Num_int64_dict :: "( 64 word)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Num_int64_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_Num_int64_dict :: "( 64 word)NumDivision_class " where
+ " instance_Num_NumDivision_Num_int64_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val int64Mod : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Num_NumRemainder_Num_int64_dict :: "( 64 word)NumRemainder_class " where
+ " instance_Num_NumRemainder_Num_int64_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+\<comment> \<open>\<open>val int64Min : int64 -> int64 -> int64\<close>\<close>
+
+\<comment> \<open>\<open>val int64Max : int64 -> int64 -> int64\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_int64_dict :: "( 64 word)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_int64_dict = ((|
+
+ max_method = ((\<lambda> x y. if (word_sle y x) then x else y)),
+
+ min_method = ((\<lambda> x y. if (word_sle x y) then x else y))|) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> integer \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val integerFromNumeral : numeral -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val integerFromNat : nat -> integer\<close>\<close> \<comment> \<open>\<open> TODO: check \<close>\<close>
+
+\<comment> \<open>\<open>val integerEq : integer -> integer -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val integerLess : integer -> integer -> bool\<close>\<close>
+\<comment> \<open>\<open>val integerLessEqual : integer -> integer -> bool\<close>\<close>
+\<comment> \<open>\<open>val integerGreater : integer -> integer -> bool\<close>\<close>
+\<comment> \<open>\<open>val integerGreaterEqual : integer -> integer -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val integerCompare : integer -> integer -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_integer_dict :: "(int)Ord_class " where
+ " instance_Basic_classes_Ord_Num_integer_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val integerNegate : integer -> integer\<close>\<close>
+
+definition instance_Num_NumNegate_Num_integer_dict :: "(int)NumNegate_class " where
+ " instance_Num_NumNegate_Num_integer_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val integerAbs : integer -> integer\<close>\<close> \<comment> \<open>\<open> TODO: check \<close>\<close>
+
+definition instance_Num_NumAbs_Num_integer_dict :: "(int)NumAbs_class " where
+ " instance_Num_NumAbs_Num_integer_dict = ((|
+
+ abs_method = abs |) )"
+
+
+\<comment> \<open>\<open>val integerAdd : integer -> integer -> integer\<close>\<close>
+
+definition instance_Num_NumAdd_Num_integer_dict :: "(int)NumAdd_class " where
+ " instance_Num_NumAdd_Num_integer_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val integerMinus : integer -> integer -> integer\<close>\<close>
+
+definition instance_Num_NumMinus_Num_integer_dict :: "(int)NumMinus_class " where
+ " instance_Num_NumMinus_Num_integer_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val integerSucc : integer -> integer\<close>\<close>
+definition instance_Num_NumSucc_Num_integer_dict :: "(int)NumSucc_class " where
+ " instance_Num_NumSucc_Num_integer_dict = ((|
+
+ succ_method = (\<lambda> n. n +( 1 :: int))|) )"
+
+
+\<comment> \<open>\<open>val integerPred : integer -> integer\<close>\<close>
+definition instance_Num_NumPred_Num_integer_dict :: "(int)NumPred_class " where
+ " instance_Num_NumPred_Num_integer_dict = ((|
+
+ pred_method = (\<lambda> n. n -( 1 :: int))|) )"
+
+
+\<comment> \<open>\<open>val integerMult : integer -> integer -> integer\<close>\<close>
+
+definition instance_Num_NumMult_Num_integer_dict :: "(int)NumMult_class " where
+ " instance_Num_NumMult_Num_integer_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+
+\<comment> \<open>\<open>val integerPow : integer -> nat -> integer\<close>\<close>
+
+definition instance_Num_NumPow_Num_integer_dict :: "(int)NumPow_class " where
+ " instance_Num_NumPow_Num_integer_dict = ((|
+
+ numPow_method = (^)|) )"
+
+
+\<comment> \<open>\<open>val integerDiv : integer -> integer -> integer\<close>\<close>
+
+definition instance_Num_NumIntegerDivision_Num_integer_dict :: "(int)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Num_integer_dict = ((|
+
+ div_method = (div)|) )"
+
+
+definition instance_Num_NumDivision_Num_integer_dict :: "(int)NumDivision_class " where
+ " instance_Num_NumDivision_Num_integer_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val integerMod : integer -> integer -> integer\<close>\<close>
+
+definition instance_Num_NumRemainder_Num_integer_dict :: "(int)NumRemainder_class " where
+ " instance_Num_NumRemainder_Num_integer_dict = ((|
+
+ mod_method = (mod)|) )"
+
+
+\<comment> \<open>\<open>val integerMin : integer -> integer -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val integerMax : integer -> integer -> integer\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_integer_dict :: "(int)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_integer_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> rational \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val rationalFromNumeral : numeral -> rational\<close>\<close>
+
+\<comment> \<open>\<open>val rationalFromInt : int -> rational\<close>\<close>
+
+\<comment> \<open>\<open>val rationalFromInteger : integer -> rational\<close>\<close>
+
+\<comment> \<open>\<open>val rationalEq : rational -> rational -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val rationalLess : rational -> rational -> bool\<close>\<close>
+\<comment> \<open>\<open>val rationalLessEqual : rational -> rational -> bool\<close>\<close>
+\<comment> \<open>\<open>val rationalGreater : rational -> rational -> bool\<close>\<close>
+\<comment> \<open>\<open>val rationalGreaterEqual : rational -> rational -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val rationalCompare : rational -> rational -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_rational_dict :: "(rat)Ord_class " where
+ " instance_Basic_classes_Ord_Num_rational_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val rationalAdd : rational -> rational -> rational\<close>\<close>
+
+definition instance_Num_NumAdd_Num_rational_dict :: "(rat)NumAdd_class " where
+ " instance_Num_NumAdd_Num_rational_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val rationalMinus : rational -> rational -> rational\<close>\<close>
+
+definition instance_Num_NumMinus_Num_rational_dict :: "(rat)NumMinus_class " where
+ " instance_Num_NumMinus_Num_rational_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val rationalNegate : rational -> rational\<close>\<close>
+
+definition instance_Num_NumNegate_Num_rational_dict :: "(rat)NumNegate_class " where
+ " instance_Num_NumNegate_Num_rational_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val rationalAbs : rational -> rational\<close>\<close>
+
+definition instance_Num_NumAbs_Num_rational_dict :: "(rat)NumAbs_class " where
+ " instance_Num_NumAbs_Num_rational_dict = ((|
+
+ abs_method = abs |) )"
+
+
+\<comment> \<open>\<open>val rationalSucc : rational -> rational\<close>\<close>
+definition instance_Num_NumSucc_Num_rational_dict :: "(rat)NumSucc_class " where
+ " instance_Num_NumSucc_Num_rational_dict = ((|
+
+ succ_method = (\<lambda> n. n +(Fract ( 1 :: int) (1 :: int)))|) )"
+
+
+\<comment> \<open>\<open>val rationalPred : rational -> rational\<close>\<close>
+definition instance_Num_NumPred_Num_rational_dict :: "(rat)NumPred_class " where
+ " instance_Num_NumPred_Num_rational_dict = ((|
+
+ pred_method = (\<lambda> n. n -(Fract ( 1 :: int) (1 :: int)))|) )"
+
+
+\<comment> \<open>\<open>val rationalMult : rational -> rational -> rational\<close>\<close>
+
+definition instance_Num_NumMult_Num_rational_dict :: "(rat)NumMult_class " where
+ " instance_Num_NumMult_Num_rational_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+\<comment> \<open>\<open>val rationalDiv : rational -> rational -> rational\<close>\<close>
+
+definition instance_Num_NumDivision_Num_rational_dict :: "(rat)NumDivision_class " where
+ " instance_Num_NumDivision_Num_rational_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val rationalFromFrac : int -> int -> rational\<close>\<close>
+\<comment> \<open>\<open>let rationalFromFrac n d= (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)\<close>\<close>
+
+\<comment> \<open>\<open>val rationalNumerator : rational -> integer\<close>\<close> \<comment> \<open>\<open> TODO: test \<close>\<close>
+
+\<comment> \<open>\<open>val rationalDenominator : rational -> integer\<close>\<close> \<comment> \<open>\<open> TODO: test \<close>\<close>
+
+\<comment> \<open>\<open>val rationalPowInteger : rational -> integer -> rational\<close>\<close>
+fun rationalPowInteger :: " rat \<Rightarrow> int \<Rightarrow> rat " where
+ " rationalPowInteger b e = (
+ if e =( 0 :: int) then(Fract ( 1 :: int) (1 :: int)) else
+ if e >( 0 :: int) then rationalPowInteger b (e -( 1 :: int)) * b else
+ rationalPowInteger b (e +( 1 :: int)) div b )"
+
+
+\<comment> \<open>\<open>val rationalPowNat : rational -> nat -> rational\<close>\<close>
+\<comment> \<open>\<open>let rationalPowNat r e= rationalPowInteger r (integerFromNat e)\<close>\<close>
+
+definition instance_Num_NumPow_Num_rational_dict :: "(rat)NumPow_class " where
+ " instance_Num_NumPow_Num_rational_dict = ((|
+
+ numPow_method = power |) )"
+
+
+\<comment> \<open>\<open>val rationalMin : rational -> rational -> rational\<close>\<close>
+
+\<comment> \<open>\<open>val rationalMax : rational -> rational -> rational\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_rational_dict :: "(rat)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_rational_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> real \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val realFromNumeral : numeral -> real\<close>\<close>
+
+\<comment> \<open>\<open>val realFromInteger : integer -> real\<close>\<close>
+
+\<comment> \<open>\<open>val realEq : real -> real -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val realLess : real -> real -> bool\<close>\<close>
+\<comment> \<open>\<open>val realLessEqual : real -> real -> bool\<close>\<close>
+\<comment> \<open>\<open>val realGreater : real -> real -> bool\<close>\<close>
+\<comment> \<open>\<open>val realGreaterEqual : real -> real -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val realCompare : real -> real -> ordering\<close>\<close>
+
+definition instance_Basic_classes_Ord_Num_real_dict :: "(real)Ord_class " where
+ " instance_Basic_classes_Ord_Num_real_dict = ((|
+
+ compare_method = (genericCompare (<) (=)),
+
+ isLess_method = (<),
+
+ isLessEqual_method = (\<le>),
+
+ isGreater_method = (>),
+
+ isGreaterEqual_method = (\<ge>)|) )"
+
+
+\<comment> \<open>\<open>val realAdd : real -> real -> real\<close>\<close>
+
+definition instance_Num_NumAdd_Num_real_dict :: "(real)NumAdd_class " where
+ " instance_Num_NumAdd_Num_real_dict = ((|
+
+ numAdd_method = (+)|) )"
+
+
+\<comment> \<open>\<open>val realMinus : real -> real -> real\<close>\<close>
+
+definition instance_Num_NumMinus_Num_real_dict :: "(real)NumMinus_class " where
+ " instance_Num_NumMinus_Num_real_dict = ((|
+
+ numMinus_method = (-)|) )"
+
+
+\<comment> \<open>\<open>val realNegate : real -> real\<close>\<close>
+
+definition instance_Num_NumNegate_Num_real_dict :: "(real)NumNegate_class " where
+ " instance_Num_NumNegate_Num_real_dict = ((|
+
+ numNegate_method = (\<lambda> i. - i)|) )"
+
+
+\<comment> \<open>\<open>val realAbs : real -> real\<close>\<close>
+
+definition instance_Num_NumAbs_Num_real_dict :: "(real)NumAbs_class " where
+ " instance_Num_NumAbs_Num_real_dict = ((|
+
+ abs_method = abs |) )"
+
+
+\<comment> \<open>\<open>val realSucc : real -> real\<close>\<close>
+definition instance_Num_NumSucc_Num_real_dict :: "(real)NumSucc_class " where
+ " instance_Num_NumSucc_Num_real_dict = ((|
+
+ succ_method = (\<lambda> n. n +( 1 :: real))|) )"
+
+
+\<comment> \<open>\<open>val realPred : real -> real\<close>\<close>
+definition instance_Num_NumPred_Num_real_dict :: "(real)NumPred_class " where
+ " instance_Num_NumPred_Num_real_dict = ((|
+
+ pred_method = (\<lambda> n. n -( 1 :: real))|) )"
+
+
+\<comment> \<open>\<open>val realMult : real -> real -> real\<close>\<close>
+
+definition instance_Num_NumMult_Num_real_dict :: "(real)NumMult_class " where
+ " instance_Num_NumMult_Num_real_dict = ((|
+
+ numMult_method = ( * )|) )"
+
+
+\<comment> \<open>\<open>val realDiv : real -> real -> real\<close>\<close>
+
+definition instance_Num_NumDivision_Num_real_dict :: "(real)NumDivision_class " where
+ " instance_Num_NumDivision_Num_real_dict = ((|
+
+ numDivision_method = (div)|) )"
+
+
+\<comment> \<open>\<open>val realFromFrac : integer -> integer -> real\<close>\<close>
+definition realFromFrac :: " int \<Rightarrow> int \<Rightarrow> real " where
+ " realFromFrac n d = ( ((real_of_int n)) div ((real_of_int d)))"
+
+
+\<comment> \<open>\<open>val realPowInteger : real -> integer -> real\<close>\<close>
+fun realPowInteger :: " real \<Rightarrow> int \<Rightarrow> real " where
+ " realPowInteger b e = (
+ if e =( 0 :: int) then( 1 :: real) else
+ if e >( 0 :: int) then realPowInteger b (e -( 1 :: int)) * b else
+ realPowInteger b (e +( 1 :: int)) div b )"
+
+
+\<comment> \<open>\<open>val realPowNat : real -> nat -> real\<close>\<close>
+\<comment> \<open>\<open>let realPowNat r e= realPowInteger r (integerFromNat e)\<close>\<close>
+
+definition instance_Num_NumPow_Num_real_dict :: "(real)NumPow_class " where
+ " instance_Num_NumPow_Num_real_dict = ((|
+
+ numPow_method = power |) )"
+
+
+\<comment> \<open>\<open>val realSqrt : real -> real\<close>\<close>
+
+\<comment> \<open>\<open>val realMin : real -> real -> real\<close>\<close>
+
+\<comment> \<open>\<open>val realMax : real -> real -> real\<close>\<close>
+
+definition instance_Basic_classes_OrdMaxMin_Num_real_dict :: "(real)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Num_real_dict = ((|
+
+ max_method = max,
+
+ min_method = min |) )"
+
+
+\<comment> \<open>\<open>val realCeiling : real -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val realFloor : real -> integer\<close>\<close>
+
+
+\<comment> \<open>\<open>val integerSqrt : integer -> integer\<close>\<close>
+definition integerSqrt :: " int \<Rightarrow> int " where
+ " integerSqrt i = ( floor (sqrt ((real_of_int i))))"
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Translation between number types \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> integerFrom... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val integerFromInt : int -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val integerFromNatural : natural -> integer\<close>\<close>
+
+
+\<comment> \<open>\<open>val integerFromInt32 : int32 -> integer\<close>\<close>
+
+
+\<comment> \<open>\<open>val integerFromInt64 : int64 -> integer\<close>\<close>
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> naturalFrom... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromNat : nat -> natural\<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromInteger : integer -> natural\<close>\<close>
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> intFrom ... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val intFromInteger : integer -> int\<close>\<close>
+
+\<comment> \<open>\<open>val intFromNat : nat -> int\<close>\<close>
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> natFrom ... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val natFromNatural : natural -> nat\<close>\<close>
+
+\<comment> \<open>\<open>val natFromInt : int -> nat\<close>\<close>
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> int32From ... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val int32FromNat : nat -> int32\<close>\<close>
+
+\<comment> \<open>\<open>val int32FromNatural : natural -> int32\<close>\<close>
+
+\<comment> \<open>\<open>val int32FromInteger : integer -> int32\<close>\<close>
+\<comment> \<open>\<open>let int32FromInteger i= (
+ let abs_int32 = int32FromNatural (naturalFromInteger i) in
+ if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int32.~ abs_int32) else abs_int32
+)\<close>\<close>
+
+\<comment> \<open>\<open>val int32FromInt : int -> int32\<close>\<close>
+\<comment> \<open>\<open>let int32FromInt i= int32FromInteger (integerFromInt i)\<close>\<close>
+
+
+\<comment> \<open>\<open>val int32FromInt64 : int64 -> int32\<close>\<close>
+\<comment> \<open>\<open>let int32FromInt64 i= int32FromInteger (integerFromInt64 i)\<close>\<close>
+
+
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> int64From ... \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val int64FromNat : nat -> int64\<close>\<close>
+
+\<comment> \<open>\<open>val int64FromNatural : natural -> int64\<close>\<close>
+
+\<comment> \<open>\<open>val int64FromInteger : integer -> int64\<close>\<close>
+\<comment> \<open>\<open>let int64FromInteger i= (
+ let abs_int64 = int64FromNatural (naturalFromInteger i) in
+ if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int64.~ abs_int64) else abs_int64
+)\<close>\<close>
+
+\<comment> \<open>\<open>val int64FromInt : int -> int64\<close>\<close>
+\<comment> \<open>\<open>let int64FromInt i= int64FromInteger (integerFromInt i)\<close>\<close>
+
+
+\<comment> \<open>\<open>val int64FromInt32 : int32 -> int64\<close>\<close>
+\<comment> \<open>\<open>let int64FromInt32 i= int64FromInteger (integerFromInt32 i)\<close>\<close>
+
+
+\<comment> \<open>\<open>****************\<close>\<close>
+\<comment> \<open>\<open> what's missing \<close>\<close>
+\<comment> \<open>\<open>****************\<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromInt : int -> natural\<close>\<close>
+\<comment> \<open>\<open>val naturalFromInt32 : int32 -> natural\<close>\<close>
+\<comment> \<open>\<open>val naturalFromInt64 : int64 -> natural\<close>\<close>
+
+
+\<comment> \<open>\<open>val intFromNatural : natural -> int\<close>\<close>
+\<comment> \<open>\<open>val intFromInt32 : int32 -> int\<close>\<close>
+\<comment> \<open>\<open>val intFromInt64 : int64 -> int\<close>\<close>
+
+\<comment> \<open>\<open>val natFromInteger : integer -> nat\<close>\<close>
+\<comment> \<open>\<open>val natFromInt32 : int32 -> nat\<close>\<close>
+\<comment> \<open>\<open>val natFromInt64 : int64 -> nat\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_num_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_num_extra.thy
new file mode 100644
index 0000000..f6ac64a
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_num_extra.thy
@@ -0,0 +1,34 @@
+chapter \<open>Generated by Lem from \<open>num_extra.lem\<close>.\<close>
+
+theory "Lem_num_extra"
+
+imports
+ Main
+ "Lem_num"
+ "Lem_string"
+
+begin
+
+\<comment> \<open>\<open> **************************************************** \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> A library of additional functions on numbers \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> **************************************************** \<close>\<close>
+
+\<comment> \<open>\<open>open import Num\<close>\<close>
+\<comment> \<open>\<open>open import String\<close>\<close>
+
+\<comment> \<open>\<open>val naturalOfString : string -> natural\<close>\<close>
+
+\<comment> \<open>\<open>val integerOfString : string -> integer\<close>\<close>
+
+
+\<comment> \<open>\<open> Truncation integer division (round toward zero) \<close>\<close>
+\<comment> \<open>\<open>val integerDiv_t: integer -> integer -> integer\<close>\<close>
+
+\<comment> \<open>\<open> Truncation modulo \<close>\<close>
+\<comment> \<open>\<open>val integerRem_t: integer -> integer -> integer\<close>\<close>
+
+\<comment> \<open>\<open> Flooring modulo \<close>\<close>
+\<comment> \<open>\<open>val integerRem_f: integer -> integer -> integer\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_pervasives.thy b/prover_snapshots/isabelle/lib/lem/Lem_pervasives.thy
new file mode 100644
index 0000000..a7306bf
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_pervasives.thy
@@ -0,0 +1,31 @@
+chapter \<open>Generated by Lem from \<open>pervasives.lem\<close>.\<close>
+
+theory "Lem_pervasives"
+
+imports
+ Main
+ "Lem_basic_classes"
+ "Lem_bool"
+ "Lem_tuple"
+ "Lem_maybe"
+ "Lem_either"
+ "Lem_function"
+ "Lem_num"
+ "Lem_map"
+ "Lem_set"
+ "Lem_list"
+ "Lem_string"
+ "Lem_word"
+ "Lem_show"
+ "Lem_sorting"
+ "Lem_relation"
+
+begin
+
+
+
+\<comment> \<open>\<open>include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show\<close>\<close>
+
+\<comment> \<open>\<open>import Sorting Relation\<close>\<close>
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy
new file mode 100644
index 0000000..1da5043
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy
@@ -0,0 +1,26 @@
+chapter \<open>Generated by Lem from \<open>pervasives_extra.lem\<close>.\<close>
+
+theory "Lem_pervasives_extra"
+
+imports
+ Main
+ "Lem_pervasives"
+ "Lem_function_extra"
+ "Lem_maybe_extra"
+ "Lem_map_extra"
+ "Lem_num_extra"
+ "Lem_set_extra"
+ "Lem_set_helpers"
+ "Lem_list_extra"
+ "Lem_string_extra"
+ "Lem_assert_extra"
+ "Lem_show_extra"
+ "Lem_machine_word"
+
+begin
+
+
+
+\<comment> \<open>\<open>include import Pervasives\<close>\<close>
+\<comment> \<open>\<open>include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_relation.thy b/prover_snapshots/isabelle/lib/lem/Lem_relation.thy
new file mode 100644
index 0000000..2f21e59
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_relation.thy
@@ -0,0 +1,449 @@
+chapter \<open>Generated by Lem from \<open>relation.lem\<close>.\<close>
+
+theory "Lem_relation"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_tuple"
+ "Lem_set"
+ "Lem_num"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes Tuple Set Num\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `set_relationTheory`\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> The type of relations \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+type_synonym( 'a, 'b) rel_pred =" 'a \<Rightarrow> 'b \<Rightarrow> bool "
+type_synonym( 'a, 'b) rel_set =" ('a * 'b) set "
+
+\<comment> \<open>\<open> Binary relations are usually represented as either
+ sets of pairs (rel_set) or as curried functions (rel_pred).
+
+ The choice depends on taste and the backend. Lem should not take a
+ decision, but supports both representations. There is an abstract type
+ pred, which can be converted to both representations. The representation
+ of pred itself then depends on the backend. However, for the time beeing,
+ let's implement relations as sets to get them working more quickly. \<close>\<close>
+
+type_synonym( 'a, 'b) rel =" ('a, 'b) rel_set "
+
+\<comment> \<open>\<open>val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b\<close>\<close>
+\<comment> \<open>\<open>val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b\<close>\<close>
+
+\<comment> \<open>\<open>val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool\<close>\<close>
+definition relEq :: "('a*'b)set \<Rightarrow>('a*'b)set \<Rightarrow> bool " where
+ " relEq r1 r2 = ( (r1 = r2))"
+
+
+\<comment> \<open>\<open>val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b\<close>\<close>
+\<comment> \<open>\<open>val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b\<close>\<close>
+
+definition relToPred :: "('a*'b)set \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow> bool " where
+ " relToPred r = ( (\<lambda> x y . (x, y) \<in> r))"
+
+definition relFromPred :: " 'a set \<Rightarrow> 'b set \<Rightarrow>('a \<Rightarrow> 'b \<Rightarrow> bool)\<Rightarrow>('a*'b)set " where
+ " relFromPred xs ys p = ( set_filter ( \<lambda>x .
+ (case x of (x,y) => p x y )) (xs \<times> ys))"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Basic Operations \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> membership test \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> empty relation \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Insertion \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Identity relation \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a\<close>\<close>
+definition relIdOn :: " 'a set \<Rightarrow>('a*'a)set " where
+ " relIdOn s = ( relFromPred s s (=))"
+
+
+\<comment> \<open>\<open>val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> relation union \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> relation intersection \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Relation Composition \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c\<close>\<close>
+\<comment> \<open>\<open>let relComp r1 r2= relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> restrict \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a\<close>\<close>
+definition relRestrict :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow>('a*'a)set " where
+ " relRestrict r s = ( ((let x2 =
+ ({}) in Finite_Set.fold
+ (\<lambda>a x2 . Finite_Set.fold
+ (\<lambda>b x2 .
+ if (a, b) \<in> r then Set.insert (a, b) x2 else x2)
+ x2 s) x2 s)))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Converse \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a\<close>\<close>
+\<comment> \<open>\<open>let relConverse r= relFromSet (Set.map swap (relToSet r))\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> domain \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a\<close>\<close>
+\<comment> \<open>\<open>let relDomain r= Set.map (fun x -> fst x) (relToSet r)\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> range \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b\<close>\<close>
+\<comment> \<open>\<open>let relRange r= Set.map (fun x -> snd x) (relToSet r)\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> field / definedOn \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> avoid the keyword field \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> relOver \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> avoid the keyword field \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition relOver :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " relOver r s = ( ((((Domain r) \<union> (Range r))) \<subseteq> s))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> apply a relation \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> Given a relation r and a set s, relApply r s applies s to r, i.e.
+ it returns the set of all value reachable via r from a value in s.
+ This operation can be seen as a generalisation of function application. \<close>\<close>
+
+\<comment> \<open>\<open>val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b\<close>\<close>
+\<comment> \<open>\<open>let relApply r s= { y | forall ((x, y) IN (relToSet r)) | x IN s }\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Properties \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> subrel \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> reflexivity \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isReflexiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isReflexiveOn r s = ( ((\<forall> e \<in> s. (e, e) \<in> r)))"
+
+
+\<comment> \<open>\<open>val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let ~{ocaml;coq} isReflexive r= (forall e. inRel e e r)\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> irreflexivity \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isIrreflexiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isIrreflexiveOn r s = ( ((\<forall> e \<in> s. \<not> ((e, e) \<in> r))))"
+
+
+\<comment> \<open>\<open>val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isIrreflexive r= (forall ((e1, e2) IN (relToSet r)). not (e1 = e2))\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> symmetry \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isSymmetricOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isSymmetricOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> ((e2, e1) \<in> r))))"
+
+
+\<comment> \<open>\<open>val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isSymmetric r= (forall ((e1, e2) IN relToSet r). inRel e2 e1 r)\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> antisymmetry \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isAntisymmetricOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isAntisymmetricOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> (((e2, e1) \<in> r) \<longrightarrow> (e1 = e2)))))"
+
+
+\<comment> \<open>\<open>val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isAntisymmetric r= (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> transitivity \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isTransitiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isTransitiveOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. \<forall> e3 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> (((e2, e3) \<in> r) \<longrightarrow> ((e1, e3) \<in> r)))))"
+
+
+\<comment> \<open>\<open>val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let isTransitive r= (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> total \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isTotalOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isTotalOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<or> ((e2, e1) \<in> r))))"
+
+
+
+\<comment> \<open>\<open>val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>let ~{ocaml;coq} isTotal r= (forall e1 e2. (inRel e1 e2 r) || (inRel e2 e1 r))\<close>\<close>
+
+\<comment> \<open>\<open>val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isTrichotomousOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isTrichotomousOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<or> ((e1 = e2) \<or> ((e2, e1) \<in> r)))))"
+
+
+\<comment> \<open>\<open>val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isTrichotomous :: "('a*'a)set \<Rightarrow> bool " where
+ " isTrichotomous r = ( ((\<forall> e1. \<forall> e2. ((e1, e2) \<in> r) \<or> ((e1 = e2) \<or> ((e2, e1) \<in> r)))))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> is_single_valued \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool\<close>\<close>
+definition isSingleValued :: "('a*'b)set \<Rightarrow> bool " where
+ " isSingleValued r = ( ((\<forall> (e1, e2a) \<in> r. \<forall> e2b \<in> Image r {e1}. e2a = e2b)))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> equivalence relation \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isEquivalenceOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isEquivalenceOn r s = ( isReflexiveOn r s \<and> (isSymmetricOn r s \<and> isTransitiveOn r s))"
+
+
+
+\<comment> \<open>\<open>val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isEquivalence :: "('a*'a)set \<Rightarrow> bool " where
+ " isEquivalence r = ( refl r \<and> (sym r \<and> trans r))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> well founded \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isWellFounded :: "('a*'a)set \<Rightarrow> bool " where
+ " isWellFounded r = ( ((\<forall> P. ((\<forall> x. ((\<forall> y. ((y, x) \<in> r) \<longrightarrow> P x)) \<longrightarrow> P x)) \<longrightarrow> ((\<forall> x. P x)))))"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Orders \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> pre- or quasiorders \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isPreorderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isPreorderOn r s = ( isReflexiveOn r s \<and> isTransitiveOn r s )"
+
+
+\<comment> \<open>\<open>val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isPreorder :: "('a*'a)set \<Rightarrow> bool " where
+ " isPreorder r = ( refl r \<and> trans r )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> partial orders \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isPartialOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isPartialOrderOn r s = ( isReflexiveOn r s \<and> (isTransitiveOn r s \<and> isAntisymmetricOn r s))"
+
+
+
+\<comment> \<open>\<open>val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isStrictPartialOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isStrictPartialOrderOn r s = ( isIrreflexiveOn r s \<and> isTransitiveOn r s )"
+
+
+
+\<comment> \<open>\<open>val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isStrictPartialOrder :: "('a*'a)set \<Rightarrow> bool " where
+ " isStrictPartialOrder r = ( irrefl r \<and> trans r )"
+
+
+\<comment> \<open>\<open>val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isPartialOrder :: "('a*'a)set \<Rightarrow> bool " where
+ " isPartialOrder r = ( refl r \<and> (trans r \<and> antisym r))"
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> total / linear orders \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isTotalOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isTotalOrderOn r s = ( isPartialOrderOn r s \<and> isTotalOn r s )"
+
+
+\<comment> \<open>\<open>val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool\<close>\<close>
+definition isStrictTotalOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where
+ " isStrictTotalOrderOn r s = ( isStrictPartialOrderOn r s \<and> isTrichotomousOn r s )"
+
+
+\<comment> \<open>\<open>val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isTotalOrder :: "('a*'a)set \<Rightarrow> bool " where
+ " isTotalOrder r = ( isPartialOrder r \<and> total r )"
+
+
+\<comment> \<open>\<open>val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool\<close>\<close>
+definition isStrictTotalOrder :: "('a*'a)set \<Rightarrow> bool " where
+ " isStrictTotalOrder r = ( isStrictPartialOrder r \<and> isTrichotomous r )"
+
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> closures \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> transitive closure \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a\<close>\<close>
+\<comment> \<open>\<open>val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a\<close>\<close>
+\<comment> \<open>\<open>val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> ordering) -> rel 'a 'a -> rel 'a 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> transitive closure step \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a\<close>\<close>
+
+definition transitiveClosureAdd :: " 'a \<Rightarrow> 'a \<Rightarrow>('a*'a)set \<Rightarrow>('a*'a)set " where
+ " transitiveClosureAdd x y r = (
+ (((((Set.insert (x,y) (r)))) \<union> ((((((let x2 =
+ ({}) in Finite_Set.fold
+ (\<lambda>z x2 . if (y, z) \<in> r then Set.insert (x, z) x2 else x2)
+ x2 (Range r)))) \<union> (((let x2 =
+ ({}) in Finite_Set.fold
+ (\<lambda>z x2 . if (z, x) \<in> r then Set.insert (z, y) x2 else x2)
+ x2 (Domain r))))))))))"
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> reflexive closure \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a\<close>\<close>
+definition reflexiveTransitiveClosureOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow>('a*'a)set " where
+ " reflexiveTransitiveClosureOn r s = ( trancl (((r) \<union> ((relIdOn s)))))"
+
+
+
+\<comment> \<open>\<open>val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a\<close>\<close>
+definition reflexiveTransitiveClosure :: "('a*'a)set \<Rightarrow>('a*'a)set " where
+ " reflexiveTransitiveClosure r = ( trancl (((r) \<union> (Id))))"
+
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> inverse of closures \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> without transitve edges \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a\<close>\<close>
+\<comment> \<open>\<open>let withoutTransitiveEdges r=
+ let tc = transitiveClosure r in
+ {(a, c) | forall ((a, c) IN r)
+ | forall (b IN relRange r). a <> b && b <> c --> not ((a, b) IN tc && (b, c) IN tc)}\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_set.thy b/prover_snapshots/isabelle/lib/lem/Lem_set.thy
new file mode 100644
index 0000000..9302b92
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_set.thy
@@ -0,0 +1,325 @@
+chapter \<open>Generated by Lem from \<open>set.lem\<close>.\<close>
+
+theory "Lem_set"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_maybe"
+ "Lem_function"
+ "Lem_num"
+ "Lem_list"
+ "Lem_set_helpers"
+ "Lem"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> A library for sets \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> It mainly follows the Haskell Set-library \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open> Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets.
+ OCaml and Haskell both represent sets by some kind of balancing trees. This means
+ that sets are finite and an order on the element type is required.
+ Such sets are constructed by simple, executable operations like inserting or
+ deleting elements, union, intersection, filtering etc.
+
+ On the other hand, we want to use sets for specifications. This leads often
+ infinite sets, which are specificied in complicated, perhaps even undecidable
+ ways.
+
+ The set library in this file, chooses the first approach. It describes
+ *finite* sets with an underlying order. Infinite sets should in the medium
+ run be represented by a separate type. Since this would require some significant
+ changes to Lem, for the moment also infinite sets are represented using this
+ class. However, a run-time exception might occour when using these sets.
+ This problem needs adressing in the future. \<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Header \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>open import Bool Basic_classes Maybe Function Num List Set_helpers\<close>\<close>
+
+\<comment> \<open>\<open> DPM: sets currently implemented as lists due to mismatch between Coq type
+ * class hierarchy and the hierarchy implemented in Lem.
+ \<close>\<close>
+\<comment> \<open>\<open>open import {coq} `Coq.Lists.List`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `lemTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `$LIB_DIR/Lem`\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Equality check \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val setEqualBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Empty set \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val empty : forall 'a. SetType 'a => set 'a\<close>\<close>
+\<comment> \<open>\<open>val emptyBy : forall 'a. ('a -> 'a -> ordering) -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> any / all \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> (IN) \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val memberBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> not (IN) \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool\<close>\<close>
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Emptyness check \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val null : forall 'a. SetType 'a => set 'a -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> singleton \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val singletonBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val singleton : forall 'a. SetType 'a => 'a -> set 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> size \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val size : forall 'a. SetType 'a => set 'a -> nat\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> setting up pattern matching \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> union \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val unionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> insert \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> filter \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>let filter P s= {e | forall (e IN s) | P e}\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> partition \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a\<close>\<close>
+definition partition :: "('a \<Rightarrow> bool)\<Rightarrow> 'a set \<Rightarrow> 'a set*'a set " where
+ " partition P s = ( (set_filter P s, set_filter (\<lambda> e . \<not> (P e)) s))"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> split \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a\<close>\<close>
+definition split :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a set \<Rightarrow> 'a set*'a set " where
+ " split dict_Basic_classes_Ord_a p s = ( (set_filter (
+ (isGreater_method dict_Basic_classes_Ord_a) p) s, set_filter ((isLess_method dict_Basic_classes_Ord_a) p) s))"
+
+
+\<comment> \<open>\<open>val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a\<close>\<close>
+definition splitMember :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a set \<Rightarrow> 'a set*bool*'a set " where
+ " splitMember dict_Basic_classes_Ord_a p s = ( (set_filter (
+ (isLess_method dict_Basic_classes_Ord_a) p) s, (p \<in> s), set_filter (
+ (isGreater_method dict_Basic_classes_Ord_a) p) s))"
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> subset and proper subset \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val isSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val isProperSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> delete \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> bigunion \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val bigunionBy : forall 'a. ('a -> 'a -> ordering) -> set (set 'a) -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open>let bigunion bs= {x | forall (s IN bs) (x IN s) | true}\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> big intersection \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open> Shaked's addition, for which he is now forever responsible as a de facto
+ * Lem maintainer...
+ \<close>\<close>
+\<comment> \<open>\<open>val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a\<close>\<close>
+definition bigintersection :: "('a set)set \<Rightarrow> 'a set " where
+ " bigintersection bs = ( (let x2 =
+ ({}) in Finite_Set.fold
+ (\<lambda>x x2 .
+ if( \<forall> s \<in> bs. x \<in> s) then Set.insert x x2 else x2)
+ x2 (\<Union> bs)))"
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> difference \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val differenceBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> intersection \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>val intersectionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> map \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b\<close>\<close> \<comment> \<open>\<open> before image \<close>\<close>
+\<comment> \<open>\<open>let map f s= { f e | forall (e IN s) | true }\<close>\<close>
+
+\<comment> \<open>\<open>val mapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> 'b) -> set 'a -> set 'b\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> bigunionMap \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open> In order to avoid providing an comparison function for sets of sets,
+ it might be better to combine bigunion and map sometimes into a single operation. \<close>\<close>
+
+\<comment> \<open>\<open>val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b\<close>\<close>
+\<comment> \<open>\<open>val bigunionMapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> set 'b) -> set 'a -> set 'b\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> mapMaybe and fromMaybe \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open> If the mapping function returns Just x, x is added to the result
+ set. If it returns Nothing, no element is added. \<close>\<close>
+
+\<comment> \<open>\<open>val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> maybe 'b) -> set 'a -> set 'b\<close>\<close>
+definition setMapMaybe :: "('a \<Rightarrow> 'b option)\<Rightarrow> 'a set \<Rightarrow> 'b set " where
+ " setMapMaybe f s = (
+ \<Union> (Set.image (\<lambda> x . (case f x of
+ Some y => {y}
+ | None => {}
+ )) s))"
+
+
+\<comment> \<open>\<open>val removeMaybe : forall 'a. SetType 'a => set (maybe 'a) -> set 'a\<close>\<close>
+definition removeMaybe :: "('a option)set \<Rightarrow> 'a set " where
+ " removeMaybe s = ( setMapMaybe (\<lambda> x . x) s )"
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> min and max \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a\<close>\<close>
+\<comment> \<open>\<open>val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> fromList \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val fromList : forall 'a. SetType 'a => list 'a -> set 'a\<close>\<close> \<comment> \<open>\<open> before from_list \<close>\<close>
+\<comment> \<open>\<open>val fromListBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> set 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> Sigma \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)\<close>\<close>
+\<comment> \<open>\<open>val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)\<close>\<close>
+
+\<comment> \<open>\<open>let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> cross product \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)\<close>\<close>
+\<comment> \<open>\<open>val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> set 'b -> set ('a * 'b)\<close>\<close>
+
+\<comment> \<open>\<open>let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }\<close>\<close>
+
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> finite \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open>val finite : forall 'a. SetType 'a => set 'a -> bool\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> fixed point \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val leastFixedPoint : forall 'a. SetType 'a
+ => nat -> (set 'a -> set 'a) -> set 'a -> set 'a\<close>\<close>
+fun leastFixedPoint :: " nat \<Rightarrow>('a set \<Rightarrow> 'a set)\<Rightarrow> 'a set \<Rightarrow> 'a set " where
+ " leastFixedPoint 0 f x = ( x )"
+|" leastFixedPoint ((Suc bound')) f x = ( (let fx = (f x) in
+ if fx \<subseteq> x then x
+ else leastFixedPoint bound' f (fx \<union> x)))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_set_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_set_extra.thy
new file mode 100644
index 0000000..50ed89a
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_set_extra.thy
@@ -0,0 +1,121 @@
+chapter \<open>Generated by Lem from \<open>set_extra.lem\<close>.\<close>
+
+theory "Lem_set_extra"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_maybe"
+ "Lem_function"
+ "Lem_num"
+ "Lem_list"
+ "Lem_sorting"
+ "Lem_set"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> A library for sets \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> It mainly follows the Haskell Set-library \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Header \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>open import Bool Basic_classes Maybe Function Num List Sorting Set\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> set choose (be careful !) \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val choose : forall 'a. SetType 'a => set 'a -> 'a\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> chooseAndSplit \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> The idea here is to provide a simple primitive that Lem code can use
+ * to perform its own custom searches within the set -- likely using a
+ * search criterion related to the element ordering, but not necessarily).
+ * For example, sometimes we don't necessarily want to search for a specific
+ * element, but want to search for elements greater than or less than some other.
+ * Someties we'd like to use "split" but don't know a good value to "split" at.
+ * This function lets the set implementation decide that value.
+ *
+ * The contract of chooseAndSplit is simply to select an element nondeterministically
+ * and return that element, together with the subsets of elements less than and
+ * greater than it. In this way, we can recursively traverse the set with any
+ * search criterion, and we avoid baking in the tree representation (although that
+ * is the obvious choice).
+ \<close>\<close>
+\<comment> \<open>\<open>val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> maybe (set 'a * 'a * set 'a)\<close>\<close>
+definition chooseAndSplit :: " 'a Ord_class \<Rightarrow> 'a set \<Rightarrow>('a set*'a*'a set)option " where
+ " chooseAndSplit dict_Basic_classes_Ord_a s = (
+ if s = {} then
+ None
+ else
+ (let element = (set_choose s) in
+ (let (lt, gt) = (Lem_set.split
+ dict_Basic_classes_Ord_a element s) in
+ Some (lt, element, gt))))"
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> universal set \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val universal : forall 'a. SetType 'a => set 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> toList \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val toList : forall 'a. SetType 'a => set 'a -> list 'a\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> toOrderedList \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> "toOrderedList" returns a sorted list. Therefore the result is (given a suitable order) deterministic.
+ Therefore, it is much preferred to "toList". However, it still is only defined for finite sets. So, please
+ use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations
+ and then transforming back to sets. \<close>\<close>
+
+\<comment> \<open>\<open>val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a\<close>\<close>
+
+\<comment> \<open>\<open>val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> compare \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val setCompareBy: forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> ordering\<close>\<close>
+definition setCompareBy :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a set \<Rightarrow> 'a set \<Rightarrow> ordering " where
+ " setCompareBy cmp ss ts = (
+ (let ss' = (ordered_list_of_set (\<lambda> x y . cmp x y = LT) ss) in
+ (let ts' = (ordered_list_of_set (\<lambda> x y . cmp x y = LT) ts) in
+ lexicographicCompareBy cmp ss' ts')))"
+
+
+\<comment> \<open>\<open>val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> ordering\<close>\<close>
+definition setCompare :: " 'a Ord_class \<Rightarrow> 'a set \<Rightarrow> 'a set \<Rightarrow> ordering " where
+ " setCompare dict_Basic_classes_Ord_a = ( setCompareBy
+ (compare_method dict_Basic_classes_Ord_a) )"
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> unbounded fixed point \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> Is NOT supported by the coq backend! \<close>\<close>
+\<comment> \<open>\<open>val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a\<close>\<close>
+\<comment> \<open>\<open>let rec leastFixedPointUnbounded f x=
+ let fx = f x in
+ if fx subset x then x
+ else leastFixedPointUnbounded f (fx union x)\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_set_helpers.thy b/prover_snapshots/isabelle/lib/lem/Lem_set_helpers.thy
new file mode 100644
index 0000000..d48f217
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_set_helpers.thy
@@ -0,0 +1,50 @@
+chapter \<open>Generated by Lem from \<open>set_helpers.lem\<close>.\<close>
+
+theory "Lem_set_helpers"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_maybe"
+ "Lem_function"
+ "Lem_num"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> Helper functions for sets \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open> Usually there is a something.lem file containing the main definitions and a
+ something_extra.lem one containing functions that might cause problems for
+ some backends or are just seldomly used.
+
+ For sets the situation is different. folding is not well defined, since it
+ is only sensibly defined for finite sets and the traversal
+ order is underspecified. \<close>\<close>
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Header \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+\<comment> \<open>\<open>open import Bool Basic_classes Maybe Function Num\<close>\<close>
+
+\<comment> \<open>\<open>open import {coq} `Coq.Lists.List`\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+\<comment> \<open>\<open> fold \<close>\<close>
+\<comment> \<open>\<open> ------------------------ \<close>\<close>
+
+\<comment> \<open>\<open> fold is suspicious, because if given a function, for which
+ the order, in which the arguments are given, matters, its
+ results are undefined. On the other hand, it is very handy to
+ define other - non suspicious functions.
+
+ Moreover, fold is central for OCaml, since it is used to
+ compile set comprehensions \<close>\<close>
+
+\<comment> \<open>\<open>val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b\<close>\<close>
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_show.thy b/prover_snapshots/isabelle/lib/lem/Lem_show.thy
new file mode 100644
index 0000000..1469dc6
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_show.thy
@@ -0,0 +1,87 @@
+chapter \<open>Generated by Lem from \<open>show.lem\<close>.\<close>
+
+theory "Lem_show"
+
+imports
+ Main
+ "Lem_string"
+ "Lem_maybe"
+ "Lem_num"
+ "Lem_basic_classes"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import String Maybe Num Basic_classes\<close>\<close>
+
+\<comment> \<open>\<open>open import {hol} `lemTheory`\<close>\<close>
+
+record 'a Show_class=
+
+ show_method::" 'a \<Rightarrow> string "
+
+
+
+definition instance_Show_Show_string_dict :: "(string)Show_class " where
+ " instance_Show_Show_string_dict = ((|
+
+ show_method = (\<lambda> s. ([(CHR 0x22)]) @ (s @ ([(CHR 0x22)])))|) )"
+
+
+\<comment> \<open>\<open>val stringFromMaybe : forall 'a. ('a -> string) -> maybe 'a -> string\<close>\<close>
+fun stringFromMaybe :: "('a \<Rightarrow> string)\<Rightarrow> 'a option \<Rightarrow> string " where
+ " stringFromMaybe showX (Some x) = ( (''Just ('') @ (showX x @ ('')'')))"
+|" stringFromMaybe showX None = ( (''Nothing''))"
+
+
+definition instance_Show_Show_Maybe_maybe_dict :: " 'a Show_class \<Rightarrow>('a option)Show_class " where
+ " instance_Show_Show_Maybe_maybe_dict dict_Show_Show_a = ((|
+
+ show_method = (\<lambda> x_opt. stringFromMaybe
+ (show_method dict_Show_Show_a) x_opt)|) )"
+
+
+\<comment> \<open>\<open>val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string\<close>\<close>
+function (sequential,domintros) stringFromListAux :: "('a \<Rightarrow> string)\<Rightarrow> 'a list \<Rightarrow> string " where
+ " stringFromListAux showX ([]) = ( (''''))"
+|" stringFromListAux showX (x # xs') = (
+ (case xs' of
+ [] => showX x
+ | _ => showX x @ ((''; '') @ stringFromListAux showX xs')
+ ))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val stringFromList : forall 'a. ('a -> string) -> list 'a -> string\<close>\<close>
+definition stringFromList :: "('a \<Rightarrow> string)\<Rightarrow> 'a list \<Rightarrow> string " where
+ " stringFromList showX xs = (
+ (''['') @ (stringFromListAux showX xs @ ('']'')))"
+
+
+definition instance_Show_Show_list_dict :: " 'a Show_class \<Rightarrow>('a list)Show_class " where
+ " instance_Show_Show_list_dict dict_Show_Show_a = ((|
+
+ show_method = (\<lambda> xs. stringFromList
+ (show_method dict_Show_Show_a) xs)|) )"
+
+
+\<comment> \<open>\<open>val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string\<close>\<close>
+fun stringFromPair :: "('a \<Rightarrow> string)\<Rightarrow>('b \<Rightarrow> string)\<Rightarrow> 'a*'b \<Rightarrow> string " where
+ " stringFromPair showX showY (x,y) = (
+ (''('') @ (showX x @ (('', '') @ (showY y @ ('')'')))))"
+
+
+definition instance_Show_Show_tup2_dict :: " 'a Show_class \<Rightarrow> 'b Show_class \<Rightarrow>('a*'b)Show_class " where
+ " instance_Show_Show_tup2_dict dict_Show_Show_a dict_Show_Show_b = ((|
+
+ show_method = (stringFromPair
+ (show_method dict_Show_Show_a) (show_method dict_Show_Show_b))|) )"
+
+
+definition instance_Show_Show_bool_dict :: "(bool)Show_class " where
+ " instance_Show_Show_bool_dict = ((|
+
+ show_method = (\<lambda> b. if b then (''true'') else (''false''))|) )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_show_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_show_extra.thy
new file mode 100644
index 0000000..d741580
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_show_extra.thy
@@ -0,0 +1,74 @@
+chapter \<open>Generated by Lem from \<open>show_extra.lem\<close>.\<close>
+
+theory "Lem_show_extra"
+
+imports
+ Main
+ "Lem_string"
+ "Lem_maybe"
+ "Lem_num"
+ "Lem_basic_classes"
+ "Lem_set"
+ "Lem_relation"
+ "Lem_show"
+ "Lem_set_extra"
+ "Lem_string_extra"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import String Maybe Num Basic_classes Set Relation Show\<close>\<close>
+\<comment> \<open>\<open>import Set_extra String_extra\<close>\<close>
+
+definition instance_Show_Show_nat_dict :: "(nat)Show_class " where
+ " instance_Show_Show_nat_dict = ((|
+
+ show_method = Lem_string_extra.stringFromNat |) )"
+
+
+definition instance_Show_Show_Num_natural_dict :: "(nat)Show_class " where
+ " instance_Show_Show_Num_natural_dict = ((|
+
+ show_method = Lem_string_extra.stringFromNatural |) )"
+
+
+definition instance_Show_Show_Num_int_dict :: "(int)Show_class " where
+ " instance_Show_Show_Num_int_dict = ((|
+
+ show_method = Lem_string_extra.stringFromInt |) )"
+
+
+definition instance_Show_Show_Num_integer_dict :: "(int)Show_class " where
+ " instance_Show_Show_Num_integer_dict = ((|
+
+ show_method = Lem_string_extra.stringFromInteger |) )"
+
+
+definition stringFromSet :: "('a \<Rightarrow> string)\<Rightarrow> 'a set \<Rightarrow> string " where
+ " stringFromSet showX xs = (
+ (''{'') @ (Lem_show.stringFromListAux showX (list_of_set xs) @ (''}'')))"
+
+
+\<comment> \<open>\<open> Abbreviates the representation if the relation is transitive. \<close>\<close>
+definition stringFromRelation :: "('a*'a \<Rightarrow> string)\<Rightarrow>('a*'a)set \<Rightarrow> string " where
+ " stringFromRelation showX rel = (
+ if trans rel then
+ (let pruned_rel = (LemExtraDefs.without_trans_edges rel) in
+ if ((\<forall> e \<in> rel. (e \<in> pruned_rel))) then
+ \<comment> \<open>\<open> The relations are the same (there are no transitive edges),
+ so we can just as well print the original one. \<close>\<close>
+ stringFromSet showX rel
+ else
+ (''trancl of '') @ stringFromSet showX pruned_rel)
+ else
+ stringFromSet showX rel )"
+
+
+definition instance_Show_Show_set_dict :: " 'a Show_class \<Rightarrow>('a set)Show_class " where
+ " instance_Show_Show_set_dict dict_Show_Show_a = ((|
+
+ show_method = (\<lambda> xs. stringFromSet
+ (show_method dict_Show_Show_a) xs)|) )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_sorting.thy b/prover_snapshots/isabelle/lib/lem/Lem_sorting.thy
new file mode 100644
index 0000000..cdf2559
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_sorting.thy
@@ -0,0 +1,110 @@
+chapter \<open>Generated by Lem from \<open>sorting.lem\<close>.\<close>
+
+theory "Lem_sorting"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_maybe"
+ "Lem_list"
+ "Lem_num"
+ "Lem"
+ "HOL-Library.Permutation"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes Maybe List Num\<close>\<close>
+
+\<comment> \<open>\<open>open import {isabelle} `HOL-Library.Permutation`\<close>\<close>
+\<comment> \<open>\<open>open import {coq} `Coq.Lists.List`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `sortingTheory` `permLib`\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `$LIB_DIR/Lem`\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> permutations \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool\<close>\<close>
+
+fun isPermutationBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where
+ " isPermutationBy eq ([]) l2 = ( (l2 = []))"
+|" isPermutationBy eq (x # xs) l2 = ( (
+ (case delete_first (eq x) l2 of
+ None => False
+ | Some ys => isPermutationBy eq xs ys
+ )
+ ))"
+
+
+
+
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+\<comment> \<open>\<open> isSorted \<close>\<close>
+\<comment> \<open>\<open> ------------------------- \<close>\<close>
+
+\<comment> \<open>\<open> isSortedBy R l
+ checks, whether the list l is sorted by ordering R.
+ R should represent an order, i.e. it should be transitive.
+ Different backends defined "isSorted" slightly differently. However,
+ the definitions coincide for transitive R. Therefore there is the
+ following restriction:
+
+ WARNING: Use isSorted and isSortedBy only with transitive relations!
+\<close>\<close>
+
+\<comment> \<open>\<open>val isSorted : forall 'a. Ord 'a => list 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open> DPM: rejigged the definition with a nested match to get past Coq's termination checker. \<close>\<close>
+\<comment> \<open>\<open>let rec isSortedBy cmp l= match l with
+ | [] -> true
+ | x1 :: xs ->
+ match xs with
+ | [] -> true
+ | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs)
+ end
+end\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> insertion sort \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a\<close>\<close>
+
+\<comment> \<open>\<open>val insertSort: forall 'a. Ord 'a => list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a\<close>\<close>
+
+\<comment> \<open>\<open>let rec insertBy cmp e l= match l with
+ | [] -> [e]
+ | x :: xs -> if cmp x e then x :: (insertBy cmp e xs) else (e :: x :: xs)
+end\<close>\<close>
+
+\<comment> \<open>\<open>let insertSortBy cmp l= List.foldl (fun l e -> insertBy cmp e l) [] l\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> general sorting \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val sort: forall 'a. Ord 'a => list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a\<close>\<close>
+\<comment> \<open>\<open>val sortByOrd: forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a\<close>\<close>
+
+\<comment> \<open>\<open>val predicate_of_ord : forall 'a. ('a -> 'a -> ordering) -> 'a -> 'a -> bool\<close>\<close>
+definition predicate_of_ord :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where
+ " predicate_of_ord f x y = (
+ (case f x y of
+ LT => True
+ | EQ => True
+ | GT => False
+ ))"
+
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_string.thy b/prover_snapshots/isabelle/lib/lem/Lem_string.thy
new file mode 100644
index 0000000..0a2c6bc
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_string.thy
@@ -0,0 +1,75 @@
+chapter \<open>Generated by Lem from \<open>string.lem\<close>.\<close>
+
+theory "Lem_string"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+ "Lem_list"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes List\<close>\<close>
+\<comment> \<open>\<open>open import {ocaml} `Xstring`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `lemTheory` `stringTheory`\<close>\<close>
+\<comment> \<open>\<open>open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`\<close>\<close>
+
+\<comment> \<open>\<open> ------------------------------------------- \<close>\<close>
+\<comment> \<open>\<open> translations between strings and char lists \<close>\<close>
+\<comment> \<open>\<open> ------------------------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val toCharList : string -> list char\<close>\<close>
+
+\<comment> \<open>\<open>val toString : list char -> string\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> generating strings \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val makeString : nat -> char -> string\<close>\<close>
+\<comment> \<open>\<open>let makeString len c= toString (replicate len c)\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> length \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val stringLength : string -> nat\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> string concatenation \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val ^ [stringAppend] : string -> string -> string\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------------\<close>\<close>
+\<comment> \<open>\<open> setting up pattern matching \<close>\<close>
+\<comment> \<open>\<open> --------------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a\<close>\<close>
+
+\<comment> \<open>\<open>let string_case s c_empty c_cons=
+ match (toCharList s) with
+ | [] -> c_empty
+ | c :: cs -> c_cons c (toString cs)
+ end\<close>\<close>
+
+\<comment> \<open>\<open>val empty_string : string\<close>\<close>
+
+\<comment> \<open>\<open>val cons_string : char -> string -> string\<close>\<close>
+
+\<comment> \<open>\<open>val concat : string -> list string -> string\<close>\<close>
+function (sequential,domintros) concat :: " string \<Rightarrow>(string)list \<Rightarrow> string " where
+ " concat sep ([]) = ( (''''))"
+|" concat sep (s # ss') = (
+ (case ss' of
+ [] => s
+ | _ => s @ (sep @ concat sep ss')
+ ))"
+by pat_completeness auto
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_string_extra.thy b/prover_snapshots/isabelle/lib/lem/Lem_string_extra.thy
new file mode 100644
index 0000000..1d836c0
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_string_extra.thy
@@ -0,0 +1,137 @@
+chapter \<open>Generated by Lem from \<open>string_extra.lem\<close>.\<close>
+
+theory "Lem_string_extra"
+
+imports
+ Main
+ "Lem_num"
+ "Lem_list"
+ "Lem_basic_classes"
+ "Lem_string"
+ "Lem_list_extra"
+
+begin
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> String functions \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>open import Basic_classes\<close>\<close>
+\<comment> \<open>\<open>open import Num\<close>\<close>
+\<comment> \<open>\<open>open import List\<close>\<close>
+\<comment> \<open>\<open>open import String\<close>\<close>
+\<comment> \<open>\<open>open import List_extra\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `stringLib`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `ASCIInumbersTheory`\<close>\<close>
+
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> Character's to numbers \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val ord : char -> nat\<close>\<close>
+
+\<comment> \<open>\<open>val chr : nat -> char\<close>\<close>
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> Converting to strings \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val stringFromNatHelper : nat -> list char -> list char\<close>\<close>
+fun stringFromNatHelper :: " nat \<Rightarrow>(char)list \<Rightarrow>(char)list " where
+ " stringFromNatHelper n acc1 = (
+ if n =( 0 :: nat) then
+ acc1
+ else
+ stringFromNatHelper (n div( 10 :: nat)) ((%n. char_of (n::nat)) ((n mod( 10 :: nat)) +( 48 :: nat)) # acc1))"
+
+
+\<comment> \<open>\<open>val stringFromNat : nat -> string\<close>\<close>
+definition stringFromNat :: " nat \<Rightarrow> string " where
+ " stringFromNat n = (
+ if n =( 0 :: nat) then (''0'') else (stringFromNatHelper n []))"
+
+
+\<comment> \<open>\<open>val stringFromNaturalHelper : natural -> list char -> list char\<close>\<close>
+fun stringFromNaturalHelper :: " nat \<Rightarrow>(char)list \<Rightarrow>(char)list " where
+ " stringFromNaturalHelper n acc1 = (
+ if n =( 0 :: nat) then
+ acc1
+ else
+ stringFromNaturalHelper (n div( 10 :: nat)) ((%n. char_of (n::nat)) ( ((n mod( 10 :: nat)) +( 48 :: nat))) # acc1))"
+
+
+\<comment> \<open>\<open>val stringFromNatural : natural -> string\<close>\<close>
+definition stringFromNatural :: " nat \<Rightarrow> string " where
+ " stringFromNatural n = (
+ if n =( 0 :: nat) then (''0'') else (stringFromNaturalHelper n []))"
+
+
+\<comment> \<open>\<open>val stringFromInt : int -> string\<close>\<close>
+definition stringFromInt :: " int \<Rightarrow> string " where
+ " stringFromInt i = (
+ if i <( 0 :: int) then
+ (''-'') @ stringFromNat (nat (abs i))
+ else
+ stringFromNat (nat (abs i)))"
+
+
+\<comment> \<open>\<open>val stringFromInteger : integer -> string\<close>\<close>
+definition stringFromInteger :: " int \<Rightarrow> string " where
+ " stringFromInteger i = (
+ if i <( 0 :: int) then
+ (''-'') @ stringFromNatural (nat (abs i))
+ else
+ stringFromNatural (nat (abs i)))"
+
+
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> List-like operations \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val nth : string -> nat -> char\<close>\<close>
+definition nth :: " string \<Rightarrow> nat \<Rightarrow> char " where
+ " nth s n = ( List.nth ( s) n )"
+
+
+\<comment> \<open>\<open>val stringConcat : list string -> string\<close>\<close>
+definition stringConcat :: "(string)list \<Rightarrow> string " where
+ " stringConcat s = (
+ List.foldr (@) s (''''))"
+
+
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+\<comment> \<open>\<open> String comparison \<close>\<close>
+\<comment> \<open>\<open>****************************************************************************\<close>\<close>
+
+\<comment> \<open>\<open>val stringCompare : string -> string -> ordering\<close>\<close>
+
+definition stringLess :: " string \<Rightarrow> string \<Rightarrow> bool " where
+ " stringLess x y = ( orderingIsLess (EQ))"
+
+definition stringLessEq :: " string \<Rightarrow> string \<Rightarrow> bool " where
+ " stringLessEq x y = ( \<not> (orderingIsGreater (EQ)))"
+
+definition stringGreater :: " string \<Rightarrow> string \<Rightarrow> bool " where
+ " stringGreater x y = ( stringLess y x )"
+
+definition stringGreaterEq :: " string \<Rightarrow> string \<Rightarrow> bool " where
+ " stringGreaterEq x y = ( stringLessEq y x )"
+
+
+definition instance_Basic_classes_Ord_string_dict :: "(string)Ord_class " where
+ " instance_Basic_classes_Ord_string_dict = ((|
+
+ compare_method = (\<lambda> x y. EQ),
+
+ isLess_method = stringLess,
+
+ isLessEqual_method = stringLessEq,
+
+ isGreater_method = stringGreater,
+
+ isGreaterEqual_method = stringGreaterEq |) )"
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_tuple.thy b/prover_snapshots/isabelle/lib/lem/Lem_tuple.thy
new file mode 100644
index 0000000..850edac
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_tuple.thy
@@ -0,0 +1,51 @@
+chapter \<open>Generated by Lem from \<open>tuple.lem\<close>.\<close>
+
+theory "Lem_tuple"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_basic_classes"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Basic_classes\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> fst \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val fst : forall 'a 'b. 'a * 'b -> 'a\<close>\<close>
+\<comment> \<open>\<open>let fst (v1, v2)= v1\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> snd \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val snd : forall 'a 'b. 'a * 'b -> 'b\<close>\<close>
+\<comment> \<open>\<open>let snd (v1, v2)= v2\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> curry \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)\<close>\<close>
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> uncurry \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)\<close>\<close>
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> swap \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)\<close>\<close>
+\<comment> \<open>\<open>let swap (v1, v2)= (v2, v1)\<close>\<close>
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/Lem_word.thy b/prover_snapshots/isabelle/lib/lem/Lem_word.thy
new file mode 100644
index 0000000..7608033
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/Lem_word.thy
@@ -0,0 +1,1024 @@
+chapter \<open>Generated by Lem from \<open>word.lem\<close>.\<close>
+
+theory "Lem_word"
+
+imports
+ Main
+ "Lem_bool"
+ "Lem_maybe"
+ "Lem_num"
+ "Lem_basic_classes"
+ "Lem_list"
+ "HOL-Word.Word"
+
+begin
+
+
+
+\<comment> \<open>\<open>open import Bool Maybe Num Basic_classes List\<close>\<close>
+
+\<comment> \<open>\<open>open import {isabelle} `HOL-Word.Word`\<close>\<close>
+\<comment> \<open>\<open>open import {hol} `wordsTheory` `wordsLib`\<close>\<close>
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Define general purpose word, i.e. sequences of bits of arbitrary length \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+datatype bitSequence = BitSeq "
+ nat option " " \<comment> \<open>\<open> length of the sequence, Nothing means infinite length \<close>\<close>
+ bool " " bool \<comment> \<open>\<open> sign of the word, used to fill up after concrete value is exhausted \<close>\<close>
+ list " \<comment> \<open>\<open> the initial part of the sequence, least significant bit first \<close>\<close>
+
+\<comment> \<open>\<open>val bitSeqEq : bitSequence -> bitSequence -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val boolListFrombitSeq : nat -> bitSequence -> list bool\<close>\<close>
+
+fun boolListFrombitSeqAux :: " nat \<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " boolListFrombitSeqAux n s bl = (
+ if n =( 0 :: nat) then [] else
+ (case bl of
+ [] => List.replicate n s
+ | b # bl' => b # (boolListFrombitSeqAux (n-( 1 :: nat)) s bl')
+ ))"
+
+
+fun boolListFrombitSeq :: " nat \<Rightarrow> bitSequence \<Rightarrow>(bool)list " where
+ " boolListFrombitSeq n (BitSeq _ s bl) = ( boolListFrombitSeqAux n s bl )"
+
+
+
+\<comment> \<open>\<open>val bitSeqFromBoolList : list bool -> maybe bitSequence\<close>\<close>
+definition bitSeqFromBoolList :: "(bool)list \<Rightarrow>(bitSequence)option " where
+ " bitSeqFromBoolList bl = (
+ (case dest_init bl of
+ None => None
+ | Some (bl', s) => Some (BitSeq (Some (List.length bl)) s bl')
+ ))"
+
+
+
+\<comment> \<open>\<open> cleans up the representation of a bitSequence without changing its semantics \<close>\<close>
+\<comment> \<open>\<open>val cleanBitSeq : bitSequence -> bitSequence\<close>\<close>
+fun cleanBitSeq :: " bitSequence \<Rightarrow> bitSequence " where
+ " cleanBitSeq (BitSeq len s bl) = ( (case len of
+ None => (BitSeq len s (List.rev (dropWhile ((\<longleftrightarrow>) s) (List.rev bl))))
+ | Some n => (BitSeq len s (List.rev (dropWhile ((\<longleftrightarrow>) s) (List.rev (List.take (n-( 1 :: nat)) bl)))))
+))"
+
+
+
+\<comment> \<open>\<open>val bitSeqTestBit : bitSequence -> nat -> maybe bool\<close>\<close>
+fun bitSeqTestBit :: " bitSequence \<Rightarrow> nat \<Rightarrow>(bool)option " where
+ " bitSeqTestBit (BitSeq None s bl) pos = ( if pos < List.length bl then index bl pos else Some s )"
+|" bitSeqTestBit (BitSeq(Some l) s bl) pos = ( if (pos \<ge> l) then None else
+ if ((pos = (l -( 1 :: nat))) \<or> (pos \<ge> List.length bl)) then Some s else
+ index bl pos )"
+
+
+\<comment> \<open>\<open>val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence\<close>\<close>
+fun bitSeqSetBit :: " bitSequence \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> bitSequence " where
+ " bitSeqSetBit (BitSeq len s bl) pos v = (
+ (let bl' = (if (pos < List.length bl) then bl else bl @ List.replicate pos s) in
+ (let bl'' = (List.list_update bl' pos v) in
+ (let bs' = (BitSeq len s bl'') in
+ cleanBitSeq bs'))))"
+
+
+
+\<comment> \<open>\<open>val resizeBitSeq : maybe nat -> bitSequence -> bitSequence\<close>\<close>
+definition resizeBitSeq :: "(nat)option \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " resizeBitSeq new_len bs = (
+ (case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ (let shorten_opt = ((case (new_len, len) of
+ (None, _) => None
+ | (Some l1, None) => Some l1
+ | (Some l1, Some l2) =>
+ if (l1 < l2) then Some l1 else None
+ )) in
+ (case shorten_opt of
+ None => BitSeq new_len s bl
+ | Some l1 => (
+ (let bl' = (List.take l1 (bl @ [s])) in
+ (case dest_init bl' of
+ None => (BitSeq len s bl) \<comment> \<open>\<open> do nothing if size 0 is requested \<close>\<close>
+ | Some (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'')
+ )))
+ ))
+ ) )"
+
+
+\<comment> \<open>\<open>val bitSeqNot : bitSequence -> bitSequence\<close>\<close>
+fun bitSeqNot :: " bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqNot (BitSeq len s bl) = ( BitSeq len (\<not> s) (List.map (\<lambda> x. \<not> x) bl))"
+
+
+\<comment> \<open>\<open>val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence\<close>\<close>
+
+\<comment> \<open>\<open>val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool\<close>\<close>
+fun bitSeqBinopAux :: "(bool \<Rightarrow> bool \<Rightarrow> bool)\<Rightarrow> bool \<Rightarrow>(bool)list \<Rightarrow> bool \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where
+ " bitSeqBinopAux binop s1 ([]) s2 ([]) = ( [])"
+|" bitSeqBinopAux binop s1 (b1 # bl1') s2 ([]) = ( (binop b1 s2) # bitSeqBinopAux binop s1 bl1' s2 [])"
+|" bitSeqBinopAux binop s1 ([]) s2 (b2 # bl2') = ( (binop s1 b2) # bitSeqBinopAux binop s1 [] s2 bl2' )"
+|" bitSeqBinopAux binop s1 (b1 # bl1') s2 (b2 # bl2') = ( (binop b1 b2) # bitSeqBinopAux binop s1 bl1' s2 bl2' )"
+
+
+definition bitSeqBinop :: "(bool \<Rightarrow> bool \<Rightarrow> bool)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqBinop binop bs1 bs2 = ( (
+ (case cleanBitSeq bs1 of
+ (BitSeq len1 s1 bl1) =>
+ (case cleanBitSeq bs2 of
+ (BitSeq len2 s2 bl2) =>
+ (let len = ((case (len1, len2) of
+ (Some l1, Some l2) => Some (max l1 l2)
+ | _ => None
+ )) in
+ (let s = (binop s1 s2) in
+ (let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in
+ cleanBitSeq (BitSeq len s bl))))
+ )
+ )
+))"
+
+
+definition bitSeqAnd :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqAnd = ( bitSeqBinop (\<and>))"
+
+definition bitSeqOr :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqOr = ( bitSeqBinop (\<or>))"
+
+definition bitSeqXor :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqXor = ( bitSeqBinop (\<lambda> b1 b2. \<not> (b1 \<longleftrightarrow> b2)))"
+
+
+\<comment> \<open>\<open>val bitSeqShiftLeft : bitSequence -> nat -> bitSequence\<close>\<close>
+fun bitSeqShiftLeft :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where
+ " bitSeqShiftLeft (BitSeq len s bl) n = ( cleanBitSeq (BitSeq len s (List.replicate n False @ bl)))"
+
+
+\<comment> \<open>\<open>val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence\<close>\<close>
+definition bitSeqArithmeticShiftRight :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where
+ " bitSeqArithmeticShiftRight bs n = (
+ (case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ cleanBitSeq (BitSeq len s (List.drop n bl))
+ ) )"
+
+
+\<comment> \<open>\<open>val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence\<close>\<close>
+definition bitSeqLogicalShiftRight :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where
+ " bitSeqLogicalShiftRight bs n = (
+ if (n =( 0 :: nat)) then cleanBitSeq bs else
+ (case cleanBitSeq bs of
+ (BitSeq len s bl) =>
+ (case len of
+ None => cleanBitSeq (BitSeq len s (List.drop n bl))
+ | Some l => cleanBitSeq
+ (BitSeq len False ((List.drop n bl) @ List.replicate l s))
+ )
+ ) )"
+
+
+
+\<comment> \<open>\<open> integerFromBoolList sign bl creates an integer from a list of bits
+ (least significant bit first) and an explicitly given sign bit.
+ It uses two's complement encoding. \<close>\<close>
+\<comment> \<open>\<open>val integerFromBoolList : (bool * list bool) -> integer\<close>\<close>
+
+fun integerFromBoolListAux :: " int \<Rightarrow>(bool)list \<Rightarrow> int " where
+ " integerFromBoolListAux (acc1 :: int) (([]) :: bool list) = ( acc1 )"
+|" integerFromBoolListAux (acc1 :: int) ((True # bl') :: bool list) = ( integerFromBoolListAux ((acc1 *( 2 :: int)) +( 1 :: int)) bl' )"
+|" integerFromBoolListAux (acc1 :: int) ((False # bl') :: bool list) = ( integerFromBoolListAux (acc1 *( 2 :: int)) bl' )"
+
+
+fun integerFromBoolList :: " bool*(bool)list \<Rightarrow> int " where
+ " integerFromBoolList (sign, bl) = (
+ if sign then
+ - (integerFromBoolListAux(( 0 :: int)) (List.rev (List.map (\<lambda> x. \<not> x) bl)) +( 1 :: int))
+ else integerFromBoolListAux(( 0 :: int)) (List.rev bl))"
+
+
+\<comment> \<open>\<open> [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.\<close>\<close>
+\<comment> \<open>\<open>val boolListFromInteger : integer -> bool * list bool\<close>\<close>
+
+fun boolListFromNatural :: "(bool)list \<Rightarrow> nat \<Rightarrow>(bool)list " where
+ " boolListFromNatural acc1 (remainder :: nat) = (
+ if (remainder >( 0 :: nat)) then
+ (boolListFromNatural (((remainder mod( 2 :: nat)) =( 1 :: nat)) # acc1)
+ (remainder div( 2 :: nat)))
+ else
+ List.rev acc1 )"
+
+
+definition boolListFromInteger :: " int \<Rightarrow> bool*(bool)list " where
+ " boolListFromInteger (i :: int) = (
+ if (i <( 0 :: int)) then
+ (True, List.map (\<lambda> x. \<not> x) (boolListFromNatural [] (nat (abs (- (i +( 1 :: int)))))))
+ else
+ (False, boolListFromNatural [] (nat (abs i))))"
+
+
+
+\<comment> \<open>\<open> [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough
+ bits, truncation happens \<close>\<close>
+\<comment> \<open>\<open>val bitSeqFromInteger : maybe nat -> integer -> bitSequence\<close>\<close>
+definition bitSeqFromInteger :: "(nat)option \<Rightarrow> int \<Rightarrow> bitSequence " where
+ " bitSeqFromInteger len_opt i = (
+ (let (s, bl) = (boolListFromInteger i) in
+ resizeBitSeq len_opt (BitSeq None s bl)))"
+
+
+
+\<comment> \<open>\<open>val integerFromBitSeq : bitSequence -> integer\<close>\<close>
+definition integerFromBitSeq :: " bitSequence \<Rightarrow> int " where
+ " integerFromBitSeq bs = (
+ (case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) ) )"
+
+
+
+\<comment> \<open>\<open> Now we can via translation to integers map arithmetic operations to bitSequences \<close>\<close>
+
+\<comment> \<open>\<open>val bitSeqArithUnaryOp : (integer -> integer) -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqArithUnaryOp :: "(int \<Rightarrow> int)\<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqArithUnaryOp uop bs = (
+ (case bs of
+ (BitSeq len _ _) =>
+ bitSeqFromInteger len (uop (integerFromBitSeq bs))
+ ) )"
+
+
+\<comment> \<open>\<open>val bitSeqArithBinOp : (integer -> integer -> integer) -> bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqArithBinOp :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqArithBinOp binop bs1 bs2 = (
+ (case bs1 of
+ (BitSeq len1 _ _) =>
+ (case bs2 of
+ (BitSeq len2 _ _) =>
+ (let len = ((case (len1, len2) of
+ (Some l1, Some l2) => Some (max l1 l2)
+ | _ => None
+ )) in
+ bitSeqFromInteger len
+ (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)))
+ )
+ ) )"
+
+
+\<comment> \<open>\<open>val bitSeqArithBinTest : forall 'a. (integer -> integer -> 'a) -> bitSequence -> bitSequence -> 'a\<close>\<close>
+definition bitSeqArithBinTest :: "(int \<Rightarrow> int \<Rightarrow> 'a)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> 'a " where
+ " bitSeqArithBinTest binop bs1 bs2 = ( binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))"
+
+
+
+\<comment> \<open>\<open> now instantiate the number interface for bit-sequences \<close>\<close>
+
+\<comment> \<open>\<open>val bitSeqFromNumeral : numeral -> bitSequence\<close>\<close>
+
+\<comment> \<open>\<open>val bitSeqLess : bitSequence -> bitSequence -> bool\<close>\<close>
+definition bitSeqLess :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where
+ " bitSeqLess bs1 bs2 = ( bitSeqArithBinTest (<) bs1 bs2 )"
+
+
+\<comment> \<open>\<open>val bitSeqLessEqual : bitSequence -> bitSequence -> bool\<close>\<close>
+definition bitSeqLessEqual :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where
+ " bitSeqLessEqual bs1 bs2 = ( bitSeqArithBinTest (\<le>) bs1 bs2 )"
+
+
+\<comment> \<open>\<open>val bitSeqGreater : bitSequence -> bitSequence -> bool\<close>\<close>
+definition bitSeqGreater :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where
+ " bitSeqGreater bs1 bs2 = ( bitSeqArithBinTest (>) bs1 bs2 )"
+
+
+\<comment> \<open>\<open>val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool\<close>\<close>
+definition bitSeqGreaterEqual :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where
+ " bitSeqGreaterEqual bs1 bs2 = ( bitSeqArithBinTest (\<ge>) bs1 bs2 )"
+
+
+\<comment> \<open>\<open>val bitSeqCompare : bitSequence -> bitSequence -> ordering\<close>\<close>
+definition bitSeqCompare :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> ordering " where
+ " bitSeqCompare bs1 bs2 = ( bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2 )"
+
+
+definition instance_Basic_classes_Ord_Word_bitSequence_dict :: "(bitSequence)Ord_class " where
+ " instance_Basic_classes_Ord_Word_bitSequence_dict = ((|
+
+ compare_method = bitSeqCompare,
+
+ isLess_method = bitSeqLess,
+
+ isLessEqual_method = bitSeqLessEqual,
+
+ isGreater_method = bitSeqGreater,
+
+ isGreaterEqual_method = bitSeqGreaterEqual |) )"
+
+
+\<comment> \<open>\<open> arithmetic negation, don't mix up with bitwise negation \<close>\<close>
+\<comment> \<open>\<open>val bitSeqNegate : bitSequence -> bitSequence\<close>\<close>
+definition bitSeqNegate :: " bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqNegate bs = ( bitSeqArithUnaryOp (\<lambda> i. - i) bs )"
+
+
+definition instance_Num_NumNegate_Word_bitSequence_dict :: "(bitSequence)NumNegate_class " where
+ " instance_Num_NumNegate_Word_bitSequence_dict = ((|
+
+ numNegate_method = bitSeqNegate |) )"
+
+
+
+\<comment> \<open>\<open>val bitSeqAdd : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqAdd :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqAdd bs1 bs2 = ( bitSeqArithBinOp (+) bs1 bs2 )"
+
+
+definition instance_Num_NumAdd_Word_bitSequence_dict :: "(bitSequence)NumAdd_class " where
+ " instance_Num_NumAdd_Word_bitSequence_dict = ((|
+
+ numAdd_method = bitSeqAdd |) )"
+
+
+\<comment> \<open>\<open>val bitSeqMinus : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqMinus :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqMinus bs1 bs2 = ( bitSeqArithBinOp (-) bs1 bs2 )"
+
+
+definition instance_Num_NumMinus_Word_bitSequence_dict :: "(bitSequence)NumMinus_class " where
+ " instance_Num_NumMinus_Word_bitSequence_dict = ((|
+
+ numMinus_method = bitSeqMinus |) )"
+
+
+\<comment> \<open>\<open>val bitSeqSucc : bitSequence -> bitSequence\<close>\<close>
+definition bitSeqSucc :: " bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqSucc bs = ( bitSeqArithUnaryOp (\<lambda> n. n +( 1 :: int)) bs )"
+
+
+definition instance_Num_NumSucc_Word_bitSequence_dict :: "(bitSequence)NumSucc_class " where
+ " instance_Num_NumSucc_Word_bitSequence_dict = ((|
+
+ succ_method = bitSeqSucc |) )"
+
+
+\<comment> \<open>\<open>val bitSeqPred : bitSequence -> bitSequence\<close>\<close>
+definition bitSeqPred :: " bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqPred bs = ( bitSeqArithUnaryOp (\<lambda> n. n -( 1 :: int)) bs )"
+
+
+definition instance_Num_NumPred_Word_bitSequence_dict :: "(bitSequence)NumPred_class " where
+ " instance_Num_NumPred_Word_bitSequence_dict = ((|
+
+ pred_method = bitSeqPred |) )"
+
+
+\<comment> \<open>\<open>val bitSeqMult : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqMult :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqMult bs1 bs2 = ( bitSeqArithBinOp ( * ) bs1 bs2 )"
+
+
+definition instance_Num_NumMult_Word_bitSequence_dict :: "(bitSequence)NumMult_class " where
+ " instance_Num_NumMult_Word_bitSequence_dict = ((|
+
+ numMult_method = bitSeqMult |) )"
+
+
+
+\<comment> \<open>\<open>val bitSeqPow : bitSequence -> nat -> bitSequence\<close>\<close>
+definition bitSeqPow :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where
+ " bitSeqPow bs n = ( bitSeqArithUnaryOp (\<lambda> i . i ^ n) bs )"
+
+
+definition instance_Num_NumPow_Word_bitSequence_dict :: "(bitSequence)NumPow_class " where
+ " instance_Num_NumPow_Word_bitSequence_dict = ((|
+
+ numPow_method = bitSeqPow |) )"
+
+
+\<comment> \<open>\<open>val bitSeqDiv : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqDiv :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqDiv bs1 bs2 = ( bitSeqArithBinOp (div) bs1 bs2 )"
+
+
+definition instance_Num_NumIntegerDivision_Word_bitSequence_dict :: "(bitSequence)NumIntegerDivision_class " where
+ " instance_Num_NumIntegerDivision_Word_bitSequence_dict = ((|
+
+ div_method = bitSeqDiv |) )"
+
+
+definition instance_Num_NumDivision_Word_bitSequence_dict :: "(bitSequence)NumDivision_class " where
+ " instance_Num_NumDivision_Word_bitSequence_dict = ((|
+
+ numDivision_method = bitSeqDiv |) )"
+
+
+\<comment> \<open>\<open>val bitSeqMod : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqMod :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqMod bs1 bs2 = ( bitSeqArithBinOp (mod) bs1 bs2 )"
+
+
+definition instance_Num_NumRemainder_Word_bitSequence_dict :: "(bitSequence)NumRemainder_class " where
+ " instance_Num_NumRemainder_Word_bitSequence_dict = ((|
+
+ mod_method = bitSeqMod |) )"
+
+
+\<comment> \<open>\<open>val bitSeqMin : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqMin :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqMin bs1 bs2 = ( bitSeqArithBinOp min bs1 bs2 )"
+
+
+\<comment> \<open>\<open>val bitSeqMax : bitSequence -> bitSequence -> bitSequence\<close>\<close>
+definition bitSeqMax :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where
+ " bitSeqMax bs1 bs2 = ( bitSeqArithBinOp max bs1 bs2 )"
+
+
+definition instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict :: "(bitSequence)OrdMaxMin_class " where
+ " instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict = ((|
+
+ max_method = bitSeqMax,
+
+ min_method = bitSeqMin |) )"
+
+
+
+
+
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+\<comment> \<open>\<open> Interface for bitoperations \<close>\<close>
+\<comment> \<open>\<open> ========================================================================== \<close>\<close>
+
+record 'a WordNot_class=
+
+ lnot_method ::" 'a \<Rightarrow> 'a "
+
+
+
+record 'a WordAnd_class=
+
+ land_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a WordOr_class=
+
+ lor_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+
+record 'a WordXor_class=
+
+ lxor_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+record 'a WordLsl_class=
+
+ lsl_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a "
+
+
+
+record 'a WordLsr_class=
+
+ lsr_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a "
+
+
+
+record 'a WordAsr_class=
+
+ asr_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a "
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> bitSequence \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+definition instance_Word_WordNot_Word_bitSequence_dict :: "(bitSequence)WordNot_class " where
+ " instance_Word_WordNot_Word_bitSequence_dict = ((|
+
+ lnot_method = bitSeqNot |) )"
+
+
+definition instance_Word_WordAnd_Word_bitSequence_dict :: "(bitSequence)WordAnd_class " where
+ " instance_Word_WordAnd_Word_bitSequence_dict = ((|
+
+ land_method = bitSeqAnd |) )"
+
+
+definition instance_Word_WordOr_Word_bitSequence_dict :: "(bitSequence)WordOr_class " where
+ " instance_Word_WordOr_Word_bitSequence_dict = ((|
+
+ lor_method = bitSeqOr |) )"
+
+
+definition instance_Word_WordXor_Word_bitSequence_dict :: "(bitSequence)WordXor_class " where
+ " instance_Word_WordXor_Word_bitSequence_dict = ((|
+
+ lxor_method = bitSeqXor |) )"
+
+
+definition instance_Word_WordLsl_Word_bitSequence_dict :: "(bitSequence)WordLsl_class " where
+ " instance_Word_WordLsl_Word_bitSequence_dict = ((|
+
+ lsl_method = bitSeqShiftLeft |) )"
+
+
+definition instance_Word_WordLsr_Word_bitSequence_dict :: "(bitSequence)WordLsr_class " where
+ " instance_Word_WordLsr_Word_bitSequence_dict = ((|
+
+ lsr_method = bitSeqLogicalShiftRight |) )"
+
+
+definition instance_Word_WordAsr_Word_bitSequence_dict :: "(bitSequence)WordAsr_class " where
+ " instance_Word_WordAsr_Word_bitSequence_dict = ((|
+
+ asr_method = bitSeqArithmeticShiftRight |) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int32 \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val int32Lnot : int32 -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordNot_Num_int32_dict :: "( 32 word)WordNot_class " where
+ " instance_Word_WordNot_Num_int32_dict = ((|
+
+ lnot_method = (\<lambda> w. (NOT w))|) )"
+
+
+
+\<comment> \<open>\<open>val int32Lor : int32 -> int32 -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordOr_Num_int32_dict :: "( 32 word)WordOr_class " where
+ " instance_Word_WordOr_Num_int32_dict = ((|
+
+ lor_method = (OR)|) )"
+
+
+\<comment> \<open>\<open>val int32Lxor : int32 -> int32 -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordXor_Num_int32_dict :: "( 32 word)WordXor_class " where
+ " instance_Word_WordXor_Num_int32_dict = ((|
+
+ lxor_method = (XOR)|) )"
+
+
+\<comment> \<open>\<open>val int32Land : int32 -> int32 -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordAnd_Num_int32_dict :: "( 32 word)WordAnd_class " where
+ " instance_Word_WordAnd_Num_int32_dict = ((|
+
+ land_method = (AND)|) )"
+
+
+\<comment> \<open>\<open>val int32Lsl : int32 -> nat -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordLsl_Num_int32_dict :: "( 32 word)WordLsl_class " where
+ " instance_Word_WordLsl_Num_int32_dict = ((|
+
+ lsl_method = (<<)|) )"
+
+
+\<comment> \<open>\<open>val int32Lsr : int32 -> nat -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordLsr_Num_int32_dict :: "( 32 word)WordLsr_class " where
+ " instance_Word_WordLsr_Num_int32_dict = ((|
+
+ lsr_method = (>>)|) )"
+
+
+
+\<comment> \<open>\<open>val int32Asr : int32 -> nat -> int32\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordAsr_Num_int32_dict :: "( 32 word)WordAsr_class " where
+ " instance_Word_WordAsr_Num_int32_dict = ((|
+
+ asr_method = (>>>)|) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int64 \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val int64Lnot : int64 -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordNot_Num_int64_dict :: "( 64 word)WordNot_class " where
+ " instance_Word_WordNot_Num_int64_dict = ((|
+
+ lnot_method = (\<lambda> w. (NOT w))|) )"
+
+
+\<comment> \<open>\<open>val int64Lor : int64 -> int64 -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordOr_Num_int64_dict :: "( 64 word)WordOr_class " where
+ " instance_Word_WordOr_Num_int64_dict = ((|
+
+ lor_method = (OR)|) )"
+
+
+\<comment> \<open>\<open>val int64Lxor : int64 -> int64 -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordXor_Num_int64_dict :: "( 64 word)WordXor_class " where
+ " instance_Word_WordXor_Num_int64_dict = ((|
+
+ lxor_method = (XOR)|) )"
+
+
+\<comment> \<open>\<open>val int64Land : int64 -> int64 -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordAnd_Num_int64_dict :: "( 64 word)WordAnd_class " where
+ " instance_Word_WordAnd_Num_int64_dict = ((|
+
+ land_method = (AND)|) )"
+
+
+\<comment> \<open>\<open>val int64Lsl : int64 -> nat -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordLsl_Num_int64_dict :: "( 64 word)WordLsl_class " where
+ " instance_Word_WordLsl_Num_int64_dict = ((|
+
+ lsl_method = (<<)|) )"
+
+
+\<comment> \<open>\<open>val int64Lsr : int64 -> nat -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordLsr_Num_int64_dict :: "( 64 word)WordLsr_class " where
+ " instance_Word_WordLsr_Num_int64_dict = ((|
+
+ lsr_method = (>>)|) )"
+
+
+\<comment> \<open>\<open>val int64Asr : int64 -> nat -> int64\<close>\<close> \<comment> \<open>\<open> XXX: fix \<close>\<close>
+
+definition instance_Word_WordAsr_Num_int64_dict :: "( 64 word)WordAsr_class " where
+ " instance_Word_WordAsr_Num_int64_dict = ((|
+
+ asr_method = (>>>)|) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> Words via bit sequences \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a\<close>\<close>
+definition defaultLnot :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a " where
+ " defaultLnot fromBitSeq toBitSeq x = ( fromBitSeq (bitSeqNegate (toBitSeq x)))"
+
+
+\<comment> \<open>\<open>val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a\<close>\<close>
+definition defaultLand :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where
+ " defaultLand fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2)))"
+
+
+\<comment> \<open>\<open>val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a\<close>\<close>
+definition defaultLor :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where
+ " defaultLor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2)))"
+
+
+\<comment> \<open>\<open>val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a\<close>\<close>
+definition defaultLxor :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where
+ " defaultLxor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2)))"
+
+
+\<comment> \<open>\<open>val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a\<close>\<close>
+definition defaultLsl :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where
+ " defaultLsl fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqShiftLeft (toBitSeq x) n))"
+
+
+\<comment> \<open>\<open>val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a\<close>\<close>
+definition defaultLsr :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where
+ " defaultLsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n))"
+
+
+\<comment> \<open>\<open>val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a\<close>\<close>
+definition defaultAsr :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where
+ " defaultAsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n))"
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> integer \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open>val integerLnot : integer -> integer\<close>\<close>
+definition integerLnot :: " int \<Rightarrow> int " where
+ " integerLnot i = ( - (i +( 1 :: int)))"
+
+
+definition instance_Word_WordNot_Num_integer_dict :: "(int)WordNot_class " where
+ " instance_Word_WordNot_Num_integer_dict = ((|
+
+ lnot_method = integerLnot |) )"
+
+
+
+\<comment> \<open>\<open>val integerLor : integer -> integer -> integer\<close>\<close>
+definition integerLor :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " integerLor i1 i2 = ( defaultLor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )"
+
+
+definition instance_Word_WordOr_Num_integer_dict :: "(int)WordOr_class " where
+ " instance_Word_WordOr_Num_integer_dict = ((|
+
+ lor_method = integerLor |) )"
+
+
+\<comment> \<open>\<open>val integerLxor : integer -> integer -> integer\<close>\<close>
+definition integerLxor :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " integerLxor i1 i2 = ( defaultLxor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )"
+
+
+definition instance_Word_WordXor_Num_integer_dict :: "(int)WordXor_class " where
+ " instance_Word_WordXor_Num_integer_dict = ((|
+
+ lxor_method = integerLxor |) )"
+
+
+\<comment> \<open>\<open>val integerLand : integer -> integer -> integer\<close>\<close>
+definition integerLand :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " integerLand i1 i2 = ( defaultLand integerFromBitSeq (bitSeqFromInteger None) i1 i2 )"
+
+
+definition instance_Word_WordAnd_Num_integer_dict :: "(int)WordAnd_class " where
+ " instance_Word_WordAnd_Num_integer_dict = ((|
+
+ land_method = integerLand |) )"
+
+
+\<comment> \<open>\<open>val integerLsl : integer -> nat -> integer\<close>\<close>
+definition integerLsl :: " int \<Rightarrow> nat \<Rightarrow> int " where
+ " integerLsl i n = ( defaultLsl integerFromBitSeq (bitSeqFromInteger None) i n )"
+
+
+definition instance_Word_WordLsl_Num_integer_dict :: "(int)WordLsl_class " where
+ " instance_Word_WordLsl_Num_integer_dict = ((|
+
+ lsl_method = integerLsl |) )"
+
+
+\<comment> \<open>\<open>val integerAsr : integer -> nat -> integer\<close>\<close>
+definition integerAsr :: " int \<Rightarrow> nat \<Rightarrow> int " where
+ " integerAsr i n = ( defaultAsr integerFromBitSeq (bitSeqFromInteger None) i n )"
+
+
+definition instance_Word_WordLsr_Num_integer_dict :: "(int)WordLsr_class " where
+ " instance_Word_WordLsr_Num_integer_dict = ((|
+
+ lsr_method = integerAsr |) )"
+
+
+definition instance_Word_WordAsr_Num_integer_dict :: "(int)WordAsr_class " where
+ " instance_Word_WordAsr_Num_integer_dict = ((|
+
+ asr_method = integerAsr |) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> int \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> sometimes it is convenient to be able to perform bit-operations on ints.
+ However, since int is not well-defined (it has different size on different systems),
+ it should be used very carefully and only for operations that don't depend on the
+ bitwidth of int \<close>\<close>
+
+\<comment> \<open>\<open>val intFromBitSeq : bitSequence -> int\<close>\<close>
+definition intFromBitSeq :: " bitSequence \<Rightarrow> int " where
+ " intFromBitSeq bs = ( (integerFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))"
+
+
+
+\<comment> \<open>\<open>val bitSeqFromInt : int -> bitSequence\<close>\<close>
+definition bitSeqFromInt :: " int \<Rightarrow> bitSequence " where
+ " bitSeqFromInt i = ( bitSeqFromInteger (Some(( 31 :: nat))) ( i))"
+
+
+
+\<comment> \<open>\<open>val intLnot : int -> int\<close>\<close>
+definition intLnot :: " int \<Rightarrow> int " where
+ " intLnot i = ( - (i +( 1 :: int)))"
+
+
+definition instance_Word_WordNot_Num_int_dict :: "(int)WordNot_class " where
+ " instance_Word_WordNot_Num_int_dict = ((|
+
+ lnot_method = intLnot |) )"
+
+
+\<comment> \<open>\<open>val intLor : int -> int -> int\<close>\<close>
+definition intLor :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " intLor i1 i2 = ( defaultLor intFromBitSeq bitSeqFromInt i1 i2 )"
+
+
+definition instance_Word_WordOr_Num_int_dict :: "(int)WordOr_class " where
+ " instance_Word_WordOr_Num_int_dict = ((|
+
+ lor_method = intLor |) )"
+
+
+\<comment> \<open>\<open>val intLxor : int -> int -> int\<close>\<close>
+definition intLxor :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " intLxor i1 i2 = ( defaultLxor intFromBitSeq bitSeqFromInt i1 i2 )"
+
+
+definition instance_Word_WordXor_Num_int_dict :: "(int)WordXor_class " where
+ " instance_Word_WordXor_Num_int_dict = ((|
+
+ lxor_method = intLxor |) )"
+
+
+\<comment> \<open>\<open>val intLand : int -> int -> int\<close>\<close>
+definition intLand :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " intLand i1 i2 = ( defaultLand intFromBitSeq bitSeqFromInt i1 i2 )"
+
+
+definition instance_Word_WordAnd_Num_int_dict :: "(int)WordAnd_class " where
+ " instance_Word_WordAnd_Num_int_dict = ((|
+
+ land_method = intLand |) )"
+
+
+\<comment> \<open>\<open>val intLsl : int -> nat -> int\<close>\<close>
+definition intLsl :: " int \<Rightarrow> nat \<Rightarrow> int " where
+ " intLsl i n = ( defaultLsl intFromBitSeq bitSeqFromInt i n )"
+
+
+definition instance_Word_WordLsl_Num_int_dict :: "(int)WordLsl_class " where
+ " instance_Word_WordLsl_Num_int_dict = ((|
+
+ lsl_method = intLsl |) )"
+
+
+\<comment> \<open>\<open>val intAsr : int -> nat -> int\<close>\<close>
+definition intAsr :: " int \<Rightarrow> nat \<Rightarrow> int " where
+ " intAsr i n = ( defaultAsr intFromBitSeq bitSeqFromInt i n )"
+
+
+definition instance_Word_WordAsr_Num_int_dict :: "(int)WordAsr_class " where
+ " instance_Word_WordAsr_Num_int_dict = ((|
+
+ asr_method = intAsr |) )"
+
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> natural \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> some operations work also on positive numbers \<close>\<close>
+
+\<comment> \<open>\<open>val naturalFromBitSeq : bitSequence -> natural\<close>\<close>
+definition naturalFromBitSeq :: " bitSequence \<Rightarrow> nat " where
+ " naturalFromBitSeq bs = ( nat (abs (integerFromBitSeq bs)))"
+
+
+\<comment> \<open>\<open>val bitSeqFromNatural : maybe nat -> natural -> bitSequence\<close>\<close>
+definition bitSeqFromNatural :: "(nat)option \<Rightarrow> nat \<Rightarrow> bitSequence " where
+ " bitSeqFromNatural len n = ( bitSeqFromInteger len (int n))"
+
+
+\<comment> \<open>\<open>val naturalLor : natural -> natural -> natural\<close>\<close>
+definition naturalLor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " naturalLor i1 i2 = ( defaultLor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )"
+
+
+definition instance_Word_WordOr_Num_natural_dict :: "(nat)WordOr_class " where
+ " instance_Word_WordOr_Num_natural_dict = ((|
+
+ lor_method = naturalLor |) )"
+
+
+\<comment> \<open>\<open>val naturalLxor : natural -> natural -> natural\<close>\<close>
+definition naturalLxor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " naturalLxor i1 i2 = ( defaultLxor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )"
+
+
+definition instance_Word_WordXor_Num_natural_dict :: "(nat)WordXor_class " where
+ " instance_Word_WordXor_Num_natural_dict = ((|
+
+ lxor_method = naturalLxor |) )"
+
+
+\<comment> \<open>\<open>val naturalLand : natural -> natural -> natural\<close>\<close>
+definition naturalLand :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " naturalLand i1 i2 = ( defaultLand naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )"
+
+
+definition instance_Word_WordAnd_Num_natural_dict :: "(nat)WordAnd_class " where
+ " instance_Word_WordAnd_Num_natural_dict = ((|
+
+ land_method = naturalLand |) )"
+
+
+\<comment> \<open>\<open>val naturalLsl : natural -> nat -> natural\<close>\<close>
+definition naturalLsl :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " naturalLsl i n = ( defaultLsl naturalFromBitSeq (bitSeqFromNatural None) i n )"
+
+
+definition instance_Word_WordLsl_Num_natural_dict :: "(nat)WordLsl_class " where
+ " instance_Word_WordLsl_Num_natural_dict = ((|
+
+ lsl_method = naturalLsl |) )"
+
+
+\<comment> \<open>\<open>val naturalAsr : natural -> nat -> natural\<close>\<close>
+definition naturalAsr :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " naturalAsr i n = ( defaultAsr naturalFromBitSeq (bitSeqFromNatural None) i n )"
+
+
+definition instance_Word_WordLsr_Num_natural_dict :: "(nat)WordLsr_class " where
+ " instance_Word_WordLsr_Num_natural_dict = ((|
+
+ lsr_method = naturalAsr |) )"
+
+
+definition instance_Word_WordAsr_Num_natural_dict :: "(nat)WordAsr_class " where
+ " instance_Word_WordAsr_Num_natural_dict = ((|
+
+ asr_method = naturalAsr |) )"
+
+
+
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+\<comment> \<open>\<open> nat \<close>\<close>
+\<comment> \<open>\<open> ----------------------- \<close>\<close>
+
+\<comment> \<open>\<open> sometimes it is convenient to be able to perform bit-operations on nats.
+ However, since nat is not well-defined (it has different size on different systems),
+ it should be used very carefully and only for operations that don't depend on the
+ bitwidth of nat \<close>\<close>
+
+\<comment> \<open>\<open>val natFromBitSeq : bitSequence -> nat\<close>\<close>
+definition natFromBitSeq :: " bitSequence \<Rightarrow> nat " where
+ " natFromBitSeq bs = ( (naturalFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))"
+
+
+
+\<comment> \<open>\<open>val bitSeqFromNat : nat -> bitSequence\<close>\<close>
+definition bitSeqFromNat :: " nat \<Rightarrow> bitSequence " where
+ " bitSeqFromNat i = ( bitSeqFromNatural (Some(( 31 :: nat))) ( i))"
+
+
+
+\<comment> \<open>\<open>val natLor : nat -> nat -> nat\<close>\<close>
+definition natLor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " natLor i1 i2 = ( defaultLor natFromBitSeq bitSeqFromNat i1 i2 )"
+
+
+definition instance_Word_WordOr_nat_dict :: "(nat)WordOr_class " where
+ " instance_Word_WordOr_nat_dict = ((|
+
+ lor_method = natLor |) )"
+
+
+\<comment> \<open>\<open>val natLxor : nat -> nat -> nat\<close>\<close>
+definition natLxor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " natLxor i1 i2 = ( defaultLxor natFromBitSeq bitSeqFromNat i1 i2 )"
+
+
+definition instance_Word_WordXor_nat_dict :: "(nat)WordXor_class " where
+ " instance_Word_WordXor_nat_dict = ((|
+
+ lxor_method = natLxor |) )"
+
+
+\<comment> \<open>\<open>val natLand : nat -> nat -> nat\<close>\<close>
+definition natLand :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " natLand i1 i2 = ( defaultLand natFromBitSeq bitSeqFromNat i1 i2 )"
+
+
+definition instance_Word_WordAnd_nat_dict :: "(nat)WordAnd_class " where
+ " instance_Word_WordAnd_nat_dict = ((|
+
+ land_method = natLand |) )"
+
+
+\<comment> \<open>\<open>val natLsl : nat -> nat -> nat\<close>\<close>
+definition natLsl :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " natLsl i n = ( defaultLsl natFromBitSeq bitSeqFromNat i n )"
+
+
+definition instance_Word_WordLsl_nat_dict :: "(nat)WordLsl_class " where
+ " instance_Word_WordLsl_nat_dict = ((|
+
+ lsl_method = natLsl |) )"
+
+
+\<comment> \<open>\<open>val natAsr : nat -> nat -> nat\<close>\<close>
+definition natAsr :: " nat \<Rightarrow> nat \<Rightarrow> nat " where
+ " natAsr i n = ( defaultAsr natFromBitSeq bitSeqFromNat i n )"
+
+
+definition instance_Word_WordAsr_nat_dict :: "(nat)WordAsr_class " where
+ " instance_Word_WordAsr_nat_dict = ((|
+
+ asr_method = natAsr |) )"
+
+
+end
diff --git a/prover_snapshots/isabelle/lib/lem/ROOT b/prover_snapshots/isabelle/lib/lem/ROOT
new file mode 100644
index 0000000..d5face9
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/lem/ROOT
@@ -0,0 +1,5 @@
+session LEM = "HOL-Word" +
+ description \<open>
+ HOL + LEM specific theories
+ \<close>
+ theories Lem_pervasives Lem_pervasives_extra \ No newline at end of file
diff --git a/prover_snapshots/isabelle/lib/sail/Hoare.thy b/prover_snapshots/isabelle/lib/sail/Hoare.thy
new file mode 100644
index 0000000..98b7d07
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Hoare.thy
@@ -0,0 +1,525 @@
+theory Hoare
+ imports
+ Sail2_state_lemmas
+ "HOL-Eisbach.Eisbach_Tools"
+begin
+
+(*adhoc_overloading
+ Monad_Syntax.bind State_monad.bindS*)
+
+section \<open>Hoare logic for the state, exception and nondeterminism monad\<close>
+
+subsection \<open>Hoare triples\<close>
+
+type_synonym 'regs predS = "'regs sequential_state \<Rightarrow> bool"
+
+definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_\<rbrace>")
+ where "PrePost P f Q \<equiv> (\<forall>s. P s \<longrightarrow> (\<forall>(r, s') \<in> f s. Q r s'))"
+
+lemma PrePostI:
+ assumes "\<And>s r s'. P s \<Longrightarrow> (r, s') \<in> f s \<Longrightarrow> Q r s'"
+ shows "PrePost P f Q"
+ using assms unfolding PrePost_def by auto
+
+lemma PrePost_elim:
+ assumes "PrePost P f Q" and "P s" and "(r, s') \<in> f s"
+ obtains "Q r s'"
+ using assms by (fastforce simp: PrePost_def)
+
+lemma PrePost_consequence:
+ assumes "PrePost A f B"
+ and "\<And>s. P s \<Longrightarrow> A s" and "\<And>v s. B v s \<Longrightarrow> Q v s"
+ shows "PrePost P f Q"
+ using assms unfolding PrePost_def by (blast intro: list.pred_mono_strong)
+
+lemma PrePost_strengthen_pre:
+ assumes "PrePost A f C" and "\<And>s. B s \<Longrightarrow> A s"
+ shows "PrePost B f C"
+ using assms by (rule PrePost_consequence)
+
+lemma PrePost_weaken_post:
+ assumes "PrePost A f B" and "\<And>v s. B v s \<Longrightarrow> C v s"
+ shows "PrePost A f C"
+ using assms by (blast intro: PrePost_consequence)
+
+named_theorems PrePost_compositeI
+named_theorems PrePost_atomI
+
+lemma PrePost_True_post[PrePost_atomI, intro, simp]:
+ "PrePost P m (\<lambda>_ _. True)"
+ unfolding PrePost_def by auto
+
+lemma PrePost_any: "PrePost (\<lambda>s. \<forall>(r, s') \<in> m s. Q r s') m Q"
+ unfolding PrePost_def by auto
+
+lemma PrePost_returnS[intro, PrePost_atomI]: "PrePost (P (Value x)) (returnS x) P"
+ unfolding PrePost_def returnS_def by auto
+
+lemma PrePost_bindS[intro, PrePost_compositeI]:
+ assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePost (R a) (f a) Q"
+ and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R a | Ex e \<Rightarrow> Q (Ex e))"
+ shows "PrePost P (bindS m f) Q"
+proof (intro PrePostI)
+ fix s r s'
+ assume P: "P s" and bind: "(r, s') \<in> bindS m f s"
+ from bind show "Q r s'"
+ proof (cases r s' m f s rule: bindS_cases)
+ case (Value a a' s'')
+ then have "R a' s''" using P m by (auto elim: PrePost_elim)
+ then show ?thesis using Value f by (auto elim: PrePost_elim)
+ next
+ case (Ex_Left e)
+ then show ?thesis using P m by (auto elim: PrePost_elim)
+ next
+ case (Ex_Right e a s'')
+ then have "R a s''" using P m by (auto elim: PrePost_elim)
+ then show ?thesis using Ex_Right f by (auto elim: PrePost_elim)
+ qed
+qed
+
+lemma PrePost_bindS_ignore:
+ assumes f: "PrePost R f Q"
+ and m : "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R | Ex e \<Rightarrow> Q (Ex e))"
+ shows "PrePost P (bindS m (\<lambda>_. f)) Q"
+ using assms by auto
+
+lemma PrePost_bindS_unit:
+ fixes m :: "('regs, unit, 'e) monadS"
+ assumes f: "PrePost R (f ()) Q"
+ and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R | Ex e \<Rightarrow> Q (Ex e))"
+ shows "PrePost P (bindS m f) Q"
+ using assms by auto
+
+lemma PrePost_readS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P"
+ unfolding PrePost_def readS_def returnS_def by auto
+
+lemma PrePost_updateS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P"
+ unfolding PrePost_def updateS_def returnS_def by auto
+
+lemma PrePost_if:
+ assumes "b \<Longrightarrow> PrePost P f Q" and "\<not>b \<Longrightarrow> PrePost P g Q"
+ shows "PrePost P (if b then f else g) Q"
+ using assms by auto
+
+lemma PrePost_if_branch[PrePost_compositeI]:
+ assumes "b \<Longrightarrow> PrePost Pf f Q" and "\<not>b \<Longrightarrow> PrePost Pg g Q"
+ shows "PrePost (if b then Pf else Pg) (if b then f else g) Q"
+ using assms by auto
+
+lemma PrePost_if_then:
+ assumes "b" and "PrePost P f Q"
+ shows "PrePost P (if b then f else g) Q"
+ using assms by auto
+
+lemma PrePost_if_else:
+ assumes "\<not>b" and "PrePost P g Q"
+ shows "PrePost P (if b then f else g) Q"
+ using assms by auto
+
+lemma PrePost_prod_cases[PrePost_compositeI]:
+ assumes "PrePost P (f (fst x) (snd x)) Q"
+ shows "PrePost P (case x of (a, b) \<Rightarrow> f a b) Q"
+ using assms by (auto split: prod.splits)
+
+lemma PrePost_option_cases[PrePost_compositeI]:
+ assumes "\<And>a. PrePost (PS a) (s a) Q" and "PrePost PN n Q"
+ shows "PrePost (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q"
+ using assms by (auto split: option.splits)
+
+lemma PrePost_let[intro, PrePost_compositeI]:
+ assumes "PrePost P (m y) Q"
+ shows "PrePost P (let x = y in m x) Q"
+ using assms by auto
+
+lemma PrePost_and_boolS[PrePost_compositeI]:
+ assumes r: "PrePost R r Q"
+ and l: "PrePost P l (\<lambda>r. case r of Value True \<Rightarrow> R | _ \<Rightarrow> Q r)"
+ shows "PrePost P (and_boolS l r) Q"
+ unfolding and_boolS_def
+proof (rule PrePost_bindS)
+ fix s a s'
+ assume "(Value a, s') \<in> l s"
+ show "PrePost (if a then R else Q (Value False)) (if a then r else returnS False) Q"
+ using r by auto
+next
+ show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then R else Q (Value False) | Ex e \<Rightarrow> Q (Ex e))"
+ using l by (elim PrePost_weaken_post) (auto split: result.splits)
+qed
+
+lemma PrePost_or_boolS[PrePost_compositeI]:
+ assumes r: "PrePost R r Q"
+ and l: "PrePost P l (\<lambda>r. case r of Value False \<Rightarrow> R | _ \<Rightarrow> Q r)"
+ shows "PrePost P (or_boolS l r) Q"
+ unfolding or_boolS_def
+proof (rule PrePost_bindS)
+ fix s a s'
+ assume "(Value a, s') \<in> l s"
+ show "PrePost (if a then Q (Value True) else R) (if a then returnS True else r) Q"
+ using r by auto
+next
+ show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then Q (Value True) else R | Ex e \<Rightarrow> Q (Ex e))"
+ using l by (elim PrePost_weaken_post) (auto split: result.splits)
+qed
+
+lemma PrePost_assert_expS[intro, PrePost_atomI]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P"
+ unfolding PrePost_def assert_expS_def by (auto simp: returnS_def failS_def)
+
+lemma PrePost_chooseS[intro, PrePost_atomI]: "PrePost (\<lambda>s. \<forall>x \<in> set xs. Q (Value x) s) (chooseS xs) Q"
+ by (auto simp: PrePost_def chooseS_def)
+
+lemma PrePost_failS[intro, PrePost_atomI]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q"
+ by (auto simp: PrePost_def failS_def)
+
+lemma case_result_combine[simp]:
+ "(case r of Value a \<Rightarrow> Q (Value a) | Ex e \<Rightarrow> Q (Ex e)) = Q r"
+ by (auto split: result.splits)
+
+lemma PrePost_foreachS_Nil[intro, simp, PrePost_atomI]:
+ "PrePost (Q (Value vars)) (foreachS [] vars body) Q"
+ by auto
+
+lemma PrePost_foreachS_Cons:
+ assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePost (Q (Value vars')) (foreachS xs vars' body) Q"
+ and "PrePost (Q (Value vars)) (body x vars) Q"
+ shows "PrePost (Q (Value vars)) (foreachS (x # xs) vars body) Q"
+ using assms by fastforce
+
+lemma PrePost_foreachS_invariant:
+ assumes "\<And>x vars. x \<in> set xs \<Longrightarrow> PrePost (Q (Value vars)) (body x vars) Q"
+ shows "PrePost (Q (Value vars)) (foreachS xs vars body) Q"
+proof (use assms in \<open>induction xs arbitrary: vars\<close>)
+ case (Cons x xs)
+ have "PrePost (Q (Value vars)) (bindS (body x vars) (\<lambda>vars. foreachS xs vars body)) Q"
+ proof (rule PrePost_bindS)
+ fix vars'
+ show "PrePost (Q (Value vars')) (foreachS xs vars' body) Q"
+ using Cons by auto
+ show "PrePost (Q (Value vars)) (body x vars) (\<lambda>r. case r of Value a \<Rightarrow> Q (Value a) | result.Ex e \<Rightarrow> Q (result.Ex e))"
+ unfolding case_result_combine
+ using Cons by auto
+ qed
+ then show ?case by auto
+qed auto
+
+subsection \<open>Hoare quadruples\<close>
+
+text \<open>It is often convenient to treat the exception case separately. For this purpose, we use
+a Hoare logic similar to the one used in [1]. It features not only Hoare triples, but also quadruples
+with two postconditions: one for the case where the computation succeeds, and one for the case where
+there is an exception.
+
+[1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’,
+in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close>
+
+definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_ \<bar> _\<rbrace>")
+ where "PrePostE P f Q E \<equiv> PrePost P f (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)"
+
+lemmas PrePost_defs = PrePost_def PrePostE_def
+
+lemma PrePostE_I[case_names Val Err]:
+ assumes "\<And>s a s'. P s \<Longrightarrow> (Value a, s') \<in> f s \<Longrightarrow> Q a s'"
+ and "\<And>s e s'. P s \<Longrightarrow> (Ex e, s') \<in> f s \<Longrightarrow> E e s'"
+ shows "PrePostE P f Q E"
+ using assms unfolding PrePostE_def by (intro PrePostI) (auto split: result.splits)
+
+lemma PrePostE_PrePost:
+ assumes "PrePost P m (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)"
+ shows "PrePostE P m Q E"
+ using assms unfolding PrePostE_def by auto
+
+lemma PrePostE_elim:
+ assumes "PrePostE P f Q E" and "P s" and "(r, s') \<in> f s"
+ obtains
+ (Val) v where "r = Value v" "Q v s'"
+ | (Ex) e where "r = Ex e" "E e s'"
+ using assms by (cases r; fastforce simp: PrePost_defs)
+
+lemma PrePostE_consequence:
+ assumes "PrePostE A f B C"
+ and "\<And>s. P s \<Longrightarrow> A s" and "\<And>v s. B v s \<Longrightarrow> Q v s" and "\<And>e s. C e s \<Longrightarrow> E e s"
+ shows "PrePostE P f Q E"
+ using assms unfolding PrePostE_def by (auto elim: PrePost_consequence split: result.splits)
+
+lemma PrePostE_strengthen_pre:
+ assumes "PrePostE R f Q E" and "\<And>s. P s \<Longrightarrow> R s"
+ shows "PrePostE P f Q E"
+ using assms PrePostE_consequence by blast
+
+lemma PrePostE_weaken_post:
+ assumes "PrePostE A f B E" and "\<And>v s. B v s \<Longrightarrow> C v s"
+ shows "PrePostE A f C E"
+ using assms by (blast intro: PrePostE_consequence)
+
+named_theorems PrePostE_compositeI
+named_theorems PrePostE_atomI
+
+lemma PrePostE_conj_conds:
+ assumes "PrePostE P1 m Q1 E1"
+ and "PrePostE P2 m Q2 E2"
+ shows "PrePostE (\<lambda>s. P1 s \<and> P2 s) m (\<lambda>r s. Q1 r s \<and> Q2 r s) (\<lambda>e s. E1 e s \<and> E2 e s)"
+ using assms by (auto intro: PrePostE_I elim: PrePostE_elim)
+
+lemmas PrePostE_conj_conds_consequence = PrePostE_conj_conds[THEN PrePostE_consequence]
+
+lemma PrePostE_post_mp:
+ assumes "PrePostE P m Q' E"
+ and "PrePostE P m (\<lambda>r s. Q' r s \<longrightarrow> Q r s) E"
+ shows "PrePostE P m Q E"
+ using PrePostE_conj_conds[OF assms] by (auto intro: PrePostE_weaken_post)
+
+lemma PrePostE_cong:
+ assumes "\<And>s. P1 s \<longleftrightarrow> P2 s" and "\<And>s. P1 s \<Longrightarrow> m1 s = m2 s" and "\<And>r s. Q1 r s \<longleftrightarrow> Q2 r s"
+ and "\<And>e s. E1 e s \<longleftrightarrow> E2 e s"
+ shows "PrePostE P1 m1 Q1 E1 \<longleftrightarrow> PrePostE P2 m2 Q2 E2"
+ using assms unfolding PrePostE_def PrePost_def
+ by (auto split: result.splits)
+
+lemma PrePostE_True_post[PrePostE_atomI, intro, simp]:
+ "PrePostE P m (\<lambda>_ _. True) (\<lambda>_ _. True)"
+ unfolding PrePost_defs by (auto split: result.splits)
+
+lemma PrePostE_any: "PrePostE (\<lambda>s. \<forall>(r, s') \<in> m s. case r of Value a \<Rightarrow> Q a s' | Ex e \<Rightarrow> E e s') m Q E"
+ by (intro PrePostE_I) auto
+
+lemma PrePostE_returnS[PrePostE_atomI, intro, simp]:
+ "PrePostE (P x) (returnS x) P Q"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_bindS[intro, PrePostE_compositeI]:
+ assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePostE (R a) (f a) Q E"
+ and m: "PrePostE P m R E"
+ shows "PrePostE P (bindS m f) Q E"
+ using assms
+ by (fastforce simp: PrePostE_def cong: result.case_cong)
+
+lemma PrePostE_bindS_ignore:
+ assumes f: "PrePostE R f Q E"
+ and m : "PrePostE P m (\<lambda>_. R) E"
+ shows "PrePostE P (bindS m (\<lambda>_. f)) Q E"
+ using assms by auto
+
+lemma PrePostE_bindS_unit:
+ fixes m :: "('regs, unit, 'e) monadS"
+ assumes f: "PrePostE R (f ()) Q E"
+ and m: "PrePostE P m (\<lambda>_. R) E"
+ shows "PrePostE P (bindS m f) Q E"
+ using assms by auto
+
+lemma PrePostE_readS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_updateS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_if_branch[PrePostE_compositeI]:
+ assumes "b \<Longrightarrow> PrePostE Pf f Q E" and "\<not>b \<Longrightarrow> PrePostE Pg g Q E"
+ shows "PrePostE (if b then Pf else Pg) (if b then f else g) Q E"
+ using assms by (auto)
+
+lemma PrePostE_if:
+ assumes "b \<Longrightarrow> PrePostE P f Q E" and "\<not>b \<Longrightarrow> PrePostE P g Q E"
+ shows "PrePostE P (if b then f else g) Q E"
+ using assms by auto
+
+lemma PrePostE_if_then:
+ assumes "b" and "PrePostE P f Q E"
+ shows "PrePostE P (if b then f else g) Q E"
+ using assms by auto
+
+lemma PrePostE_if_else:
+ assumes "\<not> b" and "PrePostE P g Q E"
+ shows "PrePostE P (if b then f else g) Q E"
+ using assms by auto
+
+lemma PrePostE_prod_cases[PrePostE_compositeI]:
+ assumes "PrePostE P (f (fst x) (snd x)) Q E"
+ shows "PrePostE P (case x of (a, b) \<Rightarrow> f a b) Q E"
+ using assms by (auto split: prod.splits)
+
+lemma PrePostE_option_cases[PrePostE_compositeI]:
+ assumes "\<And>a. PrePostE (PS a) (s a) Q E" and "PrePostE PN n Q E"
+ shows "PrePostE (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q E"
+ using assms by (auto split: option.splits)
+
+lemma PrePostE_sum_cases[PrePostE_compositeI]:
+ assumes "\<And>a. PrePostE (Pl a) (l a) Q E" and "\<And>b. PrePostE (Pr b) (r b) Q E"
+ shows "PrePostE (case x of Inl a \<Rightarrow> Pl a | Inr b \<Rightarrow> Pr b) (case x of Inl a \<Rightarrow> l a | Inr b \<Rightarrow> r b) Q E"
+ using assms by (auto split: sum.splits)
+
+lemma PrePostE_let[PrePostE_compositeI]:
+ assumes "PrePostE P (m y) Q E"
+ shows "PrePostE P (let x = y in m x) Q E"
+ using assms by auto
+
+lemma PrePostE_and_boolS[PrePostE_compositeI]:
+ assumes r: "PrePostE R r Q E"
+ and l: "PrePostE P l (\<lambda>r. if r then R else Q False) E"
+ shows "PrePostE P (and_boolS l r) Q E"
+ using assms unfolding PrePostE_def
+ by (intro PrePost_and_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits)
+
+lemma PrePostE_or_boolS[PrePostE_compositeI]:
+ assumes r: "PrePostE R r Q E"
+ and l: "PrePostE P l (\<lambda>r. if r then Q True else R) E"
+ shows "PrePostE P (or_boolS l r) Q E"
+ using assms unfolding PrePostE_def
+ by (intro PrePost_or_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits)
+
+lemma PrePostE_assert_expS[PrePostE_atomI, intro]:
+ "PrePostE (if c then P () else Q (Failure m)) (assert_expS c m) P Q"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_failS[PrePostE_atomI, intro]:
+ "PrePostE (E (Failure msg)) (failS msg) Q E"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_maybe_failS[PrePostE_atomI]:
+ "PrePostE (\<lambda>s. case v of Some v \<Rightarrow> Q v s | None \<Rightarrow> E (Failure msg) s) (maybe_failS msg v) Q E"
+ by (auto simp: maybe_failS_def split: option.splits)
+
+lemma PrePostE_exitS[PrePostE_atomI, intro]: "PrePostE (E (Failure ''exit'')) (exitS msg) Q E"
+ unfolding exitS_def PrePostE_def PrePost_def failS_def by auto
+
+lemma PrePostE_chooseS[intro, PrePostE_atomI]:
+ "PrePostE (\<lambda>s. \<forall>x \<in> set xs. Q x s) (chooseS xs) Q E"
+ unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre)
+
+lemma PrePostE_throwS[PrePostE_atomI]: "PrePostE (E (Throw e)) (throwS e) Q E"
+ by (intro PrePostE_I) (auto simp: throwS_def)
+
+lemma PrePostE_try_catchS[PrePostE_compositeI]:
+ assumes Ph: "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<Longrightarrow> PrePostE (Ph e) (h e) Q E"
+ and m: "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> Ph e | Failure msg \<Rightarrow> E (Failure msg))"
+ shows "PrePostE P (try_catchS m h) Q E"
+ unfolding PrePostE_def
+proof (intro PrePostI)
+ fix s r s'
+ assume "(r, s') \<in> try_catchS m h s" and P: "P s"
+ then show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'" using m
+ proof (cases rule: try_catchS_cases)
+ case (h e s'')
+ then have "Ph e s''" using P m by (auto elim!: PrePostE_elim)
+ then show ?thesis using Ph[OF h(1)] h(2) by (auto elim!: PrePostE_elim)
+ qed (auto elim!: PrePostE_elim)
+qed
+
+lemma PrePostE_catch_early_returnS[PrePostE_compositeI]:
+ assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw (Inl a) \<Rightarrow> Q a | Throw (Inr e) \<Rightarrow> E (Throw e) | Failure msg \<Rightarrow> E (Failure msg))"
+ shows "PrePostE P (catch_early_returnS m) Q E"
+ unfolding catch_early_returnS_def
+ by (rule PrePostE_try_catchS, rule PrePostE_sum_cases[OF PrePostE_returnS PrePostE_throwS])
+ (auto intro: assms)
+
+lemma PrePostE_early_returnS[PrePostE_atomI]: "PrePostE (E (Throw (Inl r))) (early_returnS r) Q E"
+ by (auto simp: early_returnS_def intro: PrePostE_throwS)
+
+lemma PrePostE_liftRS[PrePostE_compositeI]:
+ assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> E (Throw (Inr e)) | Failure msg \<Rightarrow> E (Failure msg))"
+ shows "PrePostE P (liftRS m) Q E"
+ using assms unfolding liftRS_def by (intro PrePostE_try_catchS[OF PrePostE_throwS])
+
+lemma PrePostE_foreachS_Cons:
+ assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePostE (Q vars') (foreachS xs vars' body) Q E"
+ and "PrePostE (Q vars) (body x vars) Q E"
+ shows "PrePostE (Q vars) (foreachS (x # xs) vars body) Q E"
+ using assms by fastforce
+
+lemma PrePostE_foreachS_invariant:
+ assumes "\<And>x vars. x \<in> set xs \<Longrightarrow> PrePostE (Q vars) (body x vars) Q E"
+ shows "PrePostE (Q vars) (foreachS xs vars body) Q E"
+ using assms unfolding PrePostE_def
+ by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto
+
+lemma PrePostE_untilS:
+ assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, cond, body, s)"
+ and cond: "\<And>vars. PrePostE (Inv' Q vars) (cond vars) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+ and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (Inv' Q) E"
+ shows "PrePostE (Inv Q vars) (untilS vars cond body) Q E"
+proof (unfold PrePostE_def, rule PrePostI)
+ fix s r s'
+ assume Inv_s: "Inv Q vars s" and r: "(r, s') \<in> untilS vars cond body s"
+ with dom[OF Inv_s] cond body
+ show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'"
+ proof (induction vars cond body s rule: untilS.pinduct[case_names Step])
+ case (Step vars cond body s)
+ consider
+ (Value) vars' c sb sc where "(Value vars', sb) \<in> body vars s" and "(Value c, sc) \<in> cond vars' sb"
+ and "if c then r = Value vars' \<and> s' = sc else (r, s') \<in> untilS vars' cond body sc"
+ | (Ex) e where "(Ex e, s') \<in> bindS (body vars) cond s" and "r = Ex e"
+ using Step(1,6)
+ by (auto simp: untilS.psimps returnS_def Ex_bindS_iff elim!: bindS_cases split: if_splits; fastforce)
+ then show ?case
+ proof cases
+ case Value
+ then show ?thesis using Step.IH[OF Value(1,2) _ Step(3,4)] Step(3,4,5)
+ by (auto split: if_splits elim: PrePostE_elim)
+ next
+ case Ex
+ then show ?thesis using Step(3,4,5) by (auto elim!: bindS_cases PrePostE_elim)
+ qed
+ qed
+qed
+
+lemma PrePostE_untilS_pure_cond:
+ assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, returnS \<circ> cond, body, s)"
+ and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+ shows "PrePostE (Inv Q vars) (untilS vars (returnS \<circ> cond) body) Q E"
+ using assms by (intro PrePostE_untilS) (auto simp: comp_def)
+
+lemma PrePostE_liftState_untilM:
+ assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, cond, body)"
+ and cond: "\<And>vars. PrePostE (Inv' Q vars) (liftState r (cond vars)) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E"
+ and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (Inv' Q) E"
+ shows "PrePostE (Inv Q vars) (liftState r (untilM vars cond body)) Q E"
+proof -
+ have domS: "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" if "Inv Q vars s" for s
+ using dom that by (intro untilM_dom_untilS_dom)
+ then have "PrePostE (Inv Q vars) (untilS vars (liftState r \<circ> cond) (liftState r \<circ> body)) Q E"
+ using cond body by (auto intro: PrePostE_untilS simp: comp_def)
+ moreover have "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+ if "Inv Q vars s" for s
+ unfolding liftState_untilM[OF domS[OF that] dom[OF that]] ..
+ ultimately show ?thesis by (auto cong: PrePostE_cong)
+qed
+
+lemma PrePostE_liftState_untilM_pure_cond:
+ assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, return \<circ> cond, body)"
+ and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E"
+ shows "PrePostE (Inv Q vars) (liftState r (untilM vars (return \<circ> cond) body)) Q E"
+ using assms by (intro PrePostE_liftState_untilM) (auto simp: comp_def liftState_simp)
+
+lemma PrePostE_choose_boolS_any[PrePostE_atomI]:
+ "PrePostE (\<lambda>s. \<forall>b. Q b s)
+ (choose_boolS unit) Q E"
+ unfolding choose_boolS_def seqS_def
+ by (auto intro: PrePostE_strengthen_pre)
+
+lemma PrePostE_bool_of_bitU_nondetS_any:
+ "PrePostE (\<lambda>s. \<forall>b. Q b s) (bool_of_bitU_nondetS b) Q E"
+ unfolding bool_of_bitU_nondetS_def undefined_boolS_def
+ by (cases b; simp; rule PrePostE_strengthen_pre, rule PrePostE_atomI) auto
+
+lemma PrePostE_bools_of_bits_nondetS_any:
+ "PrePostE (\<lambda>s. \<forall>bs. Q bs s) (bools_of_bits_nondetS bs) Q E"
+ unfolding bools_of_bits_nondetS_def
+ by (rule PrePostE_weaken_post[where B = "\<lambda>_ s. \<forall>bs. Q bs s"], rule PrePostE_strengthen_pre,
+ (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS
+ PrePostE_bool_of_bitU_nondetS_any)+)
+ auto
+
+lemma PrePostE_choose_boolsS_any:
+ "PrePostE (\<lambda>s. \<forall>bs. Q bs s) (choose_boolsS n) Q E"
+ unfolding choose_boolsS_def genlistS_def Let_def
+ by (rule PrePostE_weaken_post[where B = "\<lambda>_ s. \<forall>bs. Q bs s"], rule PrePostE_strengthen_pre,
+ (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS
+ PrePostE_choose_boolS_any)+)
+ auto
+
+lemma PrePostE_internal_pick:
+ "xs \<noteq> [] \<Longrightarrow> PrePostE (\<lambda>s. \<forall>x \<in> set xs. Q x s) (internal_pickS xs) Q E"
+ unfolding internal_pickS_def Let_def
+ by (rule PrePostE_strengthen_pre,
+ (rule PrePostE_compositeI PrePostE_atomI PrePostE_choose_boolsS_any)+)
+ (auto split: option.splits)
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/ROOT b/prover_snapshots/isabelle/lib/sail/ROOT
new file mode 100644
index 0000000..4ac8690
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/ROOT
@@ -0,0 +1,11 @@
+session "Sail" = "LEM" +
+ sessions
+ "HOL-Eisbach"
+ theories
+ Sail2_values_lemmas
+ Sail2_prompt
+ Sail2_state_lemmas
+ Sail2_operators_mwords_lemmas
+ Sail2_operators_bitlists
+ Sail2_string
+ Hoare
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy b/prover_snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
new file mode 100644
index 0000000..ad29747
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy
@@ -0,0 +1,576 @@
+chapter \<open>Generated by Lem from \<open>../../src/lem_interp/sail2_instr_kinds.lem\<close>.\<close>
+
+theory "Sail2_instr_kinds"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+
+begin
+
+\<comment> \<open>\<open>========================================================================\<close>\<close>
+\<comment> \<open>\<open> Sail \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> Copyright (c) 2013-2017 \<close>\<close>
+\<comment> \<open>\<open> Kathyrn Gray \<close>\<close>
+\<comment> \<open>\<open> Shaked Flur \<close>\<close>
+\<comment> \<open>\<open> Stephen Kell \<close>\<close>
+\<comment> \<open>\<open> Gabriel Kerneis \<close>\<close>
+\<comment> \<open>\<open> Robert Norton-Wright \<close>\<close>
+\<comment> \<open>\<open> Christopher Pulte \<close>\<close>
+\<comment> \<open>\<open> Peter Sewell \<close>\<close>
+\<comment> \<open>\<open> Alasdair Armstrong \<close>\<close>
+\<comment> \<open>\<open> Brian Campbell \<close>\<close>
+\<comment> \<open>\<open> Thomas Bauereiss \<close>\<close>
+\<comment> \<open>\<open> Anthony Fox \<close>\<close>
+\<comment> \<open>\<open> Jon French \<close>\<close>
+\<comment> \<open>\<open> Dominic Mulligan \<close>\<close>
+\<comment> \<open>\<open> Stephen Kell \<close>\<close>
+\<comment> \<open>\<open> Mark Wassell \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> All rights reserved. \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> This software was developed by the University of Cambridge Computer \<close>\<close>
+\<comment> \<open>\<open> Laboratory as part of the Rigorous Engineering of Mainstream Systems \<close>\<close>
+\<comment> \<open>\<open> (REMS) project, funded by EPSRC grant EP/K008528/1. \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> Redistribution and use in source and binary forms, with or without \<close>\<close>
+\<comment> \<open>\<open> modification, are permitted provided that the following conditions \<close>\<close>
+\<comment> \<open>\<open> are met: \<close>\<close>
+\<comment> \<open>\<open> 1. Redistributions of source code must retain the above copyright \<close>\<close>
+\<comment> \<open>\<open> notice, this list of conditions and the following disclaimer. \<close>\<close>
+\<comment> \<open>\<open> 2. Redistributions in binary form must reproduce the above copyright \<close>\<close>
+\<comment> \<open>\<open> notice, this list of conditions and the following disclaimer in \<close>\<close>
+\<comment> \<open>\<open> the documentation and/or other materials provided with the \<close>\<close>
+\<comment> \<open>\<open> distribution. \<close>\<close>
+\<comment> \<open>\<open> \<close>\<close>
+\<comment> \<open>\<open> THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' \<close>\<close>
+\<comment> \<open>\<open> AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED \<close>\<close>
+\<comment> \<open>\<open> TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A \<close>\<close>
+\<comment> \<open>\<open> PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR \<close>\<close>
+\<comment> \<open>\<open> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \<close>\<close>
+\<comment> \<open>\<open> SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \<close>\<close>
+\<comment> \<open>\<open> LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF \<close>\<close>
+\<comment> \<open>\<open> USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND \<close>\<close>
+\<comment> \<open>\<open> ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \<close>\<close>
+\<comment> \<open>\<open> OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT \<close>\<close>
+\<comment> \<open>\<open> OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \<close>\<close>
+\<comment> \<open>\<open> SUCH DAMAGE. \<close>\<close>
+\<comment> \<open>\<open>========================================================================\<close>\<close>
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+
+
+record 'a EnumerationType_class=
+
+ toNat_method ::" 'a \<Rightarrow> nat "
+
+
+
+
+\<comment> \<open>\<open>val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering\<close>\<close>
+definition enumeration_typeCompare :: " 'a EnumerationType_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where
+ " enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a e1 e2 = (
+ (genericCompare (<) (=) (
+ (toNat_method dict_Sail2_instr_kinds_EnumerationType_a) e1) ((toNat_method dict_Sail2_instr_kinds_EnumerationType_a) e2)))"
+ for dict_Sail2_instr_kinds_EnumerationType_a :: " 'a EnumerationType_class "
+ and e1 :: " 'a "
+ and e2 :: " 'a "
+
+
+
+definition instance_Basic_classes_Ord_var_dict :: " 'a EnumerationType_class \<Rightarrow> 'a Ord_class " where
+ " instance_Basic_classes_Ord_var_dict dict_Sail2_instr_kinds_EnumerationType_a = ((|
+
+ compare_method =
+ (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a),
+
+ isLess_method = (\<lambda> r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LT),
+
+ isLessEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT),
+
+ isGreater_method = (\<lambda> r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GT),
+
+ isGreaterEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare
+ dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )"
+ for dict_Sail2_instr_kinds_EnumerationType_a :: " 'a EnumerationType_class "
+
+
+
+\<comment> \<open>\<open> Data structures for building up instructions \<close>\<close>
+
+\<comment> \<open>\<open> careful: changes in the read/write/barrier kinds have to be
+ reflected in deep_shallow_convert \<close>\<close>
+datatype read_kind =
+ \<comment> \<open>\<open> common reads \<close>\<close>
+ Read_plain
+ \<comment> \<open>\<open> Power reads \<close>\<close>
+ | Read_reserve
+ \<comment> \<open>\<open> AArch64 reads \<close>\<close>
+ | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+ \<comment> \<open>\<open> RISC-V reads \<close>\<close>
+ | Read_RISCV_acquire | Read_RISCV_strong_acquire
+ | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+ | Read_RISCV_reserved_strong_acquire
+ \<comment> \<open>\<open> x86 reads \<close>\<close>
+ | Read_X86_locked \<comment> \<open>\<open> the read part of a lock'd instruction (rmw) \<close>\<close>
+
+definition instance_Show_Show_Sail2_instr_kinds_read_kind_dict :: "(read_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_read_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ Read_plain => (''Read_plain'')
+ | Read_reserve => (''Read_reserve'')
+ | Read_acquire => (''Read_acquire'')
+ | Read_exclusive => (''Read_exclusive'')
+ | Read_exclusive_acquire => (''Read_exclusive_acquire'')
+ | Read_stream => (''Read_stream'')
+ | Read_RISCV_acquire => (''Read_RISCV_acquire'')
+ | Read_RISCV_strong_acquire => (''Read_RISCV_strong_acquire'')
+ | Read_RISCV_reserved => (''Read_RISCV_reserved'')
+ | Read_RISCV_reserved_acquire => (''Read_RISCV_reserved_acquire'')
+ | Read_RISCV_reserved_strong_acquire => (''Read_RISCV_reserved_strong_acquire'')
+ | Read_X86_locked => (''Read_X86_locked'')
+ ))|) )"
+
+
+datatype write_kind =
+ \<comment> \<open>\<open> common writes \<close>\<close>
+ Write_plain
+ \<comment> \<open>\<open> Power writes \<close>\<close>
+ | Write_conditional
+ \<comment> \<open>\<open> AArch64 writes \<close>\<close>
+ | Write_release | Write_exclusive | Write_exclusive_release
+ \<comment> \<open>\<open> RISC-V \<close>\<close>
+ | Write_RISCV_release | Write_RISCV_strong_release
+ | Write_RISCV_conditional | Write_RISCV_conditional_release
+ | Write_RISCV_conditional_strong_release
+ \<comment> \<open>\<open> x86 writes \<close>\<close>
+ | Write_X86_locked \<comment> \<open>\<open> the write part of a lock'd instruction (rmw) \<close>\<close>
+
+definition instance_Show_Show_Sail2_instr_kinds_write_kind_dict :: "(write_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_write_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ Write_plain => (''Write_plain'')
+ | Write_conditional => (''Write_conditional'')
+ | Write_release => (''Write_release'')
+ | Write_exclusive => (''Write_exclusive'')
+ | Write_exclusive_release => (''Write_exclusive_release'')
+ | Write_RISCV_release => (''Write_RISCV_release'')
+ | Write_RISCV_strong_release => (''Write_RISCV_strong_release'')
+ | Write_RISCV_conditional => (''Write_RISCV_conditional'')
+ | Write_RISCV_conditional_release => (''Write_RISCV_conditional_release'')
+ | Write_RISCV_conditional_strong_release => (''Write_RISCV_conditional_strong_release'')
+ | Write_X86_locked => (''Write_X86_locked'')
+ ))|) )"
+
+
+datatype barrier_kind =
+ \<comment> \<open>\<open> Power barriers \<close>\<close>
+ Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+ \<comment> \<open>\<open> AArch64 barriers \<close>\<close>
+ | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+ | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+ | Barrier_TM_COMMIT
+ \<comment> \<open>\<open> MIPS barriers \<close>\<close>
+ | Barrier_MIPS_SYNC
+ \<comment> \<open>\<open> RISC-V barriers \<close>\<close>
+ | Barrier_RISCV_rw_rw
+ | Barrier_RISCV_r_rw
+ | Barrier_RISCV_r_r
+ | Barrier_RISCV_rw_w
+ | Barrier_RISCV_w_w
+ | Barrier_RISCV_w_rw
+ | Barrier_RISCV_rw_r
+ | Barrier_RISCV_r_w
+ | Barrier_RISCV_w_r
+ | Barrier_RISCV_tso
+ | Barrier_RISCV_i
+ \<comment> \<open>\<open> X86 \<close>\<close>
+ | Barrier_x86_MFENCE
+
+
+definition instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict :: "(barrier_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ Barrier_Sync => (''Barrier_Sync'')
+ | Barrier_LwSync => (''Barrier_LwSync'')
+ | Barrier_Eieio => (''Barrier_Eieio'')
+ | Barrier_Isync => (''Barrier_Isync'')
+ | Barrier_DMB => (''Barrier_DMB'')
+ | Barrier_DMB_ST => (''Barrier_DMB_ST'')
+ | Barrier_DMB_LD => (''Barrier_DMB_LD'')
+ | Barrier_DSB => (''Barrier_DSB'')
+ | Barrier_DSB_ST => (''Barrier_DSB_ST'')
+ | Barrier_DSB_LD => (''Barrier_DSB_LD'')
+ | Barrier_ISB => (''Barrier_ISB'')
+ | Barrier_TM_COMMIT => (''Barrier_TM_COMMIT'')
+ | Barrier_MIPS_SYNC => (''Barrier_MIPS_SYNC'')
+ | Barrier_RISCV_rw_rw => (''Barrier_RISCV_rw_rw'')
+ | Barrier_RISCV_r_rw => (''Barrier_RISCV_r_rw'')
+ | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'')
+ | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'')
+ | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'')
+ | Barrier_RISCV_w_rw => (''Barrier_RISCV_w_rw'')
+ | Barrier_RISCV_rw_r => (''Barrier_RISCV_rw_r'')
+ | Barrier_RISCV_r_w => (''Barrier_RISCV_r_w'')
+ | Barrier_RISCV_w_r => (''Barrier_RISCV_w_r'')
+ | Barrier_RISCV_tso => (''Barrier_RISCV_tso'')
+ | Barrier_RISCV_i => (''Barrier_RISCV_i'')
+ | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'')
+ ))|) )"
+
+
+datatype trans_kind =
+ \<comment> \<open>\<open> AArch64 \<close>\<close>
+ Transaction_start | Transaction_commit | Transaction_abort
+
+definition instance_Show_Show_Sail2_instr_kinds_trans_kind_dict :: "(trans_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_trans_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ Transaction_start => (''Transaction_start'')
+ | Transaction_commit => (''Transaction_commit'')
+ | Transaction_abort => (''Transaction_abort'')
+ ))|) )"
+
+
+\<comment> \<open>\<open> cache maintenance instructions \<close>\<close>
+datatype cache_op_kind =
+ \<comment> \<open>\<open> AArch64 DC \<close>\<close>
+ Cache_op_D_IVAC | Cache_op_D_ISW | Cache_op_D_CSW | Cache_op_D_CISW
+ | Cache_op_D_ZVA | Cache_op_D_CVAC | Cache_op_D_CVAU | Cache_op_D_CIVAC
+ \<comment> \<open>\<open> AArch64 IC \<close>\<close>
+ | Cache_op_I_IALLUIS | Cache_op_I_IALLU | Cache_op_I_IVAU
+
+definition instance_Show_Show_Sail2_instr_kinds_cache_op_kind_dict :: "(cache_op_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_cache_op_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ Cache_op_D_IVAC => (''Cache_op_D_IVAC'')
+ | Cache_op_D_ISW => (''Cache_op_D_ISW'')
+ | Cache_op_D_CSW => (''Cache_op_D_CSW'')
+ | Cache_op_D_CISW => (''Cache_op_D_CISW'')
+ | Cache_op_D_ZVA => (''Cache_op_D_ZVA'')
+ | Cache_op_D_CVAC => (''Cache_op_D_CVAC'')
+ | Cache_op_D_CVAU => (''Cache_op_D_CVAU'')
+ | Cache_op_D_CIVAC => (''Cache_op_D_CIVAC'')
+ | Cache_op_I_IALLUIS => (''Cache_op_I_IALLUIS'')
+ | Cache_op_I_IALLU => (''Cache_op_I_IALLU'')
+ | Cache_op_I_IVAU => (''Cache_op_I_IVAU'')
+ ))|) )"
+
+
+datatype instruction_kind =
+ IK_barrier " barrier_kind "
+ | IK_mem_read " read_kind "
+ | IK_mem_write " write_kind "
+ | IK_mem_rmw " (read_kind * write_kind)"
+ | IK_branch " unit "\<comment> \<open>\<open> this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+ indirect/computed-branch (single nia of kind NIA_indirect_address)
+ and branch/jump (single nia of kind NIA_concrete_address) \<close>\<close>
+ | IK_trans " trans_kind "
+ | IK_simple " unit "
+ | IK_cache_op " cache_op_kind "
+
+
+definition instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict :: "(instruction_kind)Show_class " where
+ " instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict = ((|
+
+ show_method = (\<lambda>x .
+ (case x of
+ IK_barrier barrier_kind => (''IK_barrier '') @
+ (((\<lambda>x . (case x of
+ Barrier_Sync =>
+ (''Barrier_Sync'')
+ | Barrier_LwSync =>
+ (''Barrier_LwSync'')
+ | Barrier_Eieio =>
+ (''Barrier_Eieio'')
+ | Barrier_Isync =>
+ (''Barrier_Isync'')
+ | Barrier_DMB =>
+ (''Barrier_DMB'')
+ | Barrier_DMB_ST =>
+ (''Barrier_DMB_ST'')
+ | Barrier_DMB_LD =>
+ (''Barrier_DMB_LD'')
+ | Barrier_DSB =>
+ (''Barrier_DSB'')
+ | Barrier_DSB_ST =>
+ (''Barrier_DSB_ST'')
+ | Barrier_DSB_LD =>
+ (''Barrier_DSB_LD'')
+ | Barrier_ISB =>
+ (''Barrier_ISB'')
+ | Barrier_TM_COMMIT =>
+ (''Barrier_TM_COMMIT'')
+ | Barrier_MIPS_SYNC =>
+ (''Barrier_MIPS_SYNC'')
+ | Barrier_RISCV_rw_rw =>
+ (''Barrier_RISCV_rw_rw'')
+ | Barrier_RISCV_r_rw =>
+ (''Barrier_RISCV_r_rw'')
+ | Barrier_RISCV_r_r =>
+ (''Barrier_RISCV_r_r'')
+ | Barrier_RISCV_rw_w =>
+ (''Barrier_RISCV_rw_w'')
+ | Barrier_RISCV_w_w =>
+ (''Barrier_RISCV_w_w'')
+ | Barrier_RISCV_w_rw =>
+ (''Barrier_RISCV_w_rw'')
+ | Barrier_RISCV_rw_r =>
+ (''Barrier_RISCV_rw_r'')
+ | Barrier_RISCV_r_w =>
+ (''Barrier_RISCV_r_w'')
+ | Barrier_RISCV_w_r =>
+ (''Barrier_RISCV_w_r'')
+ | Barrier_RISCV_tso =>
+ (''Barrier_RISCV_tso'')
+ | Barrier_RISCV_i =>
+ (''Barrier_RISCV_i'')
+ | Barrier_x86_MFENCE =>
+ (''Barrier_x86_MFENCE'')
+ )) barrier_kind))
+ | IK_mem_read read_kind => (''IK_mem_read '') @
+ (((\<lambda>x . (case x of
+ Read_plain =>
+ (''Read_plain'')
+ | Read_reserve =>
+ (''Read_reserve'')
+ | Read_acquire =>
+ (''Read_acquire'')
+ | Read_exclusive =>
+ (''Read_exclusive'')
+ | Read_exclusive_acquire =>
+ (''Read_exclusive_acquire'')
+ | Read_stream =>
+ (''Read_stream'')
+ | Read_RISCV_acquire =>
+ (''Read_RISCV_acquire'')
+ | Read_RISCV_strong_acquire =>
+ (''Read_RISCV_strong_acquire'')
+ | Read_RISCV_reserved =>
+ (''Read_RISCV_reserved'')
+ | Read_RISCV_reserved_acquire =>
+ (''Read_RISCV_reserved_acquire'')
+ | Read_RISCV_reserved_strong_acquire =>
+ (''Read_RISCV_reserved_strong_acquire'')
+ | Read_X86_locked =>
+ (''Read_X86_locked'')
+ )) read_kind))
+ | IK_mem_write write_kind => (''IK_mem_write '') @
+ (((\<lambda>x . (case x of
+ Write_plain =>
+ (''Write_plain'')
+ | Write_conditional =>
+ (''Write_conditional'')
+ | Write_release =>
+ (''Write_release'')
+ | Write_exclusive =>
+ (''Write_exclusive'')
+ | Write_exclusive_release =>
+ (''Write_exclusive_release'')
+ | Write_RISCV_release =>
+ (''Write_RISCV_release'')
+ | Write_RISCV_strong_release =>
+ (''Write_RISCV_strong_release'')
+ | Write_RISCV_conditional =>
+ (''Write_RISCV_conditional'')
+ | Write_RISCV_conditional_release =>
+ (''Write_RISCV_conditional_release'')
+ | Write_RISCV_conditional_strong_release =>
+ (''Write_RISCV_conditional_strong_release'')
+ | Write_X86_locked =>
+ (''Write_X86_locked'')
+ )) write_kind))
+ | IK_mem_rmw (r, w) => (''IK_mem_rmw '') @
+ ((((\<lambda>x . (case x of
+ Read_plain => (''Read_plain'')
+ | Read_reserve => (''Read_reserve'')
+ | Read_acquire => (''Read_acquire'')
+ | Read_exclusive =>
+ (''Read_exclusive'')
+ | Read_exclusive_acquire =>
+ (''Read_exclusive_acquire'')
+ | Read_stream => (''Read_stream'')
+ | Read_RISCV_acquire =>
+ (''Read_RISCV_acquire'')
+ | Read_RISCV_strong_acquire =>
+ (''Read_RISCV_strong_acquire'')
+ | Read_RISCV_reserved =>
+ (''Read_RISCV_reserved'')
+ | Read_RISCV_reserved_acquire =>
+ (''Read_RISCV_reserved_acquire'')
+ | Read_RISCV_reserved_strong_acquire =>
+ (''Read_RISCV_reserved_strong_acquire'')
+ | Read_X86_locked =>
+ (''Read_X86_locked'')
+ )) r)) @
+ (('' '') @
+ (((\<lambda>x . (case x of
+ Write_plain =>
+ (''Write_plain'')
+ | Write_conditional =>
+ (''Write_conditional'')
+ | Write_release =>
+ (''Write_release'')
+ | Write_exclusive =>
+ (''Write_exclusive'')
+ | Write_exclusive_release =>
+ (''Write_exclusive_release'')
+ | Write_RISCV_release =>
+ (''Write_RISCV_release'')
+ | Write_RISCV_strong_release =>
+ (''Write_RISCV_strong_release'')
+ | Write_RISCV_conditional =>
+ (''Write_RISCV_conditional'')
+ | Write_RISCV_conditional_release =>
+ (''Write_RISCV_conditional_release'')
+ | Write_RISCV_conditional_strong_release =>
+ (''Write_RISCV_conditional_strong_release'')
+ | Write_X86_locked =>
+ (''Write_X86_locked'')
+ )) w))))
+ | IK_branch _ => (''IK_branch'')
+ | IK_trans trans_kind => (''IK_trans '') @
+ (((\<lambda>x . (case x of
+ Transaction_start =>
+ (''Transaction_start'')
+ | Transaction_commit =>
+ (''Transaction_commit'')
+ | Transaction_abort =>
+ (''Transaction_abort'')
+ )) trans_kind))
+ | IK_simple _ => (''IK_simple'')
+ | IK_cache_op cache_kind => (''IK_cache_op '') @
+ (((\<lambda>x . (case x of
+ Cache_op_D_IVAC =>
+ (''Cache_op_D_IVAC'')
+ | Cache_op_D_ISW =>
+ (''Cache_op_D_ISW'')
+ | Cache_op_D_CSW =>
+ (''Cache_op_D_CSW'')
+ | Cache_op_D_CISW =>
+ (''Cache_op_D_CISW'')
+ | Cache_op_D_ZVA =>
+ (''Cache_op_D_ZVA'')
+ | Cache_op_D_CVAC =>
+ (''Cache_op_D_CVAC'')
+ | Cache_op_D_CVAU =>
+ (''Cache_op_D_CVAU'')
+ | Cache_op_D_CIVAC =>
+ (''Cache_op_D_CIVAC'')
+ | Cache_op_I_IALLUIS =>
+ (''Cache_op_I_IALLUIS'')
+ | Cache_op_I_IALLU =>
+ (''Cache_op_I_IALLU'')
+ | Cache_op_I_IVAU =>
+ (''Cache_op_I_IVAU'')
+ )) cache_kind))
+ ))|) )"
+
+
+
+definition read_is_exclusive :: " read_kind \<Rightarrow> bool " where
+ " read_is_exclusive = ( \<lambda>x .
+ (case x of
+ Read_plain => False
+ | Read_reserve => True
+ | Read_acquire => False
+ | Read_exclusive => True
+ | Read_exclusive_acquire => True
+ | Read_stream => False
+ | Read_RISCV_acquire => False
+ | Read_RISCV_strong_acquire => False
+ | Read_RISCV_reserved => True
+ | Read_RISCV_reserved_acquire => True
+ | Read_RISCV_reserved_strong_acquire => True
+ | Read_X86_locked => True
+ ) )"
+
+
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict :: "(read_kind)EnumerationType_class " where
+ " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict = ((|
+
+ toNat_method = (\<lambda>x .
+ (case x of
+ Read_plain =>( 0 :: nat)
+ | Read_reserve =>( 1 :: nat)
+ | Read_acquire =>( 2 :: nat)
+ | Read_exclusive =>( 3 :: nat)
+ | Read_exclusive_acquire =>( 4 :: nat)
+ | Read_stream =>( 5 :: nat)
+ | Read_RISCV_acquire =>( 6 :: nat)
+ | Read_RISCV_strong_acquire =>( 7 :: nat)
+ | Read_RISCV_reserved =>( 8 :: nat)
+ | Read_RISCV_reserved_acquire =>( 9 :: nat)
+ | Read_RISCV_reserved_strong_acquire =>( 10 :: nat)
+ | Read_X86_locked =>( 11 :: nat)
+ ))|) )"
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict :: "(write_kind)EnumerationType_class " where
+ " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict = ((|
+
+ toNat_method = (\<lambda>x .
+ (case x of
+ Write_plain =>( 0 :: nat)
+ | Write_conditional =>( 1 :: nat)
+ | Write_release =>( 2 :: nat)
+ | Write_exclusive =>( 3 :: nat)
+ | Write_exclusive_release =>( 4 :: nat)
+ | Write_RISCV_release =>( 5 :: nat)
+ | Write_RISCV_strong_release =>( 6 :: nat)
+ | Write_RISCV_conditional =>( 7 :: nat)
+ | Write_RISCV_conditional_release =>( 8 :: nat)
+ | Write_RISCV_conditional_strong_release =>( 9 :: nat)
+ | Write_X86_locked =>( 10 :: nat)
+ ))|) )"
+
+
+definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict :: "(barrier_kind)EnumerationType_class " where
+ " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict = ((|
+
+ toNat_method = (\<lambda>x .
+ (case x of
+ Barrier_Sync =>( 0 :: nat)
+ | Barrier_LwSync =>( 1 :: nat)
+ | Barrier_Eieio =>( 2 :: nat)
+ | Barrier_Isync =>( 3 :: nat)
+ | Barrier_DMB =>( 4 :: nat)
+ | Barrier_DMB_ST =>( 5 :: nat)
+ | Barrier_DMB_LD =>( 6 :: nat)
+ | Barrier_DSB =>( 7 :: nat)
+ | Barrier_DSB_ST =>( 8 :: nat)
+ | Barrier_DSB_LD =>( 9 :: nat)
+ | Barrier_ISB =>( 10 :: nat)
+ | Barrier_TM_COMMIT =>( 11 :: nat)
+ | Barrier_MIPS_SYNC =>( 12 :: nat)
+ | Barrier_RISCV_rw_rw =>( 13 :: nat)
+ | Barrier_RISCV_r_rw =>( 14 :: nat)
+ | Barrier_RISCV_r_r =>( 15 :: nat)
+ | Barrier_RISCV_rw_w =>( 16 :: nat)
+ | Barrier_RISCV_w_w =>( 17 :: nat)
+ | Barrier_RISCV_w_rw =>( 18 :: nat)
+ | Barrier_RISCV_rw_r =>( 19 :: nat)
+ | Barrier_RISCV_r_w =>( 20 :: nat)
+ | Barrier_RISCV_w_r =>( 21 :: nat)
+ | Barrier_RISCV_tso =>( 22 :: nat)
+ | Barrier_RISCV_i =>( 23 :: nat)
+ | Barrier_x86_MFENCE =>( 24 :: nat)
+ ))|) )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_operators.thy b/prover_snapshots/isabelle/lib/sail/Sail2_operators.thy
new file mode 100644
index 0000000..b3b5d02
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_operators.thy
@@ -0,0 +1,326 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_operators.lem\<close>.\<close>
+
+theory "Sail2_operators"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "LEM.Lem_machine_word"
+ "Sail2_values"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Machine_word\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+
+\<comment> \<open>\<open>** Bit vector operations \<close>\<close>
+
+\<comment> \<open>\<open>val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU\<close>\<close>
+definition concat_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow>(bitU)list " where
+ " concat_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r = ( (
+ (bits_of_method dict_Sail2_values_Bitvector_a) l @(bits_of_method dict_Sail2_values_Bitvector_b) r))"
+
+
+\<comment> \<open>\<open>val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU\<close>\<close>
+definition cons_bv :: " 'a Bitvector_class \<Rightarrow> bitU \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " cons_bv dict_Sail2_values_Bitvector_a b v = ( b #
+ (bits_of_method dict_Sail2_values_Bitvector_a) v )"
+
+
+\<comment> \<open>\<open>val cast_unit_bv : bitU -> list bitU\<close>\<close>
+definition cast_unit_bv :: " bitU \<Rightarrow>(bitU)list " where
+ " cast_unit_bv b = ( [b])"
+
+
+\<comment> \<open>\<open>val bv_of_bit : integer -> bitU -> list bitU\<close>\<close>
+definition bv_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " bv_of_bit len b = ( extz_bits len [b])"
+
+
+definition most_significant :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU " where
+ " most_significant dict_Sail2_values_Bitvector_a v = ( (case
+ (bits_of_method dict_Sail2_values_Bitvector_a) v of
+ b # _ => b
+ | _ => B0 \<comment> \<open>\<open> Treat empty bitvector as all zeros \<close>\<close>
+ ))"
+
+
+definition get_max_representable_in :: " bool \<Rightarrow> int \<Rightarrow> int " where
+ " get_max_representable_in sign (n :: int) = (
+ if (n =( 64 :: int)) then (case sign of True => max_64 | False => max_64u )
+ else if (n=( 32 :: int)) then (case sign of True => max_32 | False => max_32u )
+ else if (n=( 8 :: int)) then max_8
+ else if (n=( 5 :: int)) then max_5
+ else (case sign of True => (( 2 :: int))^ ((nat (abs ( n))) -( 1 :: nat))
+ | False => (( 2 :: int))^ (nat (abs ( n)))
+ ))"
+
+
+definition get_min_representable_in :: " 'a \<Rightarrow> int \<Rightarrow> int " where
+ " get_min_representable_in _ (n :: int) = (
+ if n =( 64 :: int) then min_64
+ else if n =( 32 :: int) then min_32
+ else if n =( 8 :: int) then min_8
+ else if n =( 5 :: int) then min_5
+ else( 0 :: int) - ((( 2 :: int))^ (nat (abs ( n)))))"
+
+
+\<comment> \<open>\<open>val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a\<close>\<close>
+definition arith_op_bv_int :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'a " where
+ " arith_op_bv_int dict_Sail2_values_Bitvector_a op1 sign l r = (
+ (let r' = ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) l) r) in (arith_op_bv_method dict_Sail2_values_Bitvector_a) op1 sign l r'))"
+
+
+\<comment> \<open>\<open>val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a\<close>\<close>
+definition arith_op_int_bv :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a " where
+ " arith_op_int_bv dict_Sail2_values_Bitvector_a op1 sign l r = (
+ (let l' = ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) r) l) in (arith_op_bv_method dict_Sail2_values_Bitvector_a) op1 sign l' r))"
+
+
+definition arith_op_bv_bool :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where
+ " arith_op_bv_bool dict_Sail2_values_Bitvector_a op1 sign l r = ( arith_op_bv_int
+ dict_Sail2_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))"
+
+definition arith_op_bv_bit :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where
+ " arith_op_bv_bit dict_Sail2_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a op1 sign l) (bool_of_bitU r))"
+
+
+\<comment> \<open>\<open> TODO (or just omit and define it per spec if needed)
+val arith_op_overflow_bv : forall 'a. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv op sign size l r =
+ let len = length l in
+ let act_size = len * size in
+ match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with
+ | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) ->
+ let n = op l_sign r_sign in
+ let n_unsign = op l_unsign r_unsign in
+ let correct_size = of_int act_size n in
+ let one_more_size_u = bits_of_int (act_size + 1) n_unsign in
+ let overflow =
+ if n <= get_max_representable_in sign len &&
+ n >= get_min_representable_in sign len
+ then B0 else B1 in
+ let c_out = most_significant one_more_size_u in
+ (correct_size,overflow,c_out)
+ | (_, _, _, _) ->
+ (repeat [BU] act_size, BU, BU)
+ end
+
+let add_overflow_bv = arith_op_overflow_bv integerAdd false 1
+let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1
+let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1
+let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1
+let mult_overflow_bv = arith_op_overflow_bv integerMult false 2
+let mults_overflow_bv = arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU)
+let arith_op_overflow_bv_bit op sign size l r_bit =
+ let act_size = length l * size in
+ match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with
+ | (Just l', Just l_u, false) ->
+ let (n, nu, changed) = match r_bit with
+ | B1 -> (op l' 1, op l_u 1, true)
+ | B0 -> (l', l_u, false)
+ | BU -> \<open> unreachable due to check above \<close>
+ failwith "arith_op_overflow_bv_bit applied to undefined bit"
+ end in
+ let correct_size = of_int act_size n in
+ let one_larger = bits_of_int (act_size + 1) nu in
+ let overflow =
+ if changed
+ then
+ if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+ then B0 else B1
+ else B0 in
+ (correct_size, overflow, most_significant one_larger)
+ | (_, _, _) ->
+ (repeat [BU] act_size, BU, BU)
+ end
+
+let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1
+let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1
+let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1
+let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1\<close>\<close>
+
+datatype shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
+
+definition invert_shift :: " shift \<Rightarrow> shift " where
+ " invert_shift = ( \<lambda>x .
+ (case x of
+ LL_shift => RR_shift
+ | RR_shift => LL_shift
+ | RR_shift_arith => LL_shift
+ | LL_rot => RR_rot
+ | RR_rot => LL_rot
+ ) )"
+
+
+\<comment> \<open>\<open>val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU\<close>\<close>
+definition shift_op_bv :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " shift_op_bv dict_Sail2_values_Bitvector_a op1 v n = (
+ (let v = ((bits_of_method dict_Sail2_values_Bitvector_a) v) in
+ if n =( 0 :: int) then v else
+ (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in
+ (case op1 of
+ LL_shift =>
+ subrange_list True v n (int (List.length v) -( 1 :: int)) @ repeat [B0] n
+ | RR_shift =>
+ repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
+ | RR_shift_arith =>
+ repeat [most_significant
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int))
+ | LL_rot =>
+ subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int))
+ | RR_rot =>
+ subrange_list False v(( 0 :: int)) (n -( 1 :: int)) @ subrange_list False v n (int (List.length v) -( 1 :: int))
+ ))))"
+
+
+definition shiftl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " shiftl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_shift )"
+ \<comment> \<open>\<open>"<<"\<close>\<close>
+definition shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv
+ dict_Sail2_values_Bitvector_a RR_shift )"
+ \<comment> \<open>\<open>">>"\<close>\<close>
+definition arith_shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " arith_shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv
+ dict_Sail2_values_Bitvector_a RR_shift_arith )"
+
+definition rotl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " rotl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_rot )"
+ \<comment> \<open>\<open>"<<<"\<close>\<close>
+definition rotr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " rotr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv
+ dict_Sail2_values_Bitvector_a LL_rot )"
+ \<comment> \<open>\<open>">>>"\<close>\<close>
+
+definition shiftl_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " shiftl_mword w n = ( w << (nat_of_int n))"
+
+definition shiftr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " shiftr_mword w n = ( w >> (nat_of_int n))"
+
+definition arith_shiftr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " arith_shiftr_mword w n = ( w >>> (nat_of_int n))"
+
+definition rotl_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " rotl_mword w n = ( Word.word_rotl (nat_of_int n) w )"
+
+definition rotr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " rotr_mword w n = ( Word.word_rotr (nat_of_int n) w )"
+
+
+fun arith_op_no0 :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)option " where
+ " arith_op_no0 (op1 :: int \<Rightarrow> int \<Rightarrow> int) l r = (
+ if r =( 0 :: int)
+ then None
+ else Some (op1 l r))"
+
+
+\<comment> \<open>\<open>val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+ (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b\<close>\<close>
+definition arith_op_bv_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'b option " where
+ " arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = (
+ Option.bind (int_of_bv
+ dict_Sail2_values_Bitvector_a sign l) (\<lambda> l' .
+ Option.bind (int_of_bv
+ dict_Sail2_values_Bitvector_a sign r) (\<lambda> r' .
+ if r' =( 0 :: int) then None else Some (
+ (of_int_method dict_Sail2_values_Bitvector_b) ((length_method dict_Sail2_values_Bitvector_a) l * size1) (op1 l' r')))))"
+
+
+definition mod_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where
+ " mod_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))"
+
+definition quot_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where
+ " quot_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))"
+
+definition quots_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where
+ " quots_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot True(( 1 :: int)))"
+
+
+definition mod_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " mod_mword = ( (mod))"
+
+definition quot_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " quot_mword = ( (div))"
+
+definition quots_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " quots_mword = ( Lem_machine_word.signedDivide )"
+
+
+definition arith_op_bv_int_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b option " where
+ " arith_op_bv_int_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = (
+ arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) l) r))"
+
+
+definition quot_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where
+ " quot_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))"
+
+definition mod_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where
+ " mod_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0
+ dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))"
+
+
+definition mod_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " mod_mword_int l r = ( l mod (Word.word_of_int r))"
+
+definition quot_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " quot_mword_int l r = ( l div (Word.word_of_int r))"
+
+definition quots_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " quots_mword_int l r = ( Lem_machine_word.signedDivide l (Word.word_of_int r))"
+
+
+definition replicate_bits_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " replicate_bits_bv dict_Sail2_values_Bitvector_a v count1 = ( repeat (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) count1 )"
+
+definition duplicate_bit_bv :: " 'a BitU_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " duplicate_bit_bv dict_Sail2_values_BitU_a bit len = ( replicate_bits_bv
+ (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len )"
+
+
+\<comment> \<open>\<open>val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool\<close>\<close>
+definition eq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where
+ " eq_bv dict_Sail2_values_Bitvector_a l r = ( (
+ (bits_of_method dict_Sail2_values_Bitvector_a) l =(bits_of_method dict_Sail2_values_Bitvector_a) r))"
+
+
+\<comment> \<open>\<open>val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool\<close>\<close>
+definition neq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where
+ " neq_bv dict_Sail2_values_Bitvector_a l r = ( \<not> (eq_bv
+ dict_Sail2_values_Bitvector_a l r))"
+
+
+\<comment> \<open>\<open>val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a\<close>\<close>
+definition get_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where
+ " get_slice_int_bv dict_Sail2_values_Bitvector_a len n lo = (
+ (let hi = ((lo + len) -( 1 :: int)) in
+ (let bs = (bools_of_int (hi +( 1 :: int)) n) in
+ (of_bools_method dict_Sail2_values_Bitvector_a) (subrange_list False bs hi lo))))"
+
+
+\<comment> \<open>\<open>val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer\<close>\<close>
+definition set_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int " where
+ " set_slice_int_bv dict_Sail2_values_Bitvector_a len n lo v = (
+ (let hi = ((lo + len) -( 1 :: int)) in
+ (let bs = (bits_of_int (hi +( 1 :: int)) n) in
+ maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v))))))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy b/prover_snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
new file mode 100644
index 0000000..f291c2c
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy
@@ -0,0 +1,750 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_operators_bitlists.lem\<close>.\<close>
+
+theory "Sail2_operators_bitlists"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "LEM.Lem_machine_word"
+ "Sail2_values"
+ "Sail2_operators"
+ "Sail2_prompt_monad"
+ "Sail2_prompt"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Machine_word\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+
+\<comment> \<open>\<open> Specialisation of operators to bit lists \<close>\<close>
+
+\<comment> \<open>\<open>val uint_maybe : list bitU -> maybe integer\<close>\<close>
+definition uint_maybe :: "(bitU)list \<Rightarrow>(int)option " where
+ " uint_maybe v = ( unsigned_of_bits (List.map (\<lambda> b. b) v))"
+
+definition uint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where
+ " uint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''uint'') (
+ (unsigned_method dict_Sail2_values_Bitvector_a) v))"
+
+definition uint_nondet :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where
+ " uint_nondet v = (
+ bools_of_bits_nondet v \<bind> (\<lambda> bs .
+ return (int_of_bools False bs)))"
+
+definition uint :: "(bitU)list \<Rightarrow> int " where
+ " uint v = ( maybe_failwith (uint_maybe v))"
+
+
+\<comment> \<open>\<open>val sint_maybe : list bitU -> maybe integer\<close>\<close>
+definition sint_maybe :: "(bitU)list \<Rightarrow>(int)option " where
+ " sint_maybe v = ( signed_of_bits (List.map (\<lambda> b. b) v))"
+
+definition sint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where
+ " sint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''sint'') (
+ (signed_method dict_Sail2_values_Bitvector_a) v))"
+
+definition sint_nondet :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where
+ " sint_nondet v = (
+ bools_of_bits_nondet v \<bind> (\<lambda> bs .
+ return (int_of_bools True bs)))"
+
+definition sint :: "(bitU)list \<Rightarrow> int " where
+ " sint v = ( maybe_failwith (sint_maybe v))"
+
+
+\<comment> \<open>\<open>val extz_vec : integer -> list bitU -> list bitU\<close>\<close>
+definition extz_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " extz_vec = (
+ extz_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val exts_vec : integer -> list bitU -> list bitU\<close>\<close>
+definition exts_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " exts_vec = (
+ exts_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val zero_extend : list bitU -> integer -> list bitU\<close>\<close>
+definition zero_extend :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " zero_extend bits len = ( extz_bits len bits )"
+
+
+\<comment> \<open>\<open>val sign_extend : list bitU -> integer -> list bitU\<close>\<close>
+definition sign_extend :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " sign_extend bits len = ( exts_bits len bits )"
+
+
+\<comment> \<open>\<open>val zeros : integer -> list bitU\<close>\<close>
+definition zeros :: " int \<Rightarrow>(bitU)list " where
+ " zeros len = ( repeat [B0] len )"
+
+
+\<comment> \<open>\<open>val vector_truncate : list bitU -> integer -> list bitU\<close>\<close>
+definition vector_truncate :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " vector_truncate bs len = ( extz_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs )"
+
+
+\<comment> \<open>\<open>val vector_truncateLSB : list bitU -> integer -> list bitU\<close>\<close>
+definition vector_truncateLSB :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " vector_truncateLSB bs len = ( take_list len bs )"
+
+
+\<comment> \<open>\<open>val vec_of_bits_maybe : list bitU -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_failwith : list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits : list bitU -> list bitU\<close>\<close>
+
+\<comment> \<open>\<open>val access_vec_inc : list bitU -> integer -> bitU\<close>\<close>
+definition access_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_vec_inc = (
+ access_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val access_vec_dec : list bitU -> integer -> bitU\<close>\<close>
+definition access_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_vec_dec = (
+ access_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val update_vec_inc : list bitU -> integer -> bitU -> list bitU\<close>\<close>
+definition update_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " update_vec_inc = (
+ update_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition update_vec_inc_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where
+ " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))"
+
+definition update_vec_inc_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))"
+
+definition update_vec_inc_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " update_vec_inc_nondet v i b = ( return (update_vec_inc v i b))"
+
+
+\<comment> \<open>\<open>val update_vec_dec : list bitU -> integer -> bitU -> list bitU\<close>\<close>
+definition update_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " update_vec_dec = (
+ update_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition update_vec_dec_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where
+ " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))"
+
+definition update_vec_dec_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))"
+
+definition update_vec_dec_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " update_vec_dec_nondet v i b = ( return (update_vec_dec v i b))"
+
+
+\<comment> \<open>\<open>val subrange_vec_inc : list bitU -> integer -> integer -> list bitU\<close>\<close>
+definition subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " subrange_vec_inc = (
+ subrange_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val subrange_vec_dec : list bitU -> integer -> integer -> list bitU\<close>\<close>
+definition subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " subrange_vec_dec = (
+ subrange_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU\<close>\<close>
+definition update_subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " update_subrange_vec_inc = (
+ update_subrange_bv_inc
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU\<close>\<close>
+definition update_subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " update_subrange_vec_dec = (
+ update_subrange_bv_dec
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val concat_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+definition concat_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " concat_vec = (
+ concat_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict)
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val cons_vec : bitU -> list bitU -> list bitU\<close>\<close>
+definition cons_vec :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " cons_vec = (
+ cons_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition cons_vec_maybe :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where
+ " cons_vec_maybe b v = ( Some (cons_vec b v))"
+
+definition cons_vec_fail :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " cons_vec_fail b v = ( return (cons_vec b v))"
+
+definition cons_vec_nondet :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " cons_vec_nondet b v = ( return (cons_vec b v))"
+
+
+\<comment> \<open>\<open>val cast_unit_vec : bitU -> list bitU\<close>\<close>
+definition cast_unit_vec :: " bitU \<Rightarrow>(bitU)list " where
+ " cast_unit_vec = ( cast_unit_bv )"
+
+definition cast_unit_vec_maybe :: " bitU \<Rightarrow>((bitU)list)option " where
+ " cast_unit_vec_maybe b = ( Some (cast_unit_vec b))"
+
+definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " cast_unit_vec_fail b = ( return (cast_unit_vec b))"
+
+definition cast_unit_vec_nondet :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " cast_unit_vec_nondet b = ( return (cast_unit_vec b))"
+
+
+\<comment> \<open>\<open>val vec_of_bit : integer -> bitU -> list bitU\<close>\<close>
+definition vec_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " vec_of_bit = ( bv_of_bit )"
+
+definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where
+ " vec_of_bit_maybe len b = ( Some (vec_of_bit len b))"
+
+definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " vec_of_bit_fail len b = ( return (vec_of_bit len b))"
+
+definition vec_of_bit_nondet :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " vec_of_bit_nondet len b = ( return (vec_of_bit len b))"
+
+
+\<comment> \<open>\<open>val msb : list bitU -> bitU\<close>\<close>
+definition msb :: "(bitU)list \<Rightarrow> bitU " where
+ " msb = (
+ most_significant
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val int_of_vec_maybe : bool -> list bitU -> maybe integer\<close>\<close>
+definition int_of_vec_maybe :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option " where
+ " int_of_vec_maybe = (
+ int_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition int_of_vec_fail :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where
+ " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))"
+
+definition int_of_vec_nondet :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where
+ " int_of_vec_nondet sign v = ( bools_of_bits_nondet v \<bind> (\<lambda> v . return (int_of_bools sign v)))"
+
+definition int_of_vec :: " bool \<Rightarrow>(bitU)list \<Rightarrow> int " where
+ " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))"
+
+
+\<comment> \<open>\<open>val string_of_bits : list bitU -> string\<close>\<close>
+definition string_of_bits :: "(bitU)list \<Rightarrow> string " where
+ " string_of_bits = (
+ string_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val decimal_string_of_bits : list bitU -> string\<close>\<close>
+definition decimal_string_of_bits :: "(bitU)list \<Rightarrow> string " where
+ " decimal_string_of_bits = (
+ decimal_string_of_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val and_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val or_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val xor_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val not_vec : list bitU -> list bitU\<close>\<close>
+definition and_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " and_vec = ( binop_list and_bit )"
+
+definition or_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " or_vec = ( binop_list or_bit )"
+
+definition xor_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " xor_vec = ( binop_list xor_bit )"
+
+definition not_vec :: "(bitU)list \<Rightarrow>(bitU)list " where
+ " not_vec = ( List.map not_bit )"
+
+
+\<comment> \<open>\<open>val arith_op_double_bl : forall 'a 'b. Bitvector 'a =>
+ (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU\<close>\<close>
+definition arith_op_double_bl :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " arith_op_double_bl dict_Sail2_values_Bitvector_a op1 sign l r = (
+ (let len =(( 2 :: int) *
+ (length_method dict_Sail2_values_Bitvector_a) l) in
+ (let l' = (if sign then exts_bv
+ dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in
+ (let r' = (if sign then exts_bv
+ dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in
+ List.map (\<lambda> b. b) (arith_op_bits op1 sign (List.map (\<lambda> b. b) l') (List.map (\<lambda> b. b) r'))))))"
+
+
+\<comment> \<open>\<open>val add_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val adds_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val sub_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val subs_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mult_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mults_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+definition add_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " add_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (+) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition adds_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " adds_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (+) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition sub_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " sub_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (-) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition subs_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " subs_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (-) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))"
+
+definition mult_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " mult_vec = ( arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) False )"
+
+definition mults_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " mults_vec = ( arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) True )"
+
+
+\<comment> \<open>\<open>val add_vec_int : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val sub_vec_int : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mult_vec_int : list bitU -> integer -> list bitU\<close>\<close>
+definition add_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " add_vec_int l r = ( arith_op_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) False l r )"
+
+definition sub_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " sub_vec_int l r = ( arith_op_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) False l r )"
+
+definition mult_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " mult_vec_int l r = ( arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) False l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))"
+
+
+\<comment> \<open>\<open>val add_int_vec : integer -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val sub_int_vec : integer -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mult_int_vec : integer -> list bitU -> list bitU\<close>\<close>
+definition add_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " add_int_vec l r = ( arith_op_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) False l r )"
+
+definition sub_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " sub_int_vec l r = ( arith_op_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) False l r )"
+
+definition mult_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " mult_int_vec l r = ( arith_op_double_bl
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) False (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )"
+
+
+\<comment> \<open>\<open>val add_vec_bit : list bitU -> bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val adds_vec_bit : list bitU -> bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val sub_vec_bit : list bitU -> bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val subs_vec_bit : list bitU -> bitU -> list bitU\<close>\<close>
+
+definition add_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where
+ " add_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (+) False l r )"
+
+definition add_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where
+ " add_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (+) False l r )"
+
+definition add_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " add_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe
+ dict_Sail2_values_Bitvector_a l r))"
+
+definition add_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " add_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (add_vec_bool
+ dict_Sail2_values_Bitvector_a l r)))"
+
+definition add_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " add_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition adds_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where
+ " adds_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (+) True l r )"
+
+definition adds_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where
+ " adds_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (+) True l r )"
+
+definition adds_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " adds_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe
+ dict_Sail2_values_Bitvector_a l r))"
+
+definition adds_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " adds_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (adds_vec_bool
+ dict_Sail2_values_Bitvector_a l r)))"
+
+definition adds_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " adds_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition sub_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where
+ " sub_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (-) False l r )"
+
+definition sub_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where
+ " sub_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (-) False l r )"
+
+definition sub_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " sub_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe
+ dict_Sail2_values_Bitvector_a l r))"
+
+definition sub_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " sub_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (sub_vec_bool
+ dict_Sail2_values_Bitvector_a l r)))"
+
+definition sub_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " sub_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+definition subs_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where
+ " subs_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool
+ dict_Sail2_values_Bitvector_a (-) True l r )"
+
+definition subs_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where
+ " subs_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit
+ dict_Sail2_values_Bitvector_a (-) True l r )"
+
+definition subs_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " subs_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe
+ dict_Sail2_values_Bitvector_a l r))"
+
+definition subs_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where
+ " subs_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (subs_vec_bool
+ dict_Sail2_values_Bitvector_a l r)))"
+
+definition subs_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " subs_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+
+\<comment> \<open>\<open>val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec = add_overflow_bv
+let add_overflow_vec_signed = add_overflow_bv_signed
+let sub_overflow_vec = sub_overflow_bv
+let sub_overflow_vec_signed = sub_overflow_bv_signed
+let mult_overflow_vec = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit = add_overflow_bv_bit
+let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed\<close>\<close>
+
+\<comment> \<open>\<open>val shiftl : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val shiftr : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val arith_shiftr : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val rotl : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val rotr : list bitU -> integer -> list bitU\<close>\<close>
+definition shiftl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " shiftl = (
+ shiftl_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " shiftr = (
+ shiftr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition arith_shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " arith_shiftr = (
+ arith_shiftr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition rotl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " rotl = (
+ rotl_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition rotr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " rotr = (
+ rotr_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val mod_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+definition mod_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " mod_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where
+ " mod_vec_maybe l r = ( mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition mod_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " mod_vec_nondet l r = ( of_bits_nondet
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec l r))"
+
+
+\<comment> \<open>\<open>val quot_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+definition quot_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " quot_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where
+ " quot_vec_maybe l r = ( quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quot_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quot_vec_nondet l r = ( of_bits_nondet
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec l r))"
+
+
+\<comment> \<open>\<open>val quots_vec : list bitU -> list bitU -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e\<close>\<close>
+definition quots_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " quots_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quots_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where
+ " quots_vec_maybe l r = ( quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quots_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quots_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quots_vec_nondet l r = ( of_bits_nondet
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec l r))"
+
+
+\<comment> \<open>\<open>val mod_vec_int : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e\<close>\<close>
+definition mod_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " mod_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where
+ " mod_vec_int_maybe l r = ( mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition mod_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition mod_vec_int_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " mod_vec_int_nondet l r = ( of_bits_nondet
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int l r))"
+
+
+\<comment> \<open>\<open>val quot_vec_int : list bitU -> integer -> list bitU\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e\<close>\<close>
+definition quot_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " quot_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where
+ " quot_vec_int_maybe l r = ( quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )"
+
+definition quot_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))"
+
+definition quot_vec_int_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where
+ " quot_vec_int_nondet l r = ( of_bits_nondet
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int l r))"
+
+
+\<comment> \<open>\<open>val replicate_bits : list bitU -> integer -> list bitU\<close>\<close>
+definition replicate_bits :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " replicate_bits = (
+ replicate_bits_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val duplicate : bitU -> integer -> list bitU\<close>\<close>
+definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " duplicate = (
+ duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict )"
+
+definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list)option " where
+ " duplicate_maybe b n = ( Some (duplicate b n))"
+
+definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " duplicate_fail b n = ( return (duplicate b n))"
+
+definition duplicate_nondet :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where
+ " duplicate_nondet b n = (
+ bool_of_bitU_nondet b \<bind> (\<lambda> b .
+ return (duplicate (bitU_of_bool b) n)))"
+
+
+\<comment> \<open>\<open>val reverse_endianness : list bitU -> list bitU\<close>\<close>
+definition reverse_endianness :: "(bitU)list \<Rightarrow>(bitU)list " where
+ " reverse_endianness v = ( reverse_endianness_list v )"
+
+
+\<comment> \<open>\<open>val get_slice_int : integer -> integer -> integer -> list bitU\<close>\<close>
+definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " get_slice_int = (
+ get_slice_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val set_slice_int : integer -> integer -> integer -> list bitU -> integer\<close>\<close>
+definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int " where
+ " set_slice_int = (
+ set_slice_int_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+
+\<comment> \<open>\<open>val slice : list bitU -> integer -> integer -> list bitU\<close>\<close>
+definition slice :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " slice v lo len = (
+ subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
+
+
+\<comment> \<open>\<open>val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU\<close>\<close>
+definition set_slice :: " int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
+ update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
+
+
+\<comment> \<open>\<open>val eq_vec : list bitU -> list bitU -> bool\<close>\<close>
+\<comment> \<open>\<open>val neq_vec : list bitU -> list bitU -> bool\<close>\<close>
+definition eq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where
+ " eq_vec = (
+ eq_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+definition neq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where
+ " neq_vec = (
+ neq_bv
+ (instance_Sail2_values_Bitvector_list_dict
+ instance_Sail2_values_BitU_Sail2_values_bitU_dict) )"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy b/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
new file mode 100644
index 0000000..7fd3dca
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy
@@ -0,0 +1,623 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_operators_mwords.lem\<close>.\<close>
+
+theory "Sail2_operators_mwords"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "LEM.Lem_machine_word"
+ "Sail2_values"
+ "Sail2_operators"
+ "Sail2_prompt_monad"
+ "Sail2_prompt"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Machine_word\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_operators\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+definition uint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where
+ " uint_maybe v = ( Some (Word.uint v))"
+
+definition uint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where
+ " uint_fail v = ( return (Word.uint v))"
+
+definition uint_nondet :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where
+ " uint_nondet v = ( return (Word.uint v))"
+
+definition sint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where
+ " sint_maybe v = ( Some (Word.sint v))"
+
+definition sint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where
+ " sint_fail v = ( return (Word.sint v))"
+
+definition sint_nondet :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where
+ " sint_nondet v = ( return (Word.sint v))"
+
+
+\<comment> \<open>\<open>val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_nondet : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a\<close>\<close>
+definition vec_of_bits_maybe :: "(bitU)list \<Rightarrow>(('a::len)Word.word)option " where
+ " vec_of_bits_maybe bits = ( map_option Word.of_bl (just_list (List.map bool_of_bitU bits)))"
+
+definition vec_of_bits_fail :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " vec_of_bits_fail bits = ( of_bits_fail
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits_nondet :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " vec_of_bits_nondet bits = ( of_bits_nondet
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits_failwith :: "(bitU)list \<Rightarrow>('a::len)Word.word " where
+ " vec_of_bits_failwith bits = ( of_bits_failwith
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+definition vec_of_bits :: "(bitU)list \<Rightarrow>('a::len)Word.word " where
+ " vec_of_bits bits = ( of_bits_failwith
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )"
+
+
+\<comment> \<open>\<open>val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU\<close>\<close>
+definition access_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_vec_inc = (
+ access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU\<close>\<close>
+definition access_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_vec_dec = (
+ access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+definition update_vec_dec_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " update_vec_dec_maybe w i b = ( update_mword_dec w i b )"
+
+definition update_vec_dec_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " update_vec_dec_fail w i b = (
+ bool_of_bitU_fail b \<bind> (\<lambda> b .
+ return (update_mword_bool_dec w i b)))"
+
+definition update_vec_dec_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " update_vec_dec_nondet w i b = (
+ bool_of_bitU_nondet b \<bind> (\<lambda> b .
+ return (update_mword_bool_dec w i b)))"
+
+definition update_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " update_vec_dec w i b = ( maybe_failwith (update_vec_dec_maybe w i b))"
+
+
+definition update_vec_inc_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " update_vec_inc_maybe w i b = ( update_mword_inc w i b )"
+
+definition update_vec_inc_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " update_vec_inc_fail w i b = (
+ bool_of_bitU_fail b \<bind> (\<lambda> b .
+ return (update_mword_bool_inc w i b)))"
+
+definition update_vec_inc_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " update_vec_inc_nondet w i b = (
+ bool_of_bitU_nondet b \<bind> (\<lambda> b .
+ return (update_mword_bool_inc w i b)))"
+
+definition update_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " update_vec_inc w i b = ( maybe_failwith (update_vec_inc_maybe w i b))"
+
+
+\<comment> \<open>\<open>val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition subrange_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " subrange_vec_dec w i j = ( Word.slice (nat_of_int j) w )"
+
+
+\<comment> \<open>\<open>val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition subrange_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " subrange_vec_inc w i j = ( subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j))"
+
+
+\<comment> \<open>\<open>val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition update_subrange_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " update_subrange_vec_dec w i j w' = ( Lem.word_update w (nat_of_int j) (nat_of_int i) w' )"
+
+
+\<comment> \<open>\<open>val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition update_subrange_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " update_subrange_vec_inc w i j w' = ( update_subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j) w' )"
+
+
+\<comment> \<open>\<open>val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b\<close>\<close>
+definition extz_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " extz_vec _ w = ( Word.ucast w )"
+
+
+\<comment> \<open>\<open>val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b\<close>\<close>
+definition exts_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " exts_vec _ w = ( Word.scast w )"
+
+
+\<comment> \<open>\<open>val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition zero_extend :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " zero_extend w _ = ( Word.ucast w )"
+
+
+\<comment> \<open>\<open>val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition sign_extend :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " sign_extend w _ = ( Word.scast w )"
+
+
+\<comment> \<open>\<open>val zeros : forall 'a. Size 'a => integer -> mword 'a\<close>\<close>
+definition zeros :: " int \<Rightarrow>('a::len)Word.word " where
+ " zeros _ = ( Word.word_of_int (int(( 0 :: nat))))"
+
+
+\<comment> \<open>\<open>val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition vector_truncate :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " vector_truncate w _ = ( Word.ucast w )"
+
+
+\<comment> \<open>\<open>val vector_truncateLSB : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition vector_truncateLSB :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " vector_truncateLSB w len = (
+ (let len = (nat_of_int len) in
+ (let lo = (size w - len) in
+ (let hi = ((lo + len) -( 1 :: nat)) in
+ Word.slice lo w))))"
+
+
+\<comment> \<open>\<open>val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c\<close>\<close>
+definition concat_vec :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('c::len)Word.word " where
+ " concat_vec = ( Word.word_cat )"
+
+
+\<comment> \<open>\<open>val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b\<close>\<close>
+definition cons_vec_bool :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " cons_vec_bool b w = ( Word.of_bl (b # Word.to_bl w))"
+
+definition cons_vec_maybe :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>(('b::len)Word.word)option " where
+ " cons_vec_maybe b w = ( map_option (\<lambda> b . cons_vec_bool b w) (bool_of_bitU b))"
+
+definition cons_vec_fail :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where
+ " cons_vec_fail b w = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cons_vec_bool b w)))"
+
+definition cons_vec_nondet :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where
+ " cons_vec_nondet b w = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (cons_vec_bool b w)))"
+
+definition cons_vec :: " bitU \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))"
+
+
+\<comment> \<open>\<open>val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a\<close>\<close>
+definition vec_of_bool :: " int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " vec_of_bool _ b = ( Word.of_bl [b])"
+
+definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " vec_of_bit_maybe len b = ( map_option (vec_of_bool len) (bool_of_bitU b))"
+
+definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " vec_of_bit_fail len b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (vec_of_bool len b)))"
+
+definition vec_of_bit_nondet :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " vec_of_bit_nondet len b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (vec_of_bool len b)))"
+
+definition vec_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))"
+
+
+\<comment> \<open>\<open>val cast_bool_vec : bool -> mword ty1\<close>\<close>
+definition cast_bool_vec :: " bool \<Rightarrow>(1)Word.word " where
+ " cast_bool_vec b = ( vec_of_bool(( 1 :: int)) b )"
+
+definition cast_unit_vec_maybe :: " bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " cast_unit_vec_maybe b = ( vec_of_bit_maybe(( 1 :: int)) b )"
+
+definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where
+ " cast_unit_vec_fail b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cast_bool_vec b)))"
+
+definition cast_unit_vec_nondet :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where
+ " cast_unit_vec_nondet b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (cast_bool_vec b)))"
+
+definition cast_unit_vec :: " bitU \<Rightarrow>('a::len)Word.word " where
+ " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))"
+
+
+\<comment> \<open>\<open>val msb : forall 'a. Size 'a => mword 'a -> bitU\<close>\<close>
+definition msb :: "('a::len)Word.word \<Rightarrow> bitU " where
+ " msb = (
+ most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer\<close>\<close>
+definition int_of_vec :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where
+ " int_of_vec sign w = (
+ if sign
+ then Word.sint w
+ else Word.uint w )"
+
+definition int_of_vec_maybe :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>(int)option " where
+ " int_of_vec_maybe sign w = ( Some (int_of_vec sign w))"
+
+definition int_of_vec_fail :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where
+ " int_of_vec_fail sign w = ( return (int_of_vec sign w))"
+
+
+\<comment> \<open>\<open>val string_of_bits : forall 'a. Size 'a => mword 'a -> string\<close>\<close>
+definition string_of_bits :: "('a::len)Word.word \<Rightarrow> string " where
+ " string_of_bits = (
+ string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val decimal_string_of_bits : forall 'a. Size 'a => mword 'a -> string\<close>\<close>
+definition decimal_string_of_bits :: "('a::len)Word.word \<Rightarrow> string " where
+ " decimal_string_of_bits = (
+ decimal_string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a\<close>\<close>
+definition and_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " and_vec = ( Bits.bitAND )"
+
+definition or_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " or_vec = ( Bits.bitOR )"
+
+definition xor_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " xor_vec = ( Bits.bitXOR )"
+
+definition not_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " not_vec = ( Bits.bitNOT )"
+
+
+\<comment> \<open>\<open>val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val adds_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val subs_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b\<close>\<close>
+\<comment> \<open>\<open>val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b\<close>\<close>
+definition add_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " add_vec l r = ( Word.word_of_int ((int_of_mword False l) + (int_of_mword False r)))"
+
+definition adds_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " adds_vec l r = ( Word.word_of_int ((int_of_mword True l) + (int_of_mword True r)))"
+
+definition sub_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " sub_vec l r = ( Word.word_of_int ((int_of_mword False l) - (int_of_mword False r)))"
+
+definition subs_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " subs_vec l r = ( Word.word_of_int ((int_of_mword True l) - (int_of_mword True r)))"
+
+definition mult_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " mult_vec l r = ( Word.word_of_int ((int_of_mword False (Word.ucast l :: ( 'b::len)Word.word)) * (int_of_mword False (Word.ucast r :: ( 'b::len)Word.word))))"
+
+definition mults_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))"
+
+
+\<comment> \<open>\<open>val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition add_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " add_vec_int l r = ( arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) False l r )"
+
+definition sub_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " sub_vec_int l r = ( arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) False l r )"
+
+definition mult_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " mult_vec_int l r = ( arith_op_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) False (Word.ucast l :: ( 'b::len)Word.word) r )"
+
+
+\<comment> \<open>\<open>val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b\<close>\<close>
+definition add_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " add_int_vec l r = ( arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) False l r )"
+
+definition sub_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " sub_int_vec l r = ( arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) False l r )"
+
+definition mult_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where
+ " mult_int_vec l r = ( arith_op_int_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) False l (Word.ucast r :: ( 'b::len)Word.word))"
+
+
+\<comment> \<open>\<open>val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val sub_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a\<close>\<close>
+
+definition add_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " add_vec_bool l r = ( arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) False l r )"
+
+definition add_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " add_vec_bit_maybe l r = ( map_option (add_vec_bool l) (bool_of_bitU r))"
+
+definition add_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " add_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (add_vec_bool l r)))"
+
+definition add_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " add_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (add_vec_bool l r)))"
+
+definition add_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " add_vec_bit l r = ( maybe_failwith (add_vec_bit_maybe l r))"
+
+
+definition adds_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " adds_vec_bool l r = ( arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) True l r )"
+
+definition adds_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " adds_vec_bit_maybe l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))"
+
+definition adds_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " adds_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (adds_vec_bool l r)))"
+
+definition adds_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " adds_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (adds_vec_bool l r)))"
+
+definition adds_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " adds_vec_bit l r = ( maybe_failwith (adds_vec_bit_maybe l r))"
+
+
+definition sub_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " sub_vec_bool l r = ( arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) False l r )"
+
+definition sub_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " sub_vec_bit_maybe l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))"
+
+definition sub_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " sub_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (sub_vec_bool l r)))"
+
+definition sub_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " sub_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (sub_vec_bool l r)))"
+
+definition sub_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " sub_vec_bit l r = ( maybe_failwith (sub_vec_bit_maybe l r))"
+
+
+definition subs_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " subs_vec_bool l r = ( arith_op_bv_bool
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) True l r )"
+
+definition subs_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " subs_vec_bit_maybe l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))"
+
+definition subs_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " subs_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (subs_vec_bool l r)))"
+
+definition subs_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " subs_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (subs_vec_bool l r)))"
+
+definition subs_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where
+ " subs_vec_bit l r = ( maybe_failwith (subs_vec_bit_maybe l r))"
+
+
+\<comment> \<open>\<open> TODO
+val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU)
+let maybe_mword_of_bits_overflow (bits, overflow, carry) =
+ Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits)
+
+val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val adds_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val subs_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU)
+let add_overflow_vec l r = maybe_mword_of_bits_overflow (add_overflow_bv l r)
+let adds_overflow_vec l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r)
+let sub_overflow_vec l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r)
+let subs_overflow_vec l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r)
+let mult_overflow_vec l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r)
+let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r)
+
+val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+let add_overflow_vec_bit = add_overflow_bv_bit
+let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed\<close>\<close>
+
+\<comment> \<open>\<open>val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+definition shiftl :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " shiftl = ( shiftl_mword )"
+
+definition shiftr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " shiftr = ( shiftr_mword )"
+
+definition arith_shiftr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " arith_shiftr = ( arith_shiftr_mword )"
+
+definition rotl :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " rotl = ( rotl_mword )"
+
+definition rotr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " rotr = ( rotr_mword )"
+
+
+\<comment> \<open>\<open>val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition mod_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " mod_vec l r = ( mod_mword l r )"
+
+definition mod_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where
+ " mod_vec_maybe l r = ( mod_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition mod_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition mod_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " mod_vec_nondet l r = (
+ (case (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ Some w => return w
+ | None => mword_nondet ()
+ ))"
+
+
+\<comment> \<open>\<open>val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition quot_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " quot_vec l r = ( quot_mword l r )"
+
+definition quot_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where
+ " quot_vec_maybe l r = ( quot_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quot_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quot_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quot_vec_nondet l r = (
+ (case (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ Some w => return w
+ | None => mword_nondet ()
+ ))"
+
+
+\<comment> \<open>\<open>val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition quots_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " quots_vec l r = ( quots_mword l r )"
+
+definition quots_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where
+ " quots_vec_maybe l r = ( quots_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quots_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quots_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quots_vec_nondet l r = (
+ (case (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ Some w => return w
+ | None => mword_nondet ()
+ ))"
+
+
+\<comment> \<open>\<open>val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition mod_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " mod_vec_int l r = ( mod_mword_int l r )"
+
+definition mod_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where
+ " mod_vec_int_maybe l r = ( mod_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition mod_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition mod_vec_int_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " mod_vec_int_nondet l r = (
+ (case (mod_bv_int instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ Some w => return w
+ | None => mword_nondet ()
+ ))"
+
+
+\<comment> \<open>\<open>val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e\<close>\<close>
+\<comment> \<open>\<open>val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition quot_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " quot_vec_int l r = ( quot_mword_int l r )"
+
+definition quot_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where
+ " quot_vec_int_maybe l r = ( quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )"
+
+definition quot_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))"
+
+definition quot_vec_int_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " quot_vec_int_nondet l r = (
+ (case (quot_bv_int
+ instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of
+ Some w => return w
+ | None => mword_nondet ()
+ ))"
+
+
+\<comment> \<open>\<open>val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b\<close>\<close>
+definition replicate_bits :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " replicate_bits v count1 = ( Word.of_bl (repeat (Word.to_bl v) count1))"
+
+
+\<comment> \<open>\<open>val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a\<close>\<close>
+definition duplicate_bool :: " bool \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " duplicate_bool b n = ( Word.of_bl (repeat [b] n))"
+
+definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where
+ " duplicate_maybe b n = ( map_option (\<lambda> b . duplicate_bool b n) (bool_of_bitU b))"
+
+definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " duplicate_fail b n = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (duplicate_bool b n)))"
+
+definition duplicate_nondet :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where
+ " duplicate_nondet b n = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (duplicate_bool b n)))"
+
+definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " duplicate b n = ( maybe_failwith (duplicate_maybe b n))"
+
+
+\<comment> \<open>\<open>val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a\<close>\<close>
+definition reverse_endianness :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " reverse_endianness v = ( Word.of_bl (reverse_endianness_list (Word.to_bl v)))"
+
+
+\<comment> \<open>\<open>val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a\<close>\<close>
+definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where
+ " get_slice_int = (
+ get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer\<close>\<close>
+definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where
+ " set_slice_int = (
+ set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )"
+
+
+\<comment> \<open>\<open>val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition slice :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " slice v lo len = (
+ subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )"
+
+
+\<comment> \<open>\<open>val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition set_slice :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = (
+ update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )"
+
+
+\<comment> \<open>\<open>val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool\<close>\<close>
+\<comment> \<open>\<open>val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy b/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
new file mode 100644
index 0000000..3e8dcb2
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy
@@ -0,0 +1,169 @@
+theory Sail2_operators_mwords_lemmas
+ imports Sail2_operators_mwords
+begin
+
+lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_nondet_def
+lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_nondet_def
+
+lemma bools_of_bits_nondet_just_list[simp]:
+ assumes "just_list (map bool_of_bitU bus) = Some bs"
+ shows "bools_of_bits_nondet bus = return bs"
+proof -
+ have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_nondet b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)"
+ if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools
+ proof (use that in \<open>induction bus arbitrary: bs bools\<close>)
+ case (Cons bu bus bs)
+ obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b"
+ using Cons.prems by (cases bu) (auto split: option.splits)
+ then show ?case
+ using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"]
+ by (cases bu) (auto simp: bool_of_bitU_nondet_def split: option.splits)
+ qed auto
+ then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_nondet_def
+ by auto
+qed
+
+lemma of_bits_mword_return_of_bl[simp]:
+ assumes "just_list (map bool_of_bitU bus) = Some bs"
+ shows "of_bits_nondet BC_mword bus = return (of_bl bs)"
+ and "of_bits_fail BC_mword bus = return (of_bl bs)"
+ by (auto simp: of_bits_nondet_def of_bits_fail_def maybe_fail_def assms BC_mword_defs)
+
+lemma vec_of_bits_of_bl[simp]:
+ assumes "just_list (map bool_of_bitU bus) = Some bs"
+ shows "vec_of_bits_maybe bus = Some (of_bl bs)"
+ and "vec_of_bits_fail bus = return (of_bl bs)"
+ and "vec_of_bits_nondet bus = return (of_bl bs)"
+ and "vec_of_bits_failwith bus = of_bl bs"
+ and "vec_of_bits bus = of_bl bs"
+ unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_nondet_def
+ vec_of_bits_failwith_def vec_of_bits_def
+ by (auto simp: assms)
+
+lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def]
+
+lemma access_vec_inc_test_bit[simp]:
+ fixes w :: "('a::len) word"
+ assumes "n \<ge> 0" and "nat n < LENGTH('a)"
+ shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))"
+ using assms
+ by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl)
+
+lemma bool_of_bitU_monadic_simps[simp]:
+ "bool_of_bitU_fail B0 = return False"
+ "bool_of_bitU_fail B1 = return True"
+ "bool_of_bitU_fail BU = Fail ''bool_of_bitU''"
+ "bool_of_bitU_nondet B0 = return False"
+ "bool_of_bitU_nondet B1 = return True"
+ "bool_of_bitU_nondet BU = choose_bool ''bool_of_bitU''"
+ unfolding bool_of_bitU_fail_def bool_of_bitU_nondet_def
+ by auto
+
+lemma update_vec_dec_simps[simp]:
+ "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)"
+ "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)"
+ "update_vec_dec_maybe w i BU = None"
+ "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)"
+ "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)"
+ "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''"
+ "update_vec_dec_nondet w i B0 = return (set_bit w (nat i) False)"
+ "update_vec_dec_nondet w i B1 = return (set_bit w (nat i) True)"
+ "update_vec_dec_nondet w i BU = choose_bool ''bool_of_bitU'' \<bind> (\<lambda>b. return (set_bit w (nat i) b))"
+ "update_vec_dec w i B0 = set_bit w (nat i) False"
+ "update_vec_dec w i B1 = set_bit w (nat i) True"
+ unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_nondet_def update_vec_dec_def
+ by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def)
+
+lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]:
+ "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)"
+ by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq)
+
+declare subrange_vec_dec_def[simp]
+
+lemma update_subrange_vec_dec_update_subrange_list_dec:
+ assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)"
+ shows "update_subrange_vec_dec (w :: 'a::len word) i j w' =
+ of_bl (update_subrange_list_dec (to_bl w) i j (to_bl w'))"
+ using assms
+ unfolding update_subrange_vec_dec_def update_subrange_list_dec_def update_subrange_list_inc_def
+ by (auto simp: word_update_def split_at_def Let_def nat_diff_distrib min_def)
+
+lemma subrange_vec_dec_subrange_list_dec:
+ assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)" and "int LENGTH('b) = i - j + 1"
+ shows "subrange_vec_dec (w :: 'a::len word) i j = (of_bl (subrange_list_dec (to_bl w) i j) :: 'b::len word)"
+ using assms unfolding subrange_vec_dec_def
+ by (auto simp: subrange_list_dec_drop_take slice_take of_bl_drop')
+
+lemma slice_simp[simp]: "slice w lo len = Word.slice (nat lo) w"
+ by (auto simp: slice_def)
+
+declare slice_id[simp]
+
+lemma of_bools_of_bl[simp]: "of_bools_method BC_mword = of_bl"
+ by (auto simp: BC_mword_defs)
+
+lemma of_bl_bin_word_of_int:
+ "len = LENGTH('a) \<Longrightarrow> of_bl (bin_to_bl_aux len n []) = (word_of_int n :: ('a::len) word)"
+ by (auto simp: of_bl_def bin_bl_bin')
+
+lemma get_slice_int_0_bin_to_bl[simp]:
+ "len > 0 \<Longrightarrow> get_slice_int len n 0 = of_bl (bin_to_bl (nat len) n)"
+ unfolding get_slice_int_def get_slice_int_bv_def subrange_list_def
+ by (auto simp: subrange_list_dec_drop_take len_bin_to_bl_aux)
+
+lemma to_bl_of_bl[simp]:
+ fixes bl :: "bool list"
+ defines w: "w \<equiv> of_bl bl :: 'a::len word"
+ assumes len: "length bl = LENGTH('a)"
+ shows "to_bl w = bl"
+ using len unfolding w by (intro word_bl.Abs_inverse) auto
+
+lemma reverse_endianness_byte[simp]:
+ "LENGTH('a) = 8 \<Longrightarrow> reverse_endianness (w :: 'a::len word) = w"
+ unfolding reverse_endianness_def by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness[simp]:
+ "8 dvd LENGTH('a) \<Longrightarrow> reverse_endianness (reverse_endianness w) = (w :: 'a::len word)"
+ unfolding reverse_endianness_def by (simp)
+
+lemma replicate_bits_zero[simp]: "replicate_bits 0 n = 0"
+ by (intro word_eqI) (auto simp: replicate_bits_def test_bit_of_bl rev_nth nth_repeat simp del: repeat.simps)
+
+declare extz_vec_def[simp]
+declare exts_vec_def[simp]
+declare concat_vec_def[simp]
+
+lemma msb_Bits_msb[simp]:
+ "msb w = bitU_of_bool (Bits.msb w)"
+ by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits)
+
+declare and_vec_def[simp]
+declare or_vec_def[simp]
+declare xor_vec_def[simp]
+declare not_vec_def[simp]
+
+lemma arith_vec_simps[simp]:
+ "add_vec l r = l + r"
+ "sub_vec l r = l - r"
+ "mult_vec l r = (ucast l) * (ucast r)"
+ unfolding add_vec_def sub_vec_def mult_vec_def
+ by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def)
+
+declare adds_vec_def[simp]
+declare subs_vec_def[simp]
+declare mults_vec_def[simp]
+
+lemma arith_vec_int_simps[simp]:
+ "add_vec_int l r = l + (word_of_int r)"
+ "sub_vec_int l r = l - (word_of_int r)"
+ "mult_vec_int l r = (ucast l) * (word_of_int r)"
+ unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def
+ by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def)
+
+lemma shiftl_simp[simp]: "shiftl w l = w << (nat l)"
+ by (auto simp: shiftl_def shiftl_mword_def)
+
+lemma shiftr_simp[simp]: "shiftr w l = w >> (nat l)"
+ by (auto simp: shiftr_def shiftr_mword_def)
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_prompt.thy b/prover_snapshots/isabelle/lib/sail/Sail2_prompt.thy
new file mode 100644
index 0000000..12584c2
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_prompt.thy
@@ -0,0 +1,181 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_prompt.lem\<close>.\<close>
+
+theory "Sail2_prompt"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail2_values"
+ "Sail2_prompt_monad"
+ "Sail2_prompt_monad_lemmas"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail_impl_base\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `Sail2_prompt_monad_lemmas`\<close>\<close>
+
+\<comment> \<open>\<open>val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e\<close>\<close>
+
+\<comment> \<open>\<open>val >> : forall 'rv 'b 'e. monad 'rv unit 'e -> monad 'rv 'b 'e -> monad 'rv 'b 'e\<close>\<close>
+
+\<comment> \<open>\<open>val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e\<close>\<close>
+fun iter_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where
+ " iter_aux i f (x # xs) = ( f i x \<then> iter_aux (i +( 1 :: int)) f xs )"
+|" iter_aux i f ([]) = ( return () )"
+
+
+\<comment> \<open>\<open>val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e\<close>\<close>
+definition iteri :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where
+ " iteri f xs = ( iter_aux(( 0 :: int)) f xs )"
+
+
+\<comment> \<open>\<open>val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e\<close>\<close>
+definition iter :: "('a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where
+ " iter f xs = ( iteri ( \<lambda>x .
+ (case x of _ => \<lambda> x . f x )) xs )"
+
+
+\<comment> \<open>\<open>val foreachM : forall 'a 'rv 'vars 'e.
+ list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e\<close>\<close>
+fun foreachM :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where
+ " foreachM ([]) vars body = ( return vars )"
+|" foreachM (x # xs) vars body = (
+ body x vars \<bind> (\<lambda> vars .
+ foreachM xs vars body))"
+
+
+\<comment> \<open>\<open>val genlistM : forall 'a 'rv 'e. (nat -> monad 'rv 'a 'e) -> nat -> monad 'rv (list 'a) 'e\<close>\<close>
+definition genlistM :: "(nat \<Rightarrow>('rv,'a,'e)monad)\<Rightarrow> nat \<Rightarrow>('rv,('a list),'e)monad " where
+ " genlistM f n = (
+ (let indices = (genlist (\<lambda> n . n) n) in
+ foreachM indices [] (\<lambda> n xs . (f n \<bind> (\<lambda> x . return (xs @ [x]))))))"
+
+
+\<comment> \<open>\<open>val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e\<close>\<close>
+definition and_boolM :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad " where
+ " and_boolM l r = ( l \<bind> (\<lambda> l . if l then r else return False))"
+
+
+\<comment> \<open>\<open>val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e\<close>\<close>
+definition or_boolM :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad " where
+ " or_boolM l r = ( l \<bind> (\<lambda> l . if l then return True else r))"
+
+
+\<comment> \<open>\<open>val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e\<close>\<close>
+definition bool_of_bitU_fail :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where
+ " bool_of_bitU_fail = ( \<lambda>x .
+ (case x of
+ B0 => return False
+ | B1 => return True
+ | BU => Fail (''bool_of_bitU'')
+ ) )"
+
+
+\<comment> \<open>\<open>val bool_of_bitU_nondet : forall 'rv 'e. bitU -> monad 'rv bool 'e\<close>\<close>
+definition bool_of_bitU_nondet :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where
+ " bool_of_bitU_nondet = ( \<lambda>x .
+ (case x of
+ B0 => return False
+ | B1 => return True
+ | BU => choose_bool (''bool_of_bitU'')
+ ) )"
+
+
+\<comment> \<open>\<open>val bools_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e\<close>\<close>
+definition bools_of_bits_nondet :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad " where
+ " bools_of_bits_nondet bits = (
+ foreachM bits []
+ (\<lambda> b bools .
+ bool_of_bitU_nondet b \<bind> (\<lambda> b .
+ return (bools @ [b]))))"
+
+
+\<comment> \<open>\<open>val of_bits_nondet : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e\<close>\<close>
+definition of_bits_nondet :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where
+ " of_bits_nondet dict_Sail2_values_Bitvector_a bits = (
+ bools_of_bits_nondet bits \<bind> (\<lambda> bs .
+ return ((of_bools_method dict_Sail2_values_Bitvector_a) bs)))"
+
+
+\<comment> \<open>\<open>val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e\<close>\<close>
+definition of_bits_fail :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where
+ " of_bits_fail dict_Sail2_values_Bitvector_a bits = ( maybe_fail (''of_bits'') (
+ (of_bits_method dict_Sail2_values_Bitvector_a) bits))"
+
+
+\<comment> \<open>\<open>val mword_nondet : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e\<close>\<close>
+definition mword_nondet :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where
+ " mword_nondet _ = (
+ bools_of_bits_nondet (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs .
+ return (Word.of_bl bs)))"
+
+
+\<comment> \<open>\<open>val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+ ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e\<close>\<close>
+function (sequential,domintros) whileM :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where
+ " whileM vars cond body = (
+ cond vars \<bind> (\<lambda> cond_val .
+ if cond_val then
+ body vars \<bind> (\<lambda> vars . whileM vars cond body)
+ else return vars))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+ ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e\<close>\<close>
+function (sequential,domintros) untilM :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where
+ " untilM vars cond body = (
+ body vars \<bind> (\<lambda> vars .
+ cond vars \<bind> (\<lambda> cond_val .
+ if cond_val then return vars else untilM vars cond body)))"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val choose_bools : forall 'rv 'e. string -> nat -> monad 'rv (list bool) 'e\<close>\<close>
+definition choose_bools :: " string \<Rightarrow> nat \<Rightarrow>('rv,((bool)list),'e)monad " where
+ " choose_bools descr n = ( genlistM ( \<lambda>x .
+ (case x of _ => choose_bool descr )) n )"
+
+
+\<comment> \<open>\<open>val choose : forall 'rv 'a 'e. string -> list 'a -> monad 'rv 'a 'e\<close>\<close>
+definition chooseM :: " string \<Rightarrow> 'a list \<Rightarrow>('rv,'a,'e)monad " where
+ " chooseM descr xs = (
+ \<comment> \<open>\<open> Use sufficiently many nondeterministically chosen bits and convert into an
+ index into the list \<close>\<close>
+ choose_bools descr (List.length xs) \<bind> (\<lambda> bs .
+ (let idx = (( (nat_of_bools bs)) mod List.length xs) in
+ (case index xs idx of
+ Some x => return x
+ | None => Fail ((''choose '') @ descr)
+ ))))"
+
+
+\<comment> \<open>\<open>val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e\<close>\<close>
+definition internal_pick :: " 'a list \<Rightarrow>('rv,'a,'e)monad " where
+ " internal_pick xs = ( chooseM (''internal_pick'') xs )"
+
+
+\<comment> \<open>\<open>let write_two_regs r1 r2 vec =
+ let is_inc =
+ let is_inc_r1 = is_inc_of_reg r1 in
+ let is_inc_r2 = is_inc_of_reg r2 in
+ let () = ensure (is_inc_r1 = is_inc_r2)
+ "write_two_regs called with vectors of different direction" in
+ is_inc_r1 in
+
+ let (size_r1 : integer) = size_of_reg r1 in
+ let (start_vec : integer) = get_start vec in
+ let size_vec = length vec in
+ let r1_v =
+ if is_inc
+ then slice vec start_vec (size_r1 - start_vec - 1)
+ else slice vec start_vec (start_vec - size_r1 - 1) in
+ let r2_v =
+ if is_inc
+ then slice vec (size_r1 - start_vec) (size_vec - start_vec)
+ else slice vec (start_vec - size_r1) (start_vec - size_vec) in
+ write_reg r1 r1_v >> write_reg r2 r2_v\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy b/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy
new file mode 100644
index 0000000..1560540
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy
@@ -0,0 +1,405 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_prompt_monad.lem\<close>.\<close>
+
+theory "Sail2_prompt_monad"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail2_instr_kinds"
+ "Sail2_values"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail_impl_base\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+
+type_synonym register_name =" string "
+type_synonym address =" bitU list "
+
+datatype( 'regval, 'a, 'e) monad =
+ Done " 'a "
+ \<comment> \<open>\<open> Read a number of bytes from memory, returned in little endian order,
+ with or without a tag. The first nat specifies the address, the second
+ the number of bytes. \<close>\<close>
+ | Read_mem " read_kind " " nat " " nat " " ( memory_byte list \<Rightarrow> ('regval, 'a, 'e) monad)"
+ | Read_memt " read_kind " " nat " " nat " " (( memory_byte list * bitU) \<Rightarrow> ('regval, 'a, 'e) monad)"
+ \<comment> \<open>\<open> Tell the system a write is imminent, at the given address and with the
+ given size. \<close>\<close>
+ | Write_ea " write_kind " " nat " " nat " " ('regval, 'a, 'e) monad "
+ \<comment> \<open>\<open> Request the result of store-exclusive \<close>\<close>
+ | Excl_res " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+ \<comment> \<open>\<open> Request to write a memory value of the given size at the given address,
+ with or without a tag. \<close>\<close>
+ | Write_mem " write_kind " " nat " " nat " " memory_byte list " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+ | Write_memt " write_kind " " nat " " nat " " memory_byte list " " bitU " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+ \<comment> \<open>\<open> Tell the system to dynamically recalculate dependency footprint \<close>\<close>
+ | Footprint " ('regval, 'a, 'e) monad "
+ \<comment> \<open>\<open> Request a memory barrier \<close>\<close>
+ | Barrier " barrier_kind " " ('regval, 'a, 'e) monad "
+ \<comment> \<open>\<open> Request to read register, will track dependency when mode.track_values \<close>\<close>
+ | Read_reg " register_name " " ('regval \<Rightarrow> ('regval, 'a, 'e) monad)"
+ \<comment> \<open>\<open> Request to write register \<close>\<close>
+ | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad "
+ \<comment> \<open>\<open> Request to choose a Boolean, e.g. to resolve an undefined bit. The string
+ argument may be used to provide information to the system about what the
+ Boolean is going to be used for. \<close>\<close>
+ | Choose " string " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)"
+ \<comment> \<open>\<open> Print debugging or tracing information \<close>\<close>
+ | Print " string " " ('regval, 'a, 'e) monad "
+ \<comment> \<open>\<open>Result of a failed assert with possible error message to report\<close>\<close>
+ | Fail " string "
+ \<comment> \<open>\<open> Exception of type 'e \<close>\<close>
+ | Exception " 'e "
+
+datatype 'regval event =
+ E_read_mem " read_kind " " nat " " nat " " memory_byte list "
+ | E_read_memt " read_kind " " nat " " nat " " ( memory_byte list * bitU)"
+ | E_write_mem " write_kind " " nat " " nat " " memory_byte list " " bool "
+ | E_write_memt " write_kind " " nat " " nat " " memory_byte list " " bitU " " bool "
+ | E_write_ea " write_kind " " nat " " nat "
+ | E_excl_res " bool "
+ | E_barrier " barrier_kind "
+ | E_footprint
+ | E_read_reg " register_name " " 'regval "
+ | E_write_reg " register_name " " 'regval "
+ | E_choose " string " " bool "
+ | E_print " string "
+
+type_synonym 'regval trace =" ( 'regval event) list "
+
+\<comment> \<open>\<open>val return : forall 'rv 'a 'e. 'a -> monad 'rv 'a 'e\<close>\<close>
+definition return :: " 'a \<Rightarrow>('rv,'a,'e)monad " where
+ " return a = ( Done a )"
+
+
+\<comment> \<open>\<open>val bind : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e\<close>\<close>
+function (sequential,domintros) bind :: "('rv,'a,'e)monad \<Rightarrow>('a \<Rightarrow>('rv,'b,'e)monad)\<Rightarrow>('rv,'b,'e)monad " where
+ " bind (Done a) f = ( f a )"
+|" bind (Read_mem rk a sz k) f = ( Read_mem rk a sz (\<lambda> v . bind (k v) f))"
+|" bind (Read_memt rk a sz k) f = ( Read_memt rk a sz (\<lambda> v . bind (k v) f))"
+|" bind (Write_mem wk a sz v k) f = ( Write_mem wk a sz v (\<lambda> v . bind (k v) f))"
+|" bind (Write_memt wk a sz v t k) f = ( Write_memt wk a sz v t (\<lambda> v . bind (k v) f))"
+|" bind (Read_reg descr k) f = ( Read_reg descr (\<lambda> v . bind (k v) f))"
+|" bind (Excl_res k) f = ( Excl_res (\<lambda> v . bind (k v) f))"
+|" bind (Choose descr k) f = ( Choose descr (\<lambda> v . bind (k v) f))"
+|" bind (Write_ea wk a sz k) f = ( Write_ea wk a sz (bind k f))"
+|" bind (Footprint k) f = ( Footprint (bind k f))"
+|" bind (Barrier bk k) f = ( Barrier bk (bind k f))"
+|" bind (Write_reg r v k) f = ( Write_reg r v (bind k f))"
+|" bind (Print msg k) f = ( Print msg (bind k f))"
+|" bind (Fail descr) f = ( Fail descr )"
+|" bind (Exception e) f = ( Exception e )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val exit : forall 'rv 'a 'e. unit -> monad 'rv 'a 'e\<close>\<close>
+definition exit0 :: " unit \<Rightarrow>('rv,'a,'e)monad " where
+ " exit0 _ = ( Fail (''exit''))"
+
+
+\<comment> \<open>\<open>val choose_bool : forall 'rv 'e. string -> monad 'rv bool 'e\<close>\<close>
+definition choose_bool :: " string \<Rightarrow>('rv,(bool),'e)monad " where
+ " choose_bool descr = ( Choose descr return )"
+
+
+\<comment> \<open>\<open>val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e\<close>\<close>
+definition undefined_bool :: " unit \<Rightarrow>('rv,(bool),'e)monad " where
+ " undefined_bool _ = ( choose_bool (''undefined_bool''))"
+
+
+\<comment> \<open>\<open>val assert_exp : forall 'rv 'e. bool -> string -> monad 'rv unit 'e\<close>\<close>
+definition assert_exp :: " bool \<Rightarrow> string \<Rightarrow>('rv,(unit),'e)monad " where
+ " assert_exp exp1 msg = ( if exp1 then Done () else Fail msg )"
+
+
+\<comment> \<open>\<open>val throw : forall 'rv 'a 'e. 'e -> monad 'rv 'a 'e\<close>\<close>
+definition throw :: " 'e \<Rightarrow>('rv,'a,'e)monad " where
+ " throw e = ( Exception e )"
+
+
+\<comment> \<open>\<open>val try_catch : forall 'rv 'a 'e1 'e2. monad 'rv 'a 'e1 -> ('e1 -> monad 'rv 'a 'e2) -> monad 'rv 'a 'e2\<close>\<close>
+function (sequential,domintros) try_catch :: "('rv,'a,'e1)monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,'e2)monad)\<Rightarrow>('rv,'a,'e2)monad " where
+ " try_catch (Done a) h = ( Done a )"
+|" try_catch (Read_mem rk a sz k) h = ( Read_mem rk a sz (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Read_memt rk a sz k) h = ( Read_memt rk a sz (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Write_mem wk a sz v k) h = ( Write_mem wk a sz v (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Write_memt wk a sz v t k) h = ( Write_memt wk a sz v t (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Read_reg descr k) h = ( Read_reg descr (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Excl_res k) h = ( Excl_res (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Choose descr k) h = ( Choose descr (\<lambda> v . try_catch (k v) h))"
+|" try_catch (Write_ea wk a sz k) h = ( Write_ea wk a sz (try_catch k h))"
+|" try_catch (Footprint k) h = ( Footprint (try_catch k h))"
+|" try_catch (Barrier bk k) h = ( Barrier bk (try_catch k h))"
+|" try_catch (Write_reg r v k) h = ( Write_reg r v (try_catch k h))"
+|" try_catch (Print msg k) h = ( Print msg (try_catch k h))"
+|" try_catch (Fail descr) h = ( Fail descr )"
+|" try_catch (Exception e) h = ( h e )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open> For early return, we abuse exceptions by throwing and catching
+ the return value. The exception type is "either 'r 'e", where "Right e"
+ represents a proper exception and "Left r" an early return of value "r". \<close>\<close>
+type_synonym( 'rv, 'a, 'r, 'e) monadR =" ('rv, 'a, ( ('r, 'e)sum)) monad "
+
+\<comment> \<open>\<open>val early_return : forall 'rv 'a 'r 'e. 'r -> monadR 'rv 'a 'r 'e\<close>\<close>
+definition early_return :: " 'r \<Rightarrow>('rv,'a,(('r,'e)sum))monad " where
+ " early_return r = ( throw (Inl r))"
+
+
+\<comment> \<open>\<open>val catch_early_return : forall 'rv 'a 'e. monadR 'rv 'a 'a 'e -> monad 'rv 'a 'e\<close>\<close>
+definition catch_early_return :: "('rv,'a,(('a,'e)sum))monad \<Rightarrow>('rv,'a,'e)monad " where
+ " catch_early_return m = (
+ try_catch m
+ (\<lambda>x . (case x of Inl a => return a | Inr e => throw e )))"
+
+
+\<comment> \<open>\<open> Lift to monad with early return by wrapping exceptions \<close>\<close>
+\<comment> \<open>\<open>val liftR : forall 'rv 'a 'r 'e. monad 'rv 'a 'e -> monadR 'rv 'a 'r 'e\<close>\<close>
+definition liftR :: "('rv,'a,'e)monad \<Rightarrow>('rv,'a,(('r,'e)sum))monad " where
+ " liftR m = ( try_catch m (\<lambda> e . throw (Inr e)))"
+
+
+\<comment> \<open>\<open> Catch exceptions in the presence of early returns \<close>\<close>
+\<comment> \<open>\<open>val try_catchR : forall 'rv 'a 'r 'e1 'e2. monadR 'rv 'a 'r 'e1 -> ('e1 -> monadR 'rv 'a 'r 'e2) -> monadR 'rv 'a 'r 'e2\<close>\<close>
+definition try_catchR :: "('rv,'a,(('r,'e1)sum))monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,(('r,'e2)sum))monad)\<Rightarrow>('rv,'a,(('r,'e2)sum))monad " where
+ " try_catchR m h = (
+ try_catch m
+ (\<lambda>x . (case x of Inl r => throw (Inl r) | Inr e => h e )))"
+
+
+\<comment> \<open>\<open>val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e\<close>\<close>
+definition maybe_fail :: " string \<Rightarrow> 'a option \<Rightarrow>('rv,'a,'e)monad " where
+ " maybe_fail msg = ( \<lambda>x .
+ (case x of Some a => return a | None => Fail msg ) )"
+
+
+\<comment> \<open>\<open>val read_memt_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte * bitU) 'e\<close>\<close>
+definition read_memt_bytes :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list*bitU),'e)monad " where
+ " read_memt_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = (
+ bind
+ (maybe_fail (''nat_of_bv'') (nat_of_bv
+ dict_Sail2_values_Bitvector_a addr))
+ (\<lambda> addr . Read_memt rk addr (nat_of_int sz) return))"
+
+
+\<comment> \<open>\<open>val read_memt : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv ('b * bitU) 'e\<close>\<close>
+definition read_memt :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,('b*bitU),'e)monad " where
+ " read_memt dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = (
+ bind
+ (read_memt_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_a rk addr sz)
+ ( \<lambda>x . (case x of
+ (bytes, tag) =>
+ (case (of_bits_method dict_Sail2_values_Bitvector_b)
+ (bits_of_mem_bytes bytes) of
+ Some v => return (v, tag)
+ | None => Fail (''bits_of_mem_bytes'')
+ )
+ )))"
+
+
+\<comment> \<open>\<open>val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e\<close>\<close>
+definition read_mem_bytes :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list),'e)monad " where
+ " read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = (
+ bind
+ (maybe_fail (''nat_of_bv'') (nat_of_bv
+ dict_Sail2_values_Bitvector_a addr))
+ (\<lambda> addr . Read_mem rk addr (nat_of_int sz) return))"
+
+
+\<comment> \<open>\<open>val read_mem : forall 'rv 'a 'b 'e 'addrsize. Bitvector 'a, Bitvector 'b => read_kind -> 'addrsize -> 'a -> integer -> monad 'rv 'b 'e\<close>\<close>
+definition read_mem :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'addrsize \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,'b,'e)monad " where
+ " read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr_sz addr sz = (
+ bind
+ (read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_a rk addr sz)
+ (\<lambda> bytes .
+ (case (of_bits_method dict_Sail2_values_Bitvector_b) (bits_of_mem_bytes bytes) of
+ Some v => return v
+ | None => Fail (''bits_of_mem_bytes'')
+ )))"
+
+
+\<comment> \<open>\<open>val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e\<close>\<close>
+definition excl_result :: " unit \<Rightarrow>('rv,(bool),'e)monad " where
+ " excl_result _ = (
+ (let k = (\<lambda> successful . (return successful)) in Excl_res k) )"
+
+
+\<comment> \<open>\<open>val write_mem_ea : forall 'rv 'a 'e 'addrsize. Bitvector 'a => write_kind -> 'addrsize -> 'a -> integer -> monad 'rv unit 'e\<close>\<close>
+definition write_mem_ea :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'addrsize \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where
+ " write_mem_ea dict_Sail2_values_Bitvector_a wk addr_size addr sz = (
+ bind
+ (maybe_fail (''nat_of_bv'') (nat_of_bv
+ dict_Sail2_values_Bitvector_a addr))
+ (\<lambda> addr . Write_ea wk addr (nat_of_int sz) (Done () )))"
+
+
+\<comment> \<open>\<open>val write_mem : forall 'rv 'a 'b 'e 'addrsize. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'addrsize -> 'a -> integer -> 'b -> monad 'rv bool 'e\<close>\<close>
+definition write_mem :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'addrsize \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('rv,(bool),'e)monad " where
+ " write_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr_size addr sz v = (
+ (case (mem_bytes_of_bits
+ dict_Sail2_values_Bitvector_b v, nat_of_bv dict_Sail2_values_Bitvector_a addr) of
+ (Some v, Some addr) =>
+ Write_mem wk addr (nat_of_int sz) v return
+ | _ => Fail (''write_mem'')
+ ))"
+
+
+\<comment> \<open>\<open>val write_memt : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> bitU -> monad 'rv bool 'e\<close>\<close>
+definition write_memt :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow> bitU \<Rightarrow>('rv,(bool),'e)monad " where
+ " write_memt dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr sz v tag = (
+ (case (mem_bytes_of_bits
+ dict_Sail2_values_Bitvector_b v, nat_of_bv dict_Sail2_values_Bitvector_a addr) of
+ (Some v, Some addr) =>
+ Write_memt wk addr (nat_of_int sz) v tag return
+ | _ => Fail (''write_mem'')
+ ))"
+
+
+\<comment> \<open>\<open>val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e\<close>\<close>
+definition read_reg :: "('s,'rv,'a)register_ref \<Rightarrow>('rv,'a,'e)monad " where
+ " read_reg reg = (
+ (let k = (\<lambda> v .
+ (case (of_regval reg) v of
+ Some v => Done v
+ | None => Fail (''read_reg: unrecognised value'')
+ )) in Read_reg (name reg) k) )"
+
+
+\<comment> \<open>\<open> TODO
+val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e
+let read_reg_range reg i j =
+ read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j))
+
+let read_reg_bit reg i =
+ read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v ->
+ return (extract_only_element v)
+
+let read_reg_field reg regfield =
+ read_reg_aux (external_reg_field_whole reg regfield)
+
+let read_reg_bitfield reg regfield =
+ read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
+ return (extract_only_element v)\<close>\<close>
+
+definition reg_deref :: "('d,'c,'b)register_ref \<Rightarrow>('c,'b,'a)monad " where
+ " reg_deref = ( read_reg )"
+
+
+\<comment> \<open>\<open>val write_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> 'a -> monad 'rv unit 'e\<close>\<close>
+definition write_reg :: "('s,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad " where
+ " write_reg reg v = ( Write_reg(name reg) ((regval_of reg) v) (Done () ))"
+
+
+\<comment> \<open>\<open> TODO
+let write_reg reg v =
+ write_reg_aux (external_reg_whole reg) v
+let write_reg_range reg i j v =
+ write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v
+let write_reg_pos reg i v =
+ let iN = nat_of_int i in
+ write_reg_aux (external_reg_slice reg (iN,iN)) [v]
+let write_reg_bit = write_reg_pos
+let write_reg_field reg regfield v =
+ write_reg_aux (external_reg_field_whole reg regfield.field_name) v
+let write_reg_field_bit reg regfield bit =
+ write_reg_aux (external_reg_field_whole reg regfield.field_name)
+ (Vector [bit] 0 (is_inc_of_reg reg))
+let write_reg_field_range reg regfield i j v =
+ write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v
+let write_reg_field_pos reg regfield i v =
+ write_reg_field_range reg regfield i i [v]
+let write_reg_field_bit = write_reg_field_pos\<close>\<close>
+
+\<comment> \<open>\<open>val barrier : forall 'rv 'e. barrier_kind -> monad 'rv unit 'e\<close>\<close>
+definition barrier :: " barrier_kind \<Rightarrow>('rv,(unit),'e)monad " where
+ " barrier bk = ( Barrier bk (Done () ))"
+
+
+\<comment> \<open>\<open>val footprint : forall 'rv 'e. unit -> monad 'rv unit 'e\<close>\<close>
+definition footprint :: " unit \<Rightarrow>('rv,(unit),'e)monad " where
+ " footprint _ = ( Footprint (Done () ))"
+
+
+\<comment> \<open>\<open> Event traces \<close>\<close>
+
+\<comment> \<open>\<open>val emitEvent : forall 'regval 'a 'e. Eq 'regval => monad 'regval 'a 'e -> event 'regval -> maybe (monad 'regval 'a 'e)\<close>\<close>
+definition emitEvent :: "('regval,'a,'e)monad \<Rightarrow> 'regval event \<Rightarrow>(('regval,'a,'e)monad)option " where
+ " emitEvent m e = ( (case (e, m) of
+ (E_read_mem rk a sz v, Read_mem rk' a' sz' k) =>
+ if (rk' = rk) \<and> ((a' = a) \<and> (sz' = sz)) then Some (k v) else None
+ | (E_read_memt rk a sz vt, Read_memt rk' a' sz' k) =>
+ if (rk' = rk) \<and> ((a' = a) \<and> (sz' = sz)) then Some (k vt) else None
+ | (E_write_mem wk a sz v r, Write_mem wk' a' sz' v' k) =>
+ if (wk' = wk) \<and> ((a' = a) \<and> ((sz' = sz) \<and> (v' = v))) then Some (k r) else None
+ | (E_write_memt wk a sz v tag r, Write_memt wk' a' sz' v' tag' k) =>
+ if (wk' = wk) \<and> ((a' = a) \<and> ((sz' = sz) \<and> ((v' = v) \<and> (tag' = tag)))) then Some (k r) else None
+ | (E_read_reg r v, Read_reg r' k) =>
+ if r' = r then Some (k v) else None
+ | (E_write_reg r v, Write_reg r' v' k) =>
+ if (r' = r) \<and> (v' = v) then Some k else None
+ | (E_write_ea wk a sz, Write_ea wk' a' sz' k) =>
+ if (wk' = wk) \<and> ((a' = a) \<and> (sz' = sz)) then Some k else None
+ | (E_barrier bk, Barrier bk' k) =>
+ if bk' = bk then Some k else None
+ | (E_print m, Print m' k) =>
+ if m' = m then Some k else None
+ | (E_excl_res v, Excl_res k) => Some (k v)
+ | (E_choose descr v, Choose descr' k) => if descr' = descr then Some (k v) else None
+ | (E_footprint, Footprint k) => Some k
+ | _ => None
+))"
+
+
+\<comment> \<open>\<open>val runTrace : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> maybe (monad 'regval 'a 'e)\<close>\<close>
+fun runTrace :: "('regval event)list \<Rightarrow>('regval,'a,'e)monad \<Rightarrow>(('regval,'a,'e)monad)option " where
+ " runTrace ([]) m = ( Some m )"
+|" runTrace (e # t') m = ( Option.bind (emitEvent m e) (runTrace t'))"
+
+
+\<comment> \<open>\<open>val final : forall 'regval 'a 'e. monad 'regval 'a 'e -> bool\<close>\<close>
+definition final :: "('regval,'a,'e)monad \<Rightarrow> bool " where
+ " final = ( \<lambda>x .
+ (case x of
+ Done _ => True
+ | Fail _ => True
+ | Exception _ => True
+ | _ => False
+ ) )"
+
+
+\<comment> \<open>\<open>val hasTrace : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool\<close>\<close>
+definition hasTrace :: "('regval event)list \<Rightarrow>('regval,'a,'e)monad \<Rightarrow> bool " where
+ " hasTrace t m = ( (case runTrace t m of
+ Some m => final m
+ | None => False
+))"
+
+
+\<comment> \<open>\<open>val hasException : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool\<close>\<close>
+definition hasException :: "('regval event)list \<Rightarrow>('regval,'a,'e)monad \<Rightarrow> bool " where
+ " hasException t m = ( (case runTrace t m of
+ Some (Exception _) => True
+ | _ => False
+))"
+
+
+\<comment> \<open>\<open>val hasFailure : forall 'regval 'a 'e. Eq 'regval => trace 'regval -> monad 'regval 'a 'e -> bool\<close>\<close>
+definition hasFailure :: "('regval event)list \<Rightarrow>('regval,'a,'e)monad \<Rightarrow> bool " where
+ " hasFailure t m = ( (case runTrace t m of
+ Some (Fail _) => True
+ | _ => False
+))"
+
+
+\<comment> \<open>\<open> Define a type synonym that also takes the register state as a type parameter,
+ in order to make switching to the state monad without changing generated
+ definitions easier, see also lib/hol/prompt_monad.lem. \<close>\<close>
+
+type_synonym( 'regval, 'regstate, 'a, 'e) base_monad =" ('regval, 'a, 'e) monad "
+type_synonym( 'regval, 'regstate, 'a, 'r, 'e) base_monadR =" ('regval, 'a, 'r, 'e) monadR "
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy b/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy
new file mode 100644
index 0000000..1fde328
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy
@@ -0,0 +1,384 @@
+theory Sail2_prompt_monad_lemmas
+ imports
+ Sail2_prompt_monad
+ Sail2_values_lemmas
+begin
+
+notation bind (infixr "\<bind>" 54)
+
+abbreviation seq :: "('rv,unit,'e)monad \<Rightarrow> ('rv,'b,'e)monad \<Rightarrow>('rv,'b,'e)monad" (infixr "\<then>" 54) where
+ "m \<then> n \<equiv> m \<bind> (\<lambda>_. n)"
+
+lemma All_bind_dom: "bind_dom (m, f)"
+ by (induction m) (auto intro: bind.domintros)
+
+termination bind using All_bind_dom by auto
+lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = bind.induct
+
+lemma bind_return[simp]: "bind (return a) f = f a"
+ by (auto simp: return_def)
+lemma bind_return_right[simp]: "bind x return = x" by (induction x) (auto simp: return_def)
+
+lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\<lambda>x. bind (f x) g)"
+ by (induction m f arbitrary: g rule: bind.induct) auto
+
+lemma bind_assert_True[simp]: "bind (assert_exp True msg) f = f ()"
+ by (auto simp: assert_exp_def)
+
+lemma All_try_catch_dom: "try_catch_dom (m, h)"
+ by (induction m) (auto intro: try_catch.domintros)
+termination try_catch using All_try_catch_dom by auto
+lemmas try_catch_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = try_catch.induct
+
+inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, 'e) monad) set" where
+ Read_mem: "((Read_mem rk addr sz k), E_read_mem rk addr sz v, k v) \<in> T"
+| Read_memt: "((Read_memt rk addr sz k), E_read_memt rk addr sz v, k v) \<in> T"
+| Write_ea: "((Write_ea wk addr sz k), E_write_ea wk addr sz, k) \<in> T"
+| Excl_res: "((Excl_res k), E_excl_res r, k r) \<in> T"
+| Write_mem: "((Write_mem wk addr sz v k), E_write_mem wk addr sz v r, k r) \<in> T"
+| Write_memt: "((Write_memt wk addr sz v t k), E_write_memt wk addr sz v t r, k r) \<in> T"
+| Footprint: "((Footprint k), E_footprint, k) \<in> T"
+| Barrier: "((Barrier bk k), E_barrier bk, k) \<in> T"
+| Read_reg: "((Read_reg r k), E_read_reg r v, k v) \<in> T"
+| Write_reg: "((Write_reg r v k), E_write_reg r v, k) \<in> T"
+| Choose: "((Choose descr k), E_choose descr v, k v) \<in> T"
+| Print: "((Print msg k), E_print msg, k) \<in> T"
+
+lemma emitEvent_iff_T: "emitEvent m e = Some m' \<longleftrightarrow> (m, e, m') \<in> T"
+ by (cases e) (auto simp: emitEvent_def elim: T.cases intro: T.intros split: monad.splits)
+
+inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where
+ Nil: "(s, [], s) \<in> Traces"
+| Step: "\<lbrakk>(s, e, s'') \<in> T; (s'', t, s') \<in> Traces\<rbrakk> \<Longrightarrow> (s, e # t, s') \<in> Traces"
+
+declare Traces.intros[intro]
+declare T.intros[intro]
+
+declare prod.splits[split]
+
+lemmas Traces_ConsI = T.intros[THEN Step, rotated]
+
+inductive_cases Traces_NilE[elim]: "(s, [], s') \<in> Traces"
+inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \<in> Traces"
+
+lemma runTrace_iff_Traces: "runTrace t m = Some m' \<longleftrightarrow> (m, t, m') \<in> Traces"
+ by (induction t m rule: runTrace.induct; fastforce simp: bind_eq_Some_conv emitEvent_iff_T)
+
+lemma hasTrace_iff_Traces_final: "hasTrace t m \<longleftrightarrow> (\<exists>m'. (m, t, m') \<in> Traces \<and> final m')"
+ by (auto simp: hasTrace_def runTrace_iff_Traces[symmetric] split: option.splits)
+
+lemma Traces_cases:
+ fixes m :: "('rv, 'a, 'e) monad"
+ assumes Run: "(m, t, m') \<in> Traces"
+ obtains (Nil) a where "m = m'" and "t = []"
+ | (Read_mem) rk addr s k t' v where "m = Read_mem rk addr s k" and "t = E_read_mem rk addr s v # t'" and "(k v, t', m') \<in> Traces"
+ | (Read_memt) rk addr s k t' v tag where "m = Read_memt rk addr s k" and "t = E_read_memt rk addr s (v, tag) # t'" and "(k (v, tag), t', m') \<in> Traces"
+ | (Write_mem) wk addr sz val k v t' where "m = Write_mem wk addr sz val k" and "t = E_write_mem wk addr sz val v # t'" and "(k v, t', m') \<in> Traces"
+ | (Write_memt) wk addr sz val tag k t' v where "m = Write_memt wk addr sz val tag k" and "t = E_write_memt wk addr sz val tag v # t'" and "(k v, t', m') \<in> Traces"
+ | (Barrier) bk k t' v where "m = Barrier bk k" and "t = E_barrier bk # t'" and "(k, t', m') \<in> Traces"
+ | (Read_reg) reg k t' v where "m = Read_reg reg k" and "t = E_read_reg reg v # t'" and "(k v, t', m') \<in> Traces"
+ | (Excl_res) k t' v where "m = Excl_res k" and "t = E_excl_res v # t'" and "(k v, t', m') \<in> Traces"
+ | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = E_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces"
+ | (Footprint) k t' where "m = Footprint k" and "t = E_footprint # t'" and "(k, t', m') \<in> Traces"
+ | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = E_write_reg reg v # t'" and "(k, t', m') \<in> Traces"
+ | (Choose) descr v k t' where "m = Choose descr k" and "t = E_choose descr v # t'" and "(k v, t', m') \<in> Traces"
+ | (Print) msg k t' where "m = Print msg k" and "t = E_print msg # t'" and "(k, t', m') \<in> Traces"
+proof (use Run in \<open>cases m t m' set: Traces\<close>)
+ case Nil
+ then show ?thesis by (auto intro: that(1))
+next
+ case (Step e m'' t')
+ note t = \<open>t = e # t'\<close>
+ note m' = \<open>(m'', t', m') \<in> Traces\<close>
+ from \<open>(m, e, m'') \<in> T\<close> and t and m'
+ show ?thesis proof (cases m e m'' rule: T.cases)
+ case (Read_memt rk addr sz k v)
+ then show ?thesis using t m' by (cases v; elim that; blast)
+ qed (elim that; blast)+
+qed
+
+abbreviation Run :: "('rv, 'a, 'e) monad \<Rightarrow> 'rv event list \<Rightarrow> 'a \<Rightarrow> bool"
+ where "Run s t a \<equiv> (s, t, Done a) \<in> Traces"
+
+lemma final_cases:
+ assumes "final m"
+ obtains (Done) a where "m = Done a" | (Fail) f where "m = Fail f" | (Ex) e where "m = Exception e"
+ using assms by (cases m) (auto simp: final_def)
+
+lemma hasTraces_elim:
+ assumes "hasTrace t m"
+ obtains m' where "(m, t, m') \<in> Traces" and "final m'"
+ using assms
+ unfolding hasTrace_iff_Traces_final
+ by blast
+
+lemma hasTrace_cases:
+ assumes "hasTrace t m"
+ obtains (Run) a where "Run m t a"
+ | (Fail) f where "(m, t, Fail f) \<in> Traces"
+ | (Ex) e where "(m, t, Exception e) \<in> Traces"
+ using assms by (elim hasTraces_elim final_cases) auto
+
+lemma Traces_appendI:
+ assumes "(s, t1, s') \<in> Traces"
+ and "(s', t2, s'') \<in> Traces"
+ shows "(s, t1 @ t2, s'') \<in> Traces"
+proof (use assms in \<open>induction t1 arbitrary: s\<close>)
+ case (Cons e t1)
+ then show ?case by (elim Traces_ConsE) auto
+qed auto
+
+lemma bind_DoneE:
+ assumes "bind m f = Done a"
+ obtains a' where "m = Done a'" and "f a' = Done a"
+ using assms by (auto elim: bind.elims)
+
+lemma bind_T_cases:
+ assumes "(bind m f, e, s') \<in> T"
+ obtains (Done) a where "m = Done a" and "(f a, e, s') \<in> T"
+ | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T"
+ using assms by (cases; fastforce elim: bind.elims)
+
+lemma Traces_bindI:
+ fixes m :: "('r, 'a, 'e) monad"
+ assumes "Run m t1 a1"
+ and "(f a1, t2, m') \<in> Traces"
+ shows "(m \<bind> f, t1 @ t2, m') \<in> Traces"
+proof (use assms in \<open>induction m t1 "Done a1 :: ('r, 'a, 'e) monad" rule: Traces.induct\<close>)
+ case (Step s e s'' t)
+ then show ?case by (elim T.cases) auto
+qed auto
+
+lemma Run_DoneE:
+ assumes "Run (Done a) t a'"
+ obtains "t = []" and "a' = a"
+ using assms by (auto elim: Traces.cases T.cases)
+
+lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a"
+ by (auto elim: Run_DoneE)
+
+lemma Run_Nil_iff_Done: "Run m [] a \<longleftrightarrow> m = Done a"
+ by auto
+
+lemma Traces_Nil_iff: "(m, [], m') \<in> Traces \<longleftrightarrow> m' = m"
+ by auto
+
+lemma bind_Traces_cases:
+ assumes "(m \<bind> f, t, m') \<in> Traces"
+ obtains (Left) m'' where "(m, t, m'') \<in> Traces" and "m' = m'' \<bind> f"
+ | (Bind) tm am tf where "t = tm @ tf" and "Run m tm am" and "(f am, tf, m') \<in> Traces"
+proof (use assms in \<open>induction "bind m f" t m' arbitrary: m rule: Traces.induct\<close>)
+ case Nil
+ then show ?case by (auto simp: Traces_Nil_iff)
+next
+ case (Step e s'' t s')
+ note IH = Step(3)
+ note Left' = Step(4)
+ note Bind' = Step(5)
+ show thesis
+ proof (use \<open>(m \<bind> f, e, s'') \<in> T\<close> in \<open>cases rule: bind_T_cases\<close>)
+ case (Done a)
+ then show ?thesis using \<open>(s'', t, s') \<in> Traces\<close> Step(5)[of "[]" "e # t" a] by auto
+ next
+ case (Bind m')
+ show ?thesis
+ proof (rule IH)
+ show "s'' = m' \<bind> f" using Bind by blast
+ next
+ fix m''
+ assume "(m', t, m'') \<in> Traces" and "s' = m'' \<bind> f"
+ then show thesis using \<open>(m, e, m') \<in> T\<close> Left'[of m''] by auto
+ next
+ fix tm tf am
+ assume "t = tm @ tf" and "Run m' tm am" and "(f am, tf, s') \<in> Traces"
+ then show thesis using \<open>(m, e, m') \<in> T\<close> Bind'[of "e # tm" tf am] by auto
+ qed
+ qed
+qed
+
+lemma final_bind_cases:
+ assumes "final (m \<bind> f)"
+ obtains (Done) a where "m = Done a" and "final (f a)"
+ | (Fail) msg where "m = Fail msg"
+ | (Ex) e where "m = Exception e"
+ using assms by (cases m) (auto simp: final_def)
+
+lemma hasFailure_iff_Traces_Fail: "hasFailure t m \<longleftrightarrow> (\<exists>msg. (m, t, Fail msg) \<in> Traces)"
+ by (auto simp: hasFailure_def runTrace_iff_Traces[symmetric] split: option.splits monad.splits)
+
+lemma hasException_iff_Traces_Exception: "hasException t m \<longleftrightarrow> (\<exists>e. (m, t, Exception e) \<in> Traces)"
+ by (auto simp: hasException_def runTrace_iff_Traces[symmetric] split: option.splits monad.splits)
+
+lemma hasTrace_bind_cases:
+ assumes "hasTrace t (m \<bind> f)"
+ obtains (Bind) tm am tf where "t = tm @ tf" and "Run m tm am" and "hasTrace tf (f am)"
+ | (Fail) "hasFailure t m"
+ | (Ex) "hasException t m"
+proof -
+ from assms obtain m' where t: "(m \<bind> f, t, m') \<in> Traces" and m': "final m'"
+ by (auto simp: hasTrace_iff_Traces_final)
+ note [simp] = hasTrace_iff_Traces_final hasFailure_iff_Traces_Fail hasException_iff_Traces_Exception
+ from t show thesis
+ proof (cases rule: bind_Traces_cases)
+ case (Left m'')
+ then show ?thesis
+ using m' Fail Ex Bind[of t "[]"]
+ by (fastforce elim!: final_bind_cases)
+ next
+ case (Bind tm am tf)
+ then show ?thesis
+ using m' that
+ by fastforce
+ qed
+qed
+
+lemma try_catch_T_cases:
+ assumes "(try_catch m h, e, m') \<in> T"
+ obtains (NoEx) m'' where "(m, e, m'') \<in> T" and "m' = try_catch m'' h"
+ | (Ex) ex where "m = Exception ex" and "(h ex, e, m') \<in> T"
+ using assms
+ by (cases m) (auto elim!: T.cases)
+
+lemma try_catch_Traces_cases:
+ assumes "(try_catch m h, t, mtc) \<in> Traces"
+ obtains (NoEx) m' where "(m, t, m') \<in> Traces" and "mtc = try_catch m' h"
+ | (Ex) tm ex th where "(m, tm, Exception ex) \<in> Traces" and "(h ex, th, mtc) \<in> Traces" and "t = tm @ th"
+proof (use assms in \<open>induction "try_catch m h" t mtc arbitrary: m rule: Traces.induct\<close>)
+ case Nil
+ then show ?case by auto
+next
+ case (Step e mtc' t mtc)
+ note e = \<open>(try_catch m h, e, mtc') \<in> T\<close>
+ note t = \<open>(mtc', t, mtc) \<in> Traces\<close>
+ note IH = Step(3)
+ note NoEx_ConsE = Step(4)
+ note Ex_ConsE = Step(5)
+ show ?case
+ proof (use e in \<open>cases rule: try_catch_T_cases\<close>)
+ case (NoEx m1)
+ show ?thesis
+ proof (rule IH)
+ show "mtc' = try_catch m1 h" using NoEx by auto
+ next
+ fix m'
+ assume "(m1, t, m') \<in> Traces" and "mtc = try_catch m' h"
+ then show ?thesis
+ using NoEx NoEx_ConsE[of m']
+ by auto
+ next
+ fix tm ex th
+ assume "(m1, tm, Exception ex) \<in> Traces" and "(h ex, th, mtc) \<in> Traces" and "t = tm @ th"
+ then show ?thesis
+ using NoEx Ex_ConsE[of "e # tm" ex th]
+ by auto
+ qed
+ next
+ case (Ex ex)
+ then show ?thesis
+ using t Ex_ConsE[of "[]" ex "e # t"]
+ by auto
+ qed
+qed
+
+lemma Done_Traces_iff[simp]: "(Done a, t, m') \<in> Traces \<longleftrightarrow> t = [] \<and> m' = Done a"
+ by (auto elim: Traces_cases)
+
+lemma Fail_Traces_iff[simp]: "(Fail msg, t, m') \<in> Traces \<longleftrightarrow> t = [] \<and> m' = Fail msg"
+ by (auto elim: Traces_cases)
+
+lemma Exception_Traces_iff[simp]: "(Exception e, t, m') \<in> Traces \<longleftrightarrow> t = [] \<and> m' = Exception e"
+ by (auto elim: Traces_cases)
+
+lemma Read_reg_TracesE:
+ assumes "(Read_reg r k, t, m') \<in> Traces"
+ obtains (Nil) "t = []" and "m' = Read_reg r k"
+ | (Cons) v t' where "t = E_read_reg r v # t'" and "(k v, t', m') \<in> Traces"
+ using assms
+ by (auto elim: Traces_cases)
+
+lemma Write_reg_TracesE:
+ assumes "(Write_reg r v k, t, m') \<in> Traces"
+ obtains (Nil) "t = []" and "m' = Write_reg r v k"
+ | (Cons) t' where "t = E_write_reg r v # t'" and "(k, t', m') \<in> Traces"
+ using assms
+ by (auto elim: Traces_cases)
+
+lemma Write_ea_TracesE:
+ assumes "(Write_ea wk addr sz k, t, m') \<in> Traces"
+ obtains (Nil) "t = []" and "m' = Write_ea wk addr sz k"
+ | (Cons) t' where "t = E_write_ea wk addr sz # t'" and "(k, t', m') \<in> Traces"
+ using assms
+ by (auto elim: Traces_cases)
+
+lemma Write_memt_TracesE:
+ assumes "(Write_memt wk addr sz v tag k, t, m') \<in> Traces"
+ obtains (Nil) "t = []" and "m' = Write_memt wk addr sz v tag k"
+ | (Cons) t' r where "t = E_write_memt wk addr sz v tag r # t'" and "(k r, t', m') \<in> Traces"
+ using assms
+ by (auto elim: Traces_cases)
+
+lemma Run_bindE:
+ fixes m :: "('rv, 'b, 'e) monad" and a :: 'a
+ assumes "Run (bind m f) t a"
+ obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a"
+proof (use assms in \<open>induction "bind m f" t "Done a :: ('rv, 'a, 'e) monad" arbitrary: m rule: Traces.induct\<close>)
+ case Nil
+ obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE)
+ then show ?case by (intro Nil(2)) auto
+next
+ case (Step e s'' t m)
+ show thesis using Step(1)
+ proof (cases rule: bind_T_cases)
+ case (Done am)
+ then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto
+ next
+ case (Bind m')
+ show ?thesis proof (rule Step(3)[OF Bind(1)])
+ fix tm tf am
+ assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a"
+ then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto
+ qed
+ qed
+qed
+
+lemma Run_bindE_ignore_trace:
+ assumes "Run (m \<bind> f) t a"
+ obtains tm tf am where "Run m tm am" and "Run (f am) tf a"
+ using assms by (elim Run_bindE)
+
+lemma Run_letE:
+ assumes "Run (let x = y in f x) t a"
+ obtains "Run (f y) t a"
+ using assms by auto
+
+lemma Run_ifE:
+ assumes "Run (if b then f else g) t a"
+ obtains "b" and "Run f t a" | "\<not>b" and "Run g t a"
+ using assms by (auto split: if_splits)
+
+lemma Run_returnE:
+ assumes "Run (return x) t a"
+ obtains "t = []" and "a = x"
+ using assms by (auto simp: return_def)
+
+lemma Run_early_returnE:
+ assumes "Run (early_return x) t a"
+ shows P
+ using assms by (auto simp: early_return_def throw_def elim: Traces_cases)
+
+lemma bind_cong[fundef_cong]:
+ assumes m: "m1 = m2"
+ and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a"
+ shows "bind m1 f1 = bind m2 f2"
+ unfolding m using f
+ by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast)
+
+lemma liftR_read_reg[simp]: "liftR (read_reg reg) = read_reg reg" by (auto simp: read_reg_def liftR_def split: option.splits)
+lemma try_catch_return[simp]: "try_catch (return x) h = return x" by (auto simp: return_def)
+lemma try_catch_choose_bool[simp]: "try_catch (choose_bool descr) h = choose_bool descr" by (auto simp: choose_bool_def)
+lemma liftR_choose_bool[simp]: "liftR (choose_bool descr) = choose_bool descr" by (auto simp: choose_bool_def liftR_def)
+lemma liftR_return[simp]: "liftR (return x) = return x" by (auto simp: liftR_def)
+lemma liftR_undefined_bool[simp]: "liftR (undefined_bool ()) = undefined_bool ()" by (auto simp: undefined_bool_def)
+lemma assert_exp_True_return[simp]: "assert_exp True msg = return ()" by (auto simp: assert_exp_def return_def)
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_state.thy b/prover_snapshots/isabelle/lib/sail/Sail2_state.thy
new file mode 100644
index 0000000..60aff98
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_state.thy
@@ -0,0 +1,152 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_state.lem\<close>.\<close>
+
+theory "Sail2_state"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail2_values"
+ "Sail2_state_monad"
+ "Sail2_state_monad_lemmas"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_state_monad\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `Sail2_state_monad_lemmas`\<close>\<close>
+
+\<comment> \<open>\<open>val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e\<close>\<close>
+fun iterS_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS " where
+ " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))"
+|" iterS_aux i f ([]) = ( returnS () )"
+
+
+\<comment> \<open>\<open>val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e\<close>\<close>
+definition iteriS :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where
+ " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )"
+
+
+\<comment> \<open>\<open>val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e\<close>\<close>
+definition iterS :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where
+ " iterS f xs = ( iteriS ( \<lambda>x .
+ (case x of _ => \<lambda> x . f x )) xs )"
+
+
+\<comment> \<open>\<open>val foreachS : forall 'a 'rv 'vars 'e.
+ list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e\<close>\<close>
+fun foreachS :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where
+ " foreachS ([]) vars body = ( returnS vars )"
+|" foreachS (x # xs) vars body = ( bindS
+ (body x vars) (\<lambda> vars .
+ foreachS xs vars body))"
+
+
+\<comment> \<open>\<open>val genlistS : forall 'a 'rv 'e. (nat -> monadS 'rv 'a 'e) -> nat -> monadS 'rv (list 'a) 'e\<close>\<close>
+definition genlistS :: "(nat \<Rightarrow> 'rv sequential_state \<Rightarrow>(('a,'e)result*'rv sequential_state)set)\<Rightarrow> nat \<Rightarrow> 'rv sequential_state \<Rightarrow>((('a list),'e)result*'rv sequential_state)set " where
+ " genlistS f n = (
+ (let indices = (genlist (\<lambda> n . n) n) in
+ foreachS indices [] (\<lambda> n xs . ( bindS(f n) (\<lambda> x . returnS (xs @ [x]))))))"
+
+
+\<comment> \<open>\<open>val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e\<close>\<close>
+definition and_boolS :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS " where
+ " and_boolS l r = ( bindS l (\<lambda> l . if l then r else returnS False))"
+
+
+\<comment> \<open>\<open>val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e\<close>\<close>
+definition or_boolS :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS " where
+ " or_boolS l r = ( bindS l (\<lambda> l . if l then returnS True else r))"
+
+
+\<comment> \<open>\<open>val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e\<close>\<close>
+definition bool_of_bitU_fail :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set " where
+ " bool_of_bitU_fail = ( \<lambda>x .
+ (case x of
+ B0 => returnS False
+ | B1 => returnS True
+ | BU => failS (''bool_of_bitU'')
+ ) )"
+
+
+\<comment> \<open>\<open>val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e\<close>\<close>
+definition bool_of_bitU_nondetS :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set " where
+ " bool_of_bitU_nondetS = ( \<lambda>x .
+ (case x of
+ B0 => returnS False
+ | B1 => returnS True
+ | BU => undefined_boolS ()
+ ) )"
+
+
+\<comment> \<open>\<open>val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e\<close>\<close>
+definition bools_of_bits_nondetS :: "(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>((((bool)list),'e)result*'rv sequential_state)set " where
+ " bools_of_bits_nondetS bits = (
+ foreachS bits []
+ (\<lambda> b bools . bindS
+ (bool_of_bitU_nondetS b) (\<lambda> b .
+ returnS (bools @ [b]))))"
+
+
+\<comment> \<open>\<open>val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e\<close>\<close>
+definition of_bits_nondetS :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monadS " where
+ " of_bits_nondetS dict_Sail2_values_Bitvector_a bits = ( bindS
+ (bools_of_bits_nondetS bits) (\<lambda> bs .
+ returnS ((of_bools_method dict_Sail2_values_Bitvector_a) bs)))"
+
+
+\<comment> \<open>\<open>val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e\<close>\<close>
+definition of_bits_failS :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>(('a,'e)result*'rv sequential_state)set " where
+ " of_bits_failS dict_Sail2_values_Bitvector_a bits = ( maybe_failS (''of_bits'') (
+ (of_bits_method dict_Sail2_values_Bitvector_a) bits))"
+
+
+\<comment> \<open>\<open>val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e\<close>\<close>
+definition mword_nondetS :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monadS " where
+ " mword_nondetS _ = ( bindS
+ (bools_of_bits_nondetS (repeat [BU] (int (len_of (TYPE(_) :: 'a itself))))) (\<lambda> bs .
+ returnS (Word.of_bl bs)))"
+
+
+
+\<comment> \<open>\<open>val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e\<close>\<close>
+function (sequential,domintros) whileS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where
+ " whileS vars cond body s = (
+ ( bindS(cond vars) (\<lambda> cond_val s' .
+ if cond_val then
+ ( bindS(body vars) (\<lambda> vars s'' . whileS vars cond body s'')) s'
+ else returnS vars s')) s )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+ ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e\<close>\<close>
+function (sequential,domintros) untilS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where
+ " untilS vars cond body s = (
+ ( bindS(body vars) (\<lambda> vars s' .
+ ( bindS(cond vars) (\<lambda> cond_val s'' .
+ if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val choose_boolsS : forall 'rv 'e. nat -> monadS 'rv (list bool) 'e\<close>\<close>
+definition choose_boolsS :: " nat \<Rightarrow> 'rv sequential_state \<Rightarrow>((((bool)list),'e)result*'rv sequential_state)set " where
+ " choose_boolsS n = ( genlistS ( \<lambda>x .
+ (case x of _ => choose_boolS () )) n )"
+
+
+\<comment> \<open>\<open> TODO: Replace by chooseS and prove equivalence to prompt monad version \<close>\<close>
+\<comment> \<open>\<open>val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e\<close>\<close>
+definition internal_pickS :: " 'a list \<Rightarrow>('rv,'a,'e)monadS " where
+ " internal_pickS xs = ( bindS
+ (
+ \<comment> \<open>\<open> Use sufficiently many nondeterministically chosen bits and convert into an
+ index into the list \<close>\<close>choose_boolsS (List.length xs)) (\<lambda> bs .
+ (let idx = (( (nat_of_bools bs)) mod List.length xs) in
+ (case index xs idx of
+ Some x => returnS x
+ | None => failS (''choose internal_pick'')
+ ))))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy b/prover_snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy
new file mode 100644
index 0000000..8be5cc6
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy
@@ -0,0 +1,536 @@
+theory Sail2_state_lemmas
+ imports Sail2_state Sail2_state_lifting
+begin
+
+text \<open>Monad lifting\<close>
+
+lemma All_liftState_dom: "liftState_dom (r, m)"
+ by (induction m) (auto intro: liftState.domintros)
+termination liftState using All_liftState_dom by auto
+
+named_theorems liftState_simp
+
+lemma liftState_bind[liftState_simp]:
+ "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)"
+ by (induction m f rule: bind.induct) auto
+
+lemma liftState_return[liftState_simp]: "liftState r (return a) = returnS a" by (auto simp: return_def)
+
+lemma Value_liftState_Run:
+ assumes "(Value a, s') \<in> liftState r m s"
+ obtains t where "Run m t a"
+ by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>;
+ simp add: failS_def throwS_def returnS_def del: read_regvalS.simps;
+ blast elim: Value_bindS_elim)
+
+lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra]
+
+lemma Value_bindS_iff:
+ "(Value b, s'') \<in> bindS m f s \<longleftrightarrow> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Value b, s'') \<in> f a s')"
+ by (auto elim!: bindS_cases intro: bindS_intros)
+
+lemma Ex_bindS_iff:
+ "(Ex e, s'') \<in> bindS m f s \<longleftrightarrow> (Ex e, s'') \<in> m s \<or> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Ex e, s'') \<in> f a s')"
+ by (auto elim!: bindS_cases intro: bindS_intros)
+
+lemma liftState_throw[liftState_simp]: "liftState r (throw e) = throwS e"
+ by (auto simp: throw_def)
+lemma liftState_assert[liftState_simp]: "liftState r (assert_exp c msg) = assert_expS c msg"
+ by (auto simp: assert_exp_def assert_expS_def)
+lemma liftState_exit[liftState_simp]: "liftState r (exit0 ()) = exitS ()"
+ by (auto simp: exit0_def exitS_def)
+lemma liftState_exclResult[liftState_simp]: "liftState r (excl_result ()) = excl_resultS ()"
+ by (auto simp: excl_result_def liftState_simp)
+lemma liftState_barrier[liftState_simp]: "liftState r (barrier bk) = returnS ()"
+ by (auto simp: barrier_def)
+lemma liftState_footprint[liftState_simp]: "liftState r (footprint ()) = returnS ()"
+ by (auto simp: footprint_def)
+lemma liftState_choose_bool[liftState_simp]: "liftState r (choose_bool descr) = choose_boolS ()"
+ by (auto simp: choose_bool_def liftState_simp)
+declare undefined_boolS_def[simp]
+lemma liftState_undefined[liftState_simp]: "liftState r (undefined_bool ()) = undefined_boolS ()"
+ by (auto simp: undefined_bool_def liftState_simp)
+lemma liftState_maybe_fail[liftState_simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x"
+ by (auto simp: maybe_fail_def maybe_failS_def liftState_simp split: option.splits)
+lemma liftState_and_boolM[liftState_simp]:
+ "liftState r (and_boolM x y) = and_boolS (liftState r x) (liftState r y)"
+ by (auto simp: and_boolM_def and_boolS_def liftState_simp cong: bindS_cong if_cong)
+lemma liftState_or_boolM[liftState_simp]:
+ "liftState r (or_boolM x y) = or_boolS (liftState r x) (liftState r y)"
+ by (auto simp: or_boolM_def or_boolS_def liftState_simp cong: bindS_cong if_cong)
+
+lemma liftState_try_catch[liftState_simp]:
+ "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)"
+ by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw)
+
+lemma liftState_early_return[liftState_simp]:
+ "liftState r (early_return x) = early_returnS x"
+ by (auto simp: early_return_def early_returnS_def liftState_simp)
+
+lemma liftState_catch_early_return[liftState_simp]:
+ "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)"
+ by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib liftState_simp cong: sum.case_cong)
+
+lemma liftState_liftR[liftState_simp]:
+ "liftState r (liftR m) = liftRS (liftState r m)"
+ by (auto simp: liftR_def liftRS_def liftState_simp)
+
+lemma liftState_try_catchR[liftState_simp]:
+ "liftState r (try_catchR m h) = try_catchRS (liftState r m) (liftState r \<circ> h)"
+ by (auto simp: try_catchR_def try_catchRS_def sum.case_distrib liftState_simp cong: sum.case_cong)
+
+lemma liftState_bool_of_bitU_nondet[liftState_simp]:
+ "liftState r (bool_of_bitU_nondet b) = bool_of_bitU_nondetS b"
+ by (cases b; auto simp: bool_of_bitU_nondet_def bool_of_bitU_nondetS_def liftState_simp)
+
+lemma liftState_read_memt[liftState_simp]:
+ shows "liftState r (read_memt BCa BCb rk a sz) = read_memtS BCa BCb rk a sz"
+ by (auto simp: read_memt_def read_memt_bytes_def maybe_failS_def read_memtS_def
+ prod.case_distrib option.case_distrib[where h = "liftState r"]
+ option.case_distrib[where h = "\<lambda>c. c \<bind>\<^sub>S f" for f] liftState_simp
+ split: option.splits intro: bindS_cong)
+
+lemma liftState_read_mem[liftState_simp]:
+ shows "liftState r (read_mem BCa BCb rk asz a sz) = read_memS BCa BCb rk asz a sz"
+ by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def
+ read_memtS_def
+ prod.case_distrib option.case_distrib[where h = "liftState r"]
+ option.case_distrib[where h = "\<lambda>c. c \<bind>\<^sub>S f" for f] liftState_simp
+ split: option.splits intro: bindS_cong)
+
+lemma liftState_write_mem_ea_BC:
+ assumes "unsigned_method BCa a = Some a'"
+ shows "liftState r (write_mem_ea BCa rk asz a sz) = returnS ()"
+ using assms by (auto simp: write_mem_ea_def nat_of_bv_def maybe_fail_def)
+
+(*lemma liftState_write_mem_ea[liftState_simp]:
+ "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = returnS ()"
+ "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = returnS ()"
+ by (auto simp: liftState_write_mem_ea_BC)*)
+
+(*lemma write_mem_bytesS_def_BC_bitU_list_BC_mword[simp]:
+ "write_mem_bytesS BC_bitU_list wk (bits_of_method BC_mword addr) sz v t =
+ write_mem_bytesS BC_mword wk addr sz v t"
+ by (auto simp: write_mem_bytesS_def)*)
+
+lemma liftState_write_memt[liftState_simp]:
+ "liftState r (write_memt BCa BCv wk addr sz v t) = write_memtS BCa BCv wk addr sz v t"
+ by (auto simp: write_memt_def write_memtS_def liftState_simp split: option.splits)
+
+lemma liftState_write_mem[liftState_simp]:
+ "liftState r (write_mem BCa BCv wk addrsize addr sz v) = write_memS BCa BCv wk addrsize addr sz v"
+ by (auto simp: write_mem_def write_memS_def write_memtS_def write_mem_bytesS_def liftState_simp
+ split: option.splits)
+
+lemma liftState_read_reg_readS:
+ assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)"
+ shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)"
+proof
+ fix s :: "'a sequential_state"
+ obtain rv v where "get_regval' (name reg) (regstate s) = Some rv"
+ and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v"
+ using assms unfolding bind_eq_Some_conv by blast
+ then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s"
+ by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def)
+qed
+
+lemma liftState_write_reg_updateS:
+ assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)"
+ shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))"
+ using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS)
+
+lemma liftState_iter_aux[liftState_simp]:
+ shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs"
+ by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct)
+ (auto simp: liftState_simp cong: bindS_cong)
+
+lemma liftState_iteri[liftState_simp]:
+ "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs"
+ by (auto simp: iteri_def iteriS_def liftState_simp)
+
+lemma liftState_iter[liftState_simp]:
+ "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs"
+ by (auto simp: iter_def iterS_def liftState_simp)
+
+lemma liftState_foreachM[liftState_simp]:
+ "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))"
+ by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct)
+ (auto simp: liftState_simp cong: bindS_cong)
+
+lemma liftState_genlistM[liftState_simp]:
+ "liftState r (genlistM f n) = genlistS (liftState r \<circ> f) n"
+ by (auto simp: genlistM_def genlistS_def liftState_simp cong: bindS_cong)
+
+lemma liftState_choose_bools[liftState_simp]:
+ "liftState r (choose_bools descr n) = choose_boolsS n"
+ by (auto simp: choose_bools_def choose_boolsS_def liftState_simp comp_def)
+
+lemma liftState_bools_of_bits_nondet[liftState_simp]:
+ "liftState r (bools_of_bits_nondet bs) = bools_of_bits_nondetS bs"
+ unfolding bools_of_bits_nondet_def bools_of_bits_nondetS_def
+ by (auto simp: liftState_simp comp_def)
+
+lemma liftState_internal_pick[liftState_simp]:
+ "liftState r (internal_pick xs) = internal_pickS xs"
+ by (auto simp: internal_pick_def internal_pickS_def liftState_simp comp_def
+ chooseM_def
+ option.case_distrib[where h = "liftState r"]
+ simp del: repeat.simps
+ cong: option.case_cong)
+
+lemma liftRS_returnS[simp]: "liftRS (returnS x) = returnS x"
+ by (auto simp: liftRS_def)
+
+lemma liftRS_bindS:
+ fixes m :: "('regs, 'a, 'e) monadS" and f :: "'a \<Rightarrow> ('regs, 'b, 'e) monadS"
+ shows "(liftRS (bindS m f) :: ('regs, 'b, 'r, 'e) monadRS) = bindS (liftRS m) (liftRS \<circ> f)"
+proof (intro ext set_eqI iffI)
+ fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+ assume lhs: "rs' \<in> liftRS (bindS m f) s"
+ then show "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+ by (cases rs')
+ (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+ intro: bindS_intros try_catchS_intros)
+next
+ fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state"
+ assume "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s"
+ then show "rs' \<in> liftRS (bindS m f) s"
+ by (cases rs')
+ (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases
+ intro: bindS_intros try_catchS_intros)
+qed
+
+lemma liftRS_assert_expS_True[simp]: "liftRS (assert_expS True msg) = returnS ()"
+ by (auto simp: liftRS_def assert_expS_def)
+
+lemma untilM_domI:
+ fixes V :: "'vars \<Rightarrow> nat"
+ assumes "Inv vars"
+ and "\<And>vars t vars' t'. \<lbrakk>Inv vars; Run (body vars) t vars'; Run (cond vars') t' False\<rbrakk> \<Longrightarrow> V vars' < V vars \<and> Inv vars'"
+ shows "untilM_dom (vars, cond, body)"
+ using assms
+ by (induction vars rule: measure_induct_rule[where f = V])
+ (auto intro: untilM.domintros)
+
+lemma untilM_dom_untilS_dom:
+ assumes "untilM_dom (vars, cond, body)"
+ shows "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ using assms
+ by (induction vars cond body arbitrary: s rule: untilM.pinduct)
+ (rule untilS.domintros, auto elim!: Value_liftState_Run)
+
+lemma measure2_induct:
+ fixes f :: "'a \<Rightarrow> 'b \<Rightarrow> nat"
+ assumes "\<And>x1 y1. (\<And>x2 y2. f x2 y2 < f x1 y1 \<Longrightarrow> P x2 y2) \<Longrightarrow> P x1 y1"
+ shows "P x y"
+proof -
+ have "P (fst x) (snd x)" for x
+ by (induction x rule: measure_induct_rule[where f = "\<lambda>x. f (fst x) (snd x)"]) (auto intro: assms)
+ then show ?thesis by auto
+qed
+
+lemma untilS_domI:
+ fixes V :: "'vars \<Rightarrow> 'regs sequential_state \<Rightarrow> nat"
+ assumes "Inv vars s"
+ and "\<And>vars s vars' s' s''.
+ \<lbrakk>Inv vars s; (Value vars', s') \<in> body vars s; (Value False, s'') \<in> cond vars' s'\<rbrakk>
+ \<Longrightarrow> V vars' s'' < V vars s \<and> Inv vars' s''"
+ shows "untilS_dom (vars, cond, body, s)"
+ using assms
+ by (induction vars s rule: measure2_induct[where f = V])
+ (auto intro: untilS.domintros)
+
+lemma whileS_dom_step:
+ assumes "whileS_dom (vars, cond, body, s)"
+ and "(Value True, s') \<in> cond vars s"
+ and "(Value vars', s'') \<in> body vars s'"
+ shows "whileS_dom (vars', cond, body, s'')"
+ by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>)
+ (auto intro: whileS.domintros)
+
+lemma whileM_dom_step:
+ assumes "whileM_dom (vars, cond, body)"
+ and "Run (cond vars) t True"
+ and "Run (body vars) t' vars'"
+ shows "whileM_dom (vars', cond, body)"
+ by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>)
+ (auto intro: whileM.domintros)
+
+lemma whileM_dom_ex_step:
+ assumes "whileM_dom (vars, cond, body)"
+ and "\<exists>t. Run (cond vars) t True"
+ and "\<exists>t'. Run (body vars) t' vars'"
+ shows "whileM_dom (vars', cond, body)"
+ using assms by (blast intro: whileM_dom_step)
+
+lemmas whileS_pinduct = whileS.pinduct[case_names Step]
+
+lemma liftState_whileM:
+ assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ and "whileM_dom (vars, cond, body)"
+ shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>)
+ case Step: (1 vars s)
+ note domS = Step(1) and IH = Step(2) and domM = Step(3)
+ show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind
+ proof (intro bindS_ext_cong, goal_cases cond while)
+ case (while a s')
+ have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' =
+ bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'"
+ if "a"
+ proof (intro bindS_ext_cong, goal_cases body while')
+ case (while' vars' s'')
+ have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM])
+ show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run)
+ show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run)
+ qed
+ then show ?case using while while' that IH by auto
+ qed auto
+ then show ?case by (auto simp: liftState_simp)
+ qed auto
+qed
+
+
+lemma untilM_dom_step:
+ assumes "untilM_dom (vars, cond, body)"
+ and "Run (body vars) t vars'"
+ and "Run (cond vars') t' False"
+ shows "untilM_dom (vars', cond, body)"
+ by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>)
+ (auto intro: untilM.domintros)
+
+lemma untilM_dom_ex_step:
+ assumes "untilM_dom (vars, cond, body)"
+ and "\<exists>t. Run (body vars) t vars'"
+ and "\<exists>t'. Run (cond vars') t' False"
+ shows "untilM_dom (vars', cond, body)"
+ using assms by (blast intro: untilM_dom_step)
+
+lemma liftState_untilM:
+ assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)"
+ and "untilM_dom (vars, cond, body)"
+ shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s"
+proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>)
+ case Step: (1 vars s)
+ note domS = Step(1) and IH = Step(2) and domM = Step(3)
+ show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind
+ proof (intro bindS_ext_cong, goal_cases body k)
+ case (k vars' s')
+ show ?case unfolding comp_def liftState_bind
+ proof (intro bindS_ext_cong, goal_cases cond until)
+ case (until a s'')
+ have "untilM_dom (vars', cond, body)" if "\<not>a"
+ proof (rule untilM_dom_ex_step[OF domM])
+ show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run)
+ show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run)
+ qed
+ then show ?case using k until IH by (auto simp: comp_def liftState_simp)
+ qed auto
+ qed auto
+qed
+
+text \<open>Simplification rules for monadic Boolean connectives\<close>
+
+lemma if_return_return[simp]: "(if a then return True else return False) = return a" by auto
+
+lemma and_boolM_simps[simp]:
+ "and_boolM (return b) (return c) = return (b \<and> c)"
+ "and_boolM x (return True) = x"
+ "and_boolM x (return False) = x \<bind> (\<lambda>_. return False)"
+ "\<And>x y z. and_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. and_boolM (y r) z))"
+ by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_if:
+ "and_boolM (return b) y = (if b then y else return False)"
+ by (auto simp: and_boolM_def)
+
+lemma and_boolM_return_return_and[simp]: "and_boolM (return l) (return r) = return (l \<and> r)"
+ by (auto simp: and_boolM_def)
+
+lemmas and_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolM x y" for y]
+
+lemma or_boolM_simps[simp]:
+ "or_boolM (return b) (return c) = return (b \<or> c)"
+ "or_boolM x (return True) = x \<bind> (\<lambda>_. return True)"
+ "or_boolM x (return False) = x"
+ "\<And>x y z. or_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. or_boolM (y r) z))"
+ by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_if:
+ "or_boolM (return b) y = (if b then return True else y)"
+ by (auto simp: or_boolM_def)
+
+lemma or_boolM_return_return_or[simp]: "or_boolM (return l) (return r) = return (l \<or> r)"
+ by (auto simp: or_boolM_def)
+
+lemmas or_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolM x y" for y]
+
+lemma if_returnS_returnS[simp]: "(if a then returnS True else returnS False) = returnS a" by auto
+
+lemma and_boolS_simps[simp]:
+ "and_boolS (returnS b) (returnS c) = returnS (b \<and> c)"
+ "and_boolS x (returnS True) = x"
+ "and_boolS x (returnS False) = bindS x (\<lambda>_. returnS False)"
+ "\<And>x y z. and_boolS (bindS x y) z = (bindS x (\<lambda>r. and_boolS (y r) z))"
+ by (auto simp: and_boolS_def)
+
+lemma and_boolS_returnS_if:
+ "and_boolS (returnS b) y = (if b then y else returnS False)"
+ by (auto simp: and_boolS_def)
+
+lemmas and_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolS x y" for y]
+
+lemma and_boolS_returnS_True[simp]: "and_boolS (returnS True) c = c"
+ by (auto simp: and_boolS_def)
+
+lemma or_boolS_simps[simp]:
+ "or_boolS (returnS b) (returnS c) = returnS (b \<or> c)"
+ "or_boolS (returnS False) m = m"
+ "or_boolS x (returnS True) = bindS x (\<lambda>_. returnS True)"
+ "or_boolS x (returnS False) = x"
+ "\<And>x y z. or_boolS (bindS x y) z = (bindS x (\<lambda>r. or_boolS (y r) z))"
+ by (auto simp: or_boolS_def)
+
+lemma or_boolS_returnS_if:
+ "or_boolS (returnS b) y = (if b then returnS True else y)"
+ by (auto simp: or_boolS_def)
+
+lemmas or_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolS x y" for y]
+
+lemma Run_or_boolM_E:
+ assumes "Run (or_boolM l r) t a"
+ obtains "Run l t True" and "a"
+ | tl tr where "Run l tl False" and "Run r tr a" and "t = tl @ tr"
+ using assms by (auto simp: or_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma Run_and_boolM_E:
+ assumes "Run (and_boolM l r) t a"
+ obtains "Run l t False" and "\<not>a"
+ | tl tr where "Run l tl True" and "Run r tr a" and "t = tl @ tr"
+ using assms by (auto simp: and_boolM_def elim!: Run_bindE Run_ifE Run_returnE)
+
+lemma maybe_failS_Some[simp]: "maybe_failS msg (Some v) = returnS v"
+ by (auto simp: maybe_failS_def)
+
+text \<open>Event traces\<close>
+
+lemma Some_eq_bind_conv: "Some x = Option.bind f g \<longleftrightarrow> (\<exists>y. f = Some y \<and> g y = Some x)"
+ unfolding bind_eq_Some_conv[symmetric] by auto
+
+lemma if_then_Some_eq_Some_iff: "((if b then Some x else None) = Some y) \<longleftrightarrow> (b \<and> y = x)"
+ by auto
+
+lemma Some_eq_if_then_Some_iff: "(Some y = (if b then Some x else None)) \<longleftrightarrow> (b \<and> y = x)"
+ by auto
+
+lemma emitEventS_update_cases:
+ assumes "emitEventS ra e s = Some s'"
+ obtains
+ (Write_mem) wk addr sz v tag r
+ where "e = E_write_memt wk addr sz v tag r \<or> (e = E_write_mem wk addr sz v r \<and> tag = B0)"
+ and "s' = put_mem_bytes addr sz v tag s"
+ | (Write_reg) r v rs'
+ where "e = E_write_reg r v" and "(snd ra) r v (regstate s) = Some rs'"
+ and "s' = s\<lparr>regstate := rs'\<rparr>"
+ | (Read) "s' = s"
+ using assms
+ by (elim emitEventS.elims)
+ (auto simp: Some_eq_bind_conv bind_eq_Some_conv if_then_Some_eq_Some_iff Some_eq_if_then_Some_iff)
+
+lemma runTraceS_singleton[simp]: "runTraceS ra [e] s = emitEventS ra e s"
+ by (cases "emitEventS ra e s"; auto)
+
+lemma runTraceS_ConsE:
+ assumes "runTraceS ra (e # t) s = Some s'"
+ obtains s'' where "emitEventS ra e s = Some s''" and "runTraceS ra t s'' = Some s'"
+ using assms by (auto simp: bind_eq_Some_conv)
+
+lemma runTraceS_ConsI:
+ assumes "emitEventS ra e s = Some s'" and "runTraceS ra t s' = Some s''"
+ shows "runTraceS ra (e # t) s = Some s''"
+ using assms by auto
+
+lemma runTraceS_Cons_tl:
+ assumes "emitEventS ra e s = Some s'"
+ shows "runTraceS ra (e # t) s = runTraceS ra t s'"
+ using assms by (elim emitEventS.elims) (auto simp: Some_eq_bind_conv bind_eq_Some_conv)
+
+lemma runTraceS_appendE:
+ assumes "runTraceS ra (t @ t') s = Some s'"
+ obtains s'' where "runTraceS ra t s = Some s''" and "runTraceS ra t' s'' = Some s'"
+proof -
+ have "\<exists>s''. runTraceS ra t s = Some s'' \<and> runTraceS ra t' s'' = Some s'"
+ proof (use assms in \<open>induction t arbitrary: s\<close>)
+ case (Cons e t)
+ from Cons.prems
+ obtain s_e where "emitEventS ra e s = Some s_e" and "runTraceS ra (t @ t') s_e = Some s'"
+ by (auto elim: runTraceS_ConsE simp: bind_eq_Some_conv)
+ with Cons.IH[of s_e] show ?case by (auto intro: runTraceS_ConsI)
+ qed auto
+ then show ?thesis using that by blast
+qed
+
+lemma runTraceS_nth_split:
+ assumes "runTraceS ra t s = Some s'" and n: "n < length t"
+ obtains s1 s2 where "runTraceS ra (take n t) s = Some s1"
+ and "emitEventS ra (t ! n) s1 = Some s2"
+ and "runTraceS ra (drop (Suc n) t) s2 = Some s'"
+proof -
+ have "runTraceS ra (take n t @ t ! n # drop (Suc n) t) s = Some s'"
+ using assms
+ by (auto simp: id_take_nth_drop[OF n, symmetric])
+ then show thesis by (blast elim: runTraceS_appendE runTraceS_ConsE intro: that)
+qed
+
+text \<open>Memory accesses\<close>
+
+lemma get_mem_bytes_put_mem_bytes_same_addr:
+ assumes "length v = sz"
+ shows "get_mem_bytes addr sz (put_mem_bytes addr sz v tag s) = Some (v, if sz > 0 then tag else B1)"
+proof (unfold assms[symmetric], induction v rule: rev_induct)
+ case Nil
+ then show ?case by (auto simp: get_mem_bytes_def)
+next
+ case (snoc x xs)
+ then show ?case
+ by (cases tag)
+ (auto simp: get_mem_bytes_def put_mem_bytes_def Let_def and_bit_eq_iff foldl_and_bit_eq_iff
+ cong: option.case_cong split: if_splits option.splits)
+qed
+
+lemma memstate_put_mem_bytes:
+ assumes "length v = sz"
+ shows "memstate (put_mem_bytes addr sz v tag s) addr' =
+ (if addr' \<in> {addr..<addr+sz} then Some (v ! (addr' - addr)) else memstate s addr')"
+ unfolding assms[symmetric]
+ by (induction v rule: rev_induct) (auto simp: put_mem_bytes_def nth_Cons nth_append Let_def)
+
+lemma tagstate_put_mem_bytes:
+ assumes "length v = sz"
+ shows "tagstate (put_mem_bytes addr sz v tag s) addr' =
+ (if addr' \<in> {addr..<addr+sz} then Some tag else tagstate s addr')"
+ unfolding assms[symmetric]
+ by (induction v rule: rev_induct) (auto simp: put_mem_bytes_def nth_Cons nth_append Let_def)
+
+lemma get_mem_bytes_cong:
+ assumes "\<forall>addr'. addr \<le> addr' \<and> addr' < addr + sz \<longrightarrow>
+ (memstate s' addr' = memstate s addr' \<and> tagstate s' addr' = tagstate s addr')"
+ shows "get_mem_bytes addr sz s' = get_mem_bytes addr sz s"
+proof (use assms in \<open>induction sz\<close>)
+ case 0
+ then show ?case by (auto simp: get_mem_bytes_def)
+next
+ case (Suc sz)
+ then show ?case
+ by (auto simp: get_mem_bytes_def Let_def
+ intro!: map_option_cong map_cong foldl_cong
+ arg_cong[where f = just_list] arg_cong2[where f = and_bit])
+qed
+
+lemma get_mem_bytes_tagged_tagstate:
+ assumes "get_mem_bytes addr sz s = Some (v, B1)"
+ shows "\<forall>addr' \<in> {addr..<addr + sz}. tagstate s addr' = Some B1"
+ using assms
+ by (auto simp: get_mem_bytes_def foldl_and_bit_eq_iff Let_def split: option.splits)
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_state_lifting.thy b/prover_snapshots/isabelle/lib/sail/Sail2_state_lifting.thy
new file mode 100644
index 0000000..3859c3b
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_state_lifting.thy
@@ -0,0 +1,75 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_state_lifting.lem\<close>.\<close>
+
+theory "Sail2_state_lifting"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail2_values"
+ "Sail2_prompt_monad"
+ "Sail2_prompt"
+ "Sail2_state_monad"
+ "Sail2_state_monad_lemmas"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt_monad\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_prompt\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_state_monad\<close>\<close>
+\<comment> \<open>\<open>open import {isabelle} `Sail2_state_monad_lemmas`\<close>\<close>
+
+\<comment> \<open>\<open> Lifting from prompt monad to state monad \<close>\<close>
+\<comment> \<open>\<open>val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e\<close>\<close>
+function (sequential,domintros) liftState :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " liftState ra (Done a) = ( returnS a )"
+|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS rk a sz) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Read_memt rk a sz k) = ( bindS (read_memt_bytesS rk a sz) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Write_mem wk a sz v k) = ( bindS (write_mem_bytesS wk a sz v) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Write_memt wk a sz v t k) = ( bindS (write_memt_bytesS wk a sz v t) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Excl_res k) = ( bindS (excl_resultS () ) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Choose _ k) = ( bindS (choose_boolS () ) (\<lambda> v . liftState ra (k v)))"
+|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v) (liftState ra k))"
+|" liftState ra (Write_ea _ _ _ k) = ( liftState ra k )"
+|" liftState ra (Footprint k) = ( liftState ra k )"
+|" liftState ra (Barrier _ k) = ( liftState ra k )"
+|" liftState ra (Print _ k) = ( liftState ra k )"
+|" liftState ra (Fail descr) = ( failS descr )"
+|" liftState ra (Exception e) = ( throwS e )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val emitEventS : forall 'regval 'regs 'a 'e. Eq 'regval => register_accessors 'regs 'regval -> event 'regval -> sequential_state 'regs -> maybe (sequential_state 'regs)\<close>\<close>
+fun emitEventS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> 'regval event \<Rightarrow> 'regs sequential_state \<Rightarrow>('regs sequential_state)option " where
+ " emitEventS ra (E_read_mem _ addr sz v) s = (
+ Option.bind (get_mem_bytes addr sz s) ( \<lambda>x .
+ (case x of (v', _) => if v' = v then Some s else None )))"
+|" emitEventS ra (E_read_memt _ addr sz (v, tag)) s = (
+ Option.bind (get_mem_bytes addr sz s) ( \<lambda>x .
+ (case x of
+ (v', tag') =>
+ if (v' = v) \<and> (tag' = tag) then Some s else None
+ )))"
+|" emitEventS ra (E_write_mem _ addr sz v success) s = (
+ if success then Some (put_mem_bytes addr sz v B0 s) else None )"
+|" emitEventS ra (E_write_memt _ addr sz v tag success) s = (
+ if success then Some (put_mem_bytes addr sz v tag s) else None )"
+|" emitEventS ra (E_read_reg r v) s = (
+ (let (read_reg1, _) = ra in
+ Option.bind (read_reg1 r(regstate s)) (\<lambda> v' .
+ if v' = v then Some s else None)))"
+|" emitEventS ra (E_write_reg r v) s = (
+ (let (_, write_reg1) = ra in
+ Option.bind (write_reg1 r v(regstate s)) (\<lambda> rs' .
+ Some ( s (| regstate := rs' |)))))"
+|" emitEventS ra _ s = ( Some s )"
+
+
+\<comment> \<open>\<open>val runTraceS : forall 'regval 'regs 'a 'e. Eq 'regval => register_accessors 'regs 'regval -> trace 'regval -> sequential_state 'regs -> maybe (sequential_state 'regs)\<close>\<close>
+fun runTraceS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval event)list \<Rightarrow> 'regs sequential_state \<Rightarrow>('regs sequential_state)option " where
+ " runTraceS ra ([]) s = ( Some s )"
+|" runTraceS ra (e # t') s = ( Option.bind (emitEventS ra e s) (runTraceS ra t'))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_state_monad.thy b/prover_snapshots/isabelle/lib/sail/Sail2_state_monad.thy
new file mode 100644
index 0000000..9961706
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_state_monad.thy
@@ -0,0 +1,377 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_state_monad.lem\<close>.\<close>
+
+theory "Sail2_state_monad"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "Sail2_instr_kinds"
+ "Sail2_values"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_instr_kinds\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+
+\<comment> \<open>\<open> 'a is result type \<close>\<close>
+
+type_synonym memstate =" (nat, memory_byte) Map.map "
+type_synonym tagstate =" (nat, bitU) Map.map "
+\<comment> \<open>\<open> type regstate = map string (vector bitU) \<close>\<close>
+
+record 'regs sequential_state =
+
+ regstate ::" 'regs "
+
+ memstate ::" memstate "
+
+ tagstate ::" tagstate "
+
+
+\<comment> \<open>\<open>val init_state : forall 'regs. 'regs -> sequential_state 'regs\<close>\<close>
+definition init_state :: " 'regs \<Rightarrow> 'regs sequential_state " where
+ " init_state regs = (
+ (| regstate = regs,
+ memstate = Map.empty,
+ tagstate = Map.empty |) )"
+
+
+datatype 'e ex =
+ Failure " string "
+ | Throw " 'e "
+
+datatype( 'a, 'e) result =
+ Value " 'a "
+ | Ex " ( 'e ex)"
+
+\<comment> \<open>\<open> State, nondeterminism and exception monad with result value type 'a
+ and exception type 'e. \<close>\<close>
+type_synonym( 'regs, 'a, 'e) monadS =" 'regs sequential_state \<Rightarrow> ( ('a, 'e)result * 'regs sequential_state) set "
+
+\<comment> \<open>\<open>val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e\<close>\<close>
+definition returnS :: " 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " returnS a s = ( {(Value a,s)})"
+
+
+\<comment> \<open>\<open>val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e\<close>\<close>
+definition bindS :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow>('a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set " where
+ " bindS m f (s :: 'regs sequential_state) = (
+ \<Union> (Set.image (\<lambda>x .
+ (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s)))"
+
+
+\<comment> \<open>\<open>val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e\<close>\<close>
+definition seqS :: "('regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set)\<Rightarrow>('regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set " where
+ " seqS m n = ( bindS m ( \<lambda>x .
+ (case x of (_ :: unit) => n )))"
+
+
+\<comment> \<open>\<open>val chooseS : forall 'regs 'a 'e. SetType 'a => list 'a -> monadS 'regs 'a 'e\<close>\<close>
+definition chooseS :: " 'a list \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " chooseS xs s = ( List.set (List.map (\<lambda> x . (Value x, s)) xs))"
+
+
+\<comment> \<open>\<open>val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e\<close>\<close>
+definition readS :: "('regs sequential_state \<Rightarrow> 'a)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " readS f = ( (\<lambda> s . returnS (f s) s))"
+
+
+\<comment> \<open>\<open>val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e\<close>\<close>
+definition updateS :: "('regs sequential_state \<Rightarrow> 'regs sequential_state)\<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where
+ " updateS f = ( (\<lambda> s . returnS () (f s)))"
+
+
+\<comment> \<open>\<open>val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e\<close>\<close>
+definition failS :: " string \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " failS msg s = ( {(Ex (Failure msg), s)})"
+
+
+\<comment> \<open>\<open>val choose_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e\<close>\<close>
+definition choose_boolS :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where
+ " choose_boolS _ = ( chooseS [False, True])"
+
+definition undefined_boolS :: " unit \<Rightarrow>('c,(bool),'a)monadS " where
+ " undefined_boolS = ( choose_boolS )"
+
+
+\<comment> \<open>\<open>val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e\<close>\<close>
+definition exitS :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " exitS _ = ( failS (''exit''))"
+
+
+\<comment> \<open>\<open>val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e\<close>\<close>
+definition throwS :: " 'e \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " throwS e s = ( {(Ex (Throw e), s)})"
+
+
+\<comment> \<open>\<open>val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2\<close>\<close>
+definition try_catchS :: "('regs sequential_state \<Rightarrow>(('a,'e1)result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set " where
+ " try_catchS m h s = (
+ \<Union> (Set.image (\<lambda>x .
+ (case x of
+ (Value a, s') => returnS a s'
+ | (Ex (Throw e), s') => h e s'
+ | (Ex (Failure msg), s') => {(Ex (Failure msg), s')}
+ )) (m s)))"
+
+
+\<comment> \<open>\<open>val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e\<close>\<close>
+definition assert_expS :: " bool \<Rightarrow> string \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where
+ " assert_expS exp1 msg = ( if exp1 then returnS () else failS msg )"
+
+
+\<comment> \<open>\<open> For early return, we abuse exceptions by throwing and catching
+ the return value. The exception type is "either 'r 'e", where "Right e"
+ represents a proper exception and "Left r" an early return of value "r". \<close>\<close>
+type_synonym( 'regs, 'a, 'r, 'e) monadRS =" ('regs, 'a, ( ('r, 'e)sum)) monadS "
+
+\<comment> \<open>\<open>val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e\<close>\<close>
+definition early_returnS :: " 'r \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where
+ " early_returnS r = ( throwS (Inl r))"
+
+
+\<comment> \<open>\<open>val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e\<close>\<close>
+definition catch_early_returnS :: "('regs sequential_state \<Rightarrow>(('a,(('a,'e)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " catch_early_returnS m = (
+ try_catchS m
+ (\<lambda>x . (case x of Inl a => returnS a | Inr e => throwS e )))"
+
+
+\<comment> \<open>\<open> Lift to monad with early return by wrapping exceptions \<close>\<close>
+\<comment> \<open>\<open>val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e\<close>\<close>
+definition liftRS :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where
+ " liftRS m = ( try_catchS m (\<lambda> e . throwS (Inr e)))"
+
+
+\<comment> \<open>\<open> Catch exceptions in the presence of early returns \<close>\<close>
+\<comment> \<open>\<open>val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2\<close>\<close>
+definition try_catchRS :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set " where
+ " try_catchRS m h = (
+ try_catchS m
+ (\<lambda>x . (case x of Inl r => throwS (Inl r) | Inr e => h e )))"
+
+
+\<comment> \<open>\<open>val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e\<close>\<close>
+definition maybe_failS :: " string \<Rightarrow> 'a option \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " maybe_failS msg = ( \<lambda>x .
+ (case x of Some a => returnS a | None => failS msg ) )"
+
+
+\<comment> \<open>\<open>val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e\<close>\<close>
+definition read_tagS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regs,(bitU),'e)monadS " where
+ " read_tagS dict_Sail2_values_Bitvector_a addr = ( bindS
+ (maybe_failS (''nat_of_bv'') (nat_of_bv
+ dict_Sail2_values_Bitvector_a addr)) (\<lambda> addr .
+ readS (\<lambda> s . case_option B0 id ((tagstate s) addr))))"
+
+
+\<comment> \<open>\<open> Read bytes from memory and return in little endian order \<close>\<close>
+\<comment> \<open>\<open>val get_mem_bytes : forall 'regs. nat -> nat -> sequential_state 'regs -> maybe (list memory_byte * bitU)\<close>\<close>
+definition get_mem_bytes :: " nat \<Rightarrow> nat \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bitU)list)list*bitU)option " where
+ " get_mem_bytes addr sz s = (
+ (let addrs = (genlist (\<lambda> n . addr + n) sz) in
+ (let read_byte = (\<lambda> s addr . (memstate s) addr) in
+ (let read_tag = (\<lambda> s addr . case_option B0 id
+ ( (tagstate s) addr)) in
+ map_option
+ (\<lambda> mem_val . (mem_val, List.foldl and_bit B1
+ (List.map (read_tag s) addrs)))
+ (just_list (List.map (read_byte s) addrs))))))"
+
+
+\<comment> \<open>\<open>val read_memt_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte * bitU) 'e\<close>\<close>
+definition read_memt_bytesS :: " read_kind \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow>('regs,((memory_byte)list*bitU),'e)monadS " where
+ " read_memt_bytesS _ addr sz = ( bindS
+ (readS (get_mem_bytes addr sz))
+ (maybe_failS (''read_memS'')))"
+
+
+\<comment> \<open>\<open>val read_mem_bytesS : forall 'regs 'e. read_kind -> nat -> nat -> monadS 'regs (list memory_byte) 'e\<close>\<close>
+definition read_mem_bytesS :: " read_kind \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow>('regs,((memory_byte)list),'e)monadS " where
+ " read_mem_bytesS rk addr sz = ( bindS
+ (read_memt_bytesS rk addr sz) ( \<lambda>x .
+ (case x of (bytes, _) => returnS bytes )))"
+
+
+\<comment> \<open>\<open>val read_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs ('b * bitU) 'e\<close>\<close>
+definition read_memtS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,('b*bitU),'e)monadS " where
+ " read_memtS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz = ( bindS
+ (maybe_failS (''nat_of_bv'') (nat_of_bv
+ dict_Sail2_values_Bitvector_a a)) (\<lambda> a . bindS
+ (read_memt_bytesS rk a (nat_of_int sz)) ( \<lambda>x .
+ (case x of
+ (bytes, tag) => bindS
+ (maybe_failS (''bits_of_mem_bytes'')
+ ((of_bits_method dict_Sail2_values_Bitvector_b)
+ (bits_of_mem_bytes bytes)))
+ (\<lambda> mem_val . returnS (mem_val, tag))
+ ))))"
+
+
+\<comment> \<open>\<open>val read_memS : forall 'regs 'e 'a 'b 'addrsize. Bitvector 'a, Bitvector 'b => read_kind -> 'addrsize -> 'a -> integer -> monadS 'regs 'b 'e\<close>\<close>
+definition read_memS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'addrsize \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,'b,'e)monadS " where
+ " read_memS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr_size a sz = ( bindS
+ (read_memtS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz) ( \<lambda>x .
+ (case x of (bytes, _) => returnS bytes )))"
+
+
+\<comment> \<open>\<open>val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e\<close>\<close>
+definition excl_resultS :: " unit \<Rightarrow>('regs,(bool),'e)monadS " where
+ " excl_resultS = (
+ \<comment> \<open>\<open> TODO: This used to be more deterministic, checking a flag in the state
+ whether an exclusive load has occurred before. However, this does not
+ seem very precise; it might be safer to overapproximate the possible
+ behaviours by always making a nondeterministic choice. \<close>\<close>
+ undefined_boolS )"
+
+
+\<comment> \<open>\<open> Write little-endian list of bytes to given address \<close>\<close>
+\<comment> \<open>\<open>val put_mem_bytes : forall 'regs. nat -> nat -> list memory_byte -> bitU -> sequential_state 'regs -> sequential_state 'regs\<close>\<close>
+definition put_mem_bytes :: " nat \<Rightarrow> nat \<Rightarrow>((bitU)list)list \<Rightarrow> bitU \<Rightarrow> 'regs sequential_state \<Rightarrow> 'regs sequential_state " where
+ " put_mem_bytes addr sz v tag s = (
+ (let addrs = (genlist (\<lambda> n . addr + n) sz) in
+ (let a_v = (List.zip addrs v) in
+ (let write_byte = (\<lambda>mem p . (case (mem ,p ) of
+ ( mem , (addr, v) ) => map_update
+ addr
+ v mem
+ )) in
+ (let write_tag = (\<lambda> mem addr . map_update addr tag mem) in
+ ( s (| memstate := (List.foldl write_byte (memstate s) a_v),
+ tagstate := (List.foldl write_tag (tagstate s) addrs) |)))))))"
+
+
+\<comment> \<open>\<open>val write_memt_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> bitU -> monadS 'regs bool 'e\<close>\<close>
+definition write_memt_bytesS :: " write_kind \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow>(memory_byte)list \<Rightarrow> bitU \<Rightarrow>('regs,(bool),'e)monadS " where
+ " write_memt_bytesS _ addr sz v t = ( seqS
+ (updateS (put_mem_bytes addr sz v t))
+ (returnS True))"
+
+
+\<comment> \<open>\<open>val write_mem_bytesS : forall 'regs 'e. write_kind -> nat -> nat -> list memory_byte -> monadS 'regs bool 'e\<close>\<close>
+definition write_mem_bytesS :: " write_kind \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow>(memory_byte)list \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where
+ " write_mem_bytesS wk addr sz v = ( write_memt_bytesS wk addr sz v B0 )"
+
+
+\<comment> \<open>\<open>val write_memtS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'a -> integer -> 'b -> bitU -> monadS 'regs bool 'e\<close>\<close>
+definition write_memtS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow> bitU \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where
+ " write_memtS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr sz v t = (
+ (case (nat_of_bv dict_Sail2_values_Bitvector_a addr, mem_bytes_of_bits
+ dict_Sail2_values_Bitvector_b v) of
+ (Some addr, Some v) => write_memt_bytesS wk addr (nat_of_int sz) v t
+ | _ => failS (''write_mem'')
+ ))"
+
+
+\<comment> \<open>\<open>val write_memS : forall 'regs 'e 'a 'b 'addrsize. Bitvector 'a, Bitvector 'b =>
+ write_kind -> 'addrsize -> 'a -> integer -> 'b -> monadS 'regs bool 'e\<close>\<close>
+definition write_memS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'addrsize \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where
+ " write_memS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr_size addr sz v = ( write_memtS
+ dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b wk addr sz v B0 )"
+
+
+\<comment> \<open>\<open>val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e\<close>\<close>
+definition read_regS :: "('regs,'rv,'a)register_ref \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where
+ " read_regS reg = ( readS (\<lambda> s . (read_from reg)(regstate s)))"
+
+
+\<comment> \<open>\<open> TODO
+let read_reg_range reg i j state =
+ let v = slice (get_reg state (name_of_reg reg)) i j in
+ [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+ let v = access (get_reg state (name_of_reg reg)) i in
+ [(Value v,state)]
+let read_reg_field reg regfield =
+ let (i,j) = register_field_indices reg regfield in
+ read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+ let (i,_) = register_field_indices reg regfield in
+ read_reg_bit reg i \<close>\<close>
+
+\<comment> \<open>\<open>val read_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e\<close>\<close>
+fun read_regvalS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow>('regs,'rv,'e)monadS " where
+ " read_regvalS (read, _) reg = ( bindS
+ (readS (\<lambda> s . read reg(regstate s))) (\<lambda>x .
+ (case x of
+ Some v => returnS v
+ | None => failS ((''read_regvalS '') @ reg)
+ )))"
+
+
+\<comment> \<open>\<open>val write_regvalS : forall 'regs 'rv 'e.
+ register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e\<close>\<close>
+fun write_regvalS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow> 'rv \<Rightarrow>('regs,(unit),'e)monadS " where
+ " write_regvalS (_, write1) reg v = ( bindS
+ (readS (\<lambda> s . write1 reg v(regstate s))) (\<lambda>x .
+ (case x of
+ Some rs' => updateS (\<lambda> s . ( s (| regstate := rs' |)))
+ | None => failS ((''write_regvalS '') @ reg)
+ )))"
+
+
+\<comment> \<open>\<open>val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e\<close>\<close>
+definition write_regS :: "('regs,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where
+ " write_regS reg v = (
+ updateS (\<lambda> s . ( s (| regstate := ((write_to reg) v(regstate s)) |))))"
+
+
+\<comment> \<open>\<open> TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+ let current_value = get_reg state reg in
+ let new_value = f current_value v in
+ [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+ let current_field_value = regfield.get_field reg_val in
+ let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+ regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)\<close>\<close>
+
+\<comment> \<open>\<open> TODO Add Show typeclass for value and exception type \<close>\<close>
+\<comment> \<open>\<open>val show_result : forall 'a 'e. result 'a 'e -> string\<close>\<close>
+definition show_result :: "('a,'e)result \<Rightarrow> string " where
+ " show_result = ( \<lambda>x .
+ (case x of
+ Value _ => (''Value ()'')
+ | Ex (Failure msg) => (''Failure '') @ msg
+ | Ex (Throw _) => (''Throw'')
+ ) )"
+
+
+\<comment> \<open>\<open>val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit\<close>\<close>
+definition prerr_results :: "(('a,'e)result*'s)set \<Rightarrow> unit " where
+ " prerr_results rs = (
+ (let _ = (Set.image ( \<lambda>x .
+ (case x of (r, _) => (let _ = (prerr_endline (show_result r)) in () ) )) rs) in
+ () ))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy b/prover_snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy
new file mode 100644
index 0000000..2fbd7a5
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy
@@ -0,0 +1,243 @@
+theory Sail2_state_monad_lemmas
+ imports
+ Sail2_state_monad
+ Sail2_values_lemmas
+begin
+
+(*context
+ notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp]
+begin*)
+
+notation bindS (infixr "\<bind>\<^sub>S" 54)
+notation seqS (infixr "\<then>\<^sub>S" 54)
+
+lemma bindS_ext_cong[fundef_cong]:
+ assumes m: "m1 s = m2 s"
+ and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
+ shows "bindS m1 f1 s = bindS m2 f2 s"
+ using assms unfolding bindS_def by (auto split: result.splits)
+
+lemma bindS_cong[fundef_cong]:
+ assumes m: "m1 = m2"
+ and f: "\<And>s a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'"
+ shows "bindS m1 f1 = bindS m2 f2"
+ using assms by (intro ext bindS_ext_cong; blast)
+
+lemma bindS_returnS_left[simp]: "bindS (returnS x) f = f x"
+ by (auto simp add: bindS_def returnS_def)
+
+lemma bindS_returnS_right[simp]: "bindS m returnS = (m :: ('regs, 'a, 'e) monadS)"
+ by (intro ext) (auto simp: bindS_def returnS_def split: result.splits)
+
+lemma bindS_readS: "bindS (readS f) m = (\<lambda>s. m (f s) s)"
+ by (auto simp: bindS_def readS_def returnS_def)
+
+lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))"
+ by (auto simp: bindS_def updateS_def returnS_def)
+
+lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()"
+ by (auto simp: assert_expS_def)
+
+lemma bindS_chooseS_returnS[simp]: "bindS (chooseS xs) (\<lambda>x. returnS (f x)) = chooseS (map f xs)"
+ by (intro ext) (auto simp: bindS_def chooseS_def returnS_def)
+
+lemma result_cases:
+ fixes r :: "('a, 'e) result"
+ obtains (Value) a where "r = Value a"
+ | (Throw) e where "r = Ex (Throw e)"
+ | (Failure) msg where "r = Ex (Failure msg)"
+proof (cases r)
+ case (Ex ex) then show ?thesis by (cases ex; auto intro: that)
+qed
+
+lemma result_state_cases:
+ fixes rs :: "('a, 'e) result \<times> 's"
+ obtains (Value) a s where "rs = (Value a, s)"
+ | (Throw) e s where "rs = (Ex (Throw e), s)"
+ | (Failure) msg s where "rs = (Ex (Failure msg), s)"
+proof -
+ obtain r s where rs: "rs = (r, s)" by (cases rs)
+ then show thesis by (cases r rule: result_cases) (auto intro: that)
+qed
+
+lemma monadS_ext_eqI:
+ fixes m m' :: "('regs, 'a, 'e) monadS"
+ assumes "\<And>a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
+ and "\<And>e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
+ and "\<And>msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
+ shows "m s = m' s"
+proof (intro set_eqI)
+ fix x
+ show "x \<in> m s \<longleftrightarrow> x \<in> m' s" using assms by (cases x rule: result_state_cases) auto
+qed
+
+lemma monadS_eqI:
+ fixes m m' :: "('regs, 'a, 'e) monadS"
+ assumes "\<And>s a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s"
+ and "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s"
+ and "\<And>s msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s"
+ shows "m = m'"
+ using assms by (intro ext monadS_ext_eqI)
+
+lemma bindS_cases:
+ assumes "(r, s') \<in> bindS m f s"
+ obtains (Value) a a' s'' where "r = Value a" and "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
+ | (Ex_Left) e where "r = Ex e" and "(Ex e, s') \<in> m s"
+ | (Ex_Right) e a s'' where "r = Ex e" and "(Value a, s'') \<in> m s" and "(Ex e, s') \<in> f a s''"
+ using assms by (cases r; auto simp: bindS_def split: result.splits)
+
+lemma bindS_intros:
+ "\<And>m f s a s' a' s''. (Value a', s'') \<in> m s \<Longrightarrow> (Value a, s') \<in> f a' s'' \<Longrightarrow> (Value a, s') \<in> bindS m f s"
+ "\<And>m f s e s'. (Ex e, s') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
+ "\<And>m f s e s' a s''. (Ex e, s') \<in> f a s'' \<Longrightarrow> (Value a, s'') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s"
+ by (auto simp: bindS_def intro: bexI[rotated])
+
+lemma bindS_assoc[simp]: "bindS (bindS m f) g = bindS m (\<lambda>x. bindS (f x) g)"
+ by (auto elim!: bindS_cases intro: bindS_intros monadS_eqI)
+
+lemma bindS_failS[simp]: "bindS (failS msg) f = failS msg" by (auto simp: bindS_def failS_def)
+lemma bindS_throwS[simp]: "bindS (throwS e) f = throwS e" by (auto simp: bindS_def throwS_def)
+declare seqS_def[simp]
+
+lemma Value_bindS_elim:
+ assumes "(Value a, s') \<in> bindS m f s"
+ obtains s'' a' where "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''"
+ using assms by (auto elim: bindS_cases)
+
+lemma Ex_bindS_elim:
+ assumes "(Ex e, s') \<in> bindS m f s"
+ obtains (Left) "(Ex e, s') \<in> m s"
+ | (Right) s'' a' where "(Value a', s'') \<in> m s" and "(Ex e, s') \<in> f a' s''"
+ using assms by (auto elim: bindS_cases)
+
+lemma try_catchS_returnS[simp]: "try_catchS (returnS a) h = returnS a"
+ and try_catchS_failS[simp]: "try_catchS (failS msg) h = failS msg"
+ and try_catchS_throwS[simp]: "try_catchS (throwS e) h = h e"
+ by (auto simp: try_catchS_def returnS_def failS_def throwS_def)
+
+lemma try_catchS_cong[cong]:
+ assumes "\<And>s. m1 s = m2 s" and "\<And>e s. h1 e s = h2 e s"
+ shows "try_catchS m1 h1 = try_catchS m2 h2"
+ using assms by (intro arg_cong2[where f = try_catchS] ext) auto
+
+lemma try_catchS_cases:
+ assumes "(r, s') \<in> try_catchS m h s"
+ obtains (Value) a where "r = Value a" and "(Value a, s') \<in> m s"
+ | (Fail) msg where "r = Ex (Failure msg)" and "(Ex (Failure msg), s') \<in> m s"
+ | (h) e s'' where "(Ex (Throw e), s'') \<in> m s" and "(r, s') \<in> h e s''"
+ using assms
+ by (cases r rule: result_cases) (auto simp: try_catchS_def returnS_def split: result.splits ex.splits)
+
+lemma try_catchS_intros:
+ "\<And>m h s a s'. (Value a, s') \<in> m s \<Longrightarrow> (Value a, s') \<in> try_catchS m h s"
+ "\<And>m h s msg s'. (Ex (Failure msg), s') \<in> m s \<Longrightarrow> (Ex (Failure msg), s') \<in> try_catchS m h s"
+ "\<And>m h s e s'' r s'. (Ex (Throw e), s'') \<in> m s \<Longrightarrow> (r, s') \<in> h e s'' \<Longrightarrow> (r, s') \<in> try_catchS m h s"
+ by (auto simp: try_catchS_def returnS_def intro: bexI[rotated])
+
+lemma no_Ex_basic_builtins[simp]:
+ "\<And>s e s' a. (Ex e, s') \<in> returnS a s \<longleftrightarrow> False"
+ "\<And>s e s' f. (Ex e, s') \<in> readS f s \<longleftrightarrow> False"
+ "\<And>s e s' f. (Ex e, s') \<in> updateS f s \<longleftrightarrow> False"
+ "\<And>s e s' xs. (Ex e, s') \<in> chooseS xs s \<longleftrightarrow> False"
+ by (auto simp: readS_def updateS_def returnS_def chooseS_def)
+
+fun ignore_throw_aux :: "(('a, 'e1) result \<times> 's) \<Rightarrow> (('a, 'e2) result \<times> 's) set" where
+ "ignore_throw_aux (Value a, s') = {(Value a, s')}"
+| "ignore_throw_aux (Ex (Throw e), s') = {}"
+| "ignore_throw_aux (Ex (Failure msg), s') = {(Ex (Failure msg), s')}"
+definition "ignore_throw m s \<equiv> \<Union>(ignore_throw_aux ` m s)"
+
+lemma ignore_throw_cong:
+ assumes "\<And>s. m1 s = m2 s"
+ shows "ignore_throw m1 = ignore_throw m2"
+ using assms by (auto simp: ignore_throw_def)
+
+lemma ignore_throw_aux_member_simps[simp]:
+ "(Value a, s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Value a, s')"
+ "(Ex (Throw e), s') \<in> ignore_throw_aux ms \<longleftrightarrow> False"
+ "(Ex (Failure msg), s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Ex (Failure msg), s')"
+ by (cases ms rule: result_state_cases; auto)+
+
+lemma ignore_throw_member_simps[simp]:
+ "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
+ "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s"
+ "(Ex (Throw e), s') \<in> ignore_throw m s \<longleftrightarrow> False"
+ "(Ex (Failure msg), s') \<in> ignore_throw m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m s"
+ by (auto simp: ignore_throw_def)
+
+lemma ignore_throw_cases:
+ assumes no_throw: "ignore_throw m s = m s"
+ and r: "(r, s') \<in> m s"
+ obtains (Value) a where "r = Value a"
+ | (Failure) msg where "r = Ex (Failure msg)"
+ using r unfolding no_throw[symmetric]
+ by (cases r rule: result_cases) (auto simp: ignore_throw_def)
+
+lemma ignore_throw_bindS[simp]:
+ "ignore_throw (bindS m f) = bindS (ignore_throw m) (ignore_throw \<circ> f)"
+ by (intro monadS_eqI) (auto simp: ignore_throw_def elim!: bindS_cases intro: bindS_intros)
+
+lemma try_catchS_bindS_no_throw:
+ fixes m1 :: "('r, 'a, 'e1) monadS" and m2 :: "('r, 'a, 'e2) monadS"
+ assumes m1: "\<And>s. ignore_throw m1 s = m1 s"
+ and m2: "\<And>s. ignore_throw m1 s = m2 s"
+ shows "try_catchS (bindS m1 f) h = bindS m2 (\<lambda>a. try_catchS (f a) h)"
+proof
+ fix s
+ have "try_catchS (bindS m1 f) h s = bindS (ignore_throw m1) (\<lambda>a. try_catchS (f a) h) s"
+ by (intro monadS_ext_eqI;
+ auto elim!: bindS_cases try_catchS_cases elim: ignore_throw_cases[OF m1];
+ auto simp: ignore_throw_def intro: bindS_intros try_catchS_intros)
+ also have "\<dots> = bindS m2 (\<lambda>a. try_catchS (f a) h) s" using m2 by (intro bindS_ext_cong) auto
+ finally show "try_catchS (bindS m1 f) h s = bindS m2 (\<lambda>a. try_catchS (f a) h) s" .
+qed
+
+lemma no_throw_basic_builtins[simp]:
+ "ignore_throw (returnS a) = returnS a"
+ "\<And>f. ignore_throw (readS f) = readS f"
+ "\<And>f. ignore_throw (updateS f) = updateS f"
+ "ignore_throw (chooseS xs) = chooseS xs"
+ "ignore_throw (choose_boolS ()) = choose_boolS ()"
+ "ignore_throw (failS msg) = failS msg"
+ "ignore_throw (maybe_failS msg x) = maybe_failS msg x"
+ unfolding ignore_throw_def returnS_def chooseS_def maybe_failS_def failS_def readS_def updateS_def choose_boolS_def
+ by (intro ext; auto split: option.splits)+
+
+lemmas ignore_throw_option_case_distrib =
+ option.case_distrib[where h = "\<lambda>c. ignore_throw c s" and option = "c s" for c s]
+ option.case_distrib[where h = "\<lambda>c. ignore_throw c" and option = "c" for c]
+
+lemma ignore_throw_let_distrib: "ignore_throw (let x = y in f x) = (let x = y in ignore_throw (f x))"
+ by auto
+
+lemma no_throw_mem_builtins:
+ "\<And>rk a sz s. ignore_throw (read_mem_bytesS rk a sz) s = read_mem_bytesS rk a sz s"
+ "\<And>rk a sz s. ignore_throw (read_memt_bytesS rk a sz) s = read_memt_bytesS rk a sz s"
+ "\<And>BC a s. ignore_throw (read_tagS BC a) s = read_tagS BC a s"
+ "\<And>BCa BCv rk asz a sz s. ignore_throw (read_memS BCa BCv rk asz a sz) s = read_memS BCa BCv rk asz a sz s"
+ "\<And>BCa BCv rk a sz s. ignore_throw (read_memtS BCa BCv rk a sz) s = read_memtS BCa BCv rk a sz s"
+ "\<And>BC wk addr sz v s. ignore_throw (write_mem_bytesS wk addr sz v) s = write_mem_bytesS wk addr sz v s"
+ "\<And>BC wk addr sz v t s. ignore_throw (write_memt_bytesS wk addr sz v t) s = write_memt_bytesS wk addr sz v t s"
+ "\<And>BCa BCv wk asz addr sz v s. ignore_throw (write_memS BCa BCv wk asz addr sz v) s = write_memS BCa BCv wk asz addr sz v s"
+ "\<And>BCa BCv wk addr sz v t s. ignore_throw (write_memtS BCa BCv wk addr sz v t) s = write_memtS BCa BCv wk addr sz v t s"
+ "\<And>s. ignore_throw (excl_resultS ()) s = excl_resultS () s"
+ "\<And>s. ignore_throw (undefined_boolS ()) s = undefined_boolS () s"
+ unfolding read_mem_bytesS_def read_memt_bytesS_def read_memtS_def read_memS_def read_tagS_def
+ unfolding write_memS_def write_memtS_def write_mem_bytesS_def write_memt_bytesS_def
+ unfolding excl_resultS_def undefined_boolS_def maybe_failS_def
+ unfolding ignore_throw_bindS
+ by (auto cong: bindS_cong bindS_ext_cong ignore_throw_cong option.case_cong
+ simp: prod.case_distrib ignore_throw_option_case_distrib ignore_throw_let_distrib comp_def)
+
+lemma no_throw_read_regvalS: "ignore_throw (read_regvalS r reg_name) s = read_regvalS r reg_name s"
+ by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
+
+lemma no_throw_write_regvalS: "ignore_throw (write_regvalS r reg_name v) s = write_regvalS r reg_name v s"
+ by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong)
+
+lemmas no_throw_builtins[simp] =
+ no_throw_mem_builtins no_throw_read_regvalS no_throw_write_regvalS
+
+(* end *)
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_string.thy b/prover_snapshots/isabelle/lib/sail/Sail2_string.thy
new file mode 100644
index 0000000..eb0a62a
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_string.thy
@@ -0,0 +1,555 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_string.lem\<close>.\<close>
+
+theory "Sail2_string"
+
+imports
+ Main
+ "LEM.Lem_pervasives"
+ "LEM.Lem_list"
+ "LEM.Lem_list_extra"
+ "LEM.Lem_string"
+ "LEM.Lem_string_extra"
+ "Sail2_operators"
+ "Sail2_values"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives\<close>\<close>
+\<comment> \<open>\<open>open import List\<close>\<close>
+\<comment> \<open>\<open>open import List_extra\<close>\<close>
+\<comment> \<open>\<open>open import String\<close>\<close>
+\<comment> \<open>\<open>open import String_extra\<close>\<close>
+
+\<comment> \<open>\<open>open import Sail2_operators\<close>\<close>
+\<comment> \<open>\<open>open import Sail2_values\<close>\<close>
+
+\<comment> \<open>\<open>val string_sub : string -> ii -> ii -> string\<close>\<close>
+definition string_sub :: " string \<Rightarrow> int \<Rightarrow> int \<Rightarrow> string " where
+ " string_sub str start len = (
+ (List.take (nat (abs ( len))) (List.drop (nat (abs ( start))) ( str))))"
+
+
+\<comment> \<open>\<open>val string_startswith : string -> string -> bool\<close>\<close>
+definition string_startswith :: " string \<Rightarrow> string \<Rightarrow> bool " where
+ " string_startswith str1 str2 = (
+ (let prefix = (string_sub str1(( 0 :: int)) (int (List.length str2))) in
+ (prefix = str2)))"
+
+
+\<comment> \<open>\<open>val string_drop : string -> ii -> string\<close>\<close>
+definition string_drop :: " string \<Rightarrow> int \<Rightarrow> string " where
+ " string_drop str n = (
+ (List.drop (nat (abs ( n))) ( str)))"
+
+
+\<comment> \<open>\<open>val string_take : string -> ii -> string\<close>\<close>
+definition string_take :: " string \<Rightarrow> int \<Rightarrow> string " where
+ " string_take str n = (
+ (List.take (nat (abs ( n))) ( str)))"
+
+
+\<comment> \<open>\<open>val string_length : string -> ii\<close>\<close>
+definition string_length :: " string \<Rightarrow> int " where
+ " string_length s = ( int (List.length s))"
+
+
+definition string_append :: " string \<Rightarrow> string \<Rightarrow> string " where
+ " string_append = ( (@))"
+
+
+\<comment> \<open>\<open>**********************************************
+ * Begin stuff that should be in Lem Num_extra *
+ **********************************************\<close>\<close>
+
+\<comment> \<open>\<open>val maybeIntegerOfString : string -> maybe integer\<close>\<close>
+definition maybeIntegerOfString :: " string \<Rightarrow>(int)option " where
+ " maybeIntegerOfString _ = ( None )"
+
+
+\<comment> \<open>\<open>**********************************************
+ * end stuff that should be in Lem Num_extra *
+ **********************************************\<close>\<close>
+
+function (sequential,domintros) maybe_int_of_prefix :: " string \<Rightarrow>(int*int)option " where
+ " maybe_int_of_prefix s = (
+ if(s = ('''')) then None else
+ ((let len = (string_length s) in
+ (case maybeIntegerOfString s of
+ Some n => Some (n, len)
+ | None => maybe_int_of_prefix
+ (string_sub s (( 0 :: int)) (len - ( 1 :: int)))
+ ))) )"
+by pat_completeness auto
+
+
+definition maybe_int_of_string :: " string \<Rightarrow>(int)option " where
+ " maybe_int_of_string = ( maybeIntegerOfString )"
+
+
+\<comment> \<open>\<open>val n_leading_spaces : string -> ii\<close>\<close>
+function (sequential,domintros) n_leading_spaces :: " string \<Rightarrow> int " where
+ " n_leading_spaces s = (
+ (let len = (string_length s) in
+ if len =( 0 :: int) then( 0 :: int) else
+ if len =( 1 :: int) then
+ if(s = ('' '')) then ( 1 :: int) else ( 0 :: int)
+ else
+ \<comment> \<open>\<open> Isabelle generation for pattern matching on characters
+ is currently broken, so use an if-expression \<close>\<close>
+ if nth s(( 0 :: nat)) = (CHR '' '')
+ then( 1 :: int) + (n_leading_spaces (string_sub s(( 1 :: int)) (len -( 1 :: int))))
+ else( 0 :: int)))"
+by pat_completeness auto
+
+ \<comment> \<open>\<open> end \<close>\<close>
+
+definition opt_spc_matches_prefix :: " string \<Rightarrow>(unit*int)option " where
+ " opt_spc_matches_prefix s = (
+ Some (() , n_leading_spaces s))"
+
+
+definition spc_matches_prefix :: " string \<Rightarrow>(unit*int)option " where
+ " spc_matches_prefix s = (
+ (let n = (n_leading_spaces s) in
+ \<comment> \<open>\<open> match n with \<close>\<close>
+\<comment> \<open>\<open> | 0 -> Nothing \<close>\<close>
+ if n =( 0 :: int) then None else
+ \<comment> \<open>\<open> | n -> \<close>\<close> Some (() , n)))"
+
+ \<comment> \<open>\<open> end \<close>\<close>
+
+\<comment> \<open>\<open> Python:
+f = """let hex_bits_{0}_matches_prefix s =
+ match maybe_int_of_prefix s with
+ | Nothing -> Nothing
+ | Just (n, len) ->
+ if 0 <= n && n < (2 ** {0}) then
+ Just ((of_int {0} n, len))
+ else
+ Nothing
+ end
+"""
+
+for i in list(range(1, 34)) + [48, 64]:
+ print(f.format(i))
+\<close>\<close>
+definition hex_bits_1_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_1_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 1 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 1 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_2_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_2_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 2 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 2 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_3_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_3_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 3 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 3 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_4_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_4_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 4 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 4 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_5_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_5_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 5 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 5 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_6_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_6_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 6 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 6 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_7_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_7_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 7 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 7 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_8_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_8_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 8 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 8 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_9_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_9_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 9 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 9 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_10_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_10_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 10 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 10 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_11_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_11_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 11 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 11 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_12_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_12_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 12 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 12 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_13_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_13_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 13 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 13 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_14_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_14_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 14 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 14 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_15_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_15_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 15 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 15 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_16_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_16_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 16 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 16 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_17_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_17_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 17 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 17 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_18_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_18_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 18 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 18 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_19_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_19_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 19 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 19 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_20_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_20_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 20 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 20 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_21_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_21_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 21 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 21 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_22_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_22_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 22 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 22 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_23_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_23_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 23 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 23 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_24_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_24_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 24 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 24 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_25_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_25_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 25 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 25 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_26_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_26_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 26 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 26 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_27_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_27_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 27 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 27 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_28_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_28_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 28 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 28 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_29_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_29_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 29 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 29 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_30_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_30_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 30 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 30 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_31_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_31_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 31 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 31 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_32_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_32_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 32 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 32 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_33_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_33_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 33 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 33 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_48_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_48_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 48 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 48 :: int)) n, len))
+ else
+ None
+ ))"
+
+
+definition hex_bits_64_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where
+ " hex_bits_64_matches_prefix dict_Sail2_values_Bitvector_a s = (
+ (case maybe_int_of_prefix s of
+ None => None
+ | Some (n, len) =>
+ if(( 0 :: int) \<le> n) \<and> (n < (( 2 :: int) ^( 64 :: nat))) then
+ Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 64 :: int)) n, len))
+ else
+ None
+ ))"
+
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_values.thy b/prover_snapshots/isabelle/lib/sail/Sail2_values.thy
new file mode 100644
index 0000000..391c00a
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_values.thy
@@ -0,0 +1,1275 @@
+chapter \<open>Generated by Lem from \<open>../../src/gen_lib/sail2_values.lem\<close>.\<close>
+
+theory "Sail2_values"
+
+imports
+ Main
+ "LEM.Lem_pervasives_extra"
+ "LEM.Lem_machine_word"
+
+begin
+
+\<comment> \<open>\<open>open import Pervasives_extra\<close>\<close>
+\<comment> \<open>\<open>open import Machine_word\<close>\<close>
+\<comment> \<open>\<open>open import Sail_impl_base\<close>\<close>
+
+
+type_synonym ii =" int "
+type_synonym nn =" nat "
+
+\<comment> \<open>\<open>val nat_of_int : integer -> nat\<close>\<close>
+definition nat_of_int :: " int \<Rightarrow> nat " where
+ " nat_of_int i = ( if i <( 0 :: int) then( 0 :: nat) else nat (abs ( i)))"
+
+
+\<comment> \<open>\<open>val pow : integer -> integer -> integer\<close>\<close>
+definition pow :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " pow m n = ( m ^ (nat_of_int n))"
+
+
+definition pow2 :: " int \<Rightarrow> int " where
+ " pow2 n = ( pow(( 2 :: int)) n )"
+
+
+\<comment> \<open>\<open>val eq : forall 'a. Eq 'a => 'a -> 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>val neq : forall 'a. Eq 'a => 'a -> 'a -> bool\<close>\<close>
+
+\<comment> \<open>\<open>let add_int l r = integerAdd l r
+let add_signed l r = integerAdd l r
+let sub_int l r = integerMinus l r
+let mult_int l r = integerMult l r
+let div_int l r = integerDiv l r
+let div_nat l r = natDiv l r
+let power_int_nat l r = integerPow l r
+let power_int_int l r = integerPow l (nat_of_int r)
+let negate_int i = integerNegate i
+let min_int l r = integerMin l r
+let max_int l r = integerMax l r
+
+let add_real l r = realAdd l r
+let sub_real l r = realMinus l r
+let mult_real l r = realMult l r
+let div_real l r = realDiv l r
+let negate_real r = realNegate r
+let abs_real r = realAbs r
+let power_real b e = realPowInteger b e\<close>\<close>
+
+\<comment> \<open>\<open>val print_endline : string -> unit\<close>\<close>
+definition print_endline :: " string \<Rightarrow> unit " where
+ " print_endline _ = ( () )"
+
+
+\<comment> \<open>\<open>val print : string -> unit\<close>\<close>
+definition print :: " string \<Rightarrow> unit " where
+ " print _ = ( () )"
+
+
+\<comment> \<open>\<open>val prerr_endline : string -> unit\<close>\<close>
+definition prerr_endline :: " string \<Rightarrow> unit " where
+ " prerr_endline _ = ( () )"
+
+
+definition prerr :: " string \<Rightarrow> unit " where
+ " prerr x = ( prerr_endline x )"
+
+
+\<comment> \<open>\<open>val print_int : string -> integer -> unit\<close>\<close>
+definition print_int :: " string \<Rightarrow> int \<Rightarrow> unit " where
+ " print_int msg i = ( print_endline (msg @ (stringFromInteger i)))"
+
+
+\<comment> \<open>\<open>val prerr_int : string -> integer -> unit\<close>\<close>
+definition prerr_int :: " string \<Rightarrow> int \<Rightarrow> unit " where
+ " prerr_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))"
+
+
+\<comment> \<open>\<open>val putchar : integer -> unit\<close>\<close>
+definition putchar :: " int \<Rightarrow> unit " where
+ " putchar _ = ( () )"
+
+
+\<comment> \<open>\<open>val shr_int : ii -> ii -> ii\<close>\<close>
+function (sequential,domintros) shr_int :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " shr_int x s = ( if s >( 0 :: int) then shr_int (x div( 2 :: int)) (s -( 1 :: int)) else x )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val shl_int : integer -> integer -> integer\<close>\<close>
+function (sequential,domintros) shl_int :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " shl_int i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int i (shift -( 1 :: int)) else i )"
+by pat_completeness auto
+
+definition take_list :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " take_list n xs = ( List.take (nat_of_int n) xs )"
+
+definition drop_list :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " drop_list n xs = ( List.drop (nat_of_int n) xs )"
+
+
+\<comment> \<open>\<open>val repeat : forall 'a. list 'a -> integer -> list 'a\<close>\<close>
+fun repeat :: " 'a list \<Rightarrow> int \<Rightarrow> 'a list " where
+ " repeat xs n = (
+ if n \<le>( 0 :: int) then []
+ else xs @ repeat xs (n-( 1 :: int)))"
+
+
+definition duplicate_to_list :: " 'a \<Rightarrow> int \<Rightarrow> 'a list " where
+ " duplicate_to_list bit length1 = ( repeat [bit] length1 )"
+
+
+fun replace :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where
+ " replace ([]) (n :: int) b' = ( [])"
+|" replace (b # bs) (n :: int) b' = (
+ if n =( 0 :: int) then b' # bs
+ else b # replace bs (n -( 1 :: int)) b' )"
+
+
+definition upper :: " 'a \<Rightarrow> 'a " where
+ " upper n = ( n )"
+
+
+\<comment> \<open>\<open> Modulus operation corresponding to quot below -- result
+ has sign of dividend. \<close>\<close>
+definition hardware_mod :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " hardware_mod (a:: int) (b::int) = (
+ (let m = ((abs a) mod (abs b)) in
+ if a <( 0 :: int) then - m else m))"
+
+
+\<comment> \<open>\<open> There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that \<close>\<close>
+definition hardware_quot :: " int \<Rightarrow> int \<Rightarrow> int " where
+ " hardware_quot (a::int) (b::int) = (
+ (let q = ((abs a) div (abs b)) in
+ if ((a<( 0 :: int)) \<longleftrightarrow> (b<( 0 :: int))) then
+ q \<comment> \<open>\<open> same sign -- result positive \<close>\<close>
+ else
+ - q))"
+ \<comment> \<open>\<open> different sign -- result negative \<close>\<close>
+
+definition max_64u :: " int " where
+ " max_64u = ( ((( 2 :: int))^(( 64 :: nat))) -( 1 :: int))"
+
+definition max_64 :: " int " where
+ " max_64 = ( ((( 2 :: int))^(( 63 :: nat))) -( 1 :: int))"
+
+definition min_64 :: " int " where
+ " min_64 = (( 0 :: int) - ((( 2 :: int))^(( 63 :: nat))))"
+
+definition max_32u :: " int " where
+ " max_32u = ( (( 4294967295 :: int) :: int))"
+
+definition max_32 :: " int " where
+ " max_32 = ( (( 2147483647 :: int) :: int))"
+
+definition min_32 :: " int " where
+ " min_32 = ( (( 0 :: int) -( 2147483648 :: int) :: int))"
+
+definition max_8 :: " int " where
+ " max_8 = ( (( 127 :: int) :: int))"
+
+definition min_8 :: " int " where
+ " min_8 = ( (( 0 :: int) -( 128 :: int) :: int))"
+
+definition max_5 :: " int " where
+ " max_5 = ( (( 31 :: int) :: int))"
+
+definition min_5 :: " int " where
+ " min_5 = ( (( 0 :: int) -( 32 :: int) :: int))"
+
+
+\<comment> \<open>\<open> just_list takes a list of maybes and returns Just xs if all elements have
+ a value, and Nothing if one of the elements is Nothing. \<close>\<close>
+\<comment> \<open>\<open>val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)\<close>\<close>
+fun just_list :: "('a option)list \<Rightarrow>('a list)option " where
+ " just_list ([]) = ( Some [])"
+|" just_list (x # xs) = (
+ (case (x, just_list xs) of
+ (Some x, Some xs) => Some (x # xs)
+ | (_, _) => None
+ ))"
+
+
+\<comment> \<open>\<open>val maybe_failwith : forall 'a. maybe 'a -> 'a\<close>\<close>
+definition maybe_failwith :: " 'a option \<Rightarrow> 'a " where
+ " maybe_failwith = ( \<lambda>x .
+ (case x of Some a => a | None => failwith (''maybe_failwith'') ) )"
+
+
+\<comment> \<open>\<open>** Bits \<close>\<close>
+datatype bitU = B0 | B1 | BU
+
+definition showBitU :: " bitU \<Rightarrow> string " where
+ " showBitU = ( \<lambda>x .
+ (case x of B0 => (''O'') | B1 => (''I'') | BU => (''U'') ) )"
+
+
+definition bitU_char :: " bitU \<Rightarrow> char " where
+ " bitU_char = ( \<lambda>x .
+ (case x of B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )"
+
+
+definition instance_Show_Show_Sail2_values_bitU_dict :: "(bitU)Show_class " where
+ " instance_Show_Show_Sail2_values_bitU_dict = ((|
+
+ show_method = showBitU |) )"
+
+
+\<comment> \<open>\<open>val compare_bitU : bitU -> bitU -> ordering\<close>\<close>
+fun compare_bitU :: " bitU \<Rightarrow> bitU \<Rightarrow> ordering " where
+ " compare_bitU BU BU = ( EQ )"
+|" compare_bitU B0 B0 = ( EQ )"
+|" compare_bitU B1 B1 = ( EQ )"
+|" compare_bitU BU _ = ( LT )"
+|" compare_bitU _ BU = ( GT )"
+|" compare_bitU B0 _ = ( LT )"
+|" compare_bitU _ _ = ( GT )"
+
+
+definition instance_Basic_classes_Ord_Sail2_values_bitU_dict :: "(bitU)Ord_class " where
+ " instance_Basic_classes_Ord_Sail2_values_bitU_dict = ((|
+
+ compare_method = compare_bitU,
+
+ isLess_method = (\<lambda> l r. (compare_bitU l r) = LT),
+
+ isLessEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> GT),
+
+ isGreater_method = (\<lambda> l r. (compare_bitU l r) = GT),
+
+ isGreaterEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> LT)|) )"
+
+
+record 'a BitU_class=
+
+ to_bitU_method ::" 'a \<Rightarrow> bitU "
+
+ of_bitU_method ::" bitU \<Rightarrow> 'a "
+
+
+
+definition instance_Sail2_values_BitU_Sail2_values_bitU_dict :: "(bitU)BitU_class " where
+ " instance_Sail2_values_BitU_Sail2_values_bitU_dict = ((|
+
+ to_bitU_method = (\<lambda> b. b),
+
+ of_bitU_method = (\<lambda> b. b)|) )"
+
+
+definition bool_of_bitU :: " bitU \<Rightarrow>(bool)option " where
+ " bool_of_bitU = ( \<lambda>x .
+ (case x of B0 => Some False | B1 => Some True | BU => None ) )"
+
+
+definition bitU_of_bool :: " bool \<Rightarrow> bitU " where
+ " bitU_of_bool b = ( if b then B1 else B0 )"
+
+
+\<comment> \<open>\<open>instance (BitU bool)
+ let to_bitU = bitU_of_bool
+ let of_bitU = bool_of_bitU
+end\<close>\<close>
+
+definition cast_bit_bool :: " bitU \<Rightarrow>(bool)option " where
+ " cast_bit_bool = ( bool_of_bitU )"
+
+
+definition not_bit :: " bitU \<Rightarrow> bitU " where
+ " not_bit = ( \<lambda>x .
+ (case x of B1 => B0 | B0 => B1 | BU => BU ) )"
+
+
+\<comment> \<open>\<open>val is_one : integer -> bitU\<close>\<close>
+definition is_one :: " int \<Rightarrow> bitU " where
+ " is_one i = (
+ if i =( 1 :: int) then B1 else B0 )"
+
+
+\<comment> \<open>\<open>val and_bit : bitU -> bitU -> bitU\<close>\<close>
+fun and_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where
+ " and_bit B0 _ = ( B0 )"
+|" and_bit _ B0 = ( B0 )"
+|" and_bit B1 B1 = ( B1 )"
+|" and_bit _ _ = ( BU )"
+
+
+\<comment> \<open>\<open>val or_bit : bitU -> bitU -> bitU\<close>\<close>
+fun or_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where
+ " or_bit B1 _ = ( B1 )"
+|" or_bit _ B1 = ( B1 )"
+|" or_bit B0 B0 = ( B0 )"
+|" or_bit _ _ = ( BU )"
+
+
+\<comment> \<open>\<open>val xor_bit : bitU -> bitU -> bitU\<close>\<close>
+fun xor_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where
+ " xor_bit B0 B0 = ( B0 )"
+|" xor_bit B0 B1 = ( B1 )"
+|" xor_bit B1 B0 = ( B1 )"
+|" xor_bit B1 B1 = ( B0 )"
+|" xor_bit _ _ = ( BU )"
+
+
+\<comment> \<open>\<open>val &. : bitU -> bitU -> bitU\<close>\<close>
+
+\<comment> \<open>\<open>val |. : bitU -> bitU -> bitU\<close>\<close>
+
+\<comment> \<open>\<open>val +. : bitU -> bitU -> bitU\<close>\<close>
+
+
+\<comment> \<open>\<open>** Bool lists **\<close>\<close>
+
+\<comment> \<open>\<open>val bools_of_nat_aux : integer -> natural -> list bool -> list bool\<close>\<close>
+fun bools_of_nat_aux :: " int \<Rightarrow> nat \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where
+ " bools_of_nat_aux len x acc1 = (
+ if len \<le>( 0 :: int) then acc1
+ else bools_of_nat_aux (len -( 1 :: int)) (x div( 2 :: nat)) ((if (x mod( 2 :: nat)) =( 1 :: nat) then True else False) # acc1))"
+
+definition bools_of_nat :: " int \<Rightarrow> nat \<Rightarrow>(bool)list " where
+ " bools_of_nat len n = ( bools_of_nat_aux len n [])"
+ \<comment> \<open>\<open>List.reverse (bools_of_nat_aux n)\<close>\<close>
+
+\<comment> \<open>\<open>val nat_of_bools_aux : natural -> list bool -> natural\<close>\<close>
+fun nat_of_bools_aux :: " nat \<Rightarrow>(bool)list \<Rightarrow> nat " where
+ " nat_of_bools_aux acc1 ([]) = ( acc1 )"
+|" nat_of_bools_aux acc1 (True # bs) = ( nat_of_bools_aux ((( 2 :: nat) * acc1) +( 1 :: nat)) bs )"
+|" nat_of_bools_aux acc1 (False # bs) = ( nat_of_bools_aux (( 2 :: nat) * acc1) bs )"
+
+definition nat_of_bools :: "(bool)list \<Rightarrow> nat " where
+ " nat_of_bools bs = ( nat_of_bools_aux(( 0 :: nat)) bs )"
+
+
+\<comment> \<open>\<open>val unsigned_of_bools : list bool -> integer\<close>\<close>
+definition unsigned_of_bools :: "(bool)list \<Rightarrow> int " where
+ " unsigned_of_bools bs = ( int (nat_of_bools bs))"
+
+
+\<comment> \<open>\<open>val signed_of_bools : list bool -> integer\<close>\<close>
+definition signed_of_bools :: "(bool)list \<Rightarrow> int " where
+ " signed_of_bools bs = (
+ (case bs of
+ True # _ =>( 0 :: int) - (( 1 :: int) + (unsigned_of_bools (List.map (\<lambda> x. \<not> x) bs)))
+ | False # _ => unsigned_of_bools bs
+ | [] =>( 0 :: int) \<comment> \<open>\<open> Treat empty list as all zeros \<close>\<close>
+ ))"
+
+
+\<comment> \<open>\<open>val int_of_bools : bool -> list bool -> integer\<close>\<close>
+definition int_of_bools :: " bool \<Rightarrow>(bool)list \<Rightarrow> int " where
+ " int_of_bools sign bs = ( if sign then signed_of_bools bs else unsigned_of_bools bs )"
+
+
+\<comment> \<open>\<open>val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a\<close>\<close>
+fun pad_list :: " 'a \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a list " where
+ " pad_list x xs n = (
+ if n \<le>( 0 :: int) then xs else pad_list x (x # xs) (n -( 1 :: int)))"
+
+
+definition ext_list :: " 'a \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " ext_list pad len xs = (
+ (let longer = (len - (int (List.length xs))) in
+ if longer <( 0 :: int) then List.drop (nat_of_int (abs (longer))) xs
+ else pad_list pad xs longer))"
+
+
+definition extz_bools :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where
+ " extz_bools len bs = ( ext_list False len bs )"
+
+definition exts_bools :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where
+ " exts_bools len bs = (
+ (case bs of
+ True # _ => ext_list True len bs
+ | _ => ext_list False len bs
+ ))"
+
+
+fun add_one_bool_ignore_overflow_aux :: "(bool)list \<Rightarrow>(bool)list " where
+ " add_one_bool_ignore_overflow_aux ([]) = ( [])"
+|" add_one_bool_ignore_overflow_aux (False # bits) = ( True # bits )"
+|" add_one_bool_ignore_overflow_aux (True # bits) = ( False # add_one_bool_ignore_overflow_aux bits )"
+
+
+definition add_one_bool_ignore_overflow :: "(bool)list \<Rightarrow>(bool)list " where
+ " add_one_bool_ignore_overflow bits = (
+ List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)))"
+
+
+\<comment> \<open>\<open>let bool_list_of_int n =
+ let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+ if n >= (0 : integer) then bs_abs
+ else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)\<close>\<close>
+definition bools_of_int :: " int \<Rightarrow> int \<Rightarrow>(bool)list " where
+ " bools_of_int len n = (
+ (let bs_abs = (bools_of_nat len (nat (abs (abs n)))) in
+ if n \<ge> (( 0 :: int) :: int) then bs_abs
+ else add_one_bool_ignore_overflow (List.map (\<lambda> x. \<not> x) bs_abs)))"
+
+
+\<comment> \<open>\<open>** Bit lists **\<close>\<close>
+
+\<comment> \<open>\<open>val has_undefined_bits : list bitU -> bool\<close>\<close>
+definition has_undefined_bits :: "(bitU)list \<Rightarrow> bool " where
+ " has_undefined_bits bs = ( ((\<exists> x \<in> (set bs). (\<lambda>x .
+ (case x of BU => True | _ => False )) x)))"
+
+
+definition bits_of_nat :: " int \<Rightarrow> nat \<Rightarrow>(bitU)list " where
+ " bits_of_nat len n = ( List.map bitU_of_bool (bools_of_nat len n))"
+
+
+definition nat_of_bits :: "(bitU)list \<Rightarrow>(nat)option " where
+ " nat_of_bits bits = (
+ (case (just_list (List.map bool_of_bitU bits)) of
+ Some bs => Some (nat_of_bools bs)
+ | None => None
+ ))"
+
+
+definition not_bits :: "(bitU)list \<Rightarrow>(bitU)list " where
+ " not_bits = ( List.map not_bit )"
+
+
+\<comment> \<open>\<open>val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a\<close>\<close>
+definition binop_list :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " binop_list op1 xs ys = (
+ List.foldr ( \<lambda>x .
+ (case x of (x, y) => \<lambda> acc1 . op1 x y # acc1 )) (List.zip xs ys) [])"
+
+
+definition unsigned_of_bits :: "(bitU)list \<Rightarrow>(int)option " where
+ " unsigned_of_bits bits = (
+ (case (just_list (List.map bool_of_bitU bits)) of
+ Some bs => Some (unsigned_of_bools bs)
+ | None => None
+ ))"
+
+
+definition signed_of_bits :: "(bitU)list \<Rightarrow>(int)option " where
+ " signed_of_bits bits = (
+ (case (just_list (List.map bool_of_bitU bits)) of
+ Some bs => Some (signed_of_bools bs)
+ | None => None
+ ))"
+
+
+\<comment> \<open>\<open>val int_of_bits : bool -> list bitU -> maybe integer\<close>\<close>
+definition int_of_bits :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option " where
+ " int_of_bits sign bs = ( if sign then signed_of_bits bs else unsigned_of_bits bs )"
+
+
+definition extz_bits :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " extz_bits len bits = ( ext_list B0 len bits )"
+
+definition exts_bits :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " exts_bits len bits = (
+ (case bits of
+ BU # _ => ext_list BU len bits
+ | B1 # _ => ext_list B1 len bits
+ | _ => ext_list B0 len bits
+ ))"
+
+
+fun add_one_bit_ignore_overflow_aux :: "(bitU)list \<Rightarrow>(bitU)list " where
+ " add_one_bit_ignore_overflow_aux ([]) = ( [])"
+|" add_one_bit_ignore_overflow_aux (B0 # bits) = ( B1 # bits )"
+|" add_one_bit_ignore_overflow_aux (B1 # bits) = ( B0 # add_one_bit_ignore_overflow_aux bits )"
+|" add_one_bit_ignore_overflow_aux (BU # bits) = ( BU # List.map ( \<lambda>x .
+ (case x of _ => BU )) bits )"
+
+
+definition add_one_bit_ignore_overflow :: "(bitU)list \<Rightarrow>(bitU)list " where
+ " add_one_bit_ignore_overflow bits = (
+ List.rev (add_one_bit_ignore_overflow_aux (List.rev bits)))"
+
+
+\<comment> \<open>\<open>let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n)
+let bits_of_int len n = exts_bits len (bit_list_of_int n)\<close>\<close>
+definition bits_of_int :: " int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " bits_of_int len n = ( List.map bitU_of_bool (bools_of_int len n))"
+
+
+\<comment> \<open>\<open>val arith_op_bits :
+ (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU\<close>\<close>
+definition arith_op_bits :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where
+ " arith_op_bits op1 sign l r = (
+ (case (int_of_bits sign l, int_of_bits sign r) of
+ (Some li, Some ri) => bits_of_int (int (List.length l)) (op1 li ri)
+ | (_, _) => repeat [BU] (int (List.length l))
+ ))"
+
+
+definition char_of_nibble :: " bitU*bitU*bitU*bitU \<Rightarrow>(char)option " where
+ " char_of_nibble = ( \<lambda>x .
+ (case x of
+ (B0, B0, B0, B0) => Some (CHR ''0'')
+ | (B0, B0, B0, B1) => Some (CHR ''1'')
+ | (B0, B0, B1, B0) => Some (CHR ''2'')
+ | (B0, B0, B1, B1) => Some (CHR ''3'')
+ | (B0, B1, B0, B0) => Some (CHR ''4'')
+ | (B0, B1, B0, B1) => Some (CHR ''5'')
+ | (B0, B1, B1, B0) => Some (CHR ''6'')
+ | (B0, B1, B1, B1) => Some (CHR ''7'')
+ | (B1, B0, B0, B0) => Some (CHR ''8'')
+ | (B1, B0, B0, B1) => Some (CHR ''9'')
+ | (B1, B0, B1, B0) => Some (CHR ''A'')
+ | (B1, B0, B1, B1) => Some (CHR ''B'')
+ | (B1, B1, B0, B0) => Some (CHR ''C'')
+ | (B1, B1, B0, B1) => Some (CHR ''D'')
+ | (B1, B1, B1, B0) => Some (CHR ''E'')
+ | (B1, B1, B1, B1) => Some (CHR ''F'')
+ | _ => None
+ ) )"
+
+
+fun hexstring_of_bits :: "(bitU)list \<Rightarrow>((char)list)option " where
+ " hexstring_of_bits (b1 # b2 # b3 # b4 # bs) = (
+ (let n = (char_of_nibble (b1, b2, b3, b4)) in
+ (let s = (hexstring_of_bits bs) in
+ (case (n, s) of
+ (Some n, Some s) => Some (n # s)
+ | _ => None
+ ))))"
+|" hexstring_of_bits ([]) = ( Some [])"
+|" hexstring_of_bits _ = ( None )"
+
+
+definition show_bitlist :: "(bitU)list \<Rightarrow> string " where
+ " show_bitlist bs = (
+ (case hexstring_of_bits bs of
+ Some s => ((CHR ''0'') # ((CHR ''x'') # s))
+ | None => ((CHR ''0'') # ((CHR ''b'') # List.map bitU_char bs))
+ ))"
+
+
+\<comment> \<open>\<open>val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a\<close>\<close>
+definition subrange_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where
+ " subrange_list_inc xs i j = (
+ (let (toJ,suffix0) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
+ (let (prefix0,fromItoJ) = (split_at (nat_of_int i) toJ) in
+ fromItoJ)))"
+
+
+\<comment> \<open>\<open>val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a\<close>\<close>
+definition subrange_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where
+ " subrange_list_dec xs i j = (
+ (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+ subrange_list_inc xs (top1 - i) (top1 - j)))"
+
+
+\<comment> \<open>\<open>val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a\<close>\<close>
+definition subrange_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where
+ " subrange_list is_inc xs i j = ( if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j )"
+
+
+\<comment> \<open>\<open>val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a\<close>\<close>
+definition update_subrange_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " update_subrange_list_inc xs i j xs' = (
+ (let (toJ,suffix) = (split_at (nat_of_int (j +( 1 :: int))) xs) in
+ (let (prefix,fromItoJ0) = (split_at (nat_of_int i) toJ) in
+ (prefix @ xs') @ suffix)))"
+
+
+\<comment> \<open>\<open>val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a\<close>\<close>
+definition update_subrange_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " update_subrange_list_dec xs i j xs' = (
+ (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+ update_subrange_list_inc xs (top1 - i) (top1 - j) xs'))"
+
+
+\<comment> \<open>\<open>val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a\<close>\<close>
+definition update_subrange_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where
+ " update_subrange_list is_inc xs i j xs' = (
+ if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' )"
+
+
+\<comment> \<open>\<open>val access_list_inc : forall 'a. list 'a -> integer -> 'a\<close>\<close>
+definition access_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> 'a " where
+ " access_list_inc xs n = ( List.nth xs (nat_of_int n))"
+
+
+\<comment> \<open>\<open>val access_list_dec : forall 'a. list 'a -> integer -> 'a\<close>\<close>
+definition access_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> 'a " where
+ " access_list_dec xs n = (
+ (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+ access_list_inc xs (top1 - n)))"
+
+
+\<comment> \<open>\<open>val access_list : forall 'a. bool -> list 'a -> integer -> 'a\<close>\<close>
+definition access_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a " where
+ " access_list is_inc xs n = (
+ if is_inc then access_list_inc xs n else access_list_dec xs n )"
+
+
+\<comment> \<open>\<open>val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a\<close>\<close>
+definition update_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where
+ " update_list_inc xs n x = ( List.list_update xs (nat_of_int n) x )"
+
+
+\<comment> \<open>\<open>val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a\<close>\<close>
+definition update_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where
+ " update_list_dec xs n x = (
+ (let top1 = ((int (List.length xs)) -( 1 :: int)) in
+ update_list_inc xs (top1 - n) x))"
+
+
+\<comment> \<open>\<open>val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a\<close>\<close>
+definition update_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where
+ " update_list is_inc xs n x = (
+ if is_inc then update_list_inc xs n x else update_list_dec xs n x )"
+
+
+definition extract_only_bit :: "(bitU)list \<Rightarrow> bitU " where
+ " extract_only_bit = ( \<lambda>x .
+ (case x of [] => BU | [e] => e | _ => BU ) )"
+
+
+\<comment> \<open>\<open>** Machine words \<close>\<close>
+
+\<comment> \<open>\<open>val length_mword : forall 'a. mword 'a -> integer\<close>\<close>
+
+\<comment> \<open>\<open>val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition slice_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " slice_mword_dec w i j = ( Word.slice (nat_of_int i) w )"
+
+
+\<comment> \<open>\<open>val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition slice_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " slice_mword_inc w i j = (
+ (let top1 = ((int (size w)) -( 1 :: int)) in
+ slice_mword_dec w (top1 - i) (top1 - j)))"
+
+
+\<comment> \<open>\<open>val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b\<close>\<close>
+definition slice_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where
+ " slice_mword is_inc w i j = ( if is_inc then slice_mword_inc w i j else slice_mword_dec w i j )"
+
+
+\<comment> \<open>\<open>val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition update_slice_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " update_slice_mword_dec w i j w' = ( Lem.word_update w (nat_of_int i) (nat_of_int j) w' )"
+
+
+\<comment> \<open>\<open>val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition update_slice_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " update_slice_mword_inc w i j w' = (
+ (let top1 = ((int (size w)) -( 1 :: int)) in
+ update_slice_mword_dec w (top1 - i) (top1 - j) w'))"
+
+
+\<comment> \<open>\<open>val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a\<close>\<close>
+definition update_slice_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where
+ " update_slice_mword is_inc w i j w' = (
+ if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' )"
+
+
+\<comment> \<open>\<open>val access_mword_dec : forall 'a. mword 'a -> integer -> bitU\<close>\<close>
+definition access_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_mword_dec w n = ( bitU_of_bool (Bits.test_bit w (nat_of_int n)))"
+
+
+\<comment> \<open>\<open>val access_mword_inc : forall 'a. mword 'a -> integer -> bitU\<close>\<close>
+definition access_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_mword_inc w n = (
+ (let top1 = ((int (size w)) -( 1 :: int)) in
+ access_mword_dec w (top1 - n)))"
+
+
+\<comment> \<open>\<open>val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU\<close>\<close>
+definition access_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_mword is_inc w n = (
+ if is_inc then access_mword_inc w n else access_mword_dec w n )"
+
+
+\<comment> \<open>\<open>val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a\<close>\<close>
+definition update_mword_bool_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " update_mword_bool_dec w n b = ( Bits.set_bit w (nat_of_int n) b )"
+
+definition update_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " update_mword_dec w n b = ( map_option (update_mword_bool_dec w n) (bool_of_bitU b))"
+
+
+\<comment> \<open>\<open>val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a\<close>\<close>
+definition update_mword_bool_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where
+ " update_mword_bool_inc w n b = (
+ (let top1 = ((int (size w)) -( 1 :: int)) in
+ update_mword_bool_dec w (top1 - n) b))"
+
+definition update_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where
+ " update_mword_inc w n b = ( map_option (update_mword_bool_inc w n) (bool_of_bitU b))"
+
+
+\<comment> \<open>\<open>val int_of_mword : forall 'a. bool -> mword 'a -> integer\<close>\<close>
+definition int_of_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where
+ " int_of_mword sign w = (
+ if sign then Word.sint w else Word.uint w )"
+
+
+\<comment> \<open>\<open> Translating between a type level number (itself 'n) and an integer \<close>\<close>
+
+definition size_itself_int :: "('a::len)itself \<Rightarrow> int " where
+ " size_itself_int x = ( int (size_itself x))"
+
+
+\<comment> \<open>\<open> NB: the corresponding sail type is forall 'n. atom('n) -> itself('n),
+ the actual integer is ignored. \<close>\<close>
+
+\<comment> \<open>\<open>val make_the_value : forall 'n. integer -> itself 'n\<close>\<close>
+definition make_the_value :: " int \<Rightarrow>('n::len)itself " where
+ " make_the_value _ = ( TYPE(_) )"
+
+
+\<comment> \<open>\<open>** Bitvectors \<close>\<close>
+
+record 'a Bitvector_class=
+
+ bits_of_method ::" 'a \<Rightarrow> bitU list "
+
+ \<comment> \<open>\<open> We allow of_bits to be partial, as not all bitvector representations
+ support undefined bits \<close>\<close>
+ of_bits_method ::" bitU list \<Rightarrow> 'a option "
+
+ of_bools_method ::" bool list \<Rightarrow> 'a "
+
+ length_method ::" 'a \<Rightarrow> int "
+
+ \<comment> \<open>\<open> of_int: the first parameter specifies the desired length of the bitvector \<close>\<close>
+ of_int_method ::" int \<Rightarrow> int \<Rightarrow> 'a "
+
+ \<comment> \<open>\<open> Conversion to integers is undefined if any bit is undefined \<close>\<close>
+ unsigned_method ::" 'a \<Rightarrow> int option "
+
+ signed_method ::" 'a \<Rightarrow> int option "
+
+ \<comment> \<open>\<open> Lifting of integer operations to bitvectors: The boolean flag indicates
+ whether to treat the bitvectors as signed (true) or not (false). \<close>\<close>
+ arith_op_bv_method ::" (int \<Rightarrow> int \<Rightarrow> int) \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a "
+
+
+
+\<comment> \<open>\<open>val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a\<close>\<close>
+definition of_bits_failwith :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'a " where
+ " of_bits_failwith dict_Sail2_values_Bitvector_a bits = ( maybe_failwith (
+ (of_bits_method dict_Sail2_values_Bitvector_a) bits))"
+
+
+definition int_of_bv :: " 'a Bitvector_class \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow>(int)option " where
+ " int_of_bv dict_Sail2_values_Bitvector_a sign = ( if sign then
+ (signed_method dict_Sail2_values_Bitvector_a) else (unsigned_method dict_Sail2_values_Bitvector_a) )"
+
+
+definition instance_Sail2_values_Bitvector_list_dict :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class " where
+ " instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a = ((|
+
+ bits_of_method = (\<lambda> v. List.map
+ (to_bitU_method dict_Sail2_values_BitU_a) v),
+
+ of_bits_method = (\<lambda> v. Some (List.map
+ (of_bitU_method dict_Sail2_values_BitU_a) v)),
+
+ of_bools_method = (\<lambda> v. List.map
+ (of_bitU_method dict_Sail2_values_BitU_a) (List.map bitU_of_bool v)),
+
+ length_method = (\<lambda> xs. int (List.length xs)),
+
+ of_int_method = (\<lambda> len n. List.map
+ (of_bitU_method dict_Sail2_values_BitU_a) (bits_of_int len n)),
+
+ unsigned_method = (\<lambda> v. unsigned_of_bits (List.map
+ (to_bitU_method dict_Sail2_values_BitU_a) v)),
+
+ signed_method = (\<lambda> v. signed_of_bits (List.map
+ (to_bitU_method dict_Sail2_values_BitU_a) v)),
+
+ arith_op_bv_method = (\<lambda> op1 sign l r. List.map
+ (of_bitU_method dict_Sail2_values_BitU_a) (arith_op_bits op1 sign (List.map
+ (to_bitU_method dict_Sail2_values_BitU_a) l) (List.map (to_bitU_method dict_Sail2_values_BitU_a) r)))|) )"
+
+
+definition instance_Sail2_values_Bitvector_Machine_word_mword_dict :: "(('a::len)Word.word)Bitvector_class " where
+ " instance_Sail2_values_Bitvector_Machine_word_mword_dict = ((|
+
+ bits_of_method = (\<lambda> v. List.map bitU_of_bool (Word.to_bl v)),
+
+ of_bits_method = (\<lambda> v. map_option Word.of_bl (just_list (List.map bool_of_bitU v))),
+
+ of_bools_method = (\<lambda> v. Word.of_bl v),
+
+ length_method = (\<lambda> v. int (size v)),
+
+ of_int_method = ( \<lambda>x .
+ (case x of _ => \<lambda> n . Word.word_of_int n )),
+
+ unsigned_method = (\<lambda> v. Some (Word.uint v)),
+
+ signed_method = (\<lambda> v. Some (Word.sint v)),
+
+ arith_op_bv_method = (\<lambda> op1 sign l r. Word.word_of_int (op1 (int_of_mword sign l) (int_of_mword sign r)))|) )"
+
+
+definition access_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_bv_inc dict_Sail2_values_Bitvector_a v n = ( access_list True (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) n )"
+
+definition access_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where
+ " access_bv_dec dict_Sail2_values_Bitvector_a v n = ( access_list False (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) n )"
+
+
+definition update_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " update_bv_inc dict_Sail2_values_Bitvector_a v n b = ( update_list True (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) n b )"
+
+definition update_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where
+ " update_bv_dec dict_Sail2_values_Bitvector_a v n b = ( update_list False (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) n b )"
+
+
+definition subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " subrange_bv_inc dict_Sail2_values_Bitvector_a v i j = ( subrange_list True (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) i j )"
+
+definition subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where
+ " subrange_bv_dec dict_Sail2_values_Bitvector_a v i j = ( subrange_list False (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v) i j )"
+
+
+definition update_subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " update_subrange_bv_inc dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list True (
+ (bits_of_method dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method dict_Sail2_values_Bitvector_a) v'))"
+
+definition update_subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " update_subrange_bv_dec dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list False (
+ (bits_of_method dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method dict_Sail2_values_Bitvector_a) v'))"
+
+
+\<comment> \<open>\<open>val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU\<close>\<close>
+definition extz_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " extz_bv dict_Sail2_values_Bitvector_a n v = ( extz_bits n (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v))"
+
+
+\<comment> \<open>\<open>val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU\<close>\<close>
+definition exts_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where
+ " exts_bv dict_Sail2_values_Bitvector_a n v = ( exts_bits n (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v))"
+
+
+\<comment> \<open>\<open>val nat_of_bv : forall 'a. Bitvector 'a => 'a -> maybe nat\<close>\<close>
+definition nat_of_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(nat)option " where
+ " nat_of_bv dict_Sail2_values_Bitvector_a v = ( map_option nat_of_int (
+ (unsigned_method dict_Sail2_values_Bitvector_a) v))"
+
+
+\<comment> \<open>\<open>val string_of_bv : forall 'a. Bitvector 'a => 'a -> string\<close>\<close>
+definition string_of_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where
+ " string_of_bv dict_Sail2_values_Bitvector_a v = ( show_bitlist (
+ (bits_of_method dict_Sail2_values_Bitvector_a) v))"
+
+
+\<comment> \<open>\<open>val print_bits : forall 'a. Bitvector 'a => string -> 'a -> unit\<close>\<close>
+definition print_bits :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit " where
+ " print_bits dict_Sail2_values_Bitvector_a str v = ( print_endline (str @ string_of_bv
+ dict_Sail2_values_Bitvector_a v))"
+
+
+\<comment> \<open>\<open>val dec_str : integer -> string\<close>\<close>
+definition dec_str :: " int \<Rightarrow> string " where
+ " dec_str bv = ( Lem_string_extra.stringFromInteger bv )"
+
+
+\<comment> \<open>\<open>val concat_str : string -> string -> string\<close>\<close>
+definition concat_str :: " string \<Rightarrow> string \<Rightarrow> string " where
+ " concat_str str1 str2 = ( str1 @ str2 )"
+
+
+\<comment> \<open>\<open>val int_of_bit : bitU -> integer\<close>\<close>
+fun int_of_bit :: " bitU \<Rightarrow> int " where
+ " int_of_bit B0 = (( 0 :: int))"
+|" int_of_bit B1 = (( 1 :: int))"
+|" int_of_bit _ = ( failwith (''int_of_bit saw unknown''))"
+
+
+\<comment> \<open>\<open>val decimal_string_of_bv : forall 'a. Bitvector 'a => 'a -> string\<close>\<close>
+definition decimal_string_of_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where
+ " decimal_string_of_bv dict_Sail2_values_Bitvector_a bv = (
+ (let place_values =
+ (Lem_list.mapi
+ (\<lambda> i b . (int_of_bit b) * (( 2 :: int) ^ i))
+ (List.rev ((bits_of_method dict_Sail2_values_Bitvector_a) bv)))
+ in
+ (let sum1 = (List.foldl (+)(( 0 :: int)) place_values) in
+ Lem_string_extra.stringFromInteger sum1)))"
+
+
+\<comment> \<open>\<open>** Bytes and addresses \<close>\<close>
+
+type_synonym memory_byte =" bitU list "
+
+\<comment> \<open>\<open>val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))\<close>\<close>
+fun byte_chunks :: " 'a list \<Rightarrow>(('a list)list)option " where
+ " byte_chunks ([]) = ( Some [])"
+|" byte_chunks (a # b # c # d # e # f # g # h # rest) = (
+ Option.bind (byte_chunks rest) (\<lambda> rest . Some ([a,b,c,d,e,f,g,h] # rest)))"
+|" byte_chunks _ = ( None )"
+
+
+\<comment> \<open>\<open>val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)\<close>\<close>
+definition bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where
+ " bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( byte_chunks (
+ (bits_of_method dict_Sail2_values_Bitvector_a) bs))"
+
+
+\<comment> \<open>\<open>val bits_of_bytes : list memory_byte -> list bitU\<close>\<close>
+definition bits_of_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where
+ " bits_of_bytes bs = ( List.concat (List.map (\<lambda> v. List.map (\<lambda> b. b) v) bs))"
+
+
+definition mem_bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where
+ " mem_bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits
+ dict_Sail2_values_Bitvector_a bs))"
+
+definition bits_of_mem_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where
+ " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))"
+
+
+\<comment> \<open>\<open>val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+let bitv_of_byte_lifteds v =
+ foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+let bitv_of_bytes v =
+ foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+let byte_lifteds_of_bitv bits =
+ let bits = List.map bit_lifted_of_bitU bits in
+ byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+let bytes_of_bitv bits =
+ let bits = List.map bit_of_bitU bits in
+ bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+let address_lifted_of_bitv v =
+ let byte_lifteds = byte_lifteds_of_bitv v in
+ let maybe_address_integer =
+ match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+ | Just bs -> Just (integer_of_byte_list bs)
+ | _ -> Nothing
+ end in
+ Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+let address_of_bitv v =
+ let bytes = bytes_of_bitv v in
+ address_of_byte_list bytes\<close>\<close>
+
+function (sequential,domintros) reverse_endianness_list :: " 'a list \<Rightarrow> 'a list " where
+ " reverse_endianness_list bits = (
+ if List.length bits \<le>( 8 :: nat) then bits else
+ reverse_endianness_list (drop_list(( 8 :: int)) bits) @ take_list(( 8 :: int)) bits )"
+by pat_completeness auto
+
+
+
+\<comment> \<open>\<open>** Registers \<close>\<close>
+
+\<comment> \<open>\<open>type register_field = string
+type register_field_index = string * (integer * integer) \<open> name, start and end \<close>
+
+type register =
+ | Register of string * \<open> name \<close>
+ integer * \<open> length \<close>
+ integer * \<open> start index \<close>
+ bool * \<open> is increasing \<close>
+ list register_field_index
+ | UndefinedRegister of integer \<open> length \<close>
+ | RegisterPair of register * register\<close>\<close>
+
+record( 'regstate, 'regval, 'a) register_ref =
+
+ name ::" string "
+
+ \<comment> \<open>\<open>is_inc : bool;\<close>\<close>
+ read_from ::" 'regstate \<Rightarrow> 'a "
+
+ write_to ::" 'a \<Rightarrow> 'regstate \<Rightarrow> 'regstate "
+
+ of_regval ::" 'regval \<Rightarrow> 'a option "
+
+ regval_of ::" 'a \<Rightarrow> 'regval "
+
+
+\<comment> \<open>\<open> Register accessors: pair of functions for reading and writing register values \<close>\<close>
+type_synonym( 'regstate, 'regval) register_accessors ="
+ ((string \<Rightarrow> 'regstate \<Rightarrow> 'regval option) *
+ (string \<Rightarrow> 'regval \<Rightarrow> 'regstate \<Rightarrow> 'regstate option))"
+
+record( 'regtype, 'a) field_ref =
+
+ field_name ::" string "
+
+ field_start ::" int "
+
+ field_is_inc ::" bool "
+
+ get_field ::" 'regtype \<Rightarrow> 'a "
+
+ set_field ::" 'regtype \<Rightarrow> 'a \<Rightarrow> 'regtype "
+
+
+\<comment> \<open>\<open>let name_of_reg = function
+ | Register name _ _ _ _ -> name
+ | UndefinedRegister _ -> failwith "name_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "name_of_reg RegisterPair"
+end
+
+let size_of_reg = function
+ | Register _ size _ _ _ -> size
+ | UndefinedRegister size -> size
+ | RegisterPair _ _ -> failwith "size_of_reg RegisterPair"
+end
+
+let start_of_reg = function
+ | Register _ _ start _ _ -> start
+ | UndefinedRegister _ -> failwith "start_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "start_of_reg RegisterPair"
+end
+
+let is_inc_of_reg = function
+ | Register _ _ _ is_inc _ -> is_inc
+ | UndefinedRegister _ -> failwith "is_inc_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "in_inc_of_reg RegisterPair"
+end
+
+let dir_of_reg = function
+ | Register _ _ _ is_inc _ -> dir_of_bool is_inc
+ | UndefinedRegister _ -> failwith "dir_of_reg UndefinedRegister"
+ | RegisterPair _ _ -> failwith "dir_of_reg RegisterPair"
+end
+
+let size_of_reg_nat reg = natFromInteger (size_of_reg reg)
+let start_of_reg_nat reg = natFromInteger (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> maybe (integer * integer)
+let rec register_field_indices_aux register rfield =
+ match register with
+ | Register _ _ _ _ rfields -> List.lookup rfield rfields
+ | RegisterPair r1 r2 ->
+ let m_indices = register_field_indices_aux r1 rfield in
+ if isJust m_indices then m_indices else register_field_indices_aux r2 rfield
+ | UndefinedRegister _ -> Nothing
+ end
+
+val register_field_indices : register -> register_field -> integer * integer
+let register_field_indices register rfield =
+ match register_field_indices_aux register rfield with
+ | Just indices -> indices
+ | Nothing -> failwith "Invalid register/register-field combination"
+ end
+
+let register_field_indices_nat reg regfield=
+ let (i,j) = register_field_indices reg regfield in
+ (natFromInteger i,natFromInteger j)\<close>\<close>
+
+\<comment> \<open>\<open>let rec external_reg_value reg_name v =
+ let (internal_start, external_start, direction) =
+ match reg_name with
+ | Reg _ start size dir ->
+ (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+ | Reg_slice _ reg_start dir (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_field _ reg_start dir _ (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ | Reg_f_slice _ reg_start dir _ _ (slice_start, _) ->
+ ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+ slice_start, dir)
+ end in
+ let bits = bit_lifteds_of_bitv v in
+ <| rv_bits = bits;
+ rv_dir = direction;
+ rv_start = external_start;
+ rv_start_internal = internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+let internal_reg_value v =
+ List.map bitU_of_bit_lifted v.rv_bits
+ \<open>(integerFromNat v.rv_start_internal)
+ (v.rv_dir = D_increasing)\<close>
+
+
+let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) =
+ match d with
+ \<open>This is the case the thread/concurrecny model expects, so no change needed\<close>
+ | D_increasing -> (i,j)
+ | D_decreasing -> let slice_i = start - i in
+ let slice_j = (i - j) + slice_i in
+ (slice_i,slice_j)
+ end \<close>\<close>
+
+\<comment> \<open>\<open> TODO
+let external_reg_whole r =
+ Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc)
+
+let external_reg_slice r (i,j) =
+ let start = natFromInteger r.start in
+ let dir = dir_of_bool r.is_inc in
+ Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+let external_reg_field_whole reg rfield =
+ let (m,n) = register_field_indices_nat reg rfield in
+ let start = start_of_reg_nat reg in
+ let dir = dir_of_reg reg in
+ Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+let external_reg_field_slice reg rfield (i,j) =
+ let (m,n) = register_field_indices_nat reg rfield in
+ let start = start_of_reg_nat reg in
+ let dir = dir_of_reg reg in
+ Reg_f_slice (name_of_reg reg) start dir rfield
+ (external_slice dir start (m,n))
+ (external_slice dir start (i,j))\<close>\<close>
+
+\<comment> \<open>\<open>val external_mem_value : list bitU -> memory_value
+let external_mem_value v =
+ byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+let internal_mem_value bytes =
+ List.reverse bytes $> bitv_of_byte_lifteds\<close>\<close>
+
+
+\<comment> \<open>\<open>val foreach : forall 'a 'vars.
+ (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars\<close>\<close>
+fun foreach :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where
+ " foreach ([]) vars body = ( vars )"
+|" foreach (x # xs) vars body = ( foreach xs (body x vars) body )"
+
+
+\<comment> \<open>\<open>val index_list : integer -> integer -> integer -> list integer\<close>\<close>
+function (sequential,domintros) index_list :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)list " where
+ " index_list from1 to1 step = (
+ if ((step >( 0 :: int)) \<and> (from1 \<le> to1)) \<or> ((step <( 0 :: int)) \<and> (to1 \<le> from1)) then
+ from1 # index_list (from1 + step) to1 step
+ else [])"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars\<close>\<close>
+function (sequential,domintros) while :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where
+ " while vars cond body = (
+ if cond vars then while (body vars) cond body else vars )"
+by pat_completeness auto
+
+
+\<comment> \<open>\<open>val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars\<close>\<close>
+function (sequential,domintros) until :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where
+ " until vars cond body = (
+ (let vars = (body vars) in
+ if cond vars then vars else until (body vars) cond body))"
+by pat_completeness auto
+
+
+
+\<comment> \<open>\<open> convert numbers unsafely to naturals \<close>\<close>
+
+record 'a ToNatural_class=
+ toNatural_method ::" 'a \<Rightarrow> nat "
+
+\<comment> \<open>\<open> eta-expanded for Isabelle output, otherwise it breaks \<close>\<close>
+definition instance_Sail2_values_ToNatural_Num_integer_dict :: "(int)ToNatural_class " where
+ " instance_Sail2_values_ToNatural_Num_integer_dict = ((|
+
+ toNatural_method = (\<lambda> n . nat (abs n))|) )"
+
+definition instance_Sail2_values_ToNatural_Num_int_dict :: "(int)ToNatural_class " where
+ " instance_Sail2_values_ToNatural_Num_int_dict = ((|
+
+ toNatural_method = (\<lambda> n . (nat (abs n)))|) )"
+
+definition instance_Sail2_values_ToNatural_nat_dict :: "(nat)ToNatural_class " where
+ " instance_Sail2_values_ToNatural_nat_dict = ((|
+
+ toNatural_method = (\<lambda> n . n)|) )"
+
+definition instance_Sail2_values_ToNatural_Num_natural_dict :: "(nat)ToNatural_class " where
+ " instance_Sail2_values_ToNatural_Num_natural_dict = ((|
+
+ toNatural_method = (\<lambda> n . n)|) )"
+
+
+fun toNaturalFiveTup :: " 'a ToNatural_class \<Rightarrow> 'b ToNatural_class \<Rightarrow> 'c ToNatural_class \<Rightarrow> 'd ToNatural_class \<Rightarrow> 'e ToNatural_class \<Rightarrow> 'd*'c*'b*'a*'e \<Rightarrow> nat*nat*nat*nat*nat " where
+ " toNaturalFiveTup dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5) = (
+ ((toNatural_method dict_Sail2_values_ToNatural_d) n1,(toNatural_method dict_Sail2_values_ToNatural_c) n2,(toNatural_method dict_Sail2_values_ToNatural_b) n3,(toNatural_method dict_Sail2_values_ToNatural_a) n4,(toNatural_method dict_Sail2_values_ToNatural_e) n5))"
+
+
+\<comment> \<open>\<open> Let the following types be generated by Sail per spec, using either bitlists
+ or machine words as bitvector representation \<close>\<close>
+\<comment> \<open>\<open>type regfp =
+ | RFull of (string)
+ | RSlice of (string * integer * integer)
+ | RSliceBit of (string * integer)
+ | RField of (string * string)
+
+type niafp =
+ | NIAFP_successor
+ | NIAFP_concrete_address of vector bitU
+ | NIAFP_indirect_address
+
+\<open> only for MIPS \<close>
+type diafp =
+ | DIAFP_none
+ | DIAFP_concrete of vector bitU
+ | DIAFP_reg of regfp
+
+let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function
+ | RFull name ->
+ let (start,length,direction,_) = reg_info name Nothing in
+ Reg name start length direction
+ | RSlice (name,i,j) ->
+ let i = natFromInteger i in
+ let j = natFromInteger j in
+ let (start,length,direction,_) = reg_info name Nothing in
+ let slice = external_slice direction start (i,j) in
+ Reg_slice name start direction slice
+ | RSliceBit (name,i) ->
+ let i = natFromInteger i in
+ let (start,length,direction,_) = reg_info name Nothing in
+ let slice = external_slice direction start (i,i) in
+ Reg_slice name start direction slice
+ | RField (name,field_name) ->
+ let (start,length,direction,span) = reg_info name (Just field_name) in
+ let slice = external_slice direction start span in
+ Reg_field name start direction field_name slice
+end
+
+let niafp_to_nia reginfo = function
+ | NIAFP_successor -> NIA_successor
+ | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v)
+ | NIAFP_indirect_address -> NIA_indirect_address
+end
+
+let diafp_to_dia reginfo = function
+ | DIAFP_none -> DIA_none
+ | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v)
+ | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r)
+end
+\<close>\<close>
+end
diff --git a/prover_snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy b/prover_snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy
new file mode 100644
index 0000000..27a6952
--- /dev/null
+++ b/prover_snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy
@@ -0,0 +1,368 @@
+theory Sail2_values_lemmas
+ imports Sail2_values
+begin
+
+lemma while_domI:
+ fixes V :: "'vars \<Rightarrow> nat"
+ assumes "\<And>vars. cond vars \<Longrightarrow> V (body vars) < V vars"
+ shows "while_dom (vars, cond, body)"
+ by (induction vars rule: measure_induct_rule[where f = V])
+ (use assms in \<open>auto intro: while.domintros\<close>)
+
+lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def)
+
+termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def)
+declare reverse_endianness_list.simps[simp del]
+declare take_list_def[simp]
+declare drop_list_def[simp]
+
+function take_chunks :: "nat \<Rightarrow> 'a list \<Rightarrow> 'a list list" where
+ "take_chunks n [] = []"
+| "take_chunks 0 xs = []"
+| "take_chunks n xs = take n xs # take_chunks n (drop n xs)" if "n > 0" and "xs \<noteq> []"
+ by auto blast
+termination by lexicographic_order
+
+lemma take_chunks_length_leq_n: "length xs \<le> n \<Longrightarrow> xs \<noteq> [] \<Longrightarrow> take_chunks n xs = [xs]"
+ by (cases n) auto
+
+lemma take_chunks_append: "n dvd length a \<Longrightarrow> take_chunks n (a @ b) = take_chunks n a @ take_chunks n b"
+ by (induction n a rule: take_chunks.induct) (auto simp: dvd_imp_le)
+
+lemma Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x"
+ by auto
+
+lemma byte_chunks_take_chunks_8:
+ assumes "8 dvd length xs"
+ shows "byte_chunks xs = Some (take_chunks 8 xs)"
+proof -
+ have Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x" for x
+ by auto
+ from assms show ?thesis
+ by (induction xs rule: byte_chunks.induct) (auto simp: Suc8_plus8 nat_dvd_not_less)
+qed
+
+lemma reverse_endianness_list_rev_take_chunks:
+ "reverse_endianness_list bits = List.concat (rev (take_chunks 8 bits))"
+ by (induction "8 :: nat" bits rule: take_chunks.induct)
+ (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_simps:
+ "length bits \<le> 8 \<Longrightarrow> reverse_endianness_list bits = bits"
+ "length bits > 8 \<Longrightarrow> reverse_endianness_list bits = reverse_endianness_list (drop 8 bits) @ take 8 bits"
+ by (cases bits; auto simp: reverse_endianness_list_rev_take_chunks)+
+
+lemma reverse_endianness_list_append:
+ assumes "8 dvd length a"
+ shows "reverse_endianness_list (a @ b) = reverse_endianness_list b @ reverse_endianness_list a"
+ using assms by (auto simp: reverse_endianness_list_rev_take_chunks take_chunks_append)
+
+lemma length_reverse_endianness_list[simp]:
+ "length (reverse_endianness_list l) = length l"
+ by (induction l rule: reverse_endianness_list.induct) (auto simp: reverse_endianness_list.simps)
+
+lemma reverse_endianness_list_take_8[simp]:
+ "reverse_endianness_list (take 8 bits) = take 8 bits"
+ by (auto simp: reverse_endianness_list_simps)
+
+lemma reverse_reverse_endianness_list[simp]:
+ assumes "8 dvd length l"
+ shows "reverse_endianness_list (reverse_endianness_list l) = l"
+proof (use assms in \<open>induction l rule: reverse_endianness_list.induct[case_names Step]\<close>)
+ case (Step bits)
+ then show ?case
+ by (auto simp: reverse_endianness_list.simps[of bits] reverse_endianness_list_append)
+qed
+
+declare repeat.simps[simp del]
+
+lemma length_repeat[simp]: "length (repeat xs n) = nat n * length xs"
+proof (induction xs n rule: repeat.induct[case_names Step])
+ case (Step xs n)
+ then show ?case unfolding repeat.simps[of xs n]
+ by (auto simp del: mult_Suc simp: mult_Suc[symmetric])
+qed
+
+lemma nth_repeat:
+ assumes "i < nat n * length xs"
+ shows "repeat xs n ! i = xs ! (i mod length xs)"
+proof (use assms in \<open>induction xs n arbitrary: i rule: repeat.induct[case_names Step]\<close>)
+ case (Step xs n i)
+ show ?case
+ using Step.prems Step.IH[of "i - length xs"]
+ unfolding repeat.simps[of xs n]
+ by (auto simp: nth_append mod_geq[symmetric] nat_diff_distrib diff_mult_distrib)
+qed
+
+termination index_list
+ by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto
+
+lemma index_list_Zero[simp]: "index_list i j 0 = []"
+ by auto
+
+lemma index_list_singleton[simp]: "n \<noteq> 0 \<Longrightarrow> index_list i i n = [i]"
+ by auto
+
+lemma index_list_simps:
+ "0 < step \<Longrightarrow> from \<le> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+ "0 < step \<Longrightarrow> from > to \<Longrightarrow> index_list from to step = []"
+ "0 > step \<Longrightarrow> from \<ge> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step"
+ "0 > step \<Longrightarrow> from < to \<Longrightarrow> index_list from to step = []"
+ by auto
+
+lemma index_list_step1_upto[simp]: "index_list i j 1 = [i..j]"
+ by (induction i j "1 :: int" rule: index_list.induct)
+ (auto simp: index_list_simps upto.simps)
+
+lemma length_upto[simp]: "i \<le> j \<Longrightarrow> length [i..j] = nat (j - i + 1)"
+ by (induction i j rule: upto.induct) (auto simp: upto.simps)
+
+lemma nth_upto[simp]: "i + int n \<le> j \<Longrightarrow> [i..j] ! n = i + int n"
+ by (induction i j arbitrary: n rule: upto.induct)
+ (auto simp: upto.simps nth_Cons split: nat.splits)
+
+declare index_list.simps[simp del]
+
+lemma genlist_add_upt[simp]: "genlist ((+) start) len = [start..<start + len]"
+ by (auto simp: genlist_def map_add_upt add.commute cong: map_cong)
+
+lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto
+
+lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs"
+ by (induction xs) (auto split: option.splits)
+
+lemma just_list_None_member_None: "None \<in> set xs \<Longrightarrow> just_list xs = None"
+ by auto
+
+lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys"
+ by (induction xs arbitrary: ys) (auto split: option.splits)
+
+lemma just_list_cases:
+ assumes "just_list xs = y"
+ obtains (None) "None \<in> set xs" and "y = None"
+ | (Some) ys where "xs = map Some ys" and "y = Some ys"
+ using assms by (cases y) auto
+
+lemma repeat_singleton_replicate[simp]:
+ "repeat [x] n = replicate (nat n) x"
+proof (induction n)
+ case (nonneg n)
+ have "nat (1 + int m) = Suc m" for m by auto
+ then show ?case by (induction n) (auto simp: repeat.simps)
+next
+ case (neg n)
+ then show ?case by (auto simp: repeat.simps)
+qed
+
+lemma and_bit_B1[simp]: "and_bit B1 b = b"
+ by (cases b) auto
+
+lemma and_bit_idem[simp]: "and_bit b b = b"
+ by (cases b) auto
+
+lemma and_bit_eq_iff:
+ "and_bit b b' = B0 \<longleftrightarrow> (b = B0 \<or> b' = B0)"
+ "and_bit b b' = BU \<longleftrightarrow> (b = BU \<or> b' = BU) \<and> b \<noteq> B0 \<and> b' \<noteq> B0"
+ "and_bit b b' = B1 \<longleftrightarrow> (b = B1 \<and> b' = B1)"
+ by (cases b; cases b'; auto)+
+
+lemma foldl_and_bit_eq_iff:
+ shows "foldl and_bit b bs = B0 \<longleftrightarrow> (b = B0 \<or> B0 \<in> set bs)" (is ?B0)
+ and "foldl and_bit b bs = B1 \<longleftrightarrow> (b = B1 \<and> set bs \<subseteq> {B1})" (is ?B1)
+ and "foldl and_bit b bs = BU \<longleftrightarrow> (b = BU \<or> BU \<in> set bs) \<and> b \<noteq> B0 \<and> B0 \<notin> set bs" (is ?BU)
+proof -
+ have "?B0 \<and> ?B1 \<and> ?BU"
+ proof (induction bs arbitrary: b)
+ case (Cons b' bs)
+ show ?case using Cons.IH by (cases b; cases b') auto
+ qed auto
+ then show ?B0 and ?B1 and ?BU by auto
+qed
+
+lemma bool_of_bitU_simps[simp]:
+ "bool_of_bitU B0 = Some False"
+ "bool_of_bitU B1 = Some True"
+ "bool_of_bitU BU = None"
+ by (auto simp: bool_of_bitU_def)
+
+lemma bitops_bitU_of_bool[simp]:
+ "and_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<and> y)"
+ "or_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<or> y)"
+ "xor_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool ((x \<or> y) \<and> \<not>(x \<and> y))"
+ "not_bit (bitU_of_bool x) = bitU_of_bool (\<not>x)"
+ "not_bit \<circ> bitU_of_bool = bitU_of_bool \<circ> Not"
+ by (auto simp: bitU_of_bool_def not_bit_def)
+
+lemma image_bitU_of_bool_B0_B1: "bitU_of_bool ` bs \<subseteq> {B0, B1}"
+ by (auto simp: bitU_of_bool_def split: if_splits)
+
+lemma bool_of_bitU_bitU_of_bool[simp]:
+ "bool_of_bitU \<circ> bitU_of_bool = Some"
+ "bool_of_bitU \<circ> (bitU_of_bool \<circ> f) = Some \<circ> f"
+ "bool_of_bitU (bitU_of_bool x) = Some x"
+ by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+
+
+abbreviation "BC_bitU_list \<equiv> instance_Sail2_values_Bitvector_list_dict instance_Sail2_values_BitU_Sail2_values_bitU_dict"
+lemmas BC_bitU_list_def = instance_Sail2_values_Bitvector_list_dict_def instance_Sail2_values_BitU_Sail2_values_bitU_dict_def
+abbreviation "BC_mword \<equiv> instance_Sail2_values_Bitvector_Machine_word_mword_dict"
+lemmas BC_mword_defs = instance_Sail2_values_Bitvector_Machine_word_mword_dict_def
+ access_mword_def access_mword_inc_def access_mword_dec_def
+ (*update_mword_def update_mword_inc_def update_mword_dec_def*)
+ subrange_list_def subrange_list_inc_def subrange_list_dec_def
+ update_subrange_list_def update_subrange_list_inc_def update_subrange_list_dec_def
+
+declare size_itself_int_def[simp]
+declare size_itself_def[simp]
+declare word_size[simp]
+
+lemma int_of_mword_simps[simp]:
+ "int_of_mword False w = uint w"
+ "int_of_mword True w = sint w"
+ "int_of_bv BC_mword False w = Some (uint w)"
+ "int_of_bv BC_mword True w = Some (sint w)"
+ by (auto simp: int_of_mword_def int_of_bv_def BC_mword_defs)
+
+lemma BC_mword_simps[simp]:
+ "unsigned_method BC_mword a = Some (uint a)"
+ "signed_method BC_mword a = Some (sint a)"
+ "length_method BC_mword (a :: ('a :: len) word) = int (LENGTH('a))"
+ by (auto simp: BC_mword_defs)
+
+lemma of_bits_mword_of_bl[simp]:
+ assumes "just_list (map bool_of_bitU bus) = Some bs"
+ shows "of_bits_method BC_mword bus = Some (of_bl bs)"
+ and "of_bits_failwith BC_mword bus = of_bl bs"
+ using assms by (auto simp: BC_mword_defs of_bits_failwith_def maybe_failwith_def)
+
+lemma nat_of_bits_aux_bl_to_bin_aux:
+ "nat_of_bools_aux acc bs = nat (bl_to_bin_aux bs (int acc))"
+ by (induction acc bs rule: nat_of_bools_aux.induct)
+ (auto simp: Bit_def intro!: arg_cong[where f = nat] arg_cong2[where f = bl_to_bin_aux] split: if_splits)
+
+lemma nat_of_bits_bl_to_bin[simp]:
+ "nat_of_bools bs = nat (bl_to_bin bs)"
+ by (auto simp: nat_of_bools_def bl_to_bin_def nat_of_bits_aux_bl_to_bin_aux)
+
+lemma unsigned_bits_of_mword[simp]:
+ "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)"
+ by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def)
+
+definition mem_bytes_of_word :: "'a::len word \<Rightarrow> bitU list list" where
+ "mem_bytes_of_word w = rev (take_chunks 8 (map bitU_of_bool (to_bl w)))"
+
+lemma mem_bytes_of_bits_mem_bytes_of_word[simp]:
+ assumes "8 dvd LENGTH('a)"
+ shows "mem_bytes_of_bits BC_mword (w :: 'a::len word) = Some (mem_bytes_of_word w)"
+ using assms
+ by (auto simp: mem_bytes_of_bits_def bytes_of_bits_def BC_mword_defs byte_chunks_take_chunks_8 mem_bytes_of_word_def)
+
+lemma bits_of_bitU_list[simp]:
+ "bits_of_method BC_bitU_list v = v"
+ "of_bits_method BC_bitU_list v = Some v"
+ by (auto simp: BC_bitU_list_def)
+
+lemma subrange_list_inc_drop_take:
+ "subrange_list_inc xs i j = drop (nat i) (take (nat (j + 1)) xs)"
+ by (auto simp: subrange_list_inc_def split_at_def)
+
+lemma subrange_list_dec_drop_take:
+ assumes "i \<ge> 0" and "j \<ge> 0"
+ shows "subrange_list_dec xs i j = drop (length xs - nat (i + 1)) (take (length xs - nat j) xs)"
+ using assms unfolding subrange_list_dec_def
+ by (auto simp: subrange_list_inc_drop_take add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_subrange_list_inc_drop_take:
+ assumes "i \<ge> 0" and "j \<ge> i"
+ shows "update_subrange_list_inc xs i j xs' = take (nat i) xs @ xs' @ drop (nat (j + 1)) xs"
+ using assms unfolding update_subrange_list_inc_def
+ by (auto simp: split_at_def min_def)
+
+lemma update_subrange_list_dec_drop_take:
+ assumes "j \<ge> 0" and "i \<ge> j"
+ shows "update_subrange_list_dec xs i j xs' = take (length xs - nat (i + 1)) xs @ xs' @ drop (length xs - nat j) xs"
+ using assms unfolding update_subrange_list_dec_def update_subrange_list_inc_def
+ by (auto simp: split_at_def min_def Let_def add.commute diff_diff_add nat_minus_as_int)
+
+declare access_list_inc_def[simp]
+
+lemma access_list_dec_rev_nth:
+ assumes "0 \<le> i" and "nat i < length xs"
+ shows "access_list_dec xs i = rev xs ! (nat i)"
+ using assms
+ by (auto simp: access_list_dec_def rev_nth intro!: arg_cong2[where f = List.nth])
+
+lemma access_bv_dec_mword[simp]:
+ fixes w :: "('a::len) word"
+ assumes "0 \<le> n" and "nat n < LENGTH('a)"
+ shows "access_bv_dec BC_mword w n = bitU_of_bool (w !! (nat n))"
+ using assms unfolding access_bv_dec_def access_list_def
+ by (auto simp: access_list_dec_rev_nth BC_mword_defs rev_map test_bit_bl)
+
+lemma access_list_dec_nth[simp]:
+ assumes "0 \<le> i"
+ shows "access_list_dec xs i = xs ! (length xs - nat (i + 1))"
+ using assms
+ by (auto simp: access_list_dec_def add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_list_inc_update[simp]:
+ "update_list_inc xs n x = xs[nat n := x]"
+ by (auto simp: update_list_inc_def)
+
+lemma update_list_dec_update[simp]:
+ "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]"
+ by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int)
+
+lemma update_list_dec_update_rev:
+ "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> update_list_dec xs n x = rev ((rev xs)[nat n := x])"
+ by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int rev_update)
+
+lemma access_list_dec_update_list_dec[simp]:
+ "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> access_list_dec (update_list_dec xs n x) n = x"
+ by (auto simp: access_list_dec_rev_nth update_list_dec_update_rev)
+
+lemma bools_of_nat_aux_simps[simp]:
+ "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc"
+ "\<And>len. bools_of_nat_aux (int (Suc len)) x acc =
+ bools_of_nat_aux (int len) (x div 2) ((if x mod 2 = 1 then True else False) # acc)"
+ by auto
+declare bools_of_nat_aux.simps[simp del]
+
+lemma bools_of_nat_aux_bin_to_bl_aux:
+ "bools_of_nat_aux len n acc = bin_to_bl_aux (nat len) (int n) acc"
+proof (cases len)
+ case (nonneg len')
+ show ?thesis unfolding nonneg
+ proof (induction len' arbitrary: n acc)
+ case (Suc len'' n acc)
+ then show ?case
+ using zmod_int[of n 2]
+ by (auto simp del: of_nat_simps simp add: bin_rest_def bin_last_def zdiv_int)
+ qed auto
+qed auto
+
+lemma bools_of_nat_bin_to_bl[simp]:
+ "bools_of_nat len n = bin_to_bl (nat len) (int n)"
+ by (auto simp: bools_of_nat_def bools_of_nat_aux_bin_to_bl_aux)
+
+lemma add_one_bool_ignore_overflow_aux_rbl_succ[simp]:
+ "add_one_bool_ignore_overflow_aux xs = rbl_succ xs"
+ by (induction xs) auto
+
+lemma add_one_bool_ignore_overflow_rbl_succ[simp]:
+ "add_one_bool_ignore_overflow xs = rev (rbl_succ (rev xs))"
+ unfolding add_one_bool_ignore_overflow_def by auto
+
+lemma map_Not_bin_to_bl:
+ "map Not (bin_to_bl_aux len n acc) = bin_to_bl_aux len (-n - 1) (map Not acc)"
+proof (induction len arbitrary: n acc)
+ case (Suc len n acc)
+ moreover have "(- (n div 2) - 1) = ((-n - 1) div 2)" by auto
+ moreover have "(n mod 2 = 0) = ((- n - 1) mod 2 = 1)" by presburger
+ ultimately show ?case by (auto simp: bin_rest_def bin_last_def)
+qed auto
+
+lemma bools_of_int_bin_to_bl[simp]:
+ "bools_of_int len n = bin_to_bl (nat len) n"
+ by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def])
+
+end
diff --git a/sail-riscv.install b/sail-riscv.install
new file mode 100644
index 0000000..ce50f55
--- /dev/null
+++ b/sail-riscv.install
@@ -0,0 +1,2 @@
+bin: ["c_emulator/riscv_sim_RV64" "c_emulator/riscv_sim_RV32"]
+share: [ "model/riscv_insts_mext.sail" {"model/riscv_insts_mext.sail"} "model/riscv_insts_cext.sail" {"model/riscv_insts_cext.sail"} "model/riscv_csr_map.sail" {"model/riscv_csr_map.sail"} "model/riscv_addr_checks.sail" {"model/riscv_addr_checks.sail"} "model/riscv_sys_exceptions.sail" {"model/riscv_sys_exceptions.sail"} "model/riscv_vmem_sv32.sail" {"model/riscv_vmem_sv32.sail"} "model/riscv_types.sail" {"model/riscv_types.sail"} "model/riscv_addr_checks_common.sail" {"model/riscv_addr_checks_common.sail"} "model/riscv_step.sail" {"model/riscv_step.sail"} "model/riscv_step_rvfi.sail" {"model/riscv_step_rvfi.sail"} "model/riscv_step_common.sail" {"model/riscv_step_common.sail"} "model/riscv_platform.sail" {"model/riscv_platform.sail"} "model/riscv_insts_next.sail" {"model/riscv_insts_next.sail"} "model/riscv_sys_control.sail" {"model/riscv_sys_control.sail"} "model/riscv_insts_begin.sail" {"model/riscv_insts_begin.sail"} "model/riscv_vmem_sv48.sail" {"model/riscv_vmem_sv48.sail"} "model/riscv_csr_ext.sail" {"model/riscv_csr_ext.sail"} "model/riscv_regs.sail" {"model/riscv_regs.sail"} "model/riscv_fetch.sail" {"model/riscv_fetch.sail"} "model/riscv_step_ext.sail" {"model/riscv_step_ext.sail"} "model/riscv_fetch_rvfi.sail" {"model/riscv_fetch_rvfi.sail"} "model/riscv_termination_rv32.sail" {"model/riscv_termination_rv32.sail"} "model/riscv_jalr_rmem.sail" {"model/riscv_jalr_rmem.sail"} "model/riscv_vmem_common.sail" {"model/riscv_vmem_common.sail"} "model/riscv_decode_ext.sail" {"model/riscv_decode_ext.sail"} "model/riscv_next_regs.sail" {"model/riscv_next_regs.sail"} "model/riscv_xlen64.sail" {"model/riscv_xlen64.sail"} "model/riscv_insts_zicsr.sail" {"model/riscv_insts_zicsr.sail"} "model/riscv_pc_access.sail" {"model/riscv_pc_access.sail"} "model/riscv_insts_rmem.sail" {"model/riscv_insts_rmem.sail"} "model/prelude_mapping.sail" {"model/prelude_mapping.sail"} "model/riscv_vmem_rv32.sail" {"model/riscv_vmem_rv32.sail"} "model/riscv_insts_end.sail" {"model/riscv_insts_end.sail"} "model/riscv_ext_regs.sail" {"model/riscv_ext_regs.sail"} "model/rvfi_dii.sail" {"model/rvfi_dii.sail"} "model/prelude_mem.sail" {"model/prelude_mem.sail"} "model/riscv_duopod.sail" {"model/riscv_duopod.sail"} "model/riscv_sync_exception.sail" {"model/riscv_sync_exception.sail"} "model/riscv_vmem_sv39.sail" {"model/riscv_vmem_sv39.sail"} "model/riscv_next_control.sail" {"model/riscv_next_control.sail"} "model/riscv_vmem_rv64.sail" {"model/riscv_vmem_rv64.sail"} "model/riscv_analysis.sail" {"model/riscv_analysis.sail"} "model/main.sail" {"model/main.sail"} "model/riscv_vmem_tlb.sail" {"model/riscv_vmem_tlb.sail"} "model/riscv_sys_regs.sail" {"model/riscv_sys_regs.sail"} "model/riscv_termination_rv64.sail" {"model/riscv_termination_rv64.sail"} "model/prelude_mem_metadata.sail" {"model/prelude_mem_metadata.sail"} "model/prelude.sail" {"model/prelude.sail"} "model/riscv_xlen32.sail" {"model/riscv_xlen32.sail"} "model/riscv_termination_common.sail" {"model/riscv_termination_common.sail"} "model/riscv_insts_base.sail" {"model/riscv_insts_base.sail"} "model/riscv_jalr_seq.sail" {"model/riscv_jalr_seq.sail"} "model/riscv_reg_type.sail" {"model/riscv_reg_type.sail"} "model/riscv_mem.sail" {"model/riscv_mem.sail"} "model/riscv_insts_aext.sail" {"model/riscv_insts_aext.sail"} "c_emulator/riscv_platform.c" {"c_emulator/riscv_platform.c"} "c_emulator/riscv_sim.c" {"c_emulator/riscv_sim.c"} "c_emulator/riscv_platform_impl.c" {"c_emulator/riscv_platform_impl.c"} "c_emulator/riscv_prelude.c" {"c_emulator/riscv_prelude.c"} "c_emulator/riscv_platform_impl.h" {"c_emulator/riscv_platform_impl.h"} "c_emulator/riscv_prelude.h" {"c_emulator/riscv_prelude.h"} "c_emulator/riscv_sail.h" {"c_emulator/riscv_sail.h"} "c_emulator/riscv_platform.h" {"c_emulator/riscv_platform.h"} "c_emulator/riscv_config.h" {"c_emulator/riscv_config.h"} ]
diff --git a/test/get_perf.py b/test/get_perf.py
index c3e94cf..1570cac 100755
--- a/test/get_perf.py
+++ b/test/get_perf.py
@@ -24,14 +24,14 @@ def test_perf(d, test_pat, test_type):
total_insts += insts
total_msecs += msecs
- Kips = total_insts/total_msecs
+ Kips = total_insts/total_msecs if total_msecs != 0 else float("nan")
print("Average {0} performance: {1} Kips".format(test_type, Kips))
def get_test_pat(iset, emode):
return "rv64{0}-{1}-*.cout".format(iset, emode)
if __name__ == '__main__':
- test_dir = os.path.join(os.path.dirname(__file__), "tests")
+ test_dir = os.path.join(os.path.dirname(__file__), "riscv-tests")
for mode in ["p", "v"]:
test_perf(test_dir, get_test_pat("ui", mode), "ui-{0}".format(mode))
test_perf(test_dir, get_test_pat("um", mode), "um-{0}".format(mode))